A d v a nced C onv ersion T ech nolog ies
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CRC Press
Taylor & Francis Group
Boca Raton London New York
CRC Press is an imprint of the
Taylor &Francis Group, an Informa business
Fang Lin Luo
Hong Ye
Power Electronics
A d v a nced C onv ersion T ech nolog ies
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Library of Congress CataloginginPublication Data
Luo, Fang Lin.
Power electronics : advanced conversion technologies / authors, Fang Lin Luo, Hong Ye.
p. cm.
Includes bibliographical references and index.
ISBN 9781420094299 (hardcover : alk. paper)
1. Power electronics. I. Ye, Hong, 1973 II. Title.
TK7881.15.L86 2010
621.31’7dc22 2009043846
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Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Authors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Symbols and Factors Used in This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Symbols Used in Power Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Factors and Symbols Used in AC Power Systems . . . . . . . . . . . . . . 4
1.1.3 Factors and Symbols Used in DC Power Systems . . . . . . . . . . . . . . 7
1.1.4 Factors and Symbols Used in Switching Power Systems . . . . . . . . . 8
1.1.5 Other Factors and Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.5.1 Very Small Damping Time Constant . . . . . . . . . . . . . . . . . 11
1.1.5.2 Small Damping Time Constant . . . . . . . . . . . . . . . . . . . . . 11
1.1.5.3 Critical Damping Time Constant . . . . . . . . . . . . . . . . . . . 12
1.1.5.4 Large Damping Time Constant . . . . . . . . . . . . . . . . . . . . . 13
1.1.6 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1.6.1 Central Symmetrical Periodical Function . . . . . . . . . . . . . 15
1.1.6.2 Axial (Mirror) Symmetrical Periodical Function . . . . . . . . 16
1.1.6.3 Nonperiodical Function . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.6.4 Useful Formulae and Data . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.6.5 Examples of FFT Applications . . . . . . . . . . . . . . . . . . . . . 17
1.2 AC/DC Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2.1 Historic Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2.2 Updated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.3 Power Factor Correction Methods . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 DC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.1 Updated Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.2 New Concepts and Mathematical Modeling . . . . . . . . . . . . . . . . . . 24
1.3.3 Power Rate Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4 DC/AC Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4.1 Sorting Existing Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.2 Updated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.3 SoftSwitching Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5 AC/AC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6 AC/DC/AC and DC/AC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . 27
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2. Uncontrolled AC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 SinglePhase HalfWave Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
v
vi Contents
2.2.1 R Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.2 R–L Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.2.1 Graphical Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.2.2 Iterative Method 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.2.3 Iterative Method 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.3 R–L Circuit with Freewheeling Diode . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.4 An R–L Load Circuit with a Back Emf . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.4.1 Negligible LoadCircuit Inductance . . . . . . . . . . . . . . . . . 42
2.2.5 SinglePhase HalfWave Rectiﬁer with a Capacitive Filter . . . . . . . . 42
2.3 SinglePhase FullWave Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3.1 R Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.2 R–C Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.3 R–L Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.4 ThreePhase HalfWave Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.4.1 R Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4.2 R–L Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.5 SixPhase HalfWave Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.5.1 SixPhase with a Neutral Line Circuit . . . . . . . . . . . . . . . . . . . . . . . 57
2.5.2 Double Antistar with a BalanceChoke Circuit . . . . . . . . . . . . . . . . 58
2.6 ThreePhase FullWave Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7 Multiphase FullWave Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.7.1 SixPhase FullWave Diode Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . 60
2.7.2 SixPhase DoubleBridge FullWave Diode Rectiﬁers . . . . . . . . . . . . 60
2.7.3 SixPhase DoubleTransformer DoubleBridge FullWave
Diode Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.7.4 SixPhase TripleTransformer DoubleBridge FullWave
Diode Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3. Controlled AC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.2 SinglePhase HalfWave Controlled Converters . . . . . . . . . . . . . . . . . . . . 68
3.2.1 R Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.2.2 R–L Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2.3 R–L Load Plus Back Emf V
c
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.3 SinglePhase FullWave Controlled Converters . . . . . . . . . . . . . . . . . . . . . 73
3.3.1 α > φ, Discontinuous Load Current . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.2 α < φ, Verge of Continuous Load Current . . . . . . . . . . . . . . . . . . . . 76
3.3.3 α < φ, Continuous Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4 ThreePhase HalfWave Controlled Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . 77
3.4.1 R Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.4.2 R–L Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.5 SixPhase HalfWave Controlled Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.5.1 SixPhase with a Neutral Line Circuit . . . . . . . . . . . . . . . . . . . . . . . 81
3.5.2 Double Antistar with a BalanceChoke Circuit . . . . . . . . . . . . . . . . 83
3.6 ThreePhase FullWave Controlled Converters . . . . . . . . . . . . . . . . . . . . . . 84
3.7 Multiphase FullWave Controlled Converters . . . . . . . . . . . . . . . . . . . . . . 87
3.7.1 Effect of Line Inductance on Output Voltage (Overlap) . . . . . . . . . . 90
Contents vii
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4. Implementing Power Factor Correction in AC/DC Converters . . . . . . . . . . . . . 95
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.2 DC/DC Converterized Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.3 PWM BoostType Rectiﬁers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.3.1 DCSide PWM BoostType Rectiﬁer . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3.1.1 ConstantFrequency Control . . . . . . . . . . . . . . . . . . . . . . 104
4.3.1.2 ConstantToleranceBand (Hysteresis) Control . . . . . . . . . 105
4.3.2 SourceSide PWM BoostType Rectiﬁers . . . . . . . . . . . . . . . . . . . . . 107
4.4 TappedTransformer Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.5 SingleStage PFC AC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.5.1 Operating Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.2 Mathematical Model Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.5.2.1 Averaged Model over One Switching Period T
s
. . . . . . . . 115
4.5.2.2 Averaged Model over One Half Line Period T
L
. . . . . . . . . 118
4.5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.5.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.6 VIENNARectiﬁers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.6.1 Circuit Analysis and Principle of Operation . . . . . . . . . . . . . . . . . . 124
4.6.2 Proposed Control Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.6.3 Block Diagram of the Proposed Controller for the
VIENNARectiﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.6.4 Converter Design and Simulation Results . . . . . . . . . . . . . . . . . . . . 131
4.6.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5. Ordinary DC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.2 Fundamental Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.2.1 Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.2.1.1 Voltage Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.2.1.2 Circuit Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.2.1.3 Continuous Current Condition (Continuous
Conduction Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.2.1.4 Capacitor Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.2.2 Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.2.2.1 Voltage Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.2.2.2 Circuit Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.2.2.3 Continuous Current Condition . . . . . . . . . . . . . . . . . . . . . 149
5.2.2.4 Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.2.3 Buck–Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.2.3.1 Voltage and Current Relations . . . . . . . . . . . . . . . . . . . . . 149
5.2.3.2 CCM Operation and Circuit Currents . . . . . . . . . . . . . . . . 150
5.3 P/O Buck–Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.1 Buck Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.2 Boost Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
viii Contents
5.3.3 Buck–Boost Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.4 Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.4 TransformerType Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.4.1 Forward Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.4.1.1 Fundamental Forward Converter . . . . . . . . . . . . . . . . . . . 157
5.4.1.2 Forward Converter with Tertiary Winding . . . . . . . . . . . . 160
5.4.1.3 Switch Mode Power Supplies with Multiple Outputs . . . . 161
5.4.2 FlyBack Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.4.3 Push–Pull Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.4.4 HalfBridge Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.4.5 Bridge Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.4.6 Zeta Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.5 Developed Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.5.1 P/O LuoConverter (Elementary Circuit) . . . . . . . . . . . . . . . . . . . . 165
5.5.2 N/O LuoConverter (Elementary Circuit) . . . . . . . . . . . . . . . . . . . . 171
5.5.3 D/O LuoConverter (Elementary Circuit) . . . . . . . . . . . . . . . . . . . . 173
5.5.4 CúkConverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.5.5 SEPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.6 TappedInductor Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6. Voltage Lift Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.2 Seven SelfLift Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.2.1 SelfLift CúkConverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.2.1.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 186
6.2.1.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 189
6.2.2 SelfLift P/O LuoConverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.2.2.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 191
6.2.2.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 192
6.2.3 Reverse SelfLift P/O LuoConverter . . . . . . . . . . . . . . . . . . . . . . . 193
6.2.3.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 194
6.2.3.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . 196
6.2.4 SelfLift N/O LuoConverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.2.4.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 196
6.2.4.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 198
6.2.5 Reverse SelfLift N/O LuoConverter . . . . . . . . . . . . . . . . . . . . . . . 198
6.2.5.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 199
6.2.5.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 201
6.2.6 SelfLift SEPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.2.6.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 202
6.2.6.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 204
6.2.7 Enhanced SelfLift P/O LuoConverter . . . . . . . . . . . . . . . . . . . . . 204
6.3 P/O LuoConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.3.1 ReLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.3.1.1 Variations of Currents and Voltages . . . . . . . . . . . . . . . . . 209
6.3.2 TripleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.3.3 QuadrupleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Contents ix
6.4 N/O LuoConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.4.1 ReLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
6.4.2 N/O TripleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.4.3 N/O QuadrupleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.5 Modiﬁed P/O LuoConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
6.5.1 SelfLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
6.5.2 ReLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.5.3 MultiLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.6 D/O LuoConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.6.1 SelfLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
6.6.1.1 Positive Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.6.1.2 Negative Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . 240
6.6.1.3 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 243
6.6.2 ReLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.6.2.1 Positive Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . . 245
6.6.2.2 Negative Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . 247
6.6.2.3 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 249
6.6.3 TripleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.6.3.1 Positive Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.6.3.2 Negative Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . 252
6.6.3.3 Discontinuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.6.4 QuadrupleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.6.4.1 Positive Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.6.4.2 Negative Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . 257
6.6.4.3 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 258
6.6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
6.6.5.1 Positive Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . . 260
6.6.5.2 Negative Conversion Path . . . . . . . . . . . . . . . . . . . . . . . . 261
6.6.5.3 Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.7 VL CúkConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.7.1 Elementary SelfLift Cúk Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.7.2 Developed SelfLift Cúk Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.7.3 ReLift Cúk Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.7.4 MultipleLift Cúk Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
6.7.5 Simulation and Experimental Veriﬁcation of an Elementary and a
Developed SelfLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
6.8 VL SEPICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.8.1 SelfLift SEPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.8.2 ReLift SEPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.8.3 MultipleLift SEPICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.8.4 Simulation and Experimental Results of a ReLift SEPIC . . . . . . . . . 270
6.9 Other D/O VoltageLift Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
6.9.1 Elementary Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.9.2 SelfLift D/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.9.3 Enhanced Series D/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
6.9.4 Simulation and Experimental Veriﬁcation of an Enhanced D/O
SelfLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
x Contents
6.10 SC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
6.10.1 OneStage SC Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
6.10.1.1 Operation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
6.10.1.2 Simulation and Experimental Results . . . . . . . . . . . . . . . . 280
6.10.2 TwoStage SC Buck–Boost Converter . . . . . . . . . . . . . . . . . . . . . . . 281
6.10.2.1 Operation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
6.10.2.2 Simulation and Experimental Results . . . . . . . . . . . . . . . . 282
6.10.3 ThreeStage SC P/O LuoConverter . . . . . . . . . . . . . . . . . . . . . . . . 282
6.10.3.1 Operation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
6.10.3.2 Simulation and Experimental Results . . . . . . . . . . . . . . . . 283
6.10.4 ThreeStage SC N/O LuoConverter . . . . . . . . . . . . . . . . . . . . . . . . 285
6.10.4.1 Operation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
6.10.4.2 Simulation and Experimental Results . . . . . . . . . . . . . . . . 285
6.10.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
6.10.5.1 Voltage Drop across Switched Capacitors . . . . . . . . . . . . . 286
6.10.5.2 Necessity of the Voltage Drop across SwitchedCapacitors
and Energy Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
6.10.5.3 Inrush Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
6.10.5.4 Power SwitchOn Process . . . . . . . . . . . . . . . . . . . . . . . . 289
6.10.5.5 Suppression of the Inrush and Surge Input Currents . . . . . 289
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7. SuperLift Converters and Ultralift Converter . . . . . . . . . . . . . . . . . . . . . . . . . 295
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
7.2 P/O SL LuoConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
7.2.1 Main Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
7.2.1.1 Elementary Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
7.2.1.2 ReLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
7.2.1.3 TripleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
7.2.1.4 HigherOrder Lift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.2.2 Additional Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.2.2.1 Elementary Additional Circuit . . . . . . . . . . . . . . . . . . . . . 302
7.2.2.2 ReLift Additional Circuit . . . . . . . . . . . . . . . . . . . . . . . . 305
7.2.2.3 TripleLift Additional Circuit . . . . . . . . . . . . . . . . . . . . . . 306
7.2.2.4 HigherOrder Lift Additional Circuit . . . . . . . . . . . . . . . . 309
7.2.3 Enhanced Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
7.2.3.1 Elementary Enhanced Circuit . . . . . . . . . . . . . . . . . . . . . . 309
7.2.3.2 ReLift Enhanced Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 311
7.2.3.3 TripleLift Enhanced Circuit . . . . . . . . . . . . . . . . . . . . . . . 312
7.2.3.4 HigherOrder Lift Enhanced Circuit . . . . . . . . . . . . . . . . . 314
7.2.4 ReEnhanced Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
7.2.4.1 Elementary ReEnhanced Circuit . . . . . . . . . . . . . . . . . . . 315
7.2.4.2 ReLift ReEnhanced Circuit . . . . . . . . . . . . . . . . . . . . . . . 317
7.2.4.3 TripleLift ReEnhanced Circuit . . . . . . . . . . . . . . . . . . . . 318
7.2.4.4 HigherOrder Lift ReEnhanced Circuit . . . . . . . . . . . . . . 320
7.2.5 MultipleEnhanced Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
7.2.5.1 Elementary MultipleEnhanced Circuit . . . . . . . . . . . . . . 321
7.2.5.2 ReLift MultipleEnhanced Circuit . . . . . . . . . . . . . . . . . . 323
Contents xi
7.2.5.3 TripleLift MultipleEnhanced Circuit . . . . . . . . . . . . . . . . 325
7.2.5.4 HigherOrder Lift MultipleEnhanced Circuit . . . . . . . . . . 327
7.2.6 Summary of P/O SL LuoConverters . . . . . . . . . . . . . . . . . . . . . . . 327
7.3 N/O SL LuoConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
7.3.1 Main Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
7.3.1.1 N/O Elementary Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 330
7.3.1.2 N/O ReLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
7.3.1.3 N/O TripleLift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 336
7.3.1.4 N/O HigherOrder Lift Circuit . . . . . . . . . . . . . . . . . . . . . 338
7.3.2 N/OAdditional Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
7.3.2.1 N/O Elementary Additional Circuit . . . . . . . . . . . . . . . . . 339
7.3.2.2 N/O ReLift Additional Circuit . . . . . . . . . . . . . . . . . . . . 342
7.3.2.3 TripleLift Additional Circuit . . . . . . . . . . . . . . . . . . . . . . 344
7.3.2.4 N/O HigherOrder Lift Additional Circuit . . . . . . . . . . . . 346
7.3.3 Enhanced Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
7.3.3.1 N/O Elementary Enhanced Circuit . . . . . . . . . . . . . . . . . 347
7.3.3.2 N/O ReLift Enhanced Circuit . . . . . . . . . . . . . . . . . . . . . 347
7.3.3.3 N/O TripleLift Enhanced Circuit . . . . . . . . . . . . . . . . . . 350
7.3.3.4 N/O HigherOrder Lift Enhanced Circuit . . . . . . . . . . . . . 353
7.3.4 ReEnhanced Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
7.3.4.1 N/O Elementary ReEnhanced Circuit . . . . . . . . . . . . . . . 353
7.3.4.2 N/O ReLift ReEnhanced Circuit . . . . . . . . . . . . . . . . . . 355
7.3.4.3 N/O TripleLift ReEnhanced Circuit . . . . . . . . . . . . . . . . 356
7.3.4.4 N/O HigherOrder Lift ReEnhanced Circuit . . . . . . . . . . 357
7.3.5 N/O MultipleEnhanced Series . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
7.3.5.1 N/O Elementary MultipleEnhanced Circuit . . . . . . . . . . 358
7.3.5.2 N/O ReLift MultipleEnhanced Circuit . . . . . . . . . . . . . . 360
7.3.5.3 N/O TripleLift MultipleEnhanced Circuit . . . . . . . . . . . 361
7.3.5.4 N/O HigherOrder Lift MultipleEnhanced Circuit . . . . . 362
7.3.6 Summary of N/O SL LuoConverters . . . . . . . . . . . . . . . . . . . . . . . 363
7.4 P/O Cascaded BoostConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
7.4.1 Main Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
7.4.1.1 Elementary Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 366
7.4.1.2 TwoStage Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 367
7.4.1.3 ThreeStage Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 368
7.4.1.4 HigherStage Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . 370
7.4.2 Additional Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
7.4.2.1 Elementary Boost Additional (Double) Circuit . . . . . . . . . 370
7.4.2.2 TwoStage Boost Additional Circuit . . . . . . . . . . . . . . . . . 372
7.4.2.3 ThreeStage Boost Additional Circuit . . . . . . . . . . . . . . . . 374
7.4.2.4 HigherStage Boost Additional Circuit . . . . . . . . . . . . . . . 375
7.4.3 Double Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
7.4.3.1 Elementary Double Boost Circuit . . . . . . . . . . . . . . . . . . . 376
7.4.3.2 TwoStage Double Boost Circuit . . . . . . . . . . . . . . . . . . . . 376
7.4.3.3 ThreeStage Double Boost Circuit . . . . . . . . . . . . . . . . . . . 378
7.4.3.4 HigherStage Double Boost Circuit . . . . . . . . . . . . . . . . . . 379
7.4.4 Triple Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
7.4.4.1 Elementary Triple Boost Circuit . . . . . . . . . . . . . . . . . . . . 380
7.4.4.2 TwoStage Triple Boost Circuit . . . . . . . . . . . . . . . . . . . . . 381
xii Contents
7.4.4.3 ThreeStage Triple Boost Circuit . . . . . . . . . . . . . . . . . . . . 383
7.4.4.4 HigherStage Triple Boost Circuit . . . . . . . . . . . . . . . . . . . 385
7.4.5 Multiple Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
7.4.5.1 Elementary Multiple Boost Circuit . . . . . . . . . . . . . . . . . . 386
7.4.5.2 TwoStage Multiple Boost Circuit . . . . . . . . . . . . . . . . . . . 387
7.4.5.3 ThreeStage Multiple Boost Circuit . . . . . . . . . . . . . . . . . . 388
7.4.5.4 HigherStage Multiple Boost Circuit . . . . . . . . . . . . . . . . . 390
7.4.6 Summary of P/O Cascaded Boost Converters . . . . . . . . . . . . . . . . . 390
7.5 N/O Cascaded Boost Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
7.5.1 Main Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
7.5.1.1 N/O Elementary Boost Circuit . . . . . . . . . . . . . . . . . . . . . 392
7.5.1.2 N/O TwoStage Boost Circuit . . . . . . . . . . . . . . . . . . . . . . 393
7.5.1.3 N/O ThreeStage Boost Circuit . . . . . . . . . . . . . . . . . . . . 395
7.5.1.4 N/O HigherStage Boost Circuit . . . . . . . . . . . . . . . . . . . 397
7.5.2 N/OAdditional Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
7.5.2.1 N/O Elementary Additional Boost Circuit . . . . . . . . . . . . 398
7.5.2.2 N/O TwoStage Additional Boost Circuit . . . . . . . . . . . . . 399
7.5.2.3 N/O ThreeStage Additional Boost Circuit . . . . . . . . . . . . 401
7.5.2.4 N/O HigherStage Additional Boost Circuit . . . . . . . . . . . 403
7.5.3 Double Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
7.5.3.1 N/O Elementary Double Boost Circuit . . . . . . . . . . . . . . . 404
7.5.3.2 N/O TwoStage Double Boost Circuit . . . . . . . . . . . . . . . . 404
7.5.3.3 N/O ThreeStage Double Boost Circuit . . . . . . . . . . . . . . 406
7.5.3.4 N/O HigherStage Double Boost Circuit . . . . . . . . . . . . . 408
7.5.4 Triple Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
7.5.4.1 N/O Elementary Triple Boost Circuit . . . . . . . . . . . . . . . . 408
7.5.4.2 N/O TwoStage Triple Boost Circuit . . . . . . . . . . . . . . . . . 410
7.5.4.3 N/O ThreeStage Triple Boost Circuit . . . . . . . . . . . . . . . . 412
7.5.4.4 N/O HigherStage Triple Boost Circuit . . . . . . . . . . . . . . . 413
7.5.5 Multiple Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
7.5.5.1 N/O Elementary Multiple Boost Circuit . . . . . . . . . . . . . . 414
7.5.5.2 N/O TwoStage Multiple Boost Circuit . . . . . . . . . . . . . . . 415
7.5.5.3 N/O ThreeStage Multiple Boost Circuit . . . . . . . . . . . . . 418
7.5.5.4 N/O HigherStage Multiple Boost Circuit . . . . . . . . . . . . 419
7.5.6 Summary of N/O Cascaded Boost Converters . . . . . . . . . . . . . . . . 419
7.6 UL LuoConverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
7.6.1 Operation of the UL LuoConverter . . . . . . . . . . . . . . . . . . . . . . . . 422
7.6.1.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 423
7.6.1.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 425
7.6.2 Instantaneous Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
7.6.2.1 Continuous Conduction Mode . . . . . . . . . . . . . . . . . . . . . 428
7.6.2.2 Discontinuous Conduction Mode . . . . . . . . . . . . . . . . . . . 429
7.6.3 Comparison of the Gain to Other Converters’ Gains . . . . . . . . . . . . 431
7.6.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
7.6.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
7.6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Contents xiii
8. PulseWidthModulated DC/AC Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
8.2 Parameters Used in PWM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
8.2.1 Modulation Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
8.2.1.1 Linear Range (m
a
≤ 1.0) . . . . . . . . . . . . . . . . . . . . . . . . . . 438
8.2.1.2 Overmodulation (1.0 < m
a
≤ 1.27) . . . . . . . . . . . . . . . . . . 438
8.2.1.3 Square Wave (Sufﬁciently Large m
a
> 1.27) . . . . . . . . . . . 439
8.2.1.4 Small m
f
(m
f
≤ 21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
8.2.1.5 Large m
f
(m
f
> 21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
8.2.2 Harmonic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
8.3 Typical PWM Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
8.3.1 Voltage Source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
8.3.2 Current Source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
8.3.3 Impedance Source Inverter (ZSI) . . . . . . . . . . . . . . . . . . . . . . . . . . 442
8.3.4 Circuits of DC/AC Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
8.4 SinglePhase VSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
8.4.1 SinglePhase HalfBridge VSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
8.4.2 SinglePhase FullBridge VSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
8.5 ThreePhase FullBridge VSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
8.6 ThreePhase FullBridge CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
8.7 Multistage PWM Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
8.7.1 Unipolar PWM VSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
8.7.2 Multicell PWM VSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
8.7.3 Multilevel PWM Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
8.8 ImpedanceSource Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
8.8.1 Comparison with VSI and CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
8.8.2 Equivalent Circuit and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 460
8.8.3 Circuit Analysis and Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . 463
8.9 Extended Boost ZSIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
8.9.1 Introduction to ZSI and Basic Topologies . . . . . . . . . . . . . . . . . . . . 466
8.9.2 Extended Boost qZSI Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
8.9.2.1 DiodeAssisted Extended Boost qZSI Topologies . . . . . . . 467
8.9.2.2 CapacitorAssisted Extended Boost qZSI Topologies . . . . . 470
8.9.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
9. Multilevel and SoftSwitching DC/AC Inverters . . . . . . . . . . . . . . . . . . . . . . . 479
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
9.2 DiodeClamped Multilevel Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
9.3 CapacitorClamped Multilevel Inverters (Flying Capacitor Inverters) . . . . . 487
9.4 Multilevel Inverters Using HBridge Converters . . . . . . . . . . . . . . . . . . . . 489
9.4.1 Cascaded EqualVoltage Multilevel Inverters . . . . . . . . . . . . . . . . . 491
9.4.2 Binary Hybrid Multilevel Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 491
9.4.3 QuasiLinear Multilevel Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.4.4 Trinary Hybrid Multilevel Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.5 Investigation of THMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
9.5.1 Topology and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
xiv Contents
9.5.2 Proof that the THMI has the Greatest Number of Output
Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
9.5.2.1 Theoretical Proof . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
9.5.2.2 Comparison of Various Kinds of Multilevel Inverters . . . . 498
9.5.2.3 Modulation Strategies for THMI . . . . . . . . . . . . . . . . . . . 499
9.5.2.4 Regenerative Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
9.5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
9.5.3.1 Experiment to Verify the Step Modulation and the Virtual
Stage Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
9.5.3.2 Experiment to Verify the New Method of Eliminating the
Regenerative Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
9.5.4 Trinary Hybrid 81Level Multilevel Inverters . . . . . . . . . . . . . . . . . 522
9.5.4.1 Space Vector Modulation . . . . . . . . . . . . . . . . . . . . . . . . . 525
9.5.4.2 DC Sources of HBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
9.5.4.3 Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
9.5.4.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . 531
9.6 Other Kinds of Multilevel Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
9.6.1 Generalized Multilevel Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . 535
9.6.2 MixedLevel Multilevel Inverter Topologies . . . . . . . . . . . . . . . . . . 535
9.6.3 Multilevel Inverters by Connection of ThreePhase
TwoLevel Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
9.7 SoftSwitching Multilevel Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
9.7.1 Notched DCLink Inverters for Brushless DC Motor Drive . . . . . . . 537
9.7.1.1 Resonant Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
9.7.1.2 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
9.7.1.3 Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
9.7.1.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . 546
9.7.2 Resonant Pole Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
9.7.2.1 Topology of the Resonant Pole Inverter . . . . . . . . . . . . . . 551
9.7.2.2 Operation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
9.7.2.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
9.7.2.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . 560
9.7.3 TransformerBased Resonant DCLink Inverter . . . . . . . . . . . . . . . 562
9.7.3.1 Resonant Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
9.7.3.2 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
9.7.3.3 Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
9.7.3.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . 573
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
10. Traditional AC/AC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
10.2 SinglePhase AC/AC VoltageRegulation Converters . . . . . . . . . . . . . . . . . 582
10.2.1 PhaseControlled SinglePhase AC/AC Voltage Controller . . . . . . . 582
10.2.1.1 Operation with R Load . . . . . . . . . . . . . . . . . . . . . . . . . . 582
10.2.1.2 Operation with RL Load . . . . . . . . . . . . . . . . . . . . . . . . . 585
10.2.1.3 Gating Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . 588
10.2.1.4 Operation with α < φ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
10.2.1.5 Power Factor and Harmonics . . . . . . . . . . . . . . . . . . . . . . 589
Contents xv
10.2.2 SinglePhase AC/AC Voltage Controller with On/Off Control . . . . 590
10.2.2.1 Integral Cycle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
10.2.2.2 PWMAC Chopper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
10.3 ThreePhase AC/AC VoltageRegulation Converters . . . . . . . . . . . . . . . . . 593
10.3.1 PhaseControlled ThreePhase AC Voltage Controllers . . . . . . . . . . 593
10.3.2 Fully Controlled ThreePhase ThreeWire AC Voltage Controller . . . 593
10.3.2.1 StarConnected Load with Isolated Neutral . . . . . . . . . . . 593
10.3.2.2 RL Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
10.3.2.3 DeltaConnected R Load . . . . . . . . . . . . . . . . . . . . . . . . . 597
10.4 Cycloconverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
10.4.1 SinglePhase/SinglePhase (SISO) Cycloconverters . . . . . . . . . . . . . 600
10.4.1.1 Operation with R Load . . . . . . . . . . . . . . . . . . . . . . . . . . 600
10.4.1.2 Operation with RL Load . . . . . . . . . . . . . . . . . . . . . . . . . 605
10.4.2 ThreePhase Cycloconverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
10.4.2.1 ThreePhase ThreePulse Cycloconverter . . . . . . . . . . . . . 606
10.4.2.2 ThreePhase 6Pulse and 12Pulse
Cycloconverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
10.4.3 Cycloconverter Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
10.4.3.1 Control Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . 612
10.4.3.2 Improved Control Schemes . . . . . . . . . . . . . . . . . . . . . . . 615
10.4.4 Cycloconverter Harmonics and Input Current Waveform . . . . . . . . 616
10.4.4.1 CirculatingCurrentFree Operations . . . . . . . . . . . . . . . . 616
10.4.4.2 CirculatingCurrent Operation . . . . . . . . . . . . . . . . . . . . . 616
10.4.4.3 Other Harmonic Distortion Terms . . . . . . . . . . . . . . . . . . 617
10.4.4.4 Input Current Waveform . . . . . . . . . . . . . . . . . . . . . . . . . 617
10.4.5 Cycloconverter Input Displacement/Power Factor . . . . . . . . . . . . . 618
10.4.6 Effect of Source Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
10.4.7 Simulation Analysis of Cycloconverter Performance . . . . . . . . . . . . 618
10.4.8 ForcedCommutated Cycloconverter . . . . . . . . . . . . . . . . . . . . . . . 618
10.5 Matrix Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
10.5.1 Operation and Control Methods of the MC . . . . . . . . . . . . . . . . . . . 622
10.5.1.1 Venturini Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
10.5.1.2 The SVM Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
10.5.1.3 Control Implementation and Comparison of the
Two Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
10.5.2 Commutation and Protection Issues in an MC. . . . . . . . . . . . . . . . . 626
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
11. Improved AC/AC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
11.1 DCmodulated SinglePhase SingleStage AC/AC Converters . . . . . . . . . . 629
11.1.1 Bidirectional Exclusive Switches S
M
–S
S
. . . . . . . . . . . . . . . . . . . . . 631
11.1.2 Mathematical Modeling of DC/DC Converters . . . . . . . . . . . . . . . . 632
11.1.3 DCModulated SingleStage BuckType
AC/AC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
11.1.3.1 Positive Input Voltage HalfCycle . . . . . . . . . . . . . . . . . . . 635
11.1.3.2 Negative Input Voltage HalfCycle . . . . . . . . . . . . . . . . . . 636
11.1.3.3 WholeCycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 636
11.1.3.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . 637
xvi Contents
11.1.4 DCModulated SingleStage BoostType AC/AC Converter . . . . . . 642
11.1.4.1 Positive Input Voltage HalfCycle . . . . . . . . . . . . . . . . . . . 643
11.1.4.2 Negative Input Voltage HalfCycle . . . . . . . . . . . . . . . . . . 644
11.1.4.3 WholeCycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 644
11.1.4.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . 645
11.1.5 DCModulated SingleStage Buck–BoostType AC/AC
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
11.1.5.1 Positive Input Voltage HalfCycle . . . . . . . . . . . . . . . . . . . 648
11.1.5.2 Negative Input Voltage HalfCycle . . . . . . . . . . . . . . . . . . 650
11.1.5.3 WholeCycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 650
11.1.5.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . 651
11.2 Other Types of DCModulated AC/AC Converters . . . . . . . . . . . . . . . . . . 653
11.2.1 DCModulated P/O LuoConverterType AC/AC Converter . . . . . 653
11.2.2 DCModulated TwoStage BoostType AC/AC Converter . . . . . . . . 656
11.3 DCModulated Multiphase AC/AC Converters . . . . . . . . . . . . . . . . . . . . . 658
11.3.1 DCModulated ThreePhase BuckType AC/AC Converter . . . . . . . 660
11.3.2 DCModulated ThreePhase BoostType AC/AC Converter . . . . . . 660
11.3.3 DCModulated ThreePhase Buck–BoostType AC/AC
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
11.4 Subenvelope Modulation Method to Reduce the THD
of AC/AC Matrix Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
11.4.1 SEM Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
11.4.1.1 Measure the Input Instantaneous Voltage . . . . . . . . . . . . . 667
11.4.1.2 Modulation Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
11.4.1.3 Improve Voltage Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
11.4.2 24Switch Matrix Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
11.4.3 Current Commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
11.4.3.1 Current Commutation between Two Input Phases . . . . . . 675
11.4.3.2 Current CommutationRelated Three Input Phases . . . . . . 676
11.4.4 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 678
11.4.4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
11.4.4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
12. AC/DC/AC and DC/AC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
12.2 AC/DC/AC Converters Used in Wind Turbine Systems . . . . . . . . . . . . . . 688
12.2.1 Review of Traditional AC/AC Converters . . . . . . . . . . . . . . . . . . . 689
12.2.2 NewAC/DC/AC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
12.2.2.1 AC/DC/AC BoostType Converters . . . . . . . . . . . . . . . . . 690
12.2.2.2 ThreeLevel DiodeClamped AC/DC/AC
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
12.2.3 TwoLevel AC/DC/AC ZSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
12.2.4 ThreeLevel DiodeClamped AC/DC/AC ZSI . . . . . . . . . . . . . . . . 695
12.2.5 Linking a Wind Turbine System to a Utility Network . . . . . . . . . . . 695
12.3 DC/AC/DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
12.3.1 Review of Traditional DC/DC Converters . . . . . . . . . . . . . . . . . . . 696
12.3.2 ChopperType DC/AC/DC Converters . . . . . . . . . . . . . . . . . . . . . 698
Contents xvii
12.3.3 SwitchedCapacitor DC/AC/DC Converters . . . . . . . . . . . . . . . . . 698
12.3.3.1 SingleStage SwitchedCapacitor DC/AC/DC
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
12.3.3.2 ThreeStage SwitchedCapacitor DC/AC/DC
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
12.3.3.3 FourStage SwitchedCapacitor DC/AC/DC
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Homework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
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Preface
This book is aimed at both engineering students and practicing professionals specializing
in power electronics and provides useful and concise information with regard to advanced
converters. It contains more than 200 topologies concerning advanced converters that have
been developed by the authors. Some recently published topologies are also included. The
prototypes presented here demonstrate novel approaches that the authors hope will be of
great beneﬁt to the area of power electronics.
Power electronics is the technology behind the conversion of electrical energy from a
source to the requirements of the enduser. Although, it is of vital importance to both
industry and the individual citizen, it is somewhat taken for granted in much the same
way as the air we breathe and the water we drink. Energy conversion techniques are now
a primary focus of the power electronics community with rapid advances being made in
conversion technologies in recent years that are detailed in this book along with a look at
the historical problems that have now been solved.
The necessary equipment for energy conversion can be divided into four groups: AC/DC
rectiﬁers, DC/DC converters, DC/AC inverters, and AC/AC transformers. AC/DC recti
ﬁers were the earliest converters to be developed and, consequently, most of the traditional
circuits have now been widely published and discussed. However, some of those circuits
have not been analyzed in any great detail with the singlephase diode rectiﬁer with R–C
load being a typical example. Recently, there has been a new approach to AC/DC rectiﬁers
that involves power factor correction (PFC) and unity power factor (UPF), the techniques
of which are introduced in this book.
The technology of DC/DCconversion is making rapid progress and, according to incom
plete statistics, there are more than 600 topologies of DC/DC converters in existence with
new ones being created every year. It would be an immense task to try and examine all of
these approaches. However, in 2001, the authors were able to systematically sort and cate
gorize the DC/DC converters into six groups. Our main contribution in this ﬁeld involves
voltagelift and superlift techniques for which more than 100 topologies are introduced in
this book.
DC/AC inverters can be divided into two groups: pulsewidthmodulation (PWM)
inverters and multilevel inverters. People will be more familiar with PWM inverters as
the voltage source inverter (VSI) and current source inverter (CSI). In 2003, details of the
impedancesource inverter (ZSI) ﬁrst appeared and a great deal of interest was created
from power electronics experts. With its advantages so obvious in research and indus
trial applications, hundreds of papers concerning ZSI have been published in the ensuing
years. Multilevel inverters were invented in the early 1980s and developed quickly. Many
new topologies have been designed and applied to industrial applications, especially in
renewable energy systems. Typical circuits include diodeclamped inverters, capacitor
clampedinverters, andhybridHbridge multilevel inverters. Multilevel inverters overcame
the drawbacks of the PWM inverter and paved the way for industrial applications.
xix
xx Preface
Traditional AC/AC converters are divided into three groups: voltagemodulation
AC/AC converters, cycloconverters, and matrix converters. All traditional AC/AC con
verters can only convert a high voltage to a low voltage with adjustable amplitude and
frequency. Their drawbacks are limited output voltage and poor total harmonic distortion
(THD). Therefore, newtypes of AC/ACconverters, suchas subenvelopemodulated(SEM)
AC/AC converters and DCmodulated AC/AC converters have been created. These tech
niques successfully overcome the disadvantage of high THD. Also, DCmodulatedAC/AC
converters have other advantages, for instance, multiphase outputs.
Due to the world’s increasing problem of energy resource shortage, the development of
renewable energysources, energysavingtechniques, andpower supplyqualityhas become
an urgent issue. There is no time for delay. Renewable energy source systems require a large
number of converters. For example, new AC/DC/AC converters are necessary in wind
turbine power systems, and DC/AC/DC converters are necessary in solar panel power
systems.
The book consists of 12 chapters. The general knowledge on converters is introduced
in Chapter 1. Traditional AC/DC diode rectiﬁers, controlled AC/DC rectiﬁers, and power
factor correction and unity power factor techniques are discussed in Chapters 2 through 4.
Classic DC/DCconverters, voltagelift andsuperlift techniques are introducedinChapters
5 through 7. Pulsewidthmodulated DC/AC inverters are investigated in Chapter 8 and
multilevel DC/AC inverters in Chapter 9. Traditional and improved AC/AC converters
are introduced in Chapters 10 and 11. AC/DC/AC and DC/AC/DC converters used in
renewable energy source systems are presented in Chapter 12.
As a textbook, there are many examples and homework questions in each chapter, which
will help the reader thoroughly understand all aspects of research and application. This
book can be both a textbook for university students studying power electronics and a
reference book for practicing engineers involved in the design and application of power
electronics.
MATLAB
®
is a registered trademark of The MathWorks, Inc. For product information,
please contact:
The MathWorks, Inc.
3 Apple Hill Drive
Natick, MA017602098 USA
Tel: 508 647 7000
Fax: 5086477001
Email: info@mathworks.com
Web: www.mathworks.com
Dr. Fang Lin Luo and Dr. Hong Ye
Nanyang Technological University
Singapore
Authors
Dr. Fang Lin Luo is an associate professor with the School
of Electrical and Electronic Engineering, Nanyang Techno
logical University (NTU), Singapore. He received his BSc
degree, ﬁrst class with honors, in RadioElectronic Physics
from Sichuan University, Chengdu, China, in 1968 and his
PhD degree in Electrical Engineering and Computer Science
(EE & CS) from Cambridge University, UK, in 1986.
After his graduation from Sichuan University, he joined
the Chinese Automation Research Institute of Metallurgy
(CARIM), Beijing, China, as Senior Engineer. From there, he
then went to Entreprises Saunier Duval, Paris, France, as a
project engineer in 1981–1982, and subsequently to Hocking
NDT Ltd, AllenBradley IAP Ltd, and Simplatroll Ltd in England as senior engineer after
he received his PhD degree from Cambridge University. He is Fellow of the Cambridge
philosophical society and a senior member of IEEE. He has published nine books and 300
technical papers in IEEE Transactions, IEE/IET Proceedings and other international journals,
and in various international conferences. His present research interests include power elec
tronics and DC & AC motor drives with computerized artiﬁcial intelligent control (AIC)
and digital signal processing (DSP), and digital power electronics.
He is currently the associate editor of both IEEE Transactions on Power Electronics and IEEE
Transactions on Industrial Electronics. He is also an international editor for the international
journal Advanced Technology of Electrical Engineering and Energy. Dr. Luo was chief editor
of the international journal Power Supply Technologies and Applications in 1998–2003. He is
general chairman of the First IEEE Conference on Industrial Electronics and Applications
(ICIEA2006) and of the Third IEEE Conference on Industrial Electronics and Applications
(ICIEA2008).
Dr. Hong Ye received her bachelor’s degree, ﬁrst class, in
1995, a master engineering degree from Xi’an JiaoTong Uni
versity, China, in 1999, and her PhD degree from Nanyang
Technological University (NTU), Singapore, in 2005. She was
with the R&D Institute, XIYI Company Ltd, China, as a
research engineer from 1995 to 1997. She was with NTU as
a research associate in 2003–2004 and has been a research
fellow from 2005.
Dr. Ye is an IEEE member and has coauthored nine books.
She has published more than 60 technical papers in IEEE
Transactions, IEE Proceedings and other international journals
and various international conferences. Her research interests
are power electronics and conversion technologies, signal processing, operations research,
and structural biology.
xxi
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1
Introduction
Power electronics is the technology of processing and controlling the ﬂowof electric energy
by supplying voltages and currents in a form that is optimally suited to the enduser’s
requirements [1]. Atypical block diagramis given in Figure 1.1 [2]. The input power can be
either AC and DC sources. Ageneral example is one in which the AC input power is from
the electric utility. The output power to the load can be either AC and DC voltages. The
power processor inthe blockdiagramis usuallycalleda converter. Conversiontechnologies
are used to construct converters. There are four types of converters [3]:
• AC/DC converters/rectiﬁers (AC to DC)
• DC/DC converters (DC to DC)
• DC/AC inverters/converters (DC to AC)
• AC/AC converters (AC to AC).
We will use converter as a generic term to refer to a single power conversion stage that
may perform any of the functions listed above. To be more speciﬁc, during AC to DC and
DC to AC conversion, the term rectiﬁer refers to a converter in which the average power
ﬂow is from the AC to the DC side. The term inverter refers to a converter in which the
average power ﬂowis fromthe DC to the AC side. If the power ﬂowthrough the converter
is reversible, as shown in Figure 1.2 [2], we refer to the converter in terms of its rectiﬁer and
inverter modes of operation.
1.1 Symbols and Factors Used in This Book
In this chapter, we list the factors and symbols used in this book. If no speciﬁc description
is given, the parameters follow the meaning stated here.
1.1.1 Symbols Used in Power Systems
For instantaneous values of variables such as voltage, current, and power, which are func
tions of time, lowercase letters v, i, and p are, respectively, used. They are functions of time
performing in the time domain. We may or may not explicitly show that they are functions
of time, for example, using v rather than v(t). Uppercase symbols V and I refer to their
computed values from their instantaneous waveforms. They generally refer to an average
value in DC quantities and a rootmeansquare (rms) value in AC quantities. If there is a
1
2 Power Electronics
Power input
Power
processor
Power output
Load
Measurement
Control
signal
Controller
Reference
v
i
i
i
i
O
v
O
FIGURE 1.1 Block diagram of a power electronics system.
possibility of confusion, the subscript avg or rms is added explicitly. The average power is
always indicated by P.
Usually, the input voltage and current are represented by v
in
and i
in
(or v
1
and i
1
), and
the output voltage and current are represented by v
O
and i
O
(or v
2
and i
2
). The input and
output powers are represented by P
in
and P
O
. The power transfer efﬁciency (η) is deﬁned
as η = P
O
/P
in
.
Passive loads such as resistor R, inductor L, and capacitor C are generally used in circuits.
We use R, L, and C to indicate their symbols and values as well. All these three parameters
and their combination Zare linear loads since the performance of the circuit constructed by
these components is described by a linear differential equation. Z is used as the impedance
of a linear load. If the circuit consists of a resistor R, an inductor L, and a capacitor C in
series connection, the impedance Z is represented by
Z = R +jωL −j
1
ωC
= Z ∠φ, (1.1)
where Ris the resistance measured in units of Ω, L is the inductance measured in H, C is the
capacitance measured in F, ω is the AC supply angular frequency measured in rad/s, and
ω = 2πf where f is the AC supply frequency measured in Hz. For the calculation of Z, if
there is no capacitor in the circuit, j(1/ωC) is omitted (do not take c = 0 and j(1/ωC) = >∞).
The absolute impedance Z and the phase angle φ are
Z =
_
R
2
+[ωL −(1/ωC)]
2
,
φ = tan
−1
ωL −(1/ωC)
R
.
(1.2)
Rectifier mode
Converter
AC DC
P
P
Inverter mode
FIGURE 1.2 AC to DC converters.
Introduction 3
Example 1.1
A circuit has a load with a resistor R = 20Ω, an inductor L = 20mH, and a capacitor C = 200μF
in series connection. The voltage supply frequency f = 60Hz. Calculate the load impedance and
the phase angle.
SOLUTION
From Equation 1.1, the impedance Z is
Z = R +jωL −j
1
ωC
= 20 +j120π ×0.02 −j
1
120π ×0.0002
= 20 +j(7.54 −13.26) = 20 −j5.72 = Z ∠φ.
From Equation 1.2, the absolute impedance Z and the phase angle φ are
Z =
_
R
2
+
_
ωL −
1
ωC
_
2
=
_
20
2
+5.72
2
= 20.8Ω,
φ = tan
−1
ωL −(1/ωC)
R
= tan
−1
−5.72
20
= −17.73
◦
.
If a circuit consists of a resistor R and an inductor L in series connection, the corresponding
impedance Z is given by
Z = R +jωL = Z ∠φ. (1.3)
The absolute impedance Z and the phase angle φ are
Z =
_
R
2
+(ωL)
2
,
φ = tan
−1
ωL
R
.
(1.4)
We deﬁne the circuit time constant τ as
τ =
L
R
. (1.5)
If a circuit consists of a resistor R and a capacitor C in series connection, the impedance Z is
given by
Z = R −j
1
ωC
= Z ∠φ. (1.6)
The absolute impedance Z and the phase angle φ are
Z =
_
R
2
+
_
1
ωC
_
2
,
φ = −tan
−1
1
ωCR
.
(1.7)
4 Power Electronics
We deﬁne the circuit time constant τ as
τ = RC. (1.8)
Summary of the Symbols
Symbol Explanation (measuring unit)
C Capacitance (F)
f Frequency (Hz)
i, I Instantaneous current, Average/rms current (A)
L Inductance (H)
R Resistance (Ω)
p, P Instantaneous power, Rated/real power (W)
q, Q Instantaneous reactive power, Rated reactive power (VAR)
s, S Instantaneous apparent power, Rated apparent power (VA)
v, V Instantaneous voltage, Average/rms voltage (V)
Z Impedance (Ω)
φ Phase angle (
◦
or rad)
η Efﬁciency (%)
τ Time constant (s)
ω Angular frequency (rad/s), ω = 2πf
1.1.2 Factors and Symbols Used in AC Power Systems
The input AC voltage can be either singlephase or threephase voltages. They are usually
a pure sinusoidal wave function. Asinglephase input voltage v(t) can be expressed as [4]
v(t) =
√
2V sin ωt = V
m
sin ωt, (1.9)
where v is the instantaneous input voltage, V the rms value, V
m
the amplitude, and ω the
angular frequency, ω = 2πf ( f is the supply frequency). Usually, the input current may
not be a pure sinusoidal wave that depends on load. If the input voltage supplies a linear
load (resistive, inductive, capacitive loads or their combination), the input current i(t) is
not distorted, but may be delayed in a phase angle φ. In this case, it can be expressed as
i(t) =
√
2I sin(ωt −φ) = I
m
sin(ωt −φ), (1.10)
where i is the instantaneous input current, I the rms value, I
m
the amplitude, and φ the
phasedelay angle. We deﬁne the power factor (PF) as
PF = cos φ. (1.11)
PF is the ratio of real power (P) to apparent power (S). We have the relation S = P +jQ,
where Q is the reactive power. The power vector diagram is shown in Figure 1.3. We have
Introduction 5
S = P+jQ
jQ
P
f
FIGURE 1.3 Power vector diagram.
the relations between the powers as follows:
S = VI
∗
=
V
2
Z
∗
= P +jQ = S ∠φ, (1.12)
S =
_
P
2
+Q
2
, (1.13)
φ = tan
−1
Q
P
, (1.14)
P = Scos φ, (1.15)
Q = Ssin φ. (1.16)
If the input current is distorted, it consists of harmonics. Its fundamental harmonic can
be expressed as
i
1
=
√
2I
1
sin(ωt −φ
1
) = I
m1
sin(ωt −φ
1
), (1.17)
where i
1
is the fundamental harmonic instantaneous value, I
1
the rms value, I
m1
the
amplitude, and φ
1
the phase angle. In this case, the displacement power factor (DPF) is
deﬁned as
DPF = cos φ
1
. (1.18)
Correspondingly, PF is deﬁned as
PF =
DPF
_
1 +THD
2
, (1.19)
where THD is the total harmonic distortion. It can be used to measure both voltage and
current waveforms. It is deﬁned as
THD =
_
∞
n=2
I
2
n
I
1
or THD =
_
∞
n=2
V
2
n
V
1
, (1.20)
where I
n
or V
n
is the amplitude of the nthorder harmonic.
The harmonic factor (HF) is a variable that describes the weightedpercent of the nthorder
harmonic referring to the amplitude of the fundamental harmonic V
1
. It is deﬁned as
HF
n
=
I
n
I
1
or HF
n
=
V
n
V
1
, (1.21)
6 Power Electronics
where n = 1 corresponds to the fundamental harmonic. Therefore, HF
1
= 1. THD can be
written as
THD =
¸
¸
¸
_
∞
n=2
HF
2
n
. (1.22)
Apure sinusoidal waveform has THD = 0.
The weightedtotal harmonic distortion(WTHD) is a variable that describes the waveform
distortion. It is deﬁned as
WTHD =
_
∞
n=2
(V
2
n
/n)
V
1
. (1.23)
Note that THD gives an immediate measure of the inverter output voltage waveform
distortion. WTHD is often interpreted as the normalized current ripple expected in an
inductive load when fed from the inverter output voltage.
Example 1.2
A load with a resistor R = 20Ω, an inductor L = 20mH, and a capacitor C = 200μF in series
connection is supplied by an AC voltage of 240V (rms) with frequency f = 60Hz. Calculate the
circuit current, and the corresponding apparent power S, real power P, reactive power Q, and PF.
SOLUTION
From Example 1.1, the impedance Z is
Z = R +jωL −j
1
ωC
= 20 +j120π ×0.02 −j
1
120π ×0.0002
= 20 +j(7.54 −13.26) = 20 −j5.72 = 20.8∠−17.73
◦
Ω.
The circuit current I is
I =
V
Z
=
240
20.8∠−17.73
◦
= 11.54∠17.73
◦
A.
The apparent power S is
S = VI
∗
= 240 ×11.54∠−17.73
◦
= 2769.23∠−17.73
◦
VA.
The real power P is
P = S cos φ = 2769.23 ×cos 17.73
◦
= 2637.7W.
The reactive power Q is
Q = S sinφ = 2769.23 ×sin−17.73
◦
= −843.3VAR.
PF is
PF = cos φ = 0.9525 leading.
Introduction 7
Summary of the Symbols
Symbol Explanation (measuring unit)
DPF Displacement power factor (%)
HF
n
nthorder harmonic factor
i
1
, I
1
Instantaneous fundamental current, Average/rms fundamental current (A)
i
n
, I
n
Instantaneous nthorder harmonic current, Average/rms nthorder harmonic current (A)
I
m
Current amplitude (A)
PF Power factor (leading/lagging %)
q, Q Instantaneous reactive power, Rated reactive power (VAR)
s, S Instantaneous apparent power, Rated apparent power (VA)
t Time (s)
THD Total harmonic distortion (%)
v
1
, V
1
Instantaneous fundamental voltage, Average/rms fundamental voltage (V)
v
n
, V
n
Instantaneous nthorder harmonic voltage, Average/rms nthorder harmonic voltage (V)
WTHD Weighted total harmonic distortion (%)
φ
1
Phase angle of the fundamental harmonic (
◦
or rad)
1.1.3 Factors and Symbols Used in DC Power Systems
We deﬁne the output DC voltage instantaneous value as v
d
and the average value as V
d
(or V
d0
) [5]. A pure DC voltage has no ripple; hence it is called ripplefree DC voltage.
Otherwise, a DC voltage is distorted, and consists of DC components and AC harmonics.
Its rms value is V
d−rms
. For a distorted DC voltage, the rms value V
d−rms
is constantly
higher than the average value V
d
. The ripple factor (RF) is deﬁned as
RF =
_
∞
n=1
V
2
n
V
d
, (1.24)
where V
n
is the nthorder harmonic. The form factor (FF) is deﬁned as
FF =
V
d−rms
V
d
=
_
∞
n=0
V
2
n
V
d
, (1.25)
where V
0
is the 0thorder harmonic, that is, the average component V
d
. Therefore, we obtain
FF > 1, and the relation
RF =
_
FF
2
−1. (1.26)
FF and RF are used to describe the quality of a DC waveform (voltage and current
parameters). For a pure DC voltage, FF = 1 and RF = 0.
Summary of the Symbols
Symbol Explanation (measuring unit)
FF Form factor (%)
RF Ripple factor (%)
v
d
, V
d
Instantaneous DC voltage, Average DC voltage (V)
V
d−rms
rms DC voltage (V)
v
n
, V
n
Instantaneous nthorder harmonic voltage, Average/rms nthorder harmonic voltage (V)
8 Power Electronics
1.1.4 Factors and Symbols Used in Switching Power Systems
Switching power systems, such as power DC/DCconverters, power PWMDC/ACinvert
ers, softswitching converters, and resonant converters, are widely used in power transfer
equipment. Ingeneral, a switching power systemhas a pumping circuit andseveral energy
storage elements. It is likely an energy container to store some energy during performance.
The input energy does not smoothly ﬂow through the switching power system from the
input source to the load. The energy is quantiﬁedby the switching circuit, andthenpumped
through the switching power system from the input source to the load [6–8].
We assume that the switching frequency is f andthat the corresponding periodis T = 1/f .
The pumping energy (PE) is used to count the input energy in a switching period T. Its
calculation formula is
PE =
T
0
P
in
(t) dt =
T
0
V
in
i
in
(t) dt = V
in
I
in
T, (1.27)
where
I
in
=
T
0
i
in
(t) dt (1.28)
is the average value of the input current if the input voltage V
1
is constant. Usually, the
input average current I
1
depends on the conduction duty cycle.
Energy storage in switching power systems has received much attention in the past.
Unfortunately, there is still no clear concept to describe the phenomena and reveal the
relationship between the stored energy (SE) and its characteristics.
The SE in an inductor is
W
L
=
1
2
LI
2
L
. (1.29)
The SE across a capacitor is
W
C
=
1
2
CV
2
C
. (1.30)
Therefore, if there are n
L
inductors andn
C
capacitors, the total SEina DC/DCconverter is
SE =
n
L
j=1
W
Lj
+
n
C
j=1
W
Cj
. (1.31)
Usually, the SE is independent of switching frequency f (as well as switching period T).
Since inductor currents and capacitor voltages rely on the conduction duty cycle k, the SE
also relies on k. We use SE as a new parameter in further descriptions.
Most switching power systems consist of inductors and capacitors. Therefore, we can
deﬁne the capacitor–inductor stored energy ratio (CIR) as
CIR =
n
C
j=1
W
Cj
n
C
j=1
W
Lj
. (1.32)
Introduction 9
As describedinthe previous sections, the input energy ina periodT is the PE = P
in
×T =
V
in
I
in
×T. We now deﬁne the energy factor (EF), that is, the ratio of SE to PE, as
EF =
SE
PE
=
SE
V
in
I
in
T
=
m
j=1
W
Lj
+
n
j=1
W
Cj
V
in
I
in
T
. (1.33)
EF is a very important factor of a switching power system. It is usually independent of
the conduction duty cycle and inversely proportional to switching frequency f since PE is
proportional to switching period T.
The time constant τ of a switching power system is a new concept that describes the
transient process. If there are no power losses in the system, it is deﬁned as
τ =
2T ×EF
1 +CIR
. (1.34)
This time constant τ is independent of switching frequency f (or period T = 1/f ). It is
available to estimate the systemresponses for a unitstepfunctionandimpulse interference.
If there are power losses and η < 1, τ is deﬁned as
τ =
2T ×EF
1 +CIR
_
1 +CIR
1 −η
η
_
. (1.35)
If there are no power losses, η = 1, Equation 1.35 becomes Equation 1.34. Usually, if the
power losses (lower efﬁciency η) are higher, the time constant τ is larger since CIR > 1.
The damping time constant τ
d
of a switching power systemis a newconcept that describes
the transient process. If there are no power losses, it is deﬁned as
τ
d
=
2T ×EF
1 +CIR
CIR. (1.36)
This damping time constant τ
d
is independent of switching frequency f (or period T =
1/f ). It is available to estimate the oscillation responses for a unitstep function and impulse
interference.
If there are power losses and η < 1, τ
d
is deﬁned as
τ
d
=
2T ×EF
1 +CIR
CIR
η +CIR(1 −η)
. (1.37)
If there are no power losses, η = 1, Equation 1.37 becomes Equation 1.36. Usually, if the
power losses (lower efﬁciency η) are higher, the damping time constant τ
d
is smaller since
CIR > 1.
The time constant ratio ξ of a switching power system is a new concept that describes the
transient process. If there are no power losses, it is deﬁned as
ξ =
τ
d
τ
= CIR. (1.38)
This time constant ratio is independent of switching frequency f (or period T = 1/f ).
It is available to estimate the oscillation responses for a unitstep function and impulse
interference.
10 Power Electronics
If there are power losses and η < 1, ξ is deﬁned as
ξ =
τ
d
τ
=
CIR
η[1 +CIR(1 −η/η)]
2
. (1.39)
If there are no power losses, η = 1, Equation 1.39 becomes Equation 1.38. Usually, if the
power losses (the lower efﬁciency η) are higher, the time constant ratio ξ is smaller since
CIR > 1. Fromthis analysis, most switchingpower systems withlower power losses possess
larger output voltage oscillation when the converter operation state changes. On the other
hand, switching power systems with high power losses will possess smoothening output
voltage when the converter operation state changes.
By cybernetic theory, we can estimate the unitstep function response using the ratio ξ. If
the ratio ξ is equal to or smaller than0.25, the corresponding unitstepfunctionresponse has
no oscillation and overshot. However, if the ratio ξ is greater than 0.25, the corresponding
unitstep function response has oscillation and overshot. The higher the value of the ratio
ξ, the heavier the oscillation with higher overshot.
Summary of the Symbols
Symbol Explanation (measuring unit)
CIR Capacitor–inductor stored energy ratio
EF Energy factor
f Switching frequency (Hz)
k Conduction duty cycle
PE Pumping energy ( J)
SE Total stored energy ( J)
W
L
, W
C
SE in an inductor/capacitor ( J)
T Switching period (s)
τ Time constant (s)
τ
d
Damping time constant (s)
ξ Time constant ratio
1.1.5 Other Factors and Symbols
Atransfer function is the mathematical modeling of a circuit and a system. It describes the
dynamic characteristics of the circuit and the system. Using the transfer function, we can
easily obtain the system step and impulse responses by applying an input signal. Atypical
secondorder transfer function is [6–8]
G(s) =
M
1 +sτ +s
2
ττ
d
=
M
1 +sτ +s
2
ξτ
2
, (1.40)
where M is the voltage transfer gain (M = V
O
/V
in
), τ the time constant (Equation 1.35),
τ
d
the damping time constant (Equation 1.37), τ
d
= ξτ (Equation 1.39), and s the Laplace
operator in the sdomain.
Using this mathematical model of a switching power system, it is signiﬁcantly easier to
describe the characteristics of the transfer function. In order to appreciate the characteristics
of the transfer function more fully, a few situations are given below.
Introduction 11
1.1.5.1 Very Small Damping Time Constant
If the damping time constant is very small (i.e., τ
d
τ, ξ 1) and it can be ignored, the
value of the damping time constant τ
d
is omitted (i.e., τ
d
= 0, ξ = 0). The transfer function
(Equation 1.40) is downgraded to ﬁrst order as
G(s) =
M
1 +sτ
. (1.41)
The unitstep function response in the time domain is
g(t) = M(1 −e
−t/τ
). (1.42)
The transient process (settlingtime) is nearlythree times the time constant (3τ), toproduce
g(t) = g(3τ) = 0.95 M. The response in the time domain is shown in Figure 1.4 with τ
d
= 0.
The impulse interference response is
Δg(t) = U · e
−t/τ
, (1.43)
where Uis the interference signal. The interference recovering progress is nearly three times
the time constant (3τ), and is shown in Figure 1.5 with τ
d
= 0.
1.1.5.2 Small Damping Time Constant
If the damping time constant is small (i.e., τ
d
< τ/4, ξ < 0.25) and cannot be ignored, the
value of the damping time constant τ
d
is not omitted. The transfer function (Equation 1.40)
is retained as a secondorder function with two real poles (−σ
1
and −σ
2
) as
G(s) =
M
1 +sτ +s
2
ττ
d
=
M/ττ
d
(s +σ
1
)(s +σ
2
)
, (1.44)
0
0
0.2
0.4
0.6
0.8
1
1 2 3 4
Time (tor)
M
a
g
n
i
t
u
d
e
(
M
)
t
d
= 0
t
d
= 0.1t
t
d
= 0.25t
t
d
= 0.5t
5 6 7 8
FIGURE 1.4 Unitstep function responses (τ
d
= 0, 0.1τ, 0.25τ, and 0.5τ).
12 Power Electronics
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
Time (tor)
M
a
g
n
i
t
u
d
e
(
M
)
t
d
= 0
t
d
= 0.1t
t
d
= 0.25t
t
d
= 0.5t
0 1 2 3 4 5 6 7 8 9 10
FIGURE 1.5 Impulse responses (τ
d
= 0, 0.1τ, 0.25τ, and 0.5τ).
where
σ
1
=
τ +
_
τ
2
−4ττ
d
2ττ
d
and σ
2
=
τ −
_
τ
2
−4ττ
d
2ττ
d
.
There are two real poles in the transfer function, assuming σ
1
> σ
2
. The unitstep function
response in the time domain is
g(t) = M(1 +K
1
e
−σ
1
t
+K
2
e
−σ
2
t
), (1.45)
where
K
1
= −
1
2
+
τ
2
_
τ
2
−4ττ
d
and K
2
= −
1
2
−
τ
2
_
τ
2
−4ττ
d
.
The transient process is nearly three times the time value 1/σ
1
, 3/σ
1
< 3τ. The response
process is quick without oscillation. The corresponding waveform in the time domain is
shown in Figure 1.4 with τ
d
= 0.1τ.
The impulse interference response is
Δg(t) =
U
√
1 −4τ
d
/τ
(e
−σ
2
t
−e
−σ
1
t
), (1.46)
where U is the interference signal. The transient process is nearly three times the time value
1/σ
1
, 3/σ
1
< 3τ. The response waveform in the time domain is shown in Figure 1.5 with
τ
d
= 0.1τ.
1.1.5.3 Critical Damping Time Constant
If the damping time constant is equal to the critical value (i.e., τ
d
= τ/4), the transfer
function (Equation 1.40) is retained as a secondorder function with two poles σ
1
= σ
2
=
Introduction 13
σ as
G(s) =
M
1 +sτ +s
2
ττ
d
=
M/ττ
d
(s +σ)
2
, (1.47)
where
σ =
1
2τ
d
=
2
τ
.
There are two folded real poles in the transfer function. This expression describes
the characteristics of the DC/DC converter. The unitstep function response in the
timedomain is
g(t) = M
_
1 −
_
1 +
2t
τ
_
e
−(2t/τ)
_
. (1.48)
The transient process is nearly 2.4 times the time constant τ(2.4τ). The response process is
quick without oscillation. The response waveforminthe time domainis showninFigure 1.4
with τ
d
= 0.25τ.
The impulse interference response is
Δg(t) =
4U
τ
te
−(2t/τ)
, (1.49)
where U is the interference signal. The transient process is still nearly 2.4 times the time
constant, 2.4τ. The response waveform in the time domain is shown in Figure 1.5 with
τ
d
= 0.25τ.
1.1.5.4 Large Damping Time Constant
If the damping time constant is large (i.e., τ
d
> τ/4, ξ > 0.25), the transfer function 1.40 is
a secondorder function with a couple of conjugated complex poles −s
1
and −s
2
in the
lefthand half plane (LHHP) in the sdomain:
G(s) =
M
1 +sτ +s
2
ττ
d
=
M/ττ
d
(s +s
1
)(s +s
2
)
, (1.50)
where s
1
= σ +jω and s
2
= σ −jω,
σ =
1
2τ
d
and ω =
_
4ττ
d
−τ
2
2ττ
d
.
There are a couple of conjugated complex poles −s
1
and −s
2
in the transfer function. This
expression describes the characteristics of the DC/DC converter. The unitstep function
response in the time domain is
g(t) = M
_
1 −e
−t/2τ
d
_
cos ωt −
1
√
4τ
d
/τ −1
sin ωt
__
. (1.51)
The transient response has an oscillation progress with a damping factor σ and the fre
quency ω. The corresponding waveform in the time domain is shown in Figure 1.4 with
τ
d
= 0.5τ, and in Figure 1.6 with τ, 2τ, 5τ, and 10τ.
14 Power Electronics
0
0.4
0.2
0.6
0.8
1
1.2
1.4
1.6
1.8
Time (tor)
M
a
g
n
i
t
u
d
e
(
M
)
t
d
= t
t
d
= 2t
t
d
= 5t
t
d
= 10t
0 5 10 15 20 25 30 35 40 45 50
FIGURE 1.6 Unitstep function responses (τ
d
= τ, 2τ, 5τ, and 10τ).
The impulse interference response is
Δg(t) =
U
√
(τ
d
/τ) −(1/4)
e
−t/2τ
d
sin ωt, (1.52)
where U is the interference signal. The recovery process is a curve with damping factor σ
and frequency ω. The response waveform in the time domain is shown in Figure 1.5 with
τ
d
= 0.5τ, and in Figure 1.7 with τ, 2τ, 5τ, and 10τ.
1.1.6 Fast Fourier Transform
Fast Fourier transform (FFT) [9] is a very versatile method to analyze waveforms. A
periodical function with radian frequency ω can be represented by a series of sinusoidal
functions:
f (t) =
a
0
2
+
∞
n=1
(a
n
cos nωt +b
n
sin nωt), (1.53)
where the Fourier coefﬁcients are
a
n
=
1
π
2π
0
f (t) cos(nωt) d(ωt), n = 0, 1, 2, . . . , ∞ (1.54)
and
b
n
=
1
π
2π
0
f (t) sin(nωt) d(ωt), n = 0, 1, 2, . . . , ∞. (1.55)
Introduction 15
0.4
0.6
0.5
0.7
0.8
0.9
1
1.1
1.2
1.3
Time (tor)
M
a
g
n
i
t
u
d
e
(
M
)
t
d
= t
t
d
= 2t
t
d
= 5t
t
d
= 10t
0 5 10 15 20 25 30 35 40 45 50
FIGURE 1.7 Impulse responses (τ
d
= τ, 2τ, 5τ, and 10τ).
In this case, we call the item with radian frequency ω the fundamental harmonic and the
items with radian frequency nω (n > 1) higherorder harmonics. Draw the amplitudes of
all harmonics in the frequency domain. We obtain the spectrum in an individual peak. The
item a
0
/2 is the DC component.
1.1.6.1 Central Symmetrical Periodical Function
If the periodical function is a central symmetrical periodical function, then all the items
with cosine function disappear. The FFT remains as
f (t) =
∞
n=1
b
n
sin nωt, (1.56)
where
b
n
=
1
π
2π
0
f (t) sin(nωt) d(ωt), n = 1, 2, . . . , ∞. (1.57)
We usually call this function an odd function. In this case, we call the item with radian
frequency ω the fundamental harmonic and the items with radian frequency nω (n > 1)
the higherorder harmonics. Draw the amplitudes of all harmonics in the frequency
domain. We obtain the spectrum in an individual peak. Since it is an odd function, the
DC component is zero.
16 Power Electronics
1.1.6.2 Axial (Mirror) Symmetrical Periodical Function
If the periodical function is an axial symmetrical periodical function, then all the items with
sine function disappear. The FFT remains as
f (t) =
a
0
2
+
∞
n=1
a
n
cos nωt, (1.58)
where a
0
/2 is the DC component and
a
n
=
1
π
2π
0
f (t) cos(nωt) d(ωt), n = 0, 1, 2, . . . , ∞. (1.59)
The item a
0
/2 is the DC component. We usually call this function an even function. In
this case, we call the item with radian frequency ω the fundamental harmonic and the
items with radian frequency nω(n > 1) higherorder harmonics. Draw the amplitudes of
all harmonics in the frequency domain. We obtain the spectrumin an individual peak. Since
it is an even function, the DC component is usually not zero.
1.1.6.3 Nonperiodical Function
The spectrum of a periodical function in the time domain is a discrete function in the
frequency domain. If a function is a nonperiodical function in the time domain, it is possibly
represented by Fourier integration. The spectrumis a continuous function in the frequency
domain.
1.1.6.4 Useful Formulae and Data
Some trigonometric formulae are useful for FFT:
sin
2
x +cos
2
x = 1, sin x = cos
_
π
2
−x
_
,
sin x = −sin(−x), sin x = sin(π −x),
cos x = cos(−x), cos x = −cos(π −x),
d
dx
sin x = cos x,
d
dx
cos x = −sin x,
sin x dx = −cos x,
cos x dx = sin x,
sin(x ±y) = sin x cos y ±cos x sin y,
cos(x ±y) = cos x cos y ∓sin x sin y,
sin 2x = 2 sin x cos x,
cos 2x = cos
2
x −sin
2
x.
Introduction 17
Some values corresponding to the special angles are usually used:
sin
π
12
= sin 15
◦
= 0.2588, cos
π
12
= cos 15
◦
= 0.9659,
sin
π
8
= sin 22.5
◦
= 0.3827, cos
π
8
= cos 22.5
◦
= 0.9239,
sin
π
6
= sin 30
◦
= 0.5, cos
π
6
= cos 30
◦
=
√
3
2
= 0.866,
sin
π
4
= sin 45
◦
=
√
2
2
= 0.7071, cos
π
4
= cos 45
◦
=
√
2
2
= 0.7071,
tan
π
12
= tan 15
◦
= 0.2679, tan
π
8
= tan 22.5
◦
= 0.4142,
tan
π
6
= tan 30
◦
=
√
3
3
= 0.5774, tan
π
4
= tan 45
◦
= 1,
tan x =
1
co tan x
, tan x = co tan
_
π
2
−x
_
.
1.1.6.5 Examples of FFT Applications
Example 1.3
An oddsquare waveform is shown in Figure 1.8. Find FFT, HF up to seventh order, THD, and
WTHD.
SOLUTION
The function f (t ) is
f (t ) =
⎧
⎨
⎩
1, 2nπ ≤ ωt < (2n +1)π,
−1, (2n +1)π ≤ ωt < 2(n +1)π.
(1.60)
The Fourier coefﬁcients are
b
n
=
1
π
2π
0
f (t ) sin(nωt ) d(ωt ) =
2
nπ
nπ
0
sinθ dθ = 2
1 −(−1)
n
nπ
2p 0
1
p
wt
FIGURE 1.8 Awaveform.
18 Power Electronics
and
b
n
=
4
nπ
, n = 1, 3, 5, . . . , ∞. (1.61)
Finally, we obtain
F(t ) =
4
π
∞
n=1
sinnωt
n
, n = 1, 3, 5, . . . , ∞. (1.62)
The fundamental harmonic has amplitude 4/π. If we consider the higherorder harmonics up
to the seventh order, that is, n = 3, 5, 7, the HFs are
HF
3
=
1
3
, HF
5
=
1
5
, and HF
7
=
1
7
.
The THD is
THD =
_
∞
n=2
V
2
n
V
1
=
_
_
1
3
_
2
+
_
1
5
_
2
+
_
1
7
_
2
= 0.41415. (1.63)
The WTHD is
WTHD =
_
∞
n=2
(V
2
n
/n)
V
1
=
_
_
1
3
_
3
+
_
1
5
_
3
+
_
1
7
_
3
= 0.219. (1.64)
Example 1.4
An evensquare waveform is shown in Figure 1.9. Find FFT, HF up to the seventh order, THD, and
WTHD.
The function f (t ) is
f (t ) =
⎧
⎨
⎩
1, (2n −0.5)π ≤ ωt < (2n +0.5)π,
−1, (2n +0.5)π ≤ ωt < (2n +1.5)π.
(1.65)
The Fourier coefﬁcients are
a
0
= 0,
a
n
=
1
π
2π
0
f (t ) cos(nωt ) d(ωt ) =
4
nπ
nπ/2
0
cos θ dθ =
4sin(nπ/2)
nπ
,
2p 0
1
p
wt
FIGURE 1.9 Evensquare waveform.
Introduction 19
and
a
n
=
4
nπ
sin
nπ
2
, n = 1, 3, 5, . . . , ∞. (1.66)
The item sin(nπ/2) is used to deﬁne the sign. Finally, we obtain
F(t ) =
4
π
∞
n=1
sin
nπ
2
cos(nωt ), n = 1, 3, 5, . . . , ∞. (1.67)
The fundamental harmonic has amplitude 4/π. If we consider the higherorder harmonics up
to the seventh order, that is, n = 3, 5, 7, the HFs are
HF
3
=
1
3
, HF
5
=
1
5
, and HF
7
=
1
7
.
The THD is
THD =
_
∞
n=2
V
2
n
V
1
=
_
_
1
3
_
2
+
_
1
5
_
2
+
_
1
7
_
2
= 0.41415. (1.68)
The WTHD is
WTHD =
_
∞
n=2
(V
2
n
/n)
V
1
=
_
_
1
3
_
3
+
_
1
5
_
3
+
_
1
7
_
3
= 0.219. (1.69)
Example 1.5
An oddwaveformpulse with pulse width x is shown in Figure 1.10. Find FFT, HF up to the seventh
order, THD, and WTHD.
The function f (t ) is in the period −π to +π:
f (t ) =
⎧
⎪
⎨
⎪
⎩
1,
π −x
2
≤ ωt <
π +x
2
,
−1, −
π +x
2
≤ ωt < −
π −x
2
.
(1.70)
2p p/2 p 0
1
x
wt
FIGURE 1.10 Oddwaveform pulse.
20 Power Electronics
The Fourier coefﬁcients are
b
n
=
1
π
2π
0
f (t ) sin(nωt ) d(ωt ) =
2
nπ
n[(π+x)/2]
n[(π−x)/2]
sinθ dθ = 2
cos[n(π −x)/2] −cos[n(π +x)/2]
nπ
= 2
2cos[n(π −x)/2]
nπ
=
4sin(nπ/2) sin(nx/2)
nπ
,
or
b
n
=
4
nπ
sin
nπ
2
sin
nx
2
, n = 1, 3, 5, . . . , ∞. (1.71)
Finally, we obtain
F(t ) =
4
π
∞
n=1
sin(nωt )
n
sin
nπ
2
sin
nx
2
, n = 1, 3, 5, . . . , ∞. (1.72)
The fundamental harmonic has amplitude (4/π) sin(x/2). If we consider the higherorder
harmonics up to the seventh order, that is, n = 3, 5, 7, the HFs are
HF
3
=
sin(3x/2)
3sin(x/2)
, HF
5
=
sin(5x/2)
5sin(x/2)
, and HF
7
=
sin(7x/2)
7sin(x/2)
.
The values of the HFs should be absolute values.
If x = π, the THD is
THD =
_
∞
n=2
V
2
n
V
1
=
_
_
1
3
_
2
+
_
1
5
_
2
+
_
1
7
_
2
= 0.41415. (1.73)
The WTHD is
WTHD =
_
∞
n=2
(V
2
n
/n)
V
1
=
_
_
1
3
_
3
+
_
1
5
_
3
+
_
1
7
_
3
= 0.219. (1.74)
Example 1.6
A ﬁvelevel odd waveform is shown in Figure 1.11. Find FFT, HF up to the seventh order, THD, and
WTHD.
The function f (t ) is in the period −π to +π:
f (t ) =
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
2,
π
3
≤ ωt <
2π
3
,
1,
π
6
≤ ωt <
π
3
,
2π
3
≤ ωt <
5π
6
,
0, other,
−1, −
5π
6
≤ ωt < −
2π
3
, −
π
3
≤ ωt < −
π
6
,
−2, −
2π
3
≤ ωt < −
π
3
.
(1.75)
Introduction 21
p
5p/6
2p/3 p/6
p/3
2p 0
1
2
wt
FIGURE 1.11 Fivelevel odd waveform.
The Fourier coefﬁcients are
b
n
=
1
π
2π
0
f (t ) sin(nωt ) d(ωt ) =
2
nπ
⎛
⎜
⎝
5nπ/6
nπ/6
sinθ dθ +
2nπ/3
nπ/3
sinθ dθ
⎞
⎟
⎠
=
2
nπ
__
cos
nπ
6
−cos
5nπ
6
_
+
_
cos
nπ
3
−cos
2nπ
3
__
=
4
nπ
_
cos
nπ
6
+cos
nπ
3
_
or
b
n
=
4
nπ
_
cos
nπ
6
+cos
nπ
3
_
, n = 1, 3, 5, . . . , ∞. (1.76)
Finally, we obtain
F(t ) =
4
π
∞
n=1
sin(nωt )
n
_
cos
nπ
6
+cos
nπ
3
_
, n = 1, 3, 5, . . . , ∞. (1.77)
The fundamental harmonic has amplitude 2/π(1 +
√
3). If we consider the higherorder
harmonics up to the seventh order, that is, n = 3, 5, 7, the HFs are
HF
3
=
2
3(1 +
√
3)
= 0.244, HF
5
=
√
3 −1
5(1 +
√
3)
= 0.0536, and
HF
7
=
√
3 −1
7(1 +
√
3)
= 0.0383.
The values of the HFs should be absolute values.
The THD is
THD =
_
∞
n=2
V
2
n
V
1
=
¸
¸
¸
_
∞
n=2
HF
2
n
=
_
0.244
2
+0.0536
2
+0.0383
2
= 0.2527. (1.78)
22 Power Electronics
The WTHD is
WTHD =
_
∞
n=2
(V
2
n
/n)
V
1
=
¸
¸
¸
_
∞
n=2
HF
2
n
n
=
_
0.244
2
3
+
0.0536
2
5
+
0.0383
2
7
= 0.1436. (1.79)
1.2 AC/DC Rectifiers
AC/DC rectiﬁers [3] have been used in industrial applications for a long time now. Before
the 1960s, most power AC/DC rectiﬁers were constructed using mercuryarc rectiﬁers.
Then the large power silicon diode and the thyristor (or SCR—siliconcontrolled rectiﬁer)
were successfully developed in the 1960s. Since then, all power AC/DCrectiﬁers have been
constructed using power silicon diodes and thyristors.
Using a power silicon diode, we can construct uncontrolled diode rectiﬁers. Using a
power thyristor, we can construct controlled SCR rectiﬁers since the thyristor is usually
triggered at ﬁring angle α, which is variable. If the ﬁring angle α = 0, the characteristics of
the controlled SCR rectiﬁer will return to those of the uncontrolled diode rectiﬁer. Research
on the characteristics of the uncontrolled diode rectiﬁer enables designers to get an idea of
the characteristics of the controlled SCR rectiﬁer.
Asinglephase halfwave diode rectiﬁer is showninFigure 1.12. The loadcanbe a resistive
load, inductive load, capacitive load, or back electromotive force (emf) load. The diode can
be conducting when current ﬂows from the anode to the cathode, and the corresponding
voltage applied across the diode is deﬁned as positive. However, the diode is blocked when
the voltage applied across the diode is negative, and no current ﬂows through it. Therefore,
the singlephase halfwave diode rectiﬁer supplying different load has different output
voltage waveform.
There are three important aims for this book:
• Clearing up the historic problems.
• Introducing updated circuits.
• Investigating PFC methods.
1.2.1 Historic Problems
Rectiﬁer circuits are easily understood. The input power supply can be singlephase, three
phase, and multiphase sinewave voltages. Usually, the more phases that an input power
supplies to a circuit, the simpler the circuit operation. The most difﬁcult analysis occurs in
v = 2V sin wt
L
o
a
d
D
FIGURE 1.12 Singlephase halfwave diode rectiﬁer.
Introduction 23
the simplest circuit. Although a singlephase diode rectiﬁer circuit is the simplest circuit,
analysis of it has not been discussedin any great detail. Infact, the results presentedin many
recently published papers and books have given the wrong idea.
1.2.2 Updated Circuits
Manyupdatedcircuits andcontrol methods have beendevelopedinthe last tenyears. How
ever, most of these updated circuits and control methods have yet to appear in dedicated
books.
1.2.3 Power Factor Correction Methods
Power factor correction (PFC) methods have attracted the most attention in recent years.
Many papers on PFChave been published but, as above, there is a distinct lack of dedicated
textbooks on this subject.
1.3 DC/DC Converters
DC/DCconversiontechnology[5] is a vast subject area. It developedveryfast andachieved
much. There are believed to be more than 500 existing topologies of DC/DC converters
according to current statistics. DC/DC converters have been widely used in industrial
applications such as DC motor drives, communication equipment, mobile phones, and
digital cameras. Many newtopologies have been developed in the recent decade. They will
be systematically introduced in this book.
Mathematical modeling is the historic problem accompanying the development of
DC/DCconversion technology. Fromthe 1940s onward, many scholars conductedresearch
in this area and offered various mathematical modelings and control methods. We will
discuss these problems in detail.
Most DC/DC converters have at least one pump circuit. For example, the buck–boost
converter shown in Figure 1.13 has the pump circuit S–L. When the switch S is on, the
inductor L absorbs energy from the source V
1
. When the switch S is off, the inductor L
releases the stored energy to the load and to charge the capacitor C.
From the example, we recognize that all energy obtained by the load must be a part of
the energy stored in the inductor L. Theoretically, the energy transferred to the load looks
no limit. In any particular operation, the energy rate cannot be very high. Consequently,
power losses will increase sharply and the power transfer efﬁciency will largely decrease.
C
+
–
R L
D
S
+
–
i
1
i
2
V
2
V
1
i
L
V
D
V
C
i
C
+
–
FIGURE 1.13 Buck–boost converter.
24 Power Electronics
The following three important points will be emphasized in this book:
• The introduction of updated circuits.
• The introduction of new concepts and mathematical modeling.
• Checking the power rates.
1.3.1 Updated Converter
The voltagelift (VL) conversion technique is widely used in electronic circuit design. Using
this technique opened a the ﬂood gates for designing DC/DC converters with in new
topologies being developed in the last decade.
Furthermore, the superlift (SL) technique and the ultralift (UL) technique have also
been created. Both techniques facilitate on increase in the voltage transfer gains of DC/DC
converters with the SL technique being the most outstanding with regard to the DC/DC
conversion technology.
1.3.2 New Concepts and Mathematical Modeling
DC/DC converters are an element in an energy control system. In order to obtain satisfac
tory performance of the energy control system, it is necessary to know the mathematical
modeling of the DC/DC converter used. Traditionally, the modeling of power DC/DC
converters was derived from the impedance voltagedivision method. The idea is that the
inductor impedance is sL and the inductor impedance is 1/sC, where s is the Laplace oper
ator. The output voltage is the voltage divided by the impedance calculation. Actually,
it successfully solves the problem of fundamental DC/DC converters. The transfer func
tion of a DC/DC converter has an order number equal to the number of energystorage
elements. A DC/DC converter with two inductors and two capacitors has a fourthorder
transfer function. Even more, a DC/DC converter with four inductors and four capacitors
must have an eighthorder transfer function. It is hard to believe that it can be used for
industrial applications.
1.3.3 Power Rate Checking
How can a large power be used in an energy system with DC/DC converters? This rep
resents a very sensitive problem for industrial applications. DC/DC converters are quite
different from transformers and AC/DC rectiﬁers. Their output power is limited by the
pump circuit power rate.
The power rate of an inductor pump circuit depends on the inductance, applied current
and current ripple, and switching frequency. The energy transferred by the inductor pump
circuit in a cycle T = 1/f is
ΔE =
L
2
(I
2
max
−I
2
min
). (1.80)
The maximum power that can be transferred is
P
max
= f ΔE =
fL
2
(I
2
max
−I
2
min
). (1.81)
Therefore, when designing an energy system with a DC/DC converter, we have to
estimate the power rate.
Introduction 25
1.4 DC/AC Inverters
DC/AC inverters [1,2] were not widely used in industrial applications before the 1960s
because of their complexity and cost. However, they were used in most fractional horse
power AC motor drives in the 1970s because AC motors have the advantage of lower cost
when compared to DC motors, were smaller in size, and were maintenance free. In the
1980s, because of semiconductor development, more effective devices such as IGBT and
MOSFET were produced, and DC/AC inverters started to be widely applied in industrial
applications. To date, DC/AC conversion techniques can be sorted into two categories:
pulsewidth modulation (PWM) and multilevel modulation (MLM). Each category has
many circuits to implement the modulation. Using PWM, we can design various inverters
such as voltagesource inverters (VSI), currentsource inverters (CSI), impedancesource
inverters (ZSI), and multistage PWM inverters. A singlephase halfwave PWM is shown
in Figure 1.14.
The PWM method is suitable for DC/AC conversion since the input voltage is usu
ally a constant DC voltage (DC link). The pulsephase modulation (PPM) method is also
possible, but is less convenient. The pulseamplitude modulation (PAM) method is not
suitable for DC/AC conversion since the input voltage is usually a constant DC voltage.
PWM operation has all the pulses’ leading edge starting from the beginning of the pulse
period, and their trailer edge is adjustable. The PWM method is a fundamental technique
for many types of PWM DC/AC inverters such as VSI, CSI, ZSI, and multistage PWM
inverters.
Another group of DC/AC inverters are the multilevel inverters (MLI). These inverters
were invented in the late 1970s. The early MLIs are constructed using diodeclamped and
capacitorclamped circuits. Later, various MLIs were developed.
Three important points will be examined in this book:
• Sorting the existing inverters.
• Introducing updated circuits.
• Investigating softswitching methods.
i
i
i
O
V
d
V
d/2
V
d/2
S
–
S
+
D
+
D
–
–
+
v
O
C
+
a
N
C
–
FIGURE 1.14 Singlephase halfwave PWM VSI.
26 Power Electronics
1.4.1 Sorting Existing Inverters
Since a large number of inverters exist, we have to sort them systematically. Some circuits
have not been deﬁned with an exact title and thus mislead readers’ understanding as to the
particular function.
1.4.2 Updated Circuits
Many updated DC/AC inverters have been developed in the last decade but have not yet
been introduced into textbooks. This book seeks to redress that point and show students
the new methods.
1.4.3 SoftSwitching Methods
The softswitching technique has been widely used in switching circuits for a long time
now. It effectively reduce the power losses of equipment and increases the power transfer
efﬁciency. Afew softswitching technique methods will be introduced into this book.
1.5 AC/AC Converters
AC/AC converters [10] were not very widely used in industrial applications before
the 1960s because of their complexity and cost. They were used in heating systems
for temperature control and in light dimmers in cinemas, theaters, and nightclubs, or
in bedroom night dimmers for light color and brightening control. The early AC/AC
converters were designed by the voltageregulation (VR) method. A typical singlephase
VR AC/AC converter is shown in Figure 1.15.
VR AC/AC converters have been successfully used in heating and lightdimming
systems. One disadvantage is that the output AC voltage of VR AC/AC converters is a
heavily distorted waveform with a poor THD and PF. Other disadvantages are that the
+
+
–
–
v
s
= 2V
s
sin wt
v
O
v
T1
i
s
i
g1
i
g2
T
2
T
1
i
O
L
o
a
d
FIGURE 1.15 Singlephase VR AC/AC converter.
Introduction 27
output voltage is constantly lower than the input voltage and the output frequency is not
adjustable.
Cycloconverters and matrix converters can change the output frequency, but the output
voltage is also constantly lower than the input voltage. Their THD and PF are also very
poor.
DCmodulated (DM) AC/AC converters can easily give an output voltage higher than
the input voltage, which will be discussed in this book. In addition, the DM method can
successfully improve THD and PF.
1.6 AC/DC/AC and DC/AC/DC Converters
AC/DC/AC and DC/AC/DC converters are designed for special applications. In recent
years, it has been realised that renewable energy sources and distributed generations (DG)
need to be developed rapidly because fossil energy sources (coal, oil, gas, and so on) will
soon be exhausted. Sources such as solar panels, photovoltaic cells, fuel cells, and wind
turbines have unstable DCand/or ACoutput voltages. Theyare usuallypart of a microgrid.
It is necessary to use special AC/DC/ACand DC/AC/DCconverters to link these sources
to the general buss inside the microgrid.
Wind turbines have singlephase or multiphase AC output voltages with variable ampli
tude and frequency since the wind speed varies constantly. As it is difﬁcult to use these
unstable AC voltages for any application, we need to use an AC/DC/AC converter to con
vert them to a suitable AC voltage (singlephase or multiphase) with stable amplitude and
frequency.
Solar panels have DC output voltages with variable amplitude due to the variations of
available sunlight. As it is difﬁcult to use these unstable DCvoltages for any application, we
need to use a DC/AC/DC converter to convert them to a suitable DC voltage with stable
amplitude and frequency.
Homework
1.1. Aload Z with a resistance R = 10 Ω, an inductance L = 10 mH, and a capacitance
C = 1000 μF in series connection is supplied by a singlephase AC voltage with
frequency f = 60 Hz. Calculate the impedance Z and the phase angle φ.
1.2. Aload Z with resistance R = 10 Ωand inductance L = 10 mH in series connection
is supplied by a singlephase AC voltage with frequency f = 60 Hz. Calculate the
impedance Z, the phase angle φ, and the time constant τ.
1.3. Aload Z with resistance R = 10 Ω and capacitance C = 1000 μF in series connec
tion is supplied by a singlephase ACvoltage with frequency f = 60 Hz. Calculate
the impedance Z, the phase angle φ, and the time constant τ.
1.4. Refer to Question 1.1. If the AC supply voltage is 240 V (rms) with f = 60 Hz,
calculate the circuit current, and the corresponding apparent power S, real power
P, reactive power Q, and PF.
1.5. Aﬁvelevel oddwaveform is shown in Figure 1.16.
28 Power Electronics
The central symmetrical function f (t) is in the period −π to +π:
f (t) =
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
2E,
3π
8
≤ ωt <
5π
8
,
E,
π
8
≤ ωt <
3π
8
,
5π
8
≤ ωt <
7π
8
,
0, other,
−E, −
7π
8
≤ ωt < −
5π
8
, −
3π
8
≤ ωt < −
π
8
,
−2E, −
5π
8
≤ ωt < −
3π
8
.
Consider the harmonics up to the seventh order and calculate the HFs, THD, and WTHD.
7p/8 3p/8
5p/8 p/8 p
2E
E
0
f (t)
wt
FIGURE 1.16 Fivelevel odd waveform.
References
1. Luo, F. L., Ye, H., and Rashid, M. H. 2005. Digital Power Electronics and Applications. Boston:
Academic Press.
2. Mohan, N., Undeland, T. M., and Robbins, W. P. 2003. Power Electronics: Converters, Applications
and Design (3rd edition). New York: Wiley.
3. Rashid, M. H. 2004. Power Electronics: Circuits, Devices and Applications (3rd edition). Englewood
Cliffs, NJ: PrenticeHall.
4. Luo, F. L. and Ye, H. 2007. DCmodulated singlestage power factor correction AC/AC
converters. Proceedings of ICIEA 2007 Harbin, China, pp. 1477–1483.
5. Luo, F. L. and Ye, H. 2004. Advanced DC/DC Converters. Boca Raton: CRC Press.
6. Luo, F. L. and Ye, H. 2005. Energy factor and mathematical modeling for power DC/DC
converters. IEE EPA Proceedings, 152(2), 191–198.
7. Luo, F. L. and Ye, H. 2007. Small signal analysis of energy factor and mathematical modeling
for power DC/DC converters. IEEE Transactions on Power Electronics, 22(1), 69–79.
8. Luo, F. L. and Ye, H. 2006. Synchronous and Resonant DC/DC Conversion Technology, Energy Factor
and Mathematical Modeling. Boca Raton: Taylor & Francis.
9. Carlson A. B. 2000. Circuits. Paciﬁc Grove, CA: Brooks/Cole.
10. Rashid, M. H. 2007. Power Electronics Handbook (2nd edition). Boston: Academic Press.
2
Uncontrolled AC/DC Converters
Most electronic equipment and circuits require DC sources for their operation. Dry cells
and rechargeable batteries can be used for these applications but they only offer limited
power and unstable voltage. The most useful DC sources are AC/DC converters [1]. The
technology of AC/DCconversion is a wide subject area covering research investigation and
industrial applications. AC/DC converters (usually called rectiﬁers) convert an AC power
supplysource voltage toaDCvoltage load. UncontrolledAC/DCconverters usuallyconsist
of diode circuits. They can be sorted into the following groups [2]:
• Singlephase halfwave rectiﬁers
• Singlephase fullwave rectiﬁers
• Threephase rectiﬁers
• Multipulse rectiﬁers
• PFC rectiﬁers
• Pulsewidthmodulated boosttype rectiﬁers.
Since some of the theoretical analysis andcalculationresults inthis bookare different from
that of some published papers and books, the associated underlying historical problems
will be brought to the attention of the reader by way of ADVICE sections.
2.1 Introduction
The input of a diode rectiﬁer is AC voltage, which can be either a single or threephase
voltage, and is usually a pure sinusoidal wave. A singlephase input voltage v(t) can be
expressed as
v(t) =
√
2V sin ωt = V
m
sin ωt, (2.1)
where v(t) is the instantaneous input voltage, V the rms value, V
m
the amplitude, and ωthe
angular frequency where ω = 2πf ( f is the supply frequency). Usually, the input current i(t)
is a pure sinusoidal wave with a phase shift angle φ if it is not distorted, and is expressed as
i(t) =
√
2I sin(ωt −φ) = I
m
sin(ωt −φ), (2.2)
where i(t) is the instantaneous input current, I the rms value, I
m
the amplitude, and φ the
phase shift angle. In this case, we deﬁne the PF as
PF = cos φ. (2.3)
29
30 Power Electronics
If the input current is distorted, it consists of harmonics. Its fundamental harmonic can be
expressed as in Equation 1.17 and the DPF is deﬁned in Equation 1.18. PF is measured as
shown in Equation 1.19 and the THD is deﬁned as in Equation 1.20 [3, 4].
When a pure DC voltage has no ripple, it is called a ripplefree DC voltage. Otherwise,
DCvoltage is distortedandits rms value is V
d−rms
. For a distortedDCvoltage, its rms value
V
d−rms
is constantly higher than its average value V
d
. The RF is deﬁned in Equation 1.24
and the FF is deﬁned in Equation 1.25.
2.2 SinglePhase HalfWave Converters
A singlephase halfwave diode rectiﬁer consists of a singlephase AC input voltage and
one diode [5]. While it is the simplest rectiﬁer, its analysis is the most complex. This rectiﬁer
can supply various loads as described in the following subsections.
2.2.1 R Load
Asinglephase halfwave diode rectiﬁer with R load is shown in Figure 2.1a, and the input
voltage, input current, and output voltage waveforms are shown in Figures 2.1b–d, respec
tively. The output voltage is similar to the input voltage in the positive halfcycle and zero
in the negative halfcycle.
The output average voltage is
V
d
=
1
2π
π
0
√
2V sin ωt d(ωt) =
2
√
2
2π
V = 0.45 V. (2.4)
The output rms voltage is
V
d−rms
=
¸
¸
¸
¸
_
1
2π
π
0
(
√
2V sin ωt)
2
d(ωt) = V
¸
¸
¸
¸
_
1
π
π
0
(sin α)
2
dα =
1
√
2
V = 0.707 V. (2.5)
The output average and rms currents are
I
d
=
V
d
R
=
√
2
π
V
R
= 0.45
V
R
, (2.6)
I
d−rms
=
V
d−rms
R
=
1
√
2
V
R
= 0.707
V
R
. (2.7)
The FF, RF, and PF of the output voltage are
FF =
V
d−rms
V
d
=
1/
√
2
√
2/π
=
π
2
= 1.57, (2.8)
RF =
_
FF
2
−1 =
_
_
π
2
_
2
−1 = 1.21, (2.9)
Uncontrolled AC/DC Converters 31
SW
i
v
O
= v
R
D (a)
(b)
(c)
(d)
+
+
–
–
R
÷2V
÷2V
R
p 2p wt
p
2p wt
p 2p wt
v
i
0
0
÷2V
v
O
0
v = ÷2V sinwt
FIGURE 2.1 Singlephase halfwave diode rectiﬁer with R load: (a) circuit, (b) input voltage, (c) input current,
and (d) output voltage.
and
PF =
1
√
2
= 0.707. (2.10)
2.2.2 R–L Load
Asinglephase halfwave diode rectiﬁer withR–Lloadis showninFigure 2.2a, while various
circuit waveforms are shown in Figures 2.2b–d.
It can be seen that the load current ﬂows not only in the positive halfcycle of the supply
voltage, but also in a portion of the negative halfcycle of the supply voltage [6]. The load
inductor SE maintains the load current, and the inductor’s terminal voltage changes so
32 Power Electronics
as to overcome the negative supply and keep the diode forward biased and conducting.
Area A is equal to area B in Figure 2.2c. During diode conduction, the following equation
is available:
L
di
dt
+Ri =
√
2V sin ωt (2.11)
R
0
e
10
e
20
e
20
i
i
iR
B
Voltage
across R
1 cycle
Voltage
across L
L
1 2
(a)
(b)
(c)
(d)
A
Di
DI
wLDi
wt
0
wt
wt
1
wt
2
wt
3
C
D
Voltage
across diode
FIGURE 2.2 Halfwave rectiﬁer with R−L load: (a) circuit, (b) input voltage and current, (c) analysis of input
voltage and current, (d) output voltage.
Uncontrolled AC/DC Converters 33
or
di
dt
+
R
L
i =
√
2V
L
sin ωt.
This is a nonnormalized differential equation. The solution has two parts. The forced
component is determined by
i
F
= e
−(R/L)t
_
√
2V
L
sin ωt
_
e
(R/L)t
dt. (2.12)
If the circuit is blockedduringthe negative halfcycle, thenbysinusoidal steadystate circuit
analysis the forced component of the current is
i
F
=
√
2V sin(ωt −φ)
_
R
2
+(ωL)
2
, (2.13)
where
φ = tan
−1
_
ωL
R
_
. (2.14)
The natural response of such a circuit is given by
i
N
= Ae
−(R/L)t
= Ae
−(t/τ)
with τ =
L
R
. (2.15)
Thus,
i = i
F
+i
N
=
√
2V
Z
sin(ωt −φ) +Ae
−(R/L)t
, (2.16)
where
Z =
_
R
2
+(ωL)
2
. (2.17)
The constant A is determined by substitution in Equation 2.16 of the initial condition i = 0
at t = 0, giving
A =
√
2V
Z
sin φ.
Thus,
i =
√
2V
Z
_
sin(ωt −φ) +e
−(R/L)t
sin φ
_
. (2.18)
We deﬁne the extinction angle β where the current becomes zero. Therefore,
i = 0, β ≤ ωt < 2π. (2.19)
The current extinction angle β is determined by the load impedance and can be solved
from Equation 2.18 when i = 0 and ωt = β,
sin(β −φ) = −e
−(Rβ/ωL)
sin φ. (2.20)
34 Power Electronics
sin f, e
–
b/wt
sin(b–f)
b
Operating point
–sin f, e
–
b/wt
FIGURE 2.3 Determination of extinction angle β.
This is a transcendental equation with an unknown value of β (see Figure 2.3). The term
sin(β −φ) is a sinusoidal function and the terme
−(Rβ/ωL)
sin φ is an exponentially decaying
function; the operating point of β is the intersection of sin(β −φ) and those terms. The
value of β can be obtained by using MATLAB
simulation and can be solved by numerical
techniques such as iterative methods.
2.2.2.1 Graphical Method
Using MATLAB
to solve Equation 2.20, the resultant values of β for the corresponding
values of φ are plotted as a graph shown in Figure 2.4. It can be observed that the graph
commences at 180
◦
(or πradians) onthe β(x) axis and, for small values of φ, the characteristic
is linear,
β ≈ π +φ
However, for large values of φ, the corresponding value of β tends to be
β > π +φ
with a terminal value of 2π (or 360
◦
) for purely inductive load.
ADVICE
If L > 0, β > π +φ. Using the graph in Figure 2.4, a highly accurate result cannot be
obtained. (Historic problem: β = π +φ.)
2.2.2.2 Iterative Method 1
The operating point setting: If β ≥ π +φ. Let starting point β = π +φ.
L1: Calculate x = sin(β −φ).
Calculate y = −e
−(Rβ/ωL)
sin φ.
If x = y, then β is the correct value, END.
Uncontrolled AC/DC Converters 35
180
0
10
20
30
40
50
60
70
80
90
100
200 240 280 320 360 400
b°
f°
FIGURE 2.4 β versus φ.
If x < y, then increment β and return to L1.
If x > y, then decrement β and return to L1.
Example 2.1
A singlephase halfwave diode rectiﬁer operates from a supply of V = 240V, 50Hz to a load of
R = 10Ω and L = 0.1H. Determine the extinction angle β using iterative method 1.
SOLUTION
From Equation 2.20, φ = tan
−1
(ωL/R) = 72.34
◦
.
Then, letting β
1
= π +φ = 252.34
◦
:
Step β (deg) x = sin(β −φ) y = e
−(Rβ/ωL)
sinφ x : y
1 252.34 0 0.2345 <
2↑ 260 −0.1332 0.2248 <
3↑ 270 −0.3033 0.2126 >
4↓ 265 −0.2191 0.2186 ≈
5↓ 264 −0.2020 0.2198 <
6↓ 266 −0.2360 0.2174 >
Therefore, to satisfy Equation 2.20, the best value is β = 265
◦
.
2.2.2.3 Iterative Method 2
Let β
n
= π +φ.
36 Power Electronics
L1: Calculate x = sin(β −φ).
Calculate y = e
−(Rβ/ωL)
sin φ.
Let x = y and β
n+1
= (sin
−1
y) +π +φ.
If β
n+1
= β
n
then END. Else
Choose β
n
= β
n+1
and return to L1.
The reader is referred to Homework Question 2.2.
The average value of the rectiﬁed current can be obtained by
v
d
= v
R
+v
L
=
√
2V sin ωt,
β
0
v
R
d(ωt) +
β
0
v
L
d(ωt) =
β
0
√
2V sin ωt d(ωt),
R
β
0
i(t) d(ωt) =
√
2V(1 −cos β),
I
d
=
1
2π
β
0
i(t) d(ωt) =
√
2V
2πR
(1 −cos β).
(2.21)
The average output voltage is given by
V
d
=
√
2V
2π
(1 −cos β). (2.22)
The output rms voltage is given by
V
d−rms
=
¸
¸
¸
¸
_
1
2π
β
0
(
√
2V sin ωt)
2
d(ωt) = V
¸
¸
¸
¸
_
1
π
β
0
(sin α)
2
dα
= V
¸
¸
¸
¸
_
1
π
β
0
_
1 −cos 2α
2
_
dα = V
_
1
π
_
β
2
−
sin 2β
4
_
.
(2.23)
The FF and RF of the output voltage are
FF =
V
d−rms
V
d
=
_
(1/π)[(β/2) −(sin 2β/4)]
(
√
2/2π)(1 −cos β)
=
_
π
2
_
2β −sin 2β
1 −cos β
, (2.24)
RF =
_
FF
2
−1 =
_
π
2
2β −sin 2β
(1 −cos β)
2
−1. (2.25)
Uncontrolled AC/DC Converters 37
2.2.3 R–L Circuit with Freewheeling Diode
The circuit in Figure 2.2a, which has an R–L load, is characterized by discontinuous and
high ripple current. Continuous load current can result when a diode is added across the
load as shown in Figure 2.5a.
2V sin wt
v = ÷
2V
÷
2V
÷
SW
R
i
0
i
D
v
0
v
R
D
1
(a)
(b)
D
2
L
V
L
v
v
0
i
0
I '
0p
I '
0p
I
02p
I
02p
i
0
0 2p wt
0 p
p
2p wt
0 p 2p wt
np (n + 1) p (n + 2) p wt
+
+
–
–
+
–
i
i
D
i
i
D
FIGURE 2.5 Halfwave rectiﬁer with R−L load plus freewheeling diode. (a) Circuit and (b) waveforms.
38 Power Electronics
The diode prevents the voltage across the load from reversing during the negative half
cycle of the supply voltage. When diode D
1
ceases to conduct at zero volts, diode D
2
provides an alternative freewheeling path as indicated by the waveforms in Figure 2.5b.
After alarge number of supplycycles, steadystate loadcurrent conditions are established,
and the load current is given by
i
0
=
√
2V
Z
sin(ωt −φ) +Ae
−(R/L)t
. (2.26)
Also,
i
0

t=0
= I
0

t=2π
. (2.27)
Substitution of the initial conditions of Equation 2.27 into Equation 2.26 yields
i
0
=
√
2V
Z
sin(ωt −φ) +
_
I
0−2π
+
√
2V
Z
sin φ
_
e
−(R/L)t
. (2.28)
At ωt = π, diode D
2
begins to conduct, the input current i falls instantaneously to zero, and
from Equation 2.28,
I
0−π
= i
0
¸
¸
t=π/ω
=
√
2V
Z
sin(π −φ) +
_
I
0−2π
+
√
2V
Z
sin φ
_
e
−(πR/ωL)
. (2.29)
Duringthe succeedinghalfcycle, v
0
is zero. The SEinthe inductor is dissipatedbycurrent
i
D
ﬂowing in the R−L−D
2
mesh. Thus
i
0
= i
D
= I
0−π
e
−(R/L)(t−π/ω)
(2.30)
at ωt = 2π. Therefore, v, and hence v
0
, becomes positive.
i
0
¸
¸
t=2π/ω
= I
0−π
e
−(R/L)(t−π/ω)
= I
0

ωt=2π
. (2.31)
Thus, from Equations 2.29 and 2.31,
√
2V
Z
sin φ +
_
I
0−2π
+
√
2V
Z
sin φ
_
e
−(πR/ωL)
= I
0−2π
e
πR/ωL
(2.32)
so that
I
0−2π
=
(
√
2V/Z) sin φ(1 +e
−(πR/ωL)
)
e
πR/ωL
−e
−(πR/ωL)
. (2.33)
2.2.4 An R–L Load Circuit with a Back Emf
A singlephase halfwave rectiﬁer to supply an R–L load with a back emf V
c
is shown in
Figure 2.6a. The corresponding waveforms are shown in Figure 2.6b.
Uncontrolled AC/DC Converters 39
i D
R
V
D
+ –
V
L
+
+ –
+
V
R
+
–
–
V
0
V
c
–
L
2V sin wt v = ÷
(a)
(b)
2V ÷
v
1.0
m
1.0
m
i
0
0
0
a
a+g
a+g
v
0
Z
i
Z
i
Z
cos f
sin(a+g)
m
p wt 2p
a
p wt 2p
a
a+g p
wt 2p
0 a
a+g p
wt 2p
f
g
Be
–(R/L)t
2V ÷
2V ÷
2V ÷
2V ÷
FIGURE 2.6 Halfwave rectiﬁer with R−L load plus a back emf. (a) Circuit and (b) waveforms.
40 Power Electronics
The effect of introducing a back electromotive force V
c
into the load circuit of a halfwave
rectiﬁer is investigated in this section. This is the situation that would arise if such a circuit
were employed to charge a battery or to excite a DC motor armature circuit.
The current component due to the AC source is
i
SF
=
√
2V
Z
sin(ωt −φ). (2.34)
The component due to the direct emf is
i
cF
=
−V
c
R
. (2.35)
The natural component is
i
N
= Ae
−(R/L)t
. (2.36)
The total current in the circuit is the sum of these three components:
i =
√
2V
Z
sin(ωt −φ) −
V
c
R
+Ae
−(R/L)t
, α < ωt < α +γ, (2.37)
where α is the angle at which conduction begins and γ is the conduction angle. As may be
seen from the voltage curve in Figure 2.6b,
sin α =
V
c
√
2V
= m. (2.38)
At ωt = α, i = 0 so that from Equation 2.37
A =
_
V
c
R
−
√
2V
Z
sin(α −φ)
_
e
αR/ωL
. (2.39)
Also
R = Zcos φ. (2.40)
Substituting Equations 2.38 through 2.40 into Equation 2.37 yields
Z
√
2V
i = sin(ωt −φ) −
_
m
cos φ
−Be
−(R/L)t
_
, α < ωt < α +γ, (2.41)
where
B =
_
m
cos φ
−sin(α −φ)
_
e
αR/ωL
, ωt = α. (2.42)
The terms onthe righthandside of Equation2.41 maybe representedseparatelyas shown
in Figure 2.6b. At the end of the conduction period,
i = 0, ωt = α +γ. (2.43)
Uncontrolled AC/DC Converters 41
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
0 40 80 120 160 200
f
=
9
0
°
f
=
7
5
°
f
=
6
0
°
f
=
4
5
°
f
=
3
0
°
f
=
1
5
°
f
=
0
°
240 280 320 360
0 m
g
FIGURE 2.7 m versus γ referring to φ.
Substituting Equation 2.43 in Equation 2.41 yields
(m/cos φ) −sin(α +γ −φ)
(m/cos φ) −sin(α −φ)
= e
−γ/ tan φ
. (2.44)
We obtain
e
−γ/ωτ
=
(m/cos φ) −sin(η +γ −φ)
(m/cos φ) −sin(η −φ)
. (2.45)
Solve for conduction angle γ using suitable iterative techniques. For practicing design
engineers, a quick reference graph of m–φ–γ is given in Figure 2.7.
Example 2.2
A singlephase halfwave diode rectiﬁer operates from a supply of V = 240V, 50 Hz to a load
of R = 10Ω, L = 0.1H, and an emf V
c
= 200V. Determine the conduction angle γ and the total
current i(t ).
SOLUTION
From Equation 2.20, φ = tan
−1
(ωL/R) = 72.34
◦
.
Therefore,
τ =
L
R
= 10 ms, Z =
_
R
2
+(ωL)
2
=
√
100 +986.96 = 32.969Ω.
From Equation 2.38
m = sinα =
200
240
√
2
= 0.589.
42 Power Electronics
Therefore, α = sin
−1
0.589 = 36.1
◦
= 0.63rad.
Checking the graph in Figure 2.7, we obtain γ = 156
◦
.
From Equation 2.39
A =
_
V
c
R
−
√
2V
Z
sin(α −φ)
_
e
αR/ωL
= [20 −10.295sin(−36.24)]e
0.2
= 26.086 ×1.2214 = 31.86.
Therefore, i(t ) = 10.295sin(314.16t −72.34
◦
) −20 +31.86e
−100t
A in 36.1
◦
< ωt < 192.1
◦
.
2.2.4.1 Negligible LoadCircuit Inductance
From Equation 2.37, if L = 0, we obtain
i =
√
2V
R
sin ωt −
V
c
R
(2.46)
or
R
√
2V
i = sin ωt −m. (2.47)
The current (R/
√
2V)i is shown in Figure 2.8, from which it may be seen that
γ = π −2α. (2.48)
The average current is
I
0
=
1
2π
π−α
α
√
2V
R
(sin ωt −m) d(ωt)
=
√
2V
πR
[cos α −m(π/2 −α)] =
√
2V
πR
_
_
1 −m
2
−mcos
−1
m
_
.
(2.49)
2.2.5 SinglePhase HalfWave Rectiﬁer with a Capacitive Filter
The singlephase halfwave rectiﬁer shown in Figure 2.9 has a parallel R−C load. The
purpose of the capacitor is to reduce the variation in the output voltage, making it more
like a pure DC voltage.
Assuming the rectiﬁer works in steadystate, the capacitor is initially charged in a certain
DC voltage and the circuit is energized at ωt = 0; the diode becomes forward biased at the
angle ωt = α as the source becomes positive. As the source decreases after ωt = π/2, the
capacitor discharges from the discharging angle θ into the load resistor. From this point,
the voltage of the source becomes less than the output voltage, reverse biasing the diode
and isolating the load from the source. The output voltage is a decaying exponential with
time constant RC while the diode is off.
Uncontrolled AC/DC Converters 43
SW
i
1.0
m
0
a
a+g p wt 2p
0
a
a+g p wt 2p
p wt 2p
2V ÷
v
2V ÷
R
1.0
m
0
2V ÷
v
g
2V sin wt
v = ÷
+
v
AK
–
D
1
+
–
+
+ –
–
V
0
V
c
V
R R
(a)
(b)
i
FIGURE 2.8 Halfwave rectiﬁer with R load plus back emf. (a) Circuit and (b) waveforms.
The output voltage is described by
v
d
(ωt) =
_
√
2V sin ωt, diode on,
V
θ
e
−(ωt−θ)/ωRC
, diode off,
(2.50)
where
V
θ
=
√
2V sin θ. (2.51)
At ωt = θ, the slopes of the voltage functions are equal to
√
2V cos θ =
√
2V sin θ
−ωRC
e
−(θ−θ)/ωRC
.
44 Power Electronics
÷2V=V
m
wt
2V sin wt v = ÷
i
D
i
C
i
R
R C
V
0
(a)
(b)
V
in
V
q
V
0
0
p
2
q
a
2p 2p+a
FIGURE 2.9 Halfwave rectiﬁer with an R−C load: (a) circuit and (b) input and output voltage.
Hence
1
tan θ
=
−1
ωRC
. (2.52)
Thus
θ = π −tan
−1
(ωRC).
ADVICE
The discharging angle θ must be >π/2. (Historic problem: θ = π/2.)
The angle at which the diode turns on in the second period, ωt = 2π +α, is the point at
which the sinusoidal source reaches the same value as the decaying exponential output.
√
2V sin(2π +α) = (
√
2V sin θ)e
−(2π+α−θ)/ωRC
or
sin α −(sin θ)e
−(2π+α−θ)/ωRC
= 0. (2.53)
The preceding equation must be solved numerically.
Peak capacitor current occurs when the diode turns on at ωt = 2π +α,
i
C−peak
= ωC
√
2V cos(2π +α) = ωC
√
2V cos α. (2.54)
Uncontrolled AC/DC Converters 45
ADVICE
The capacitor peak current locates at ωt = α, which is usually much smaller than π/2.
(Historic problem: α ≈ π/2.)
Resistor current i
R
(t) is
i
R
(t) =
⎧
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎩
√
2V
R
sin ωt diode on,
V
θ
R
e
−(ωt−θ)/ωRC
diode off,
where V
θ
=
√
2V sin θ.
Its peak current at ωt = π/2 is,
i
R−peak
=
√
2V
R
.
Its current at ωt = 2π +α (and ωt = α) is
i
R
(2π +α) =
√
2V
R
sin(2π +α) =
√
2V
R
sin α. (2.55)
Usually, the capacitive reactance is smaller than the resistance R; the main component of
the source current is capacitor current. Therefore, the peak diode (source) current is
i
D−peak
= ωC
√
2V cos α +
√
2V
R
sin α. (2.56)
ADVICE
The source peak current locates at ωt = α, which is usually much smaller than π/2. (Historic
problem: The source peak current locates at ωt = π/2.)
The peaktopeak ripple of the output voltage is given by
ΔV
d
=
√
2V −
√
2V sin α =
√
2V(1 −sin α). (2.57)
Example 2.3
Asinglephase halfwave diode rectiﬁer shown in Figure 2.9a operates froma supply of V = 240V,
50Hz to a load of R = 100Ω and C = 100μF in parallel. If α = 12.63
◦
(see Question 2.5),
determine the peak capacitor current and peak source current.
SOLUTION
From Equation 2.54, the peak capacitor current at ωt = α is
i
C−peak
= ωC
√
2V cos α = 100π ×0.0001 ×240 ×
√
2 ×cos 12.63
◦
= 10.4A.
From Equation 2.56, the peak source current at ωt = α is
i
D−peak
= ωC
√
2V cos α +
√
2V
R
sinα = 10.4 +
240
√
2
100
sin12.63
◦
= 11.14A.
In order to help readers understand the current waveforms, the simulation results are presented
below (Figure 2.10) for reference: V
in
= 340V/50Hz, C = 100μF, and R = 100Ω.
46 Power Electronics
(a)
(b)
R
C
V
in
400.00
V
0
V
in
200.00
0.00
–200.00
–400.00
140.00 150.00 160.00
Time (ms)
170.00 180.00
D
V
0
(c)
12.50
10.00
7.50
5.00
2.50
–2.50
–5.00
140.00 150.00 160.00 170.00 180.00
0.00
Input I(R) I(C)
Time (ms)
FIGURE 2.10 Simulation results: (a) circuit, (b) input (sinewave) and output voltages, and (c) input (top),
capacitor (middle), and resistor (lower) currents.
Uncontrolled AC/DC Converters 47
2.3 SinglePhase FullWave Converters
Singlephase uncontrolled fullwave bridge circuits are shown in Figures 2.11a and
2.12a. They are called the centertap (midpoint) rectiﬁer and the bridge (Graetz) rectiﬁer,
V
D1
D
1
V
s
V
p
+
–
+
+
+
–
–
–
V
s
v
s
v
L
v
D
V
D2
V
D1
v
s
=
V
m
sinwt
V
m
–V
m
–2V
m
V
m
0
0 p
2p wt
0 p 2p wt
R
i
L
V
L
V
D2
D
2
p
2p
wt
(a)
(b)
FIGURE 2.11 Centertap (midpoint) rectiﬁer: (a) circuit diagram and (b) waveforms.
48 Power Electronics
respectively. Figures 2.11a and 2.12a appear identical as far as the load is concerned. It can
be seen in Figure 2.11a that two less diodes are employed, but a centertapped transformer
is required. The rectifying diodes in Figure 2.11a experience twice the reverse voltage, as
do the four diodes in the circuit of Figure 2.12a. As most industrial applications, use the
bridge (Graetz) rectiﬁer circuit, further analysis and discussion will be based on the bridge
rectiﬁer.
D
1
D
4
D
3
R
I
L
D
2
V
p V
s
V
L
+
–
+
–
+
–
v
s
v
s
=
V
m
sinwt
V
m
–V
m
–V
m
V
m
0
0
0
p
p
2p wt
2p wt
2p wt
p
v
L
v
D
v
D3
, v
D4
v
D1
, v
D2
(a)
(b)
FIGURE 2.12 Bridge (Graetz) rectiﬁer: (a) circuit diagram and (b) waveforms.
Uncontrolled AC/DC Converters 49
2.3.1 R Load
Referring to the bridge circuit shown in Figure 2.12, it is seen that the load is pure resistive,
R. In Figure 2.12b, the bridge circuit voltage and current waveforms are shown. The output
average voltage is
V
d
=
1
π
π
0
√
2V sin ωt d(ωt) =
2
√
2
π
V = 0.9 V. (2.58)
The output rms voltage is
V
d−rms
=
¸
¸
¸
¸
_
1
2π
π
0
_
√
2V sin ωt
_
2
d(ωt) = V
¸
¸
¸
¸
_
1
π
π
0
(sin α)
2
dα = V. (2.59)
The output average and rms currents are
I
d
=
V
d
R
=
2
√
2
π
V
R
= 0.9
V
R
, (2.60)
I
d−rms
=
V
d−rms
R
=
V
R
. (2.61)
The FF and RF of the output voltage are
FF =
V
d−rms
V
d
=
1
2
√
2/π
=
π
2
√
2
= 1.11, (2.62)
RF =
_
FF
2
−1 =
_
(1.11)
2
−1 = 0.48, (2.63)
PF =
1
√
2
= 0.707 for the midpoint circuit, (2.64)
RF = 1 for the Graetz circuit. (2.65)
ADVICE
For all diode rectiﬁers, only the Graetz (bridge) circuit has a unity power factor (UPF).
(Historic problem: Multiphase fullwave rectiﬁers may have UPF.)
2.3.2 R–C Load
Linear and switchmode DC power supplies require AC/DC rectiﬁcation. To obtain a
“smooth” output, capacitor C is connected as shown in Figure 2.13.
Neglecting diode forward voltage drop, the peak of the output voltage is
√
2V. Dur
ing each half cycle, the capacitor undergoes cyclic changes from v
d(min)
to
√
2V in the
period between ωt = α and ωt = π/2, and discharges from
√
2V to v
d(min)
in the period
between ωt = θ and ωt = π +α. The resultant output of the diode bridge is unipolar, but
time dependent.
v
d
(ωt) =
_
√
2V sin ωt diode on,
V
θ
e
−(ωt−θ)/ωRC
diode off,
(2.66)
50 Power Electronics
I
d
(a)
D
1
D
3
V
d
+
–
V
D
2
D
4
C R
V
m
–V
m
0 p 2p wt
(b)
v
v
s
=
V
m
sin wt
v
d
v
d
V
m
wt 0
(c)
a q p 2p
(d)
o
i
D
i
C
i
R
wt p 2p
FIGURE 2.13 Singlephase fullwave bridge rectiﬁer with R−C load: (a) circuit, (b) input voltage, (c) output
voltage, and (d) current waveforms.
Uncontrolled AC/DC Converters 51
where
V
θ
=
√
2V sin θ. (2.67)
At ωt = θ, the slopes of the voltage functions are equal to
√
2V cos θ =
√
2V sin θ
−ωRC
e
−(θ−θ)/ωRC
.
Therefore
1
tan θ
=
−1
ωRC
. (2.68)
Thus
θ = π −tan
−1
(ωRC).
The angle at which the diode turns on in the second period, ωt = π +α, is the point at
which the sinusoidal source reaches the same value as the decaying exponential output.
√
2V sin(π +α) = (
√
2V sin θ)e
−(π+α−θ)/ωRC
or
sin α −(sin θ)e
−(π+α−θ)/ωRC
= 0. (2.69)
The preceding equation must be solved numerically.
The output average voltage is
V
d
=
1
π
π+α
α
v
d
d(ωt) =
√
2V
π
⎡
⎣
θ
α
sin ωt d(ωt) +
π+α
θ
sin θ e
−(t−θ/ω)/RC
d(ωt)
⎤
⎦
=
√
2V
π
⎡
⎢
⎣
(cos α −cos θ) +ωRCsin θ
(π+α−θ)/ω
0
e
−t/RC
d
_
t
RC
_
⎤
⎥
⎦
=
√
2V
π
_
(cos α −cos θ) +ωRCsin θ
_
1 −e
−(π+α−θ)/ωRC
__
.
(2.70)
The output rms voltage is
V
d−rms
=
¸
¸
¸
¸
_
1
π
π+α
α
v
2
d
d(ωt) =
¸
¸
¸
¸
_
2V
2
π
⎡
⎣
θ
α
(sin ωt)
2
d(ωt) +
π+α
θ
sin
2
θ e
−2((t−θ)ω)/RC
d(ωt)
⎤
⎦
=
√
2V
_
1
π
__
θ −α
2
−
cos 2α −cos 2θ
4
_
+ωRCsin
2
θ
_
1 −
e
−2(π+α−θ)/ωRC
2
__
.
(2.71)
52 Power Electronics
Since the average capacitor current is zero, the output average current is
I
d
=
V
d
R
=
√
2V
πR
_
(cos α −cos θ) +ωRCsin θ
_
1 −e
−(π+α−θ)/ωRC
__
. (2.72)
The FF and RF of the output voltage are
FF =
V
d−rms
V
d
=
√
2V
_
(1/π)[((θ −α)/2) −((cos 2α −cos 2θ)/4) +ωRCsin
2
θ(1 −(e
−2(π+α−θ)/ωRC
/2))]
_
√
2V/π
_
_
(cos α −cos θ) +ωRCsin θ
_
1 −e
−(π+α−θ)/ωRC
__
=
√
π
_
((θ −α)/2) −((cos 2α −cos 2θ)/4) +ωRCsin
2
θ(1 −(e
−2(π+α−θ)/ωRC
/2))
cos α −cos θ +ωRCsin θ
_
1 −e
−(π+α−θ)/ωRC
_ ,
RF =
_
FF
2
−1. (2.73)
2.3.3 R–L Load
A singlephase fullwave diode rectiﬁer with R−L load is shown in Figure 2.14a, while
various circuit waveforms are shown in Figures 2.14b and c.
If the inductance L is large enough, the load current can be considered as a continuous
constant current to simplify the analysis and calculations. It is accurate enough for theoret
ical analysis and engineering calculations. In this case, the load current is assumed to be a
constant DC current.
The output average voltage is
V
d
=
1
π
π
0
√
2V sin ωt d(ωt) =
2
√
2
π
V = 0.9 V. (2.74)
The output rms voltage is
V
d–rms
=
¸
¸
¸
¸
_
1
2π
π
0
_
√
2V sin ωt
_
2
d(ωt) = V
¸
¸
¸
¸
_
1
π
π
0
(sin α)
2
dα = V. (2.75)
The output current is a constant DC value; its average and rms currents are
I
d
= I
d–rms
=
V
d
R
=
2
√
2
π
V
R
= 0.9
V
R
. (2.76)
The FF and RF of the output voltage are
FF =
V
d–rms
V
d
=
1
2
√
2/π
=
π
2
√
2
= 1.11, (2.77)
RF =
_
FF
2
−1 =
_
(1.11)
2
−1 = 0.48. (2.78)
Uncontrolled AC/DC Converters 53
(a)
(b)
(c)
D
1
v
v
d
v
=
V
m
sin wt
–V
m
V
m
V
m
0 2p wt
R
L
D
2
D
3
D
4
p
0 2p wt p
v
d v = √2Vsinwt
i
FIGURE 2.14 Singlephase fullwave bridge rectiﬁer with R plus large L load: (a) circuit, (b) input voltage, and
(c) output voltage.
2.4 ThreePhase HalfWave Converters
If the AC power supply is from a transformer, four circuits can be used. The threephase
halfwave rectiﬁers are shown in Figure 2.15.
The ﬁrst circuit is called a Y/Y circuit, shown in Figure 2.15a; the second circuit is called
a Δ/Y circuit, shown in Figure 2.15b; the third circuit is called a Y/Y bending circuit,
shown in Figure 2.15c; and the fourth circuit is called a Δ/Y bending circuit, shown in
Figure 2.15d. Each diode is conducted in 120
◦
a cycle. Some waveforms are shown in
Figure 2.16 corresponding to L = 0. The threephase voltages are balanced, so that
v
a
(t) =
√
2V sin ωt, (2.79)
v
b
(t) =
√
2V sin(ωt −120
◦
), (2.80)
v
c
(t) =
√
2V sin(ωt −240
◦
). (2.81)
54 Power Electronics
V
a
V
a
V
a
V
a
I
d
I
d
V
d0
V
d0
V
a
L
R
L
R
3V
a
(a) (b)
(c) (d)
I
d
L
R
V
a
/ 3
V
a
/
V
d0
3
V
a
3V
a
I
d
V
a
/ 3
V
d0
V
a
/ 3
L
R
FIGURE 2.15 Threephase halfwave diode rectiﬁers: (a) Y/Y circuit, (b) Δ/Y circuit, (c) Y/Y bending circuit,
and (d) Δ/Y bending circuit.
2.4.1 R Load
Referring to the bridge circuit shown in Figure 2.15a, the load is pure resistive, R (L = 0).
Figure 2.16 shows the voltage and current waveforms. The output average voltage is
V
d0
=
3
2π
5π/6
π/6
√
2V sin ωt d(ωt) =
3
√
3
√
2π
V = 1.17 V. (2.82)
Uncontrolled AC/DC Converters 55
v
0
v
a
v
Da
v
c
v
b
V
0
i
0
i
a
i
b
i
c
i
0
i
0
I
0
I
0
wt
wt
wt
wt
wt
wt
÷2V
÷6V
FIGURE 2.16 Waveforms of the threephase halfwave rectiﬁer.
The output rms voltage is
V
d–rms
=
¸
¸
¸
¸
¸
_
3
2π
5π/6
π/6
_
√
2V sin ωt
_
2
d(ωt) = V
¸
¸
¸
_
6
π
_
π
6
+
√
3
8
_
= 1.1889 V. (2.83)
The output average and rms currents are
I
d
=
V
d
R
= 1.17
V
R
, (2.84)
I
d−rms
=
V
d−rms
R
= 1.1889
V
R
. (2.85)
The FF, RF, and PF of the output voltage are
FF =
V
d−rms
V
d
=
1.1889
1.17
= 1.016, (2.86)
56 Power Electronics
RF =
_
FF
2
−1 =
_
(1.016)
2
−1 = 0.18, (2.87)
and
PF = 0.686. (2.88)
2.4.2 R–L Load
Athreephase halfwave diode rectiﬁer withR−L loadis showninFigure 2.15a. If the induc
tance L is large enough, the load current can be considered as a continuous constant current
to simplify the analysis and calculations. It is accurate enough for theoretical analysis and
engineering calculations. In this case, the load current is assumed to be a constant DC
current. The output average voltage is
V
d0
=
3
2π
5π/6
π/6
√
2V sin ωt d(ωt) =
3
√
3
√
2π
V = 1.17 V. (2.89)
The output rms voltage is
V
d−rms
=
¸
¸
¸
¸
¸
_
3
2π
5π/6
π/6
_
√
2V sin ωt
_
2
d(ωt) = V
¸
¸
¸
_
6
π
_
π
6
+
√
3
8
_
= 1.1889 V. (2.90)
The output current is nearly a constant DC value; its average and rms currents are
I
d
= I
d−rms
=
V
d
R
= 1.17
V
R
. (2.91)
The FF and RF of the output voltage are
FF =
V
d−rms
V
d
=
1.1889
1.17
= 1.016, (2.92)
RF =
_
FF
2
−1 =
_
(1.016)
2
−1 = 0.18. (2.93)
2.5 SixPhase HalfWave Converters
Sixphase halfwave rectiﬁers have two constructions: sixphase with a neutral line circuit
and double antistar with a balancechoke circuit. The following description is based on the
R load or R plus large L load.
Uncontrolled AC/DC Converters 57
2.5.1 SixPhase with a Neutral Line Circuit
If the AC power supply is from a transformer, four circuits can be used. The sixphase
halfwave rectiﬁers are shown in Figure 2.17.
The ﬁrst circuit is called a Y/star circuit, shown in Figure 2.17a; the second circuit is called
a Δ/star circuit, shown in Figure 2.17b; the third circuit is called a Y/star bending circuit,
shown in Figure 2.17c; and the fourth circuit is called a Δ/star bending circuit, shown in
Figure 2.17d. Each diode is conducted in 60
◦
a cycle. Since the load is an R−L circuit, the
output voltage average value is
V
d0
=
1
π/3
2π/3
π/3
V
m
sin(ωt) d(ωt) =
3
√
2
π
V
a
= 1.35V
a
, (2.94)
V
a
V
a
V
a
÷3V
a
÷3V
a
V
a
/÷3 V
a
/÷3
V
a
V
a
V
d0
V
d0
V
a
I
d
I
d
V
d0
I
d
L R
V
d0
I
d
L R
L R L R
(a) (b)
(c) (d)
FIGURE 2.17 Sixphase halfwave diode rectiﬁers: (a) Y/star circuit, (b) Δ/star circuit, (c) Y/star bending circuit,
and (d) Δ/star bending circuit.
58 Power Electronics
I
d I
d
V
d0
V
a
V
a
V
a
L R
L R
V
d0
(a) (b)
÷3V
a
FIGURE 2.18 Threephase double antistar with balancechoke diode rectiﬁers: (a) Y/YY circuit and (b) Δ/YY
circuit.
FF = 1.00088, (2.95)
RF = 0.042, (2.96)
PF = 0.552. (2.97)
2.5.2 Double Antistar with BalanceChoke Circuit
If the AC power supply is from a transformer, two circuits can be used. The sixphase
halfwave rectiﬁers are shown in Figure 2.18.
The ﬁrst circuit is called a Y/YY circuit, shown in Figure 2.18a, and the second circuit
is called a Δ/YY circuit, shown in Figure 2.18b. Each diode is conducted in 120
◦
a cycle.
Since the load is an R−L circuit, the output voltage average value is
V
d0
=
1
2π/3
5π/6
π/6
V
m
sin(ωt) d(ωt) =
3
√
6
2π
V
a
= 1.17V
a
, (2.98)
FF = 1.01615, (2.99)
RF = 0.18, (2.100)
PF = 0.686. (2.101)
2.6 ThreePhase FullWave Converters
If the AC power supply is from a transformer, four circuits can be used. The threephase
fullwave diode rectiﬁers, shown in Figure 2.19, all consist of six diodes. The ﬁrst circuit
is called a Y/Y circuit, shown in Figure 2.19a; the second circuit is called a Δ/Y circuit,
shown in Figure 2.19b; the third circuit is called a Y/Δ circuit, shown in Figure 2.19c; and
Uncontrolled AC/DC Converters 59
I
d
V
a
V
a
V
a
L R
V
d0
I
d
L R
V
d0
I
d
L R
V
d0
(a) (b)
(c)
V
a
÷3V
a
÷3V
a
I
d
L R
V
d0
(d)
÷3V
a
÷3V
a
FIGURE 2.19 Threephase fullwave diode rectiﬁers: (a) Y/Ycircuit, (b) Δ/Ycircuit, (c) Y/Δcircuit, and (d) Δ/Δ
circuit.
the fourth circuit is called a Δ/Δcircuit, shown in Figure 2.19d. Each diode is conducted in
120
◦
a cycle. Since the load is an R−L circuit, the output voltage average value is
V
d0
=
2
2π/3
5π/6
π/6
V
m
sin(ωt) d(ωt) =
3
√
6
π
V
a
= 2.34V
a
, (2.102)
FF = 1.00088, (2.103)
60 Power Electronics
RF = 0.042, (2.104)
PF = 0.956. (2.105)
Some waveforms are shown in Figure 2.20.
ADVICE
The threephase fullwave bridge rectiﬁer has high PF (although no UPF) and low RF =
4.2%. It is a proven circuit that can be used in most industrial applications.
2.7 Multiphase FullWave Converters
Usually, the more the phases, the smaller the output voltage ripple. In this section, several
circuits with sixphase, twelvephase, and eighteenphase supply are investigated.
2.7.1 SixPhase FullWave Diode Rectiﬁers
In Figure 2.21, two circuits of sixphase fullwave diode rectiﬁers, each all consisting of 12
diodes, are shown. The ﬁrst circuit is called the sixphase bridge circuit (Figure 2.21a) and
the secondcircuit is calledthe hexagonbridge circuit (Figure 2.21b). Eachdiode is conducted
in 60
◦
a cycle. Since the load is an R−L circuit, the average output voltage value is
V
d0
=
2
π/3
2π/3
π/3
V
m
sin(ωt) d(ωt) =
6
√
2
π
V
a
= 2.7V
a
, (2.106)
FF = 1.00088, (2.107)
RF = 0.042, (2.108)
PF = 0.956. (2.109)
2.7.2 SixPhase DoubleBridge FullWave Diode Rectiﬁers
Figure 2.22 shows two circuits of the sixphase doublebridge fullwave diode rectiﬁers.
The ﬁrst circuit is called a Y/YΔ circuit (Figure 2.22a), and the second circuit is called a
Δ/YΔ circuit (Figure 2.22b). Each diode is conducted in 120
◦
a cycle. There are 12 pulses
during each period and the phase shift is 30
◦
. Since the load is an R−L circuit, the output
voltage V
d0
is nearly pure DC voltage.
V
d0
=
4
2π/3
5π/6
π/6
V
m
sin(ωt) d(ωt) =
6
√
6
π
V
a
= 4.678V
a
, (2.110)
FF = 1.0000567, (2.111)
RF = 0.0106, (2.112)
PF = 0.956. (2.113)
Uncontrolled AC/DC Converters 61
V
a
V
0
V
0
0
0
0
0
0
0
0
V
0
V
0
V
XN
V
ZN
V
b
V
c
÷2V
÷3V = V
L
÷2V
L
÷2V
L
wt
wt
wt
wt
wt
wt
wt
i
0
i
0
i
a
= i
D1
– i
D4
V
D1
= V
a
– V
XN
i
D1
i
D4
V
D1
i
a
i
0
FIGURE 2.20 Waveforms of a threephase fullwave bridge rectiﬁer.
62 Power Electronics
÷3V
a
÷3V
a
÷3V
a
Neutral line can
be unconnected
V
a
V
a
V
d0
I
d
I
d
L R
L R
V
d0
(a)
(b)
FIGURE 2.21 Sixphase fullwave diode rectiﬁers: (a) sixphase bridge circuit and (b) hexagon bridge circuit.
ADVICE
The sixphase doublebridge fullwave diode rectiﬁer has high PF (although no UPF) and a
lowRF = 1.06%. It is a provencircuit that canbe usedinlarge power industrial applications.
2.7.3 SixPhase DoubleTransformer DoubleBridge FullWave Diode Rectiﬁers
Figure 2.23 shows the sixphase doubletransformer doublebridge fullwave diode rec
tiﬁer. The ﬁrst transformer T
1
is called a Y/YΔ connection transformer, and the second
transformer T
2
is called a bending Y/YΔ connection transformer with 15
◦
phase shift. In
total, there are 24 diodes involved in the rectiﬁer. Each diode is conducted in 120
◦
a cycle,
There are 24 pulses a period and the phase shift is 15
◦
. Since the load is an R−L circuit, the
output voltage V
d0
is nearly pure DC voltage.
V
d0
=
8
2π/3
5π/6
π/6
V
m
sin(ωt) d(ωt) =
12
√
6
π
V
a
= 9.356V
a
, (2.114)
÷3V
a
÷3V
a
V
a
V
a
I
d
I
d
L R
V
d0
L R
V
d0
÷3V
a
(a) (b)
V
a
FIGURE 2.22 Sixphase doublebridge fullwave diode rectiﬁers: (a) Y/YΔ circuit and (b) Δ/YΔ circuit.
Uncontrolled AC/DC Converters 63
V
a
V
a
V
a
V
a
T
1
T
2
I
d
L R
V
d0
÷3V
a
÷3V
a
FIGURE 2.23 Sixphase doubletransformer doublebridge fullwave diode rectiﬁer.
FF = 1.0000036, (2.115)
RF = 0.00267, (2.116)
PF = 0.956. (2.117)
2.7.4 SixPhase TripleTransformer DoubleBridge FullWave Diode Rectiﬁers
Figure 2.24 shows the sixphase tripletransformer doublebridge fullwave diode rectiﬁer.
The ﬁrst transformer T
1
is called a Y/YΔ connection transformer, the second transformer
T
2
is called a positivebending Y/YΔ connection transformer with a +10
◦
phase shift, and
the third transformer T
3
is called a negativebending Y/YΔ connection transformer with
a −10
◦
phase shift. There are 36 diodes involved in the rectiﬁer. Each diode is conducted
in 120
◦
a cycle. There are 36 pulses a period, and the phase shift is 10
◦
. Since the load is an
R−L circuit, the output voltage V
d0
is nearly pure DC voltage.
V
d0
=
12
2π/3
5π/6
π/6
V
m
sin(ωt) d(ωt) =
18
√
6
π
V
a
= 14.035V
a
, (2.118)
V
a
V
a
V
a
V
a
V
a
V
a
T
1
T
2
T
3
I
d
L R
V
d0
÷3V
a
÷3V
a
÷3V
a
FIGURE 2.24 Sixphase tripletransformer doublebridge fullwave diode rectiﬁer.
64 Power Electronics
FF = 1.0000007, (2.119)
RF = 0.00119, (2.120)
PF = 0.956. (2.121)
Homework
2.1. Asinglephase halfwave diode rectiﬁer operates from a supply of 200 V, 60 Hz to
a load of R = 15 Ωand L = 0.2 H. Determine the extinction angle β using the graph
in Figure 2.4.
2.2. Asinglephase halfwave diode rectiﬁer operates from a supply of 240 V, 50 Hz to
a load of R = 10 Ω and L = 0.1 H. Determine the extinction angle β using iterative
method 2 (see Section 2.2.2.3).
2.3. Referring to the singlephase halfwave rectiﬁer with R−L load as shown in
Figure 2.2a and given that R = 100 Ω, L = 0.1 H, ω = 377 rad/s ( f = 60 Hz), and
V = 100/
√
2 V, determine:
a. Expression angle β for the current.
b. Average current.
c. Average output voltage.
2.4. In the circuit shown in Figure 2.8a, the source voltage v(t) = 110
√
2 sin 120 πt,
R = 1 Ω, and the loadcircuit emf V
c
= 100 V. If the circuit is closed during the
negative halfcycle of the source voltage, calculate:
a. Angle α at which D starts to conduct.
b. Conduction angle γ.
c. Average value of current i.
d. Rms value of current i.
e. Power delivered by the AC source.
f. The PF at the AC source.
2.5. A singlephase halfwave rectiﬁer, as shown in Figure 2.9a, has an AC input of
240 V (rms) at f = 50 Hz with a load R = 100 Ω and C = 100 μF in parallel. Deter
mine angle α and angle θ within an accuracy of 0.1
◦
using iterative method 1 (see
Section 2.2.2.2).
2.6. A fullwave rectiﬁer, as shown in Figure 2.12a, has an AC input of 240 V (rms) at
50 Hz with a load R = 100 Ω and C = 100 μF in parallel. Determine angle α and
angle θ within an accuracy of 0.1
◦
using iterative method 1 (see Section 2.2.2.2).
Calculate the average output voltage V
d
and current I
d
.
References
1. Rashid, M. H. 2007. Power Electronics Handbook (2nd edition). Boston: Academic Press.
2. Luo, F. L., Ye, H., and Rashid, M. H. 2005. Digital Power Electronics and Applications. New York:
Academic Press.
Uncontrolled AC/DC Converters 65
3. Dorf, R. C. 2006. The Electrical Engineering Handbook (3rd edition). Boca Raton: Taylor &Francis.
4. Mohan, N., Undeland, T. M., and Robbins, W. P. 2003. Power Electronics: Converters, Applica
tions and Design (3rd edition). New York: Wiley.
5. Rashid, M. H. 2003. Power Electronics: Circuits, Devices and Applications (3rdedition). NewJersey:
PrenticeHall, Inc.
6. Keown, J. 2001. OrCAD PSpice and Circuit Analysis (4th edition). New Jersey: PrenticeHall.
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3
Controlled AC/DC Converters
Controlled AC/DC converters are usually called controlled rectiﬁers. They convert an AC
power supply source voltage to a controlled DC load voltage [1–3]. Controlled AC/DC
conversion technology is a vast subject area spanning research investigation to indus
trial applications. Usually, such rectiﬁer devices are thyristors (or SCRs—siliconcontrolled
rectiﬁers), gateturnoff thyristors (GTOs), power transistors (PTs), insulated gate bipolar
transistors (IGBTs), and so on. Generally, the device used most is the thyristor (or SCR).
Controlled AC/DC converters consist of thyristor/diode circuits, which can be sorted into
the following groups:
• Singlephase halfwave rectiﬁers.
• Singlephase fullwave rectiﬁers with half/full control.
• Threephase rectiﬁers with half/full control.
• Multipulse rectiﬁers.
3.1 Introduction
As is the case of the diode rectiﬁers discussed in Chapter 2, the diode should be assumed
that the diodes are replaced by thyristors or other semiconductor devices in controlled
rectiﬁers, which are then supplied from an ideal AC source. Two conditions must be met
before the thyristor can be conducting [4–10]:
1. The thyristor must be forward biased.
2. Acurrent must be applied to the gate of the thyristor.
Only one condition must be met before the thyristor can be switched off: the current that
ﬂows throughit shouldbe lower thanthe latchedvalue, irrespective of whether the thyristor
is forward or reverse biased.
According to the above conditions, a ﬁring pulse with a variable angle is then required to
be applied to the gate of the thyristor. Usually, the ﬁring angle is deﬁned as α. If the ﬁring
angle α = 0, the thyristor functions as a diode. The corresponding output DC voltage of
the rectiﬁer is its maximumvalue. Referring to the results in Chapter 2, properly controlled
rectiﬁers can be designed that satisfy industrial application needs.
67
68 Power Electronics
3.2 SinglePhase HalfWave Controlled Converters
Asinglephase halfwave controlledrectiﬁer consists of a singlephaseACinput voltage and
one thyristor. It is the simplest rectiﬁer. This rectiﬁer can supply various loads as described
in the following subsections.
3.2.1 R Load
A singlephase halfwave diode rectiﬁer with R load is shown in Figure 3.1a; the input
voltage, output voltage, and current waveforms are shown in Figures 3.1b–d. The output
÷2V sin wt v = R
T
v
O
v
R
i
i
G
i
G
v
O
i
v
0
0
Z
0
0
p
p a
a
a
2p
2p
wt
wt
wt
wt
÷2V
÷2V
÷2V
FIGURE 3.1 Singlephase halfwave controlled rectiﬁer with R load.
Controlled AC/DC Converters 69
voltage is the same as the input voltage in the positive halfcycle and zero in the negative
halfcycle.
The output average voltage is
V
d
=
1
2π
π
α
√
2V sin ωt d(ωt) =
√
2
2π
V(1 +cos α) = 0.45V
1 +cos α
2
. (3.1)
Using the deﬁnition, we obtain
V
dO
=
1
2π
π
0
√
2V sin ωt d(ωt) =
√
2
2π
V. (3.2)
We can rewrite Equation 3.1 as
V
d
=
1
2π
π
α
√
2V sin ωt d(ωt) =
1 +cos α
2
V
dO
. (3.3)
The output rms voltage is
V
d−rms
=
¸
¸
¸
¸
_
1
2π
π
α
(
√
2V sin ωt)
2
d(ωt) = V
¸
¸
¸
¸
_
1
π
π
α
(sin x)
2
dx = V
_
1
π
_
π −α
2
+
sin 2α
4
_
.
(3.4)
The output average and rms currents are
I
d
=
V
d
R
=
√
2
π
V
R
1 +cos α
2
=
1 +cos α
2
V
dO
R
, (3.5)
I
d−rms
=
V
d−rms
R
=
V
R
_
1
π
_
π −α
2
+
sin 2α
4
_
. (3.6)
3.2.2 R–L Load
A singlephase halfwave diode rectiﬁer with an R–L load is shown in Figure 3.2a, while
various circuit waveforms are shown in Figures 3.2b–d.
It can be seen that load current ﬂows not only during the positive part of the supply
voltage but also during a portion of the negative supply voltage as well [11–21]. The load
inductor SE maintains the load current, and the inductor’s terminal voltage changes so as
to overcome the negative supply and keep the diode forward biased and conducting. The
load impedance Z is
Z = R +jωL = Z∠φ with φ = tan
−1
ωL
R
,
Z =
_
R
2
+(ωL)
2
.
(3.7)
70 Power Electronics
R
L
Q
0
v
0
0
0
i
Z
v
O
v
L
v
R
i
i
G
i
G
v
O
p
p
p
b
b
g
a
a
a
2p
2p
2p
wt
wt
wt
wt
÷2V sin wt v =
÷2V
÷2V
÷2V
FIGURE 3.2 Halfwave controlled rectiﬁer with R–L load.
When the thyristor is conducting, the dynamic equation is
L
di
dt
+Ri =
√
2V sin ωt with α ≤ ωt < β (3.8)
or
di
dt
+
R
L
i =
√
2V
L
sin ωt with α ≤ ωt < β,
where α is the ﬁring angle and β is the extinction angle. The thyristor conducts between α
and β. Equation 3.8 is a nonnormalized differential equation. The solution has two parts.
The forced solution is determined by
i
F
=
√
2V
L
sin(ωt −φ). (3.9)
Controlled AC/DC Converters 71
The natural response of such a circuit is given by
i
N
= Ae
−(R/L)t
= Ae
−t/τ
with τ =
L
R
. (3.10)
The solution of Equation 3.8 is
i = i
F
+i
N
=
√
2V
Z
sin(ωt −φ) +Ae
−(R/L)t
. (3.11)
The constant Ais determined by substitution in Equation 3.11 of the initial conditions i = 0
at ωt = α, which yields
i =
√
2V
Z
_
sin(ωt −φ) −sin(α −φ)e
(R/L)((α/ω)−t)
_
. (3.12)
Also, i = 0, β < ωt < 2π.
The current extinction angle β is determined by the load impedance and can be solved
using Equation 2.12 when i = 0 and ωt = β, that is,
sin(β −φ) = −e
−(Rβ/ωL)
sin(α −φ), (3.13)
which is a transcendental equation with an unknown value of β. The term sin(β −φ) is a
sinusoidal function. The term e
−(Rβ/ωL)
sin(φ −α) is an exponentially decaying function.
The operating point of β is at the intersection of sin(β −φ) and e
−(Rβ/ωL)
sin(φ −α), and its
value canbe determinedbyiterative methods andMATLAB
®
. The average output voltage is
V
O
=
1
2π
β
α
√
2V sin(ωt) d(ωt)
=
V
√
2π
[cos α −cos β]. (3.14)
Example 3.1
A controlled halfwave rectiﬁer has an AC input of 240V (rms) at 50Hz with a load R = 10Ω and
L = 0.1H in series. The ﬁring angle α is 45
◦
, as shown in Figure 3.2. Determine the extinction
angle β within an accuracy of 0.01
◦
using iterative method 2 (see Section 2.2.2.3).
SOLUTION
Calculation of the extinction angle β using iterative method 2 (see Section 2.2.2.3).
ωL
R
= π ≈ 3.14,
z =
_
R
2
+ω
2
L
2
= 33Ω,
Φ = tan
−1
_
ωL
R
_
= 72.34
◦
,
α = 45
◦
, V
m
=
√
2V = 240
√
2 = 340V.
72 Power Electronics
At ωt = β, the current is zero:
sin(β −φ) = e
(α−β)/ tanφ
sin(α −φ).
Using iterative method 2 (see Section 2.2.2.3), deﬁne
x =  sin(β −φ),
y = e
(α−β)/ tanφ
sin(φ −α) = sin(72.34 −α)e
(α−β)/π
= 0.46e
(α−β)/π
.
Make a table as follows:
β (deg) x y sin
−1
y (deg) x: y
252.34 0 0.1454 8.36 <
260.7 0.1454 0.1388 7.977 >
260.32 0.1388 0.13907 7.994 <
260.33 0.13907 0.139066 7.994 ≈
From the above table, we can choose β = 260.33
◦
.
3.2.3 R–L Load Plus Back Emf V
c
If the circuit involves an emf or battery V
c
, the circuit diagram is shown in Figure 3.3. To
guarantee that the thyristor is successfully ﬁred on, the minimumﬁring angle is requested.
If a ﬁring angle is allowable to supply the load with an emf V
c
, the minimumdelay angle is
α
min
= sin
−1
_
V
c
√
2V
_
. (3.15)
This means that the ﬁring pulse has to be appliedto the thyristor when the supply voltage
is higher than the emf V
c
. Other characteristics can be derived as shown in Section 2.2.4.
i
G
R
v
T
v
L
L
T
v
O
v
R
–
–
–
–
+
+
+
+
v
c
i
÷2V sin wt v =
FIGURE 3.3 Halfwave controlled rectiﬁer with R–L load plus an emf V
c
.
Example 3.2
A controlled halfwave rectiﬁer has an AC input of 120V (rms) at 60Hz, R = 2Ω, L = 20mH, and
an emf of V
c
= 100V. The ﬁring angle α is 45
◦
. Determine
a. An expression for the current.
b. The power absorbed by the DC source V
c
in the load.
Controlled AC/DC Converters 73
SOLUTION
From the parameters given,
z =
_
R
2
+ω
2
L
2
= 7.8Ω,
φ = tan
−1
_
ωL
R
_
= 1.312rad,
ωL
R
= 3.77,
α = 45
◦
, V
m
=
√
2V = 120
√
2 = 169.7V.
a. First, use Equation 3.15 to determine the minimum delay angle, if α = 45
◦
is allowable. The
minimum delay angle is
α
min
= sin
−1
_
100
120
√
2
_
= 36
◦
,
which indicates that α = 45
◦
is allowable. The equation
Z
√
2V
i = sin(ωt −φ) −
_
m
cos φ
−Be
(α−ωt )/ tanφ
_
, α < ωt ≤ β,
B =
m
cos φ
−sin(α −φ), ωt = α, i = 0,
becomes
i = 21.8sin(ωt −1.312) +75e
−ωt /3.77
−50 for 0.785rad ≤ ωt ≤ 3.37rad.
Here the extinction angle β is numerically found to be 3.37rad from the equation i(β) = 0.
b. The power absorbed by the DC source V
c
is
P
DC
= IV
c
= V
c
1
2π
β
α
i(ωt ) d(ωt ) = 2.19 ×100 = 219W.
3.3 SinglePhase FullWave Controlled Converters
Fullwave voltage control is possible withthe circuits withanR–L loadshowninFigure 3.4a
and b. The circuit in Figure 3.4a uses a centertapped transformer and two thyristors, which
experience a reverse bias of twice the supply. At high powers where a transformer may not
be applicable, a fourthyristor conﬁguration as in Figure 3.4b is suitable. The load current
waveform becomes continuous when the (maximum) phase control angle α is given by
α = tan
−1
ωL
R
= φ (3.16)
at which the output current is a rectiﬁer sine wave.
For α > φ, discontinuous load current ﬂows as shown in Figure 3.4c. At α = φ, the load
current becomes continuous as shown in Figure 3.4d, where β = α +π. Afurther decrease
74 Power Electronics
v = 2V sin wt
T
1
i
R
L
T
2
(a)
T
2
(b)
v
O
T
4
R
L
i
T
1
T
3
v
O
v
R
v
v
L
= v
O
– v
R
a + p
wt
(c)
a
b
0
v
O
v
R
b = a + p a = f
wt
(d)
0
v
v
O
v
R
a + p
wt
(e)
a
0
v
FIGURE 3.4 (a)–(e) Fullwave voltagecontrolled circuit.
in α, that is, α < φ, results in continuous load current that is always greater than zero, as
shown in Figure 3.4e.
3.3.1 α > φ, Discontinuous Load Current
The load current waveform is the same as for the halfwave situation considered in
Section 3.2.2 by Equation 3.15, that is,
i =
√
2V
Z
_
sin(ωt −φ) −sin(α −φ)e
(R/L)(α/ω−t)
_
. (3.17)
The average output voltage for this fullwave circuit will be twice that of the halfwave
case in Section 3.2.2 by Equation 3.14.
V
O
=
1
π
β
α
√
2V sin(ωt) d(ωt)
=
√
2V
π
[cos α −cos β], (3.18)
where β has to be found numerically.
Controlled AC/DC Converters 75
Example 3.3
A fullwave controlled rectiﬁer, shown in Figure 3.4, has an AC input of 240V (rms) at 50Hz with
a load R = 10Ω and L = 0.1H in series. The ﬁring angle α is 80
◦
.
a. Determine whether the load current is discontinuous. If it is, ﬁnd the extinction angle β to
within an accuracy of 0.01
◦
using iterative method 2 (see Section 2.2.2.3).
b. Derive expressions for current i and output voltage v
O
, and ﬁnd the average output voltage V
O
.
SOLUTION
a. The thyristor ﬁring angle α = 80
◦
. Since the ﬁring angle α is greater than the load phase angle
φ = tan
−1
(ωL/R) = 72.34
◦
, the load current is discontinuous. The extinction angle β is >π,
but <(π +α) = 260
◦
. The output voltage becomes negative when π ≤ ωt ≤ β.
Calculation of the extinction angle β using iterative method 2 (see Section 2.2.2.3) is as
follows:
ωL
R
= π ≈ 3.14,
z =
_
R
2
+ω
2
L
2
= 33Ω,
Φ = tan
−1
_
ωL
R
_
= 72.34
◦
,
α = 80
◦
, V
m
=
√
2V = 240
√
2 = 340V.
Since α > φ, the rectiﬁer is working in the discontinuous current state.
With ωt = β and the current is zero, we obtain the following equation
sin(β −φ) = e
(α−β)/ tanφ
sin(α −φ).
Using iterative method 2 (see Section 2.2.2.3), we deﬁne
x = sin(β −φ),
y = e
(α−β)/ tanφ
sin(α −φ) = sin(α −72.34)e
(α−β)/π
= 0.1333e
(α−β)/π
.
Make a table as follows:
β (deg) x y sin
−1
y (deg) x>, =, <y?
252.34 0 0.05117 2.933 <
255.273 0.05117 0.05034 2.886 >
255.226 0.05034 0.05036 2.8864 <
255.2264 0.05036 0.05036 ≈
From the above table, we choose β = 255.23
◦
.
b. The equation of the current
i =
√
2V
Z
_
sin(ωt −φ) −sin(α −φ)e
(R/L)(α/ω−t )
_
76 Power Electronics
becomes
i =
√
2V
Z
[sin(ωt −φ) +0.1333e
(α−ωt )/π
] = 10.29sin(ωt −72.34) +1.37e
(α−ωt )/π
.
The current expression is
i = 10.29sin(ωt −72.34) +2.138e
−ωt /π
.
The output voltage expression in a period is
v
O
(t ) =
_
240
√
2sinωt α ≤ ωt ≤ β, (π +α) ≤ ωt ≤ (π +β),
0 otherwise.
The average output voltage V
O
is
V
O
=
1
π
β
α
v d(ωt ) =
240
√
2
π
β
α
sin(ωt ) d(ωt ) =
240
√
2
π
(cos α −cos β)
=
240
√
2
π
(0.1736 +0.2549) = 46.3V.
3.3.2 α < φ, Verge of Continuous Load Current
When α = φ, the load current is given by
i =
√
2V
Z
sin(ωt −ϕ), ϕ < ωt < ϕ +π, (3.19)
and the average output voltage is given by
V
O
=
2
√
2V
π
cos α, (3.20)
which is independent of the load.
3.3.3 α < φ, Continuous Load Current
Under these conditions, a thyristor is still conducting when another is forward biased and
turned on. The ﬁrst device is instantaneously reverse biased by the second device that has
been turned on. The average output voltage is
V
O
=
2
√
2V
π
cos α. (3.21)
The rms output voltage is
V
r
= V. (3.22)
Controlled AC/DC Converters 77
3.4 ThreePhase HalfWave Controlled Rectifiers
Athreephase halfwave controlled rectiﬁer is shown in Figure 3.5. The input threephase
voltages are:
v
a
(t) =
√
2V sin ωt,
v
b
(t) =
√
2V sin(ωt −120
◦
),
v
c
(t) =
√
2V sin(ωt +120
◦
).
(3.23)
A
B
V
c
V
b
V
a
V
O
V
a
a = 0
V
b
V
c
I
O
I
O
I
O
I
O
i
O
i
O
i
a
i
b
i
c
V
O
wt
wt
wt
wt
wt
T
a
T
b
V
O
T
c i
c
i
b
i
a
(a)
(b)
C
N
a
L
o
a
d
÷2V
FIGURE 3.5 Threephase halfwave controlled rectiﬁer: (a) circuit and (b) waveforms.
78 Power Electronics
Usually the load is an inductive load, that is, R–L load. If the inductance is large enough,
the load current is continuous for most of the ﬁring angle α, and the corresponding voltage
and current waveforms are shown in Figure 3.5b. Each thyristor conducts for 120
◦
a cycle. If
the load is a pure resistive load and the ﬁring angle is 0 < α < π/6, the output voltage and
current are continuous and each thyristor is conducted in 120
◦
a cycle. If the ﬁring angle
α > π/6 (or 30
◦
), the output voltage and current are discontinuous and each thyristor is
conducting in the period between α to 150
◦
a cycle.
3.4.1 R Load Circuit
If the load is a resistive load and the ﬁring angle α ≤ π/6 (ωt = α +π/6), referring to
Figure 3.5, the output voltage is
V
O
=
3
2π
α+(5π/6)
α+(π/6)
√
2V sin(ωt) d(ωt) =
3V
√
2π
_
cos
_
α +
π
6
_
−cos
_
α +
5π
6
__
=
3
√
3V
√
2π
cos α = V
dO
cos α.
(3.24)
Here V
dO
is the output voltage corresponding to the ﬁring angle α = 0,
V
dO
=
3
√
3V
√
2π
= 1.17 V. (3.25)
For α = π/6, the output current is
I
O
=
V
O
R
=
V
dO
R
cos α = 1.17
V
R
cos α. (3.26)
If the load is a resistive load and the ﬁring angle π/6 < α < 5π/6 (ωt = α +π/6), the output
voltage is
V
O
=
3
2π
π
α+(π/6)
√
2V sin(ωt) d(ωt) =
3V
√
2π
_
cos
_
α +
π
6
_
+1
_
=
3V
√
2π
_
√
3
2
cos α −
sin α
2
+1
_
= 0.675V
_
√
3
2
cos α −
sin α
2
+1
_
.
(3.27)
The output current is
I
0
=
V
O
R
=
0.675V
R
_
√
3
2
cos α −
sin α
2
+1
_
. (3.28)
Since π/6 < α < 5π/6, the output current is always positive.
When α ≥ 5π/6, both the output voltage and current are zero. In this case, all thyristors
are reversely biased when ﬁring pulses are applied. Therefore, all thyristors cannot be
conducting.
Controlled AC/DC Converters 79
Example 3.4
A threephase halfwave controlled rectiﬁer shown in Figure 3.5 has an AC input of 200 V (rms)
at 50Hz with a load R = 10Ω. The ﬁring angle α is
a. 20
◦
.
b. 60
◦
.
Calculate the output voltage and current.
SOLUTION
a. The ﬁring angle α = 20
◦
, and the output voltage and current are continuous. Referring to
Equations 3.24 through 3.26, the output voltage and current are
V
O
= 1.17V
in
cos α = 1.17 ×200 ×cos 20
◦
= 220V,
I
O
=
V
O
R
=
220
10
= 22A.
b. The ﬁring angle α = 60
◦
, which is >π/6 = 30
◦
. The output voltage and current are discontin
uous. Referring to Equations 3.27 and 3.28, the output voltage and current are
V
O
= 0.675V
_
√
3
2
cos α −
sinα
2
+1
_
= 0.675 ×200(0.433 −0.433 +1) = 135 V,
I
O
=
V
O
R
=
135
10
= 13.5A.
3.4.2 R–L Load Circuit
Figure 3.6 shows four circuit diagrams for an R–L load. If the inductance is large enough
and can maintain current continuity, the output voltage is
V
O
= V
dO
cos α = 1.17V cos α. (3.29)
For (α < π/2), the output current is
I
O
=
V
O
R
=
V
dO
R
cos α = 1.17
V
R
cos α. (3.30)
When the ﬁring angle α is >π/2, the output voltage can have negative values, but the
output current can only have positive values. This situation corresponds to the regenerative
state.
80 Power Electronics
L
R
L
R
L
R
L
R
3V
a
3V
a
V
a
/ 3
V
a
/ 3
V
a
/ 3
V
a
/ 3
V
d0
V
a
V
a
V
a
V
d0
V
d0
V
d0
I
d
I
d
I
d
I
d
V
a
V
a
V
a
(a)
(c)
(b)
(d)
FIGURE 3.6 Threephase halfwave controlled rectiﬁers: (a) Y/Y circuit, (b) Δ/Y circuit, (c) Y/Y bending circuit,
and (d) Δ/Y bending circuit.
Example 3.5
A threephase halfwave controlled rectiﬁer shown in Figure 3.5 has an AC input of 200 V (rms)
at 50Hz with a load R = 10Ω plus a large inductance that can maintain the continuous output
current. The ﬁring angle α is
a. 20
◦
.
b. 100
◦
.
Calculate the output voltage and current.
Controlled AC/DC Converters 81
SOLUTION
a. The ﬁring angle α = 20
◦
, and the output voltage and current are continuous. Referring to
Equations 3.24 through 3.26, the output voltage and current are
V
O
= 1.17V
in
cos α = 1.17 ×200 ×cos 20
◦
= 220 V,
I
O
=
V
0
R
=
220
10
= 22A.
b. The ﬁring angle α = 100
◦
, but the large inductance can maintain the output current as con
tinuous. The output voltage and current are continuous and have negative values. Referring to
Equations 3.29 and 3.30, the output voltage and current are
V
O
= 1.17V
in
cos α = 1.17 ×200 ×cos 100
◦
= −40.6 V,
I
O
=
V
0
R
=
−40.6
10
= −4.06 A.
3.5 SixPhase HalfWave Controlled Rectifiers
Sixphase halfwave controlled rectiﬁers have two constructions: sixphase with a neutral
line circuit and double antistar with a balancechoke circuit. The following description is
based on the R load or R plus large L load.
3.5.1 SixPhase with a Neutral Line Circuit
If the AC power supply is from a transformer, four circuits can be used. The sixphase
halfwave rectiﬁers are shown in Figure 3.7.
The power supply is a sixphase balanced voltage source. Each phase is shifted by 60
◦
.
v
a
(t) =
√
2V sin ωt,
v
b
(t) =
√
2V sin(ωt −60
◦
),
v
c
(t) =
√
2V sin(ωt −120
◦
),
v
d
(t) =
√
2V sin(ωt −180
◦
),
v
e
(t) =
√
2V sin(ωt −240
◦
),
v
f
(t) =
√
2V sin(ωt −300
◦
).
(3.31)
The ﬁrst circuit is called a Y/star circuit, shown in Figure 3.7a; the second circuit is called
a Δ/star circuit, shown in Figure 3.7b; the third circuit is called a Y/star bending circuit,
shown in Figure 3.7c, and the fourth circuit is called a Δ/star bending circuit, shown in
Figure 3.7d. Each diode is conducted in 60
◦
a cycle. The ﬁring angle α = ωt −π/3 in the
82 Power Electronics
V
d0
V
d0 I
d
V
a
V
a
/
V
d0
V
d0
V
a
V
a
I
d
L R
I
d
I
d
L
L
R
R L
R
V
a
V
a
V
a
3V
a
3V
a
3
V
a
/ 3
(b) (a)
(c) (d)
FIGURE 3.7 Sixphase halfwave controlled rectiﬁers: (a) Y/Star circuit, (b) Δ/Star circuit, (c) Y/Star bending
circuit, and (d) Δ/Star bending circuit.
range of 0–2π/3. Since the load is an R–L circuit, the output voltage average value is
V
O
=
1
π/3
2π/3+α
π/3+α
√
2V sin(ωt) d(ωt) =
3
√
2V
π
_
cos
_
π
3
+α
_
−cos
_
2π
3
+α
__
=
3
√
2
π
V cos α = 1.35V cos α.
(3.32)
Controlled AC/DC Converters 83
The output voltage can have positive (α < π/2) and negative (α > π/2) values. When
α < π/2, the output current is
I
O
=
V
O
R
=
3
√
2
πR
V cos α = 1.35
V
R
cos α. (3.33)
Whenthe ﬁring angle α is >π/2, the output voltage canhave negative values, but the output
current can only have positive values. This situation corresponds to the regenerative state.
3.5.2 Double Antistar with a BalanceChoke Circuit
If the ACpower supply is froma transformer, two circuits can be used. Sixphase halfwave
controlled rectiﬁers are shown in Figure 3.8. The threephase double antistar with balance
choke controlled rectiﬁers is shown in Figure 3.8. The ﬁrst circuit is called a Y/YY circuit,
shown in Figure 3.8a, and the second circuit is called a Δ/YYcircuit, shown in Figure 3.8b.
Each device is conducted in 120
◦
a cycle. The ﬁring angle α = ωt −π/6. Since the load is an
R–L circuit, the average output voltage value is
V
O
=
1
2π/3
5π/6+α
π/6+α
√
2V sin(ωt) d(ωt) =
3
√
3
√
2π
V cos α = 1.17V cos α. (3.34)
The output voltage can have positive (α < π/2) and negative (α > π/2) value. The output
current is
I
O
=
V
O
R
= 1.17
V
R
cos α. (3.35)
Whenthe ﬁringangle αis >π/2, the output voltage canhave a negative value, but the output
current can have only a positive value. This situation corresponds to the regenerative state.
V
a
V
a
I
d
L R
V
d0
3V
a
V
a
V
d0
I
d
R L
(a) (b)
FIGURE 3.8 Threephase double antistar withbalancechoke controlledrectiﬁers: (a) Y/YYcircuit and(b) Δ/YY
circuit.
84 Power Electronics
These circuits have the following advantages:
• Alarge output current can be obtained since there are two threephase halfwave
rectiﬁers.
• The output voltage has a lower ripple since each thyristor conducts at 120
◦
.
3.6 ThreePhase FullWave Controlled Converters
Athreephase bridge is fully controlled when all six bridge devices are thyristors, as shown
in Figure 3.9. The frequency of the output voltage ripple is six times the supply frequency.
The average output voltage is given by
V
O
=
3
π
α
−π/3+α
v
ry
d(ωt) =
3
π
α
−π/3+α
√
3
√
2V sin
_
ωt +2π
3
_
d(ωt)
=
3
√
3
π
√
2V cos α = 2.34V cos α.
(3.36)
The equation illustrates that the rectiﬁer DC output voltage V
O
is positive when the ﬁring
angle α is <π/2 and becomes negative for a ﬁring angle α > π/2. However, the DC current
I
O
is always positive irrespective of the polarity of the DC output voltage.
Whenthe rectiﬁer produces a positive DCvoltage, the power is deliveredfromthe supply
to the load. With a negative DC voltage, the rectiﬁer operates in an inverter mode and the
power is fed from the load back to the supply. This phenomenon is usually used in elec
trical drive systems where the motor drive is allowed to decelerate and the kinetic energy
of the motor and its mechanical load is converted to electrical energy and then sent back to
the power supply by the thyristor rectiﬁer for fast dynamic braking. The power ﬂow in the
thyristor rectiﬁer is therefore bidirectional.
Figure 3.10 shows some waveforms corresponding to various ﬁring angles. The shaded
area Ais the device conduction period and the corresponding rectiﬁed voltage.
The rms value of the output voltage is given by
V
rms
=
¸
¸
¸
¸
_
3
π
α
−π/3+α
_
√
3
√
2V sin
_
ωt +2π
3
__
2
d(ωt) =
√
2
√
6V
_
1
4
+
3
√
3
8π
cos 2α
_
1/2
.
(3.37)
The line current i
r
can be expressed in a Fourier series as
i
r
=
2
√
3
π
I
DC
_
sin(ωt −ϕ
1
) −
1
5
sin 5(ωt −ϕ
1
)
−
1
7
sin 7(ωt −ϕ
1
) +
1
11
sin 11(ωt −ϕ
1
) +
1
13
sin 13(ωt −ϕ
1
) −· · ·
_
,
(3.38)
Controlled AC/DC Converters 85
a
b
+
–
Load Highly inductive
load
On
v
0
0
0
0
0
0
(a)
(b)
C
n
I
a
= I
1
I
a
= I
1
I
b
I
O
= I
a
I
T1
T
1
T
5
, T
6
T
1
T
3
T
5
T
5 T
4
T
2
T
6
v
cb
i
T1
i
T1
+l
a
+I
a
–I
a
+I
a
I
a
I
O
p
v
ab
v
ac
v
bc
v
ba
v
ca
v
cb
v
O
v
ch
v
bh
v
ah
a
T
1
, T
6
T
1
, T
2
T
2
, T
3
V
m a
T
3
, T
4
T
4
, T
5
T
5
, T
6
T
3
T
6
T
2
T
4
I
c
I
T4
T
5
V
O
p
6
p
6
+ a
5p
6
+ a
7p
6
+ a
5p
6
+ a
p
6
+ a
11p
6
+ a
p
6
+ a
3p
2
2p
wt
p
2
a
FIGURE 3.9 Threephase bridge fully controlled rectiﬁer: (a) circuit and (b) waveforms.
where φ
1
is the phase angle between the supply voltage v
r
and the fundamental frequency
line current i
r1
. The rms value of i
r
can be calculated using
I
r
=
¸
¸
¸
¸
_
1
2π
2π
0
i
r
d(ωt) =
¸
¸
¸
¸
_
1
2π
⎡
⎣
60+α
−60+α
I
2
DC
d(ωt) +
240+α
120+α
I
2
DC
d(ωt)
⎤
⎦
=
_
2
3
I
DC
= 0.816I
DC
. (3.39)
86 Power Electronics
a
a
a
a = 90°
a = 60°
a = 30°
a = 0°
0
0
0
0
A
A
FIGURE 3.10 Rectiﬁed voltage waveforms for various ﬁring angles.
from which the THD for the line current i
r
is
THD =
_
I
2
r
−I
2
r1
I
r1
=
(0.816I
DC
)
2
−(0.78I
DC
)
2
0.78I
DC
= 0.311, (3.40)
where I
r1
is the rms value of i
r1
(i.e., (
√
6/π)I
DC
).
Example 3.6
A threephase fullwave controlled rectiﬁer shown in Figure 3.9 has an AC input of 200 V (rms)
at 50Hz with a load R = 10Ω plus a large inductance that can maintain the continuous output
current. Given that the ﬁring angle α is (a) 30
◦
and (b) 120
◦
, calculate the output voltage and
current.
SOLUTION
a. With a ﬁring angle α = 30
◦
and the output voltage and current continuous, by referring to
Equation 3.36, the output voltage and current are
V
O
= 2.34V cos α = 2.34 ×200cos 30
◦
= 234V,
I
O
=
V
O
R
=
234
10
= 23.4A.
Controlled AC/DC Converters 87
b. With a ﬁring angle α = 120
◦
and the output voltage and current continuous and with negative
values, by referring to Equation 3.36, the output voltage and current are
V
O
= 2.34V cos α = 2.34 ×200cos 120
◦
= −234 V,
I
O
=
V
O
R
=
−234
10
= −23.4A.
3.7 Multiphase FullWave Controlled Converters
Figure 3.11 shows the typical conﬁguration of a 12pulse seriestype controlled rectiﬁer.
There are two identical threephase controlledrectiﬁers to be used. Two sixpulse controlled
rectiﬁers are powered by a phaseshifting transformer with two secondary windings in
delta and star connections. Therefore, the phase angle between both secondary windings
shifts 30
◦
.
The DC outputs of the rectiﬁers are connected in series. To dominate lowerorder har
monics in the line current i
A
, the linetoline voltage v
a1b1
of the starconnected secondary
winding is in phase with the primary voltage v
AB
, while the deltaconnected secondary
winding voltage v
a1b1
leads the primary voltage v
AB
by
δ = ∠v
a2b2
−∠V
AB
= 30
◦
. (3.41)
The rms linetoline voltage of each secondary winding is
V
a1b1−rms
= V
a2b2−rms
=
V
AB−rms
2
, (3.42)
B
A
C
v
C i
C
b
1
a
1
c
1
i
a1
V
d
I
d
i
a2b2
i
c2a2
v
AB
v
A
v
B
i
B
i
A
i
a2
i
b2c2
v
a2b2
a
2
b
2
c
2
i
b2
i
c2
i
A
= i'
a1
+ i'
c2a2
FIGURE 3.11 Twelvepulse controlled rectiﬁer.
88 Power Electronics
wt
wt
wt
wt
wt
wt
wt
2p
4p/3
5p/6
2p/3
p/6 0
0
0
0
0
0
0
i
a1
i
a2
i
c2
i
c2a2
i'
c2a2
i'
a1
i
A
I
d
I
d
2I
d
I
d
p
3
I
d
I
d
I
d
/2
I
d
/2
3
3
2
I
d
3 2
I
d
3 2
I
d
3
FIGURE 3.12 Current waveforms.
from which the turn’s ratio of the transformer can be determined by
N
1
N
2
= 2 for Y/Y,
N
1
N
3
=
2
√
3
for Y/Δ.
(3.43)
Consider an idealized 12pulse rectiﬁer where the line inductance L
s
and the total leakage
inductance L
lk
of the transformer are assumed to be zero. The current waveforms are illus
trated in Figure 3.12, where i
a1
and i
c2a2
are the secondary line primary currents referred
from the secondary side, and i
A
is the primary line current given by i
A
= i
a1
+i
c2a2
.
The secondary line current i
a1
can be expressed as
i
a1
=
2
√
3
π
I
d
_
sin ωt −
1
5
sin 5ωt −
1
7
sin 7ωt +
1
11
sin 11ωt +
1
13
sin 13ωt +· · ·
_
, (3.44)
Controlled AC/DC Converters 89
where ω = 2πf is the angular frequencyof the supplyvoltage. Since the waveformof current
i
a1
is of halfwave symmetry, it does not contain any evenorder harmonics. Current i
A
does
not contain any triple harmonics either due to the balanced threephase system.
Other secondary currents such as i
a2
lead i
a1
by 30
◦
, and the Fourier expression is
i
a2
=
2
√
3
π
I
d
[sin(ωt +30
◦
) −
1
5
sin 5(ωt +30
◦
) −
1
7
sin 7(ωt +30
◦
)
+
1
11
sin 11(ωt +30
◦
) +
1
13
sin 13(ωt +30
◦
) · · · ].
(3.45)
The waveform for the referred current i
a1
in Figure 3.12 is identical to i
a1
except that its
magnitude is halved due to the turn’s ratio of the Y/Yconnected windings. The current i
a1
can be expressed in Fourier series as
i
a1
=
√
3
π
I
d
_
sin ωt −
1
5
sin 5 ωt −
1
7
sin 7ωt +
1
11
sin 11ωt +
1
13
sin 13ωt · · ·
_
. (3.46)
The phase currents i
b2a2
, i
a2c2
, and i
c2b2
can be derived from the line currents using the
relationships in Equation 3.47:
⎛
⎝
i
a2b2
i
b2c2
i
c2a2
⎞
⎠
=
1
3
⎛
⎝
−1 1 0
0 −1 1
1 0 −1
⎞
⎠
⎛
⎝
i
a2
i
b2
i
c2
⎞
⎠
. (3.47)
These currents have a stepped waveform, each step being of 60
◦
duration and the height
of the steps being I
d
/3 and 2I
d
/3. The currents i
a2b2
, i
b2a2
, and i
c2a2
need to be multiplied by
√
3/2 when they are referredto the primary side. Using Equation 3.45 andsimilar equations
for i
b2
and i
c2
, one can derive Fourier expressions for i
a2b2
, i
b2c2
, and i
c2a2
. For example,
i
a2b2
=
1
3
(i
b2
−i
a2
), i
b2c2
=
1
3
(i
c2
−i
b2
), and i
c2a2
=
1
3
(i
a2
−i
c2
).
Therefore,
i
c2a2
=
1
3
2
√
3
π
I
d
_
sin(ωt +30
◦
) −
1
5
sin 5(ωt +30
◦
) −
1
7
sin 7(ωt +30
◦
)
+
1
11
sin 11(ωt +30
◦
) · · · +sin(ωt +150
◦
) −
1
5
sin 5(ωt +150
◦
)
−
1
7
sin 7(ωt +150
◦
) +
1
11
sin 11(ωt +150
◦
) · · ·
_
.
(3.48)
By simplifying Equation 3.48 and multiplying with
√
3/2, we have
i
c2a2
=
√
3
π
I
E
_
sin ωt +
1
5
sin 5ωt +
1
7
sin 7ωt +
1
11
sin 11 ωt · · ·
_
. (3.49)
As can be seen from Equation 3.48, the phase angles of some harmonic currents are altered
due to the Y/Δconnected windings. As a result, the current i
c2a2
does not maintain the
same wave shape as i
a1
. The line current i
A
can be found from
i
A
= i
a1
+i
c2a2
=
2
√
3
π
I
d
_
sin ωt +
1
11
sin 11ωt +
1
13
sin 13 ωt · · ·
_
,
90 Power Electronics
where the two dominant current harmonics, the 5th and 7th, are cancelled in addition to
the 17th and 19th.
The THD of the secondary and primary line currents i
a1
and i
A
can be determined by
THD(i
a1
) =
_
I
2
a1
−I
2
a1,1
I
a1,1
=
_
I
2
a1,5
+I
2
a1,7
+· · ·
I
a1,1
(3.50)
and
THD(i
A
) =
_
I
2
A
−I
2
A,1
I
A,1
=
_
I
2
A,11
+I
2
A,13
+· · ·
I
a1,1
. (3.51)
The THD of the primary line current i
A
in the idealized 12pulse rectiﬁer is reduced by
nearly 50% compared to that of i
a1
.
3.7.1 Effect of Line Inductance on Output Voltage (Overlap)
We now investigate a threephase fullycontrolled rectiﬁer as shown in Figure 3.9a. We
partially redraw the circuit in Figure 3.13 (only show phase A and phase C). In practice,
the cable length from phase A to A
(or C to C
) has an inductance (L). The commutation
process (e.g., for i
a
to replace i
c
) will take a certain time interval. This affects the voltage at
point P to neutral point N and the ﬁnal half output voltage is V
PN
.
During the commutation process (e.g., for i
A
to replace i
C
), Kirchhoff’s voltage law(KVL)
for the commutation loop and Kirchhoff’s current law (KCL) at point P give the output
current I
O
, which is ﬁltered by a large inductance, and this implies that its change is much
slower than that of i
C
and i
A
. We can write
v
AN
−v
CN
= L
di
A
dt
−L
di
C
dt
, (3.52)
i
A
+i
C
= I
O
⇒
di
A
dt
+
di
C
dt
=
dI
O
dt
⇒ 0, (3.53)
di
A
dt
= −
di
C
dt
. (3.54)
From Equations 3.52 and 3.54,
v
AN
−v
CN
= L
di
A
dt
−L
di
C
dt
⇒ L
di
A
dt
=
v
AN
−v
CN
2
. (3.55)
V
AN
A
C
A'
C'
V
CN
T
1
T
5
i
a
i
c
P
L
L
N
I
O
FIGURE 3.13 Effect of line inductance.
Controlled AC/DC Converters 91
v
CN
v
AN
A
u
I
d
I
d
i
c
= i
5
(a
+ u)
0
0
5 1
i
a
= i
1
v
PN
v
BN
v
CN
3 5
4 2
wt
wt
(wt = 0)
6
u
a
a
FIGURE 3.14 Waveforms affected by line inductance.
This allows one to derive V
PN
. Thus, V
PN
takes the midpoint value between V
AN
and V
CN
during commutation. The output voltage waveform is shown in Figure 3.14.
v
PN
= v
AN
−L
di
A
dt
= v
AN
−
v
AN
−v
CN
2
⇒ v
PN
=
v
AN
+v
CN
2
. (3.56)
Thus, the integral of V
PN
will involve two parts: one from ﬁring angle α to (α +u) where u
is the overlap angle and, subsequently, the other from(α +u) to the next phase ﬁred, where
commutation happened and the v
PN
is
v
PN
=
3
2π
⎡
⎢
⎣
π/6+α+u
π/6+α
v
AN
+v
CN
2
d(ωt) +
π/6+α+2π/3
π/6+α+u
v
AN
d(ωt)
⎤
⎥
⎦
. (3.57)
Hence
v
PN
=
3
2π
⎡
⎢
⎣
π/6+α+u
π/6+α
v
AN
+v
CN
2
d(ωt) +
π/6+α+2π/3
π/6+α+u
v
AN
d(ωt)
+
π/6+α+u
π/6+α
v
AN
−v
CN
2
d(ωt) −
π/6+α+u
π/6+α
v
AN
−v
CN
2
d(ωt)
⎤
⎥
⎦
Note that the ﬁrst integral is the original integral involving V
AN
for the full 120
◦
interval.
The second interval can be linked to the derivative of current i
A
for the commutation
92 Power Electronics
interval
π/6+α+u
π/6+α
v
AN
−v
CN
2
d(ωt) =
π/6+α+u
π/6+α
_
L
di
A
dt
_
ω
ω
d(ωt)
=
i
end
i
start
Lωd(i
A
) = Lω[I
O
+0] = LωI
O
.
(3.58)
Therefore, by an identical analysis for the bottom three thyristors, the output voltage is
V
O
= 2v
PN
=
3
√
6
π
V cos α −
3
π
LωI
O
for 0
◦
< α < 180
◦
. (3.59)
Thus, the commutation interval duration due to the line inductance modiﬁes the output
voltage waveform (ﬁnite time for current change) and this changes the average output
voltage by a reduction of (3/π)Lω. This can be compensated for by feedforward.
The above ﬁgure shows how V
PN
is affected during the commutation interval u. It takes
the midpoint value between the incoming phase (V
AN
) and outgoing phase (V
CN
) voltages.
The corresponding currents i
A
and i
C
can be seen to rise and fall at ﬁnite rates. The rate
of current change will be slower for high values of line interference (EMI) and certain
standards limit this rise time.
Homework
3.1. Afullwave controlled rectiﬁer shown in Figure 3.4 has a source of 120 V (rms) at
60 Hz, R = 10 Ω, L = 20 mH, and α = 60
◦
.
a. Determine an expression for load current.
b. Determine the average load current.
c. Determine the average output voltage.
3.2. Athreephase halfwave controlled rectiﬁer shown in Figure 3.5 has an AC input
of 240 V (rms) at 60 Hz with a load R = 100 Ω. Given that are ﬁring angle α is (a)
15
◦
and (b) 75
◦
, calculate the output voltage and current.
3.3. Athreephase fullwave controlled rectiﬁer shown in Figure 3.9 has an AC input
of 240 V (rms) at 60 Hz with a load R = 100 Ω with high inductance. Given that
the ﬁring angle α is (a) 20
◦
and (b) 100
◦
, calculate the output voltage and current.
References
1. Luo, F. L., Ye, H., and Rashid M. H. 2005. Digital Power Electronics and Applications. New York:
Academic Press.
2. Rashid, M. H. 2007. Power Electronics Handbook (2nd edition). Boston: Academic Press.
Controlled AC/DC Converters 93
3. Dorf, R. C. 2006. The Electrical Engineering Handbook (3rd edition). Boca Raton: Taylor &Francis.
4. Luo, F. L., Jackson, R. D., and Hill R. J. 1985. Digital controller for thyristor current source.
IEEProceedings Part B, 132, 46–52.
5. Luo, F. L. and Hill, R. J. 1985. Disturbance response techniques for digital control systems. IEEE
Transactions on Industrial Electronics, 32, 245–253.
6. Luo, F. L. and Hill, R. J. 1985. Minimisation of interference effects in thyristor converters by
feedback feedforward control. IEEE Transactions on Measurement and Control, 7, 175–182.
7. Luo, F. L. and Hill, R. J. 1986. Inﬂuence of feedback ﬁlter on system stability area in digitally
controlled thyristor converters. IEEE Transactions on Industry Applications, 18–24.
8. Luo, F. L. and Hill, R. J. 1986. Fast response and optimum regulation in digitallycontrolled
thyristor converters. IEEE Transactions on Industry Applications, 22, 10–17.
9. Luo, F. L. and Hill, R. J. 1986. System analysis of digitallycontrolled thyristor converters. IEEE
Transactions on Measurement and Control, 8, 39–45.
10. Luo, F. L. and Hill, R. J. 1986. System optimisation—selfadaptive controller for digitally
controlled thyristor current controller. IEEE Transactions on Industrial Electronics, 33, 254–261.
11. Luo, F. L. and Hill, R. J. 1987. Stability analysis of thyristor current controllers. IEEE Transactions
on Industry Applications, 23, 49–56.
12. Luo, F. L. and Hill, R. J. 1987. Current source optimisation in ACDC GTO thyristor converters.
IEEE Transactions on Industrial Electronics, 34, 475–482.
13. Luo, F. L. and Hill, R. J. 1989. Microprocessorbased control of steel rolling mill digital DC
drives. IEEE Transactions on Power Electronics, 4, 289–297.
14. Luo, F. L. and Hill, R. J. 1990. Microprocessorcontrolled power converter using singlebridge
rectiﬁer and GTO current switch. IEEE Transactions on Measurement and Control, 12, 2–8.
15. Muth, E. J. 1977. Transform Method with Applications to Engineering and Operation Research. New
Jersey: PrenticeHall.
16. Oliver, G., Stefanovic, R., and Jamil, A. 1979. Digitally controlled thyristor current source. IEEE
Transactions on Industrial Electronics and Control Instrumentation, 185–191.
17. Fallside, F. andJackson, R. D. 1969. Direct digital control of thyristor ampliﬁers. IEEProceedings,
Part B, 873–878.
18. Arrillaga, J., Galanos, G., and Posner, E. T. 1970. Direct digital control of HVDC converters.
IEEE Transactions on Power Apparatus and Systems, 2056–2065.
19. Daniels, A. R. andLipczyski, R. T. 1969. Digital ﬁringangle circuit for thyristor motor controllers.
IEEProceedings, Part B, pp. 245–256.
20. Dewan, S. B. and Dunford, W. G. 1983. A microprocessorbased controller for a threephase
controlled bridge rectiﬁers. IEEE Transactions on Industry Applications, 113–119.
21. Cheung, W. N. 1971. The realisation of converter control using sampledanddelay method.
IEEProceedings, Part B, pp. 701–705.
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4
Implementing Power Factor Correction in
AC/DC Converters
Power factor correction (PFC) is the capacity for generating or absorbing the reactive power
produced by a load [1–3]. Power quality issues and regulations require rectiﬁer loads to be
connected to the utility to achieve high PFs. This means that a PFC rectiﬁer needs to draw
close to a sinusoidal current in phase with the supply voltage, unlike phasecontrolled
rectiﬁers (making the PFC rectiﬁer “look like” a resistive load to the utility).
4.1 Introduction
Refer to the following formula [3]:
PF =
DPF
_
1 +THD
2
,
where DPF is the displacement power factor and THD is the total harmonic distortion. We
can explain DPF as the fundamental harmonic of the current that has a delay angle θ (or
φ), that is, DPF = cos θ (or cos φ). THD is calculated using Equation 1.20. Most AC/DC
uncontrolled and controlled rectiﬁers have poor PFs, except for the singlephase fullwave
uncontrolled bridge (Graetz) rectiﬁer with R load. All threephase uncontrolled and con
trolled rectiﬁers have the input current fundamental harmonic delaying its corresponding
voltage by an angle 30
◦
plus α, where α is the ﬁring angle of the controlled rectiﬁer. Con
sequently, AC/DC rectiﬁers naturally have poor PFs. In order to maintain power quality,
PFC is necessary. Implementing the PFC means
• Reducing the phase difference between the line voltage and current (DPF = >1).
• Shaping the line current to a sinusoidal waveform (THD = >0).
The ﬁrst condition requires that the fundamental harmonic of the current has a delay angle
θ = >0
◦
. The second condition requires that the harmonic components are as small as
possible. In recent research, the following methods have been used to implement PFC:
1. DC/DC converterized rectiﬁers.
2. Pulsewidth modulation (PWM) boosttype rectiﬁers.
3. Tappedtransformer converters.
95
96 Power Electronics
4. Singlestage PFC AC/DC converters.
5. VIENNArectiﬁers.
6. Other methods.
4.2 DC/DC Converterized Rectifiers
Afullwave diode rectiﬁer with R load has a high PF. If this rectiﬁer supplies an R–C load,
the PFis poor. Usinga DC/DCconverter inthis circuit will improve the PF. The PFCrectiﬁer
circuit is shown in Figure 4.1.
The resistor emulation of the PFC rectiﬁer is carried out by the DC/DC converter. The
input to the DC/DC converter is a fully rectiﬁed sinusoidal voltage waveform. A con
stant DC voltage is maintained at the output of the PFC rectiﬁer. The DC/DC converter is
switchedat a switching frequency f
s
that is many times higher than the line frequency f . The
input current waveform into the diode bridge is modiﬁed to contain a strong fundamental
sinusoid at the line frequency but with harmonics at a frequency several times higher than
the line frequency.
Since the switching frequency f
s
is very high in comparison with the line frequency f , the
input andoutput voltages of the PFCrectiﬁer may be consideredas constant throughout the
switching period. Thus, the PFC rectiﬁer can be analyzed like a regular DC/DC converter:
v
s
= V
s
sin θ,
v
1
= V
s
 sin θ with θ = 2πft.
(4.1)
The voltage transfer ratio of the PFC rectiﬁer is required to vary with angle θ in a half
supply period. The voltage transfer ratio of the DC/DC converter is
T
vv
(θ) =
V
DC
V
1
(θ)
=
V
DC
V
s
sin θ
with f
s
f , (4.2)
where V
DC
is the local average DC output voltage.
T
vv
in a supply period is shown in Figure 4.2. The high voltage transfer ratio in the
vicinity of ωt = 0
◦
and 180
◦
can be achieved by using converters such as boost, buck–boost,
or ﬂyback converters.
R
D
1
–
+
D
4
D
3
D
2
V
DC
V
1
i
O
i
1
i
s
V
s
AC
DC/DC
converter
C
FIGURE 4.1 PFC rectiﬁer.
Implementing Power Factor Correction in AC/DC Converters 97
p/2
p
0
0
0
I
O
2I
O
i
O
T
vv
v
1
3p/2
2p
2p p
q
q
q
FIGURE 4.2 DC/DC converter output current required.
To prove this technique, a fullwave diode rectiﬁer with R–C load (R = 100 Ω and C =
100 μF) plus a buck–boost converter is investigated. Before applying any converter, the
input voltage and current waveforms are shown in Figure 4.3. The fundamental harmonic
of the input current delays the input voltage by an angle θ = 33.45
◦
.
The harmonics (FFT spectrum) of the input current are shown in Figure 4.4.
The harmonics, values are listed in Table 4.1.
1000.00
–10.00
–5.00
0.0
5.00
10.00
–400.00
–200.00
0.0
200.0
400.0
I
i
n
1010.00 1020.00
Time (ms)
1040.00
Time 0.0018588
Frequency 537.981
V
in
172.308
I
in
Measure
6.67783
V
i
n
FIGURE 4.3 Input voltage and current waveforms.
98 Power Electronics
Frequency (kHz)
1.00 0.80 0.60 0.40 0.20 0.0
0.0
1.00
2.00
3.00
4.00
5.00
I
i
n
(49.9, 4.546)
(150.1, 2.645)
(549.6, 0.523) (649.6, 0.473)
(750.67, 0.288)
(848.9, 0.295)
(949.9,
0.316)
(449.5, 0.738)
(349.4, 0.746)
(250.2, 0.833)
FIGURE 4.4 FFT spectrum of the input current.
The THD of the input current is obtained as THD
2
=
α
i=2
(I
i
/I
1
)
2
= 0.4625 and the DPF
is obtained as cos(33.45
◦
) = 0.834. Therefore,
PF =
DPF
_
1 +THD
2
=
cos 33.45
√
1 +0.4625
= 0.689. (4.3)
A buck–boost converter (see Figure 5.7 in Chapter 5) is used for this purpose. The circuit
diagram is shown in Figure 4.5.
The input voltage is 311 V (peak)/50 Hz. The duty ratio k is calculated as 20 chopping
periods for ahalfcycle. For one cycle, there are 40choppingperiods (maintainthe same duty
ratio) corresponding to its frequency of 2 kHz. The inductance value was set as L = 0.6 mH
and the capacitance value as 800 μF to maintain the output voltage at 200 V. The duty ratio
k was calculated to set a constant DC output voltage of 200 V (see Table 4.2).
The duty ratio k waveformin twoandahalf cycles is shown in Figure 4.6 and the switch
(transistor) turnon and turnoff in a halfcycle are shown in Figure 4.7.
TABLE 4.1
Harmonic Current Values of Normal AC to DC Converter
Current Frequency (Hz) Fourier Component
I1 50 4.546
I3 150 2.645
I5 250 0.833
I7 350 0.746
I9 450 0.738
I11 550 0.523
I13 650 0.473
I15 750 0.288
I17 850 0.295
I19 950 0.316
Implementing Power Factor Correction in AC/DC Converters 99
311Vp
V
duty_ra1
V
ramp
V
~
+
–
L = 0.6mH
C = 100m R = 100
FIGURE 4.5 Buck–boost converter used for PFC with R–C load.
The input voltage and current waveforms are shown in Figure 4.8. From the waveform
we can see that the fundamental harmonic delay angle θ is about 3.21
◦
. The output voltage
of the buck–boost converter is 200 V, as shown in Figure 4.9.
The FFT spectrum of the input current is shown in Figure 4.10 and the harmonic
components are shown in Table 4.3.
TABLE 4.2
Duty Ratio k in the 20 Chopping Periods in a HalfCycle
ωt (deg) Input Voltage = 311 sin(ωt) (V) k
9 48.65 0.804
18 96.1 0.676
27 141.2 0.586
36 182.8 0.522
45 219.9 0.476
54 251.6 0.443
63 277.1 0.419
72 295.8 0.403
81 307.2 0.394
90 311 0.391
99 307.2 0.394
108 295.8 0.403
117 277.1 0.419
126 251.6 0.443
135 219.9 0.476
144 182.8 0.522
153 141.2 0.586
162 96.1 0.676
171 48.65 0.804
180 0 ∞
100 Power Electronics
1.00
0.80
0.60
0.40
0.20
0.0
1000.00 1010.00 1020.00 1030.00
Time (ms)
1040.00 1050.00
V
d
u
t
y
_
r
a
t
i
o
FIGURE 4.6 Duty ratio k waveform in twoandahalf cycles.
V
s
w
i
t
c
h
1.00
0.80
0.60
0.40
0.20
0.0
1000.00 1000.10 1000.20 1000.30
Time (ms)
1000.40 1000.50
FIGURE 4.7 Switch turnon and turnoff waveform in a halfcycle.
From the data in Table 4.3, the THD of the input current is obtained as THD
2
=
α
i=2
(I
i
/I
1
)
2
= 0.110062 and DPF is obtained as cos(3.21
◦
) = 0.998431. Therefore,
PF =
DPF
_
1 +THD
2
=
cos 3.21
√
1 +0.110062
= 0.95. (4.4)
Using this technique, PF is signiﬁcantly improved from 0.689 to 0.95.
V
i
n
I
i
n
1000.00 1010.00 1020.00
Time (ms)
1030.00 1040.00
15.00
–15.00
–10.00
–5.00
10.00
5.00
0.0
400.00
200.00
–200.00
–400.00
0.0
FIGURE 4.8 Input voltage and current waveforms.
Implementing Power Factor Correction in AC/DC Converters 101
100.00
V
l
o
a
d
0.0
–100.00
–200.00
–300.00
–400.00
0.0 0.50 1.00
Time (s)
1.50 2.00
FIGURE 4.9 Output voltage of the buck–boost converter.
3.00
2.50
2.00
1.50
1.00
0.50
0.0
–0.50
0.0 0.20 0.40
Frequency (kHz)
0.60 0.80
(949.062,
0.011)
(850.6, 0.1)
(750.7, 0.01)
(549.7, 0.077)
(451.26, 0.295)
(149.5, 0.664)
(50, 2680)
I
i
n
(349.5, 0.379)
(250.2, 0.313)
(649.5, 0.071)
FIGURE 4.10 FFT spectrum of the input current.
TABLE 4.3
Harmonic Components of the Input Current
Current Frequency (Hz) Fourier Component
I1 50 2.680
I3 150 0.664
I5 250 0.313
I7 350 0.379
I9 450 0.295
I11 550 0.077
I13 650 0.071
I15 750 0.010
I17 850 0.100
I19 950 0.011
102 Power Electronics
From the above investigation, we know that using a buck–boost converter to implement
PFCcanbe successful, but the output voltage has a negative polarity. If a P/OLuoconverter
or SEPIC or a P/O buck–boost converter is used, we can obtain the P/O voltage.
Example 4.1
A P/O Luoconverter (see Figure 5.11 in Chapter 5) is used to implement PFC in a singlephase
diode rectiﬁer with an R–C load. The AC supply voltage is 240 V/50Hz and the required output
voltage is 200 V. The switching frequency is 4kHz. Determine the duty cycle k in a half supply
period (10ms). Other component values for reference are the following: R = 100Ω, C = C
O
=
20μF, and L
1
= L
2
= 10mH.
SOLUTION
Since the supply frequency is 50Hz and the switching frequency is 4kHz, there are 40 switching
periods in a half supply period (10ms). The voltage transfer gain of the P/O Luoconverter is
V
O
=
k
1 −k
V
in
,
k =
V
O
V
O
+V
in
=
200
200 +240
√
2sinωt
.
Duty cycle k is listed in Table 4.4.
4.3 PWM BoostType Rectifiers
Using this method, we can obtain the UPF. In order to obtain UPF, that is, PF=1, the current
from the diode bridge must be identical in shape and in phase with the supply voltage
waveform. Hence,
i
1
= I
s
 sin θ. (4.5)
The input and output powers averaged over a switching period are
P
in
= V
s
I
s
sin
2
θ,
P
O
= V
DC
i
O
.
(4.6)
Assuming a lossless rectiﬁer, the output current requirement is determined as
i
O
=
V
s
I
s
V
DC
sin
2
θ. (4.7)
The input and output powers averaged over a supply period are
P
in
=
V
s
I
s
2
,
P
O
= V
DC
I
O
,
(4.8)
where I
O
is the averaged DC output current.
Implementing Power Factor Correction in AC/DC Converters 103
TABLE 4.4
Duty Ratio k in the 40 Chopping Periods in a HalfCycle
ωt (deg) Input Voltage = 240
√
2 sin(ωt) (V) k
4.5 26.6 0.88
9 53.1 0.79
13.5 79.2 0.72
18 104.9 0.66
22.5 129.9 0.61
27 154.1 0.56
31.5 177.3 0.53
36 199.5 0.5
40.5 220.4 0.48
45 240 0.45
49.5 258.1 0.44
54 274.6 0.42
58.5 289.4 0.41
63 302.4 0.4
67.5 313.6 0.39
72 322.8 0.38
76.5 330 0.377
81 335.2 0.374
85.5 338.4 0.371
90 339.4 0.37
94.5 338.4 0.371
99 335.2 0.374
103.5 330 0.377
108 322.8 0.38
112.5 313.6 0.39
117 302.4 0.4
121.5 289.4 0.41
126 274.6 0.42
130.5 258.1 0.44
135 240 0.45
139.5 220.4 0.48
144 199.5 0.5
148.5 177.3 0.53
153 154.1 0.56
157.5 129.9 0.61
162 104.9 0.66
166.5 79.2 0.72
171 53.1 0.79
175.5 26.6 0.88
180 0 ∞
104 Power Electronics
The instantaneous output currents are
i
O
=
V
s
I
s
V
DC
sin
2
θ = 2I
O
sin
2
θ
= I
O
(1 −cos 2θ).
(4.9)
The DC/DC converter output current required for a UPF, as a function of angle θ, is shown
in Figure 4.2.
Because the input current to the DC/DCconverter is to be shaped, the DC/DCconverter
is operated in a currentregulated mode.
4.3.1 DCSide PWM BoostType Rectiﬁer
The DCside PWM boosttype rectiﬁer is shown in Figure 4.11 where i
∗
1
is the reference
of the desired value of the current i
1
. Here i
∗
1
has the same waveform shape as v
s
. The
amplitude of i
∗
1
should be able to maintain the output voltage at a desired or reference level
v
∗
dc
, in spite of the variation on load and the ﬂuctuation of line voltage from its nominal
value. The waveformof i
∗
1
is obtained by measuring v
s
 and multiplying it by the ampliﬁed
error between v
∗
dc
and v
dc
. The actual current i
1
is measured. The status of the switch in the
DC/DC converter is controlled by comparing the actual current with i
∗
1
.
Once i
∗
1
and i
1
are available, there are various ways of implementing the currentmode
control of the DC/DC converter.
4.3.1.1 ConstantFrequency Control
Here, the switching frequency f
s
is kept constant. When i
1
reaches i
∗
1
, the switch in the
DC/DC converter is turned off. The switch is turned on by a clock period at a ﬁxed fre
quency f
s
. This method is likely an openloop control. The operation indication is shown in
Figure 4.12.
Example 4.2
A boost converter (see Figure 5.5 in Chapter 5) is used to implement PFC in the circuit shown
in Figure 4.11a. The switching frequency is 2kHz, L = 10mH, C
d
= 20μF, R = 100Ω, and the
output voltage V
O
= 400V. The AC supply voltage is 240 V/50Hz. Determine the duty cycle k in
a half supply period (10ms).
SOLUTION
Since the supply frequency is 50Hz and the switching frequency is 2kHz, there are 20 switching
periods in a half supply cycle (10ms). The voltage transfer gain of the boost converter is
V
O
=
1
1 −k
V
in
,
k =
V
O
−V
in
V
O
=
400 −240
√
2 sinωt
400
.
The duty ratio k is listed in Table 4.5.
Implementing Power Factor Correction in AC/DC Converters 105
R
D
1
+
D
4
D
3
D
2
i
s
i
1
i
O
V
s
V
1 V
dc
C
d
–
L
S
0
0
wt
(q)
wt
(q)
v
1
i
1
v
s
i
s
PI
regulator
Multiplier
Current
mode
control
Gate
signal
(s)
V
dc
(actual)
V
*
dc
Error
i
*
1
i
1
(measured)
v
s
(d)
(c)
(b)
(a)
FIGURE 4.11 UPF diode rectiﬁer with feedback control: (a) circuit, (b) input voltage and current, (c) output
voltage and current of the diode rectiﬁer, and (d) control block diagram.
4.3.1.2 ConstantToleranceBand (Hysteresis) Control
Here, the constant i
1
is controlledsothat the peaktopeakripple (I
rip
) ini
1
remains constant.
With a preselected value of I
rip
, i
1
is forced to be within the tolerance band (i
∗
1
+I
rip
/2) and
(i
∗
1
−I
rip
/2) bycontrollingthe switchstatus. This methodis likelytobe aclosedloopcontrol.
A current sensor is necessary to measure the particular current i
1
to determine switchon
and switchoff. The operation indication is shown in Figure 4.13.
106 Power Electronics
(1/f
s
)
0
i
1
wt
p
FIGURE 4.12 Operation indication of constantfrequency control.
TABLE 4.5
Duty Ratio k in the 20 Chopping Periods in a HalfCycle (10 ms)
ωt (deg) Input Current = 240
√
2 sin(ωt) (V) k
9 53.1 0.867
18 104.9 0.738
27 154.1 0.615
36 199.5 0.501
45 240 0.4
54 274.6 0.314
63 302.4 0.244
72 322.8 0.193
81 335.2 0.162
90 339.4 0.152
99 335.2 0.162
108 322.8 0.193
117 302.4 0.244
126 274.6 0.314
135 240 0.4
144 199.5 0.501
153 154.1 0.615
162 104.9 0.738
171 53.1 0.867
180 0 ∞
Son
i
1
i
*
1
Tolerence
band (I
rip
)
wt
Soff
FIGURE 4.13 Operation indication of hysteresis control.
Implementing Power Factor Correction in AC/DC Converters 107
4.3.2 SourceSide PWM BoostType Rectiﬁers
In motor drive applications with regenerative braking, the power ﬂow from the AC line is
required to be bidirectional. A bidirectional converter can be designed using phase angle
delay control but at the expense of poor input PF and high waveform distortion in the line
current. It is possible to overcome these limitations by using a switchmode converter, as
shown in Figure 4.14.
The rectiﬁer being the dominant mode of operation, i
s
is deﬁned with a direction. An
inductance L
s
(that augments the internal inductance of the utility source) is included to
reduce the ripple in i
s
at a ﬁnite switching frequency. The four switching devices (IGBTs
or MOSFETs) are operated in PWM. Their switching frequency f
s
is usually measured in
kilohertz. From Figure 4.14, we have
v
s
= v
conv
+v
L
. (4.10)
Assuming v
s
to be sinusoidal, the fundamental frequency components of v
conv
and i
s
in
Figure 4.14 can be expressed as phasors
−−−−→
V
conv1
and
−→
I
s1
, respectively (subscript 1 denotes
the fundamental component). Arbitrarily choosing the reference phasor to be
−→
V
s
= V
s
e
j0
◦
,
at the line frequency ω = 2πf
−→
V
s
=
−−−−→
V
conv1
+
−→
V
L1
, (4.11)
where
−→
V
L1
= iωL
s
−→
I
s1
. (4.12)
Aphasor diagram corresponding to Equations 4.11 and 4.12 is shown in Figure 4.15 where
−→
I
s1
lags
−→
V
s
by an arbitrary phase angle θ.
The real power P supplied by the AC source to the converter is
P = V
s
I
s1
cos θ =
V
2
s
ωL
s
V
conv1
V
s
sin δ. (4.13)
From Figure 4.15a,
V
L1
cos θ = ωL
s
I
s1
cos θ = V
conv1
sin δ. (4.14)
In the phasor diagram of Figure 4.15a, the reactive power Q supplied by the AC source is
positive. It can be expressed as
Q = V
s
I
s1
sin θ =
V
2
s
ωL
s
_
1 −
V
conv1
V
s
cos δ
_
. (4.15)
i
s
V
s
i
d
C
d R
–
+
V
d
V
conv
L
s
FIGURE 4.14 Switchmode converter.
108 Power Electronics
I
s1
I
s1
V
conv1
V
L1
V
L1
I
s1
V
s
V
L1
V
L1
V
s
V
s
V
conv1
V
conv1
d
d
d
q
(a)
(b) (c)
q = p
q = 0°
FIGURE 4.15 Phasor diagram: (a) overall diagram; (b) δ is negative; (c) δ is positive.
From Figure 4.15a, we also have
V
s
−ωL
s
I
s1
sin θ = V
conv1
cos δ. (4.16)
From these equations, it is clear that for a given line voltage v
s
and the chosen inductance
L
s
, the desired values of P and Q can be obtained by controlling the magnitude and the
phase of v
conv1
.
Figure 4.15 shows how
−−−−→
V
conv1
can be varied, keeping the magnitude of
−→
I
s1
constant. The
two special cases of rectiﬁcation and inversion at a UPF are shown in Figure 4.15b and c.
In both cases
V
conv1
=
_
V
2
s
+(ωL
s
I
s1
)
2
. (4.17)
In the circuit of Figure 4.14, V
d
is established by charging the capacitor C
d
through the
switchmode converter. The value of V
d
should have a sufﬁciently large magnitude so that
v
conv1
at the AC side of the converter is produced by a PWM that corresponds to a PWM
in a linear region. The control circuit to regulate V
d
in Figure 4.14 is shown in Figure 4.16.
The reference value V
∗
d
intends to achieve a UPF of operation. The ampliﬁed error between
V
d
and V
∗
d
is multiplied by the signal proportional to the input voltage v
s
waveform to
produce the reference signal i
∗
s
. Acurrentmode control such as a tolerance band control or
a ﬁxedfrequency control can be used to deliver i
s
equal to i
∗
s
. The magnitude and direction
of power ﬂow are automatically controlled by regulating V
d
at its desired value.
i
s
(measured)
V
s
(t)
Current
mode
control
Gate
signals
Multiplier
PI
regulator
V
d
V
*
d
i
*
s
i
s
FIGURE 4.16 Block diagram of UPF operation.
Implementing Power Factor Correction in AC/DC Converters 109
4.4 TappedTransformer Converters
A simple method to improve the PF is to use tappedtransformer converters. DC motor
variable speedcontrol drive systems are widely usedinindustrial applications. Some appli
cations require the DC motor to run at lower speeds. For example, winding machines and
rolling mills mostly work at lower speeds (lower than their 50%rated speed). If DC motors
are supplied by AC/DC rectiﬁers, the lower speed corresponds to lower armature voltage.
Assume that the DC motor rated voltage corresponding to the rectiﬁer ﬁring angle α is
about 10
◦
. The ﬁring angle α will be about 60
◦
if the motor runs at half rated speed. In the
ﬁrst case, the DPF is about (cos α), that is, DPF=0.98. In the second case, the DPF is about
0.48. This means that the PF is very poor if the DC motor works at lower speed.
A tappedtransformer converter is shown in Figure 4.17a, which is a singlephase con
trolled rectiﬁer. The original bridge consists of thyristors T
1
–T
4
. The transformer is tapped
at 50%of the secondary winding. The thirdleg consists of thyristors T
5
–T
6
, whichare linked
at the tappedpoint at the middle point of the secondary winding. Since the DCmotor arma
ture circuit has enough inductance, the armature current is always continuous. The motor
armature voltage is
V
O
= V
dO
cos α. (4.18)
wt
wt
V
O
V
O
V
O
i
T
6
T
4
T
2
v = 2V sinwt
T
5
T
3
T
1
(a)
(b)
(c)
FIGURE 4.17 Tappedtransformer converter: (a) circuit diagram, (b) output voltage waveform from original
bridge, and (c) output voltage waveform from new leg.
110 Power Electronics
If the motor works at alower speed, for example, at 45%of its ratedspeed, the corresponding
ﬁring angle α is about 64
◦
. The output voltage waveformfromthe original bridge is shown
inFigure 4.17b. The fundamental harmonic component sine wave must have the delayangle
φ
1
= α = 64
◦
and DPF = cos α. After Fourier transform analysis and THD calculation, the
voltage waveform in Figure 4.17b is 0.24. Therefore,
PF =
DPF
_
1 +THD
2
=
cos 64
◦
_
1 +0.24
2
=
0.443
1.028
= 0.43. (4.19)
Keeping the same armature voltage, we obtain the voltage fromlegs 2 and 3, that is, thyris
tors T
1
and T
2
are idled. This means that the input voltage is reduced by half the supply
voltage, and the ﬁring angle α
is about 27.6
◦
. The output voltage waveform from legs
2 and 3 is shown in Figure 4.17c. The fundamental harmonic component sine wave must
have the delay angle φ
1
= α
= 27.6
◦
and DPF = cos α
. After Fourier transform analysis
and THD calculation, the voltage waveform in Figure 4.17c is 0.07. Therefore,
PF =
DPF
_
1 +THD
2
=
cos 27.6
◦
_
1 +0.07
2
=
0.8863
1.0024
= 0.884. (4.20)
In comparison with the PFs in Equations 4.19 and 4.20, it is obvious that the PF has been
signiﬁcantly corrected.
This method is very simple and straightforward. The tapped point can be shifted to any
other percentage (not ﬁxed at 50%), depending on the applications.
Atest rig can be constructed for collecting the measured results. The circuit is shown in
Figure 4.18. The secondary voltage of the transformer is 230/115 V. The requested output
voltage is set as 80 V.
V
THY1 THY3
THY2
THY5
THY4 THY6
Gating
pulse
Gating
pulse
V
A
DC
machine
V
s
FIGURE 4.18 Singlephase controlled rectiﬁer with a tapped transformer.
Implementing Power Factor Correction in AC/DC Converters 111
10.00
–400.00
–200.00
0.0
200.0
400.0
V
a
20.00 30.00 40.00
Time (ms)
50.00 60.00
FIGURE 4.19 Output voltage 80 V with input voltage 230 V.
If the supply voltage is 230 V, the ﬁring angle is approximately 67
◦
. The output voltage
is shown in Figure 4.19 and the measured record is shown in Figure 4.20. PF is indicated to
be 0.64.
If the supply voltage is 115 V, the ﬁring angle is approximately 39.4
◦
. The output voltage
is shown in Figure 4.21, and the measured record is shown in Figure 4.22. The indication
of the PF in it is 0.87.
If the output voltage increases to 103 Vand the supply voltage remains at 115 V, the ﬁring
angle is approximately 1
◦
. The output voltage is showninFigure 4.23, andthe measurement
record is shown in Figure 4.24. PF is indicated to be 0.98.
FIGURE 4.20 PF with input voltage 230 V and output voltage 80 V.
112 Power Electronics
10.00
–200.00
–100.00
0.00
100.00
200.00
V
a
20.00 30.00 40.00
Time (ms)
50.00 60.00
FIGURE 4.21 Output voltage 80 V with input voltage 115 V.
4.5 SingleStage PFC AC/DC Converters
Adoublecurrent synchronous rectiﬁer converter is a popular circuit that is usedin comput
ers [1,2]. Unfortunately, its PF is not high. However, the singlestage PFC doublecurrent
synchronous rectiﬁer (DCSR) converter is able to improve its PF nearly to unity. The circuit
diagram is shown in Figure 4.25.
The system consists of an AC/DC diode rectiﬁer and a DCSR converter [1]. Suppose
that the output inductors L
1
and L
2
are equal to each other, L
1
= L
2
= L
O
. There are three
switches: main switch S and two auxiliary synchronous switches S
1
and S
2
. It inherently
FIGURE 4.22 PF with input voltage 115 V and output voltage 80 V.
Implementing Power Factor Correction in AC/DC Converters 113
10.00
–100.00
0.0
–50.00
50.00
100.0
150.0
200.0
V
a
20.00 30.00 40.00
Time (ms)
50.00 60.00
FIGURE 4.23 Output voltage 103 V with input voltage 115 V.
exhibits high PF because the PFC cell operates in continuous conduction mode (CCM). In
addition, it is also free to have high voltage stress across the bulk capacitor at light loads.
In order to investigate the dynamical behaviors, the averaging method is used to drive the
DC operating point and the smallsignal model. Aproportionalintegraldifferential (PID)
controller is designedto achieve output voltage regulation despite variations in line voltage
and load resistance.
In power electronic equipment, the PFC circuits are usually added between the bridge
rectiﬁer and the loads to eliminate high harmonic distortion of the line current. In gen
eral, they can be divided into two categories, the twostage approach and the singlestage
FIGURE 4.24 PF with input voltage 115 V and output voltage 103 V.
114 Power Electronics
D
5
V
g
D
3
D
6
D
4
1 : n
C
B
v
CB
L
i
m
+
–
PWM
S D
+
–
FT
L
m
S
2
S
1
L
1
L
2
D
2
D
1
C
O
V
O
R
+ –
i
Lm
i
Li
FIGURE 4.25 Proposed singlestage PFC DCSR converter.
approach. The twostage approach includes a PFC stage and a DC/DC regulation stage.
This approach has good PFC and fast output regulations, but the size and cost increase. To
overcome the drawbacks, the graft scheme is proposed in reference [4]. Many singlestage
approaches have been proposed in the literature [5–8]. They integrate a PFC cell and a
DC/DC conversion cell to form a single stage with a common switch. Therefore, the sinu
soidal input current waveform and the output voltage regulation can be simultaneously
achieved, thereby meeting the requirements of performance and cost.
However, a highvoltage stress exists across the bulkcapacitor C
B
at light loads if a DC/DC
cell operates in discontinuous current mode. To overcome this drawback, a negative mag
netic feedback technique has been proposed in the literature [5–8]. However, the dead band
exists in the input current and the PF is thereby degraded. To deal with this problem, the
DC/DC cell operates in discontinuous current mode. The voltage across the bulk capacitor
is independent of loads and the voltage stress is effectively reduced.
4.5.1 Operating Principles
Figure 4.25 depicts the proposedsinglestage highPFCconverter topology. Aphysical three
winding transformer has a turns ratio of 1:n:m. A tertiary transformer winding, in series
with diode D
4
, is added to the converter for transformer ﬂux resetting. The magnetizing
inductance L
m
is parallel with the ideal transformer. In the proposed converter, both the
PFC cell and the DC/DC conversion cell are operating in CCM. To simplify the analysis of
the circuit, the following assumptions are made:
1. The largevalued bulk capacitor C
B
and the output capacitor C
O
are sufﬁciently
large enough to allow the voltages across the bulk capacitor and the output
capacitor to be approximately constant during one switching period T
s
.
2. All switches and diodes of the converter are ideal. The switching time of the switch
and the reverse recovery time of the diodes are negligible.
3. The inductors andthe capacitors of the converter are consideredto be ideal without
parasitic components.
Based on the switching of the switch and diodes, the proposed converter operating in
one switching period T
s
can be divided into ﬁve linear stages as described below.
Implementing Power Factor Correction in AC/DC Converters 115
Stage 1 [0,t
1
] (S: on; D
1
: on; D
2
: off; D
3
: off; D
4
: off; D
5
: on; D
6
: on): In the ﬁrst stage, the
switch S is turned on. The diodes D
1
, D
5
, and D
6
are turned on and the diodes D
2
, D
3
, and
D
4
are turned off. Power is transferred from the bulk capacitor C
B
to the output via the
transformer.
Stage 2 [t
1
,t
2
] (S: off; D
1
: off; D
2
: on; D
3
: on; D
4
: on; D
5
: off; D
6
: off): The stage begins
when the switch S is turned off. The diodes D
2
, D
3
, and D
4
are turned on and the diodes
D
1
, D
5
, and D
6
are turned off. The current i
Li
ﬂows through diode D
3
and charges the bulk
capacitor C
B
. Diode D
4
is turned on for transformer ﬂux resetting. In this stage, the output
power is provided by the inductor L
O
.
Stage 3 [t
2
,t
3
] (S: off; D
1
: off; D
2
: on; D
3
: off; D
4
: on; D
5
: off; D
6
: off): The stage begins at
t
2
when the input current i
Li
falls to zero and thus diode D
3
is turned off. Switch S is still
off. All diodes, except D
3
, maintain their states as shown in the previous stage. During this
stage, the voltages −v
CB
/m and −v
O
are applied across the inductors L
m
and L
O
, and thus
the inductor currents continue to decrease linearly. The output power is also provided by
the output inductor L
O
.
Stage 4 [t
3
,t
4
] (S: off; D
1
: off; D
2
: off; D
3
: off; D
4
: on; D
5
: off; D
6
: off): The stage begins when
the current i
LO
decreases to zero and thus diode D
2
is turned off. Switch S is still off. Diode
D
4
is still turned on and diodes D
1
, D
3
, D
5
, and D
6
are still turned off. During this stage, the
voltage −v
CB
/m is applied across inductor L
m
. The inductor current continues to decrease
linearly. The output power is provided by the output capacitor C
O
in this stage.
Stage 5 [t
4
,t
5
] (S: off; D
1
: off; D
2
: off; D
3
: off; D
4
: off; D
5
: off; D
6
: off): The stage begins when
the current i
Lm
falls to zero andthus diode D
4
is turnedoff. Switch S is still off andall diodes
are off. The output power is also provided by the output capacitor C
O
. The operation of the
converter returns to the ﬁrst stage when switch S is turned on again.
According to the analysis of the proposed converter, the key waveforms over one switch
ing period T
s
are schematically depicted in Figure 4.26. The slopes of the waveforms i
CO
(t)
and i
CB
(t) are deﬁned as
m
CO1
=
nv
CB
−v
CO
L
O
, m
CO2
= −
v
CO
L
O
, m
CB1
= −
_
v
CB
L
m
+
n(nv
CB
−v
CO
)
L
O
_
,
m
CB2
= −
_
v
CB
L
i
+
v
CB
m
2
L
m
_
, m
CB2
= −
v
CB
m
2
L
m
. (4.21)
4.5.2 Mathematical Model Derivation
In this section, the smallsignal model of the proposed converter can be derived by the
averagingmethod. The movingaverage of a variable, voltage or current, over one switching
period T
s
is deﬁned as the area, encompassed by its waveform and time axis, divided
by T
s
.
4.5.2.1 Averaged Model over One Switching Period T
s
There are six storage elements in the proposed converter in Figure 4.25. The state variables
of the converter are chosen as the current through the inductor and the voltage across
the capacitor. Since bothPFCcells andDC/DCcells operate indiscontinuous current mode,
the initial and ﬁnal values of inductor currents vanish in each switching period T
s
. From
a system point of view, the inductor currents i
Li
, i
LO
, and i
Lm
should not be considered as
116 Power Electronics
v
Li
(t)
v
LO
(t)
v
LM
(t)
v
CS
v
CS
m
CB1
m
CB2
m
Ca2
i
CO
(t)
i
CB
(t)
v
CS
S
S
d
1
T
s
d
1
T
s d
2
T
s
d
2
T
s d
3
T
s
d
3
T
s
t
1
t
1
t
2
t
2
t
3
t
3 t
4
t
4
d
4
T
s
d
4
T
s d
5
T
s
d
5
T
s
T
s
T
s
t
t t
t
t
t
t
nv
CB
–v
CO
–v
CO
–v
CO
v
g
(t)
–
On On
0
0
Off Off
1
m
m
Ca1
m
CB3
FIGURE 4.26 Typical waveforms of the proposed converter.
state variables. Only the bulk capacitor voltage v
CB
and the output capacitor voltage v
CO
are considered to be state variables of the proposed converter.
For notational brevity, a variable with an upper bar denotes its moving average over one
switching period T
s
. With the aid of this deﬁnition, the averaged statevariable description
of the converter is given by
C
B
d¯ v
CB
dt
=
¯
i
CB
and C
O
d¯ v
CO
dt
=
¯
i
CO
. (4.22)
Moreover, in discontinuous conduction, the averaged voltage across each inductor over
one switching period is zero. Hence we have three constraints of the form
L
i
d
¯
i
Li
dt
= ¯ v
Li
= 0, L
O
d
¯
i
LO
dt
= ¯ v
LO
= 0, L
m
d
¯
i
Lm
dt
= ¯ v
Lm
= 0. (4.23)
The output equation is expressed as
¯ v
O
= ¯ v
CO
. (4.24)
Implementing Power Factor Correction in AC/DC Converters 117
Based on the typical waveforms in Figure 4.26, the averaged variables are given by
¯
i
CB
=
1
T
s
5
j=1
area[i
CB(j)
] =
1
T
s
_
d
2
1
T
2
s
m
CB1
+
1
2
d
2
T
2
s
, [d
2
m
CB2
+2(d
3
+d
4
)m
CB2
]
+
1
2
(d
3
+d
4
)
2
T
2
s
m
CB3
_
, (4.25)
¯
i
CO
=
1
T
s
5
j=1
area[i
CO(j)
] =
1
T
s
_
d
1
T
2
s
(d
1
+d
2
+d
3
)
n¯ v
CB
− ¯ v
CO
2 L
O
−T
s
¯ v
CO
R
_
, (4.26)
where the notation area [i
CB(j)
] denotes the area, encompassed by the waveform i
CB
(t) and
time axis, during stage j. Similarly, we have
¯ v
Li
=
1
T
s
5
j=1
area[v
Li(j)
] =
1
T
s
[d
1
T
s
¯ v
g
(t) +d
2
T
s
(−¯ v
CB
)],
¯ v
Lm
=
1
T
s
5
j=1
area[v
Lm(j)
] =
1
T
s
_
d
1
T
s
¯ v
CB
+(d
2
+d
3
+d
4
)T
s
_
−
¯ v
CB
m
__
,
¯ v
LO
=
1
T
s
5
j=1
area[v
LO(j)
] =
1
T
s
[d
1
T
s
(n¯ v
CB
− ¯ v
CO
) +(d
2
+d
3
)T
s
(−¯ v
CO
)].
(4.27)
Substituting Equation 4.27 into the constraints given by Equation 4.23, and performing
mathematical manipulations, gives
d
2
=
¯ v
g
(t)
¯ v
CB
d
1
, d
3
=
_
n¯ v
CB
¯ v
CO
−1 −
¯ v
g
(t)
¯ v
CB
_
d
1
, d
4
=
_
m+1 −
n¯ v
CB
¯ v
CO
_
d
1
. (4.28)
Now, substituting Equations 4.21 and 4.28 into Equations 4.25 and 4.26, the averaged state
Equation 4.22 can be rewritten as
C
B
d¯ v
CB
dt
= −d
2
1
T
s
n(n¯ v
CB
− ¯ v
CO
)
2L
o
+
d
2
1
T
s
¯ v
2
g
(t)
2L
i
¯ v
CB
and
C
O
d¯ v
CO
dt
= −
¯ v
CO
R
+d
2
1
T
s
n(n¯ v
CB
− ¯ v
CO
)
2L
O
¯ v
CO
. (4.29)
The averaged rectiﬁed line current is given by
¯
i
g
(t) =
1
T
s
{area[i
Li(1)
]} =
1
T
s
_
1
2
(d
1
T
s
)
2
¯ v
g
(t)
L
i
_
. (4.30)
It is revealed from Equation 4.30 that
¯
i
g
(t) is proportional to ¯ v
g
(t).‘ Thus, the proposed
converter is provided with an UPF.
118 Power Electronics
4.5.2.2 Averaged Model over One Half Line Period T
L
Basedonthe derivedaveragedmodel describedbyEquation4.30 over one switchingperiod
T
s
, we now proceed to develop the averaged model over one half line period T
L
. Since the
bulk capacitance and the output capacitance are sufﬁciently large, both capacitor voltages
canbe consideredas constants over T
L
. Therefore, the state equations of the averagedmodel
over one half line period T
L
can be given by
C
B
d¯ v
CB
T
L
dt
=
_
d
2
1
T
s
2
_
−(n
2
¯ v
CB
+n¯ v
CO
)
L
O
+
¯ v
2
g
(t)
L
i
¯ v
CB
__
T
L
=
1
π
π
0
d
2
1
T
s
2
_
−(n
2
¯ v
CB
+n¯ v
CO
)
L
O
+
v
2
m
sin
2
(ωt)
L
i
¯ v
CB
_
d(ωt)
=
d
2
1
T
s
2
_
−n
2
¯ v
CB
T
L
+n¯ v
CO
T
L
L
O
+
v
2
m
2L
i
¯ v
CB
T
L
_
, (4.31)
C
O
d¯ v
CO
T
L
dt
=
_
−
¯ v
CO
R
+d
2
1
T
s
n
2
¯ v
2
CB
−n¯ v
CB
¯ v
CO
2L
O
¯ v
CO
_
T
L
=
1
π
π
0
_
−
¯ v
CO
R
+d
2
1
T
s
n
2
¯ v
2
CB
−n¯ v
CB
¯ v
CO
L
O
¯ v
CO
_
d(ωt)
=
¯ v
CO
T
L
R
+
d
2
1
T
s
_
−n
2
¯ v
CB
2
T
L
−n¯ v
CB
T
L
¯ v
CO
T
L
_
2L
O
¯ v
CO
T
L
, (4.32)
and the output equation is given by
¯ v
O
T
L
= ¯ v
CO
T
L
. (4.33)
Notably, Equations 4.31 and4.32 are nonlinear state equations that can be linearizedaround
the DCoperatingpoint. The DCoperatingpoint canbe determinedbysettingd¯ v
CB
T
L
/dt =
0 and d¯ v
CO
T
L
/dt = 0 in Equations 4.31 and 4.32. Mathematically, we then successively
compute the bulk capacitor voltage V
CB
and the output voltage V
O
as
V
CB
=
1
2n
⎛
⎝
_
D
2
1
RT
s
4L
i
+
2L
O
L
i
+
_
D
2
1
RT
s
4L
i
⎞
⎠
, V
O
= D
1
_
RT
s
4L
i
V
m
. (4.34)
The design speciﬁcations and the component values of the proposed converter are listed
in Table 4.6. In Table 4.6, it follows directly from Equation 4.34 that V
CB
= 146.6 V and
V
O
= 108 V. Therefore, the proposed converter exhibits low voltage stress across the bulk
capacitor for a VAC 110 input voltage.
Implementing Power Factor Correction in AC/DC Converters 119
TABLE 4.6
Design Speciﬁcations and Component Values of the Proposed Converter
Input peak voltage V
m
156 V Duty ratio D
1
0.26
Input inductor L
i
75 μH Switching period T
s
20 μs
Magnetizing inductor L
m
3.73 mH Switching frequency f
s
50 kHz
Output inductor L
O
340 μH Load resistance R 108 Ω
Bulk capacitor C
B
330 μF Turns ratio 1:n:m 1:2:1
Output capacitor C
O
1000 μF PWM gain k
PWM
1/12 V
−1
Bulk capacitor voltage V
CB
146.6 V Output voltage V
O
108 V
After determining the DC operating point, we proceed to derive the smallsignal model
linearized around the operating point. To proceed, small perturbations
v
m
= V
m
+ ˜ v
m
, d
1
= D
1
+
˜
d
1
, ¯ v
CB
T
L
= V
C
B
+ ˜ v
C
B
,
¯ v
CO
T
L
= V
CO
+ ˜ v
CO
, ¯ v
O
T
L
= V
O
+ ˜ v
O
,
(4.35)
with
V
m
˜ v
m
, D
1
˜
d
1
, V
CB
˜ v
CB
, V
CO
˜ v
CO
, V
O
˜ v
O
, (4.36)
are introduced into Equations 4.31 and 4.32 and highorder terms are neglected, yielding
dynamical equations of the form
C
B
d˜ v
CB
dt
=
D
2
1
T
s
2
_
−
n
2
L
O
−
V
2
m
2L
i
V
2
CB
_
˜ v
CB
+
D
2
1
T
s
2
_
n
L
O
_
˜ v
CO
+
D
2
1
T
s
2
_
V
m
L
i
V
CB
_
˜ v
m
+D
1
T
s
_
−n
2
V
CB
+nV
CO
L
O
+
V
2
m
2L
i
V
CB
_
˜
d
1
= a
11
˜ v
CB
+a
12
˜ v
CO
+b
11
˜ v
m
+b
12
˜
d
1
, (4.37)
C
O
d˜ v
CO
dt
=
D
2
1
T
s
2
_
2n
2
V
CB
L
O
V
CO
−
n
L
O
_
˜ v
CB
+
_
−
1
R
−
D
2
1
T
s
2
n
2
V
2
CB
L
O
V
2
CO
_
˜ v
CO
+0 · ˜ v
m
+D
1
T
s
_
n
2
V
2
CB
L
O
V
CO
−
nV
CB
L
O
_
˜
d
1
= a
21
˜ v
CB
+a
22
˜ v
CO
+b
21
˜ v
m
+b
22
˜
d
1
. (4.38)
The parameters are deﬁned as
a
11
=
−D
2
1
T
s
2
_
n
2
L
O
+
V
2
m
2L
i
V
2
CB
_
, a
12
=
D
2
1
T
s
2
_
n
L
O
_
,
a
21
=
D
2
1
T
s
2
_
2n
2
V
CB
L
O
V
CO
−
n
L
O
_
, a
22
= −
_
1
R
+
D
2
1
T
s
2
n
2
V
2
CB
L
O
V
2
CO
_
,
120 Power Electronics
b
11
=
D
2
1
T
s
2
_
V
m
L
i
V
CB
_
, b
12
= D
1
T
s
_
−n
2
V
CB
+nV
CO
L
O
+
V
2
m
2L
i
V
CB
_
,
b
21
= 0, b
22
= D
1
T
s
_
n
2
V
2
CB
L
O
V
C
O
−
nV
CB
L
O
_
.
Mathematically, the dynamical equations in Equations 4.37 and 4.38 can be expressed in
matrix form as
_
˙
˜ v
CB
˙
˜ v
CO
_
=
⎡
⎢
⎢
⎣
a
11
C
B
a
12
C
B
a
21
C
O
a
22
C
O
⎤
⎥
⎥
⎦
_
˜ v
CB
˜ v
Co
_
+
⎡
⎢
⎢
⎣
b
11
C
B
b
12
C
B
b
21
C
O
b
22
C
O
⎤
⎥
⎥
⎦
_
˜ v
m
˜
d
1
_
, (4.39)
˜ v
O
= [0 1]
_
˜ v
CB
˜ v
CO
_
. (4.40)
Now taking the Laplace transform for the dynamical equation, the resulting transfer
functions from line to output and duty ratio to output are given by
˜ v
O
(s)
˜ v
m
(s)
=
b
11
a
21
/C
B
C
O
s
2
+[(−a
11
/C
B
) −(a
22
/C
O
)]s +(a
11
a
22
−a
12
a
21
)/C
B
C
O
,
˜ v
o
(s)
˜
d
1
(s)
=
(b
22
/C
O
)s +(a
21
b
12
−a
11
b
22
)/C
B
C
O
s
2
+[(−a
11
/C
B
) −(a
22
/C
O
)]s +(a
11
a
22
−a
12
a
21
)/C
B
C
O
.
(4.41)
4.5.3 Simulation Results
The PSpice simulation results presented in Figure 4.27 demonstrate that both PFC and
DC/DC cells are operating in discontinuous current mode. The input inductor current
i
Li
(t) and the output inductor current i
LO
(t) both reach zero for the remainder of the switch
ing period. Figure 4.28a presents the bulk capacitor voltage V
CB
= 149 V and Figure 4.28b
presents the output capacitor voltage V
CO
= 110 V. They are close to the theoretical results
V
CB
= 146.6 V and V
CO
= 108 V.
8.00
4.00
–4.00
–8.00
Time (s) Time (s)
i
L
O
(
t
)
i
L
i
(
t
)
0
20.00
(a) (b)
10.00
–10.00
–20.00
0
FIGURE 4.27 Current waveforms: (a) input inductor currents i
Li
(t) (horizontal: 10 μs/div) and (b) output induc
tor currents i
LO
(t) (horizontal: 10 μs/div).
Implementing Power Factor Correction in AC/DC Converters 121
112
111
110
V
O
(
t
)
V
C
B
(
t
)
109
108 129
139
149
159
169
(a)
(b)
Time (s) Time (s)
FIGURE 4.28 Ripples of (a) bulk capacitor voltage V
CB
(t) (vertical: 5 V/div; horizontal: 5 ms/div) and (b) output
capacitor voltage V
CO
(t) (vertical: 0.5 V/div; horizontal: 5 ms/div)
4.5.4 Experimental Results
Aprototype based on the topology depicted in Figure 4.25 was built and tested to verify the
operating principle of the proposed converter. The experimental results are depicted in the
following ﬁgures. Figure 4.29a presents the rectiﬁed line voltage and current. Figure 4.29b
presents the input line voltage and current. This reveals that the proposed converter has a
high PF. According to the THD obtained in the simulation results, PF=0.999.
200
(a)
100
0
–100
V
g
(
t
)
–200
Time (s)
40.00
20.00
0
–20.00
i
g
(
t
)
i
g
(t)
u
g
(t)
–40.00
(b)
Time (s)
i
i
(t)
v
i
(t)
200
100
0
–100
V
i
n
(
t
)
–200
4.00
2.00
0
–2.00
i
i
n
(
t
)
–4.00
FIGURE 4.29 Line voltages andcurrents: (a) rectiﬁedline voltage andcurrent (horizontal: 5 ms/div) and(b) input
line voltage and current (horizontal: 5 ms/div).
122 Power Electronics
TRG = 0.02div SMPL 10MS/s
Stop
TRG = 0.02div SMPL 10MS/s
Stop
(a) (b)
FIGURE 4.30 Inductor currents (horizontal: 10 μs/div): (a) input inductor currents i
Li
(t) (vertical: 5A/div) and
(b) output inductor currents i
LO
(t) (vertical: 2A/div).
Figure 4.30 presents the waveform of the input inductor current i
Li
(t) and the output
inductor current i
LO
(t). Figure 4.31 presents the voltage ripples of the bulk capacitor voltage
V
CB
(t) andthe output capacitor voltage V
CO
(t). Figure 4.32presents the rectiﬁedline voltage
and current and the input line voltage and current. The proposed converter exhibits low
voltage stress and a high PF. The measured PF of the converter is 0.998. The efﬁciency of
the proposed converter is about 72%.
FIGURE 4.31 Ripples of (a) bulk capacitor voltage V
CB
(t) (vertical: 5 V/div; horizontal: 5 ms/div) and (b) output
capacitor voltage V
CO
(t) (vertical: 0.5 V/div; horizontal: 5 ms/div).
TRG = 0.02div SMPL 20kS/s
Stop
(a) (b)
FIGURE 4.32 Line voltages and currents (horizontal: 5 ms/div): (a) rectiﬁed line voltage and current (vertical:
50 V/div, 10A/div) and (b) input line voltage and current (vertical: 50 V/div, 2A/div).
Implementing Power Factor Correction in AC/DC Converters 123
4.6 VIENNA Rectifiers
The VIENNArectiﬁer can be used to improve the PF of a threephase rectiﬁer. The “critical
input inductor” is calculated for the nominal load condition, and both PF and THD are
degraded in the lowoutput power region. Anovel strategy implementing reference com
pensation current is proposed based on the operation principle of the VIENNArectiﬁer in
this section. This strategy can realize a threephase threelevel UPF rectiﬁer. With the pro
posed control algorithm, the converter draws highquality sinusoidal supply currents and
maintains good DClink voltage regulation under wide load variation. Theoretical analysis
is initially veriﬁed by digital simulation. Finally, experimental results of a 1kVAlaboratory
prototype system conﬁrm the feasibility and effectivity of the proposed technique.
Diode rectiﬁers with smoothing capacitors have been widely used in many threephase
power electronic systems such as DCmotor drives and switchmode power supplies. How
ever, this topology injects large current harmonics into utilities, which result in the decrease
of PF. Expressions of the current THD and the input PF are given as
THD = 100 ×
_
∞
h=2
I
2
sh
I
s1
, (4.42)
PF =
1
_
1 +THD
2
DPF. (4.43)
The international standards presented in IEC 100032 and EN6100032 imposed har
monic restrictions to modern rectiﬁers that stimulated a focused research effort on the topic
of UPF rectiﬁers. A slew of new topologies, including those based on threelevel power
conversion, have been proposed to realize highquality input waveforms [9–20].
Among the reported threephase rectiﬁer topologies, the threephase starconnected
switch threelevel (VIENNA) rectiﬁer [21–25] is an attractive choice because its switch volt
age stress is onehalf the total output voltage. This rectiﬁer withthree bidirectional switches,
three input inductors, and two seriesconnected capacitors is shown in Figure 4.33.
Each bidirectional switch is turned on when the corresponding phase voltage crosses
the zerovolt point and conducts for 30
◦
of the line voltage cycle. Thus, the input current
waveform is well shaped and approximately sinusoidal. The input current THD can be
as low as 6.6%, and the PF can be as high as 0.99. In addition, the bidirectional switches
conduct at twice the line frequency; therefore, the switching losses are negligible.
However, the optimal input inductance required to obtain such a result is usually large,
and this technique was proposed for the rectiﬁer operating with a ﬁxed load and a ﬁxed
optimal input inductor. Therefore, the DClink voltage is sensitive to load variation and
high performance is achieved within a very limited output power range.
In order to overcome these drawbacks, some control strategies have been proposed [26–
31]. Acontrol strategythat takes intoaccount the actual loadlevel onthe rectiﬁer is proposed
in reference [27]. With this method, high performance can be achievedwithin a wide output
power range. The required optimal input inductance for a prototype rated at 8 kWis about
4 mH. This methodis especially suitable for mediumto highpower applications. However,
for lowpower application (i.e., 1–5 kW), the required optimal input inductance should be
larger: for example, around 24 mH for a converter with rated power 1.5 kW. This can result
in a bulky and impractical structure.
124 Power Electronics
v
sa
v
sb
v
sc
i
sa
i
sb
i
sc
i
fc
i
fa
S
a
D
4
D
6
D
2
Bidirectional
switches
O
C
b
C
a
V
DC
R
o
M
D
3
D
1
A
B
C
D
5
i
la
i
lb
i
lc
S
b
S
c
i
fb
L
FIGURE 4.33 AC/DC converter with bidirectional switches—the VIENNArectiﬁer.
The ramp comparison current control presented in reference [26] derives the duty cycle
by a comparison of the current error and the ﬁxedfrequency carrier signal. The ripple
current in the input inductor makes the current error noisy, although synchronization is
carefully considered. Another approach that features constant switching frequency was
proposed based on integration control [28]. The input voltage sensors were eliminated in
the integration control. However, a signiﬁcant lowfrequency distortion can be observed
in the input currents. Recently, a synchronousreferenceframebased hysteresis current
control (HCC) was adopted as the inner loop and DClink voltage control as the outer
loop [29], but a referenceframe transformation was required that increased the controller
operation time (digital signal processor [DSP] [29]). A hysteresis current controller was
proposed in references [30,31]. The switching signals are generated by the comparison of
a reference current template (sinusoidal) and the measured main currents. Although this
approach is easy to implement, one needs to measure the DC current and the equipment is
costly.
The novel control method proposed in this chapter was based on the operation principle
of the VIENNArectiﬁer. The VIENNArectiﬁer is composed of two parts: an active compen
sation circuit and a conventional rectiﬁer circuit. The harmonics injected by a conventional
rectiﬁer can be compensated by the active compensation circuit, which enables the input
PF can be increased. The average real power consumed by the load is supplied by the
source and the active compensation circuit does not provide or consume any average real
power. Then the reference compensational current can be obtained. The conduction period
of bidirectional switches (S
a
, S
b
, and S
c
) is controlled by using HCC. The idea is that a
high switching frequency results in the input inductor size being effectively reduced. This
control method does not need to measure the DClink current and so results in the decrease
of the equipment size and cost. Simulation and experimental results have shown that the
input PF can be signiﬁcantly improved and the input current harmonics can be effectively
eliminated under wide load variation. The proposed control strategy also maintains good
DClink voltage.
4.6.1 Circuit Analysis and Principle of Operation
The AC/DC converter topology shown in Figure 4.33 is composed of a threephase diode
rectiﬁer with two identical seriesconnected capacitors and three bidirectional switches
Implementing Power Factor Correction in AC/DC Converters 125
D
+
D
–
D
–
S
D
+
FIGURE 4.34 Construction of a bidirectional switch.
(S
a
, S
b
, and S
c
). The switches consist of four diodes and a MOSFET to form a bidirectional
switch (see Figure 4.34).
These bidirectional switches are controlled by using HCC to ensure good supply current
waveform, constant DClink voltage, and accurate voltage balance between the two capac
itors. In Figure 4.33, the voltage sources v
sa
, v
sb
, and v
sc
denote the threephase AC system.
The waveforms and the current of phase a (i
sa
) are shown in Figure 4.35.
For the circuit analysis (Figure 4.35), six topological stages are presented, corresponding
to a halfcycle (0
◦
to 180
◦
), which refer to the input voltage v
sa
shown in Figure 4.35; for
simplicity, only the components where current is present are pictured at each of those
intervals.
In the interval between 0
◦
and 30
◦
(see Figure 4.36a and b), the polarities of the source
voltages v
sa
andv
sc
are positive withthat of v
sb
negative. Whenthe bidirectional switchS
a
is
on, the source current i
sa
ﬂows throughS
a
, anddiodes D
5
andD
6
are on. The other diodes not
shown in Figure 4.36a are off. When the bidirectional switch S
a
is off, the current i
sa
ﬂowing
through the input inductor is continuedthrough diode D
1
anddiodes D
5
andD
6
are still on.
The other diodes not showninFigure 4.36bare off. The current commutationfromS
a
toD
1
is
at a certain moment determined by HCC. Diodes D
5
and D
6
offer a conventional rectifying
wave. SwitchS
a
anddiode D
1
turnonexclusively, andoffer the active compensationcurrent.
In the interval between 30
◦
and 60
◦
(see Figure 4.36c and d), the polarities of the source
voltages v
sa
andv
sc
are positive withthat of v
sb
negative. Whenthe bidirectional switchS
c
is
on, the source current i
sc
ﬂows throughS
c
, anddiodes D
1
andD
6
are on. The other diodes not
shown in Figure 4.36c are off. When the bidirectional switch S
c
is off, the current i
sc
ﬂowing
through the input inductor continues through diode D
5
, and diodes D
1
and D
6
are still on.
v
sa
v
sb
v
sc
v
0
wt
i
sa
FIGURE 4.35 Waveforms of source voltages and current of phase a, i
sa
.
v
sa
v
sb
v
sc
v
sa
v
sb
v
sc
v
sa
v
sa
v
sa
v
sa
v
sa
v
sa
v
sb
v
sb
v
sb v
sb
v
sb
v
sb
v
sc
v
sc
v
sc
v
sc
v
sc
v
sc
v
sa
v
sa
v
sb
v
sb
v
sc
v
sc
v
sa
v
sa
v
sb
v
sb
v
sc
v
sc
i
sc
i
sb
S
a
S
c
S
c
S
b
S
b
S
a
D
6
D
6
O
(a)
(c)
(e)
(g)
(i)
(k)
(b)
(d)
(f )
(h)
(j)
(l)
O
O
O
O
O
O
O
O
O
O
O
D
1
D
1
D
1
D
1
D
1
D
1
D
1
D
3
D
3
D
6
D
2
D
1
D
1
D
3
D
2
D
6
D
6
D
6
D
6
D
2
D
2
D
2
D
2
D
2
V
DC
V
DC
V
DC
V
DC
V
DC
V
DC
R
O
R
O
R
O
R
O
R
O
R
O
D
5
D
5
D
1
D
5
C
a
C
a
C
a
C
a
C
a
C
a
C
a
C
a
C
a
C
a
C
b
C
b
C
b
C
b
C
b
C
b
C
b
C
b
C
b
C
b
M
M
M M
M M
M
M
M
M M
M
i
sa
i
sc
i
sb
i
sa
i
sc
i
sc
i
sc
i
sc
i
sc
i
sc
i
sc
i
sc
i
sb
i
sb
i
sb
i
sb
i
sb
i
sb
i
sb
i
sb
i
sa
i
sa
i
sa
i
sa
i
sa
i
sa
i
sa
i
sa
C
a
C
a
C
b
C
b
i
sc
i
sc
i
sb
i
sb
i
sa
i
sa
L
L
L L
L
L
L
L
L L
L
V
DC
R
O
V
DC
R
O
V
DC
R
O
V
DC
R
O
V
DC
R
O
V
DC
R
O
FIGURE 4.36 Topological stages for 0
◦
–180
◦
referring to the input voltage v
sa
(a) 0
◦
–30
◦
; S
a
is on; (b) 0
◦
–30
◦
; S
a
is off, the current i
sa
ﬂowing through the input inductor is continued through the diode D
1
, diodes D
5
and D
6
are
still on. (c) 30
◦
–60
◦
; S
c
is on; (d) 30
◦
–60
◦
; S
c
is off, the current i
sc
ﬂowing through the input inductor is continued
through the diode D
5
, diodes D
1
and D
6
are still on. (e) 60
◦
–90
◦
; S
c
is on; (f) 60
◦
–90
◦
; S
c
is off, the current i
sc
ﬂowing through the input inductor is continued through the diode D
2
, diodes D1 and D6 are still on. (g) 90
◦
–120
◦
;
S
b
is on; (h) 90
◦
–120
◦
; S
b
is off, the current i
sb
ﬂowing through the input inductor is continued through the diode
D
6
, diodes D
1
and D
2
are still on. (i) 120
◦
–150
◦
; S
b
is on; (j) 90
◦
–120
◦
; S
b
is off, the current i
sb
ﬂowing through
the input inductor is continued through the diode D
3
, diodes D
1
and D
2
are still on. (k) 150
◦
–180
◦
; S
a
is on; (l)
150
◦
–180
◦
; S
a
is off, the current i
sa
ﬂowing through the input inductor is continued through the diode D
1
, diodes
D
3
and D
2
are still on.
Implementing Power Factor Correction in AC/DC Converters 127
The other diodes not shown in Figure 4.36d are off. The current commutation fromS
c
to D
5
is at a certainmoment determinedbyHCC. Diodes D
1
andD
6
offer a conventional rectifying
wave. SwitchS
c
anddiode D
5
turnonexclusively, andoffer the active compensationcurrent.
In the interval between 60
◦
and 90
◦
(see Figure 4.36e and f), the polarity of the source
voltage v
sa
is positive with those of v
sb
and v
sc
negative. When the bidirectional switch S
c
is
on, the source current i
sc
ﬂows throughS
c
, anddiodes D
1
andD
6
are on. The other diodes not
shown in Figure 4.36e are off. When the bidirectional switch S
c
is off, the current i
sc
ﬂowing
throughthe input inductor is continuedthroughdiode D
2
, anddiodes D
1
andD
6
are still on.
The other diodes not showninFigure 4.36f are off. The current commutationfromS
c
to D
2
is
at a certain moment determined by HCC. Diodes D
1
and D
6
offer a conventional rectifying
wave. SwitchS
c
anddiode D
2
turnonexclusively, andoffer the active compensationcurrent.
In the interval between 90
◦
and 120
◦
(see Figure 4.36g and h), the polarity of the source
voltage v
sa
is positive with those of v
sb
and v
sc
negative. When the bidirectional switch S
b
is
on, the source current i
b
ﬂows throughS
b
anddiodes D
1
andD
2
are on. The other diodes not
shown in Figure 4.36g are off. When the bidirectional switch S
b
is off, the current i
b
ﬂowing
through the input inductor continues through diode D
6
, and diodes D
1
and D
2
are still on.
The other diodes not shown in Figure 4.36h are off. The current commutation fromS
b
to D
6
is at a certainmoment determinedbyHCC. Diodes D
1
andD
2
offer a conventional rectifying
wave. SwitchS
b
anddiodeD
6
turnonexclusively, andoffer theactivecompensationcurrent.
In the interval between 120
◦
and 150
◦
(see Figure 4.36i and j), the polarities of the source
voltages v
sa
andv
sb
are positive withthat of v
sc
negative. Whenthe bidirectional switchS
b
is
on, the source current i
sb
ﬂows throughS
b
anddiodes D
1
andD
2
are on. The other diodes not
shown in Figure 4.36i are off. When the bidirectional switch S
b
is off, the current i
sb
ﬂowing
through the input inductor continues through diode D
3
and diodes D
1
and D
2
are still on.
The other diodes not showninFigure 4.36j are off. The current commutationfromS
b
to D
3
is
at a certain moment determined by HCC. Diodes D
1
and D
2
offer a conventional rectifying
wave. SwitchS
b
anddiodeD
3
turnonexclusively, andoffer theactivecompensationcurrent.
In the interval between 150
◦
and 180
◦
(see Figure 4.36k and l), the polarities of the source
voltages v
sa
andv
sb
are positive withthat of v
sc
negative. Whenthe bidirectional switchS
a
is
on, the source current i
sa
ﬂows throughS
a
anddiodes D
3
andD
2
are on. The other diodes not
shown in Figure 4.36k are off. When the bidirectional switch S
a
is off, the current i
sa
ﬂowing
through the input inductor continues through diode D
1
and diodes D
3
and D
2
are still on.
The other diodes not showninFigure 4.36l are off. The current commutationfromS
a
to D
1
is
at a certain moment determined by HCC. Diodes D
3
and D
2
offer a conventional rectifying
wave. SwitchS
a
anddiode D
1
turnonexclusively, andoffer the active compensationcurrent.
An active compensation circuit is composed of one of the bidirectional switches and an
offdiode in the rectiﬁer bridge legs, but the other legs act as a conventional rectiﬁer. So
there are two circuits in the VIENNArectiﬁer, namely the conventional rectiﬁer circuit and
the active compensation circuit. Thus, the load average real power is supplied by the source
(the same as a conventional rectiﬁer) and the active compensation circuit does not provide
or consume any real power.
4.6.2 Proposed Control Arithmetic
The proposed controller is based on the requirement that the source currents need to be
balanced, undistorted, and in phase with the source voltages. The functions of the active
compensationcircuit areto(1) unitizesupplyPF, (2) minimizeaveragereal power consumed
or supplied by the active compensation circuit, and (3) compensate harmonics and reactive
128 Power Electronics
currents. To carry out the functions, the desired threephase source currents of Equation
4.44 must be in phase with the source voltages of Equation 4.45:
⎧
⎪
⎨
⎪
⎩
i
sa
= I
m
sin(ωt +φ),
i
sb
= I
m
sin(ωt +φ −120
◦
),
i
sc
= I
m
sin(ωt +φ +120
◦
),
(4.44)
⎧
⎪
⎨
⎪
⎩
v
sa
= V
m
sin(ωt +φ),
v
sb
= V
m
sin(ωt +φ −120
◦
),
v
sc
= V
m
sin(ωt +φ +120
◦
).
(4.45)
where V
m
and φ are the voltage magnitude and the phase angle of the source voltages,
respectively. Under the conditions that the load active power is supplied by the source
and the active compensation circuit does not provide or consume any real power, the cur
rent magnitude I
m
needs to be determined from the sequential instantaneous voltage and
real power components supplied to the load. According to the symmetrical component
transformation for the threephase rms currents at each harmonic order, the threephase
instantaneous load currents can be expressed by
i
lk
=
∞
n=1
i
+
lkn
+
∞
n=1
i
−
lkn
+
∞
n=1
i
0
lkn
, k ∈ K. (4.46)
In Equation 4.46, K = {a, b, c}; 0, +, and − stands for zero, positive, and negative
sequence components, respectively, and n represents the fundamental (i.e., n = 1) and the
harmonic components. Since the average real power consumed by the load over one period
of time T must be supplied by the source and requires that the active compensation circuit
consumes or supplies null average real power, Equations 4.47 through 4.51 must hold
p
s
= p
l
+p
f
, (4.47)
¯ p
s
=
1
T
T
0
k∈K
v
sk
i
sk
dt, (4.48)
¯ p
l
=
1
T
T
0
k∈K
v
sk
i
lk
dt, (4.49)
¯ p
f
= 0, (4.50)
¯ p
s
= ¯ p
l
. (4.51)
Substituting Equation 4.46 into Equation 4.49 yields the sum of the fundamental and the
harmonic power terms at the three sequential components
¯ p
l
= ¯ p
+
l1
+ ¯ p
−
l1
+ ¯ p
0
l1
+ ¯ p
+
lh
+ ¯ p
−
lh
+ ¯ p
0
lh
, (4.52)
where
¯ p
+
l1
=
1
T
T
0
k∈K
v
sk
i
+
lk1
dt =
1
T
T
0
k∈K
v
sk
i
sk
dt =
3V
m
I
m
2
(4.53)
Implementing Power Factor Correction in AC/DC Converters 129
and
¯ p
−
l1
= ¯ p
0
l1
= ¯ p
+
lh
= ¯ p
−
lh
= ¯ p
0
lh
= 0. (4.54)
Each power term in Equation 4.54 is determined based on the orthogonal theorem for a
periodic sinusoidal function. Then, Equation 4.49 becomes
¯ p
s
= ¯ p
l
= ¯ p
+
l1
=
1
T
T
0
k∈K
v
sk
i
sk
dt. (4.55)
Using Equations 4.51, 4.53, and 4.55, the desired source current magnitude at each phase
is determined as
I
m
=
2¯ p
l
3V
m
=
2
T
0
k∈K
v
sk
i
lk
dt
3TV
m
(4.56)
and the source currents of Equation 4.44 can be expressed by
i
sk
= I
m
v
sk
V
m
=
2¯ p
l
3(V
m
)
2
v
sk
, k ∈ K. (4.57)
The required current compensation at each phase by the active compensation circuit is
then obtained by subtracting the desired source current from the load current as
i
∗
fk
= i
lk
−i
sk
= i
lk
−
2¯ p
l
3(V
m
)
2
v
sk
, k ∈ K. (4.58)
The average real power consumed or supplied by the active compensation circuit is
expressed as
¯ p
f
=
1
T
T
0
k∈K
v
sk
i
fk
dt. (4.59)
Substituting Equation 4.58 into Equation 4.59 yields
¯ p
f
=
1
T
T
0
k∈K
v
sk
i
lk
dt −
2¯ p
l
3(V
m
)
2
1
T
T
0
k∈K
v
2
sk
dt
= ¯ p
l
−
2¯ p
l
3(V
m
)
2
3(V
m
)
2
2
= ¯ p
l
− ¯ p
l
= 0. (4.60)
Therefore, the active compensation circuit does not consume or supply average real power.
4.6.3 Block Diagram of the Proposed Controller for the VIENNA Rectiﬁer
Figure 4.37 depicts the block diagramof the control circuit based on the proposed approach
to fulﬁll the function of the reference compensation current calculator. The source voltages
130 Power Electronics
v
sa
v
sb
PLL
v
sc
i
la
i
lb
V
m
÷
T
DI S
I
m
i
lc
i
lb
i
la
i
sa
i
sb
i
sc
2
3
I
m
sin(wt +f – 120°)
I
m
sin(wt +f + 120°)
I
m
sin(wt +f)
i
lc
p
a
p
b
p
c
p
l
i
*
fa
i
*
fb
i
*
fc
FIGURE 4.37 Block diagram of the controller.
are input to a phase lockedloop (PLL) where the peak voltage magnitude V
m
, the unity
voltages (i.e., v
sk
/V
m
), and the period T are generated. The average real power of the load
consumed is calculated using Equation 4.55 and is input to a divider to obtain the desired
source current amplitude I
m
in Equation 4.56. DI denotes the calculation of deﬁnite integral.
The desiredsource currents in Equation 4.57 andthe reference compensation currents of the
active compensation circuit in Equation 4.58 are computed by using the voltage magnitude
and the unity voltages.
Once the reference compensation currents are determined, they are input to a current
controller to produce control signals to the bidirectional switches. The block diagramof the
proposed control scheme is shown in Figure 4.38. The bidirectional switches are controlled
by the HCC technique to ensure sinusoidal input current with UPF and DClink voltage.
In addition, since the capacitor voltage must be maintained at a constant level, the power
losses caused by switching and capacitor voltage variations are supplied by the source. The
sum of the power losses, ¯ p
sw
, is controlled via a proportionalintegral (PI) controller and
is then input to the reference compensation current calculator. Since the rectiﬁer provides
continuous input currents, the current stresses on the switching devices are smaller and the
critical input inductor size can be reduced.
V
DC
v
sa
v
sb
v
sc
i
la
i
lb
i
lc
S
b
S
c
Threephase bridge
rectifier with
bidirectional switches
Hysteresis
current controller
Load
Reference
compensation current
calculator
PI
controller
S
a
V
*
dc
i
*
fa
i
*
fb
i
*
fc
p
sw
FIGURE 4.38 Block diagram of the control system.
Implementing Power Factor Correction in AC/DC Converters 131
4.6.4 Converter Design and Simulation Results
To verify the performance of the proposed control strategy, a MATLAB
®
–SIMULINK
®
prototype of the rectiﬁer is developed. Asinusoidal PWM(SPWM) voltage source inverter,
whichis a verypopular topologyinindustry, is usedas the DC/ACinverter for the intended
rectiﬁer–inverter AC motor drive topology (see Figure 4.39).
To illustrate the design feasibility of the proposed converter, a prototype with the
following speciﬁcations is chosen:
1. Input linetoline voltage 220 V.
2. DClink reference voltage 370 V.
3. Input inductance 5 mH.
4. Rated output power 1 kW.
AMATLAB
®
–SIMULINK
®
model for the proposedrectiﬁer–inverter structure is developed
to perform the digital simulation. Figure 4.40 shows the converter input phase current
waveformandits harmonic spectrumat ratedoutput power operation. The same waveform
for a conventional converter is shown in Figure 4.41.
v
sa
v
sb
v
sc
i
sa
i
sb
i
sc
D
1
D
3
AC/DC converter AC/DC inverter
D
5
Z
1
Z
3
Z
5
Z
2
Z
6
Z
4
C
b
C
a
V
DC
V
DC
M
Induction
motor
Bidirectional switches
with controller
Control
circuit Switching pulses
D
2
D
6
D
4
L
FIGURE 4.39 Complete diagram of the proposed UPF AC drive.
0.24 0.26 0.28 0.3
Time (s)
0.32 0.34 0.36 0.38
5
0
I
n
p
u
t
c
u
r
r
e
n
t
(
A
)
–5
18 16 14 12 10 8
Order of harmonic
6 4 2 0
M
a
g
n
i
t
u
d
e
b
a
s
e
d
o
n
B
a
s
e
p
e
a
k
—
p
a
r
a
m
e
t
e
r
1
0
2
3
4
FIGURE 4.40 Input current and spectral composition of the proposed scheme at rated load.
132 Power Electronics
5
0
I
n
p
u
t
c
u
r
r
e
n
t
(
A
)
–5
0.24 0.26 0.28 0.3
Time (s)
0.32 0.34 0.36 0.38 18 16 14 12 10 8
Order of harmonic
M
a
g
n
i
t
u
d
e
b
a
s
e
d
o
n
B
a
s
e
p
e
a
k
—
p
a
r
a
m
e
t
e
r
6 4 2 0
0
1
2
3
4
FIGURE 4.41 Input current and spectral composition of a typical commercial converter.
Before improvement, the THDof the rectiﬁer input current was foundto be 91.5%andthe
input PF was 0.72. After improvement, the input current THD was 3.8% and the input PF
was 0.999. Thus, with the proposed reference compensation current strategy, the harmonics
are effectively reduced and the PF is dramatically increased.
In order to show the performance of the converter under varying load conditions, it is
operatedbelowandabove its ratedvalue. The converter input phase current waveformand
its harmonic spectrum at 50% rated output power are shown in Figure 4.42. The converter
input PF is found to be 0.996 and the input current THD is 4.0%.
The converter input phase current waveform and its harmonic spectrum at 150% rated
output power are shown in Figure 4.43. The converter input PF is found to be 0.999 and the
input current THDis 3.7%. It is evident that the proposedcontrol strategy has a goodadapt
ability to different load conditions. This strategy can also be used for rectiﬁers operating at
various rated power levels.
Figure 4.44 illustrates the input phase currents and DClink voltage waveforms when the
converter output power demand changes instantaneously from 50% to 100% of its rated
value due to load disturbance. The load change was initiated at 0.26 s where the converter
was in steady state. One can clearly see that the converter exhibits a good response to the
5
0
I
n
p
u
t
c
u
r
r
e
n
t
(
A
)
–5
0.24 0.26 0.28 0.3
Time (s)
0.32 0.34 0.36 0.38
18 16 14 12 10 8
Order of harmonic
M
a
g
n
i
t
u
d
e
b
a
s
e
d
o
n
B
a
s
e
p
e
a
k
—
p
a
r
a
m
e
t
e
r
6 4 2 0
0
0.5
1
1.5
2
2.5
FIGURE 4.42 Input current and spectral composition of the proposed scheme at 50% rated load.
5
0
I
n
p
u
t
c
u
r
r
e
n
t
(
A
)
–5
0.24 0.26 0.28 0.3
Time (s)
0.32 0.34 0.36 0.38
18 16 14 12 10 8
Order of harmonic
M
a
g
n
i
t
u
d
e
b
a
s
e
d
o
n
B
a
s
e
p
e
a
k
—
p
a
r
a
m
e
t
e
r
6 4 2 0
0
2
4
6
FIGURE 4.43 Input current and spectral composition of the proposed scheme at 150% rated load.
Implementing Power Factor Correction in AC/DC Converters 133
5
0
I
n
p
u
t
c
u
r
r
e
n
t
(
A
)
–5
0.24 0.26 0.28 0.3
Time (s)
0.32 0.34 0.36 0.38 0.24
100
200
300
D
C
l
i
n
k
v
o
l
t
a
g
e
(
V
)
400
500
0.26 0.28 0.3
Time (s)
0.32 0.34 0.36 0.38
FIGURE 4.44 Converter response due to load change.
sudden load variation. From this ﬁgure, it can be seen that this proposed control technique
has a good adaptability to load variation.
4.6.5 Experimental Results
The control system is implemented using a singleboard dSPACE 1102 microprocessor and
is developedunder the integrateddevelopment of MATLAB
®
–SIMULINK
®
RTWprovided
by The MathWorks. A1kWhardware prototype of the rectiﬁer–inverter structure as shown
in Figure 4.39 was constructed and its performance was observed.
The rectiﬁer input current and voltage waveforms before and after improvements are
shown in Figures 4.45 and 4.46, respectively. The ﬂuke43 spectrum analyzer with online
numerical value illustration is used to monitor the waveforms. The input PF is shown
online at the upper righthand side of Figures 4.45 and 4.46. Prior to improvement, the
input current THD and PF were 91.5% and 0.72, respectively.
The proposedscheme is able toimprove the input current THDto3.8%andthe input PFto
0.99. There is a remarkable improvement in PF andTHD. The experimental results are iden
tical to the MATLAB
®
predicted ones calculated based on the waveforms in Figures 4.40
and 4.41. Figures 4.47 and 4.48 show the experimental input current fastFourier trans
form (FFT) spectrum for a typical conventional converter and the proposed converter,
respectively.
Power
0.51 kW
0.72 PF
1.00 DPF
50.0 Hz
0.71 kVA
0.49 kVAR
Full
100V
10A
Back Screen 1
0
0
FIGURE 4.45 Input voltage and current of a typical conventional converter.
134 Power Electronics
Power
0.51 kW
0.99 PF
1.00 DPF
50.1 Hz 0.51 kVA
0.01 kVAR
Fundamental
100V
10A
Back Screen 1
0
0
FIGURE 4.46 Input voltage and current of the proposed prototype.
At 50% rated output power, the converter input PF is found to be 0.99 and the input
current THD has increased to 4.0%, as shown in Figure 4.49. At 150% rated output power,
the converter input PF is found to be 0.99 and the input current THD is reduced to 3.7%
(see Figure 4.50).
Figure 4.51 shows the DClink voltage waveforms when the converter output power
demand changes instantaneously from 50% to 100% of its rated value responding to load
disturbance. One can see that with the proposed control strategy, the converter exhibits a
good response to sudden load variation.
To investigate the effect of input inductance, this was varied as well. Under 3 and 7 mH
input inductances, the converter input currents and voltages are shown in Figures 4.52
and4.53, respectively. These results illustrate that the proposedconverter withbidirectional
switches coupled with the proposed strategy overcomes most of the shortcomings of the
conventional converters such as change of input PF due to output power, input inductance,
and load torque variations.
Harmonics
91.5 THD%f
1
50.00 Hz
4.15 A
100%f
0°
5.64 rmsA
17.7 KF
Back Screen 3
100
%f
50
0
1 5 9 13 17 21 25 29 33 37 41 45 49
FIGURE 4.47 Input current FFT of a typical conventional converter.
Implementing Power Factor Correction in AC/DC Converters 135
Harmonics
3.8 THD%f
1
50.08 Hz
3.93 A
100%f
0°
3.93 rmsA
1.2 KF
Back
Screen 2
100
%f
50
0
1 5 9 13 17 21 25 29 33 37 41 45 49
FIGURE 4.48 Input current FFT of the proposed prototype conventional converter.
Harmonics
4.0 THD%f
1
50.00 Hz
1.97 A
100%f
0°
1.97 rmsA
2.0 KF
Back Screen 5
100
%f
50
0
1 5 9 13 17 21 25 29 33 37 41 45 49
FIGURE 4.49 Input current FFT of the proposed prototype at 50% rated load.
Harmonics
3.7 THD%f
1
50.08 Hz
5.86 A
100%f
0°
5.86 rmsA
1.1 KF
Back
Screen
7
100
%f
50
0
1 5 9 13 17 21 25 29 33 37 41 45 49
FIGURE 4.50 Input current FFT of the proposed prototype at 150% rated load.
136 Power Electronics
500
400
300
200
D
C
l
i
n
k
v
o
l
t
a
g
e
(
V
)
100
0.6 0.62 0.64
Time (s)
0.66 0.68
FIGURE 4.51 Converter response to a sudden load change in DClink voltage.
Power
0.51 kW
0.99 PF
1.00 DPF
49.9 Hz
0.51 kVA
0.01 kVAR
Fundamental
100V
10A
Back Screen
1
0
0
FIGURE 4.52 Converter input current and voltage for 3 mH input inductance.
Power
0.51 kW 1.00 PF
1.00 DPF
50.1 Hz
0.51 kVA
0.01 kVAR Fundamental
100V
10A
Back Screen 1
0
0
FIGURE 4.53 Converter input current and voltage for 7 mH input inductance.
Implementing Power Factor Correction in AC/DC Converters 137
Homework
4.1. A P/O selflift Luoconverter (see Figure 6.4 in Chapter 6) is used to imple
ment PFC in a singlephase diode rectiﬁer with R−C load. The AC supply
voltage is 200 V/60 Hz and the required output voltage is 400 V. The switch
ing frequency is 2.4 kHz. Determine the duty cycle k in a half supply period
(8.33 ms). Other component values for reference are R = 100 Ω, L
1
= L
2
= 10, and
C = C
1
= C
O
= 20 μF.
4.2. A P/O superlift Luoconverter (see Figure 7.1 in Chapter 7) is used to imple
ment PFC in a singlephase diode rectiﬁer with R−C load. The AC supply
voltage is 200 V/60 Hz and the required output voltage is 600 V. The switch
ing frequency is 3.6 kHz. Determine the duty cycle k in a half supply period
(8.33 ms). Other component values for reference are R = 100 Ω, L
1
= L
2
= 10, and
C = C
1
= C
O
= 20 μF.
References
1. Luo, F. L. and Ye, H. 2004. Advanced DC/DC Converters. Boca Raton: CRC Press.
2. Luo, F. L. 2005. A singlestage power factor correction AC/DC converter. Proceedings of the
International Conference IPEC 2005, pp. 513–518.
3. Mohan, N., Undeland, T. M., and Robbins, W. P. 2003. Power Electronics: Converters, Applications
and Design (3rd edition). New York: Wiley.
4. Wu, T. F. and Chen, Y. K. 1998. Asystematic and uniﬁed approach to modeling PWM DC/DC
converters based on the graft scheme. IEEE Transactions on Industrial Electronics, 45, 88–98.
5. Kheraluwala, M. H. 1991. Fastresponse high power factor converter with a single power stage.
Proceedings of the IEEEPESC, pp. 769–779.
6. Lee, Y. S. and Siu, K. W. 1996. Singleswitch fastresponse switching regulators with unity
power factor. Proceedings of the IEEEAPEC, pp. 791–796.
7. Shen, M. and Qian, Z. 2002. A novel highefﬁciency singlestage PFC converter with reduced
voltage stress. IEEE Transactions on Industry Applications, 49, 507–513.
8. Qiu, M. 1999. Analysis and design of a single stage power factor corrected fullbridge converter.
Proceedings of the IEEEAPEC, pp. 119–125.
9. Zhang, S. and Luo, F. L. 2009. Anovel reference compensation current strategy for threephase
threelevel unity PF rectiﬁer. Proceedings of the IEEEICIEA 2009, pp. 581–586.
10. Suryawanshi, H. M., Ramteke, M. R., Thakre, K. L., andBorghate, V. B. 2008. Unitypowerfactor
operation of threephase ACDCsoft switched converter based on boost active clamp topology
in modular approach. IEEE Transactions on Industrial Electronics, 55, 229–236.
11. Lu, D. D., Iu, H. H., and Jevalica, P. 2008. A singlestage AC/DC converter with high power
factor, regulated bus voltage, and output voltage. IEEE Transactions on Power Electronics, 23,
218–228.
12. Chen, J. F., Chen, R. Y., and Liang, T. J. 2008. Study and implementation of a singlestage
currentfed boost PFC converter with ZCS for high voltage applications. IEEE Transactions on
Power Electronics, 23, 379–386.
13. Kong, P., Wang, S., and Lee, F. C. 2008. Common mode EMI noise suppression for bridgeless
PFC converters. IEEE Transactions on Power Electronics, 23, 291–297.
14. Chen, M., Mathew, A., and Sun, J. 2007. Nonlinear current control of singlephase PFC
converters. IEEE Transactions on Power Electronics, 22, 2187–2194.
138 Power Electronics
15. Tutakne, D. R., Suryawanshi, H. M., and Tarnekar, S. G. 2007. Adaptive pulse synchronizing
control for highpowerfactor operation of variable speed DCdrive. IEEE Transactions on Power
Electronics, 22, 2499–2510.
16. Greul, R., Round, S. D., and Kolar, J. W. 2007. Analysis and control of a threephase, unity power
factor Yrectiﬁer. IEEE Transactions on Power Electronics, 22, 1900–1911.
17. Bendre, A. and Venkataramanan, G. 2003. Modeling and design of a neutral point regulator for
a three level diode clamped rectiﬁer, Proceedings of IEEE IAS 2003, pp. 1758–1765.
18. Kolar, J. W. and Drofenik, U. 1999. Anew switching loss reduced discontinuous PWM scheme
for a unidirectional threephase/switch/level boost type PWM(VIENNA) rectiﬁer. Proceedings
of the 21st INTELEC, Paper 292.
19. Kolar, J. W. and Zach, F. C. 1994. A novel threephase utility interface minimizing line cur
rent harmonics of highpower telecommunications rectiﬁer modules. Proceedings of the 16th
INTELEC, pp. 367–374.
20. Youssef, N. B. H., Fnaiech, F., andAlHaddad, K. 2003. Small signal modelingandcontrol design
of a threephase AC/DC Vienna converter. Proceedings of the 29th IEEE IECON, pp. 656–661.
21. Mehl, E. L. M. and Barbi, I. 1997. An improved high power factor and low cost threephase
rectiﬁer. IEEE Transactions on Industry Applications, pp. 485–492.
22. Salmon, J. 1995. Circuit topologies for PWMboost rectiﬁers operated from1phase and 3phase
AC supplies and using either single or split DC rail voltage outputs. Proceedings of the IEEE
Applied Power Electronics Conference, pp. 473–479.
23. Kolar, J. W. and Zach, F. C. 1997. Anovel threephase utility interface minimizing line current
harmonics of highpower telecommunications rectiﬁers modules. IEEETransactions on Industrial
Electronics, 456–467.
24. Kolar, J. W., Ertl, H., andZach, F. C. 1996. Designandexperimental investigationof a threephase
high power density high efﬁciency unitypowerfactor PWM (VIENNA) rectiﬁer employing a
novel integrated power semiconductor module. Proceedings of APEC 96, pp. 514–523.
25. Maswood, A. I., Yusop, A. K., and Rahman, M. A. 2002. A novel suppressedlink rectiﬁer–
inverter topology with unity power factor. IEEE Transactions on Power Electronics, 692–700.
26. Drofenik, U. and Kolar, J. W. 1999. Comparison of not synchronized sawtooth carrier and
synchronized triangular carrier phase current control for the VIENNArectiﬁer I. Proceedings of
IEEE ISIE, pp. 13–18.
27. Maswood, A. I. andLiu, F. 2005. Anovel unitypower factor input stage for ACdrive application.
IEEE Transactions on Power Electronics, pp. 839–846.
28. Qiao, C. and Smedley, K. M. 2003. Threephase unitypowerfactor starconnected switch
(VIENNA) rectiﬁer with uniﬁed constantfrequency integration control. IEEE Transactions on
Power Electronics, 952–957.
29. Liu, F. and Maswood, A. I. 2006. Anovel variable hysteresis band current control of threephase
threelevel unity PF rectiﬁer with constant switching frequency. IEEE Transactions on Power
Electronics, 1727–1734.
30. Maswood, A. I. and Liu, F. 2006. Aunity power factor frontend rectiﬁer with hysteresis current
control. IEEE Transactions on Energy Conversion, 69–76.
31. Maswood, A. I. and Liu, F. 2007. A unitypowerfactor converter using the synchronous
referenceframebased hysteresis current control. IEEE Transactions on Industry Applications,
593–599.
5
Ordinary DC/DC Converters
According to certain statistics, there are more than 600 prototypes at present of DC/DC. In
their book Advanced DC/DC Converters [1,2], the authors have systematically sorted them
into six categories. According to the systematic categorization, the ordinary converters
introduced in this book will fall under these generations.
5.1 Introduction
DC/DC conversion technology is an important area of research and has industrial appli
cations. Since the last century, the DC/DC conversion technique has been extensively
developedandthere are nowmany newtopologies of DC/DCconverters. DC/DCconvert
ers are now widely used in communication equipment, cell phones and digital cameras,
computer hardware circuits, dental apparatus, and other industrial applications. Since
there are a lot of DC/DC converters, we have sorted them into six generations: ﬁrst
generation (classical/traditional), secondgeneration (multiquadrant), thirdgeneration
(switchedcomponent), fourthgeneration (softswitching), ﬁfthgeneration (synchronous
rectiﬁer), and sixthgeneration (multielement resonant power).
The ﬁrstgeneration DC/DC converters are socalled classical or traditional converters.
These converters operate ina singlequadrant mode andina lowpower range (upto100 W).
Since there are a large number of prototype converters in this generation, they are further
sorted into the following six categories [1–5]:
• Fundamental
• Transformertype
• Developed
• VL
• SL
• UL
Fundamental converters such as the buck converter, the boost converter, and the buck–
boost converter are named after their functions. These three prototypes perform basic
functions and therefore will be investigated in detail. Because of the effects of parasitic ele
ments, the output voltage and power transfer efﬁciency of these converters are restricted.
As a consequence, transformertype and developed converters were created.
The VL technique is a popular method that is widely applied in electronic circuit design.
Applying this technique can effectively overcome the effects of parasitic elements and
139
140 Power Electronics
greatly increase the voltage transfer gain. Therefore, these DC/DC converters can con
vert the source voltage into a higher output voltage with a high power efﬁciency, a high
power density, and a simple structure. The SL and UL techniques are even more powerful
methods that are used to increase the voltage transfer gain in power series.
The secondgeneration converters perform twoquadrant or fourquadrant operation
with output power in a medium range (say, 100–1000 W). These converters are usually
used in industrial applications, for example, DC motor drives with multiquadrant opera
tion. Since most secondgeneration converters are still made of capacitors and inductors,
they are large in size.
The thirdgeneration converters are called switchedcomponent DC/DC converters; as
they are made of either capacitors or inductors, they are called switchedcapacitor convert
ers or switchedinductor converters, respectively. They usually perform twoquadrant or
fourquadrant operationwithoutput power ina highrange (say, 1000 W). Since they consist
of only capacitors or inductors, they are small in size.
Switchedcapacitor DC/DC converters consist of capacitors only. Since switched
capacitors can be integrated into power semiconductor integrated circuit (IC) chips, they
have a limited size and work at a high switching frequency. They have been successfully
employed in inductorless DC/DC converters and this has opened up the way for the con
struction of converters with a high power density. As a consequence, they have received a
great deal of attention fromresearch workers andmanufacturers. However, most switched
capacitor converters in the literature perform singlequadrant operation and work in the
push–pull status. In addition, their control circuit and topologies are very complex due to
the large difference between input and output voltages.
Switchedinductor DC/DC converters consist of inductors only and have been derived
from fourquadrant choppers. They usually perform multiquadrant operation with a very
simple structure. Two advantages of these converters are simplicity and high power den
sity. No matter how large the difference between the input and output voltages, only one
inductor is required for each switchedinductor DC/DC converter. Consequently, they are
widely used in industrial applications.
The fourthgeneration converters are calledsoftswitching converters. The softswitching
technique involves many methods for implementing resonance characteristics with res
onant switching a popular method. There are two main groups of fourthgeneration
converters: zerocurrentswitching (ZCS) and zerovoltageswitching (ZVS). As described
in the literature, they usually perform in singlequadrant operation.
ZCS and ZVS converters have large current and voltage stresses. In addition, the con
duction duty cycle k and switching frequency f are not individually adjusted. In order to
overcome these drawbacks, zerovoltagepluszerocurrentswitching (ZV/ZCS) and zero
transition (ZT) converters were developed, which implement the ZVS and ZCS techniques
in the operation. Since the switches turn on and off at the moment the voltage and/or
current is equal to zero, the power losses during switchingon and switchingoff become
zero. As a consequence, these converters have a high power density and a high transfer
efﬁciency. Usually, the repeating frequency is not very high and the converter works in the
resonance state. As the components of higherorder harmonics are very low, the EMI is low
and EMS and EMC should be reasonable.
The ﬁfthgeneration converters are called synchronous rectiﬁer DC/DC converters. Cor
responding to the development of microelectronics and computer science, power supplies
with low output voltage and strong current are widely required in industrial applications.
These power supplies provide very lowvoltages (5, 3.3, 2.5, and 1.8–1.5 V) and a strong cur
rent (30, 60, and 100–200A) with a high power density and a high power transfer efﬁciency
Ordinary DC/DC Converters 141
(88%, 90–92%). Traditional diode bridge rectiﬁers are not available for this requirement. The
new type of synchronous rectiﬁer DC/DC converters can realize these technical features.
The sixthgeneration converters are called multielement resonant power converters
(RPC). There are eight topologies of twoelement RPC, 38 topologies of threeelement RPC,
and 98 topologies of fourelement RPC. They are widely applied in military equipment and
industrial applications.
The DC/DC converter family tree is shown in Figure 5.1.
In this book, the input voltage is represented by V
1
and/or V
I
(V
in
), the output voltage
by V
2
and/or V
O
, the input current by I
1
and/or I
I
(I
in
), and the output current by I
2
and/or
I
O
. The switching frequency is represented by f and the switching period is represented
by T = 1/f . The conduction duty cycle/ratio is represented by k and k is the ratio of the
switchingon time over the period T. The value of k is in the range of 0 < k < 1.
5.2 Fundamental Converters
Fundamental converters are exempliﬁed by the buck converter, the boost converter, the
buck–boost converter, and the P/O buck–boost converter. Considering the input current
continuity, we can divide all DC/DC converters into two main modes: continuous input
current mode (CICM) and discontinuous input current mode (DICM). The boost converter
operates in CICM whereas the buck converter and the buck–boost converter operate in
DICM [6–12].
5.2.1 Buck Converter
Abuck converter is shown in Figure 5.2a. It converts the input voltage into output voltage
that is less than the input voltage. Its switchon andswitchoff equivalent circuits are shown
in Figure 5.2b and 5.2c.
5.2.1.1 Voltage Relations
When switch S is on, the inductor current increases. For easy analysis in the steady state, we
assume that the capacitor C is large enough (the ripple can be negligible), namely v
C
= V
2
.
Therefore, we have
V
1
= v
L
+v
C
= L
di
L
dt
+v
C
, (5.1)
di
L
dt
=
V
1
−v
C
L
=
V
1
−V
2
L
. (5.2)
For the period of time kT, the inductor current increases at a constant slope (V
1
−V
2
)/L
(see Figure 5.3). The inductor current starts at the initial value I
min
and changes to a top
value I
max
at the end of the switchclosure period.
142 Power Electronics
D
C
/
D
C
c
o
n
v
e
r
t
e
r
s
1G
classical
converters
2G
multiquadrant
converters
3G
switched
component
converters
4G
softswitching
converters
5G
synchoronous
rectiﬁer
converters
6G
multielements
resonant power
converters
Fundamental
circuits
Developed
Transformer
Voltage lift
Superlift
Buck converters
Boost converters
Buckboost converters
Positive output Luoconverters
Negative output Luoconverters
Double output Luoconverters
Cúkconverters
SEPIC
Forward converters
Pushpull converters
Halfbridge converters
Bridge converters
Flyback converters
ZETA converters
Positive output Luoconverters
Negative output Luoconverters
7 selflift converters
Modiﬁed P/O Luoconverters
Double output Luoconverters
Positive output cascaded boost converters
Negative output cascaded boost converters
Positive output superlift Luoconverters
Negative output superlift Luoconverters
Switchedcapacitor converters
Multiquadrant Luoconverters
Two quadrants converters
Four quadranrts SC Luoconverters
MultiLift
P/O multilift pushpull
Luoconverters
N/O multilift pushpull
Luoconverters
Switchedinductor converters
ZCSQRCFour quadrants zerocurrent switching Luoconverters
ZVSQRC Four quadrants zerovoltage switching Luoconverters
ZTC Four quadrants zerotransition Luoconverters
2Elements
3Elements
4Elements
Double gammaCL current source resonant inverters
Reverse double gammaCL resonant power converters
Flattransformer synchronous rectifier converters
Synchronous rectiﬁer converter with active clamp circuit
Double current synchronous rectifier converters
ZCS synchronous rectifier converters
ZVS synchronous rectifier converters
Transformertype converters
Developed
Transformertype converters
Four quadranrts SI Luoconverters
Tappedinductor converters
Voltagelift SEPIC
Voltagelift Cúkconverters
Voltagelift D/O converters
Switchedcapacitorized converters
Ultralift Luoconverters
’–CLL Current source resonant inverters
FIGURE 5.1 DC/DC converter family tree.
Ordinary DC/DC Converters 143
i
1
i
1
i
2
V
1
V
1 V
2
V
2
i
2
D C
C R C R
+
+
–
+
–
V
2
+
–
–
+
–
R
(a)
(b) (c)
S L
L
i
2
L
FIGURE 5.2 A buck converter and its equivalent circuits: (a) buck converter, (b) switchon, and (c) switchoff.
(Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC,
p. 22. With permission.)
When the switch is off, the inductor current decreases and freewheels through the diode.
We have the following equations:
0 = v
L
+v
C
, (5.3)
di
L
dt
= −
v
C
L
= −
V
2
L
. (5.4)
When the switch is off in the time interval (1 −k)T, the inductor current decreases with
a constant slope −V
2
/L from I
max
to I
min
. The ending value I
min
must be the same as that
at the beginning of the period in the steady state. The current increment during switchon
is equal to the current decrement during switchoff:
I
max
−I
min
=
V
1
−V
2
L
kT, (5.5)
I
min
−I
max
=
−V
2
L
(1 −k)T. (5.6)
Thus,
V
1
−V
2
L
kT =
V
2
L
(1 −k)T, V
2
= kV
1
. (5.7)
The output voltage (capacitor voltage) depends solely on the duty cycle k and the input
voltage. From Figure 5.3, it can be seen that the input source current i
1
(which is equal to
switch current i
S
) is discontinuous. Consequently, the buck converter operates in DICM.
144 Power Electronics
i
S
i
D
i
L
v
L
V
1
–V
C
i
max
i
min
i
max
i
min
i
max
i
min
0
kT T t
0
kT T t
0
kT T t
0
kT T t
–V
C
FIGURE 5.3 Some current and voltage waveforms of the buck converter.
5.2.1.2 Circuit Currents
From Figure 5.3, we can ﬁnd the average value of inductor current easily by inspecting the
waveform:
I
L
=
I
max
+I
min
2
. (5.8)
Applying the Kirchhoff current law (KCL), we have
i
L
= i
C
+i
2
. (5.9)
Because the average capacitor current is zero in periodic operation, the result can be written
by averaging values over one period of operation:
I
L
= I
2
. (5.10)
By Ohm’s law, the current I
2
is given by
I
2
=
V
2
R
. (5.11)
Ordinary DC/DC Converters 145
Considering Equations 5.5, 5.10, and 5.11, we have
I
max
+I
min
= 2
V
2
R
, (5.12)
I
max
= kV
1
_
1
R
+
1 −k
2L
T
_
, (5.13)
I
min
= kV
1
_
1
R
−
1 −k
2L
T
_
. (5.14)
5.2.1.3 Continuous Current Condition (Continuous Conduction Mode)
If I
min
is zero, we obtain a relation for the minimuminductance that results in a continuous
inductor current:
L
min
=
1 −k
2
TR (5.15)
5.2.1.4 Capacitor Voltage Ripple
The condition that there are no ripples in the capacitor voltage is now relaxed to allow a
small ripple. This has only a secondorder effect on the currents calculated in the previous
section, so the previous results can be used without change.
As noted previously, in order to have periodic operation, the capacitor current must
be entirely alternating. The graph of the capacitor current needs to be as shown in
Figure 5.4 for the continuous inductor current. The peak value of this triangular wave
form is (I
max
−I
min
)/2. The resulting ripple in the capacitor voltage depends on the area
under the curve of the capacitor current versus time. The charge added to the capacitor in
a halfcycle is given by the triangular area above the axis:
ΔQ =
1
2
I
max
−I
min
2
T
2
=
I
max
−I
min
8
T. (5.16)
v
C
0
i
C
0
t
T
kT
t
T
kT
Dv
C
FIGURE 5.4 Waveforms of i
C
and v
C
.
146 Power Electronics
The graph of the capacitor voltage is also shown in the lower graph of Figure 5.4. The
ripple in the voltage is exaggerated to show its effect. Minimum and maximum capacitor
voltage values occur at the time the capacitor current becomes zero. The peaktopeak value
of the capacitor voltage ripple is given by
Δv
C
= ΔQ/C =
I
max
−I
min
8C
T =
k(1 −k)V
1
8CL
T
2
. (5.17)
Example 5.1
A buck converter has the following components: V
1
= 20V, L = 10mH, C = 20μF, R = 20Ω,
switching frequency f = 20kHz, and conduction duty cycle k = 0.6. Calculate the output voltage
and its ripple in the steady state. Does this converter work in CCM or discontinuous conduction
mode (DCM)?
SOLUTION
1. From Equation 5.7, the output voltage is V
2
= kV
1
= 0.6 ×20 = 12V.
2. From Equation 5.17, the output voltage ripple is
Δv
2
= Δv
C
=
k(1 −k)V
1
8CL
T
2
=
0.6 ×0.4 ×20
8 ×20μF ×10mH×(20k)
2
= 7.5mV.
3. From Equation 5.15, the inductor
L = 10mH > L
min
=
_
1 −k
2
_
TR =
_
0.4
2 ×20k
_
20 = 0.2mH.
This converter works in CCM.
5.2.2 Boost Converter
If the three elements S, L, andDof the buckconverter are rearrangedas showninFigure 5.5a,
a boost converter is created. Its equivalent circuits during switchon and switchoff are
shown in Figure 5.5b and 5.5c.
5.2.2.1 Voltage Relations
When the switch S is on, the inductor current increases:
di
L
dt
=
V
1
L
. (5.18)
Since the diode is inversely biased, the capacitor supplies current to the load, and the capac
itor current i
C
is negative. Upon opening the switch, the inductor current must decrease so
that the current at the end of the cycle can be the same as that at the start of the cycle in the
steady state. For the inductor current to decrease, the value V
C
= V
2
must be >V
1
. For this
interval with the switch open, the inductor current derivative is given by
di
L
dt
=
V
1
−V
C
L
=
V
1
−V
2
L
. (5.19)
Agraph of the inductor current versus time is shown in Figure 5.6.
Ordinary DC/DC Converters 147
i
2
i
2
i
2
i
1
i
1
i
1
i
L
i
L
i
L
i
C
i
C
i
C
V
1
V
1
V
D
V
C
V
C
V
C
D
R
R
R
S
C
C
C
L
L
L
(a)
(b)
(c)
+
–
V
2
V
2
V
2
V
1
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
FIGURE 5.5 Boost converter: (a) circuit, (b) switchon, and (c) switchoff. (Reprinted from Luo, F. L. and Ye, H.
2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 23. With permission.)
The increment of i
L
during switchon must be equal to its decrement during switchoff:
I
max
−I
min
=
V
1
L
kT (5.20)
and
I
min
−I
max
=
V
1
−V
C
L
(1 −k)T; (5.21)
V
2
= V
C
=
V
1
1 −k
. (5.22)
From Equation 5.22, we can see that if k is large, the output voltage V
2
can be very large. In
fact, as k approaches unity, the output voltage decreases rather than increasing because of
the effect of circuit parasitic elements. The value of k must be limited within a certain upper
limit (say 0.9) to prevent such a problem. Practical limits to this also become important for
an increase in the voltage transfer gain, for example, 10. The switch may be open for only
a very short time (0.1 T since k = 0.9).
5.2.2.2 Circuit Currents
The I
max
and I
min
values can be found via the input average power and the load average
power, if there are no power losses:
P
in
=
I
max
+I
min
2
V
1
(input power) (5.23)
and
P
O
=
V
2
2
R
(output power). (5.24)
148 Power Electronics
i
max
i
min
i
S
i
D
0
kT
T t
i
max
i
min
0
kT
T t
i
L
V
1
i
max
i
min
0
kT
T t
v
L
0
kT
–(V
C
– V
1
)
T t
FIGURE 5.6 Some current and voltage waveforms.
Considering Equation 5.22, we have
I
max
+I
min
= 2
V
1
R(1 −k)
2
. (5.25)
From Equations 5.21 and 5.25
I
min
=
V
1
R(1 −k)
2
−
V
1
2L
kT, (5.26)
I
max
=
V
1
R(1 −k)
2
+
V
1
2L
kT. (5.27)
The loadcurrent value I
2
is givenbyI
2
= V
2
/R, andthe average current ﬂowingthroughthe
capacitor is zero. The instantaneous capacitor current is likelya triangular waveform, which
is approximately (i
L
−I
2
) during switchoff and −I
2
during switchon. From Figure 5.6,
the input source current i
1
= i
S
= i
L
is continuous. Hence, the buck converter operates in
CICM.
Ordinary DC/DC Converters 149
5.2.2.3 Continuous Current Condition
When the I
min
is equal to zero, the minimum inductance can be determined to ensure a
continuous inductor current. Using Equation 5.26 and solving it, we obtain
L
min
=
k(1 −k)
2
2
TR. (5.28)
5.2.2.4 Output Voltage Ripple
The change of the charge across the capacitor C is
ΔQ = kTI
2
= kT
V
2
R
=
kTV
1
(1 −k)R
.
Therefore, the ripple voltage Δv
C
across the capacitor C is
Δv
C
=
ΔQ
C
=
kTV
2
RC
=
kTV
1
(1 −k)RC
. (5.29)
5.2.3 Buck–Boost Converter
If the three elements S, D, and L in a boost converter are rearranged as shown in Figure 5.7a,
a buck–boosttype converter is created. Applying a similar analysis to this converter, we can
easily obtain all the characteristics of a buck–boost converter under steadystate operating
conditions.
5.2.3.1 Voltage and Current Relations
With the switch closed, the inductor current changes:
di
L
dt
=
V
1
L
(5.30)
i
2
i
2
i
2
i
1
i
1
i
L
i
L
i
L
i
C
i
C
i
C
V
1
V
1
V
D
V
C
V
C
V
C
D
R
R
R
S
C
C
C
L
L
L
(a)
(b)
(c)
–
+
V
2
V
2
V
2
–
+
+
–
+
–
+
–
+
–
–
+
+
–
FIGURE 5.7 Buck–boost converter: (a) circuit, (b) switchon, and (c) switchoff. (Reprinted from Luo, F. L. and
Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 151. With permission.)
150 Power Electronics
and
I
max
−I
min
=
V
1
L
kT. (5.31)
With the switch open,
di
L
dt
= −
V
C
L
(5.32)
and
I
min
−I
max
= −
V
C
L
(1 −k)T. (5.33)
Equating these two changes in i
L
gives the result
V
2
= V
C
=
k
1 −k
V
1
. (5.34)
5.2.3.2 CCM Operation and Circuit Currents
Some waveforms are shown in Figure 5.8. The input source current i
1
= i
S
is discontinuous
during switchoff. Hence, the buck–boost converter operates in DICM. The input average
power is then found from
P
in
=
I
max
+I
min
2
kV
1
(input power), (5.35)
and
P
O
=
V
2
2
R
(output power). (5.36)
Other parameters are listed below:
I
max
+I
min
=
2kV
1
R(1 −k)
2
, (5.37)
I
min
=
kV
1
R(1 −k)
2
−
V
1
2L
kT, (5.38)
I
max
=
kV
1
R(1 −k)
2
+
V
1
2L
kT. (5.39)
The boundary for a continuous current is found by setting I
min
to zero; this deﬁnes a
minimum inductance to ensure a continuous inductor current. Using Equation 5.38 and
solving it, we obtain
L
min
=
(1 −k)
2
2
TR. (5.40)
The ripple voltage Δv
C
across the capacitor C is
Δv
C
=
ΔQ
C
=
kTI
2
C
=
kTV
2
RC
=
k
2
TV
1
(1 −k)RC
. (5.41)
Ordinary DC/DC Converters 151
i
S
i
D
i
L
v
L
V
1
i
max
i
min
0
kT T t
i
max
i
min
0
kT T t
i
max
i
min
0
0
kT T t
kT T t
–V
C
FIGURE 5.8 Some current and voltage waveforms.
Example 5.2
A buck–boost converter has the following components: V
1
= 20V, L = 10mH, C = 20μF,
R = 20Ω, switching frequency f = 50kHz, and conduction duty cycle k = 0.6. Calculate the
output voltage and its ripple in the steady state. Does this converter work in CCM or DCM?
SOLUTION
1. From Equation 5.34, the output voltage is
V
2
= V
C
=
k
1 −k
V
1
=
0.6
0.4
20 = 30V.
2. From Equation 5.41, the output voltage ripple is
Δv
2
= Δv
C
=
kV
2
fRC
=
0.6 ×20
50k ×20 ×20μ
= 0.6V.
152 Power Electronics
3. From Equation 5.40, the inductor
L = 10mH > L
min
=
1 −k
2
TR =
0.4
2 ×50k
20 = 0.08mH.
This converter works in CCM.
5.3 P/O Buck–Boost Converter
Traditional buck–boost converters have negative output (N/O) voltage. In some applica
tions, changing the voltage polarity is not allowed. For example, the Liion battery is the
common choice for most portable applications such as mobile phones and digital cameras.
With the increasing use of lowvoltage portable devices and increasing requirements of
functionalities embedded into such devices, efﬁcient power management techniques are
needed for a longer battery life. The voltage of a single Liion battery varies from 4.2 to
2.7 V. ADC/DCconverter is needed to maintain the varying voltage of the Liion battery at
a constant value of 3.3 V. This converter needs to operate in both the stepup and stepdown
conditions. Smooth transition fromthe buck mode to the boost mode is the most desiredcri
teria for a longer battery life. AP/Obuck–boost converter with two independent controlled
switches is shown in Figure 5.9.
There are three operation modes shown in Figure 5.10:
• Buck operation mode, if V
1
is higher than V
2
• Boost operation mode, if V
1
is lower than V
2
• Buck–boost operation mode, if V
1
is similar to V
2
.
Here V
2
= 3.3 V for this application.
This converter can work as a buck converter or a boost converter depending on input–
output voltages. The problemof output regulation with guaranteedtransient performances
for noninverting buck–boost converter topology is discussed. Various digital control tech
niques are addressed, whichcansmoothlyperformthe transitionjob. Inthe ﬁrst two modes,
the operation principles are the same as those of the buck converter and the boost converter
described in the previous section. The third operation needs to be described here.
i
1
i
2
S
1
S
2
D
2
V
1
V
2
D
1
+
–
+
–
i
L
L
C
R
FIGURE 5.9 Circuit diagram of a P/O buck–boost converter.
Ordinary DC/DC Converters 153
V
1H
=
4.2 V
V
1L
=
2.7 V
V
V
1
ª
V
2
V
1
<
V
2
V
1
>
V
2
V
2
A
B
Buck
Ta Tb Tc t
Boost Buckboost
FIGURE 5.10 Input and output characteristics curves of the P/O buck–boost converter.
5.3.1 Buck Operation Mode
When the input voltage V
1
is higher than the output voltage V
2
(e.g., V
1
> 1.03V
2
, say
3.4 V), the positive buck–boost converter can be operated in the “Buck Operation Mode.”
In this case, the switch S
2
is constantly open, and the diode D
2
will be constantly on. The
remaining components are the same as those of a buck converter.
5.3.2 Boost Operation Mode
When the input voltage V
1
is lower than the output voltage V
2
(e.g., V
1
> 0.97V
2
, say
3.2 V), the positive buck–boost converter can be operated in the “Boost Operation Mode.”
In this case, the switch S
1
is constantly on, and the diode D
1
will be constantly blocked. The
remaining components are the same as those of a boost converter.
5.3.3 Buck–Boost Operation Mode
When the input voltage V
1
is nearly equal to the output voltage V
2
(e.g., 3.2 V< V
1
< 3.4 V),
the positive buck–boost converter can be operated in the “buck–boost operation mode.” In
this case, both the switches S
1
and S
2
switch on and switch off simultaneously. When the
switches are on, the inductor current increases:
Δi
L
=
V
1
L
kT. (5.42)
When the switches are off, the inductor current decreases:
Δi
L
=
V
2
L
(1 −k)T. (5.43)
Hence
V
2
=
k
1 −k
V
1
. (5.44)
154 Power Electronics
The other parameters can be determined by the corresponding formulae of the normal
buck–boost converter. Therefore, the positive buck–boost converter operates in“buck–boost
operation mode,” and the output voltage keeps positive polarity.
Whenthis converter works in“buck operationmode” and“buck–boost operationmode,”
its input current is discontinuous, that is, it works in DICM.
5.3.4 Operation Control
The general control block diagram is shown in Figure 5.11. It implements two functions:
logic control to select the operationmode andvoltage closedloopcontrol to keepthe output
voltage constant.
Refer to Figure 5.11. When the input voltage V
1
is higher than the upper limit voltage, for
example, 1.03V
ref
(here the upper limit voltage is set as 3.4 V) as the point Ain Figure 5.10,
the P/O buck–boost converter operates in the buck mode. When the input voltage V
1
is
lower than the lower limit voltage, for example, 0.97V
ref
(the upper limit voltage is set as
3.2 V) as the point B in Figure 5.10, the P/O buck–boost converter operates in the boost
mode. When the input voltage V
1
is that between the upper and lower limit voltages, for
example, 0.97V
ref
< V
1
< 1.03V
ref
, the P/O buck–boost converter operates in the buck–
boost mode.
The output voltage feedback signal compares with the V
ref
= 3.3 V to regulate the duty
cycle k inorder to keepthe output voltage V
2
= 3.3 V. Inorder to analyze the performance of
the systemduring operation in the buck and boost modes and the behavior of the systemin
transition, the typical parameters of the converter are showninTable 5.1. The voltage source
is modeledto act as a singlecell Liionbattery, whose voltage varies fromV
1H
= 4.2 Vwhen
it is fully charged to V
1L
= 2.7 V when it is not charged.
A proportionalintegral (PI) controller is used for voltage closedloop control. All logic
operations and the voltage feedback control diagram of the P/O buck–boost converter are
shown in Figure 5.12.
The simulation results are shown in Figure 5.13.
A test rig is constructed for experimental testing. The measured results are shown in
Table 5.2.
V
1
Buck
Boost
Control
logic
Saw tooth
waveform
Controller
S
1
S
2
Buckboost
Upper limit
voltage
Lower limit
voltage
V
2feedback
V
ref
+
+
+
–
–
–
+
–
FIGURE 5.11 General control block diagram.
Ordinary DC/DC Converters 155
TABLE 5.1
Circuit Parameters of the P/O Buck–Boost Converter
Variable Parameter Value
L Magnetizing inductance 220 μH
C Output ﬁlter capacitance 500 μF
V
1
Input voltage 4.2–2.7 V
Upper limit voltage 3.4 V
V
ref
Output voltage reference 3.3 V
Lower limit voltage 3.2 V
R Load resistance 7 Ω
f Switching frequency 20 kHz
5.4 TransformerType Converters
Transformertype converters consist of transformers and other parts. They can isolate the
input and output circuits, and have additional voltage transfer gain corresponding to the
winding turn’s ratio n. After reviewing popular topologies, a few new circuits will be
introduced.
• Forward converter
• Flyback converter
220u
V
ref_L
3.2
–
–
+
+
+
+
–
+
–
–
–
+
–
VLS
PI
Sawtooth
50K
+
–
+
–
+
V
ref_H
3.4
V
ref
3.3
–
–
+
+
500u
–R
+
+
+
+
V
O
7
Q1
D2
L
V
in
D1 Q2 C
>
FIGURE 5.12 Simulation diagram of the P/O buck–boost converter.
156 Power Electronics
0.00
1.00
2.00
3.00
4.00
5.00
6.00
(a)
(b)
(c)
V
1
V
O
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
V
1
V
O
Time (s)
0.00
0.00
1.00
2.00
3.00
4.00
5.00
6.00
V
1
V
O
0.10 0.20 0.30 0.40 0.50
Time (s)
0.00 0.10 0.20 0.30 0.40 0.50
Time (s)
0.00 0.10 0.20 0.30 0.40 0.50
FIGURE 5.13 Simulation results: (a) buck mode operation with V
1
= 4.0 V, (b) boost mode operation with
V
1
= 2.8 V, and (c) overall operation with V
1
= 2.7–4.2 V.
Ordinary DC/DC Converters 157
TABLE 5.2
Measured Simulation Results
Step V
in
V
out
1 4.20000 3.30
2 4.15909 3.30
3 3.99091 3.30
4 3.75748 3.30
5 3.54412 3.30
6 3.44875 3.30
7 3.18519 3.30
8 3.08228 3.30
9 2.95426 3.30
10 2.82877 3.30
11 2.70000 3.30
• Push–pull converters
• Halfbridge converters
• Bridge converters
• Zeta converter.
5.4.1 Forward converter
A forward converter is the ﬁrst transformertype converter, and is widely applied in
industrial applications.
5.4.1.1 Fundamental Forward Converter
The forward converter shown in Figure 5.14 is a transformertype topology, which consists
of a transformer andother parts inthe circuits. This converter insolates the input andoutput
circuitry. Therefore, the output voltage can be applied in any ﬂoating circuit. Furthermore,
since the secondary winding polarity is reversible, it is very convenient to perform N/O
and multiquadrant operation. In this text explanation, the polarity is shown in Figure 5.14,
which means that the output voltage is positive.
1:n D
1
D
2
C R
L
+
+
–
–
Control
V
1
V
2
T
1
FIGURE 5.14 Forward converter. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 24. With permission.)
158 Power Electronics
V
C
V
2
i'
1
i
L
i
L
i
C i
C
R
i
2
L
+
nV
1
–
(a) (b)
+
–
+
–
C
V
2
V
C
i
2
L
+
–
+
–
R
C
FIGURE 5.15 Equivalent circuits: (a) switchingon and (b) switchingoff.
In Figure 5.14, n is the transformer turn’s ratio and k is the conduction duty cycle. The
turn’s ratio n can be any value greater or smaller than unity; the conduction duty cycle k is
deﬁnitely smaller than unity.
The equivalent circuits during switchingon and switchingoff are shown in Figure 5.15a
and 5.15b. During switchingon, we have the following equations:
nV
1
= v
L
+v
C
, nV
1
= L
di
L
dt
+V
C
,
di
L
dt
=
nV
1
−V
C
L
. (5.45)
During switchingoff, we have the following equations:
0 = v
L
+v
C
, 0 = L
di
L
dt
+V
C
,
di
L
dt
=
−V
C
L
. (5.46)
Some voltage and current waveforms are shown in Figure 5.16.
In the steady state, the current increment (I
max
−I
min
) during switchingon is equal to
the current decrement (I
min
−I
max
) during switchingoff. We have obtained the following
Equations to determine the voltage transfer gain:
I
max
−I
min
=
nV
1
−V
C
L
kT, (5.47)
I
min
−I
max
=
−V
C
L
(1 −k)T. (5.48)
Thus,
nV
1
−V
C
L
kT =
V
C
L
(1 −k)T, (5.49)
(nV
1
−V
C
)kT = V
C
(1 −k)T,
V
2
= V
C
= nkV
1
. (5.50)
Ordinary DC/DC Converters 159
i
S
/n
nV
1
–V
C
i
D
v
L
i
max
i
min
0
i
max
i
min
0
kT T t
kT T t
i
L
i
max
i
min
0
0
kT T t
kT T t
–V
C
FIGURE 5.16 Some voltage and current waveforms.
FromFigure 5.16, we can ﬁnd the average value of the inductor current easily by inspecting
the waveform.
I
L
= I
2
=
V
2
R
=
I
max
+I
min
2
. (5.51)
The values of I
max
and I
min
are expressed below:
I
max
= V
2
_
1
R
+
1 −k
2L
T
_
, (5.52)
I
min
= V
2
_
1
R
−
1 −k
2L
T
_
. (5.53)
160 Power Electronics
i
C
v
C Δv
C
0
kT T t
kT T t
FIGURE 5.17 Waveforms of i
C
and v
C
.
If the I
min
is greater than zero, we call the operation the CCM, and vice versa, the DCM.
Solving Equation 5.53 for a zero value of I
min
yields a relation for the minimum value of
circuit inductance, which results in continuous inductor current:
L
min
=
1 −k
2
TR. (5.54)
The rippleless condition in the capacitor voltage is now relaxed to allow a small ripple.
This has only a secondorder effect on the currents calculated in the previous section; so
the previous results can be used without change.
As noted previously, the capacitor current must be entirely alternating to have peri
odic operation. The graph of the capacitor current must be as shown in Figure 5.17 for
a continuous inductor current. The peak value of this triangular waveform is located at
(I
max
−I
min
)/2. The resulting ripple in the capacitor voltage depends on the area under the
curve of capacitor current versus time. The charge added to the capacitor in a halfcycle is
given by the triangular area above the axis:
ΔQ =
1
2
I
max
−I
min
2
T
2
=
I
max
−I
min
8
T. (5.55)
The graph of capacitor voltage is also shown as part of Figure 5.17. The ripple in the
voltage is exaggerated to showits effect. Minimumand maximumcapacitor voltage values
occur at the time the capacitor current becomes zero. The peaktopeakvalue of the capacitor
voltage ripple is given by
Δv
2
= Δv
C
=
ΔQ
C
=
I
max
−I
min
8C
T =
(1 −k)V
2
8CL
T
2
=
nk(1 −k)V
1
8CL
T
2
. (5.56)
5.4.1.2 Forward Converter with Tertiary Winding
In order to exploit the magnetizing characteristics ability, a tertiary winding is applied in a
forward converter. The circuit diagram is shown in Figure 5.18.
The tertiary winding very much exploits the core magnetization ability and reduces the
transformer size largely.
Ordinary DC/DC Converters 161
T
1
D
2
V
2
V
1
D
1
D
3
+
1:1:n
–
+
–
L
C R
FIGURE 5.18 Forward converter with tertiary winding. (From Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 25. With permission.)
5.4.1.3 Switch Mode Power Supplies with Multiple Outputs
In many applications, more than one output is required, with each output likely to have dif
ferent voltage and current speciﬁcations. Aforward converter with three outputs is shown
in Figure 5.19. Each output voltage will be determined by the turn’s ratio n
1
, n
2
, or n
3
. The
three output voltages are
V
O1
= n
1
kV
1
,
V
O2
= n
2
kV
1
,
V
O3
= n
3
kV
1
.
(5.50a)
However, multiple outputs can be readily obtained using any of the converters that have
an isolating transformer, by employing a separate secondary winding for each output, as
shown in the forward converter in Figure 5.19.
5.4.2 FlyBack Converter
A ﬂyback converter is a transformertype converter using the demagnetizing effect. Its
circuit diagram is shown in Figure 5.20. The output voltage is calculated by
V
O
=
k
1 −k
nV
in
, (5.57)
where n is the transformer turn’s ratio and k is the conduction duty cycle, k = t
on
/T.
V
1
T
1
+
1:1:n
1
O/P 1
O/P 2
O/P 3
–
n
2
n
3
FIGURE 5.19 Forward converter with three outputs. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 25. With permission.)
162 Power Electronics
T
1
N
1
N
2
D
1
+
+
–
Control
1:n
–
C
V
O
R
FIGURE 5.20 Flyback converter. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 26. With permission.)
5.4.3 Push–Pull Converter
Apush–pull converter works in the push–pull state, which effectively avoids the iron core
saturation. Its circuit diagramis shown in Figure 5.21. Since there are two switches working
alternatively, the output voltage is doubled. The output voltage is calculated by
V
O
= 2nkV
in
, (5.58)
where n is the transformer turn’s ratio and k is the conduction duty cycle, k = t
on
/T.
5.4.4 HalfBridge Converter
Inorder to reduce the primaryside inone winding, a halfbridge converter was constructed.
Its circuit diagram is shown in Figure 5.22. The output voltage is calculated by
V
O
= nkV
in
, (5.59)
where n is the transformer turn’s ratio and k is the conduction duty cycle, k = t
on
/T.
+
–
+
–
+
–
1:n
D
1
D
2
V
O
T
1
V'
T
2
L
C R
FIGURE 5.21 Push–pull converter. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 25. With permission.)
Ordinary DC/DC Converters 163
T
1
T
2
C
1
C
2
D
1
V
O
D
2
C
3
L
R
V
in
+
+
–
–
1:n
FIGURE 5.22 Halfbridge converter. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 151. With permission.)
5.4.5 Bridge Converter
A bridge converter is shown in Figure 5.23. The transformer has a couple of identical
secondary windings. The primary circuit is a bridge inverter; hence it is called a bridge con
verter. Since the two pairs of the switches work symmetrically with 180
◦
phase angle shift,
the transformer iron core is not saturated, and the magnetizing characteristics have been
fully exploited. No tertiary winding is required. The secondary side contains an antipar
alleled diode fullwave rectiﬁer. It is likely that the two antiparalleled forward converters
work together.
To avoid short circuit, each pair of the switches can be switched on only in the phase
angle 0–180
◦
; usually it is set at 18–162
◦
. The corresponding conduction duty cycle k is in
the range of 0.05–0.45.
The circuit analysis is also similar to the forward converter. Some voltage and current
waveforms are shown in Figure 5.24. The repeating period is T/2 in bridge converter
operation, while it is T in forward converter operation.
The voltage transfer gain is
V
2
= 2nkV
1
. (5.60)
Analogously, the average current is
I
L
= I
2
=
V
2
R
=
I
max
+I
min
2
. (5.61)
T
1
T
3
T
4
D
1
D
2
L
T
2
V
1
V
2
C
1
C R
+
1:n
–
+
–
FIGURE 5.23 Bridge converter. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 27. With permission.)
164 Power Electronics
I
max
I
min
I
max
I
D
I
L
v
L
nV
1
– V
C
I
min
0 kT T/2 t
0
I
max
I
min
kT T/2 t
0
0
kT T/2 t
T/2 kT t
I
S
/n
–V
C
FIGURE 5.24 Some voltage and current waveforms.
The currents I
max
and I
min
are
I
max
= V
2
_
1
R
+
0.5 −k
2L
T
_
, (5.62)
I
min
= V
2
_
1
R
−
0.5 −k
2L
T
_
. (5.63)
The minimum inductor to retain CCM is
L
min
=
0.5 −k
2
TR. (5.64)
Ordinary DC/DC Converters 165
L
1
C
1
C
2
L
2
+
1:n
–
+
–
V
in
V
O
S
D
R
FIGURE 5.25 Zeta converter. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton:
Taylor & Francis Group LLC, p. 27. With permission.)
The peaktopeak value of the capacitor voltage ripple is
Δv
2
= Δv
C
=
ΔQ
C
=
I
max
−I
min
8C
T =
(0.5 −k)V
2
8CL
T
2
=
nk(0.5 −k)V
1
4CL
T
2
. (5.65)
5.4.6 Zeta Converter
Azeta converter is a transformertype converter with a lowpass ﬁlter. Its circuit diagram
is shown in Figure 5.25. Many people do not know its original circuit and call a P/O Luo
converter as a zeta converter. The output voltage ripple of the zeta converter is small. The
output voltage is calculated by
V
O
=
k
1 −k
nv
in
(5.66)
where n is the transformer turn’s ratio and k is the conduction duty cycle, k = t
on
/T.
5.5 Developed Converters
All the developed converters are derived from fundamental converters. Since there are
more components, the output voltage ripple is smaller. Five types of developed converters
are introduced in this section.
• P/O Luoconverter
• N/O Luoconverter
• Double output (D/O) Luoconverter
• Cúkconverter
• Singleended primary inductance converter (SEPIC).
5.5.1 P/O LuoConverter (Elementary Circuit)
AP/O Luoconverter (elementary circuit) is shown in Figure 5.26a. The capacitor C acts as
the primary means of storing and transferring energy from the input source to the output
166 Power Electronics
i
S
i
C
i
S
i
C
i
C
i
D
i
L1
i
L1
i
L1
i
L1
i
CO
i
L2
i
L2
i
L2
i
L2
i
D
i
0
–V
C
V
L1
V
S
V
in
V
in
V
D
V
D
V
D
V
L2
V
L2
S
C
D C
O
R
+
+
+
–
+
+ –
+ –
–
+
–
–
+
–
V
L1
+
–
+
–
+
–
+
–
L
1
L
1
L
1
L
2
L
2
L
2
L
2
V
O
V
O
V
O
V
O
V
O
V
O
V
O
(a)
(b)
(d)
(c)
FIGURE 5.26 P/O Luoconverter (elementary circuit): (a) circuit diagram, (b) switchon, (c) switch off, and (d)
discontinuous conduction mode. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 29. With permission.)
load via the pump inductor L
1
. Assuming the capacitor C to be sufﬁciently large, the varia
tion of the voltage across the capacitor C from its average value V
C
can be neglected in the
steady state, that is, v
C
(t) ≈ V
C
, even though it stores and transfers energy from the input
to the output.
When the switch S is on, the source current i
I
= i
L1
+i
L2
. The inductor L
1
absorbs energy
from the source. In the meantime, the inductor L
2
absorbs energy from the source and the
capacitor C, and both currents i
L1
and i
L2
increase. When the switch S is off, source current
i
I
= 0. Current i
L1
ﬂows through the freewheeling diode D to the charge capacitor C. The
inductor L
1
transfers its SE to the capacitor C. In the meantime, the inductor current i
L2
ﬂows through the (C
O
−R) circuit and freewheeling diode D to keep itself continuous.
Both currents i
L1
and i
L2
decrease. In order to analyze the progress in the circuit’s working,
the equivalent circuits inswitchingonandswitchingoff states are showninFigure 5.26b–d.
Actually, the variations of currents i
L1
and i
L2
are small so that i
L1
≈ I
L1
and i
L2
≈ I
L2
.
The charge on the capacitor C increases during switchoff:
Q+ = (1 −k)TI
L1
.
It decreases during switchon: Q− = kTI
L2
.
Ordinary DC/DC Converters 167
m
E
10
8
6
4
2
k
0
0 0.2 0.4 0.6 0.8 1
FIGURE 5.27 Voltage transfer gain M
E
versus k.
In the whole period of the investigation, Q+ = Q−. Thus,
I
L2
=
1 −k
k
I
L1
.
Since the capacitor C
O
performs as a lowpass ﬁlter, the output current
I
L2
= I
O
. (5.67)
Equations 5.66 and 5.67 are available for all P/O Luoconverters.
Thesourcecurrent i
I
= i
L1
+i
L2
duringtheswitchonperiod, andi
I
= 0duringtheswitch
off period. Thus, the average source current I
I
is
I
I
= k ×i
I
= k(i
L1
+i
L2
) = k
_
1 +
1 −k
k
_
I
L1
= I
L1
. (5.68)
Therefore, the output current is
I
O
=
1 −k
k
I
I
. (5.69)
Hence, the output voltage is
V
O
=
k
1 −k
V
I
. (5.70)
The voltage transfer gain in continuous mode is
M
E
=
V
O
V
I
=
k
1 −k
. (5.71)
The curve of M
E
versus k is shown in Figure 5.27.
168 Power Electronics
The current i
L1
increases and is supplied by V
I
during switchon. It decreases and is
inversely biased by −V
C
during switchoff. Therefore, kTV
I
= (1 −k)TV
C
. The average
voltage across the capacitor C is
V
C
=
k
1 −k
V
I
= V
O
. (5.72)
The current i
L1
increases and is supplied by V
I
during switchon. It decreases and is
inversely biased by −V
C
during switchoff. Therefore, its peaktopeak variation is
Δi
L1
=
kTV
I
L
1
.
Considering Equation 5.68, the variation ratio of the current i
L1
is
ξ
1
=
Δi
L1
/2
I
L1
=
kTV
I
2L
1
I
I
=
1 −k
2M
E
R
fL
1
. (5.73)
The current i
L2
increases andis suppliedbythe voltage (V
I
+V
C
−V
O
) = V
I
duringswitch
on. It decreases andis inverselybiasedby−V
O
duringswitchoff. Therefore its peaktopeak
variation is
Δi
L2
=
kTV
I
L
2
. (5.74)
Considering Equation 5.66, the variation ratio of the current i
L2
is
ξ
2
=
Δi
L2
/2
I
L2
=
kTV
I
2L
2
I
O
=
k
2M
E
R
fL
2
. (5.75)
When the switch is off, the freewheeling diode current i
D
= i
L1
+i
L2
and
Δi
D
= Δi
L1
+Δi
L2
=
kTV
I
L
1
+
kTV
I
L
2
=
kTV
I
L
=
(1 −k)TV
O
L
. (5.76)
Considering Equations 5.66 and 5.67, the average current in the switchoff period is
I
D
= I
L1
+I
L2
= I
O
/(1 −k).
The variation ratio of current i
D
is
ζ =
Δi
D
/2
I
D
=
(1 −k)
2
TV
O
2LI
O
=
k(1 −k)R
2M
E
fL
=
k
2
M
2
E
R
2fL
. (5.77)
The peaktopeak variation of v
C
is
Δv
C
=
Q+
C
=
1 −k
C
TI
I
.
Considering Equation 5.72, the variation ratio of v
C
is
ρ =
Δv
C
/2
V
C
=
(1 −k)TI
I
2CV
O
=
k
2
1
fCR
. (5.78)
Ordinary DC/DC Converters 169
In order to investigate the variation of output voltage v
O
, we have to calculate the charge
variation on the output capacitor C
O
, because Q = C
O
V
O
and ΔQ = C
O
Δv
O
. Here, ΔQ is
caused by Δi
L2
and corresponds to the area of the triangle with the height of half of Δi
L2
and
the width of half of the repeating period T/2. Considering Equation 5.74,
ΔQ =
1
2
Δi
L2
2
T
2
=
T
8
kTV
I
L
2
.
Thus, the half peaktopeak variation of output voltage v
O
and v
CO
is
Δv
O
2
=
ΔQ
2C
O
=
kT
2
V
I
16C
O
L
2
.
The variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
kT
2
16C
O
L
2
V
I
V
O
=
k
16M
E
1
f
2
C
O
L
2
. (5.79)
For analysis in DCM, referring to Figure 5.26d, we can see that the diode current i
D
becomes zero during switchoff before the next period switchon. The condition for DCM
is ζ ≥ 1, that is,
k
2
M
2
E
R
2fL
≥ 1, M
E
≤ k
_
R
2fL
= k
_
z
N
2
. (5.80)
The graph of the boundary curve versus the normalized load z
N
= R/fL is shown in
Figure 5.28. It can be seen that the boundary curve is a monorising function of the
parameter k.
Continuous mode
Discontinuous mode
20
10
5
2
1
0.5
0.2
0.1
R/fL
m
E
1 2 5 10 20 50 100 200 500 1000
K = 0.9
K = 0.7
K = 0.5
K = 0.3
K = 0.1
FIGURE 5.28 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/fL.
170 Power Electronics
i
D
i
max
O
kT T
t
1
t
FIGURE 5.29 The discontinuous current waveform. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC. With permission.)
In the DCMcase, the current i
D
exists in the periodbetween kT andt
1
= [k +(1 −k)m
E
]T,
where m
E
is the ﬁlling efﬁciency and is deﬁned as
m
E
=
1
ζ
=
M
2
E
k
2
(R/2fL)
. (5.81)
The diode current i
D
decreases to zero at t = t
1
= kT +(1 −k)m
E
T; therefore, 0 < m
E
< 1
(Figure 5.29).
For the current i
L
, we have
kTV
I
= (1 −k)m
E
TV
C
or
V
C
=
k
(1 −k)m
E
V
I
= k(1 −k)
R
2fL
V
I
with
_
R
2fL
≥
1
1 −k
.
For the current i
LO
, we have kT(V
I
+V
C
−V
O
) = (1 −k)m
E
TV
O
.
Therefore, the output voltage in discontinuous mode is
V
O
=
k
(1 −k)m
E
V
I
= k(1 −k)
R
2fL
V
I
with
_
R
2fL
≥
1
1 −k
. (5.82)
The output voltage increases linearly with an increase in the loadresistance R. The output
voltage versus the normalized load z
N
= R/fL is shown in Figure 5.28. It can be seen that
larger load resistance R may cause higher output voltage in DCM.
Example 5.3
A P/O Luoconverter has the following components: V
I
= 20V, L
1
= L
2
= 10mH, C = C
O
=
20μF, R = 20Ω, switching frequency f = 50kHz, and conduction duty cycle k = 0.6. Calculate
the output voltage, its variation ratio, and the variation ratio of the inductor currents i
L1
and i
L2
in steady state.
Ordinary DC/DC Converters 171
SOLUTION
1. From Equation 5.70, the output voltage is V
O
= kV
I
/(1 −k) = 0.6 ×20/0.4 = 30V.
2. From Equation 5.79, the variation ratio of v
O
is
ε =
k
16M
E
1
f
2
C
O
L
2
=
0.6
16 ×1.5
1
(50k)
2
×20μ ×10m
= 0.00005.
3. From Equation 5.73, the variation ratio of the current i
L1
is
ξ
1
=
1 −k
2M
E
R
fL
1
=
0.4
2 ×1.5
20
50k ×10m
= 0.0053.
4. From Equation 5.75, the variation ratio of the current i
L2
is
ξ
2
=
k
2M
E
R
fL
2
=
0.6
2 ×1.5
20
50k ×10m
= 0.008.
5.5.2 N/O LuoConverter (Elementary Circuit)
The N/O Luoconverter (elementary circuit) and its switchon and switchoff equivalent
circuits are shown in Figure 5.30. This circuit can be considered as a combination of an
electronic pump SLD(C) and a “Π”type lowpass ﬁlter CL
O
C
O
. The electronic pump
injects certain energy to the lowpass ﬁlter in each cycle. The capacitor C in Figure 5.30
acts as the primary means of storing and transferring energy from the input source to the
output load. Assuming the capacitor C to be sufﬁciently large, the variation of the voltage
across the capacitor C from its average value V
C
can be neglected in the steady state, that
is, V
C
(t) ≈ V
C
, even though it stores and transfers energy from the input to the output.
The voltage transfer gain in CCM is
M
E
=
V
O
V
I
=
I
I
I
O
=
k
1 −k
. (5.83)
The transfer gain is shown in Figure 5.27. The current i
L
increases and is supplied by V
I
during switchon. Thus, its peaktopeak variation is Δi
L
= kTV
I
/L. The inductor current
I
L
is
I
L
= I
C−off
+I
O
=
I
O
1 −k
. (5.84)
V
D
V
O
V
C V
L
L
O
i
LO
i
CO
–V
LO
+
+
+
–
–
+ i
D
i
L
i
C
D
L
C
R
–
–
+
–
+
V
S
V
in
i
0
i
S
C
O
FIGURE 5.30 N/O Luoconverter (elementary circuit). (Reprinted from Luo, F. L. and Ye, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 29. With permission.)
172 Power Electronics
Considering R = V
O
/I
O
, the variation ratio of the current i
L
is
ζ =
Δi
L
/2
I
L
=
k(1 −k)V
I
T
2LI
O
=
k(1 −k)R
2M
E
fL
=
k
2
M
2
E
R
2fL
. (5.85)
The peaktopeak variation of the voltage v
C
is
Δv
C
=
Q−
C
=
k
C
TI
O
. (5.86)
The variation ratio of the voltage v
C
is
ρ =
Δv
C
/2
V
C
=
kI
O
T
2CV
O
=
k
2
1
fCR
. (5.87)
The peaktopeak variation of current i
LO
is
Δi
LO
=
k
8f
2
CL
O
I
O
. (5.88)
Considering I
LO
= I
O
,
ξ =
Δi
LO
/2
I
LO
=
k
16
1
f
2
CL
O
. (5.89)
The variation of the voltage v
CO
is
Δv
CO
=
A
C
O
=
1
2
T
2
k
16f
2
CC
O
L
O
I
O
=
k
64f
3
CC
O
L
O
I
O
. (5.90)
The variation ratio of the output voltage v
CO
is
ε =
Δv
CO
/2
V
CO
=
k
128f
3
CC
O
L
O
I
O
V
O
=
k
128
1
f
3
CC
O
L
O
R
. (5.91)
In DCM, the diode current i
D
becomes zero during switchoff before the next periodswitch
on. The condition for DCM is ζ ≥ 1, that is,
k
2
M
2
E
R
2fL
≥ 1
or
M
E
≤ k
_
R
2fL
= k
_
z
N
2
. (5.92)
The graph of the boundary curve versus the normalized load z
N
= R/fL is shown in
Figure 5.28. It can be seen that the boundary curve is a monorising function of the
parameter k.
Ordinary DC/DC Converters 173
In the DCMcase, the current i
D
exists in the periodbetween kT andt
1
= [k +(1 −k)m
E
]T,
where m
E
is the ﬁlling efﬁciency and is deﬁned as
m
E
=
1
ζ
=
M
2
E
k
2
(R/2fL)
. (5.93)
Considering ζ > 1 for DCMoperation, therefore 0 < m
E
< 1. The diode current i
D
becomes
zero at t = t
1
= kT +(1 −k)m
E
T.
For the current i
L
, we have
TV
I
= (1 −k)m
E
TV
C
or
V
C
=
k
(1 −k)m
E
V
I
= k(1 −k)
R
2fL
V
I
with
_
R
2fL
≥
1
1 −k
.
For the current i
LO
, we have kT(V
I
+V
C
−V
O
) = (1 −k)m
E
TV
O
.
Therefore, the output voltage in discontinuous mode is
V
O
=
k
(1 −k)m
E
V
I
= k(1 −k)
R
2fL
V
I
with
_
R
2fL
≥
1
1 −k
. (5.94)
That is, the output voltage increases linearly withanincrease inthe loadresistance R. Larger
load resistance R may cause higher output voltage in DCM.
5.5.3 D/O LuoConverter (Elementary Circuit)
Combining P/OandN/Oelementary Luoconverters together, we obtain the D/Oelemen
tary Luoconverter that is shown in Figure 5.31. For all the analyses, refer to the previous
two sections on P/O and N/O output elementary Luoconverters. The voltage transfer
gains are calculated by
V
O
+
V
I
=
V
O
−
V
I
=
k
1 −k
. (5.95)
FIGURE 5.31 D/O elementary Luoconverter. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 30. With permission.)
174 Power Electronics
5.5.4 CúkConverter
The Cúkconverter is derived from the boost converter. Its circuit diagram is shown in
Figure 5.32. The Cúkconverter was published in 1977 as the boost–buck converter, and
was renamed by Cúk’s students afterwards in 1986–1990.
The inductor current i
L
increases with slope +V
1
/L during switchon and decreases with
slope −(V
C
−V
1
)/L during switchoff. Thus
V
I
L
kT =
V
C
−V
I
L
(1 −k)T,
V
C
=
1
1 −k
V
I
.
Since L
O
−C
O
is a lowpass ﬁlter, the output voltage is calculated by
V
O
= V
C
−V
I
=
k
1 −k
V
I
. (5.96)
The voltage transfer gain is
M =
V
O
V
I
=
k
1 −k
, (5.97)
and also
M =
I
I
I
O
=
k
1 −k
.
Since the inductor L is connected in series to the source voltage and the inductor L
O
is
connected in series to the output circuit R–C
O
, we have the relations
I
L
= I
I
and I
LO
= I
O
.
The variation of the current i
L
is
Δi
L
=
V
I
L
kT.
Therefore, the variation ratio of the current i
L
is
ξ =
Δi
L
/2
I
L
=
V
I
2I
I
L
kT =
k
2M
2
R
fL
. (5.98)
i
L
i
O
i
LO
V
C
+
+
–
+
–
L
S R
L
O
V
I
V
O
C
C
O
D
–
FIGURE 5.32 Cúkconverter. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton:
Taylor & Francis Group LLC, p. 30. With permission.)
Ordinary DC/DC Converters 175
The variation of the current i
LO
is
Δi
LO
=
V
O
L
O
(1 −k)T.
Therefore, the variation ratio of the current i
LO
is
ξ
O
=
Δi
LO
/2
I
LO
=
V
O
2I
O
L
O
(1 −k)T =
1 −k
2
R
fL
O
. (5.99)
The variation of the diode current i
D
is
Δi
D
= Δi
L
+Δi
LO
=
_
V
O
L
+
V
O
L
O
_
(1 −k)T.
We can deﬁne L
/
= L//L
O
.
Δi
D
= Δi
L
+Δi
LO
=
V
O
L
//
(1 −k)T
and
I
D
= I
L
+I
LO
= I
I
+I
O
= (M +1)I
O
=
1
1 −k
I
O
.
Therefore, the variation ratio of the diode current i
D
is
ζ =
Δi
D
/2
I
D
=
V
O
2I
O
L
//
(1 −k)
2
T =
(1 −k)
2
2
R
fL
//
. (5.100)
The variation of the voltage v
C
is
Δv
C
=
ΔQ
C
=
I
I
C
(1 −k)T.
Therefore, the variation ratio of the voltage v
C
is
ρ =
Δv
C
/2
V
C
=
I
I
2CV
C
(1 −k)T =
k(1 −k)M
2
1
fRC
. (5.101)
The variation of the voltage v
CO
is
Δv
CO
=
ΔQ
O
C
O
=
T
8C
O
Δi
LO
=
V
O
8f
2
C
O
L
O
(1 −k).
Therefore, the variation ratio of the voltage v
CO
is
ε =
Δv
CO
/2
V
O
=
1 −k
16f
2
C
O
L
O
. (5.102)
The boundary is determined by the condition
ζ = 1
176 Power Electronics
or
ζ =
(1 −k)
2
2
R
fL
//
=
1
2(1 +M)
2
Z
N
= 1 with Z
N
=
R
fL
//
.
Therefore, the boundary between CCM and DCM is
M =
_
Z
N
2
−1. (5.103)
If (M +1) >
√
Z
N
/2, the converter works in CCM; if (M +1) <
√
Z
N
/2, the converter
works in DCM.
Example 5.4
A Cúkconverter has the following components: V
1
= 20V, L = L
O
= 10mH, C = C
O
= 20μF,
R = 20Ω, switching frequency f = 50kHz, and conduction duty cycle k = 0.6. Calculate the
output voltage and its ripple in the steady state. Does this converter work in CCM or DCM?
SOLUTION
1. From Equation 5.59, the output voltage is
V
2
= V
C
=
k
1 −k
V
1
=
0.6
0.4
20 = 30V.
2. From Equation 5.102, the output voltage ripple is
ε =
1 −k
16f
2
C
O
L
O
=
0.4
16(50k)
2
×20μ ×10m
= 0.00005.
3. We have M +1 = 2.5, which is greater than
√
Z
N
/2 =
_
20/(2 ×5m×50k) = 0.2. Referring
to Equation 5.103, we know that this converter works in CCM.
5.5.5 SEPIC
The SEPIC is derived from the boost converter. Its circuit diagram is shown in Figure 5.33.
The SEPIC was created immediately after the Cúkconverter, and is also called the P/O
Cúkconverter.
The inductor current i
L1
increases with slope +V
C
/L
1
during switchingon and decreases
with slope −V
O
/L
1
during switchingoff.
Thus
V
C
L
1
kT =
V
O
L
1
(1 −k)T,
V
C
=
1 −k
k
V
O
.
(5.104)
The inductor current i
L
increases with slope +V
I
/L during switchingon and decreases
with slope −(V
C
+V
O
−V
I
)/L during switchingoff.
Ordinary DC/DC Converters 177
i
L
i
L1
i
O
V
C
+
+
–
+
–
L
S R
L
1
V
I
V
O
C
C
O
D
–
FIGURE 5.33 Singleended primary inductance converter (SEPIC). (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 30. With permission.)
Thus
V
I
L
kT =
V
C
+V
O
−V
I
L
(1 −k)T,
V
O
=
k
1 −k
V
I
,
(5.105)
that is,
M =
V
O
V
I
=
k
1 −k
.
Since the inductor Lis connectedinseries tothe source voltage, the inductor average current
I
L
is
I
L
= I
I
.
Since the inductor L
1
is connected in parallel to the capacitor C during switchingoff, the
inductor average current I
L1
is (I
CO−on
= I
O
and I
CO−off
= I
I
), I
L1
= I
O
.
The variation of the current i
L
is
Δi
L
=
V
I
L
kT.
Therefore, the variation ratio of the current i
L
is
ξ =
Δi
L
/2
I
L
=
V
I
2I
I
L
kT =
k
2M
2
R
fL
. (5.106)
The variation of the current i
L1
is
Δi
L1
=
V
C
L
1
kT.
Therefore, the variation ratio of the current i
L1
is
ξ
1
=
Δi
L1
/2
I
L1
=
V
C
2I
O
L
1
kT =
1 −k
2
R
fL
1
. (5.107)
178 Power Electronics
The variation of the diode current i
D
is
Δi
D
= Δi
L
+Δi
L1
=
_
V
O
L
+
V
O
L
1
_
(1 −k)T.
We can deﬁne L
//
= L//L
1
.
Hence
Δi
D
= Δi
L
+Δi
L1
=
V
O
L
//
(1 −k)T
and
I
D
= I
L
+I
LO
= I
I
+I
O
= (M +1)I
O
=
1
1 −k
I
O
.
Therefore, the variation ratio of the diode current i
D
is
ζ =
Δi
D
/2
I
D
=
V
O
2I
O
L
//
(1 −k)
2
T =
(1 −k)
2
2
R
fL
//
. (5.108)
The variation of the voltage v
C
is
Δv
C
=
ΔQ
C
=
I
I
C
(1 −k)T.
Therefore, the variation ratio of the voltage v
C
is
ρ =
Δv
C
/2
V
C
=
I
I
2CV
C
(1 −k)T =
kM
2
1
fRC
. (5.109)
The variation of the voltage v
CO
is
Δv
CO
=
ΔQ
O
C
O
=
kTI
O
C
O
=
kI
O
fC
O
.
Therefore, the variation ratio of the voltage v
CO
is
ε =
Δv
CO
/2
V
O
=
kI
O
2fC
O
V
O
=
k
2fRC
O
. (5.110)
The boundary is determined by the condition
ζ = 1
or
ζ =
(1 −k)
2
2
R
fL
//
=
1
2(1 +M)
2
Z
N
= 1 with Z
N
=
R
fL
//
.
Therefore, the boundary between CCM and DCM is
M =
_
Z
N
2
−1. (5.111)
O
r
d
i
n
a
r
y
D
C
/
D
C
C
o
n
v
e
r
t
e
r
s
1
7
9
TABLE 5.3
Circuit Diagrams of the TappedInductor Fundamental Converters
Standard Converter Switch Tap Diode to Tap Rail to Tap
Buck
S
L
V
in
V
O
C
D
S
V
in V
O
n
2
n
1
C D
S
V
in
V
O
n
1
C
D
n
2
S
V
in
n
2
CV
O
D
n
1
Boost
L
S
V
in C V
O
D
S
V
in
n
1
n
2
C V
O
D
S
V
in
n
1
n
2
C V
O
D
S
V
in
n
1
n
2
C V
O
D
Buck–boost
S
V
in
C V
O
D
L
S
V
in
n
1
n
2
C
V
O
D
S
V
in
n
1
n
2
C V
o
D
S
V
in
n
1
n
2
C
V
O
D
Source: Data from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters,. Boca Raton: Taylor & Francis Group LLC, p. 31.
180 Power Electronics
TABLE 5.4
Voltage Transfer Gains of the TappedInductor Fundamental Converters
Converter No Tap Switched to Tap Diode to Tap Rail to Tap
Buck k
k
n +k(1 −n)
nk
1 +k(n −1)
k −n
k(1 −n)
Boost
1
1 −k
n +k(1 −n)
n(1 −k)
1 +k(n −1)
1 −k
n −k
n(1 −k)
Buckboost
k
1 −k
k
n(1 −k)
nk
1 −k
k
1 −k
Source: Data from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters, Boca Raton:
Taylor & Francis Group LLC, p. 32.
5.6 TappedInductor Converters
These converters have been derived from fundamental converters, whose circuit diagrams
are shown in Table 5.3. The voltage transfer gains are presented in Table 5.4. Here the
tappedinductor ratio is n = n
1
/(n
1
+n
2
).
Homework
5.1. A boost converter has the following components: V
1
= 20 V, L = 10 mH, C =
20 μF, R = 20 Ω, switching frequency f = 50 kHz, and conduction duty cycle
k = 0.6. Calculate the output voltage and its ripple in the steady state. Does this
converter work in CCM or DCM?
5.2. A P/O buck–boost converter working in “buck–boost operation mode” has the
following components: V
1
= 20 V, L = 10 mH, C = 20 μF, R = 20 Ω, switching
frequency f = 20 kHz, and conduction duty cycle k = 0.6. Calculate the output
voltage and its ripple in the steady state. Does this converter work in CCM or
DCM?
5.3. A multiple charger is required to offer three output voltages at 6, 9, and 12 V
to charge mobile phones, digital cameras, and GPS. A forward converter with
multiple outputs in Figure 5.19 can be used for this purpose. It has the following
components: V
1
= 20 V, all L = 10 mH, all C = 20 μF, all R are about 20 Ω, switch
ing frequency f = 20 kHz, and conduction duty cycle k = 0.5. Calculate the turn’s
ratio for each secondary winding of the transformer. If the primary winding has
600 turns, what are the three secondary winding’s turns?
5.4. A Zeta converter in Figure 5.25 is used to provide high output voltage V
O
=
1500 V. It has the following components: V
in
= 50 V, L
1
= L
2
= 10 mH, C
1
= C
2
=
20 μF, R = 100 Ω, switching frequency f = 50 kHz, and conduction duty cycle
k = 0.8. If the primary winding has 200 turns, calculate the transformer turn’s
ratio and the particular turns of the secondary winding.
Ordinary DC/DC Converters 181
5.5. A negative output Luoconverter has the following components: V
I
= 20 V, L =
L
O
= 10 mH, C = C
O
= 20 μF, R = 3000 Ω, switching frequency f = 20 kHz, and
conduction duty cycle k = 0.6. Calculate the output voltage and its variation ratio
in the steady state.
References
1. Luo, F. L. and Ye, H. 2004. Advanced DC/DC Converters. Boca Raton: CRC Press.
2. Luo, F. L. andYe, H. 2006. Essential DC/DCConverters. Boca Raton: Taylor &Francis Group LLC.
3. Luo, F. L. 1999. Positive output Luoconverters: Voltage lift technique. IEEEPA Proceedings,
vol. 146, pp. 415–432.
4. Luo, F. L. 1999. Negative output Luoconverters: Voltage lift technique. IEEEPA Proceedings,
vol. 146, pp. 208–224.
5. Luo, F. L. 2000. Double output Luoconverters: Advanced voltage lift technique. IEEEPA
Proceedings, vol. 147, pp. 469–485.
6. Erickson, R. W. and Maksimovic, D. 1999. Fundamentals of Power Electronics. Norwell, MA:
Kluwer and Academic Publishers.
7. Middlebrook, R. D. and Cuk, S. 1981. Advances in SwitchedMode Power Conversion. Pasadena:
TESLAco.
8. Maksimovic, D. and Cuk, S. 1991. Switching converters with wide DC conversion range. IEEE
Transactions on Power Electronics, 151–159.
9. Smedley, K. M. and Cuk, S. 1995. Onecycle control of switching converters. IEEE Transactions
on Power Electronics, 10, 625–634.
10. Redl, R., Molnar, B., and Sokal, N. O. 1986. ClassE resonant DCDCpower converters: Analysis
of operations, and experimental results at 1.5 MHz. IEEE Transactions on Power Electronics, 1,
111–121.
11. Kazimierczuk, M. K. and Bui, X. T. 1989. ClassE DC–DC converters with an inductive
impedance inverter. IEEE Transactions on Power Electronics, 4, 124–133.
12. Liu, Y. and Sen, P. C. 1996. New ClassE DCDC converter topologies with constant switching
frequency. IEEE Transactions on Industry Applications, 32, 961–972.
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6
Voltage Lift Converters
The ordinary DC/DCconverter has limitedvoltage transfer gain. Considering the effects of
the component called parasitic elements, the conduction duty cycle k can only be 0.1 < k <
0.9. This restriction blocks ordinary DC/DC converter voltage transfer gain increase. The
VL technique is a common method used in electronics circuitry design to amplify output
voltage. Using this technique in DC/DC conversion technology, we can design, stage by
stage, VL power converters with high voltage transfer gains in arithmetic progression. It
opens the way to signiﬁcantly increase the voltage transfer gain of DC/DC converters.
Using this technique, the following series of VL converters are designed [1,2]:
• P/O Luoconverters
• N/O Luoconverters
• D/O Luoconverters
• VL Cúkconverters
• VL SEPIC
• Other VL D/O converters
• Switchedcapacitorized (SC) converters.
6.1 Introduction
The VL technique is applied to the periodical switching circuit. Usually, a capacitor is
charged, during switchon, by a certain voltage, for example, the source voltage. This
charged capacitor voltage can be arranged on topup to some parameter, for example,
output voltage during switchoff. Therefore, the output voltage can be lifted higher. Con
sequently, this circuit is called a selflift circuit. A typical example is the sawtooth wave
generator with a selflift circuit.
Repeating this operation, another capacitor can be charged by a certain voltage, which
is possibly the input voltage or other equivalent voltages. The second capacitorcharged
voltage can also be arranged on topup to some parameter, especially the output voltage.
Therefore, the output voltage can be higher than that of a selflift circuit. Usually, this circuit
is called a relift circuit.
Analogously, this operation can be repeated many times. Consequently, the series circuits
are called a triplelift circuit, a quadruplelift circuit, and so on.
Because of the effect of parasitic elements, the output voltage and power transfer efﬁ
ciency of DC–DC converters are limited. The VLtechnique offers a good way of improving
183
184 Power Electronics
circuit characteristics. After longtermresearch, this technique has beensuccessfullyapplied
to DC–DC converters. Three series of Luoconverters have now been developed from
prototypes using the VL technique. These converters perform DC–DC voltage increas
ing conversion with high power density, high efﬁciency, and cheap topology in a simple
structure. They are different from other DC–DC stepup converters and possess many
advantages, including the high output voltage with small ripples. Therefore, these con
verters will be widely used in computer peripheral equipment and industrial applications,
especially for highoutputvoltage projects. The contents of this chapter are arranged as
follows:
1. Seven types of selflift converters
2. P/O Luoconverters
3. N/O Luoconverters
4. Modiﬁed P/O Luoconverters
5. D/O Luoconverters.
Using the VL technique, we can easily obtain the other series of VL converters. For
example, VL Cúkconverters, VL SEPICs, other types of D/O converters, and switched
capacitorized converters.
6.2 Seven SelfLift Converters
All selflift converters introduced here are derived fromdeveloped converters such as Luo
converters, Cúkconverters, and SEPICs, which were described in Section 5.5. Since all
circuits are simple, usually only one more capacitor and diode are required; the output
voltage is higher than the input voltage [3–5]. The output voltage is calculated by
V
O
=
_
k
1 −k
+1
_
V
in
=
1
1 −k
V
in
. (6.1)
Seven circuits were developed:
• Selflift Cúkconverter
• Selflift P/O Luoconverter
• Reverse selflift P/O Luoconverter
• Selflift N/O Luoconverter
• Reverse selflift Luoconverter
• Selflift SEPIC
• Enhanced selflift P/O Luoconverter.
These converters perform DC–DC voltage increasing conversion in simple structures. In
these circuits, the switch S is a semiconductor device (MOSFET, BJT, IGBT, and so on). It is
driven by a PWM switching signal with variable frequency f and conduction duty cycle k.
For all circuits, the load is usually resistive, that is, R = V
O
/I
O
.
Voltage Lift Converters 185
The normalized impedance Z
N
is
Z
N
=
R
f L
eq
, (6.2)
where L
eq
is the equivalent inductance.
We concentrate on the absolute values rather than polarity in the description and calcu
lations given below. The directions of all voltages and currents are deﬁned and shown in
the corresponding ﬁgures. We also assume that the semiconductor switch and the passive
components are all ideal. All capacitors are assumed to be large enough that the ripple
voltage across the capacitors can be negligible in one switching cycle, for the average value
discussions.
For any component X (e.g., C, L, and so on), its instantaneous current and voltage are
expressed as i
X
and v
X
. Its average current and voltage values are expressed as I
x
and V
x
.
The output voltage and current are V
O
and I
O
; the input voltage and current are V
I
and I
I
.
T and f are the switching period and frequency.
The voltage transfer gain for the CCM is as follows:
M =
V
O
V
I
=
I
I
I
O
. (6.3)
Variation of current i
L
: ζ
1
=
Δi
L
/2
I
L
. (6.4)
Variation of current i
LO
: ζ
2
=
Δi
LO
/2
I
LO
. (6.5)
Variation of current i
D
: ξ =
Δi
D
/2
I
D
. (6.6)
Variaton of voltage v
C
: ρ =
Δv
C
/2
V
C
. (6.7)
Variation of voltage v
C1
: σ
1
=
Δv
C1
/2
v
C1
. (6.8)
Variation of voltage v
C2
: σ
2
=
Δv
C2
/2
v
C2
. (6.9)
Variation of output voltage v
O
: ε =
ΔV
O
/2
V
O
. (6.10)
Here, I
D
refers tothe average current i
D
that ﬂows throughthe diode Dduringthe switchoff
period, and not its average current over the whole period.
A detailed analysis of the seven selflift DC–DC converters is given in the following
sections. Due to the limit on the length of the book, only the simulation and experimental
results of the selflift Cúkconverter are given. However, the results and conclusions of
other selflift converters should be quite similar to those of the selflift Cúkconverter.
6.2.1 SelfLift CúkConverter
The selflift Cúkconverter and its equivalent circuits during the switchon and switchoff
periods are shown in Figure 6.1. It is derived fromthe Cúkconverter. During the switchon
186 Power Electronics
D
1
C
1
C
1
C
1
L
O
L
O
L
O
L
(a)
(b)
(c)
L
L
V
C1
V
C1
V
C1
V
I
V
I
V
I
V
C
V
C
V
C
D S
S
C
C
C
i
LO
i
LO
i
I
i
I
i
I
i
O
i
O
i
O
C
O
C
O
C
O
V
O
V
O
V
O
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
+
+
+
+
+
FIGURE 6.1 (a) Selflift Cúkconverter circuit and its equivalent circuits during (b) switchon, and (c) switchoff.
(Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC,
p. 45. With permission.)
period, S and D
1
are on and D is off. During the switchoff period, D is on and S and D
1
are off.
6.2.1.1 Continuous Conduction Mode
In steady state, the average of inductor voltages over a period is zero. Thus
V
C1
= V
CO
= V
O
. (6.11)
During the switchon period, the voltages across capacitors C and C
1
are equal. Since we
assume that C and C
1
are sufﬁciently large,
V
C
= V
C1
= V
O
. (6.12)
The inductor current i
L
increases during switchon and decreases during switchoff. The
corresponding voltages across L are V
I
and −(V
C
−V
I
).
Therefore, kTV
I
= (1 −k)T(V
C
−V
I
).
Hence,
V
O
= V
C
= V
C1
= V
CO
=
1
1 −k
V. (6.13)
Voltage Lift Converters 187
The voltage transfer gain in the CCM is
M =
V
O
V
I
=
I
I
I
O
=
1
1 −k
. (6.14)
The characteristics of M versus conduction duty cycle k are shown in Figure 6.2.
Since all the components are considered ideal, the power loss associated with all the
circuit elements is neglected. Therefore the output power P
O
is considered to be equal to
the input power P
IN
: V
O
I
O
= V
I
I
I
.
Thus,
I
L
= I
I
=
1
(1 −k)
I
O
.
During switchoff,
i
D
= i
L
, I
D
=
1
1 −k
I
O
. (6.15)
The capacitor C
O
acts as a lowpass ﬁlter, so that I
LO
= I
O
.
The current i
L
increases during switchon. The voltage across it during switchon is V
I
;
therefore its peaktopeak current variation is ΔI
L
= kTV
I
/L.
The variation ratio of current i
L
is
ζ
1
=
Δi
L
/2
I
L
=
kTV
I
2I
L
=
k(1 −k)
2
R
2f L
=
kR
2M
2
f L
. (6.16)
The variation of current i
D
is
ξ = ζ
1
=
kR
2M
2
f L
. (6.17)
12
10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1
k
M
FIGURE 6.2 Voltage transfer gain M versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 46. With permission.)
188 Power Electronics
The peaktopeak variation of voltage v
C
is
Δv
C
=
I
L
(1 −k)T
C
=
I
O
f C
. (6.18)
The variation ratio of voltage v
C
is
ρ =
Δv
C
/2
V
C
=
I
O
2f CV
O
=
1
2fRC
. (6.19)
The peaktopeak variation of voltage v
C1
is
Δv
C1
=
I
LO
(1 −k)T
C
1
=
I
O
(1 −k)
f C
1
. (6.20)
The variation ratio of voltage v
C1
is
σ
1
=
Δv
C1
/2
V
C1
=
I
O
(1 −k)
2f C
1
V
O
=
1
2MfRC
1
. (6.21)
The peaktopeak variation of current i
LO
is approximately
Δi
LO
=
(1/2)(Δv
C1
/2)(T/2)
L
O
=
I
O
(1 −k)
8f
2
L
O
C
1
. (6.22)
The variation ratio of current i
LO
is approximately
ζ
2
=
Δi
LO
/2
I
LO
=
I
O
(1 −k)
16f
2
L
O
C
1
I
O
=
1
16Mf
2
L
O
C
1
. (6.23)
The peaktopeak variation of voltages v
O
and v
CO
is
Δv
O
= Δv
CO
=
(1/2)(Δi
LO
/2)(T/2)
C
O
=
I
O
(1 −k)
64f
3
L
O
C
1
C
O
. (6.24)
The variation ratio of the output voltage is
ε =
Δv
O
/2
V
O
=
I
O
(1 −k)
128f
3
L
O
C
1
C
O
V
O
=
1
128Mf
3
L
O
C
1
C
O
R
. (6.25)
The voltage transfer gain of the selflift Cúkconverter is the same as the original boost
converter. However, the output current of the selflift Cúkconverter is continuous, with
small ripples.
The output voltage of the selflift Cúkconverter is higher than the corresponding Cúk
converter by an input voltage. It retains one of the merits of the Cúkconverter. They both
have continuous input and output currents in the CCM. As for component stress, it can
be seen that the selflift Cúkconverter has a smaller voltage and current stresses than the
original Cúkconverter.
Voltage Lift Converters 189
6.2.1.2 Discontinuous Conduction Mode
The selflift Cúkconverter operates in the DCM if the current i
D
decreases to zero during
switchoff. Aspecial case is seenwheni
D
decreases to zero at t = T, then, the circuit operates
at the boundary of CCM and DCM. The variation ratio of current i
D
is 1 when the circuit
works in the boundary state:
ξ =
k
2
R
M
2
f L
= 1. (6.26)
Therefore the boundary between CCM and DCM is
M
B
=
√
k
_
R
2f L
=
_
kz
N
2
, (6.27)
where z
N
is the normalized load R/(fL). The boundary between CCMand DCMis shown in
Figure 6.3a. The curve that describes the relationship between M
B
and z
N
has the minimum
value M
B
= 1.5 and k = 1/3 when the normalized load z
N
is 13.5.
WhenM > M
B
, the circuit operates inthe DCM. Inthis case, the diode current i
D
decreases
to zero at t = t
1
= [k +(1 −k)m]T, where kT < t
1
< T and 0 < m < 1.
Deﬁne m as the current ﬁlling factor. After mathematical manipulation,
m =
1
ξ
=
M
2
k(R/2f L)
. (6.28)
From the above equation, we can see that the DCM is caused by the following factors:
• Switching frequency f is too low
• Duty cycle k is too small
• Inductance L is too small
• Load resistor R is too big.
In the DCM, current i
L
increases during switchon and decreases in the period from kT
to (1 −k)mT. The corresponding voltages across L are V
I
and −(V
C
−V
I
). Therefore,
kTV
I
= (1 −k)mT(V
C
−V
I
).
Hence,
V
C
=
_
1 +
k
(1 −k)m
_
V
I
. (6.29)
Since we assume that C, C
1
, and C
O
are large enough,
V
O
= V
C
= V
CO
=
_
1 +
k
(1 −k)m
_
V
I
(6.30)
or
V
O
=
_
1 +k
2
(1 −k)
R
2f L
_
V
I
. (6.31)
190 Power Electronics
10
2
10
1
10
0
10
1
10
2
10
1
k=0.95
(a)
(b)
k=0.8
k=0.6
k=0.33
k=0.1
10
0
10
0
10
1
10
2
R/fL
M
10
3
10
2
10
3
R/fL
M
FIGURE 6.3 Output voltage characteristics of the selflift Cúkconverter: (a) boundary between CCM and DCM
and (b) Voltage transfer gain M versus the normalized load at various k. (Reprinted from Luo, F. L. and Ye, H.
2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 49. With permission.)
The voltage transfer gain in the DCM is
M
DCM
= 1 +k
2
(1 −k)
R
2f L
. (6.32)
The relationship between DCvoltage transfer gain M and the normalized load at various
k in the DCMis also shown in Figure 6.3b. It can be seen that in the DCM, the output voltage
increases as the load resistance R increases.
6.2.2 SelfLift P/O LuoConverter
Aselflift P/O Luoconverter and its equivalent circuits during the switchon and switch
off periods are shown in Figure 6.4. It is the selflift circuit of the P/O Luoconverter. It is
Voltage Lift Converters 191
derivedfromthe elementary circuit of the P/OLuoconverter. During the switchonperiod,
S and D
1
are switched on and D is switched off. During the switchoff period, D is on, and
S and D
1
are off.
6.2.2.1 Continuous Conduction Mode
In steady state, the average of inductor voltages over a period is zero. Thus
V
C
= V
CO
= V
O
.
During the switchon period, the voltage across capacitor C
1
is equal to the source voltage.
Since we assume that C and C
1
are sufﬁciently large, V
C1
= V
I
.
The inductor current i
L
increases in the switchon period and decreases in the switchoff
period. The corresponding voltages across L are V
I
and −(V
C
−V
C1
). Therefore, kTV
I
=
(1 −k)T(V
C
−V
C1
). Hence, V
O
= (1/(1 −k))V
I
.
C
1
L
L
O
C
i
LO
V
C
i
I
V
C1
V
I
i
L
+
–
i
O
C
O
V
O
+
+
+
–
–
–
R
(b)
C
1
L
L
O C
i
LO V
C
i
I
V
C1
V
I
i
L
+
–
i
O
C
O
V
O
+
+
+
–
–
–
R
(c)
C
1
L
L
O
D
1
D
C
S
i
LO
V
C
i
I
V
C1
V
I
i
L
+
–
i
O
C
O
V
O
+
(a)
+
+
–
–
–
R
FIGURE 6.4 (a) Selflift P/OLuoconverter circuit andits equivalent circuits during (b) switchon, and(c) switch
off. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group
LLC, p. 51. With permission.)
192 Power Electronics
The voltage transfer gain in the CCM is
M =
V
O
V
I
=
1
1 −k
. (6.33)
Since all the components are considered to be ideal, the power loss associated with all
the circuit elements is neglected. Therefore, the output power P
O
is considered to be equal
to the input power P
IN
: V
O
I
O
= V
I
I
I
. Thus, I
I
= (1/1 −k)I
O
.
The capacitor C
O
acts as a lowpass ﬁlter so that I
LO
= I
O
.
The charge of capacitor C increases during switchon and decreases during
switchoff:
Q
+
= I
C−on
kT = I
O
kT, Q
−
= I
C−off
(1 −k)T = I
L
(1 −k)T.
In a switching period, Q
+
= Q
−
, I
L
= (k/(1 −k))I
O
.
During the switchoff period, i
D
= i
L
+i
LO
.
Therefore, I
D
= I
L
+I
LO
= (1/(1 −k))I
O
.
For the current and voltage variations and boundary condition, we can obtain the
following equations using a similar method to that used in the analysis of the selflift
Cúkconverter.
Current variations: ζ
1
=
1
2M
2
R
f L
, ζ
2
=
k
2M
R
f L
O
, ξ =
k
2M
2
R
f L
eq
,
where L
eq
refers to L
eq
= LL
O
/(L +L
O
).
Voltage variations: ρ =
k
2
1
f CR
, σ
1
=
M
2
1
f C
1
R
, ε =
k
8M
1
f
2
L
O
C
O
.
6.2.2.2 Discontinuous Conduction Mode
The selflift P/O Luoconverter operates in the DCM if the current i
D
decreases to zero
during switchoff. In the critical case when i
D
decreases to zero at t = T, the circuit operates
at the boundary of CCM and DCM.
The variation ratio of current i
D
is 1 when the circuit works in the boundary state:
ξ =
k
2M
2
R
f L
eq
= 1.
Therefore, the boundary between CCM and DCM is
M
B
=
√
k
_
R
2f L
eq
=
_
kz
N
2
, (6.34)
where z
N
is the normalized load R/(fL
eq
), and L
eq
refers to L
eq
= LL
O
/(L +L
O
).
WhenM > M
B
, the circuit operates inthe DCM. Inthis case, the diode current i
D
decreases
to zero at t = t
1
= [k +(1 −k)m]T, where KT < t
1
< T and0 < m < 1. Here, mis the current
ﬁlling factor. We deﬁne m as
m =
1
ξ
=
M
2
k(R/2f L
eq
)
. (6.35)
Voltage Lift Converters 193
In the DCM, the current i
L
increases in the switchon period kT and decreases in the
period fromkT to (1 −k)mT. The corresponding voltages across L are V
I
and −(V
C
−V
C1
).
Therefore, kTV
I
= (1 −k)mT(V
C
−V
C1
) and V
C
= V
CO
= V
O
V
C1
= V
I
. Hence,
V
O
=
_
1 +
k
(1 −k)m
_
V
I
or V
O
=
_
1 +k
2
(1 −k)
R
2f L
eq
_
V
I
. (6.36)
So the real DC voltage transfer gain in the DCM is
M
DCM
= 1 +k
2
(1 −k)
R
2f L
eq
. (6.37)
In DCM, the output voltage increases as the load resistance R increases.
Example 6.1
A P/Oselflift Luoconverter has the following components: V
I
= 20V, L = L
O
= 1mH, C = C
1
=
C
O
= 20μF, R = 40Ω, f = 50kHz, and k = 0.5. Calculate the output voltage, and the variation
ratios ζ
1
, ζ
2
, ξ, ρ, σ
1
, and ε in steady state.
SOLUTION
1. From Equation 6.33, the output voltage is V
O
= V
I
/(1 −k) = 20/0.5 = 40V, that is, M = 2.
2. From the formulae we can obtain the following ratios:
ζ
1
=
1
2M
2
R
f L
=
1
2 ×2
2
40
50k ×1m
= 0.1,
ζ
2
=
k
2M
R
f L
O
=
1
2 ×2
2
40
50k ×1m
= 0.1,
ξ =
k
2M
2
R
f L
eq
=
1
2 ×2
2
40
50k ×0.5m
= 0.2,
ρ =
k
2
1
f CR
=
0.5
2
1
50k ×20μ ×40
= 0.00625,
σ
1
=
M
2
1
f C
1
R
=
2
2
1
50k ×20μ ×40
= 0.025,
ε =
k
8M
1
f
2
L
O
C
O
=
0.5
8 ×2
1
(50k)
2
×20μ ×1m
= 0.000625.
From the calculations, the variations of i
L1
, i
L2
, v
C
, and v
C1
are small. The output voltage v
O
(also v
C1
) is almost a real DC voltage with very small ripples. Because of the resistive load, the
output current i
O
(i
O
= v
O
/R) is almost a real DC waveform with very small ripples as well.
6.2.3 Reverse SelfLift P/O LuoConverter
The reverse selflift P/O Luoconverter and its equivalent circuits during the switchon
and switchoff periods are shown in Figure 6.5. It is derived from the elementary circuit of
P/OLuoconverters. During the switchon period, S and D
1
are on and Dis off. During the
switchoff period, D is on, and S and D
1
are off.
194 Power Electronics
6.2.3.1 Continuous Conduction Mode
In steady state, the average of inductor voltages over a period is zero. Thus V
C1
=
V
CO
= V
O
.
During the switchon period, the voltage across capacitor C is equal to the source voltage
plus the voltage across C
1
. Since we assume that C and C
1
are sufﬁciently large, V
C1
=
V
I
+V
C
.
Therefore,
V
C1
= V
I
+
k
1 −k
V
I
=
1
1 −k
V
I
, V
O
= V
CO
= V
C1
=
1
1 −k
V
I
. (6.38)
V
C1
V
C
V
C1
C
1
V
I
i
I
i
L
i
L
V
I
i
LO
i
LO
i
O
i
O
V
O
L
O
L
O
R C
O
C
O
C
O
S
–
–
V
I
–
–
+
V
C
–
+
+
+
C
1
L
O
+
+ –
(a)
i
I
V
C1
i
LO
i
O
+ –
i
I
(b)
(c)
+
+
–
V
O
R
+
–
V
O
R
+
–
–
L
L
D
D
1
C
1
C
C
i
L
V
C
–
+
L
C
FIGURE 6.5 (a) Reverse selflift P/O Luoconverter circuit and its equivalent circuits during (b) switchon, and
(c) switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor &Francis
Group LLC, p. 55. With permission.)
Voltage Lift Converters 195
The voltage transfer gain in the CCM is
M =
V
O
V
I
=
1
1 −k
. (6.39)
Since all the components are considered to be ideal, the power losses on all the circuit
elements are neglected. Therefore, the output power P
O
is considered to be equal to the
input power P
IN
:
V
O
I
O
= V
I
I
I
.
Thus, I
I
= (1/(1 −k))I
O
.
The capacitor C
O
acts as a lowpass ﬁlter, so that I
LO
= I
O
.
The charge of capacitor C
1
increases during switchon and decreases during switchoff:
Q
+
= I
C1−on
kT,
Q
−
= I
LO
(1 −k)T = I
O
(1 −k)T.
In a switching period,
Q
+
= Q
−
,
I
C1−on
= ((1 −k)/k)I
O
,
I
C−on
= I
LO
+I
C1−on
= I
O
+
1 −k
k
I
O
=
1
k
I
O
. (6.40)
The charge on the capacitor C increases during switchoff and decreases during
switchon.
Q
+
= I
C−off
(1 −k)T, Q
−
= I
C−on
kT =
1
k
I
O
kT.
In a switching period,
Q
+
= Q
−
, I
C−off
=
1 −k
k
I
C−on
=
1
1 −k
I
O
. (6.41)
Therefore,
I
L
= I
LO
+I
C−off
= I
O
+
1
1 −k
I
O
=
2 −k
1 −k
I
O
= I
O
+I
I
.
During switchoff, i
D
= i
L
−i
LO
.
Therefore, I
D
= I
L
−I
LO
= I
O
.
The following equations are used for current and voltage variations and boundary
condition:
Current variations: ζ
1
=
k
(2 −k)M
2
R
f L
, ζ
2
=
k
2M
R
f L
O
, ξ =
1
2M
2
R
f L
eq
,
where L
eq
refers to L
eq
= (LL
O
/L +L
O
).
Voltage variations: ρ =
1
2k
1
f CR
, σ
1
=
1
2M
1
f C
1
R
, ε =
k
16M
1
f
2
C
O
L
O
.
196 Power Electronics
6.2.3.2 Discontinuous Conduction Mode
The reverse selflift P/O Luoconverter operates in the DCM; if the current i
D
decreases
to zero during switchoff at t = T, then the circuit operates at the boundary of CCM and
DCM. The variation ratio of current i
D
is 1 when the circuit works in the boundary state:
ξ =
k
2M
2
R
f L
eq
= 1.
Therefore, the boundary between CCM and DCM is
M
B
=
√
k
_
R
2f L
eq
=
_
kz
N
2
, (6.42)
where z
N
is the normalized load R/(fL
eq
), and L
eq
refers to L
eq
= LL
O
/(L +L
O
).
WhenM > M
B
, the circuit operates inthe DCM. Inthis case, the diode current i
D
decreases
to zero at t = t
1
= [k +(1 −k)m]T, where kT< t
1
< T and 0 < m < 1. Here, mis the current
ﬁlling factor and is deﬁned as
m =
1
ξ
=
M
2
k(R/2f L
eq
)
. (6.43)
In the DCM, current i
L
increases during switchon and decreases in the period from kT
to (1 −k)mT. The corresponding voltages across L are V
I
and −V
C
.
Therefore, kTV
I
= (1 −k)mTV
C
and V
C1
= V
CO
= V
O
, V
C1
= V
I
+V
C
.
Hence,
V
O
=
_
1 +
k
(1 −k)m
_
V
I
or V
O
=
_
1 +k
2
(1 −k)
R
2f L
eq
_
V
I
. (6.44)
So the real DC voltage transfer gain in the DCM is
M
DCM
= 1 +k
2
(1 −k)
R
2f L
. (6.45)
In DCM, the output voltage increases as the load resistance R increases.
6.2.4 SelfLift N/O LuoConverter
The selflift N/OLuoconverter andits equivalent circuits duringthe switchonandswitch
off periods are shown in Figure 6.6. It is the selflift circuit of the N/O Luoconverter. The
function of capacitor C
1
is to lift the voltage V
C
to a level higher than the source voltage
V
I
. S and D
1
are on and D is off during the switchon period. D is on and S and D
1
are off
during the switchoff period.
6.2.4.1 Continuous Conduction Mode
Insteadystate, the average of inductor voltages over a periodis zero. Thus V
C
= V
CO
= V
O
.
During the switchon period, the voltage across capacitor C
1
is equal to the source voltage.
Since we assume that C and C
1
are sufﬁciently large, V
C1
= V
I
.
Voltage Lift Converters 197
The inductor current i
L
increases in the switchon period and decreases in the switchoff
period. The corresponding voltages across L are V
I
and −(V
C
−V
C1
).
Therefore, kTV
I
= (1 −k)T(V
C
−V
C1
).
Hence,
V
O
= V
C
= V
CO
=
1
1 −k
V
I
. (6.46)
The voltage transfer gain in the CCM is
M =
V
O
V
I
=
1
1 −k
. (6.47)
Since all the components are considered to be ideal, the power loss associated with all
the circuit elements is neglected. Therefore, the output power P
O
is considered to be equal
to the input power P
IN
: V
O
I
O
= V
I
I
I
. Thus, I
I
= (1/(1 −k))I
O
. The capacitor C
O
acts as a
lowpass ﬁlter so that I
LO
= I
O
.
For the current and voltage variations and boundary condition, the following equa
tions can be obtained using a similar method to that used in the analysis of the selflift
i
I
V
I
V
C1
i
L
i
LO
C
I
V
C
V
O
i
O
R L
L
O C
1
S
–
+
+
+
–
–
–
+
(a)
D
C
i
L
V
O
C
O
i
LO i
O
L
L
O
C
1
V
C1
+ –
R
–
+
i
I
V
I
–
+
(b)
V
C
+
–
C
V
O
i
L
L
C
1
V
C1
+ –
C
O
i
LO i
O
L
O
R
–
+
i
I
V
I
–
+
(b)
V
C
+
–
C
FIGURE 6.6 (a) Selflift N/O Luoconverter circuit and its equivalent circuits during (b) switchon, and
(c) switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor &
Francis Group LLC, p. 59. With permission.)
198 Power Electronics
Cúkconverter:
Current variations: ζ
1
=
k
2M
2
R
f L
, ζ
2
=
k
16
1
f
2
L
O
C
, ξ = ζ
1
=
k
2M
2
R
f L
.
Voltage variations: ρ =
k
2
1
f CR
, σ
1
=
M
2
1
f C
1
R
, ε =
k
128
1
f
3
L
O
CC
O
R
.
6.2.4.2 Discontinuous Conduction Mode
The selflift N/O Luoconverter operates in the DCM; if the current i
D
decreases to zero at
t = T, then the circuit operates at the boundary of CCM and DCM. The variation ratio of
current i
D
is 1 when the circuit works at the boundary state:
ξ =
k
2M
2
R
f L
= 1.
Therefore, the boundary between CCM and DCM is
M
B
=
√
k
_
R
2f L
eq
=
_
kz
N
2
, (6.48)
where L
eq
refers to L
eq
= L and z
N
is the normalized load R/( fL).
WhenM > M
B
, the circuit operates inthe DCM. Inthis case, the diode current i
D
decreases
to zero at t = t
1
= [k +(1 −k)m]T, where KT < t
1
< T and0 < m < 1. Here, mis the current
ﬁlling factor and is deﬁned as
m =
1
ξ
=
M
2
k(R/2f L)
. (6.49)
In the DCM, current i
L
increases during switchon and decreases during the period from
kT to (1 −k)mT. The voltages across L are V
I
and −(V
C
−V
C1
).
Therefore,
kTV
I
= (1 −k)mT(V
C
−V
C1
)
and V
C1
= V
I
, V
C
= V
CO
= V
O
. Hence,
V
O
=
_
1 +
k
(1 −k)m
_
V
I
or V
O
=
_
1 +k
2
(1 −k)
R
2f L
_
V
I
.
So the real DC voltage transfer gain in the DCM is
M
DCM
= 1 +k
2
(1 −k)
R
2f L
. (6.50)
We can see that in DCM, the output voltage increases as the load resistance R increases.
6.2.5 Reverse SelfLift N/O LuoConverter
The reverse selflift N/O Luoconverter and its equivalent circuits during the switchon
and switchoff periods are shown in Figure 6.7. During the switchon period, S and D
1
are
on and D is off. During the switchoff period, D is on and S and D
1
are off.
Voltage Lift Converters 199
V
C
i
I
V
I
i
LO
i
L
V
C1
i
O
V
O
L
L
O
D
1
R
C
C
1
D
C
O
S
–
–
+
+
(a)
+
+
–
–
i
I
V
C1
i
LO
i
L
i
O
L
C
L
O
C
1 C
O
–
+
V
I
–
+
(b)
V
O
R
+
–
V
C
+ –
i
I
i
LO
i
O
L
O
C
O
V
I
V
C1
–
+
–
+
(c)
V
O
R
+
–
i
L
L
C
1
C
1
V
C
+ –
S
FIGURE 6.7 (a) Reverse selflift N/O Luoconverter circuit and its equivalent circuits during (b) switchon, and
(c) switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor &Francis
Group LLC, p. 62. With permission.)
6.2.5.1 Continuous Conduction Mode
In steady state, the average of inductor voltages over a period is zero. Thus
V
C1
= V
CO
= V
O
.
The inductor current i
L
increases in the switchon period and decreases in the switchoff
period. The corresponding voltages across L are V
I
and −V
C
.
Therefore, kTV
I
= (1 −k)TV
C
.
Hence,
V
C
=
k
1 −k
V
I
(6.51)
is the voltage across C. Since we assume that C and C
1
are sufﬁciently large, V
C1
= V
I
+V
C
.
Therefore,
V
C1
= V
I
+
k
1 −k
V
I
=
1
1 −k
V
I
, V
O
= V
CO
= V
C1
=
1
1 −k
V
I
.
200 Power Electronics
The voltage transfer gain in the CCM is
M =
V
O
V
I
=
1
1 −k
. (6.52)
Since all the components are considered ideal, the power loss associated with all the
circuit elements is neglected. Therefore, the output power P
O
is considered to be equal
to the input power P
IN
: V
O
I
O
= V
I
I
I
. Thus, I
I
= (1/(1 −k))I
O
. The capacitor C
O
acts as a
lowpass ﬁlter so that I
LO
= I
O
.
The charge of capacitor C
1
increases during switchon and decreases during
switchoff:
Q
+
= I
C1−on
kT, Q
−
= I
C1−off
(1 −k)T = I
O
(1 −k)T.
In a switching period,
Q
+
= Q
−
, I
C1−on
=
1 −k
k
I
C−off
=
1 −k
k
I
O
.
The charge of capacitor C increases during switchon and decreases during
switchoff:
Q
+
= I
C−on
kT, Q
−
= I
C−off
(1 −k)T.
In a switching period, Q
+
= Q
−
.
I
C−on
= I
C1−on
+I
LO
=
1 −k
k
I
O
+I
O
=
1
k
I
O
,
I
C−off
=
k
1 −k
I
C−on
=
k
1 −k
1
k
I
O
=
1
1 −k
I
O
.
Therefore,
I
L
= I
C−off
=
1
1 −k
I
O
.
During the switchoff period,
i
D
= i
L
, I
D
= I
L
=
1
1 −k
I
O
.
For the current and voltage variations and the boundary condition, we can obtain the
following equations using a similar method to that used in the analysis of the selflift
Cúkconverter.
Current variations: ζ
1
=
k
2M
2
R
f L
, ζ
2
=
1
16M
R
f
2
L
O
C
1
, ξ =
k
2M
2
R
f L
.
Voltage variations: ρ =
1
2k
1
f CR
, σ
1
=
1
2M
1
f C
1
R
, ε =
1
128M
1
f
3
L
O
C
1
C
O
R
.
Voltage Lift Converters 201
6.2.5.2 Discontinuous Conduction Mode
The reverse selflift N/O Luoconverter operates in the DCM if the current i
D
decreases to
zero during switchoff. In the special case when i
D
decreases to zero at t = T, the circuit
operates at the boundary of CCM and DCM.
The variation ratio of current i
D
is 1 when the circuit works in the boundary state:
ξ =
k
2M
2
R
f L
eq
= 1.
The boundary between CCM and DCM is
M
B
=
√
k
_
R
2f L
eq
=
_
kz
N
2
,
where z
N
is the normalized load R/(fL
eq
) and L
eq
refers to L
eq
= L.
When M > M
B
, the circuit operates at the DCM. In this case, diode current i
D
decreases to
zero at t = t
1
= [k +(1 −k)m]T, where KT < t
1
< T and0 < m < 1 with mbeing the current
ﬁlling factor:
m =
1
ξ
=
M
2
k(R/2f L
eq
)
. (6.53)
In the DCM, current i
L
increases in the switchon period kT and decreases in the period
from kT to (1 −k)mT. The corresponding voltages across L are V
I
and −V
C
.
Therefore,
kTV
I
= (1 −k)mTV
C
and V
C1
= V
CO
= V
O
, V
C1
= V
I
+V
C
. Hence,
V
O
=
_
1 +
k
(1 −k)m
_
V
I
or V
O
=
_
1 +k
2
(1 −k)
R
2f L
_
V
I
. (6.54)
The voltage transfer gain in the DCM is
M
DCM
= 1 +k
2
(1 −k)
R
2f L
. (6.55)
It can be seen that in DCM, the output voltage increases as the load resistance R increases.
6.2.6 SelfLift SEPIC
The selflift SEPIC and its equivalent circuits during the switchon and switchoff periods
are shown in Figure 6.8. It is derived from the SEPIC (with output ﬁlter). S and D
1
are on
and D is off during the switchon period, whereas D is on and S and D
1
are off during the
switchoff period.
202 Power Electronics
V
C
V
C1
i
I
V
I
i
LO
i
L1
V
C2
i
O
V
O
L
1
L
O
D
1
D
R
L
C
C
2 C
O
S
–
–
+
+
(a)
+
+
–
+ – –
i
L1
V
C
V
C1
i
I
i
LO
i
O
L
1
L L
O
C
C
2 S
V
C2
–
+
(b)
–
+
V
I
V
O
R C
O
+
–
+ + – –
V
C
V
C1
i
I
i
LO
i
O
(c)
L
V
I
–
+
L
O
C
2
V
C2
–
+
V
O
R C
O
+
–
C
i
L1
L
1 S
+ + – –
FIGURE 6.8 (a) Selflift SEPIC converter and its equivalent circuits during (b) switchon, and (c) switchoff.
(Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC,
p. 67. With permission.)
6.2.6.1 Continuous Conduction Mode
Inthe steadystate, the average voltage across inductor Lover a periodis zero. Thus V
C
= V
I
.
During the switchon period, the voltage across capacitor C
1
is equal to the voltage
across C. Since we assume that C and C
1
are sufﬁciently large, V
C1
= V
C
= V
I
.
In the steady state, the average voltage across inductor L
O
over a period is also zero.
Thus V
C2
= V
CO
= V
O
.
The inductor current i
L
increases in the switchon period and decreases in the switchoff
period. The corresponding voltages across L are V
I
and −(V
C
−V
C1
+V
C2
−V
I
).
Therefore
kTV
I
= (1 −k)T(V
C
−V
C1
+V
C2
−V
I
)
or
kTV
I
= (1 −k)T(V
O
−V
I
).
Hence,
V
O
=
1
1 −k
V
I
= V
CO
= V
C2
. (6.56)
The voltage transfer gain in the CCM is
M =
V
O
V
I
=
1
1 −k
. (6.57)
Voltage Lift Converters 203
Since all the components are considered to be ideal, the power loss associated with all
the circuit elements is neglected. Therefore, the output power P
O
is considered to be equal
to the input power P
IN
: V
O
I
O
= V
I
I
I
. Thus,
I
I
=
1
1 −k
I
O
= I
L
.
The capacitor C
O
acts as a lowpass ﬁlter so that I
LO
= I
O
.
The charge of capacitor C increases during switchoff and decreases during switchon:
Q
−
= I
C−on
kT, Q
+
= I
C−off
(1 −k)T = I
I
(1 −k)T.
In a switching period,
Q
+
= Q
−
, I
C−on
=
1 −k
k
I
C−off
=
1 −k
k
I
I
.
The charge of capacitor C
2
increases during switchoff and decreases during switchon:
Q
−
= I
C2−on
kT = I
O
kT, Q
+
= I
C2−off
(1 −k)T.
In a switching period,
Q
+
= Q
−
, I
C2−off
=
k
1 −k
I
C−N
=
k
1 −k
I
O
.
The charge of capacitor C
1
increases during switchon and decreases during switchoff:
Q
+
= I
C1−on
kT, Q
−
= I
C1−off
(1 −k)T.
In a switching period,
Q
+
= Q
−
, I
C1−off
= I
C2−off
+I
LO
=
k
1 −k
I
O
+I
O
=
1
1 −k
I
O
.
Therefore,
I
C1−on
=
1 −k
k
I
C1−off
=
1
k
I
O
, I
L1
= I
C1−on
−I
C−on
= 0.
During switchoff, i
D
= i
L
−i
L1
.
Therefore,
I
D
= I
I
=
1
1 −k
I
O
.
For the current and voltage variations and the boundary condition, we can obtain the
following equations using a similar method to that used in the analysis of the selflift
Cúkconverter:
Current variations: ζ
1
=
k
2M
2
R
f L
, ζ
2
=
k
16
R
f
2
L
O
C
2
, ξ =
k
2M
2
R
f L
eq
,
where L
eq
refers to L
eq
= LL
O
/(L +L
O
).
Voltage variations: ρ =
M
2
1
f CR
σ
1
=
M
2
1
f C
1
R
, σ
2
=
k
2
1
f C
2
R
, ε =
k
128
1
f
3
L
O
C
2
C
O
R
.
204 Power Electronics
6.2.6.2 Discontinuous Conduction Mode
The selflift SEPIC converter operates in the DCMif the current i
D
decreases to zero during
switchoff. As a special case, when i
D
decreases to zero at t = T, the circuit operates at the
boundary of CCM and DCM.
The variation ratio of current i
D
is 1 when the circuit works in the boundary state:
ξ =
k
2M
2
R
f L
eq
= 1.
Therefore, the boundary between CCM and DCM is
M
B
=
√
k
_
R
2f L
eq
=
_
kz
N
2
, (6.58)
where z
N
is the normalized load R/( fL
eq
) and L
eq
refers to L
eq
= LL
O
/(L +L
O
).
WhenM > M
B
, the circuit operates inthe DCM. Inthis case, the diode current i
D
decreases
to zero at t = t
1
= [k +(1 −k)m]T, where KT < t
1
< T and 0 < m < 1. Here, mis deﬁned as
m =
1
ξ
=
M
2
k(R/2f L
eq
)
. (6.59)
In the DCM, current i
L
increases during switchon and decreases in the period from kT
to (1 −k)mT. The corresponding voltages across L are V
I
and −(V
C
−V
C1
+V
C2
−V
I
).
Thus,
kTV
I
= (1 −k)T(V
C
−V
C1
+V
C2
−V
I
)
and V
C
= V
I
, V
C1
= V
C
= V
I
, V
C2
= V
CO
= V
O
.
Hence,
V
O
=
_
1 +
k
(1 −k)m
_
V
I
or V
O
=
_
1 +k
2
(1 −k)
R
2f L
eq
_
V
I
.
So the real DC voltage transfer gain in the DCM is
M
DCM
= 1 +k
2
(1 −k)
R
2f L
eq
. (6.60)
In DCM, the output voltage increases as the load resistance R increases.
6.2.7 Enhanced SelfLift P/O LuoConverter
Enhanced selflift P/OLuoconverter circuit and the equivalent circuits during the switch
on and switchoff periods are shown in Figure 6.9. It is derived from the selflift P/O
Luoconverter in Figure 6.4 with swapping of the positions of switch S and inductor L.
During the switchon period, S and D
1
are on and D is off. We obtain
V
C
= V
C1
and Δi
L
=
V
I
L
kT.
Voltage Lift Converters 205
V
C1
i
I
D
1
C
1
V
I
L
O
i
LO i
O
V
O
C
O
V
C
D
L
S
C
R
+
–
+
+
+
–
–
–
FIGURE 6.9 Enhanced selflift P/O Luoconverter. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 71. With permission.)
During the switchoff period, D is on and S and D
1
are off:
Δi
L
=
V
C
−V
I
L
(1 −k)T,
so that
V
C
=
1
1 −k
V
I
.
The output voltage and current and the voltage transfer gain are
V
O
= V
I
+V
C1
=
_
1 +
1
1 −k
_
V
I
, (6.61)
I
O
=
1 −k
2 −k
I
I
, (6.62)
M = 1 +
1
1 −k
=
2 −k
1 −k
. (6.63)
Average voltages are
V
C
=
1
1 −k
V
I
, (6.64)
V
C1
=
1
1 −k
V
I
. (6.65)
Average currents are
I
LO
= I
O
, (6.66)
I
L
=
2 −k
1 −k
I
O
= I
I
. (6.67)
Therefore,
V
O
V
I
=
1
1 −k
+1 =
2 −k
1 −k
. (6.68)
206 Power Electronics
6.3 P/O LuoConverters
P/O Luoconverters perform the voltage conversion from positive to positive voltages
using the VL technique. They work in the ﬁrst quadrant with large voltage ampliﬁcation.
Five circuits have been introduced in the literature [6–11]:
• Elementary circuit
• Selflift circuit
• Relift circuit
• Triplelift circuit
• Quadruplelift circuit
The elementary circuit is discussed in Section 5.5.1 and the selflift circuit is discussed in
Section 6.2.2.
6.3.1 ReLift Circuit
The relift circuit and its equivalent switchon and switchoff circuits are shown in
Figure 6.10, which is derived from the selflift circuit. Capacitors C
1
and C
2
perform char
acteristics to lift the capacitor voltage V
C
to a level 2 times higher than the source voltage
V
I
. L
3
performs the function of a ladder joint to link the two capacitors C
1
and C
2
and lift
the capacitor voltage V
C
up.
When switches S and S
1
are turned on, the source’s instantaneous current i
I
= i
L1
+
i
L2
+i
C1
+i
L3
+i
C2
. Inductors L
1
and L
3
absorb energy from the source. In the meantime,
inductor L
2
absorbs energy from the source and capacitor C. Three currents i
L1
, i
L3
, and
i
L2
increase. When switches S and S
1
turn off, the source current i
I
= 0. Current i
L1
ﬂows
through capacitor C
1
, inductor L
3
, capacitor C
2
, anddiode Dto charge capacitor C. Inductor
L
1
transfers its SE to capacitor C. In the meantime, current i
L2
ﬂows through the (C
O
−R)
circuit, capacitor C
1
, inductor L
3
, capacitor C
2
, and diode D to keep itself continuous. Both
currents i
L1
and i
L2
decrease. In order to analyze the progress of the working of the cir
cuit, the equivalent circuits in switchon and switchoff states are shown in Figure 6.10b–d.
Assume that capacitors C
1
andC
2
are sufﬁciently large, andthe voltages V
C1
andV
C2
across
them are equal to V
I
in steady state.
Voltage v
L3
is equal to V
I
during switchon. The peaktopeak variation of current i
L3
is
Δi
L3
=
V
I
kT
L
3
. (6.69)
This variation is equal to the current reduction during switchoff. Suppose that its voltage
is −V
L3−off
, then
Δi
L3
=
V
L3−off
(1 −k)T
L
3
.
Thus, during switchoff, the voltagedrop across inductor L
3
is
V
L3−off
=
k
1 −k
V
I
. (6.70)
Voltage Lift Converters 207
i
L1
i
L3
i
L2
i
in
V
in
V
O V
L2
V
L1
V
in
L
1
C
1
C
2
L
2
L
3
V
D
V
O
V
in
(b) +
+
+
–
–
C
–
i
L1
i
L1
i
L3
i
L3
V
in
V
in
V
in
C
2
C
1
C
1
C
2
L
1
L
1
(c) (d)
C
i
L2
V
O
V
L2
L
2
C
L
2
L
3
V
in
V
D
L
3
V
O
i
L2
V
O
+ + –
V
L2
+ –
–
V
O
+ –
i
in
i
C1
i
D
i
L2
i
C
i
D1
i
L1
V
S
V
S1
V
C
V
L2
D
1
D
2
D
L
1
L
3
L
2
i
L2
i
CO
C
2
C
O
V
I
C
C1
V
O
S
(a)
S
1
R
+
+ + –
+
–
–
–
+
–
FIGURE 6.10 P/O relift circuit (a) circuit diagram, (b) switchon (c) switchoff, and (d) discontinuous mode.
(Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC,
p. 97. With permission.)
Current i
L1
increases in the switchon period kT, and decreases in the switchoff period
(1 −k)T. The corresponding voltages applied across L
1
are V
I
and −(V
C
−2V
I
−V
L3−off
).
Therefore,
kTV
I
= (1 −k)T(V
C
−2V
I
−V
L3−off
).
Hence,
V
C
=
2
1 −k
V
I
. (6.71)
Current i
L2
increases in the switchon period kT, and it decreases in the switchoff period
(1 −k)T. The corresponding voltages applied across L
2
are (V
I
+V
C
−V
O
) and −(V
O
−
2V
I
−V
L3−off
). Therefore,
kT(V
C
+V
I
−V
O
) = (1 −k)T(V
O
−2V
I
−V
L3−off
).
Hence,
V
O
=
2
1 −k
V
I
(6.72)
208 Power Electronics
20
16
12
8
4
0
0 0.2 0.4 0.6
k
M
R
0.8 1
FIGURE 6.11 Voltage transfer gain M
R
versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 99. With permission.)
and the output current is
I
O
=
1 −k
2
I
I
. (6.73)
The voltage transfer gain in the continuous mode is
M
R
=
V
O
V
I
=
2
1 −k
. (6.74)
The curve of M
R
versus k is shown in Figure 6.11.
Other average currents are
I
L1
=
k
1 −k
I
O
=
k
2
I
I
(6.75)
and
I
L3
= I
L1
+I
L2
=
1
1 −k
I
O
. (6.76)
Currents i
C1
and i
C2
are equal to (i
L1
+i
L2
) during the switchoff period (1 −k)T, and the
charges on capacitors C
1
and C
2
decrease, that is,
i
C1
= i
C2
= (i
L1
+i
L2
) =
1
1 −k
I
O
.
The charges increase during the switchon period kT, so their average currents are
I
C1
= I
C2
=
1 −k
k
(I
L1
+I
L2
) =
1 −k
k
_
k
1 −k
+1
_
I
O
=
I
O
k
. (6.77)
Voltage Lift Converters 209
During switchoff, the source current i
I
is 0, and in the switchon period kT, it is
i
I
= i
L1
+i
L2
+i
C1
+i
L3
+i
C2
.
Hence,
I
I
= ki
I
= k(I
L1
+I
L2
+I
C1
+I
L3
+I
C2
) = k[2(I
L1
+I
L2
) +2I
C1
]
= 2k(I
L1
+I
L2
)
_
1 +
1 −k
k
_
= 2k
I
L2
1 −k
1
k
=
2
1 −k
I
O
. (6.78)
6.3.1.1 Variations of Currents and Voltages
Current i
L1
increases and is supplied by V
I
during the switchon period kT. It decreases and
is inversely biased by −(V
C
−2V
I
−V
L3
) during the switchoff period (1 −k)T. Therefore,
its peaktopeak variation is
Δi
L1
=
kTV
I
L
1
.
The variation ratio of current i
L1
is
ξ
1
=
Δi
L1
/2
I
L1
=
kV
I
T
kL
1
I
I
=
1 −k
2M
R
R
f L
1
. (6.79)
Current i
L2
increases and is supplied by the voltage (V
I
+V
C
−V
O
) = V
I
during the
switchon period kT. It decreases and is inversely biased by −(V
O
−2V
I
−V
L3
) during
switchoff. Therefore, its peaktopeak variation is
Δi
L
2
=
kTV
I
L
2
.
The variation ratio of current i
L2
is
ξ
2
=
Δi
L2
/2
I
L2
=
kTV
I
2L
2
I
O
=
k
2M
R
R
f L
2
. (6.80)
When the switch is off, the freewheeling diode current i
D
= i
L1
+i
L2
and
Δi
D
= Δi
L3
= Δi
L1
+Δi
L2
=
kTV
I
L
=
k(1 −k)V
O
2L
T. (6.81)
Since I
D
= I
L1
+I
L2
= I
O
/1 −k, the variation ratio of current i
D
is
ζ =
Δi
D
/2
I
D
=
k(1 −k)
2
TV
O
4LI
O
=
k(1 −k)R
2M
R
f L
=
k
M
2
R
R
f L
. (6.82)
The variation ratio of current i
L3
is
χ
1
=
Δi
L3
/2
I
L3
=
kV
I
T
2L
3
(1/1 −k)I
O
=
k
M
2
R
R
f L
3
. (6.83)
210 Power Electronics
The peaktopeak variation of v
C
is
Δv
C
=
Q+
C
=
1 −k
C
TI
L1
=
k(1 −k)
2C
TI
I
.
Considering Equation 6.71, the variation ratio is
ρ =
Δv
C
/2
V
C
=
k(1 −k)TI
I
4CV
O
=
k
2f CR
. (6.84)
The charges oncapacitors C
1
andC
2
increase duringthe switchonperiodkT, anddecrease
during the switchoff period (1 −k)T because of the current (I
L1
+I
L2
). Therefore, their
peaktopeak variations are
Δv
C1
=
(1 −k)T(I
L1
+I
L2
)
C
1
=
(1 −k)I
I
2C
1
f
,
Δv
C2
=
(1 −k)T(I
L1
+I
L2
)
C
2
=
(1 −k)I
I
2C
2
f
.
Considering V
C1
= V
C2
= V
I
, the variation ratios of voltages v
C1
and v
C2
are
σ
1
=
Δv
C1
/2
V
C1
=
(1 −k)I
I
4f C
1
V
I
=
M
R
2f C
1
R
, (6.85)
σ
2
=
Δv
C2
/2
V
C2
=
(1 −k)I
I
4V
I
C
2
f
=
M
R
2f C
2
R
. (6.86)
Analogously, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
kT
2
16C
O
L
2
V
I
V
O
=
k
16M
R
1
f
2
C
O
L
2
. (6.87)
Example 6.2
A P/O relift Luoconverter has the following components: V
I
= 20V, L
1
= L
2
= 1mH, L
3
=
0.5mH, and all capacitors have 20μF, R = 160Ω, f = 50kHz, and k = 0.5. Calculate the output
voltage and the variation ratios ξ
1
, ξ
2
, ζ, χ
1
, ρ, σ
1
, σ
2
, and ε in steady state.
SOLUTION
From Equation 6.72, we obtain the output voltage as
V
O
=
2
1 −k
V
I
=
2
1 −0.5
20 = 80V.
The variation ratios are ξ
1
= 0.2, ξ
2
= 0.2, ζ = 0.1, χ
1
= 0.1, ρ = 0.0016 σ
1
= 0.0125, σ
2
=
0.0125, and ε = 1.56 ×10
−4
. Therefore, the variations are small.
From the example, we know the variations are small. Therefore, the output voltage v
O
is almost
a real DC voltage with very small ripples. Because of the resistive load, the output current i
O
(t )
is almost a real DC waveform with very small ripples as well, and I
O
= V
O
/R.
Voltage Lift Converters 211
60
k=0.95
k=0.9
k=0.8
k=0.5
k=0.33
k=0.1
40
20
10
M
R
6
4
3
2
27 32 50 125
R/fL
444
Discontinuous mode
Continuous mode
1684
FIGURE 6.12 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/f L. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton:
Taylor & Francis Group LLC, p. 106. With permission.)
For DCM, referring to Figure 6.10d, we can see that the diode current i
D
becomes zero during
switchoff before the next period switchon. The condition for the DCM is ζ ≥ 1, that is,
k
M
2
R
R
f L
≥ 1,
or
M
R
≤
√
k
_
R
f L
=
√
k
√
z
N
. (6.88)
The graph of the boundary curve versus the normalized load z
N
= R/fL is shown in Figure 6.12.
It can be seen that the boundary curve has a minimum value of 3.0 at k =1/3.
In this case, the current i
D
exists in the period between kT and t
1
= [k +(1 −k)m
R
]T, where
m
R
is the ﬁlling efﬁciency and is deﬁned as
m
R
=
1
ζ
=
M
2
R
k(R/f L)
. (6.89)
Therefore, 0 < m
R
< 1. Since the diode current i
D
becomes zero at t = t
1
= kT +(1 −k)m
R
T,
for the current i
L
kTV
I
= (1 −k)m
R
T(V
C
−2V
I
−V
L3−off
)
or
V
C
=
_
2 +
k
1 −k
+
k
(1 −k)m
R
_
V
I
=
_
2 +
k
1 −k
+k
2
(1 −k)
R
4f L
_
V
I
with
√
k
_
R
f L
≥
2
1 −k
,
212 Power Electronics
and for the current i
LO
kT(V
I
+V
C
−V
O
) = (1 −k)m
R
T(V
O
−2V
I
−V
L3−off
).
Therefore, the output voltage in the discontinuous mode is
V
O
=
_
2 +
k
1 −k
+
k
(1 −k)m
R
_
V
I
=
_
2 +
k
1 −k
+k
2
(1 −k)
R
4f L
_
V
I
with
√
k
_
R
f L
≥
2
1 −k
. (6.90)
That is, the output voltage linearly increases as the load resistance R increases. The output voltage
versus the normalized load z
N
= R/fL is shown in Figure 6.12. Larger load resistance R may cause
higher output voltage in the discontinuous mode.
6.3.2 TripleLift Circuit
The triplelift circuit, shown in Figure 6.13, consists of two static switches S and S
1
, four
inductors L
1
, L
2
, L
3
, andL
4
, ﬁve capacitors C, C
1
, C
2
, C
3
, andC
O
, andﬁve diodes. Capacitors
C
1
, C
2
, and C
3
perform characteristics to lift the capacitor voltage V
C
to a level 3 times
higher than the source voltage V
I
. L
3
and L
4
performthe function of ladder joints to link the
capacitors C
1
, C
2
, and C
3
and lift the capacitor voltage V
C
up. Currents i
C1
(t), i
C2
(t), and
i
C3
(t) are exponential functions. They have large values at the moment of switching power
on, but they are small because v
C1
= v
C2
= v
C3
= V
I
in steady state.
The output voltage and current are
V
O
=
3
1 −k
V
I
(6.91)
D
1
V
S
i
L1
V
in
L
1
i
C1 C
1
i
L3
L
3
i
C2
C
2
D
3
+
–
V
S1 S
1
C
3
C
O
V
O
R
+
–
i
C3
L
4
i
L4
D
2
D
4
L
2
i
L2
V
L2
V
C
i
C
D
C
S
– +
+
+
–
–
FIGURE 6.13 Triplelift circuit. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 110. With permission.)
Voltage Lift Converters 213
30
24
18
M
T
12
6
0
0 0.2 0.4 0.6
k
0.8 1
FIGURE 6.14 Voltage transfer gain M
T
versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 111. With permission.)
and
I
O
=
1 −k
3
I
I
. (6.92)
The voltage transfer gain in the continuous mode is
M
T
=
V
O
V
I
=
3
1 −k
. (6.93)
The curve of M
T
versus k is shown in Figure 6.14.
Other average voltages: V
C
= V
O
, V
C1
= V
C2
= V
C3
= V
I
.
Other average currents: I
L2
= I
O
, I
L1
=
k
1 −k
I
O
, I
L3
= I
L4
= I
L1
+I
L2
=
1
1 −k
I
O
.
Current variations: ξ
1
=
1 −k
2M
T
R
f L
1
, ξ
2
=
k
2M
T
R
f L
2
, ζ =
k(1 −k)R
2M
T
f L
=
k
M
2
T
3R
2f L
,
χ
1
=
k
M
2
T
3R
2f L
3
, χ
2
=
k
M
2
T
3R
2f L
4
.
Voltage variations: ρ =
k
2f CR
, σ
1
=
M
T
2f C
1
R
, σ
2
=
M
T
2f C
2
R
, σ
3
=
M
T
2f C
3
R
.
The variation ratio of output voltage v
C
is
ε =
k
16M
T
1
f
2
C
O
L
2
. (6.94)
The output voltage ripple is very small.
214 Power Electronics
40
30
Continuous mode
Discontinuous mode
15
6
4.5
3
40 48
k=0.1
k=0.33
k=0.5
k=0.8
k=0.9
75 188 667
R/fL
M
T
FIGURE 6.15 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/f L. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton:
Taylor & Francis Group LLC, p. 113. With permission.)
The boundary between CCM and DCM is
M
T
≤
√
k
_
3R
2f L
=
_
3kz
N
2
. (6.95)
This boundary curve is shown in Figure 6.15. It can be seen that the boundary curve has a
minimum value of M
T
that is equal to 4.5, corresponding to k = 1/3.
In the discontinuous mode, the current i
D
exists in the period between kT and t
1
= [k +
(1 −k)m
T
]T, where m
T
is the ﬁlling efﬁciency, that is,
m
T
=
1
ζ
=
M
2
T
k(3R/2f L)
. (6.96)
The diode current i
D
becomes zero at t = t
1
= kT +(1 −k)m
T
T; therefore, 0 < m
T
< 1.
For the current i
L1
,
kTV
I
= (1 −k)m
T
T(V
C
−3V
I
−V
L3−off
−V
L4−off
)
or
V
C
=
_
3 +
2k
1 −k
+
k
(1 −k)m
T
_
V
I
=
_
3 +
2k
1 −k
+k
2
(1 −k)
R
6f L
_
V
I
with
√
k
_
3R
2f L
≥
3
1 −k
,
and for the current i
L2
, kT(V
I
+V
C
−V
O
) = (1 −k)m
T
T(V
O
−2V
I
−V
L3−off
−V
L4−off
).
Voltage Lift Converters 215
Therefore, the output voltage in the discontinuous mode is
V
O
=
_
3 +
2k
1 −k
+
k
(1 −k)m
T
_
V
I
=
_
3 +
2k
1 −k
+k
2
(1 −k)
R
6f L
_
V
I
with
√
k
_
3R
2f L
≥
3
1 −k
. (6.97)
That is, the output voltage linearly increases as the load resistance R increases, as shown in
Figure 6.15.
6.3.3 QuadrupleLift Circuit
The quadruplelift circuit, shown in Figure 6.16, consists of two static switches S and S
1
,
ﬁve inductors L
1
, L
2
, L
3
, L
4
, and L
5
, six capacitors C, C
1
, C
2
, C
3
, C
4
, and C
O
, and seven
diodes. Capacitors C
1
, C
2
, C
3
, and C
4
performcharacteristics to lift the capacitor voltage V
C
to a level 4 times higher than the source voltage V
I
. L
3
, L
4
, and L
5
perform the function of
ladder joints to link the capacitors C
1
, C
2
, C
3
, and C
4
, and lift the output capacitor voltage
V
C
up. Current i
C1
(t), i
C2
(t), i
C3
(t), and i
C4
(t) are exponential functions. They have large
values at the moment of power on, but they are small because v
C1
= v
C2
= v
C3
= v
C4
= V
I
in steady state.
The output voltage and current are
V
O
=
4
1 −k
V
I
(6.98)
and
I
O
=
1 −k
4
I
I
. (6.99)
+
+
+
–
–
–
V
S
V
C
i
C
D
4
L
4
i
L4
D
3
C
2
i
C3
i
C2
L
3
i
L3
C
1
i
C1
L
1
D
1
i
L1
V
L1
V
in
D
2
D
6
V
L2
L
2
i
L2
C
O
C
4
L
5
i
C4
V
S1
S
1
D
5
C
3
i
L5
R
V
O
+
+
–
–
C
D
S
FIGURE 6.16 Quadruplelift circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 114. With permission.)
216 Power Electronics
The voltage transfer gain in the continuous mode is
M
Q
=
V
O
V
I
=
4
1 −k
. (6.100)
The curve of M
Q
versus k is shown in Figure 6.17.
Other average voltages: V
C
= V
O
, V
C1
= V
C2
= V
C3
= V
C4
= V
I
.
Other average currents: I
L2
= I
O
, I
L1
=
k
1 −k
I
O
,
I
L3
= I
L4
= L
L5
= I
L1
+I
L2
=
1
1 −k
I
O
.
Inductor current variations: ξ
1
=
1 −k
2M
Q
R
f L
1
, ξ
2
=
k
2M
Q
R
f L
2
,
ζ =
k(1 −k)R
2M
Q
f L
=
k
M
2
Q
2R
f L
χ
1
=
k
M
2
Q
2R
f L
3
,
χ
2
=
k
M
2
Q
2R
f L
4
, χ
3
=
k
M
2
Q
2R
f L
5
.
Capacitor voltage variations: ρ =
k
2f CR
σ
1
=
M
Q
2f C
1
R
σ
2
=
M
Q
2f C
2
R
σ
3
=
M
Q
2f C
3
R
σ
4
=
M
Q
2f C
4
R
.
40
32
24
16
8
0
0 0.2 0.4 0.6
k
M
Q
0.8 1
FIGURE 6.17 Voltage transfer gain M
Q
versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 115. With permission.)
Voltage Lift Converters 217
The variation ratio of output voltage V
C
is
ε =
k
16M
Q
1
f
2
C
O
L
2
. (6.101)
The output voltage ripple is very small.
The boundary between continuous and discontinuous modes is
M
Q
≤
√
k
_
2R
f L
=
_
2kz
N
. (6.102)
This boundary curve is shown in Figure 6.18. It can be seen that it has a minimum value of
M
Q
that is equal to 6.0, corresponding to k = 1/3.
In the discontinuous mode, the current i
D
exists in the period between kT and t
1
= [k +
(1 −k)m
Q
]T, where m
Q
is the ﬁlling efﬁciency, that is,
m
Q
=
1
ζ
=
M
2
Q
k(2R/f L)
. (6.103)
The current i
D
becomes zero at t = t
1
= kT +(1 −k)m
Q
T; therefore, 0 < m
Q
< 1. For the
current i
L1
, we have
kTV
I
= (1 −k)m
Q
T(V
C
−4V
I
−V
L3−off
−V
L4−off
−V
L5−off
),
60
k=0.9
0.8
0.5
0.33
0.1
40
50
30
20
10
M
Q
8
6
4
54 64 100 250
R/fL
889
Discontinuous mode
Continuous mode
FIGURE 6.18 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/f L. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton:
Taylor & Francis Group LCC, p. 116. With permission.)
218 Power Electronics
or
V
C
=
_
4 +
3k
1 −k
+
k
(1 −k)m
Q
_
V
I
=
_
4 +
3k
1 −k
+k
2
(1 −k)
R
8f L
_
V
I
with
√
k
_
2R
f L
≥
4
1 −k
,
and for current i
L2
, we have
kT(V
I
+V
C
−V
O
) = (1 −k)m
Q
T(V
O
−2V
I
−V
L3−off
−V
L4−off
−V
L5−off
).
Therefore, the output voltage in the discontinuous mode is
V
O
=
_
4 +
3k
1 −k
+
k
(1 −k)m
Q
_
V
I
=
_
4 +
3k
1 −k
+k
2
(1 −k)
R
8f L
_
V
I
with
√
k
_
2R
f L
≥
4
1 −k
. (6.104)
That is, the output voltage increases linearly as the load resistance R increases, as shown in
Figure 6.18.
6.3.4 Summary
Fromthe analysis and calculation in previous sections, the common formulae for all circuits
can be obtained:
M =
V
O
V
I
=
I
I
I
O
, L =
L
1
L
2
L
1
+L
2
, z
N
=
R
f L
, R =
V
O
I
O
.
Inductor current variations: ξ
1
=
1 −k
2M
R
f L
1
, ξ
2
=
k
2M
R
f L
2
, χ
i
=
k
M
2
n
2
R
f L
i+2
,
where i is the component number (i = 1, 2, 3, . . . , n −1), and n the stage number.
Capacitor voltage variations: ρ =
k
2f CR
; ε =
k
16M
1
f
2
C
O
L
2
;
σ
i
=
M
2f C
i
R
, i = 1, 2, 3, 4, . . . , n.
In order to write common formulae for the boundaries between continuous and dis
continuous modes and output voltage for all circuits, the circuits can be numbered. The
deﬁnition is that subscript n = 0 denotes the elementary circuit, 1 denotes the selflift cir
cuit, 2 denotes the relift circuit, 3 denotes the triplelift circuit, 4 denotes the quadruplelift
circuit, and so on. The voltage transfer gain is
M
n
=
n +kh(n)
1 −k
, n = 0, 1, 2, 3, 4, . . . . (6.105)
Voltage Lift Converters 219
120
100
80
50
30
10
0 0.2
(i)
(ii)
(iv)
(iii)
(v)
0.4 0.6
Conduction duty (k)
O
u
t
p
u
t
v
o
l
t
a
g
e
,
V
O
,
V
0.8 1
FIGURE 6.19 Output voltages of all P/O Luoconverters (V
I
= 10 V). (i) Quadruplelift circuit; (ii) triplelift
circuit; (iii) relift circuit; (iv) selflift circuit; and (v) elementary circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 120. With permission.)
Assumingthat f = 50 kHz, L
1
= L
2
= 1 mH, L
2
= L
3
= L
4
= L
5
= 0.5 mH, C = C
1
= C
2
=
C
3
= C
4
= C
O
= 20 μF, and the source voltage V
I
= 10 V, the values of the output voltage
V
O
with various conduction duty cycles k in the continuous mode are shown in Figure 6.19.
The variation of freewheeling diode current i
D
is given by
ζ
n
=
k
[1+h(n)]
M
2
n
n +h(n)
2
z
N
. (6.106)
The boundaries are determined by the condition:
ζ
n
≥ 1
or
k
[1+h(n)]
M
2
n
n +h(n)
2
z
N
≥ 1, n = 0, 1, 2, 3, 4, . . . . (6.107)
Therefore, the boundaries between continuous and discontinuous modes for all circuits are
M
n
= k
(1+h(n))/2
_
n +h(n)
2
z
N
, n = 0, 1, 2, 3, 4, . . . . (6.108)
The ﬁlling efﬁciency is
m
n
=
1
ζ
n
=
M
2
n
k
[1+h(n)]
2
n +h(n)
1
z
N
. (6.109)
220 Power Electronics
Continuous mode
Discontinuous mode
Normalised load (z
N
= R/fL)
44.5
0.5
1.5
3
V
o
l
t
a
g
e
t
r
a
n
s
f
e
r
g
a
i
n
(
M
)
4.5
6
13.5
M
E
M
S
M
R
M
T
M
Q
27 54 40.5
FIGURE 6.20 Boundaries between CCMand DCMof P/OLuoconverters. (Reprinted fromLuo, F. L. and Ye, H.
2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 121. With permission.)
The output voltage in the DCM for all circuits is
V
O−n
=
_
n +
n +h(n) −1
1 −k
+k
[2−h(n)]
1 −k
2[n +h(n)]
z
N
_
V
I
, n = 0, 1, 2, 3, 4, . . . , (6.110)
where
h(n) =
_
0 if n ≥ 1
1 if n = 0
is the Hong function. (6.111)
The boundaries between continuous anddiscontinuous modes of all circuits are shown in
Figure 6.20. The curves of all M versus z
N
suggest that the continuous mode area increases
from M
E
via M
S
, M
R
, M
T
to M
Q
. The boundary of an elementary circuit is a monorising
curve, but other curves are not monorising. There are minimum values of the boundaries
of other circuits which for M
S
, M
R
, M
T
, and M
Q
correspond at k = 1/3.
6.4 N/O LuoConverters
N/O Luoconverters perform the voltage conversion from positive to negative voltages
using the VLtechnique. They work in the secondquadrant with large voltage ampliﬁcation.
Five circuits have been introduced in the literature [12,13]:
• Elementary circuit
• Selflift circuit
Voltage Lift Converters 221
• Relift circuit
• Triplelift circuit
• Quadruplelift circuit.
The elementary circuit was discussed in Section 5.5.2 and the selflift circuit
was discussed in Section 6.2.4. Therefore, further circuits will be discussed in this
section.
6.4.1 ReLift Circuit
Figure 6.21 shows the N/O relift circuit, which is derived from the selflift circuit. It con
sists of one static switch S, three inductors L, L
1
, and L
O
, four capacitors C, C
1
, C
2
, and
C
O
, and diodes. It can be seen that one capacitor C
2
, one inductor L
1
, and two diodes
D
2
and D
11
have been added into the relift circuit. Circuit C
1
D
1
D
11
L
1
C
2
D
2
is the lift
circuit. Capacitors C
1
and C
2
perform characteristics to lift the capacitor voltage V
C
to
a level 2 times higher than the source voltage 2V
I
. Inductor L
1
performs the function
as a ladder joint to link the two capacitors C
1
and C
2
and lift the capacitor voltage V
C
.
Currents i
C1
(t) and i
C2
(t) are exponential functions δ
1
(t) and δ
2
(t). They have large val
ues at the moment of power switching on, but they are small because v
C1
= v
C2
∼
= V
I
in
steady state.
WhenswitchSis on, the source current i
I
= i
L
+i
C1
+i
C2
. Inductor Labsorbs energyfrom
the source, and current i
L
linearly increases with slope V
I
/L. In the meantime the diodes D
1
and D
2
are conducted so that capacitors C
1
and C
2
are charged by the currents i
C1
and i
C2
.
Inductor L
O
keeps the output current I
O
continuous and transfers energy from capacitor C
to the load R, that is, i
C−on
= i
LO
. When switch S is off, the source current i
I
= 0. Current i
L
ﬂows through the freewheeling diode D, capacitors C
1
and C
2
, and inductor L
1
to charge
capacitor C and enhance current i
LO
. Inductor L transfers its SE to capacitor C and load R
via inductor L
O
, that is, i
L
= i
C1−off
= i
C2−off
= i
L1−off
= i
C−off
+i
LO
. Thus, the current i
L
decreases.
V
S
D
11
i
L1
C
1
i
C1
i
D
V
LO
i
O
i
CO
C C
O
i
C
L
O
V
O
R
i
LO
+
+
–
–
L
1
D
1
D
2
C
2
D
10
i
D11
i
in
V
in
S
i
L
L
D
– +
FIGURE 6.21 N/O relift circuit. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 142. With permission.)
222 Power Electronics
The output current I
O
= I
LO
because the capacitor C
O
does not consume any energy in
the steady state. The average output current is
I
O
= I
LO
= I
C−on
. (6.112)
The charge of capacitor C increases during switchoff:
Q+ = (1 −k)TI
C−off
.
It decreases during switchon: Q− = kTI
C−on
.
In the whole repeating period T, Q+ = Q−. Thus,
I
C−off
=
k
1 −k
I
C−on
=
k
1 −k
I
O
.
Therefore, the inductor current I
L
is
I
L
= I
C−off
+I
O
=
I
O
1 −k
. (6.113)
We know that
I
C1−off
= I
C2−off
= I
L1
= I
L
=
1
1 −k
I
O
, (6.114)
I
C1−on
=
1 −k
k
I
C1−off
=
1
k
I
O
, (6.115)
and
I
C2−on
=
1 −k
k
I
C2−off
=
1
k
I
O
. (6.116)
In the steady state, we can use
V
C1
= V
C2
= V
I
and
V
L1−on
= V
I
, V
L1−off
=
k
1 −k
V
I
.
Considering current i
L
, it increases during switchon with slope V
I
/L and decreases during
switchoff with slope −(V
O
−V
C1
−V
C2
−V
L1−off
)/L = −[V
O
−2V
I
−kV
I
/(1 −k)]/L.
Therefore,
kTV
I
= (1 −k)T
_
V
O
−2V
I
−
k
1 −k
V
I
_
or
V
O
=
2
1 −k
V
I
, (6.117)
Voltage Lift Converters 223
and
I
O
=
1 −k
2
I
I
. (6.118)
The voltage transfer gain in the continuous mode is
M
R
=
V
O
V
I
=
I
I
I
O
=
2
1 −k
. (6.119)
The curve of M
R
versus k is shown in Figure 6.11. The circuit (CL
O
C
O
) is a “Π”type
lowpass ﬁlter. Therefore,
V
C
= V
O
=
2
1 −k
V
I
. (6.120)
Current i
L
increases and is supplied by V
I
during switchon. Thus, its peaktopeak
variation is
Δi
L
=
kTV
I
L
.
The variation ratio of current i
L
is
ζ =
Δi
L
/2
I
L
=
k(1 −k)V
I
T
2LI
O
=
k(1 −k)R
2M
R
f L
=
k
M
2
R
R
f L
. (6.121)
The peaktopeak variation of current i
L1
is
Δi
L1
=
k
L
1
TV
I
.
The variation ratio of current i
L1
is
χ
1
=
Δi
L1
/2
I
L1
=
kTV
I
2L
1
I
O
(1 −k) =
k(1 −k)
2M
R
R
f L
1
. (6.122)
The peaktopeak variation of voltage v
C
is
Δv
C
=
Q−
C
=
k
C
TI
O
.
The variation ratio of voltage v
C
is
ρ =
Δv
C
/2
V
C
=
kI
O
T
2CV
O
=
k
2
1
f CR
. (6.123)
The peaktopeak variation of voltage v
C1
is
Δv
C1
=
kT
C
1
I
C1−on
=
1
f C
I
O
.
224 Power Electronics
The variation ratio of voltage v
C1
is
σ
1
=
Δv
C1
/2
V
C1
=
I
O
2f C
1
V
I
=
M
R
2
1
f C
1
R
. (6.124)
Using the same operation, the variation ratio of voltage v
C2
is
σ
2
=
Δv
C2
/2
V
C2
=
I
O
2f C
2
V
I
=
M
R
2
1
f C
2
R
. (6.125)
Since
Δi
LO
=
1
2
T
2
k
2CL
O
TI
O
=
k
8f
2
CL
O
I
O
,
the variation ratio of current i
LO
is
ξ =
Δi
LO
/2
I
LO
=
k
16
1
f
2
CL
O
. (6.126)
Since
Δv
CO
=
B
C
O
=
1
2
T
2
k
16f
2
CC
O
L
O
I
O
=
k
64f
3
CC
O
L
O
I
O
,
the variation ratio of current v
CO
is
ε =
Δv
CO
/2
V
CO
=
k
128f
3
CC
O
L
O
I
O
V
O
=
k
128
1
f
3
CC
O
L
O
R
. (6.127)
Example 6.3
An N/O relift Luoconverter has the following components: V
I
= 20V, L = L
1
= L
O
= 1mH, all
capacitances are equal to 20μF, R = 160Ω, f = 50kHz, and k = 0.5. Calculate the output voltage
and the variation ratios ξ, ζ, χ
1
, ρ, σ
1
, σ
2
, and ε in steady state.
SOLUTION
From Equation 6.127, we obtain the output voltage as
V
O
=
2
1 −k
V
I
=
2
1 −0.5
20 = 80V.
The variation ratios are ξ = 6.25 ×10
−4
, ζ = 0.04, χ
1
= 0.1, ρ = 0.0016, σ
1
= 0.04, σ
2
= 0.04,
and ε = 7.8 ×10
−5
. Therefore, the variations are small.
In the DCM, the diode current i
D
becomes zero during switchoff before the next period switch
on. The condition for DCM is ζ ≥ 1, that is,
k
M
2
R
R
f L
≥ 1
Voltage Lift Converters 225
or
M
R
≤
√
k
_
R
f L
=
√
k
√
z
N
. (6.128)
The graph of the boundary curve versus the normalized load z
N
= R/fL is shown in Figure 6.12.
It can be seen that the boundary curve has a minimum value of 3.0 at k = 1/3.
In this case, the current i
D
exists in the period between kT and t
1
= [k +(1 −k)m
R
]T, where
m
R
is the ﬁlling efﬁciency and it is deﬁned as
m
R
=
1
ζ
=
M
2
R
k(R/f L)
. (6.129)
Therefore, 0 < m
R
< 1. Because inductor current i
L1
= 0 at t = t
1
,
V
L1−off
=
k
(1 −k)m
R
V
I
.
Since the current i
D
becomes zero at t = t
1
= [k +(1 −k)m
R
]T, for the current i
L
,
kTV
I
= (1 −k)m
R
T(V
C
−2V
I
−V
L1−off
)
or
V
C
=
_
2 +
2k
(1 −k)m
R
_
V
I
=
_
2 +k
2
(1 −k)
R
2f L
_
V
I
with
√
k
_
R
f L
≥
2
1 −k
,
and for the current i
LO
, kT(V
I
+V
C
−V
O
) = (1 −k)m
R
T(V
O
−2V
I
−V
L1−off
).
Therefore, the output voltage in the discontinuous mode is
V
O
=
_
2 +
2k
(1 −k)m
R
_
V
I
=
_
2 +k
2
(1 −k)
R
2f L
_
V
I
with
√
k
_
R
f L
≥
2
1 −k
. (6.130)
That is, the output voltage linearly increases as the load resistance R increases. Larger load resis
tance R may cause higher output voltage in the discontinuous mode.
6.4.2 N/OTripleLift Circuit
An N/O triplelift circuit is shown in Figure 6.22. It consists of one static switch S, four
inductors L, L
1
, L
2
, and L
O
, ﬁve capacitors C, C
1
, C
2
, C
3
, and C
O
, and diodes. The circuit
C
1
D
1
L
1
C
2
D
2
D
11
L
2
C
3
D
3
D
12
is the lift circuit. Capacitors C
1
, C
2
, and C
3
performchar
acteristics to lift the capacitor voltage V
C
to a level 3 times higher than the source voltage
V
I
. L
1
and L
2
perform the function as ladder joints to link the three capacitors C
1
, C
2
, and
C
3
and lift the capacitor voltage V
C
up. Currents i
C1
(t), i
C2
(t), and i
C3
(t) are exponential
functions. They have large values at the moment of power switching on, but they are small
because v
C1
= v
C2
= v
C3
∼
= V
I
in steady state.
The output voltage and current are
V
O
=
3
1 −k
V
I
(6.131)
and
I
O
=
1 −k
3
I
I
. (6.132)
226 Power Electronics
+ –
D
10
V
S
i
in
V
in
C
3
i
D3
D
3
D
2
D
1
C
O
V
O
R
–
+
C
i
D2
i
D1
i
L
L
S
D
12
D
11
i
C2
C
1
i
C1
C
2
L
2
i
L2
i
L1
L
1
i
C
i
D
V
LO
L
O
i
LO
i
CO
i
O
+ –
D
FIGURE 6.22 N/Otriplelift circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 151. With permission.)
The voltage transfer gain in the continuous mode is
M
T
=
V
O
V
I
=
3
1 −k
. (6.133)
The curve of M
T
versus k is shown in Figure 6.14.
Other average voltages: V
C
= V
O
; V
C1
= V
C2
= V
C3
= V
I
.
Other average currents: I
LO
= I
O
; I
L
= I
L1
= I
L2
=
1
1 −k
I
O
.
Current variation ratios: ζ =
k
M
2
T
3R
2f L
; ξ =
k
16
1
f
2
CL
O
; χ
1
=
k(1 −k)
2M
T
R
f L
1
;
χ
2
=
k(1 −k)
2M
T
R
f L
2
.
Voltage variation ratios: ρ =
k
2
1
f CR
; σ
1
=
M
T
2
1
f C
1
R
; σ
2
=
M
T
2
1
f C
2
R
; σ
3
=
M
T
2
1
f C
3
R
.
The variation ratio of output voltage V
C
is
ε =
k
128
1
f
3
CC
O
L
O
R
. (6.134)
The boundary between continuous and discontinuous modes is
M
T
≤
√
k
_
3R
2f L
=
_
3kz
N
2
. (6.135)
Voltage Lift Converters 227
It can be seen that the boundary curve has a minimum value of M
T
that is equal to 4.5,
corresponding to k = 1/3. The boundary curve versus the normalized load z
N
= R/fL is
shown in Figure 6.15.
In the discontinuous mode, the current i
D
exists in the period between kT and t
1
= [k +
(1 −k)m
T
]T, where m
T
is the ﬁlling efﬁciency, that is,
m
T
=
1
ζ
=
M
2
T
k(3R/2f L)
. (6.136)
Because inductor current i
L1
= i
L2
= 0 at t = t
1
; therefore 0 < m
T
< 1:
V
L1−off
= V
L2−off
=
k
(1 −k)m
T
V
I
.
Since the current i
D
becomes zero at t = t
1
= [k +(1 −k)m
T
]T, for the current i
L
, we have
kTV
I
= (1 −k)m
T
T(V
C
−3V
I
−V
L1−off
−V
L2−off
)
or
V
C
=
_
3 +
3k
(1 −k)m
T
_
V
I
=
_
3 +k
2
(1 −k)
R
2f L
_
V
I
with
√
k
_
3R
2f L
≥
3
1 −k
,
and for the current i
LO
, we have
kT(V
I
+V
C
−V
O
) = (1 −k)m
T
T(V
O
−2V
I
−V
L1−off
−V
L2−off
).
Therefore, output voltage in the discontinuous mode is
V
O
=
_
3 +
3k
(1 −k)m
T
_
V
I
=
_
3 +k
2
(1 −k)
R
2f L
_
V
I
with
√
k
_
3R
2f L
≥
3
1 −k
. (6.137)
That is, the output voltage increases linearly as the load resistance R increases. We can see
that the output voltage increases as the load resistance R increases.
6.4.3 N/O QuadrupleLift Circuit
An N/Oquadruplelift circuit is shown in Figure 6.23. It consists of one static switch S, ﬁve
inductors L, L
1
, L
2
, L
3
, andL
O
, andsix capacitors C, C
1
, C
2
, C
3
, C
4
, andC
O
. Capacitors C
1
, C
2
,
C
3
, and C
4
perform characteristics to lift the capacitor voltage V
C
to a level 4 times higher
than the source voltage V
I
. L
1
, L
2
, and L
3
perform the function of ladder joints to link the
four capacitors C
1
, C
2
, C
3
, and C
4
and lift the output capacitor voltage V
C
. Currents i
C1
(t),
i
C2
(t), i
C3
(t), and i
C4
(t) are exponential functions. They have large values at the moment
of power switching on, but they are small because v
C1
= v
C2
= v
C3
= v
C4
∼
= V
I
in steady
state.
The output voltage and current are
V
O
=
4
1 −k
V
I
(6.138)
228 Power Electronics
V
S
S
D
13
i
D13
i
C3
D
11
D
12
D
4
L
D
3
D
2
D
1
i
D1
i
D2
i
D3
i
D11
i
C2
i
C1
C
1
i
D
i
C
i
O
i
CO
C
O
C
V
O
R
i
LO
V
LO
L
O
D
–
–
+
+
C
2
i
D12
C
3
L
3
i
L3
i
L2
L
2
i
L1
L
1
D
10
i
C4
C
4
i
D4
i
L
V
in
i
in
+
–
FIGURE 6.23 N/Oquadruplelift circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 155. With permission.)
and
I
O
=
1 −k
4
I
I
. (6.139)
The voltage transfer gain in the continuous mode is
M
Q
=
V
O
V
I
=
4
1 −k
. (6.140)
The curve of M
Q
versus k is shown in Figure 6.17.
Other average voltages: V
C
= V
O
; V
C1
= V
C2
= V
C3
= V
C4
= V
I
.
Other average currents: I
LO
= I
O
; I
L
= I
L1
= I
L2
= I
L3
=
1
1 −k
I
O
.
Current variation ratios: ζ =
k
M
2
Q
2R
f L
; ξ =
k
16
1
f
2
CL
O
;
χ
1
=
k(1 −k)
2M
Q
R
f L
1
; χ
2
=
k(1 −k)
2M
Q
R
f L
2
; χ
3
=
k(1 −k)
2M
Q
R
f L
3
.
Voltage variation ratios: ρ =
k
2
1
f CR
; σ
1
=
M
Q
2
1
f C
1
R
;
σ
2
=
M
Q
2
1
f C
2
R
; σ
3
=
M
Q
2
1
f C
3
R
; σ
4
=
M
Q
2
1
f C
4
R
.
The variation ratio of output voltage V
C
is
ε =
k
128
1
f
3
CC
O
L
O
R
. (6.141)
Voltage Lift Converters 229
The output voltage ripple is very small.
The boundary between CCM and DCM is
M
Q
≤
√
k
_
2R
f L
=
_
2kz
N
. (6.142)
It can be seen that the boundary curve has a minimum value of M
Q
that is equal to 6.0,
corresponding to k =1/3. The boundary curve is shown in Figure 6.18.
In the discontinuous mode, the current i
D
exists in the period between kT and t
1
= [k +
(1 −k)m
Q
]T, where m
Q
is the ﬁlling efﬁciency, that is,
m
Q
=
1
ζ
=
M
2
Q
k(2R/f L)
. (6.143)
Because inductor current i
L1
= i
L2
= i
L3
= 0 at t = t
1
; therefore 0 < m
Q
< 1:
V
L1−off
= V
L2−off
= V
L3−off
=
k
(1 −k)m
Q
V
I
.
Since the current i
D
becomes zero at t = t
1
= kT +(1 −k)m
Q
T, for the current i
L
, we have
kTV
I
= (1 −k)m
Q
T(V
C
−4V
I
−V
L1−off
−V
L2−off
−V
L3−off
)
or with
V
C
=
_
4 +
4k
(1 −k)m
Q
_
V
I
=
_
4 +k
2
(1 −k)
R
2f L
_
V
I
with
√
k
_
2R
f L
≥
4
1 −k
,
and for current i
LO
, we have
kT(V
I
+V
C
−V
O
) = (1 −k)m
Q
T(V
O
−2V
I
−V
L1−off
−V
L2−off
−V
L3−off
).
Therefore, the output voltage in the discontinuous mode is
V
O
=
_
4 +
4k
(1 −k)m
Q
_
V
I
=
_
4 +k
2
(1 −k)
R
2f L
_
V
I
with
√
k
_
2R
f L
≥
4
1 −k
. (6.144)
That is, the output voltage linearly increases as the load resistance R increases. We can
see that the output voltage increases as load resistance R increases.
230 Power Electronics
6.4.4 Summary
From the analysis and calculation in previous sections, the common formulae for all these
circuits can be obtained:
M =
V
O
V
I
=
I
I
I
O
; z
N
=
R
f L
; R =
V
O
I
O
.
Inductor current variation ratios: ζ =
k(1 −k)R
2Mf L
; ξ =
k
16f
2
CL
O
;
χ
i
=
k(1 −k)R
2Mf L
i
, i = 1, 2, 3, . . . , n −1 with n ≥ 2.
Capacitor voltage variation ratios: ρ =
k
2f CR
; ε =
k
128f
3
CC
O
L
O
R
;
σ
i
=
M
2f C
i
R
, i = 1, 2, 3, 4, . . . , n with n ≥ 1.
Here i is the component number and n is the stage number. In order to write common
formulae for the boundaries between continuous and discontinuous modes and the output
voltage for all circuits, the circuits can be numbered. The deﬁnition is that subscript n = 0
denotes the elementary circuit, 1 the selflift circuit, 2 the relift circuit, 3 the triplelift circuit,
4 the quadruplelift circuit, and so on. Therefore, the voltage transfer gain in the continuous
120
100
80
50
30
10
0 0.2
(i)
(ii)
(iv)
(iii)
(v)
0.4 0.6
Conduction duty (k)
O
u
t
p
u
t
v
o
l
t
a
g
e
,
V
O
,
V
0.8 1
FIGURE 6.24 Output voltages of N/OLuoconverters (V
I
= 10 V). (i) Quadruplelift circuit; (ii) triplelift circuit;
(iii) relift circuit; (iv) selflift circuit; and(v) elementary circuit. (ReprintedfromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 160. With permission.)
Voltage Lift Converters 231
mode for all circuits is (Figure 6.24)
M
n
=
n +kh(n)
1 −k
, n = 0, 1, 2, 3, 4, . . . . (6.145)
The variation of freewheeling diode current i
D
is
ζ
n
=
k
[1+h(n)]
M
2
n
n +h(n)
2
z
N
. (6.146)
The boundaries are determined by the condition:
ζ
n
≥ 1
or
k
[1+h(n)]
M
2
n
n +h(n)
2
z
N
≥ 1, n = 0, 1, 2, 3, 4, . . . . (6.147)
Therefore, the boundaries between continuous and discontinuous modes for all circuits
are
M
n
= k
(1+h(n))/2
_
n +h(n)
2
z
N
, n = 0, 1, 2, 3, 4, . . . . (6.148)
For DCM, the ﬁlling efﬁciency is
m
n
=
1
ζ
n
=
M
2
n
k
[1+h(n)]
2
n +h(n)
1
z
N
. (6.149)
The voltage across capacitor C in the discontinuous mode for all circuits is
V
C−n
=
_
n +k
[2−h(n)]
1 −k
2
z
N
_
V
I
, n = 0, 1, 2, 3, 4, . . . . (6.150)
The output voltage in the discontinuous mode for all circuits is
V
O−n
=
_
n +k
[2−h(n)]
1 −k
2
z
N
_
V
I
, n = 0, 1, 2, 3, 4, . . . , (6.151)
where
h(n) =
_
0 if n ≥ 1
1 if n = 0
is the Hong function.
The voltage transfer gains inCCMfor all circuits are showninFigure 6.24. The boundaries
between continuous and discontinuous modes of all circuits are shown in Figure 6.25. The
232 Power Electronics
Continuous mode
Discontinuous mode
Normalised load (z
N
= R/fL)
44.5
0.5
1.5
3
V
o
l
t
a
g
e
t
r
a
n
s
f
e
r
g
a
i
n
(
M
)
4.5
6
13.5
M
E
M
S
M
R
M
T
M
Q
27 54 40.5
FIGURE 6.25 Boundaries between CCM and DCM of N/O Luoconverters. (Reprinted from Luo, F. L. and Ye,
H. 2006. Essential DC/DC Converters.Boca Raton: Taylor & Francis Group LLC, p. 161. With permission.)
curves of all M versus z
N
suggest that the continuous mode area increases fromM
E
via M
S
,
M
R
, and M
T
to M
Q
. The boundary of the elementary circuit is a monorising curve, but other
curves are not monorising. There are minimum values of the boundaries of other circuits,
which for M
S
, M
R
, M
T
, and M
Q
correspond at k = 1/3.
6.5 Modified P/O LuoConverters
N/O Luoconverters perform the voltage conversion from positive to negative voltages
using the VL technique with only one switch S. This section introduces the technique to
modify P/O Luoconverters that can employ only one switch for all circuits. Five circuits
have been introduced in the literature [14]:
• Elementary circuit
• Selflift circuit
• Relift circuit
• Triplelift circuit
• Quadruplelift circuit.
The elementary circuit is the original P/O Luoconverter. We will introduce the selflift
circuit, relift circuit, and multiplelift circuit in this section.
Voltage Lift Converters 233
6.5.1 SelfLift Circuit
The selflift circuit is shown in Figure 6.26. It is derived from the elementary circuit of the
P/O Luoconverter. In steady state, the average of inductor voltages in a period is zero.
Thus
V
C1
= V
CO
= V
O
. (6.152)
The inductor current i
L
increases in the switchon period and decreases in the switchoff
period. The corresponding voltages across L are V
I
and −V
C
.
Therefore, kTV
I
= (1 −k)TV
C
. Hence,
V
C
=
k
1 −k
V
I
. (6.153)
+
(a)
(b)
(c)
–
i
I
S
L
i
L
V
I
C
L
O
D
C
O
R
+
–
V
O
+
–
V
C1
i
LO
i
O
D
1
C
1
+
–
V
C
i
I
+
–
L i
L
V
I
C
L
O
C
O
R
+
–
V
O
+
–
V
C1
i
LO
i
O
C
1
+
–
V
C
+
–
L
i
L
V
I
C
L
O
C
O
R
+
–
V
O
+
–
V
C
i
LO
i
O
C
1
+
–
V
C1
i
I
=0
FIGURE 6.26 (a) Selflift circuit of modiﬁed P/O Luoconverters and its equivalent circuit during (b) switchon,
and (c) switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor &
Francis Group LLC, p. 163. With permission.)
234 Power Electronics
During the switchon period, the voltage across capacitor C
1
is equal to the source voltage
plus the voltage across C. Since we assume that C and C
1
are sufﬁciently large,
V
C1
= V
I
+V
C
.
Therefore,
V
C1
=V
I
+
k
1 −k
V
I
=
1
1 −k
V
I
.
V
O
=V
CO
= V
C1
=
1
1 −k
V
I
.
The voltage transfer gain of CCM is
M =
V
O
V
I
=
1
1 −k
.
The output voltage and current and the voltage transfer gain are
V
O
=
1
1 −k
V
I
,
I
O
= (1 −k)I
I
,
M
S
=
1
1 −k
. (6.154)
Average voltages: V
C
= kV
O
,
V
C1
= V
O
.
Average currents: I
LO
= I
O
,
I
L
=
1
1 −k
I
O
.
We also implement the breadboard prototype of the proposed selflift circuit. NMOS
IRFP460 is usedas the semiconductor switch. The diode is MR824. The other parameters are
V
I
= 0−30 V, R = 30−340, k = 0.1−0.9,
C = C
O
= 100 mF, and L = 470 μH.
6.5.2 ReLift Circuit
The relift circuit and its equivalent circuits are shown in Figure 6.27. It is derived from the
selflift circuit. The function of capacitor C
2
is to lift the voltage v
C
to a level higher than
the source voltage V
I
; inductor L
1
performs the function of the hinge of a foldable ladder
(capacitor C
2
) to lift the voltage v
C
during switchoff.
In steady state, the average of inductor voltages over a period is zero. Thus
V
C1
= V
CO
= V
O
.
Voltage Lift Converters 235
i
I
C
2
i
L1
L
1
V
I
i
L
C
1
C
O
L
O
V
C1
+
–
+
+ +
–
–
–
V
O
+
–
R
V
C2
L
V
C
i
O
i
LO
C
i
I
=0
C
2
i
L1 L
1
V
I
i
L
C
1
C
O
L
O
V
C1
+
–
+
+
+
–
–
–
V
O
+
–
R
V
C2
L
V
C i
O
i
LO
C
i
I
D
11
D
2
C
2
L
D
i
L1
V
I
L
1
V
C1 C
1
C
O
D
1
L
O
V
O
+
+
+
(a)
(b)
(c)
+
–
–
–
–
R
D
10
V
C2
V
C
i
O
i
LO
i
L
C
+
–
S
FIGURE 6.27 (a) Relift circuit and its equivalent circuit during (b) switchon, and (c) switchoff. (Reprinted from
Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 166. With
permission.)
Since we assume that C
2
is large enough and C
2
is biased by the source voltage V
I
during
the switchon period, V
C2
= V
I
.
From the switchon equivalent circuit, another capacitor voltage equation can also be
derived since we assume all the capacitors to be large enough,
V
O
= V
C1
= V
C
+V
I
.
The inductor current i
L
increases in the switchon period and decreases in the switch
off period. The corresponding voltages across L
1
are V
I
and −V
L−off
. Therefore, kTV
I
=
(1 −k)TV
L−off
. Hence,
V
L−off
=
k
1 −k
V
I
.
The inductor current i
L1
increases in the switchon period and decreases in the switch
off period. The corresponding voltages across L
1
are V
I
and −V
L1−off
. Therefore, kTV
I
=
(1 −k)TV
L1−off
.
Hence,
V
L1−off
=
k
1 −k
V
I
.
236 Power Electronics
From the switchoff period equivalent circuit,
V
C
= V
C−off
= V
L−off
+V
L1−off
+V
C2
.
Therefore,
V
C
=
k
1 −k
V
I
+
k
1 −k
V
I
+V
I
=
1 +k
1 −k
V
I
, (6.155)
V
O
=
1 +k
1 −k
V
I
+V
I
=
2
1 −k
V
I
.
Then we get the voltage transfer ratio in the CCM,
M = M
R
=
2
1 −k
. (6.156)
The following is a brief summary of the main equations for the relift circuit. The output
voltage and current and the voltage transfer gain are
V
O
=
2
1 −k
V
I
,
I
O
=
1 −k
2
I
I
,
M
R
=
2
1 −k
.
Average voltages: V
C
=
1 +k
1 −k
V
I
,
V
C1
= V
CO
= V
O
,
V
C2
= V
I
.
Average currents: I
LO
= I
O
,
I
L
= I
L1
=
1
1 −k
I
O
.
6.5.3 MultipleLift Circuit
Multiplelift circuits are derived from relift circuits by repeating the section of L
1
C
1
D
1
multiple times. For example, a triplelift circuit is shown in Figure 6.28. The function
of capacitors C
2
and C
3
is to lift the voltage V
C
across capacitor C to a level 2 times
higher than the source voltage 2V
I
, and the inductors L
1
and L
2
perform the function
of the hinges of a foldable ladder (capacitors C
2
and C
3
) to lift the voltage V
C
during
switchoff.
Voltage Lift Converters 237
D
11
D
1
V
C
i
LO i
O
C
1 D C
O
V
O
V
C1
R
+
+
–
–
L
O
i
I
S
D
12
i
L1
C
C
2
D
10
V
C3
V
C2
C
3
L
2
L
1
D
2
D
3
i
L V
I
L
+
+
+
+
–
–
–
–
FIGURE 6.28 Triplelift circuit. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 168. With permission.)
The output voltage and current and the voltage transfer gain are
V
O
=
3
1 −k
V
I
,
I
O
=
1 −k
3
I
I
, (6.157)
M
T
=
3
1 −k
.
Other average voltages: V
C
=
2 +k
1 −k
V
I
,
V
C1
= V
O
,
V
C2
= V
C3
= V
I
.
Other average currents: I
LO
= I
O
,
I
L1
= I
L2
= I
L
=
1
1 −k
I
O
.
The quadruplelift circuit is shown in Figure 6.29. The function of capacitors C
2
, C
3
, and
C
4
is to lift the voltage V
C
across capacitor Cto a level 3 times higher than the source voltage
i
I
S
D
11
V
C2
i
L1
V
C
i
LO
i
O
L
O D
1
C
C
2
C
3
V
C3
i
L2
V
C1
D
C
1
C
O
V
O
R
+
+
–
+
+
+
+
+
–
–
–
–
–
–
i
L3
V
C4
C
4
i
L
V
I
L
2
D
2
D
3
D
4 L
L
1
L
3
D
12
D
13
D
10
FIGURE 6.29 Quadruplelift circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 169. With permission.)
238 Power Electronics
3V
I
. The inductors L
1
, L
2
, and L
3
perform the function of the hinges of a foldable ladder
(capacitors C
2
, C
3
, and C
4
) to lift the voltage V
C
during switchoff. The output voltage and
current and voltage transfer gain are
V
O
=
4
1 −k
V
I
, I
O
=
1 −k
4
I
I
, (6.158)
M
Q
=
4
1 −k
.
Average voltages: V
C
=
3 +k
1 −k
V
I
, V
C1
= V
O
,
V
C2
= V
C3
= V
C4
= V
I
.
Average currents: I
LO
= I
O
, I
L
=
k
1 −k
I
O
,
I
L1
= I
L2
= I
L3
= I
L
+I
LO
=
1
1 −k
I
O
.
6.6 D/O LuoConverters
Mirrorsymmetrical D/Ovoltages are speciallyrequiredinindustrial applications andcom
puter periphery circuits. The D/ODC–DCLuoconverter can convert positive input source
voltage to P/O and N/O voltages. It consists of two conversion paths. It performs increas
ing conversion from positive to positive and negative DC–DC voltages with high power
density, high efﬁciency, and cheap topology in a simple structure [15,16]. Like P/O and
N/O Luoconverters, there are ﬁve circuits in this series:
• Elementary circuit
• Selflift circuit
• Relift circuit
• Triplelift circuit
• Quadruplelift circuit.
The elementary circuit is the original D/O Luoconverter introduced in Section 5.53. We
will introduce the selflift circuit, relift circuit, triplelift circuit, and quadruplelift circuit
in this section.
6.6.1 SelfLift Circuit
The selflift circuit shown in Figure 6.30 is derived fromthe elementary circuit. The positive
conversion path consists of a pump circuit SL
1
D
0
C
1
, a ﬁlter (C
2
)L
2
C
O
, and a lift circuit
D
1
C
2
. The negative conversionpathconsists of a pumpcircuit SL
11
D
10
(C
11
), an“Π”type
ﬁlter C
11
L
12
C
10
, and a lift circuit D
11
C
12
.
Voltage Lift Converters 239
V
S
V
in
i
in
i
in+
i
L1
L
1
V
C1
D
0
C
2
i
L2
C
O
D
20
i
in–
iL
11 L
11
D
11
D
10
C
12
D
21
C
11
C
10
i
L2
L
12
R
1
R
V
O–
V
O+
+
–
–
+
V
C11
C
1
D
1
L
2
I
O+
S
+
+
–
+
–
–
FIGURE 6.30 D/O selflift circuit. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 181. With permission.)
6.6.1.1 Positive Conversion Path
The equivalent circuit during switchon is shown in Figure 6.31a and its equivalent circuit
during switchoff is shown in Figure 6.31b. The voltage across inductor L
1
is equal to V
I
during switchon and −V
C1
during switchoff. We have the relation:
V
C1
=
k
1 −k
V
I
.
Hence,
V
O
= V
CO
= V
C2
= V
I
+V
C1
=
1
1 −k
V
I
and V
O+
= (1/(1 −k))V
I
. The output current is I
O+
= (1 −k)I
I+
.
Other relations are
I
I+
= ki
I+
, i
I+
= I
L1
+i
C1−on
, i
C1−off
=
k
1 −k
i
C1−on
,
and
I
L1
= i
C1−off
= ki
I+
= I
I+
. (6.159)
Therefore, the voltage transfer gain in the continuous mode is
M
S+
=
V
O+
V
I
=
1
1 −k
. (6.160)
The variation ratios of the parameters are
ξ
2+
=
Δi
L2
/2
I
L2
=
k
16
1
f
2
C
2
L
2
, ρ
+
=
Δv
C1
/2
V
C1
=
(1 −k)I
I+
2f C
1
(k/1 −k)V
I
=
1
2kf C
1
R
,
and σ
1+
=
Δv
C2
/2
V
C2
=
k
2f C
2
R
.
240 Power Electronics
i
L2
V
C1
V
O+
V
O+
V
C2
+
–
R
L
2
C
O
+
–
+
–
L
1 C
2
i
L1
i
L2
V
D0
L
1
V
C1
V
C2 C
2
–
R
L
2
C
O
+
–
S
i
L1
L
1 C
2
V
C1
i
in
+ i
L2
L
2
R
V
O+
+
–
V
in V
C2
C
O
+
–
– + (a)
(b)
(c)
FIGURE 6.31 Equivalent circuits positive path of the D/O selflift circuit: (a) switchon, (b) switchoff, and (c)
discontinuous conduction mode. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 182. With permission.)
The variation ratio of currents i
D0
and i
L1
is
ζ
+
= ξ
1+
=
Δi
L1
/2
I
L1
=
kV
I
T
2L
1
I
I+
=
k
M
2
S
R
2f L
1
. (6.161)
The variation ratio of output voltage v
O+
is
ε
+
=
Δv
O+
/2
V
O+
=
k
128
1
f
3
C
2
C
O
L
2
R
. (6.162)
6.6.1.2 Negative Conversion Path
The equivalent circuit during switchon is shown in Figure 6.32a, and its equivalent cir
cuit during switchoff is shown in Figure 6.32b. The relations of the average currents and
Voltage Lift Converters 241
i
L12
L
12
V
C12
V
O–
V
C11
i
C11
L
11
i
L11
+
–
R
1
C
10
– +
+
–
i
L12
L
12
V
D0
C
11 L
11
i
L11 V
C11
+
–
R
1
C
10
V
C12 – +
V
O–
+
–
S
i
L11
L
11
C
12
i
C12
i
in–
i
L12
R
1
V
O–
–
+
V
in
V
C11
C
10
C
11
+
+ –
–
(a)
(b)
(c)
FIGURE 6.32 Equivalent circuits negative path of the D/O selflift circuit: (a) switchon, (b) switchoff, and (c)
discontinuous conduction mode. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 184. With permission.)
voltages are
I
O−
= I
L12
= I
C11−on
, I
C11−off
=
k
1 −k
I
C11−on
=
k
1 −k
I
O−
,
and I
L11
= I
C11−off
+I
O−
=
I
O−
1 −k
. (6.163)
We knowthat I
C12−off
= I
L11
= (1/(1 −k))I
O−
andI
C12−on
= ((1 −k)/k)I
C12−off
= (1/k)I
O−
,
so that V
O−
= (1/(1 −k))V
I
and I
O−
= (1 −k)I
I
.
The voltage transfer gain in the continuous mode is
M
S−
=
V
O−
V
I
=
1
1 −k
. (6.164)
The circuit (C
11
L
12
C
10
) is a “Π”type lowpass ﬁlter. Therefore, V
C11
= V
O−
=
(k/(1 −k))V
I
. From Equations 6.160 and 6.161, deﬁne M
S
= M
S+
= M
S−
. The curve of M
S
versus k is shown in Figure 6.33.
242 Power Electronics
10
8
6
4
2
0
0 0.2 0.4 0.6
k
M
S
0.8 1
FIGURE 6.33 Voltage transfer gain M
S
versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 185. With permission.)
The variation ratios of the parameters are
ξ
−
=
Δi
L12
/2
I
L12
=
k
16
1
f
2
C
10
L
12
; ρ
−
=
Δv
C11
/2
V
C11
=
kI
O−
T
2C
11
V
O−
=
k
2
1
f C
11
R
1
;
σ
1−
=
Δv
C12
/2
V
C12
=
I
O−
2f C
12
V
I
=
M
S
2
1
f C
12
R
1
.
The variation ratio of currents i
D10
and i
L11
is
ζ
−
=
Δi
L11
/2
I
L11
=
k(1 −k)V
I
T
2L
11
I
O−
=
k(1 −k)R
1
2M
S
f L
11
=
k
M
2
S
R
1
2f L
11
. (6.165)
The variation ratio of current v
C10
is
ε
−
=
Δv
C10
/2
V
C10
=
k
128f
3
C
11
C
10
L
12
I
O−
V
O−
=
k
128
1
f
3
C
11
C
10
L
12
R
1
. (6.166)
Example 6.4
A D/O selflift Luoconverter has the following components: V
I
= 20V, all inductances are 1 mH,
all capacitances are equal to 20μF, R = R
1
= 160Ω, f = 50kHz, and k = 0.5. Calculate the
output voltage and the variation ratios, and ε in steady state.
Voltage Lift Converters 243
SOLUTION
From Equations 6.160 and 6.164, we obtain the output voltage as
V
O+
= V
O−
=
1
1 −k
V
I
=
1
1 −0.5
20 = 40V.
The variation ratios:
ξ
2+
= 6.25 ×10
−4
, ξ
1+
= ζ
1+
= 0.2, ρ
+
= 0.05, σ
1+
= 0.00625, and ε
+
= 2 ×10
−6
.
ξ
−
= 6.25 ×10
−4
, ζ
−
= 0.05, ρ
−
= 0.00625, σ
1−
= 0.025, and ε
+
= 2 ×10
−6
.
Therefore, the variations are small.
6.6.1.3 Discontinuous Conduction Mode
The equivalent circuits of the DCM’s operation are shown in Figures 6.31c and 6.32c. Since
we select z
N
= z
N+
= z
N−
, M
S
= M
S+
= M
S−
, and ζ = ζ
+
= ζ
−
, the boundary between
CCM and DCM is: ζ ≥ 1 or
k
M
2
S
z
N
2
≥ 1.
Hence,
M
S
≤
√
k
_
z
2
=
_
kz
N
2
. (6.167)
30
20
10
k=0.9
k=0.8
k=0.5
k=0.33
k=0.1
Discontinuous mode
Continuous mode
8
5
3
2
1.5
1
13.5 16 24.7 62.5 222
R/fL
M
S
842
FIGURE 6.34 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/f L (D/O selflift circuit). (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 187. With permission.)
244 Power Electronics
This boundary curve is shown in Figure 6.34. This curve has a minimumvalue of M
S
that
is equal to 1.5 at k = 1/3.
The ﬁlling efﬁciency is deﬁned as
m
S
=
1
ζ
=
2M
2
S
kz
N
. (6.168)
For the current i
L1
, we have
TV
I
= (1 −k)m
S+
TV
C1
or
V
C1
=
k
(1 −k)m
S
V
I
= k
2
(1 −k)
z
N
2
V
I
with
_
kz
N
2
≥
1
1 −k
. (6.169)
Therefore, the P/O voltage in the DCM is
V
O+
= V
C1
+V
I
=
_
1 +
k
(1 −k)m
S
_
V
I
=
_
1 +k
2
(1 −k)
z
N
2
_
V
I
with
_
kz
N
2
≥
1
1 −k
.
(6.170)
For the current i
L11
, we have
kTV
I
= (1 −k)m
S
T(V
C11
−V
I
)
or
V
C11
=
_
1 +
k
(1 −k)m
S
_
V
I
=
_
1 +k
2
(1 −k)
z
N
2
_
V
I
with
_
kz
N
2
≥
1
1 −k
(6.171)
and for the current i
L12
, we have kT (V
I
+V
C11
−V
O−
) = (1 −k)m
S−
T(V
O−
−V
I
).
Therefore, the N/O voltage in the DCM is
V
O−
=
_
1 +
k
(1 −k)m
S
_
V
I
=
_
1 +k
2
(1 −k)
z
N
2
_
V
I
with
_
kz
N
2
≥
1
1 −k
. (6.172)
Then we have V
O
= V
O+
= V
O−
= [1 +k
2
(1 −k)(z
N
/2)]V
I
; that is, the output voltage
linearly increases as the load resistance R increases. Larger load resistance causes higher
output voltage in the DCM, as shown in Figure 6.34.
6.6.2 ReLift Circuit
The relift circuit shown in Figure 6.35 is derived from the selflift circuit. The positive
conversion path consists of a pump circuit SL
1
D
0
C
1
, a ﬁlter (C
2
)L
2
C
O
, and a lift circuit
D
1
C
2
D
3
L
3
D
2
C
3
. Thenegativeconversionpathconsists of apumpcircuit SL
11
D
10
(C
11
),
an “Π” type ﬁlter C
11
L
12
C
10
, and a lift circuit D
11
C
12
L
13
D
22
C
13
D
12
.
Voltage Lift Converters 245
i
in+
D
2
L
1
C
3
L
3
C
1
V
C1
D
1
L
2
i
L2
C
2
C
O
D
0
D
3
D
11
L
11
C
12
D
21
i
L11
i
L1
D
22
L
13
C
13 D
10
D
12
V
C11 C
11 C
10
i
L12
L
12
I
O–
–
–
+
+
–
I
O+
V
O+
V
O–
R
1
R
V
S
S
D
20
i
in
V
in
i
in–
–
–
+
+
+
FIGURE 6.35 D/O relift circuit. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 189. With permission.)
6.6.2.1 Positive Conversion Path
The equivalent circuit during switchon is shown in Figure 6.36a, and its equivalent circuit
during switchoff is shown in Figure 6.36b.
The voltage across inductors L
1
and L
3
is equal to V
I
during switchon, and −(V
C1
−V
I
)
during switchoff. We have the following relations:
V
C1
=
1 +k
1 −k
V
I
and V
O
= V
CO
= V
C2
= V
I
+V
C1
=
2
1 −k
V
I
.
Thus,
V
O+
=
2
1 −k
V
I
and I
O+
=
1 −k
2
I
I+
.
The other relations are I
I+
= ki
I+
, i
I+
= I
L1
+I
L3
+i
C3−on
+i
C1−on
, i
C1−off
=
k/(1 −k)i
C1−on
and
I
L1
= I
L3
= i
C1−off
= i
C3−off
=
k
2
i
I+
=
1
2
I
I+
. (6.173)
The voltage transfer gain in the continuous mode is
M
R+
=
V
O+
V
I
=
2
1 −k
. (6.174)
246 Power Electronics
(a)
(b)
(c)
C
3
i
L2
C
2
+ –
L
1
L
3
I
L1
D
0
L
2
C
O
R
V
C1
V
O+
+
–
–
C
2
L
3 L
1
V
D0
V
C1
i
L2
i
L1
C
3
L
2
R
C
O
V
O+
+
–
–
+
– +
C
3
C
2 L
3
V
C1
i
L2
C
O
L
2
R
V
O+
–
+
V
in
i
L1 L
1
i
in+
S
FIGURE 6.36 Equivalent circuits positive path of the D/O relift circuit: (a) switchon, (b) switchoff, and (c)
discontinuous conduction mode. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 151. With permission.)
The variation ratios of the parameters are
ξ
2+
=
Δi
L2
/2
I
L2
=
k
16
1
f
2
C
2
L
2
; χ
1+
=
Δi
L3
/2
I
L3
=
kV
I
T
2L
3
(1/2)I
I+
=
k
M
2
R
R
f L
3
;
and
ρ
+
=
Δv
C1
/2
V
C1
=
(1 −k)TI
I
4C
1
(1 +k/1 −k)V
I
=
1
(1 +k)f C
1
R
; σ
1+
=
Δv
C2
/2
V
C2
=
k
2f C
2
R
;
σ
2+
=
Δv
C3
/2
V
C3
=
1 −k
4f C
3
I
I+
V
I
=
M
R
2f C
3
R
.
Voltage Lift Converters 247
The variation ratio of currents i
D0
and i
L1
is
ζ
+
= ξ
1+
=
Δi
D0
/2
I
D0
=
kV
I
T
L
1
I
I+
=
k
M
2
R
R
f L
1
, (6.175)
and the variation ratio of output voltage v
O+
is
ε
+
=
Δv
O+
/2
V
O+
=
k
128
1
f
3
C
2
C
O
L
2
R
. (6.176)
6.6.2.2 Negative Conversion Path
The equivalent circuit during switchon is shown in Figure 6.37a, and its equivalent circuit
during switchoff is shown in Figure 6.37b.
The relations of the average currents and voltages are
I
O−
= I
L12
= I
C11−on
I
C11−off
=
k
1 −k
I
C11−on
=
k
1 −k
I
O−
(a)
(b)
(c)
C
12 C
13
i
C11
i
L13
i
L11
L
11
C
11
i
L12
L
12
C
10
R
1
L
13
V
O–
–
+
V
D10
C
13 L
13
L
11
C
12
i
L12
R
1
C
11
V
C11
C
10
L
12
V
O–
–
–
+
+
–
+
C
12
C
13
L
13
i
L13
i
C13
C
11
C
10
i
C11
L
12
R
1
V
O–
–
+
V
in
i
L11
L
11
i
in–
S
i
C12
FIGURE 6.37 Equivalent circuits negative path of the D/O relift circuit: (a) switchon, (b) switchoff, and (c)
discontinuous conduction mode. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 192. With permission.)
248 Power Electronics
and
I
L11
= I
C11−off
+I
O−
=
I
O−
1 −k
. (6.177)
I
C12−off
= I
C13−off
= I
L11
=
1
1 −k
I
O−
; I
C12−on
=
1 −k
k
I
C12−off
=
1
k
I
O−
;
I
C13−on
=
1 −k
k
I
C13−off
=
1
k
I
O−
.
Inthe steadystate, we have: V
C12
= V
C13
= V
I
, V
L13−on
= V
I
, andV
L13−off
= (k/1 −k)V
I
.
V
O−
=
2
1 −k
V
I
and I
O−
=
1 −k
2
I
I−
.
The voltage transfer gain in the continuous mode is
M
R−
=
V
O−
V
I
=
I
I−
I
O−
=
2
1 −k
. (6.178)
The circuit (C
11
L
12
C
10
) is a “Π”type lowpass ﬁlter.
Therefore, V
C11
= V
O−
= (2/(1 −k))V
I
.
From Equations 6.174 and 6.178, we deﬁne M
R
= M
R+
= M
R−
. The curve of M
R
versus
k is shown in Figure 6.38.
20
16
12
M
R
8
4
0
0 0.2 0.4 0.6
k
0.8 1
FIGURE 6.38 Voltage transfer gain M
R
versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 193. With permission.)
Voltage Lift Converters 249
The variation ratios of the parameters are
ξ
−
=
Δi
L12
/2
I
L12
=
k
16
1
f
2
C
10
L
12
; χ
1−
=
Δi
L13
/2
I
L13
=
kTV
I
2L
13
I
O−
(1 −k) =
k(1 −k)
2M
R
R
1
f L
13
;
and
ρ
−
=
Δv
C11
/2
V
C11
=
kI
O−
T
2C
11
V
O−
=
k
2
1
f C
11
R
1
; σ
1−
=
Δv
C12
/2
V
C12
=
I
O−
2f C
12
V
I
=
M
R
2
1
f C
12
R
1
;
σ
2−
=
Δv
C13
/2
V
C13
=
I
O−
2f C
13
V
I
=
M
R
2
1
f C
13
R
1
.
The variation ratio of currents i
D10
and i
L11
is
ζ
−
=
Δi
L11
/2
I
L11
=
k(1 −k)V
I
T
2L
11
I
O−
=
k(1 −k)R
1
2M
R
f L
11
=
k
M
2
R
R
1
f L
11
. (6.179)
The variation ratio of current v
C10
is
ε
−
=
Δv
C10
/2
V
C10
=
k
128f
3
C
11
C
10
L
12
I
O−
V
O−
=
k
128
1
f
3
C
11
C
10
L
12
R
1
. (6.180)
6.6.2.3 Discontinuous Conduction Mode
The equivalent circuits of the DCM are shown in Figures 6.36c and 6.37c. In order to obtain
the mirrorsymmetrical D/O voltages, we purposely select z
N
= z
N+
= z
N−
and ζ = ζ
+
=
ζ
−
. The freewheeling diode currents i
D0
and i
D10
become zero during switchoff before the
next switchon period. The boundary between CCM and DCM is
ζ ≥ 1
or
k
M
2
R
z
N
≥ 1.
Hence,
M
R
≤
_
kz
N
. (6.181)
This boundary curve is shown in Figure 6.39. It can be seen that the boundary curve has a
minimum value of M
R
that is equal to 3.0, corresponding to k = 1/3.
The ﬁlling efﬁciency m
R
is
m
R
=
1
ζ
=
M
2
R
kz
N
. (6.182)
So
V
C1
=
_
1 +
2k
(1 −k)m
R
_
V
I
=
_
1 +k
2
(1 −k)
z
N
2
_
V
I
with
_
kz
N
≥
2
1 −k
. (6.183)
250 Power Electronics
Therefore, the P/O voltage in the DCM is
V
O+
= V
C1
+V
I
=
_
2 +
2k
(1 −k)m
R
_
V
I
=
_
2 +k
2
(1 −k)
z
N
2
_
V
I
with
_
kz
N
≥
2
1 −k
.
(6.184)
For the current i
L11
, because inductor current i
L13
=0 at t = t
1
, V
L13−off
= (k/(1 −k)m
R
)V
I
.
For the current i
L11
, we have
kTV
I
= (1 −k)m
R
T(V
C11
−2V
I
−V
L13−off
)
or
V
C11
=
_
2 +
2k
(1 −k)m
R
_
V
I
=
_
2 +k
2
(1 −k)
z
N
2
_
V
I
with
_
kz
N
≥
2
1 −k
, (6.185)
and for the current i
L12
we have kT(V
I
+V
C11
−V
O−
) = (1 −k)m
R
T(V
O−
−2V
I
−
V
L13−off
). Therefore, the N/O voltage in the DCM is
V
O−
=
_
2 +
2k
(1 −k)m
R
_
V
I
=
_
2 +k
2
(1 −k)
z
N
2
_
V
I
with
_
kz
N
≥
2
1 −k
. (6.186)
So
V
O
= V
O+
= V
O−
=
_
2 +k
2
(1 −k)
z
N
2
_
V
I
.
60
40
20
k = 0.95
k = 0.9
k = 0.8
k = 0.5
k = 0.33
k = 0.1
10
4
6
3
2
2732 50 125
Discontinuous mode
Continuous mode
R/fL
M
R
1684 444
FIGURE 6.39 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/f L (D/O relift circuit). (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 196. With permission.)
Voltage Lift Converters 251
That is, the output voltage linearly increases as the load resistance R increases. Larger
load resistance may cause higher output voltage in the discontinuous mode as shown in
Figure 6.39.
6.6.3 TripleLift Circuit
The triplelift circuit is shown in Figure 6.40.
The positive conversion path consists of a pump circuit SL
1
D
0
C
1
, a ﬁlter (C
2
)L
2
C
O
,
and a lift circuit D
1
C
2
D
2
C
3
D
3
L
3
D
4
C
4
D
5
L
4
. The negative conversion path consists of
a pump circuit SL
11
D
10
(C
11
), an “Π”type ﬁlter C
11
L
12
C
10
, and a lift circuit D
11
C
12
D
22

C
13
L
13
D
12
D
23
L
14
C
14
D
13
.
6.6.3.1 Positive Conversion Path
The lift circuit is D
1
C
2
D
2
C
3
D
3
L
3
D
4
C
4
D
5
L
4
. Capacitors C
2
, C
3
, and C
4
perform char
acteristics to lift the capacitor voltage V
C1
to a level 3 times higher than the source voltage
V
I
. L
3
, andL
4
performthe function of ladder joints to link the three capacitors C
3
andC
4
and
lift the capacitor voltage V
C1
up. Current i
C2
(t), i
C3
(t), and i
C4
(t) are exponential functions.
They have large values at the moment of power switching on, but they are small because
v
C3
= v
C4
= V
I
and v
C2
= V
O+
in the steady state.
The output voltage and current are
V
O+
=
3
1 −k
V
I
and I
O+
=
1 −k
3
I
I+
+
–
+
–
–
–
–
i
in
V
in
+
D
2
V
S
D
4
V
C1 D
1
L
2
I
O+
V
O+
V
O–
I
O–
R
1
C
10
C
11
V
C11
i
L12
D
10
L
12
C
14
C
13
L
13
D
11
D
3
L
3
L
1
C
3
i
L1
i
in+
i
in–
i
L11
L
11
C
12 D
21
D
22
D
23
C
4
D
20
C
1
L
4
D
0
C
2
C
O
i
L2
D
5
D
12
D
13
+
R
+
S
FIGURE 6.40 D/Otriplelift circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 197. With permission.)
252 Power Electronics
The voltage transfer gain in the continuous mode is
M
T+
=
V
O+
V
I
=
3
1 −k
. (6.187)
Other average voltages: V
C1
=
2 +k
1 −k
V
I
; V
C3
= V
C4
= V
I
; V
CO
= V
C2
= V
O+
.
Other average currents: I
L2
= I
O+
; I
L1
= I
L3
= I
L4
=
1
3
I
I+
=
1
1 −k
I
O+
.
Current variations: ξ
1+
= ζ
+
=
k(1 −k)R
2M
T
f L
=
k
M
2
T
3R
2f L
; ξ
2+
=
k
16
1
f
2
C
2
L
2
;
χ
1+
=
k
M
2
T
3R
2f L
3
; χ
2+
=
k
M
2
T
3R
2f L
4
.
Voltage variations: ρ
+
=
3
2(2 +k)f C
1
R
; σ
1+
=
k
2f C
2
R
; σ
2+
=
M
T
2f C
3
R
;
σ
3+
=
M
T
2f C
4
R
.
The variation ratio of the output voltage V
C0
is
ε
+
=
k
128
1
f
3
C
2
C
O
L
2
R
. (6.188)
6.6.3.2 Negative Conversion Path
The circuit C
12
D
11
L
13
D
22
C
13
D
12
L
14
D
23
C
14
D
13
is the lift circuit. Capacitors C
12
, C
13
,
and C
14
perform characteristics to lift the capacitor voltage V
C11
to a level 3 times higher
than the source voltage V
I
. L
13
and L
14
perform the function of ladder joints to link the
three capacitors C
12
, C
13
, and C
14
and lift the capacitor voltage V
C11
up. Currents i
C12
(t),
i
C13
(t), andi
C14
(t) are exponential functions. Theyhave large values at the moment of power
switching on, but they are small because v
C12
= v
C13
= v
C14
∼
= V
I
in the steady state.
The output voltage and current are
V
O−
=
3
1 −k
V
I
and I
O−
=
1 −k
3
I
I−
.
The voltage transfer gain in the continuous mode is
M
T−
=
V
O−
V
I
=
3
1 −k
. (6.189)
Voltage Lift Converters 253
From Equations 6.187 and 6.189, we deﬁne M
T
= M
T+
= M
T−
. The curve of M
T
versus k is
shown in Figure 6.41.
Other average voltages: V
C11
= V
O−
; V
C12
= V
C13
= V
C14
= V
I
.
Other average currents: I
L12
= I
O−
; I
L11
= I
L13
= I
L14
=
1
1 −k
I
O−
.
Current variation ratios: ζ
−
=
k
M
2
T
3R
1
2f L
11
; ξ
2−
=
k
16
1
f
2
C
10
L
12
;
χ
1−
=
k(1 −k)
2M
T
R
1
f L
13
; χ
2−
=
k(1 −k)
2M
T
R
1
f L
14
.
Voltage variation ratios: ρ
−
=
k
2
1
f C
11
R
1
; σ
1−
=
M
T
2
1
f C
12
R
1
;
σ
2−
=
M
T
2
1
f C
13
R
1
; σ
3−
=
M
T
2
1
f C
14
R
1
.
The variation ratio of output voltage V
C10
is
ε
−
=
k
128
1
f
3
C
11
C
10
L
12
R
1
. (6.190)
6.6.3.3 Discontinuous Mode
To obtain the mirrorsymmetrical D/Ovoltages, we purposely select: L
1
= L
11
and R = R
1
.
30
24
18
M
T
12
6
0
0 0.2 0.4 0.6
k
0.8 1
FIGURE 6.41 Voltage transfer gain M
T
versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 199. With permission.)
254 Power Electronics
Deﬁne:
V
O
= V
O+
= V
O−
, M
T
= M
T+
= M
T−
= V
O
/V
I
= (3/(1 −k)), z
N
= z
N+
= z
N−
,
and ζ = ζ
+
= ζ
−
The freewheeling diode currents i
D0
and i
D10
become zero during switchoff before the next
switchon period. The boundary between continuous and discontinuous modes is ζ ≥ 1.
The boundary between continuous and discontinuous modes is
M
T
≤
_
3kz
N
2
. (6.191)
This boundary curve is shown in Figure 6.42. It can be seen that the boundary curve has
a minimum value of M
T
that is equal to 4.5, corresponding to k = 1/3.
In the discontinuous mode, the currents i
D0
and i
D10
exist in the period between kT and
[k +(1 −k)m
T
]T, where m
T
is the ﬁlling efﬁciency, that is,
m
T
=
1
ζ
=
2M
2
T
3kz
N
. (6.192)
Considering Equation 6.191, therefore, 0 < m
T
< 1. Since the current i
D0
becomes zero at
t = t
1
= [k +(1 −k)m
T
]T, for the current i
L1
, i
L3
, and i
L4
, we have
3kTV
I
= (1 −k)m
T
T(V
C1
−2V
I
)
40
k=0.9
k=0.8
k=0.5
k=0.33
k=0.1
40 48 75 188 667
30
15
6
4.5
3
M
T
R/fL
Discontinuous mode
Continuous mode
FIGURE 6.42 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/f L (D/O triplelift circuit). (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 201. With permission.)
Voltage Lift Converters 255
or
V
C1
=
_
2 +
3k
(1 −k)m
T
_
V
I
=
_
2 +k
2
(1 −k)
z
N
2
_
V
I
with
_
3kz
N
2
≥
3
1 −k
. (6.193)
Therefore, the P/O voltage in the discontinuous mode is
V
O+
= V
C1
+V
I
=
_
3 +
3k
(1 −k)m
T
_
V
I
=
_
3 +k
2
(1 −k)
z
N
2
_
V
I
with
_
3kz
N
2
≥
3
1 −k
.
(6.194)
Because inductor current i
L11
= 0 at t = t
1
,
V
L13−off
= V
L14−off
=
k
(1 −k)m
T
V
I
.
Since i
D10
becomes 0 at t
1
= [k +(1 −k)m
T
]T, for the current i
L11
, we have kTV
I
=
(1 −k)m
T
−T(V
C11
−3V
I
−V
L13−off
−V
L14−off
)
or
V
C11
=
_
3 +
3k
(1 −k)m
T
_
V
I
=
_
3 +k
2
(1 −k)
z
N
2
_
V
I
with
_
3kz
N
2
≥
3
1 −k
, (6.195)
and for the current i
L12
, we have kT(V
I
+V
C14
−V
O−
) = (1 −k)m
T
−T(V
O−
−2V
I
−
V
L13−off
−V
L14−off
).
Therefore, the N/O voltage in discontinuous mode is
V
O−
=
_
3 +
3k
(1 −k)m
T
_
V
I
=
_
3 +k
2
(1 −k)
z
N
2
_
V
I
with
_
3kz
N
2
≥
3
1 −k
. (6.196)
So V
O
= V
O+
= V
O−
= [3 +k
2
(1 −k)(z
N
/2)]V
I
that is, the output voltage linearly increases
as the load resistance R increases. The output voltage increases as the load resistance R
increases, as shown in Figure 6.42.
6.6.4 QuadrupleLift Circuit
The quadruplelift circuit is shown in Figure 6.43.
The positive conversion path consists of a pump circuit SL
1
D
0
C
1
and a ﬁlter (C
2
)L
2

C
O
, anda lift circuit D
1
C
2
L
3
D
2
C
3
D
3
L
4
D
4
C
4
D
5
L
5
D
6
C
5
S
1
. The negative conversion
path consists of a pump circuit SL
11
D
10
(C
11
) and an “Π”type ﬁlter C
11
L
12
C
10
, and a lift
circuit D
11
C
12
D
22
L
13
C
13
D
12
D
23
L
14
C
14
D
13
D
24
L
15
C
15
D
14
.
6.6.4.1 Positive Conversion Path
Capacitors C
2
, C
3
, C
4
, and C
5
perform characteristics to lift the capacitor voltage V
C1
to a
level 4 times higher than the source voltage V
I
. L
3
, L
4
, and L
5
performthe function as ladder
joints to link the four capacitors C
2
, C
3
, C
4
, and C
5
, and lift the output capacitor voltage V
C1
256 Power Electronics
+
+
–
+
+
–
–
–
–
+
V
S
i
in
V
in
i
in–
i
L1
L
1
C
3
D
2
D
4
D
6
C
1
D
20
D
1
V
C1
L
2
I
O+
R V
O+
V
O–
I
O–
L
12
L
2
i
L12
D
10
C
15
V
C1
D
24
D
23
D
22
D
21
i
L11
L
11
C
12
L
13
C
13
C
14
V
C11
D
14
D
13
D
12
D
11
D
3
L
3
C
4
D
5
L
4
C
5
L
5
D
7
D
0
C
2
i
L2
C
O
C
11
C
10
R
1
i
in+
S
FIGURE 6.43 D/Oquadruplelift circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 203. With permission.)
up. Current i
C2
(t), i
C3
(t), i
C4
(t), and i
C5
(t) are exponential functions. They have large values
at the moment of power switching on, but they are small because v
C3
= v
C4
= v
C5
= V
I
and
v
C2
= V
O+
in steady state.
The output voltage and current are
V
O+
=
4
1 −k
V
I
and I
O+
=
1 −k
4
I
I+
.
The voltage transfer gain in the continuous mode is
M
Q+
=
V
O+
V
I
=
4
1 −k
. (6.197)
Other average voltages: V
C1
=
3 +k
1 −k
V
I
; V
C3
= V
C4
= V
C5
= V
I
; V
CO
= V
C2
= V
O
.
Other average currents: I
L2
= I
O+
; I
L1
= I
L3
= I
L4
= I
L5
=
1
4
I
I+
=
1
1 −k
I
O+
.
Current variations: ξ
1+
= ζ
+
=
k(1 −k)R
2M
Q
f L
=
k
M
2
Q
2R
f L
; ξ
2+
=
k
16
1
f
2
C
2
L
2
;
Voltage Lift Converters 257
χ
1+
=
k
M
2
Q
2R
f L
3
; χ
2+
=
k
M
2
Q
2R
f L
4
; χ
3+
=
k
M
2
Q
2R
f L
5
.
Voltage variations: ρ
+
=
2
(3 +2k)f C
1
R
; σ
1+
=
M
Q
2f C
2
R
;
σ
2+
=
M
Q
2f C
3
R
; σ
3+
=
M
Q
2f C
4
R
; σ
4+
=
M
Q
2f C
5
R
.
The variation ratio of output voltage V
C0
is
ε
+
=
k
128
1
f
3
C
2
C
0
L
2
R
. (6.198)
6.6.4.2 Negative Conversion Path
Capacitors C
12
, C
13
, C
14
, and C
15
performcharacteristics to lift the capacitor voltage V
C11
to
a level 4 times higher than the source voltage V
I
. L
13
, L
14
, and L
15
perform the function of
ladder joints to link the four capacitors C
12
, C
13
, C
14
, and C
15
, and lift the output capacitor
voltage V
C11
up. Currents i
C12
(t), i
C13
(t), i
C14
(t), and i
C15
(t) are exponential functions. They
have large values at the moment of power switching on, but they are small because v
C12
=
v
C13
= v
C14
= v
C15
∼
= V
I
in the steady state.
The output voltage and current are
V
O−
=
4
1 −k
V
I
and I
O−
=
1 −k
4
I
I−
.
The voltage transfer gain in the continuous mode is
M
Q−
=
V
O−
V
I
=
4
1 −k
. (6.199)
From Equations 6.197 and 6.199, we deﬁne M
Q
= M
Q+
= M
Q−
. The curve of M
Q
versus k
is shown in Figure 6.44.
Other average voltages: V
C10
= V
O−
; V
C12
= V
C13
= V
C14
= V
C15
= V
I
.
Other average currents: I
L12
= I
O−
; I
L11
= I
L13
= I
L14
= I
L15
=
1
1 −k
I
O−
.
Current variation ratios: ζ
−
=
k
M
2
Q
2R
1
f L
11
; ξ
−
=
k
16
1
f
2
CL
12
;
χ
1−
=
k(1 −k)
2M
Q
R
1
f L
13
; χ
2−
=
k(1 −k)
2M
Q
R
1
f L
14
; χ
3−
=
k(1 −k)
2M
Q
R
1
f L
15
.
258 Power Electronics
40
32
24
M
Q
16
8
0
0 0.2 0.4 0.6
k
0.8 1
FIGURE 6.44 Voltage transfer gain M
Q
versus k. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 205. With permission.)
Voltage variation ratios: ρ
−
=
k
2
1
f C
11
R
1
; σ
1−
=
M
Q
2
1
f C
12
R
1
;
σ
2−
=
M
Q
2
1
f C
13
R
1
; σ
3−
=
M
Q
2
1
f C
14
R
1
; σ
4−
=
M
Q
2
1
f C
15
R
1
.
The variation ratio of output voltage V
C10
is
ε
−
=
k
128
1
f
3
C
11
C
10
L
12
R
1
. (6.200)
6.6.4.3 Discontinuous Conduction Mode
In order to obtain the mirrorsymmetrical D/O voltages, we purposely select L
1
= L
11
and
R = R
1
. Therefore, we may deﬁne
V
O
= V
O+
= V
O−
, M
Q
= M
Q+
= M
Q−
=
V
O
V
I
=
4
1 −k
,
z
N
= z
N+
= z
N−
, and ζ = ζ
+
= ζ
−
.
The freewheeling diode currents i
D0
and i
D10
become zero during switchoff before the
next switchon period. The boundary between CCM and DCM is
ζ ≥ 1
or
M
Q
≤
_
2kz
N
. (6.201)
Voltage Lift Converters 259
60
50
40
30
20
0.8
0.5
0.33
0.1
k = 0.9
10
8
6
4
54 64 100 250
Discontinuous mode
Continuous mode
R/fL
M
Q
889
FIGURE 6.45 The boundary between continuous and discontinuous modes and the output voltage versus the
normalized load z
N
= R/f L (D/O quadruplelift circuit). (Reprinted from Luo, F. L. and Ye, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 206. With permission.)
This boundary curve is shown in Figure 6.45. It can be seen that it has a minimum value
of M
Q
that is equal to 6.0, corresponding to k = 1/3.
In the discontinuous mode, the currents i
D0
and i
D10
exist in the period between kT and
[k +(1 −k)m
Q
]T, where m
Q
is the ﬁlling efﬁciency, that is,
m
Q
=
1
ζ
=
M
2
Q
2kz
N
. (6.202)
Considering Equation 6.201, therefore, 0 < m
Q
< 1. Since the current i
D0
becomes zero at
t = t
1
= kT +(1 −k)m
Q
T, for the currents i
L1
, i
L3
, i
L4
, and i
L5
, we have
4kTV
I
= (1 −k)m
Q
T(V
C1
−3V
I
)
or
V
C1
=
_
3 +
4k
(1 −k)m
Q
_
V
I
=
_
3 +k
2
(1 −k)
z
N
2
_
V
I
with
_
2kz
N
≥
4
1 −k
. (6.203)
Therefore, the P/O voltage in the DCM is
V
O+
= V
C1
+V
I
=
_
4 +
4k
(1 −k)m
Q
_
V
I
=
_
4 +k
2
(1 −k)
z
N
2
_
V
I
with
_
2kz
N
≥
4
1 −k
.
(6.204)
Because inductor current i
L11
= 0 at t = t
1
,
V
L13−off
= V
L14−off
= V
L15−off
=
k
(1 −k)m
Q
V
I
.
260 Power Electronics
Since the current i
D10
becomes zero at t = t
1
= kT +(1 −k)m
Q
T, for the current i
L11
, we
have
kTV
I
= (1 −k)m
Q
−T(V
C11
−4V
I
−V
L13−off
−V
L14−off
−V
L15−off
).
So, with
V
C11
=
_
4 +
4k
(1 −k)m
Q
_
V
I
=
_
4 +k
2
(1 −k)
z
N
2
_
V
I
with
_
2kz
N
≥
4
1 −k
. (6.205)
For the current i
L12
, we have kT(V
I
+V
C15
−V
O−
) = (1 −k)m
Q
T(V
O−
−2V
I
−V
L13−off
−
V
L14−off
−V
L15−off
).
Therefore, the N/O voltage in the DCM is
V
O−
=
_
4 +
4k
(1 −k)m
Q
_
V
I
=
_
4 +k
2
(1 −k)
z
N
2
_
V
I
with
_
2kz
N
≥
4
1 −k
. (6.206)
So V
O
= V
O+
= V
O−
= [4 +k
2
(1 −k)(z
N
/2)]V
I
, that is, the output voltage linearly
increases as the load resistance R increases. It can be seen that the output voltage increases
as the load resistance R increases, as shown in Figure 6.45.
6.6.5 Summary
6.6.5.1 Positive Conversion Path
Fromthe analysis and calculation in previous sections, the common formulae for all circuits
can be obtained:
M =
V
O+
V
I
=
I
I+
I
O+
; z
N
=
R
f L
; R =
V
O+
I
O+
;
L =
L
1
L
2
L
1
+L
2
for the elementary circuit only;
L = L
1
for other lift circuits.
Current variations: ξ
1+
=
1 −k
2M
E
R
f L
1
and ξ
2+
=
k
2M
E
R
f L
2
for the elementary
circuit only;
ξ
1+
= ζ
+
=
k(1 −k)R
2Mf L
and ξ
2+
=
k
16
1
f
2
C
2
L
2
for other lift circuits;
ζ
+
=
k(1 −k)R
2Mf L
; χ
j+
=
k
M
2
R
f L
j+2
, j = 1, 2, 3, . . . .
Voltage Lift Converters 261
Voltage variations: ρ
+
=
k
2f C
1
R
; ε
+
=
k
8M
E
1
f
2
C
0
L
2
for the elementary circuit only;
ρ
+
=
M
M −1
1
2f C
1
R
; ε
+
=
k
128
1
f
3
C
2
C
0
L
2
R
for other lift circuits;
σ
1+
=
k
2f C
2
R
; σ
j+
=
M
2f C
j+1
R
, j = 2, 3, 4, . . . .
6.6.5.2 Negative Conversion Path
Fromthe analysis and calculation in previous sections, the common formulae for all circuits
can be obtained:
M =
V
O−
V
I
=
I
I−
I
O−
; z
N−
=
R
1
f L
11
; R
1
=
V
O−
I
O−
.
Current variation ratios: ζ
−
=
k(1 −k)R
1
2Mf L
11
; ξ
−
=
k
16f
2
C
11
L
12
; χ
j−
=
k(1 −k)R
1
2Mf L
j+2
,
j = 1, 2, 3, . . . .
Voltage variation ratios: ρ
−
=
k
2f C
11
R
1
; ε
−
=
k
128f
3
C
11
C
10
L
12
R
1
; σ
j−
=
M
2fC
j+11
R
1
,
j = 1, 2, 3, 4, . . . .
6.6.5.3 Common Parameters
Usually, we select the loads R = R
1
, L = L
11
, so that we obtain z
N
= z
N+
= z
N−
. In order to
write common formulae for the boundaries between continuous and discontinuous modes
and output voltage for all circuits, the circuits can be numbered. The deﬁnition is that
subscript j = 0 denotes the elementary circuit, 1 the selflift circuit, 2 the relift circuit, 3 the
triplelift circuit, 4 the quadruplelift circuit, and so on.
The voltage transfer gain is
M
j
=
k
h(j)
[j +h(j)]
1 −k
, j = 0, 1, 2, 3, 4, . . . .
The characteristics of output voltage of all circuits are shown in Figure 6.46.
The freewheeling diode current’s variation is given by
ζ
j
=
k
[1+h(j)]
M
2
j
j +h(j)
2
z
N
.
The boundaries are determined by the condition:
ζ ≥ 1
or
k
[1+h(j)]
M
2
j
j +h(j)
2
z
N
≥ 1, j = 0, 1, 2, 3, 4, . . . .
262 Power Electronics
120
100
80
50
30
10
0 0.2
(i)
(ii)
(iv)
(iii)
(v)
0.4 0.6
Conduction duty (k)
O
u
t
p
u
t
v
o
l
t
a
g
e
,
V
O
,
V
0.8 1
FIGURE 6.46 Output voltages of all D/O Luoconverters (V
I
= 10 V). (i) Quadruplelift circuit; (ii) triplelift
circuit; (iii) relift circuit; (iv) selflift circuit; and (v) elementary circuit. (Reprinted fromLuo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 211. With permission.)
Therefore, the boundaries between continuous and discontinuous modes for all circuits are
M
j
= k
(1+h(j))/2
_
j +h(j)
2
z
N
, j = 0, 1, 2, 3, 4, . . . .
The ﬁlling efﬁciency is
m
j
=
1
ζ
j
=
M
2
j
k
[1+h(j)]
2
j +h(j)
1
z
N
, j = 0, 1, 2, 3, 4, . . . .
The output voltage in the discontinuous mode for all circuits is
V
O−j
=
_
j +k
[2−h(j)]
1 −k
2
z
N
_
V
I
,
where
h(j) =
_
0 if j ≥ 1,
1 if j = 0,
j = 0, 1, 2, 3, 4 . . . ;
where h(j) is the Hong function.
The boundaries between continuous anddiscontinuous modes of all circuits are shown in
Figure 6.47. The curves of all M versus z
N
suggest that the continuous mode area increases
fromM
E
via M
S
, M
R
, andM
T
to M
Q
. The boundary of the elementary circuit is a monorising
curve, but other curves are not monorising. There are minimum values of the boundaries
of other circuits, which for M
S
, M
R
, M
T
, and M
Q
correspond at k = 1/3.
Voltage Lift Converters 263
Continuous mode
Discontinuous mode
Normalised load (z
N
= R/fL)
44.5
0.5
1.5
3
V
o
l
t
a
g
e
t
r
a
n
s
f
e
r
g
a
i
n
(
M
)
4.5
6
13.5
M
E
M
S
M
R
M
T
M
Q
27 54 40.5
FIGURE 6.47 Boundaries between continuous and discontinuous modes of all D/O Luoconverters. (Reprinted
fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor &Francis Group LCC, p. 212. With
permission.)
6.7 VL CúkConverters
The proposed N/O Cúkconverters were developed from the Cúkconverter, as shown in
Figure 5.32. They are as follows:
• Elementary selflift circuit
• Developed selflift circuit
• Relift circuit
• Multiplelift circuits (e.g., triplelift and quadruplelift circuits).
These converters perform positive to negative DC–DC voltage is increasing conversion
with higher voltage transfer gains, power density, small ripples, high efﬁciency, and cheap
topology in a simple structure [17–19].
6.7.1 Elementary SelfLift Cúk Circuit
The elementaryselflift circuit is derivedfromthe Cúkconverter byaddingthe components
(D
1
−C
1
). The circuit diagram is shown in Figure 6.48. The lift circuit consists of L
1
D
1
C
1
,
and it is a basic VL cell. When switch S turns on, D
1
is on and D
o
is off. When switch S
turns off, D
1
is off and D
o
is on. The capacitor C
1
performs characteristics to lift the output
capacitor voltage V
Co
to a level higher than the capacitor voltage V
Cs
.
264 Power Electronics
C
s
i
L
i
in
V
in
i
Cs
D
f
D
1
L
1
C
1
C
0
i
O
V
O
R
S
L
+
+ +
+
–
–
– –
FIGURE 6.48 Elementary selflift Cúkconverter.
In the steady state, the average voltage across inductor L
1
over a period is zero. Thus
V
C1
= V
Co
= V
O
.
During the switchon period, the voltages across capacitor C
1
is equal to the voltage
across C
s
. Since C
s
and C
1
are sufﬁciently large, we have V
C1
= V
Cs
= V
O
.
The inductor current i
L
increases during switchon and decreases during switch
off. The corresponding voltages across L are V
in
and −(V
Cs
−V
in
). Therefore, kTV
in
=
(1 −k)T(V
Cs
−V
in
).
Hence, the voltage transfer gain of the elementary selflift circuit is
M
S
=
V
O
V
in
=
1
1 −k
. (6.207)
6.7.2 Developed SelfLift Cúk Circuit
The developed selflift circuit is derived fromthe elementary selflift Cúk circuit by adding
the components (D
o
−S
1
) and redesigning the connection of L
1
. Static switches S and S
1
are switched on simultaneously. The circuit diagramis shown in Figure 6.49. The lift circuit
consists of C
1
L
1
S
1
D
1
. When switches S and S
1
turn on, D
1
is on and D
f
and D
o
are
off. When S and S
1
turn off, D
1
is off and D
f
and D
o
are on. The capacitor C
1
performs
characteristics to lift the output capacitor voltage V
CO
to a level higher than the capacitor
voltage V
Cs
.
During the switchon period, the voltage across capacitor C
1
is equal to the voltage across
C
s
. Since C
s
and C
1
are sufﬁciently large, we have V
C1
= V
Cs
= (1/(1 −k))V
in
.
D
1 C
s
i
L
i
Cs
i
in
V
in
+
–
+
+
+
–
–
–
C
1
S
1
D
O
C
0 R
i
O
V
O
L
1
L
D
f
S
FIGURE 6.49 Developed selflift Cúk circuit.
Voltage Lift Converters 265
The inductor current i
L1
increases during switchon and decreases during switchoff. The
corresponding voltages across L are V
Cs
and −(V
O
−V
C1
). Therefore,
kTV
Cs
= (1 −k)T(V
O
−V
C1
).
Hence, the voltage transfer gain of the developed selflift circuit is
M
S
=
V
O
V
in
=
1
(1 −k)
2
. (6.208)
6.7.3 ReLift Cúk Circuit
The relift circuit is derived from the developed selflift Cúk circuit by adding the compo
nents (D
2
C
2
L
2
D
3
). Static switches S and S
1
are switched on simultaneously. The circuit
diagram is shown in Figure 6.50. The lift circuit consists of L
1
D
1
C
1
D
2
C
2
L
2
D
3
S
1
and it
can be divided into two basic VL cells. When switches S and S
1
turn on, D
1
, D
2
, and D
3
are
on, and D
O
is off. When S and S
1
turn off, D
1
, D
2
, and D
3
are off and D
O
is on. Capacitors
C
1
and C
2
perform characteristics to lift the output capacitor voltage V
Co
to a level 2 times
higher than the capacitor voltage V
Cs
. L
2
performs the function of a ladder joint to link the
two capacitors C
1
and C
2
and lift V
Co
. To avoid the abnormal phenomena of diodes during
switchoff, it is assumed that L
1
and L
2
are the same to simplify the theoretical analysis.
During the switchon period, both the voltages across capacitors C
1
and C
2
are equal to
the voltage across C
s
. Since C
s
, C
1
, and C
2
are sufﬁciently large, we have
V
C1
= V
C2
= V
Cs
= V
in
=
1
1 −k
V
in
.
The voltage across L
1
is equal to V
Cs
during switchon. With the second voltage balance,
we have V
L1−off
= (k/1 −k)V
Cs
.
The inductor current i
L2
increases during switchon and decreases during switchoff. The
corresponding voltages across L
2
are V
Cs
and −(V
O
−V
C1
−V
C2
−V
L1−off
). Therefore,
kTV
Cs
= (1 −k)T(V
O
−V
C1
−V
C2
−V
L1−off
).
Hence, the voltage transfer gain of the relift circuit is
M
R
=
V
O
V
in
=
2
(1 −k)
2
. (6.209)
C
s
i
L
V
in
i
in
+
+
–
+
+
+
–
–
–
–
D
1
C
1
L
1
D
2
C
2
L
2
i
O
D
O
D
3
S
1
C
0
V
O R
D
f
S
L
i
Cs
FIGURE 6.50 Relift Cúk circuit.
266 Power Electronics
6.7.4 MultipleLift Cúk Circuit
It is possible to construct a multiplelift circuit by adding the components (D
2
C
2
L
2
D
3
).
Assuming that there are n VL cells, the generalized representation of multiplelift circuits
is shown in Figure 6.51. Only two synchronous switches S and S
1
are required for each
complex multiplelift circuit, which simpliﬁes the control scheme and decreases the cost
signiﬁcantly. Hence, each circuit has two switches, (n +1) inductors, (n +1) capacitors, and
(2n −1) diodes. It is noted that all inductors existing in the VL cells are the same here for
the reasons explained in the relift circuit. All the capacitors are sufﬁciently large. From the
foregoing analysis and calculation, the general formulae for all multiplelift circuits can be
obtained according to similar steps.
The generalized voltage transfer gain is
M =
n
(1 −k)
h(n)
, n = 1, 2, 3, 4, . . . , (6.210)
where
h(n) =
_
1 selflift
2 others
If the generalized circuit possesses three VL cells, it is termed the triplelift circuit. If the
generalized circuit possesses four VL cells, it is termed the quadruplelift circuit.
6.7.5 Simulation and Experimental Veriﬁcation of an Elementary
and a Developed SelfLift Circuit
Referring to Figures 6.48 and 6.49, we set these two circuits to have the same condi
tions: V
in
= 10 V, R = 100 Ω, L = 1 mH, L
1
= 500 μH, C
s
= 110 μF, C
1
= 22 μF, C
O
= 47 μF,
k = 0.5, and f = 100 kHz. According to Equation 6.207, the theoretical value V
O
of the ele
mentary selflift circuit is equal to 20 V. According to Equation 6.208, the theoretical value
V
O
of the developedselflift circuit is equal to 40 V. The simulationresults of Psimare shown
in Figure 6.52, where curve 1 is for the v
O
of the elementary selflift circuit and curve 2 is for
the v
O
of the developed selflift circuit. The steadystate values in the simulation identically
match the theoretical analysis.
Similar parameters are chosen to construct the corresponding testing hardware circuits. A
single nchannel MOSFETis usedinthe elementaryselflift circuit. Twonchannel MOSFETs
are used in the developed selflift circuit. The corresponding experimental curves in the
i
in
D
1
C
1
D
2
L
1
i
L
C
s
S
D
f
+
–
–
C
j
L
j
C
n L
n
V
O
i
O
R
D
0
S
1
C
0
+
+
–
–
+
–
D
2n–1
D
2j–1
D
2j
i
Cs L
V
in +
–
+
1
st
cell
j
th
cell
n
th
cell
FIGURE 6.51 Generalized representation of N/O Cúkconverters.
Voltage Lift Converters 267
20.00
V
O1
V
O2
0.00
–20.00
–40.00
–60.00
–80.00
0.00 20.00 10.00 40.00 30.00
Time (ms)
60.00 50.00
2
1
FIGURE 6.52 Simulation results of the elementary and developed selflift circuits.
steady state are shown in Figure 6.53. The curve shown in Channel 1 with 10 V/Div cor
responds to the output voltage of the elementary selflift circuit, which is about 19 V. The
curve shown in Channel 2 with 10 V/Div corresponds to the output voltage of the devel
oped selflift circuit, which is about 37 V. Considering the effects caused by the parasitic
parameters, we can see that the measured results are very close to the theoretical analysis
and simulation results.
6.8 VL SEPICs
The proposed P/O SEPICs are developed from SEPIC as shown in Figure 5.33. They
are as follows:
1 2 1 Stop
2
1
10.0V 10.0V 1.00m/s 0.00s
FIGURE 6.53 Experimental results of the elementary and developed selflift circuits.
268 Power Electronics
• Selflift circuit
• Relift circuit
• Multiple circuits (e.g., triplelift and quadruplelift circuits).
These converters perform positivetopositive DC–DC voltageincreasing conversion
with higher voltage transfer gains, power density, small ripples, high efﬁciency, and cheap
topology in a simple structure [18–21].
6.8.1 SelfLift SEPIC
The selflift circuit is derived from the SEPIC converter by adding the components D
1
C
1
.
The circuit diagram is shown in Figure 6.54. The lift circuit consists of L
1
D
1
C
1
and is a
basic VLcell. When switch S turns on, D
1
is on and D
o
is off. When switch S turns off, D
1
is
off and D
o
is on. Capacitor C
1
performs characteristics to lift the output capacitor voltage
V
Co
to a level higher than the capacitor voltage V
Cs
.
In the steady state, the average voltage across inductor L over a period is zero. Thus
V
Cs
= V
in
.
During the switchon period, the voltage across capacitor C
1
is equal to the voltage across
C
s
. Since C and C
1
are sufﬁciently large, we have V
C1
= V
Cs
= V
in
.
The inductor current i
L
increases during switchon and decreases during switchoff. The
corresponding voltages across L are V
Cs
and −(V
Co
−V
C1
−V
in
+V
Cs
). Therefore,
kTV
Cs
= (1 −k)T(V
Co
−V
C1
−V
in
+V
Cs
).
Hence, the voltage transfer gain of the selflift circuit is
M
S
=
V
O
V
in
=
1
1 −k
. (6.211)
6.8.2 ReLift SEPIC
The relift circuit is derived fromthe selflift circuit by adding the components L
2
D
2
C
2
S
1
.
Static switches S andS
1
are switchedonsimultaneously. The circuit diagramandequivalent
circuits during switchon and switchoff are shown in Figure 6.55. The lift circuit consists of
L
1
D
1
C
1
L
2
D
2
C
2
S
1
and can be divided into two basic VL cells. When switches S and S
1
C
s
i
L
i
L1
i
in
V
in
V
O
i
C0
C
0
i
O
L
1
L
S
D
1
D
0 C
1
i
C1
i
Cs
+ +
+
Pump
+
+
– – –
– –
R
FIGURE 6.54 Selflift SEPIC.
Voltage Lift Converters 269
i
Cs i
L
i
in
V
in
L
S
V
O
i
O
C
0
D
1
Pump
C
1
C
s
L
1
i
L1
i
C1
L
2
D
2
D
0
i
C2
C
2
S
1
i
L2
+
+
+
+
–
–
–
–
i
C0
R
–
+ +
–
FIGURE 6.55 Relift SEPIC.
turn on, D
1
and D
2
are on and D
o
is off. When S and S
1
turn off, D
1
and D
2
are off and D
o
is
on. Capacitors C
1
and C
2
perform characteristics to lift the output capacitor voltage V
Co
to
a level 2 times higher than the capacitor voltage V
Cs
. L
2
performs the function of a ladder
joint to link the two capacitors C
1
and C
2
and lift V
Co
. To avoid the abnormal phenomena
of diodes during switchoff [11], it is assumed that L
1
and L
2
are the same, which simpliﬁes
the theoretical analysis.
In steady state, both the average voltages across inductors L and L
1
over a period equal
zero. Thus V
Cs
= V
in
.
During the switchon period, both the voltages across capacitors C
1
and C
2
are equal to
the voltage across C
s
. Since C, C
1
, and C
2
are sufﬁciently large, we have
V
C1
= V
C2
= V
Cs
= V
in
.
The voltage across L
1
is equal to V
Cs
during switchon. With the second voltage balance,
we have V
L1−off
= (k/(1 −k))V
in
.
The inductor current i
L2
increases during switchon and decreases during switchoff. The
corresponding voltages across L
2
are V
Cs
and −(V
Co
−V
C1
−V
C2
−V
L1−off
). Therefore,
kTV
Cs
= (1 −k)T(V
Co
−V
C1
−V
C2
−V
L1−off
).
Hence, the voltage transfer gain of the relift circuit is
M
R
=
V
O
V
in
=
2
1 −k
. (6.212)
6.8.3 MultipleLift SEPICs
It is possible to construct a multiplelift circuit by adding the components L
2
D
2
C
2
S
1
.
Assuming that there are n VL cells, the generalized representation of multiplelift circuits
is shown in Figure 6.56.
All future active switches can be replaced by passive diodes. According to this principle,
only two synchronous switches S and S
1
are required for each complex multiplelift circuit,
which simpliﬁes the control scheme and decreases the cost signiﬁcantly. Hence, each circuit
has two switches, (n+1) inductors, (n+1) capacitors, and (2n−1) diodes. It is noted that all
270 Power Electronics
D
2n–2
D
2j–1
D
2j–2
C
j
L
j
D
3
2
n
d
c
e
l
l
1
st
cell
j
t
h
c
e
l
l
n
t
h
c
e
l
l
C
2 D
2
L
2
i
L
S
1
C
1
L
1
C
s
i
in
V
in S
L
D
1
C
0
V
0
i
C0
R
D
0
C
n
+
+
+
+ +
+ +
+
–
–
–
–
– –
– –
L
n
i
O
FIGURE 6.56 Multilift SEPIC.
inductors existing in the VL cells are the same here for the reasons explained in the relift
circuit. All the capacitors are sufﬁciently large. Fromthe foregoing analysis and calculation,
the general formulae for all multiplelift circuits can be obtained according to similar steps.
The generalized voltage transfer gain is
M =
n
1 −k
, n = 1, 2, 3, 4, . . . . (6.213)
If the generalized circuit possesses three VL cells, it is termed the triplelift circuit. If the
generalized circuit possesses four VL cells, it is termed the quadruplelift circuit.
6.8.4 Simulation and Experimental Results of a ReLift SEPIC
The circuit parameters for simulation are V
in
= 10 V, R = 100 Ω, L = 1 mH, L
1
= L
2
=
500 μH, C
s
= 110 μF, C
1
= C
2
= 22 μF, C
0
= 110 μF, and k = 0.6. The switching frequency f
is 100 kHz. According to Equation 6.212, we obtain the theoretical value V
O
, which is equal
to 50 V. The simulation results of Psim are shown in Figure 6.57, where curves 1–3 are for
v
O
, i
L2
, and i
L1
, respectively. The steadystate performance in the simulation identically
matches the theoretical analysis.
Similar parameters are chosen to construct a testing hardware circuit. Two nchannel
MOSFETs 2SK2267 are selected. We obtained the output voltage value of V
O
= 46.2 V
Voltage Lift Converters 271
80.00
V
O
i
L1
i
L2
60.00
40.00
20.00
0.00
–20.00
0.00 20.00 40.00
Time (ms)
60.00 80.00
3
2
1
FIGURE 6.57 Simulation result of a relift SEPIC.
(shown in Channel 1 with 10 V/Div) and the capacitor value of V
Cs
= 9.9 V (shown in
Channel 1 with 10 V/Div). The corresponding experimental curves in the steady state are
shown in Figure 6.58. The practical output voltage is smaller than the theoretical values
due to the effects caused by parasitic parameters. It is seen that the measured results are
very close to the theoretical analysis and simulation results.
6.9 Other D/O VoltageLift Converters
For all the abovementioned converters, each topology is divided into two sections: the
source section including voltage source, inductor L, and active switch S, and the pump
1 2 1 Stop
2
1
10.0V 10.0V 1.00m/s 0.00s
FIGURE 6.58 Experimental result of a relift SEPIC.
272 Power Electronics
L
S
C
s+
D
0
C
0+
C
0–
L
1–
C
s–
D
f
R
R
V
in +
– L
1+
V
O
i
O
V
O
i
O
FIGURE 6.59 Novel elementary D/O converter.
section consisting of the rest of the components. Each topology can be considered as a
special cascade connection of these two sections.
We compare the SEPIC converter to the Cúkconverter; both converters have the same
source sections and the same voltage transfer gains with opposite polarities. Hence, a series
of novel D/O converters based on the SEPIC and Cúkconverters can be constructed by
combining the two converters at the input side. They are the elementary circuit, the selflift
circuit, and the corresponding enhanced series [18,19].
6.9.1 Elementary Circuit
Combining the prototypes of the SEPIC and Cúkconverters, we obtain the elementary
circuit of novel D/O converters, which is shown in Figure 6.59. The positive conversion
path is the same as that of the SEPICconverter. The negative conversion path is the same as
that of the Cúkconverter. Hence, from the foregoing analysis and calculation, the voltage
transfer gains are obtained as
M
E+
=
V
O+
V
in
=
k
1 −k
,
M
E−
=
V
O−
V
in
= −
k
1 −k
.
(6.214)
6.9.2 SelfLift D/O Circuit
The selflift circuit is a derivative of the elementary circuit shown in Figure 6.60.
The positive conversion path is the same as that of the selflift SEPIC converter. The
negative conversion path is the same as that of the selflift Cúkconverter. Hence, from the
foregoing analysis and calculation, the voltage transfer gains are obtained as
M
S+
=
V
O+
V
in
=
1
1 −k
,
M
S−
=
V
O−
V
in
= −
1
1 −k
.
(6.215)
Voltage Lift Converters 273
C
1+
S
L
V
in +
–
C
s+
D
1+
C
1–
L
1–
D
1–
C
s–
D
f
C
0+
C
0–
R
R
D
0
V
O
i
O
V
O
i
O
FIGURE 6.60 Novel selflift D/O converter.
6.9.3 Enhanced Series D/O Circuits
Since the positive and negative conversion paths share a common source section that can be
regarded as a boost converter circuit, we can construct the corresponding enhanced series
using the VL technique. A series of novel boost circuits is applied into the source section,
which transfers much more energy to C
s+
and C
s−
in each cycle and increases V
Cs+
and
V
Cs−
stagebystage along geometric progression.
As shown in Figure 6.61, the source section is redesigned by adding the components
L
s1
D
s1
D
s2
C
s1
, which forma basic VLcell and are expressed by boost
1
. The newly derived
topology provides a single boost circuit enhancement using supplementary components.
When switch S turns on, D
s2
is on and D
s1
is off. When switch S turns off, D
s2
is off and
D
s1
is on. Capacitor C
s1
performs characteristics to lift the source voltage V
in
. The energy is
transferred to C
s+
and C
s−
in each cycle from C
s1
and increases V
Cs+
and V
Cs−.
We obtain
V
Cs+
= V
Cs1
=
1
1 −k
V
in
,
V
Cs−
=
1
1 −k
V
Cs1
=
1
(1 −k)
2
V
in
.
(6.216)
Therefore, from the foregoing analysis and calculation, the voltage transfer gains of this
enhanced D/O selflift DC–DC converters are
M
boost
1
−S+
=
V
O+
V
in
=
1
(1 −k)
2
,
M
boost
1
−S−
=
V
O−
V
in
= −
1
(1 −k)
2
.
(6.217)
Referring to Figure 6.61, it is possible to realize multiple boost circuits enhancement in
the source section by repeating the components L
s1
D
s1
D
s2
C
s1
stagebystage. Assuming
that there are n VLcells (denotedby boost
M
), the generalizedrepresentation of the enhanced
series for the D/O selflift DC–DC converter is shown in Figure 6.62. All circuits share the
same power switch S, which simpliﬁes the control scheme and decreases the cost signiﬁ
cantly. Hence, each circuit has one switch, (n +3) inductors, (n +5) capacitors, and (2n +4)
diodes. It is noted that all inductors existing in the VL cells are the same here for the same
reasons as explained in foregoing sections. All the capacitors are sufﬁciently large. The
274 Power Electronics
D
s1
D
s2
L
s2
V
in
+
–
C
s1
L
S
C
s+
C
s–
D
l–
L
l–
C
l–
C
0–
V
O
i
0
R
D
f
C
l+
D
l+
D
0
C
0+
R
V
O
i
0
FIGURE 6.61 Enhanced D/O selflift DC–DC converter (single boost circuit enhancement).
energy is transferred to C
s+
and C
s−
in each cycle from C
sn
, and increases by V
Cs+
and
V
Cs−.
We obtain
V
Cs+
= V
Csn
=
1
(1 −k)
n
V
in
,
V
Cs−
=
1
1 −k
V
Csn
=
1
(1 −k)
n+1
V
in
.
(6.218)
Therefore, fromthe foregoing analysis and calculation, the general voltage transfer gains
of enhanced D/O selflift DC–DC converters are
M
boost
M
−S+
=
V
O+
V
in
=
1
(1 −k)
n+1
,
M
boost
M
−S−
=
V
O−
V
in
= −
1
(1 −k)
n+1
.
(6.219)
Analogically, we can also develop a series of enhanced D/O elementary circuits using
the same source section. The general voltage transfer gains of enhanced D/O elementary
D
s1
L
sj
C
sj
+
–
C
sn
C
s–
C
s+
C
l+
D
0
D
l+
C
0+
C
0–
V
O
V
O
i
0
i
0
i
L
L
R
R
D
l–
D
f C
l–
L
l–
S
+
+
+
+
+
–
–
–
–
–
D
s(2j)
D
s(2j–1)
D
s(2n–1)
D
s(2n)
L
sn
D
s2
L
s1 V
in
–
+
–
+
1
st
cell j
th
cell n
th
cell
C
s1
FIGURE 6.62 Generalized representation of enhanced D/O selflift DC–DC converters (multiple boost circuits
enhancement).
Voltage Lift Converters 275
100.00
V
O+
V
O–
50.00
0.00
–50.00
–100.00
0.00 10.00 20.00
Time (ms)
30.00 40.00
2
1
FIGURE 6.63 Simulation result for an enhanced D/O selflift circuit (single boost circuit enhancement).
DC–DC converters are also given here for ready reference.
M
boost
M
−E+
=
V
O+
V
in
=
k
(1 −k)
n+1
,
M
boost
M
−E−
=
V
O−
V
in
= −
k
(1 −k)
n+1
.
(6.220)
6.9.4 Simulation and Experimental Veriﬁcation of an Enhanced D/O SelfLift Circuit
Referring to Figure 6.61, the circuit parameters for simulation are V
in
= 10 V, R = 100 Ω,
L
s1
= L = 1 mH, C
1+
= C
1−
= C
s1
= 22 μF, C
s+
= C
s−
= 110 μF, C
o+
= C
o−
= 47 μF, C
O
=
110 μF, k = 0.5, and f = 100 kHz. According to Equation 6.219, we obtain the theoretical
values of D/O voltages V
O+
and V
O−
, which are equal to 40 and −40 V, respectively. The
simulation results of Psim are shown in Figure 6.63, where curve 1 is for the v
O+
of the
positive conversion path and curve 2 is for the v
O−
of the negative conversion path. The
steadystate values in the simulation identically match the theoretical analysis.
Similar parameters are chosen to construct the testing hardware circuit. Only a single
nchannel MOSFET is used in the circuit. The corresponding experimental curves in the
steady state are shown in Figure 6.64. The curve shown in Channel 1 with 20 V/Div cor
responds to P/O v
O+
, which is about 37 V. The curve shown in Channel 2 with 20 V/Div
corresponds to N/O v
O−
, which is also about 37 V. Considering the effects caused by the
parasitic parameters, we can see that the measured results are very close to the theoretical
analysis and simulation results.
6.10 SC Converters
A switched capacitor is an improved component used in power electronics. Switched
capacitors can be used to construct a new type of DC–DC converter called the switched
276 Power Electronics
1
2 1 Stop
1
2
20.0V
20.0V 0.00s
1.00m/s
FIGURE 6.64 Experimental result for an enhanced D/O selflift circuit (single boost circuit enhancement).
capacitor DC–DC converter. Switched capacitors can be integrated into a power IC chip.
By using this manufacturing technology, we have the advantages of small size and low
power losses. Consequently, switchedcapacitor DC–DCconverters have a small size, a high
power density, a high power transfer efﬁciency, and a high voltage transfer gain [22–27].
Current is supplied to DC–DC converters by a DC voltage source. The input source
current can be continuous or discontinuous. In some converters such as buck converters
and buck–boost converters, the input current is discontinuous. This is called working in
the DICM. In other converters such as boost converters, the input current is continuous.
This is called working in the CICM. The VL technique can be applied to the switched
capacitor to construct DC/DC converters. The idea is that for converters to operate in
the DICM, switched capacitors can be charged with the source voltage and energy can be
stored during the input current discontinuous period (when the main switch is off). They
will join the conversion operation during the time the main switch is on, andtheir SEwill be
delivered through the DICMconverters to the load. These converters are called SCDC–DC
converters.
It is easy to construct SC DC–DC converters. Depending on how many switched capac
itors need to be used, they are called onestage SC converters, twostage SC converters,
threestage SCconverters, andnstage SCconverters. The corresponding circuits are shown
in Figures 6.65 through 6.67.
The onestage SC converter circuit is shown in Figure 6.65a. The input source voltage is
V
in
and the output voltage is V
O
. To simplify the description, we assume that the load is
resistive load R. The auxiliary switches S
1
and S
2
are switched on (the auxiliary switch S
3
is off) during the switchoff period. The switched capacitor C
1
is charged with the source
voltage V
in
. The auxiliary switches S
1
and S
2
are switched off, and the auxiliary switch S
3
is
on during the switchon period. The equivalent circuit is shown in Figure 6.65b. Therefore,
the equivalent input voltage suppliedto the DICMconverter is 2V
in
[28–32]. Inother words,
the equivalent input voltage has been lifted by using the switched capacitor.
Analogously, the circuit diagram of the twostage SC converter is shown in Figure 6.66a,
and the corresponding equivalent circuit when the main switch is on is shown in
Figure 6.66b. It supplies 3V
in
to the DICM converter. The equivalent input voltage is lifted
to a level 2 times higher than the supplied voltage V
in
.
Voltage Lift Converters 277
(a)
(b)
S
1
S
2
S
3
V
O
+
–
C
1
V
in
–
– +
+
DICM
Converter
R
C
1
DICM
Converter
V
in
–
+
+
–
V
O
+
–
R 2V
in
FIGURE 6.65 Onestage SC converter: (a) circuit diagram and (b) equivalent circuit during main switchon.
(b)
V
O
R
–
+
3V
in
DICM
Converter
C
2
–
+
C
1
–
+
V
in
–
+
(a)
S
5
C
2
S
2
C
1
V
in
S
6
V
O
R
–
– –
–
+
DICM
Converter
S
1
S
4
S
3
+ +
+
FIGURE 6.66 Twostage SC converter: (a) circuit diagram and (b) equivalent circuit during main switchon.
278 Power Electronics
(b)
(a)
S
9
C
3
S
5
S
8
C
2
S
2
C
1
V
in
S
6
V
O
R
–
– – –
–
+
DICM
Converter
V
O
R
–
+
C
3
4V
in
DICM
Converter
C
2
–
–
+
+
C
1
–
+
V
in
–
+
S
1 S
4
S
7
S
3
+
+ +
+
FIGURE 6.67 Threestage SC converter: (a) circuit and (b) equivalent circuit during main switchon.
The circuit diagram of the threestage SCconverter is shown in Figure 6.67a, and the
corresponding equivalent circuit when the main switch is on is shown in Figure 6.67b. It
supplies 4V
in
to the DICMconverter. The equivalent input voltage is lifted to a level 3 times
higher than the supplied voltage V
in
.
Several circuits will be introduced in this chapter:
• SC buck converters
• SC buck–boost converters
• SC P/O Luoconverters
• SC N/O Luoconverters.
Assume that the stage number is n and the voltage transfer gain of the DICM converter
is M. Then, in the ideal condition, we obtain the output voltage as
V
O
= (n +1)MV
in
. (6.221)
The ideal condition means that the voltage dropacross all switches anddiodes is zero and
the voltage across all the SCs has no dropdown when the main switch is off. This assump
tion is reasonable for the investigation. We will discuss the unideal condition operation in
Section 6.10.5 [33–38].
There is another advantage inthe input current being continuous. The input current of the
original DICMconverter is zero when the main switch is off. For example, the input current
of the onestage SC DC–DC converter ﬂows through the auxilliary switches S
1
and S
2
to
the charge capacitor C
1
when the main switch is off. For the nstage SC DC–DC converter,
each switched capacitor is discharged by the discharging current I
D
shown in Figure 6.68a.
The charging current of each switched capacitor should be I
d
in the switchoff period since
the average current of each switched capacitor is zero in the steady state. Therefore, the
source input average current should be
I
in
= (n +1)I
d
. (6.222)
Voltage Lift Converters 279
V
in
C
1
C
2
I
d
nI
d
V
in C
1
C
2
C
n
C
n
–
–
–
–
+
+
+
+
+ + +
– – – –
+
(a)
(b)
FIGURE 6.68 Discharging and charging currents of switchedcapacitors: (a) discharging current during switch
on and (b) charging current during switchoff.
6.10.1 OneStage SC Buck Converter
TheonestageSCbuckconverter is showninFigure6.69. ThemainswitchSandtheauxiliary
switch S
3
are on and off simultaneously. The auxiliary switches S
1
and S
2
are off and on
separately.
6.10.1.1 Operation Analysis
We assume that the converter works in the steady state and the switched capacitor C
1
is fully charged. The main switch S is on during the switchon period, and the auxiliary
S
1
V
1
S
3
S
D
L
S
2
V
in
C
1
i
L
i
O
V
O
R C
–
–
–
–
+
+
+
+
FIGURE 6.69 Onestage SC buck converter.
280 Power Electronics
switch S
3
is on simultaneously. The voltage V
1
is about 2V
in
when the main switch S is
on. This is the equivalent input voltage of 2V
in
for supply to the buck converter. Refer
ring to the buck converter voltage transfer gain M = k, we can easily obtain the output
voltage as
V
O
= 2kV
in
. (6.223)
Usingthis technique, we canobtainanoutput voltage that is higher thanthe input voltage
if the conduction duty cycle k is >0.5. The output voltage of the original buck converter is
always lower than the input voltage.
6.10.1.2 Simulation and Experimental Results
In order to verify the design and analysis, the simulation result is shown in Figure 6.70. The
simulation condition is that V
in
= 20 V, L = 10 mH, C = C
1
= 20 μF, f = 50 kHz, R = 100 Ω,
and conduction duty cycle k = 0.8. The voltage at the top end of the switched capacitor C
1
varies from 20 to 40 V. The output voltage V
O
= 32 V, which is the same as the calculation
result.
V
O
= 2kV
in
= 2 ×0.8 ×20 = 32 V. (6.224)
The experimental result is shown in Figure 6.71. The test condition is the same: V
in
=
20 V (Channel 1 in Figure 6.71), L = 10 mH, C = C
1
= 20 μF, f = 50kHz, R = 100 Ω and
conduction duty cycle k = 0.8. The output voltage V
O
= 32 V (Channel 2 in Figure 6.71),
which is the same as the calculation and simulation results.
50.00
V
1
V
in
V
O
40.00
30.00
20.00
10.00
0.00
18740.00 18750.00 18760.00
Time (μs)
18770.00 18780.00
FIGURE 6.70 Simulation result.
Voltage Lift Converters 281
1 2 1 Run
1 2
5.0V 5.0V 10.0m/s
FIGURE 6.71 Experimental result.
6.10.2 TwoStage SC Buck–Boost Converter
The twostage SC buck–boost converter is shown in Figure 6.72. The main switch S and the
auxiliary switches S
3
and S
6
are on and off simultaneously. The auxiliary switches S
1
, S
2
,
S
4
, and S
5
are off and on separately.
6.10.2.1 Operation Analysis
We assume that the converter works in the steady state and the switched capacitors C
1
and
C
2
are fully charged. The main switch S is on during the switchon period and the auxiliary
switches S
3
and S
6
are on simultaneously. The voltage V
1
is about 2V
in
and the voltage V
2
is about 3V
in
when the main switch S is on. This is the equivalent input voltage of 3V
in
for
supply to the buck–boost converter. Referring to the buck–boost converter voltage transfer
gain M = −k/(1 −k), we easily obtain the output voltage as
V
O
= −
3k
1 −k
V
in
. (6.225)
Using this technique, we effortlessly obtain a higher output voltage. For example, if
k = 0.5, the output voltage of the original buck–boost converter is equal to the input source
S
1 V
1
S
4 V
2
S
S
6
S
3
S
5
C
2
S
2
C
1
V
in
C
i
O
V
O
D
L
R
–
–
–
–
–
+
+
+ +
+
FIGURE 6.72 Twostage SC buck–boost converter.
282 Power Electronics
20.00
0.00
–20.00
–40.00
–60.00
–80.00
–100.00
60.00
50.00
40.00
30.00
20.00
10.00
16880.00 16890.00 16900.00
Time (μs)
16910.00 16920.00
V
1
V
n
V
2
V
o
FIGURE 6.73 Simulation result. (a) Waveforms of V
in
and V
O
and (b) waveforms of V
1
and V
2
.
voltage V
in
. The value of the output voltage of the twostage SC buck–boost converter is 6
times the value of the source voltage.
6.10.2.2 Simulation and Experimental Results
In order to verify the design, the simulation result is shown in Figure 6.73. The simulation
condition is that V
in
= 20 V, L = 10 mH, C = C
1
= C
2
= 20 μF, f = 50 kHz, R = 200 Ω, and
conduction duty cycle k = 0.6. The voltage at the top end of the switched capacitor C
1
in
Figure 6.72 varies from 20 to 40 V. The voltage at the top end of the switched capacitor C
2
varies from 20 to 60 V. The output voltage V
O
= −90 V, which is similar to the calculation
result.
V
O
= −
3k
1 −k
V
in
= −
3 ×0.6
1 −0.6
×20 = −90 V. (6.226)
The experimental result is shown in Figure 6.74. The test condition is that V
in
= 20 V
(Channel 1 in Figure 6.74), L = 10 mH, C = C
1
= C
2
= 20 μF, f = 50 kHz, R = 200 Ω and
conduction duty cycle k = 0.6. The output voltage V
O
= −90 V (Channel 2 in Figure 6.74),
which is similar to the simulation result and the calculation result.
6.10.3 ThreeStage SC P/O LuoConverter
The threestage SC P/O Luoconverter is shown in Figure 6.75. The main switch S and the
auxiliary switches S
3
, S
6
, and S
9
are on and off simultaneously. The auxiliary switches S
1
,
S
2
, S
4
, S
5
, S
7
, and S
8
are off and on separately.
Voltage Lift Converters 283
1 2 1 Run
1 2
20V 20V 10.0m/s
FIGURE 6.74 Experimental result.
6.10.3.1 Operation Analysis
We assume that the converter works in the steady state, and the switched capacitors C
1
,
C
2
, and C
3
are fully charged. The main switch S is on during the switchon period, and the
auxiliary switches S
3
, S
6
, and S
9
are on simultaneously. The voltage V
1
is about 2V
in
, the
voltage V
2
is about 3V
in
, andthe voltage V
3
is about 4V
in
when the main switch S is on. This
is the equivalent input voltage of 4V
in
for supply to the P/O Luoconverter. Referring to
the P/OLuoconverter voltage transfer gain M = k/(1 −k), we can easily obtain the output
voltage as
V
O
=
4k
1 −k
V
in
. (6.227)
6.10.3.2 Simulation and Experimental Results
In order to verify the design, the simulation result is shown in Figure 6.76. The simula
tion condition is that V
in
= 20 V, L = L
O
= 10 mH, C = C
1
= C
2
= C
3
= 20 μF, f = 50 kHz,
R = 400 Ω and conduction duty cycle k = 0.6. The voltage on the top end of the switched
capacitor C
1
varies from 20 to 40 V. The voltage on the top end of the switched capacitor C
2
varies from 20 to 60 V. The voltage on the top end of the switched capacitor C
3
varies from
S
1
V
1 S
4
V
2
S
7
S
9
V
3
C
3
S
3
S
5
S
8
C
2
S
2
C
1
V
in
S
6
S
C L
O
i
O
V
O
C
O
D
L
R
–
–
–
–
– –
–
+ +
+
+ +
+
+
FIGURE 6.75 Threestage SC P/O Luoconverter.
284 Power Electronics
140.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
100.00
80.00
60.00
40.00
20.00
0.00
56740.00 56750.00 56760.00
Time (μs)
V
1
V
n
V
O
V
2
V
3
56770.00 56780.00
FIGURE 6.76 Simulation result.
20 to 80 V. The output voltage V
O
= 120 V, which is the same as the calculation result.
V
O
=
4k
1 −k
V
in
=
4 ×0.6
1 −0.6
×20 = 120 V. (6.228)
The experimental result is shown in Figure 6.77. The test condition is the same: V
in
= 20 V
(Channel 1 in Figure 6.77), L = L
O
= 10 mH, C = C
O
= C
1
= C
2
= C
3
= 20 μF, f = 50 kHz,
R = 400 Ω and conduction duty cycle k = 0.6. The output voltage V
O
= 120 V (Channel 2
in Figure 6.77), which is the same as the simulation and calculation results.
1 2 1 Run
1 2
20V 20V
10.0m/s
FIGURE 6.77 Experimental result.
Voltage Lift Converters 285
S
1 V
1
S
4
V
2
S
7
S
9
V
3
C
3
S
3
S
5
S
8
C
2
S
2
C
1
V
in
S
6
S D
L
O
i
O
V
O C
O
C L
R
–
– –
– – –
–
+
+
+
+ + +
+
FIGURE 6.78 Threestage SC N/O Luoconverter.
6.10.4 ThreeStage SC N/O LuoConverter
The threestage SC N/O Luoconverter is shown in Figure 6.78. The main switch S and the
auxiliary switches S
3
, S
6
, and S
9
are on and off simultaneously. The auxiliary switches S
1
,
S
2
, S
4
, S
5
, S
7
, and S
8
are off and on separately.
6.10.4.1 Operation Analysis
We assume that the converter works in the steady state, and the switched capacitors C
1
,
C
2
, and C
3
are fully charged. The main switch S is on during the switchon period and the
auxiliary switches S
3
, S
6
, and S
9
are on simultaneously. The voltage V
1
is about 2V
in
, V
2
is
about 3V
in
, and V
3
is about 4V
in
when the main switch S is on. This is the equivalent input
voltage of 4V
in
for supply to the N/O Luoconverter. Referring to the N/O Luoconverter
voltage transfer gain M = −k/(1 −k), we can easily obtain the output voltage as
V
O
= −
4k
1 −k
V
in
. (6.229)
6.10.4.2 Simulation and Experimental Results
In order to verify the design, the simulation result is shown in Figure 6.79. The simulation
condition is that V
in
= 20 V, L = L
O
= 10 mH, C = C
1
= C
2
= C
3
= 20 μF, f = 50 kHz, R =
400 Ωandconductiondutycycle k = 0.6. The voltage at the topendof the switchedcapacitor
C
1
varies from 20 to 40 V. The voltage at the top end of the switched capacitor C
2
varies
from 20 to 60 V. The voltage at the top end of the switched capacitor C
3
varies from 20 to
80 V. The output voltage V
O
= −120 V, which is the same as the calculation result.
V
O
= −
4k
1 −k
V
in
= −
4 ×0.6
1 −0.6
×20 = −120 V. (6.230)
The experimental result is shown in Figure 6.80. The test condition is the same: V
in
= 20 V
(Channel 1 in Figure 6.80), L = L
O
= 10 mH, C = C
O
= C
1
= C
2
= C
3
= 20 μF, f = 50 kHz,
R = 400 Ω and conduction duty cycle k = 0.6. The output voltage V
O
= 120 V (Channel 2
in Figure 6.80), which is the same as the simulation and calculation results.
6.10.5 Discussion
In this section, we will discuss several factors of this technique for converter design
consideration and industrial applications.
286 Power Electronics
25.00
0.00
–25.00
–50.00
–75.00
–100.00
–125.00
–150.00
100.00
V
1
V
2
V
3
V
in
V
O
80.00
60.00
40.00
20.00
0.00
34860.00 34870.00 34880.00
Time (μs)
34890.00 34900.00
FIGURE 6.79 Simulation result.
6.10.5.1 Voltage Drop across Switched Capacitors
Referring to the waveformin Figures 6.72, 6.75, and6.78, we can clearly see the voltage drop
across the switched capacitors. For an nstage SC converter, n switched capacitors need to
be used. In the ideal condition, the total voltage across all switched capacitors should be
V
n
= nV
in
. (6.231)
1 2 1 Run
1 2
20V 20V 10.0m/s
FIGURE 6.80 Experimental result.
Voltage Lift Converters 287
If all switched capacitors have the same capacitance C, the equivalent capacitance in
the switchon period is C/n. We assume that the discharging current during the switchon
periodis a constant value I
d
, the conductionduty cycle is k, the switching frequency is f , and
the switchon period is kT = k/f . Then we calculate the voltage drop of the last switched
capacitor as
ΔV
n
=
1
C/n
kT
0
i
d
dt =
nkT
C
I
d
. (6.232)
The average current ﬂowing through switched capacitors in a period T is zero in the steady
state. The average input current from the source is I
in
= (n +1)I
D
. Current I
D
is the input
current of the DICM converter. If there are no energy losses inside the DICM converter, we
can obtain it as
I
in
V
in
= (n +1)I
d
V
in
= V
O
I
O
=
V
2
O
R
. (6.233)
Considering Equation 6.221, we have
I
d
=
V
O
(n +1)V
in
I
O
= MI
O
= M
V
O
R
, (6.234)
ΔV
n
=
nkT
C
I
d
=
nk
f C
MI
O
=
nkM
f C
V
O
R
. (6.235)
From Equation 6.235, we can see that the voltage drop is directly proportional to stages
n, duty cycle k, and output voltage V
O
. It is inversely proportional to switching frequency
f , capacitance C of the used switched capacitors, and load R. In order to reduce the voltage
drop for our design, one of the following ways can be used:
• Increase the switching frequency f
• Increase the capacitance C
• Increase the load R
• Decrease the duty cycle k.
Correspondingly, the voltage drop across each switched capacitor is
ΔV
each
=
ΔV
n
n
=
k
f C
I
d
=
kM
f C
V
O
R
. (6.236)
6.10.5.2 Necessity of the Voltage Drop across SwitchedCapacitors and Energy Transfer
Voltage drops across switched capacitors are necessary for energy transfer from the source
to the DICM converter. Switched capacitors absorb energy from the supply source during
the switchoff periodandrelease the SEto the DICMconverter during the switchonperiod.
In the steady state, the energy transferred by the switched capacitors in a period T is
ΔE =
1
2
C
n
_
V
2
n
−(V
n
−ΔV
n
)
2
_
=
C
2n
_
2V
n
ΔV
n
−ΔV
2
n
_
=
C
2n
(2V
n
−ΔV
n
) ΔV
n
. (6.237)
288 Power Electronics
Considering that 2V
n
ΔV
n
, Equation 6.237 can be rewritten as
ΔE ≈
C
n
V
n
ΔV
n
. (6.238)
Substituting Equations 6.231 and 6.235 into Equation 6.238, the total power transferred by
the switched capacitors is
P = f ΔE =
f C
n
V
n
ΔV
n
=
f C
n
(nV
in
)
_
nkM
f C
I
O
_
= nkMV
in
I
O
. (6.239)
If we wouldlike toobtainthe power transferredtothe DICMconverter as high, increasing
the switching frequency f and capacitance C is necessary. From Equation 6.239, helpful
methods are the following:
• Increase the duty cycle k
• Increase the stage number n
• Increase the transfer gain M.
6.10.5.3 Inrush Input Current
Inrush input current is large for all SC DC–DC converters, since the charging current to
the switchedcapacitors is high during the main switchoff period. As an example, the
simulation result of the inrush input current of a threestage SC P/O Luoconverter is
shown in Figure 6.81.
140.00
V
O
V
in
I
in
30.00
25.00
20.00
15.00
10.00
5.00
0.00
54600.00 54610.00 54620.00
Time (μs)
54630.00 54640.00
120.00
100.00
80.00
60.00
40.00
20.00
0.00
FIGURE 6.81 Simulation result (inrush input current).
Voltage Lift Converters 289
300.00
I
in
250.00
200.00
150.00
100.00
50.00
0.00
0.00 0.50 1.00 1.50
Time (ms)
2.00 2.50 3.00
FIGURE 6.82 Simulation result (poweron surge input current).
The load current is very small, namely I = 120/400 = 0.3A, but the peak value of the
input inrush current is about 27.3A. Another phenomenon is that the input inrush current
usually does not fully occupy the switchoff period. We will discuss how to overcome this
phenomenon in Section 6.10.5.5.
6.10.5.4 Power SwitchOn Process
Surge input current is large for all SC DC–DC converters during the power switchon
process since all switched capacitors are not precharged. For example, we show the simu
lation result of the poweron surge input current of a threestage SC P/O Luoconverter in
Figure 6.82.
The peak value of the poweron surge input current is very high, namely about
262 A.
6.10.5.5 Suppression of the Inrush and Surge Input Currents
FromFigures 6.81 and6.82, we can see that the peak inrush input current can be 90 times the
normal load current, and the peak poweron surge input current can be about 880 times the
normal load current. This is a serious problemfor industrial applications of the SCDC/DC
converters. In order to suppress the large inrush input current andthe peak poweron surge
S
1
V
1
S
4
V
2
S
7
S
9
V
3
C
3
R
3
S
3
S
5
R
2
S
8
C
2
R
1
S
2
C
1
V
in
S
6
S D
L
O
i
O
V
O C
O
C L R
–
– –
– –
–
–
+
+
+
+
+ +
+
FIGURE 6.83 Improved threestage SC P/O Luoconverter.
290 Power Electronics
5.00
I
in
l(R)
4.00
3.00
2.00
1.00
0.00
38000.00 38020.00 38040.00
Time (μs)
38060.00
FIGURE 6.84 Simulation result (inrush input current) with R
S
.
input current, we set a small resistor (the socalled suppression resistor R
S
) in series with
each switched capacitor. The circuit of such a threestage SC P/O Luoconverter is shown
in Figure 6.83. The resistance R
S
is designed to have the time constant of the RC circuit
compete with the switchoff period.
R
S
=
1 −k
C
T =
1 −k
f C
. (6.240)
150.00
I
in
125.00
100.00
75.00
50.00
25.00
0.00
0.00 0.02 0.04 0.06
Time (ms)
0.08 0.10
FIGURE 6.85 Simulation result (poweron surge input current) with R
S
.
Voltage Lift Converters 291
The same conditions as those mentioned in the previous section were used: f = 50 kHz,
all capacitances are C = 20 μF, and conduction duty cycle k = 0.6. We can choose R
1
= R
2
=
R
3
= 0.4 Ω. The inrush input current and the load current are shown in Figure 6.84.
By comparison with Figure 6.81, we can see that the peak inrush input current is largely
reduced to 4.8Aand the input current becomes continuous in the switchoff period.
The poweron surge input current waveformis shown in Figure 6.85. The peak poweron
surge input current is about 138A, which is largely reduced.
Homework
6.1. An N/O selflift Luoconverter shown in Figure 6.6a has the following com
ponents: V
I
= 20 V, L = L
O
= 1 mH, C = C
1
= C
O
= 20 μF, R = 40 Ω, f = 50 kHz,
and k = 0.5. Calculate the output voltage and the variation ratios ζ
1
, ζ
2
, ρ, σ
1
, and
ε in the steady state.
6.2. An N/O selflift Luoconverter shown in Figure 6.6a has the following compo
nents: V
I
= 20 V, all inductances are 1 mH, all capacitances are 20 μF, R = 1000 Ω,
f = 50 kHz, and k = 0.5. Calculate the output voltage in the steady state.
6.3. An enhanced selflift P/O Luoconverter shown in Figure 6.9 has the following
components: V
I
= 20 V, all inductances are 1 mH, all capacitances are 20 μF, R =
100 Ω, f = 50 kHz, and k = 0.5. Calculate the output voltage in the steady state.
6.4. An N/O triplelift Luoconverter shown in Figure 6.22 has the following com
ponents: V
I
= 20 V, L
1
= L
2
= 0.5 mH, L = L
O
= 1 mH, all capacitors have 20 μF,
R = 300 Ω, f = 50 kHz, andk = 0.5. Calculate the output voltage andthe variation
ratios ζ, ξ, χ
1
, χ
2
, ρ, σ
1
, σ
2
, σ
3
, and ε in the steady state.
6.5. An enhanced D/O selflift DC–DC converter shown in Figure 6.61 has the fol
lowing components: V
I
= 20 V, all inductances are 1 mH, all capacitances are
20 μF, R = R
1
= 300 Ω, f = 50 kHz, and k = 0.5. Calculate the output voltage in
the steady state.
6.6. A threestage SC P/O Luoconverter shown in Figure 6.75 has the following
components: V
in
= 20 V, all inductances are 1 mH, all capacitances are 20 μF,
R = 300 Ω, f = 50 kHz, and k varies from 0.1 to 0.9 with an increment of 0.1.
Calculate the output voltage in the steady state.
References
1. Luo, F. L. and Ye, H. 2004. Advanced DC/DC Converters. Boca Raton: CRC Press.
2. Luo, F. L. andYe, H. 2006. Essential DC/DCConverters. Boca Raton: Taylor &Francis Group LLC.
3. Luo, F. L. 2001. Seven selflift DC/DCconverters: Voltage lift technique. IEEProceedings on EPA,
vol. 148, pp. 329–338.
4. Luo, F. L. 2001. Six selflift DC/DC converters: Voltage lift technique. IEEE Transactions on
Industrial Electronics, 48, 1268–1272.
5. Luo, F. L. andChenX. F. 1998. Selflift DC–DCconverters. Proceedings of the 2nd IEEEInternational
Conference PEDES’98, pp. 441–446.
292 Power Electronics
6. Luo, F. L. 1999. Positive output Luoconverters: Voltage lift technique. IEEEPAProceedings, vol.
146, pp. 415–432.
7. Luo, F. L. 1998. Relift converter: Design, test, simulation and stability analysis. IEEEPA
Proceedings, vol. 145, pp. 315–325.
8. Luo, F. L. 1997. Relift circuit: Anew DC–DC stepup (boost) converter. IEE Electronics Letters,
33, 5–7.
9. Luo, F. L. 1998. Luoconverters—voltage lift technique. Proceedings of the IEEE Power Electronics
Special Conference IEEEPESC’98, pp. 1783–1789.
10. Luo, F. L. 1997. Luoconverters, a series of new DC–DC stepup (boost) conversion circuits.
Proceedings of the IEEE International Conference on Power Electronics and Drive Systems—1997,
pp. 882–888.
11. Massey, R.P. and Snyder, E.C. 1977. High voltage single ended DC–DCconverter. Record of IEEE
PESC, 156–159.
12. Luo, F. L. 1999. Negative output Luoconverters: Voltage lift technique. IEEEPA Proceedings,
vol. 146, pp. 208–224.
13. Luo, F. L. 1998. Negative output Luoconverters, implementing the voltage lift technique.
Proceedings of the Second World Energy System International Conference’98, pp. 253–260.
14. Luo, F. L. and Ye, H. 1999. Modiﬁed positive output Luo converters. Proceedings of the IEEE
International Conference PEDS’99, pp. 450–455.
15. Luo, F. L. 2000. Double output Luoconverters: Advanced voltage lift technique. Proceedings of
IEEEPA, vol. 147, pp. 469–485.
16. Luo, F. L. 1999. Double output Luoconverters. Proceedings of the International Conference IEE
IPEC’99, pp. 647–652.
17. Cuk, S. and Middlebrook, R. D. 1977. Anewoptimumtopology switching DCtoDCconverter.
Proceedings of IEEE PESC, pp. 160–179.
18. Zhu, M. and Luo, F. L. 2007. Implementing of developed voltage lift technique on SEPIC, Cúk
and doubleoutput DC/DC converters. Proceedings of IEEEICIEA 2007, pp. 674–681.
19. Zhu, M. and Luo, F. L. 2007. Implementing of development of voltage lift technique on double
output transformerless DC–DC converters. Proceedings of IECON 2007, pp. 1983–1988.
20. Jozwik, J. J. and Kazimerczuk, M. K. 1989. Dual SEPIC PWM switchingmode DC/DC power
converter. IEEE Transactions on Industrial Electronics, 36, 64–70.
21. Adar, D., Rahav, G., and BenYaakov, S. 1996. Behavioural average model of SEPIC converters
with coupled inductors. IEE Electronics Letters, 32, 1525–1526.
22. Luo, F. L. 2009. Switchedcapacitorized DC–DC converters. Proceedings of IEEEICIEA 2009,
pp. 385–389.
23. Luo, F. L. 2009. Investigation of switchedcapacitorized DC–DCconverters. Proceedings of IEEE
IPEMC 2009, pp. 1283–1288.
24. Luo, F. L. and Ye, H. 2004. Positive output multiplelift pushpull switchedcapacitor Luo
converters. IEEETransactions on Industrial Electronics, 51, 594–602.
25. Gao, Y. and Luo, F. L. 2001. Theoretical analysis on performance of a 5 V/12 V pushpull
switched capacitor DC/DC converter. Proceedings of the International Conference IPEC 2001, pp.
711–715.
26. Luo, F. L. and Ye, H. 2003. Negative output multiplelift pushpull switchedcapacitor Luo
converters. Proceedings of IEEE International Conference PESC 2003, pp. 1571–1576.
27. Luo, F. L., Ye, H., and Rashid, M. H. 1999. Switched capacitor fourquadrant Luoconverter.
Proceedings of the IEEEIAS Annual Meeting, pp. 1653–1660.
28. Makowski, M. S. 1997. Realizability conditions and bounds on synthesis of switched capacitor
DC–DC voltage multiplier circuits. IEEE Transactions on Circuits and Systems, 45, 684–691.
29. Cheong, S. V., Chung, H., and Ioinovici, A. 1994. Inductorless DC–DC converter with high
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30. Midgley, D. and Sigger, M. 1974. Switchedcapacitors in power control. IEE Proceedings, 124,
703–704.
31. Mak, O. C., Wong, Y. C., and Ioinovici, A. 1995. Stepup DCpower supply based on a switched
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Voltage Lift Converters 293
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switchedcapacitor DC/DC converters. IEEE Transactions on Industrial Electronics, 47, 238–244.
33. Pan, C. T. and Liao, Y. H. 2007. Modeling and coordinate control of circulating currents in
parallel threephase boost rectiﬁers. IEEE Transactions on Industrial Electronics, 54, 825–838.
34. Mazumder, S. K., Tahir, M., and Acharya, K. 2008. Master–slave currentsharing control of a
parallel DC–DC converter system over an RF communication interface. IEEE Transactions on
Industrial Electronics, 55, 59–66.
35. Asiminoaei, L., Aeloiza, E., Enjeti, P., and Blaabjerg, F. 2008. Shunt activepowerﬁlter topology
based on parallel interleaved inverters. IEEE Transactions on Industrial Electronics, 55, 1175–1189.
36. Chen, W. and Ruan, X. 2008. Zerovoltageswitching PWM hybrid fullbridge threelevel con
verter with secondaryvoltage clamping scheme. IEEE Transactions on Industrial Electronics, 55,
644–654.
37. Wang, C. M. 2006. New family of zerocurrentswitching PWM converters using a new zero
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AC power distribution architecture with multiple inverter modules operated in parallel. IEEE
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7
SuperLift Converters and Ultralift Converter
The VL technique has been successfully employed in the design of DC/DC converters,
and effectively enhances the voltage transfer gains of the VL converters. However, the
output voltage increases in arithmetic progression stage by stage. The SLtechnique is more
powerful than the VL technique; its voltage transfer gain can be a very large value. The
SL technique implements the output voltage increasing in geometric progression stage by
stage. It effectively enhances the voltage transfer gain in power series [1–6].
7.1 Introduction
The SL technique is the most important contribution to DC/DC conversion technology. By
applying this technique, a large number of SL converters can be designed. The following
series of VL converters are introduced in this chapter:
• P/O SL Luoconverters
• N/O SL Luoconverters
• P/O cascaded boost converters
• N/O cascaded boost converters
• UL Luoconverters.
Each series of converters has several subseries. For example, the P/O SL Luoconverters
have ﬁve subseries:
• The main series: Each circuit of the main series has only one switch S, n inductors
for the nth stage circuit, 2n capacitors, and (3n −1) diodes.
• Additional series: Each circuit of the additional series has one switch S, n inductors
for the nth stage circuit, 2(n +1) capacitors, and (3n +1) diodes.
• Enhanced series: Each circuit of the enhanced series has one switch S, n inductors
for the nth stage circuit, 4n capacitors, and (5n −1) diodes.
• Reenhanced series: Each circuit of the reenhanced series has one switch S, n
inductors for the nth stage circuit, 6n capacitors, and (7n −1) diodes.
• Multiple (j)enhanced series: Each circuit of the multiple ( j times)enhanced series
has one switch S, n inductors for the nth stage circuit, 2(1 +j)n capacitors, and
[(3 +2j)n −1] diodes.
295
296 Power Electronics
In order to concentrate the voltage enhancement, assume that the converters are working
in the steady state in the CCM. The conduction duty ratio is k, the switching frequency is
f , the switching period is T = 1/f , and the load is resistive load R. The input voltage and
current are V
in
and I
in
, and the output voltage and current are V
O
and I
O
. Assuming that
there are no power losses during the conversion process, V
in
×I
in
= V
O
×I
O
. The voltage
transfer gain G is given by
G =
V
O
V
in
.
7.2 P/O SL LuoConverters
We introduce here only three circuits from each subseries. Once the readers grasp the clue,
they can design the other circuits easily [1–4].
7.2.1 Main Series
The ﬁrst three stages of P/O SL Luoconverters, namely the main series, are shown in
Figures 7.1 through 7.3. To make it easy to explain, they are called the elementary circuit,
the relift circuit, and the triplelift circuit, respectively, and are numbered n = 1, 2, and 3,
respectively.
7.2.1.1 Elementary Circuit
The elementary circuit and its equivalent circuits during switchon and switchoff periods
are shown in Figure 7.1.
The voltage across capacitor C
1
is charged with V
in
. The current i
L1
ﬂowing through
inductor L
1
increases with V
in
during the switchon period kT and decreases with
−(V
O
−2V
in
) during the switchoff period (1 −k)T. Therefore, the ripple of the inductor
current i
L1
is
Δi
L1
=
V
in
L
1
kT =
V
O
−2V
in
L
1
(1 −k)T, (7.1)
V
O
=
2 −k
1 −k
V
in
. (7.2)
The voltage transfer gain is
G =
V
O
V
in
=
2 −k
1 −k
. (7.3)
The input current I
in
is equal to (i
L1
+i
C1
) during switchon, and only i
L1
during switch
off. The capacitor current i
C1
is equal to i
L1
during switchoff. Inthe steady state, the average
charge across capacitor C
1
should not change. The following relations are obtained:
i
in–off
= i
L1–off
= i
C1–off
, i
in–on
= i
L1–on
+i
C1–on
, kTi
C1–on
= (1 −k)Ti
C1–off
.
SuperLift Converters and Ultralift Converter 297
I
in
I
in
I
in
V
in
I
O
+ +
–
+
–
+
–
V
in
–
+
V
in
–
+
V
in
–
S
R
L
1
C
1
V
C1
+
–
L
1
L
1
V
L1
C
1
C
1
V
in
V
O
I
O
+
+ –
–
V
O
V
C2
D
1
D
2
C
2
+
–
V
C2
C
2
+
–
V
C2
C
2
(a)
(b)
(c)
R
I
O
+
–
V
O
R
FIGURE 7.1 Elementary circuit of P/O SL Luoconverters—main series: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 217. With permission.)
If inductance L
1
is large enough, i
L1
is nearly equal to its average current I
L1
. Therefore,
i
in–off
= i
C1–off
= I
L1
, i
in–on
= I
L1
+
1 −k
k
I
L1
=
I
L1
k
, i
C1–on
=
1 −k
k
I
L1
,
and the average input current is
I
in
= ki
in–on
+(1 −k)i
in–off
= I
L1
+(1 −k)I
L1
= (2 −k)I
L1
. (7.4)
Considering V
in
/I
in
= ((1 −k)/(2 −k))
2
V
O
/I
O
= ((1 −k)/(2 −k))
2
R, the variation ratio of
current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(2 −k)TV
in
2L
1
I
in
=
k(1 −k)
2
2(2 −k)
R
f L
1
. (7.5)
Usually ξ
1
is small (much lower than unity); this means that this converter normally works
in the continuous mode.
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
2
=
I
O
kT
C
2
=
k
fC
2
V
O
R
.
298 Power Electronics
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
2
. (7.6)
Example 7.1
A P/O SL Luoconverter in Figure 7.1a has V
in
= 20V, L
1
= 10mH, C
1
= C
2
= 20μF, R =
100Ω, f = 50kHz, and conduction duty cycle k = 0.6. Calculate the variation ratio of current
i
L1
, and the output voltage and its variation ratio.
SOLUTION
From Equation 7.5, we can obtain the variation ratio of current i
L1
,
ξ
1
=
k(1 −k)
2
2(2 −k)
R
f L
1
=
0.6(1 −0.6)
2
2(2 −0.6)
100
50k ×10m
= 0.00686.
From Equation 7.2, we can obtain the output voltage
V
O
=
2 −k
1 −k
V
in
=
2 −0.6
1 −0.6
20 = 70V.
From Equation 7.6, its variation ratio is
ε =
k
2RfC
2
=
0.6
2 ×100 ×50k ×20μ
= 0.003.
7.2.1.2 ReLift Circuit
The relift circuit is derived from the elementary circuit by adding the parts
(L
2
D
3
D
4
D
5
C
3
C
4
). Its circuit diagram and equivalent circuits during switchon and
switchoff periods are shown in Figure 7.2. The voltage across capacitor C
1
is charged
with V
in
. As described in the previous section, the voltage V
1
across capacitor C
2
is
V
1
= ((2 −k)/(1 −k))V
in
.
The voltage across capacitor C
3
is charged with V
1
. The current ﬂowing through inductor
L
2
increases withV
1
duringtheswitchonperiodkT anddecreases with−(V
O
−2V
1
) during
the switchoff period (1 −k)T. Therefore, the ripple of the inductor current i
L2
is
Δi
L2
=
V
1
L
2
kT =
V
O
−2V
1
L
2
(1 −k)T, (7.7)
V
O
=
2 −k
1 −k
V
1
=
_
2 −k
1 −k
_
2
V
in
. (7.8)
The voltage transfer gain is
G =
V
O
V
in
=
_
2 −k
1 −k
_
2
. (7.9)
SuperLift Converters and Ultralift Converter 299
I
in
I
O
V
O
+
V
in
V
in
–
+
–
+
–
+
–
+
–
+
–
D
1
(a)
L
1
C
1
L
2
C
3
C
2
C
4
R
S
V
C3
V
C2
V
C4
V
C1
D
2
D
3
V
1
D
4
D
5
I
in
+
–
+
–
+
–
+
–
+
–
V
O
+
–
(b)
V
1
I
O
L
2 C
3
C
4
R
V
C4
L
1
C
1
V
in
C
2
V
1
V
1
V
L1
I
in
V
in
+
V
in
–
+ –
(c)
C
3
V
O
+
–
I
O
R
+
–
V
C4
L
2
L
1
C
1
C
2 C
4
+
+
–
–
V
1
V
1
V
L2
V
1
FIGURE 7.2 Relift circuit of P/O SL Luoconverters—main series: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 218. With permission.)
Analogously, the following relations are obtained:
Δi
L1
=
V
in
L
1
kT, I
L1
=
I
in
2 −k
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
_
2 −k
1 −k
−1
_
I
O
=
I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(2 −k)TV
in
2L
1
I
in
=
k(1 −k)
4
2(2 −k)
3
R
f L
1
. (7.10)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
2L
2
I
O
=
k(1 −k)
2
TV
O
2(2 −k)L
2
I
O
=
k(1 −k)
2
2(2 −k)
R
f L
2
, (7.11)
300 Power Electronics
D
1
D
2
V
1
V
1
V
1
V
2
V
1
D
4
D
5
D
7
D
8
V
2
V
2
I
in
(a)
(c)
I
in
L
2
+
V
in
–
V
2
+
–
–
L
1
+
+ +
+
V
in
V
in
–
– – + –
–
V
L1
V
L3 V
L2
L
1
C
1
C
1
C
2
C
3
C
4
C
6
V
C6
C
2
V
C1
D
3
D
6
C
4
L
2
S
C
3
+ +
–
V
C3
+
–
V
C2
+
–
V
C4
L
3
L
3
C
5
C
5
+
–
V
C5
I
O
+
–
R
V
1
V
2
(b) I
in
V
1
V
2
V
2
L
2
V
in
C
2
+
–
+
L
3
+
– –
+
V
in
–
+
V
1
–
+
–
+
–
L
1 C
1
C
3
C
5
C
4
C
6
V
C6
I
O
V
O
+
–
V
O
+
–
R
I
O
V
O
+
–
+
–
R
V
C6
C
6
FIGURE 7.3 Triplelift circuit of P/O SL Luoconverters—main series: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 219. With permission.)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
4
. (7.12)
7.2.1.3 TripleLift Circuit
The triplelift circuit is derived from the relift circuit by twice repeating the parts
(L
2
D
3
D
4
D
5
C
3
C
4
). Its circuit diagram and equivalent circuits during switchon and
switchoff periods are shown in Figure 7.3. The voltage across capacitor C
1
is charged
with V
in
. As described in the previous section, the voltage V
1
across capacitor C
2
is V
1
=
((2 −k)/(1 −k))V
in
, and the voltage V
2
across capacitor C
4
is V
2
= ((2 −k)/(1 −k))
2
V
in
.
The voltage across capacitor C
5
is charged with V
2
. The current ﬂowing through inductor
L
3
increases withV
2
duringtheswitchonperiodkT anddecreases with−(V
O
−2V
2
) during
the switchoff period (1 −k)T. Therefore, the ripple of the inductor current i
L2
is
Δi
L3
=
V
2
L
3
kT =
V
O
−2V
2
L
3
(1 −k)T, (7.13)
SuperLift Converters and Ultralift Converter 301
V
O
=
2 −k
1 −k
V
2
=
_
2 −k
1 −k
_
2
V
1
=
_
2 −k
1 −k
_
3
V
in
. (7.14)
The voltage transfer gain is
G =
V
O
V
in
=
_
2 −k
1 −k
_
3
. (7.15)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
I
in
2 −k
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2 −k
(1 −k)
2
I
O
,
Δi
L3
=
V
2
L
3
kT, I
L3
=
I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(2 −k)TV
in
2L
1
I
in
=
k(1 −k)
6
2(2 −k)
5
R
f L
1
. (7.16)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
2(2 −k)L
2
I
O
=
kT(2 −k)
4
V
O
2(1 −k)
3
L
2
I
O
=
k(2 −k)
4
2(1 −k)
3
R
f L
2
. (7.17)
The variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
2L
3
I
O
=
k(1 −k)
2
TV
O
2(2 −k)L
2
I
O
=
k(1 −k)
2
2(2 −k)
R
f L
3
, (7.18)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
6
. (7.19)
Example 7.2
A triplelift circuit of the P/O SL Luoconverter in Figure 7.3a has V
in
= 20V, all inductors have
10mH, all capacitors have 20μF, R = 1000Ω, f = 50kHz, and conduction duty cycle k = 0.6.
Calculate the variation ratio of current i
L1
, and the output voltage and its variation ratio.
SOLUTION
From Equation 7.16, we can obtain the variation ratio of current i
L1
,
ξ
1
=
k(1 −k)
6
2(2 −k)
5
R
f L
1
=
0.6(1 −0.6)
6
2(2 −0.6)
5
1000
50k ×10m
= 0.00046.
302 Power Electronics
From Equation 7.14, we can obtain the output voltage
V
O
=
_
2 −k
1 −k
_
3
V
in
=
_
2 −0.6
1 −0.6
_
3
20 = 857.5V.
From Equation 7.19, its variation ratio is
ε =
k
2RfC
6
=
0.6
2 ×1000 ×50k ×20μ
= 0.0003.
7.2.1.4 HigherOrder Lift Circuit
The higherorder lift circuit can be designed by just multiple repeating of the parts
(L
2
D
3
D
4
D
5
C
3
C
4
). For the nthorder lift circuit, the ﬁnal output voltage across capacitor
C
2n
is
V
O
=
_
2 −k
1 −k
_
n
V
in
.
The voltage transfer gain is
G =
V
O
V
in
=
_
2 −k
1 −k
_
n
. (7.20)
The variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
2(2 −k)
2(n−i)+1
R
f L
i
, (7.21)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
1 −k
2RfC
2n
. (7.22)
7.2.2 Additional Series
By using two diodes and two capacitors (D
11
D
12
C
11
C
12
), a circuit called “double/
enhance circuit” (DEC) canbe constructed, whichis showninFigure 7.4. If the input voltage
is V
in
, the output voltage V
O
can be 2V
in
or another value higher than V
in
. The DECis very
useful to enhance the DC/DC converter’s voltage transfer gain.
All circuits of P/O SL Luoconverters—additional series—are derived from the corre
sponding circuits of the main series by adding a DEC. The ﬁrst three stages of this series
are shown in Figures 7.5 through 7.7. For ease of understanding, they are called the ele
mentary additional circuit, the relift additional circuit, and the triplelift additional circuit,
respectively, and are numbered as n = 1, 2, and 3, respectively.
7.2.2.1 Elementary Additional Circuit
The elementary additional circuit is derived from the elementary circuit by adding a DEC.
Its circuit and switchon and switchoff equivalent circuits are shown in Figure 7.5.
SuperLift Converters and Ultralift Converter 303
+
+
–
+
–
+
–
V
in
–
V
C11
V
C12
V
O
C
1
C
12
C
11
FIGURE 7.4 DEC. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton: Taylor &
Francis Group LLC, p. 223. With permission.)
The voltage across capacitor C
1
is charged with V
in
and the voltage across capacitors C
2
and C
11
is charged with V
1
. The current i
L1
ﬂowing through inductor L
1
increases with
V
in
during the switchon period kT and decreases with −(V
O
−2V
in
) during the switchoff
period (1 −k)T. Therefore,
V
1
=
2 −k
1 −k
V
in
(7.23)
I
in
I
in
I
in
I
O
+
+
–
V
in
–
+
V
in
–
+
+ –
+ –
V
in
–
S
R
R
L
1
L
1
L
1
+
–
C
1
V
C1
+
+ –
–
C
1
C
1
V
L1
V
in
V
in
+
–
C
2
V
C2
+
–
C
2
C
2
V
1
+
–
V
C12
+
–
V
C12
+
–
V
C12
+
–
V
1
+
–
V
C11
+
–
V
1
V
O
I
O
+
–
V
O
R
I
O
+
–
V
O
V
1
D
1
D
11
C
11
C
11
C
11
C
12
C
12
C
12
D
12
D
2
V
1
V
1
V
1
(a)
(b)
(c)
FIGURE 7.5 Elementary additional circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters, p. 224. Boca Raton: Taylor & Francis Group LLC. With permission.)
304 Power Electronics
and
V
L1
=
k
1 −k
V
in
. (7.24)
The output voltage is
V
O
= V
in
+V
L1
+V
1
=
3 −k
1 −k
V
in
. (7.25)
The voltage transfer gain is
G =
V
O
V
in
=
3 −k
1 −k
. (7.26)
The following relations are derived:
i
in–off
= I
L1
= i
C11–off
+i
C1–off
=
2I
O
1 −k
, i
in–on
= i
L1–on
+i
C1–on
= I
L1
+
I
O
k
,
i
C1–on
=
1 −k
k
i
C1–off
=
I
O
k
, i
C1–off
= i
C2–off
=
I
O
1 −k
,
i
C2–off
=
k
1 −k
i
C2–on
=
k
1 −k
i
C11–on
=
I
O
1 −k
, i
C11–on
=
1 −k
k
i
C11–off
=
I
O
k
,
i
C11–off
= I
O
+i
C12–off
= I
O
+
k
1 −k
i
C12–on
=
I
O
1 −k
, i
C12–off
=
k
1 −k
i
C12–on
=
kI
O
1 −k
.
If inductance L
1
is large enough, i
L1
is nearly equal to its average current I
L1
. Therefore,
i
in–off
= I
L1
=
2I
O
1 −k
, i
in–on
= I
L1
+
I
O
k
=
_
2
1 −k
+
1
k
_
I
O
=
1 +k
k(1 −k)
I
O
.
Veriﬁcation: I
in
= ki
in–on
+(1 −k)i
in–off
=
_
1 +k
1 −k
+2
_
I
O
=
3 −k
1 −k
I
O
.
Considering (V
in
/I
in
) = ((1 −k)/(2 −k))
2
(V
O
/I
O
) = ((1 −k)/(2 −k))
2
R, the variation of
current i
L1
is Δi
L1
= kTV
in
/L
1
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)TV
in
4L
1
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
1
. (7.27)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.28)
SuperLift Converters and Ultralift Converter 305
7.2.2.2 ReLift Additional Circuit
This circuit is derived from the relift circuit by adding a DEC. Its circuit diagram and
switchon and switchoff equivalent circuits are shown in Figure 7.6. The voltage across
capacitor C
1
is charged with V
in
. As described in the previous section, the voltage across
C
2
is V
1
= ((2 −k)/(1 −k))V
in
.
The voltage across capacitor C
3
is charged with V
1
and the voltage across capacitors
C
4
and C
11
is charged with V
2
. The current ﬂowing through inductor L
2
increases with
V
1
during the switchon period kT and decreases with −(V
O
−2V
1
) during the switchoff
period (1 −k)T. Therefore,
V
2
=
2 −k
1 −k
V
1
=
_
2 −k
1 −k
_
2
V
in
(7.29)
I
in
I
in
I
in
I
O
+
+
–
V
in
V
O
V
in
V
in
S
–
+
–
V
in
+
–
+
–
+
–
R
R
L
1
L
1
L
1
+
–
+
–
–
+
–
+
–
–
+
–
C
1
C
1
C
1
C
2
C
2
C
2
C
4
C
3
V
C1
+
+
–
+
+
+
+
–
–
–
V
in
C
4
C
11
C
11
C
12
C
11
C
12
C
12
V
C4
+
–
V
C12
V
O
I
O
I
O
+
–
V
O
+
–
D
1
D
4
D
11
D
12
D
5
D
2
D
3
L
2
L
2
L
2
C
3
C
3 C
4
V
C3
+
–
+
–
V
C2
+
–
V
C11
V
1
V
1
V
1
V
1
V
1
V
1
V
C12
R
+
–
V
C12
V
1
V
2
V
2
V
2
V
2
V
2
V
2
V
2
(a)
(b)
(c)
FIGURE 7.6 Relift additional circuit of P/OSLLuoconverters: (a) circuit diagram, (b) equivalent circuit during
switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 225. With permission.)
306 Power Electronics
and
V
L2
=
k
1 −k
V
1
. (7.30)
The output voltage is
V
O
= V
1
+V
L2
+V
2
=
2 −k
1 −k
3 −k
1 −k
V
in
. (7.31)
The voltage transfer gain is
G =
V
O
V
in
=
2 −k
1 −k
3 −k
1 −k
. (7.32)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
3 −k
(1 −k)
2
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
2(3 −k)L
1
I
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
1
, (7.33)
and the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
4L
2
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
2
. (7.34)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.35)
7.2.2.3 TripleLift Additional Circuit
This circuit is derived from the triplelift circuit by adding a DEC. Its circuit diagram and
equivalent circuits during switchon and switchoff periods are shown in Figure 7.7. The
voltage across capacitor C
1
is charged with V
in
. As described in the previous section, the
voltage across C
2
is V
1
= ((2 −k)/(1 −k))V
in
and the voltage across C
4
is
V
2
=
2 −k
1 −k
V
1
=
_
2 −k
1 −k
_
2
V
in
.
SuperLift Converters and Ultralift Converter 307
I
in
I
in
I
in
I
O
+
+
–
V
in
S
–
+
+ – + –
V
in
–
+
V
1
–
+
–
R
R
R
L
1
+
V
in
–
+
V
in
V
in
–
+
–
+
–
L
1
L
1
+
+
+
–
+
–
–
C
2
+
–
C
1
C
1
C
1
V
C1
C
6
C
6
C
11
C
11
C
11
C
12
C
12
C
12
V
C6
+
–
V
C12
V
3
+
–
–
V
C12
V
C12
V
O
I
O
+
–
V
O
I
O
+
–
V
O
D
1
D
4
D
11
D
12
D
5
D
6
D
2
D
3
L
2
L
2
L
2
L
3
L
3
L
3
C
5
C
5
C
4
C
4
C
4
V
C5
+
–
C
3
C
3
C
3
C
5
C
2
C
2
C
6
V
C3
+
–
+
–
V
C4
+
–
V
C2
+
–
V
C11
+
–
+
–
V
3
V
1
V
1
V
1
V
1
V
1
V
1
+ – V
2
V
3
+ –
V
3
V
3
V
2
V
2
V
2
V
2
V
2
V
3
D
7
D
8
(a)
(b)
(c)
FIGURE 7.7 Triplelift additional circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 226. With permission.)
The voltage across capacitor C
5
is charged with V
2
and the voltage across capacitors
C
6
and C
11
is charged with V
3
. The current ﬂowing through inductor L
3
increases with
V
2
during the switchon period kT and decreases with −(V
O
−2V
2
) during the switchoff
period (1 −k)T. Therefore,
V
3
=
2 −k
1 −k
V
2
=
_
2 −k
1 −k
_
2
V
1
=
_
2 −k
1 −k
_
3
V
in
(7.36)
and
V
L3
=
k
1 −k
V
2
. (7.37)
The output voltage is
V
O
= V
2
+V
L3
+V
3
=
_
2 −k
1 −k
_
2
3 −k
1 −k
V
in
. (7.38)
308 Power Electronics
The voltage transfer gain is
G =
V
O
V
in
=
_
2 −k
1 −k
_
2
3 −k
1 −k
. (7.39)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
(2 −k)(3 −k)
(1 −k)
3
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
3 −k
(1 −k)
2
I
O
,
Δi
L3
=
V
2
L
3
kT, I
L3
=
2I
O
1 −k
.
Considering
V
in
I
in
=
_
1 −k
2 −k
_
2
V
O
I
O
=
_
1 −k
2 −k
_
2
R,
the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
2(2 −k)(3 −k)L
1
I
O
=
k(1 −k)
3
T
2(2 −k)(3 −k)L
1
I
O
(1 −k)
3
(2 −k)
2
(3 −k)
V
O
=
k(1 −k)
6
2(2 −k)
3
(3 −k)
2
R
f L
1
, (7.40)
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
2(3 −k)L
2
I
O
=
k(1 −k)
2
T
2(3 −k)L
2
I
O
(1 −k)
2
(2 −k)(3 −k)
V
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
2
,
(7.41)
and the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
4L
3
I
O
=
k(1 −k)T
4L
3
I
O
1 −k
3 −k
V
O
=
k(1 −k)
2
4(3 −k)
R
f L
3
. (7.42)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.43)
SuperLift Converters and Ultralift Converter 309
7.2.2.4 HigherOrder Lift Additional Circuit
The higherorder lift additional circuit is derived from the corresponding circuits of the
main series by adding a DEC. For the nthorder lift additional circuit, the ﬁnal output
voltage is
V
O
=
_
2 −k
1 −k
_
n−1
3 −k
1 −k
V
in
.
The voltage transfer gain is
G =
V
O
V
in
=
_
2 −k
1 −k
_
n−1
3 −k
1 −k
. (7.44)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
2[2(2 −k)]
h(n−i)
(2 −k)
2(n−i)+1
(3 −k)
2u(n−i−1)
R
f L
i
, (7.45)
where
h(x) =
_
0 x > 0
1 x ≤ 0
is the Hong function
and
u(x) =
_
1 x ≥ 0
0 x < 0
is the unitstep function,
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.46)
7.2.3 Enhanced Series
All circuits of P/OSLLuoconverters—enhanced series—are derived fromthe correspond
ing circuits of the main series by adding the DEC in circuits of each stage. The ﬁrst three
stages of this series are shown in Figures 7.5, 7.8, and 7.9. For ease of understanding, they
are called the elementaryenhanced circuit, the relift enhanced circuit, and the triplelift
enhanced circuit, respectively, and numbered n = 1, 2, and 3, respectively.
7.2.3.1 Elementary Enhanced Circuit
This circuit is the same as the elementary additional circuit shown in Figure 7.5.
The output voltage is
V
O
= V
in
+V
L1
+V
1
=
3 −k
1 −k
V
in
. (7.25)
310 Power Electronics
I
in
I
in
I
O
I
O
+
+
+
–
V
in
V
in
V
in
–
I
in
+ +
+ +
+
+
+
–
+
–
–
V
in
–
–
–
– +
+
–
+
–
+
–
R
R
L
1
L
1
L
1
V
L1
C
2
C
2
C
2
C
4
+
–
C
1
C
1
C
1
V
C1
C
11
C
12
C
4
C
22 V
C12
V
C12
V
C12
V
C12
C
12
+
–
V
C12
+
–
V
in
+
–
V
O
V
O
I
O
+
–
V
O
+
–
V
2
V
2
V
1
V
1
V
1
V
1
V
1
+ –
+ –
–
V
L2
D
1
D
4
D
5
D
2
D
3
D
12 D
21
D
22
D
11
L
2
L
2
L
2
+
–
C
3
C
3
C
4
V
C3
+
–
+
–
V
C4
+
–
+
–
C
21
C
21
C
3
+
–
V
2
V
2
V
2
C
22
C
22
+
–
V
C22
V
C22
R
+
–
–
–
V
C22
+
–
V
C2
+
–
V
C11
C
11
C
11
C
12
V
C12
C
12
V
1
V
1
V
2
V
2
(a)
(b)
(c)
S
FIGURE 7.8 Relift enhanced circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit during
switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 232. With permission.)
The voltage transfer gain is
G =
V
O
V
in
=
3 −k
1 −k
. (7.26)
The variation of current i
L1
is Δi
L1
= kTV
in
/L
1
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)TV
in
4L
1
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
1
. (7.27)
SuperLift Converters and Ultralift Converter 311
I
in
I
in
+
V
in
V
in
–
+ +
–
+ +
– –
+
+
–
+
–
+
V
in
V
2
–
+ + +
– – –
V
2
V
3
+
–
V
3
–
R
L
1
L
1
L
2
L
3 L
2
+
–
+
–
C
2
C
2
C
3
C
4
C
5
C
21
C
22
C
6
+
–
C
1
C
11
C
12
C
1
C
21
V
C1
C
11
I
O
I
O
+
–
V
O
R
+
–
V
O
D
1
D
4
D
21
D
22
D
31
D
32
D
11
D
12
D
5
D
2
D
3
D
6
L
3
C
5
C
6
C
31
C
12
V
C5
+
–
C
3
C
4
C
22
+
–
V
C2
V
C4
+
–
+
–
V
C22
+
–
V
C6
+
–
V
C32
+
–
V
C12
V
C12
+
–
V
C11
V
C12
V
C21
V
C22
C
31
C
32
+
–
V
C32
V
C22
V
C31
C
32
V
C3
V
1
V
1
V
1
V
1
V
2
V
2
V
3
D
8
V
3
D
7
(a)
(b)
S S
I
in
–
–
–
–
+
+
+
+ + +
–
–
–
V
L1
V
1
–
–
+
+
+
+
+
+
+
–
–
–
–
–
+
V
L2
V
L3
–
V
C22 V
C32
V
2
V
2
L
3
V
2
+ V
3
V
3
V
3
+
V
in
V
1
V
in
–
L
1
L
2
C
3
C
5
C
22
C
4
C
31
C
32
C
21
C
6
C
12
V
C12
C
11
C
1
C
2
R
I
O
+
–
V
O
V
C12
V
C22
V
1
(c)
FIGURE 7.9 Triplelift enhanced circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 233. With permission.)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.28)
7.2.3.2 ReLift Enhanced Circuit
The relift enhanced circuit is derived from the relift circuit of the main series by adding
the DEC in each stage circuit. Its circuit diagram and switchon and switchoff equivalent
circuits are shown in Figure 7.8. As described in the previous section, the voltage across
capacitor C
12
is charged with V
C12
= ((3 −k)/(1 −k))V
in
.
The voltage across capacitor C
3
is charged with V
C12
and the voltage across capacitors C
4
and C
21
is charged with V
C4
,
V
C4
=
2 −k
1 −k
V
C12
=
2 −k
1 −k
3 −k
1 −k
V
in
. (7.47)
312 Power Electronics
The current ﬂowing through inductor L
2
increases with V
C12
during the switchon
period kT and decreases with −(V
O
−V
C4
−V
C12
) during the switchoff period (1 −k)T.
Therefore,
Δi
L2
=
k
L
2
V
C12
=
1 −k
L
2
(V
O
−V
C4
−V
C12
), (7.48)
V
O
=
3 −k
1 −k
V
C12
=
_
3 −k
1 −k
_
2
V
in
. (7.49)
The voltage transfer gain is
G =
V
O
V
in
=
_
3 −k
1 −k
_
2
. (7.50)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
3 −k
(1 −k)
2
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
2(3 −k)L
1
I
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
1
(7.51)
and the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
4L
2
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
2
. (7.52)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
22
=
I
O
kT
C
22
=
k
fC
22
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
22
. (7.53)
7.2.3.3 TripleLift Enhanced Circuit
The triplelift enhanced circuit is derived from the triplelift circuit of the main series by
adding the DEC in each stage circuit. Its circuit diagram and equivalent circuits during
switchon and switchoff periods are shown in Figure 7.9. As described in the previous
section, the voltage across capacitor C
12
is charged with V
C12
= ((3 −k)/(1 −k))V
in
, and
the voltage across capacitor C
22
is charged with V
C22
= ((3 −k)/(1 −k))
2
V
in
.
SuperLift Converters and Ultralift Converter 313
The voltage across capacitor C
5
is charged with V
C22
and the voltage across capacitors
C
6
and C
31
is charged with V
C6
,
V
C6
=
2 −k
1 −k
V
C22
=
2 −k
1 −k
_
3 −k
1 −k
_
2
V
in
. (7.54)
The current ﬂowing through inductor L
3
increases with V
C22
during the switchon
period kT and decreases with −(V
O
−V
C6
−V
C22
) during the switchoff period (1 −k)T.
Therefore,
Δi
L3
=
k
L
3
V
C22
=
1 −k
L
3
(V
O
−V
C6
−V
C22
), (7.55)
V
O
=
3 −k
1 −k
V
C22
=
_
3 −k
1 −k
_
3
V
in
. (7.56)
The voltage transfer gain is
G =
V
O
V
in
=
_
3 −k
1 −k
_
3
. (7.57)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
(2 −k)(3 −k)
(1 −k)
3
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
3 −k
(1 −k)
2
I
O
,
Δi
L3
=
V
2
L
3
kT, I
L3
=
2I
O
1 −k
.
Considering
V
in
I
in
=
_
1 −k
2 −k
_
2
V
O
I
O
=
_
1 −k
2 −k
_
2
R,
the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
2(2 −k)(3 −k)L
1
I
O
=
k(1 −k)
3
T
2(2 −k)(3 −k)L
1
I
O
(1 −k)
3
(2 −k)
2
(3 −k)
V
O
=
k(1 −k)
6
2(2 −k)
3
(3 −k)
2
R
f L
1
. (7.58)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
2(3 −k)L
2
I
O
=
k(1 −k)
2
T
2(3 −k)L
2
I
O
(1 −k)
2
(2 −k)(3 −k)
V
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
2
,
(7.59)
314 Power Electronics
and the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
4L
3
I
O
=
k(1 −k)T
4L
3
I
O
1 −k
3 −k
V
O
=
k(1 −k)
2
4(3 −k)
R
f L
3
. (7.60)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
32
=
I
O
kT
C
32
=
k
fC
32
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
32
. (7.61)
7.2.3.4 HigherOrder Lift Enhanced Circuit
The higherorder lift enhancedcircuit is derivedfromthe corresponding circuits of the main
series by adding the DEC in each stage circuit. For the nthorder lift enhanced circuit, the
ﬁnal output voltage is V
O
= ((3 −k)/(1 −k))
n
V
in
.
The voltage transfer gain is
G =
V
O
V
in
=
_
3 −k
1 −k
_
n
. (7.62)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
2[2(2 −k)]
h(n−i)
(2 −k)
2(n−i)+1
(3 −k)
2u(n−i−1)
R
f L
i
, (7.63)
where
h(x) =
_
0 x > 0
1 x ≤ 0
is the Hong function
and
u(x) =
_
1 x ≥ 0
0 x < 0
is the unitstep function,
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n2
. (7.64)
7.2.4 ReEnhanced Series
All circuits of P/O SL Luoconverters—reenhanced series—are derived from the corre
sponding circuits of the main series by adding the DEC twice in each stage circuit.
SuperLift Converters and Ultralift Converter 315
I
in
V
in
V
C2
V
C12
V
C14
L
1
+
–
+
–
+
–
–
C
1
C
2
C
12
V
C1
I
O
C
13
C
11
C
14
D
1
D
2
D
12
D
11
D
13
D
14
+
(a)
(b)
(c)
–
I
in
V
in
V
in
V
in
V
1
V
1
V
1
L
1
L
1
V
1
V
C14
V
2
V
2
V
1
V
2
C
1
C
1
C
14
C
11
C
12
C
13
C
2
C
2
C
11
C
12
+
+
–
I
in
V
in
+
–
– +
+
+
+
+
+
– –
–
–
–
–
+
–
+
–
V
2
C
13
+
–
V
2
C
14
+
–
V
C14
+
–
S
+
+
–
+ –
+
–
V
C11
V
O
I
O
–
+
V
O
I
O
–
+
V
O
V
C13
V
1
V
1
V
2
V
2
R
R
R
FIGURE 7.10 Elementaryreenhancedcircuit of P/OSLLuoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 238. With permission.)
The ﬁrst three stages of this series are shown in Figures 7.10 through 7.12. For ease of
understanding, they are called the elementary reenhanced circuit, the relift reenhanced
circuit, and the triplelift reenhanced circuit, respectively, and numbered n = 1, 2, and 3,
respectively.
7.2.4.1 Elementary ReEnhanced Circuit
This circuit is derived from the elementary circuit by adding the DEC twice in each
stage circuit. Its circuit and switchon and switchoff equivalent circuits are shown in
Figure 7.10.
316 Power Electronics
The output voltage is
V
O
= V
in
+V
L1
+V
C12
=
4 −k
1 −k
V
in
. (7.65)
The voltage transfer gain is
G =
V
O
V
in
=
4 −k
1 −k
, (7.66)
where
V
C2
=
2 −k
1 −k
V
in
, (7.67)
V
C12
=
3 −k
1 −k
V
in
, (7.68)
and
V
L1
=
k
1 −k
V
in
. (7.69)
The following relations are obtained:
i
in–off
= I
L1
= i
C11–off
+i
C1–off
=
2I
O
1 −k
, i
in–on
= i
L1–on
+i
C1–on
= I
L1
+
I
O
k
,
i
C1–on
=
1 −k
k
i
C1–off
=
I
O
k
, i
C1–off
= i
C2–off
=
I
O
1 −k
,
i
C2–off
=
k
1 −k
i
C2–on
=
k
1 −k
i
C11–on
=
I
O
1 −k
, i
C11–on
=
1 −k
k
i
C11–off
=
I
O
k
,
i
C11–off
= I
O
+i
C12–off
= I
O
+
k
1 −k
i
C12–on
=
I
O
1 −k
, i
C12–off
=
k
1 −k
i
C12–on
=
kI
O
1 −k
.
If inductance L
1
is large enough, i
L1
is nearly equal to its average current I
L1
. Therefore,
i
in–off
= I
L1
=
2I
O
1 −k
, i
in–on
= I
L1
+
I
O
k
=
_
2
1 −k
+
1
k
_
I
O
=
1 +k
k(1 −k)
I
O
.
Veriﬁcation: I
in
= ki
in–on
+(1 −k)i
in–off
=
_
1 +k
1 −k
+2
_
I
O
=
3 −k
1 −k
I
O
.
Considering
V
in
I
in
=
_
1 −k
2 −k
_
2
V
O
I
O
=
_
1 −k
2 −k
_
2
R,
the variation of current i
L1
is Δi
L1
= kTV
in
/L
1
.
Therefore, the variation ratio of current I
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)TV
in
4L
1
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
1
. (7.70)
SuperLift Converters and Ultralift Converter 317
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
14
=
I
O
kT
C
14
=
k
fC
14
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
14
. (7.71)
7.2.4.2 ReLift ReEnhanced Circuit
This circuit is derived from the relift circuit of the main series by adding the DEC twice in
each stage circuit. Its circuit and switchon and switchoff equivalent circuits are shown in
Figure 7.11.
I
in
(a)
(b)
(c)
I
in
V
in
V
in
V
in
V
in
V
1
C
12
V
1
L
1
C
1
L
1
C
1
C
11
C
3
C
22
C
24
C
4
C
13
C
23
R
C
14
C
2
C
2
C
1
C
11
C
2
V
C1
C
11
C
12
C
14
C
4
C
13
C
21
C
21
C
22
C
24
C
23
C
3
L
2
D
1
D
3
D
2
D
4
D
5
D
12
D
11
D
13
D
14
D
21
D
22
D
23
D
24
+
–
+
–
I
in
V
in
+
–
+
–
V
1
+
–
+
–
–
+
V
1 V
C12
V
C14
V
C4
V
C22
V
C4
V
C24
V
C22
C
21
V
C12
V
C14
–
– +
+
+
–
+
–
+
–
– +
+
–
+
–
–
+
+
–
+
–
C
12
V
1
+
–
C
13
V
C12
+
–
C
14
C
3
C
4
V
C12
+
–
V
C14
L
2
+
–
V
C14
+
–
C
21
V
C4
+
–
C
22
V
C4
+
C
23
+
–
V
C22
–
C
24
+
V
C22
–
R
+
V
C24
–
+
–
+
–
+
–
V
C11
+
–
V
C2
+
–
V
C12
+
–
V
C14
+
–
+
–
+
–
V
C4
V
C13
V
3
+
–
V
C23
V
C22
V
O
V
C24
I
O
+
– +
–
V
O
I
O
+
–
V
O
I
O
+
–
V
1
V
1
L
1
L
2
S
R
FIGURE 7.11 Relift reenhanced circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 239. With permission.)
318 Power Electronics
The voltage across capacitor C
14
is
V
C14
=
4 −k
1 −k
V
in
. (7.72)
By the same analysis
V
O
=
4 −k
1 −k
V
C14
=
_
4 −k
1 −k
_
2
V
in
. (7.73)
The voltage transfer gain is
G =
V
O
V
in
=
_
4 −k
1 −k
_
2
. (7.74)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
3 −k
(1 −k)
2
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
2(3 −k)L
1
I
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
1
. (7.75)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
4L
2
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
2
. (7.76)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
24
=
I
O
kT
C
24
=
k
fC
24
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
24
. (7.77)
7.2.4.3 TripleLift ReEnhanced Circuit
This circuit is derived fromthe triplelift circuit of the main series by adding the DECtwice
in each stage circuit. Its circuit and switchon and switchoff equivalent circuits are shown
in Figure 7.12.
SuperLift Converters and Ultralift Converter 319
I
in
(a)
(b)
(c)
V
in
L
1 C
1
C
2
C
12
C
14
D
3
C
22
C
24
D
6
C
6
C
32
C
34
C
4
V
C1
C
11
C
13 C
3
L
3
C
5
C
33
C
31
C
21
C
23
L
2
D
1
D
2
D
12
D
13
D
14
D
4
D
5
D
21
D
22
D
23
D
24
D
7
D
8
D
31
D
32
D
33
D
34
I
O
D
11
+
I
in
V
in
V
in
V
1
V
1
L
1
C
1
C
2
+
–
I
in
L
1
C
1
C
2
C
12
C
11
C
13
L
2
C
14
C
4
C
22
C
3
C
21
C
23
C
5
C
31
C
34
C
6
C
32
L
3
C
33
C
24
V
C12 V
C14
V
C4
V
4
V
in V
1
V
in
V
1
V
C12
V
1
+
+
+
_ _
_
+
+
_
V
C12
+
_
V
C4
+
_
V
C22
V
C24
V
C24
+
_
_
_
+ +
+
+
V
C6
V
C32
V
C32
_
_
+
+
V
C6
_
+
_
+
V
C34
_
+
+
+
_
_
_
_
–
+
C
11
+
– –
V
1
V
C12
C
12
C
13
+ +
– –
V
C12
C
14
C
3
C
4
+
–
V
C14 V
C14
L
2
+ +
– –
C
21
V
C4
+
–
C
22
V
C4
+
–
C
23
C
6
C
5
V
C22
+
–
C
24
L
3
V
C22
V
C24
V
C24
+
+
– – –
C
32
V
C6
+
C
31
+
–
V
C6
–
C
33
+
C
34
+
R
+
V
C32
V
C32
V
C34
– – –
–
+
–
V
C2
+
–
V
C12
+
–
V
C14
+
–
V
C4
+
–
V
C22
+
–
V
C24
+
–
V
C6
V
C32
+
–
+
–
V
C34
+
–
+
–
+
–
V
C11
V
C13
+
–
V
C3
+
–
V
C21
+
–
V
C23
+
–
+
–
V
C5
V
C31
+
–
V
C33
+
–
V
O
I
O
+
–
V
O
I
O
+
–
V
O
V
1
S
R
R
FIGURE 7.12 Triplelift reenhanced circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 240. With permission.)
The voltage across capacitor C
14
is
V
C14
=
4 −k
1 −k
V
in
. (7.78)
The voltage across capacitor C
24
is
V
C24
=
_
4 −k
1 −k
_
2
V
in
. (7.79)
By the same analysis
V
O
=
4 −k
1 −k
V
C24
=
_
4 −k
1 −k
_
3
V
in
. (7.80)
The voltage transfer gain is
G =
V
O
V
in
=
_
4 −k
1 −k
_
3
. (7.81)
320 Power Electronics
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
(2 −k)(3 −k)
(1 −k)
3
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
3 −k
(1 −k)
2
I
O
,
Δi
L3
=
V
2
L
3
kT, I
L3
=
2I
O
1 −k
.
Considering
V
in
I
in
=
_
1 −k
2 −k
_
2
V
O
I
O
=
_
1 −k
2 −k
_
2
R,
the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
2(2 −k)(3 −k)L
1
I
O
=
k(1 −k)
3
T
2(2 −k)(3 −k)L
1
I
O
(1 −k)
3
(2 −k)
2
(3 −k)
V
O
=
k(1 −k)
6
2(2 −k)
3
(3 −k)
2
R
f L
1
. (7.82)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
2(3 −k)L
2
I
O
=
k(1 −k)
2
T
2(3 −k)L
2
I
O
(1 −k)
2
(2 −k)(3 −k)
V
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
2
.
(7.83)
The variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
4L
3
I
O
=
k(1 −k)T
4L
3
I
O
1 −k
3 −k
V
O
=
k(1 −k)
2
4(3 −k)
R
f L
3
. (7.84)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
34
=
I
O
kT
C
34
=
k
fC
34
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
34
. (7.85)
7.2.4.4 HigherOrder Lift ReEnhanced Circuit
The higherorder lift additional circuit is derived from the corresponding circuits of the
main series by adding the DEC twice in each stage circuit. For the nthorder lift additional
circuit, the ﬁnal output voltage is V
O
= ((4 −k)/(1 −k))
n
V
in
.
SuperLift Converters and Ultralift Converter 321
The voltage transfer gain is
G =
V
O
V
in
=
_
4 −k
1 −k
_
n
. (7.86)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
2[2(2 −k)]
h(n−i)
(2 −k)
2(n−i)+1
(3 −k)
2u(n−i−1)
R
f L
i
, (7.87)
where
h(x) =
_
0 x > 0
1 x ≤ 0
is the Hong function
and
u(x) =
_
1 x ≥ 0
0 x < 0
is the unitstep function,
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n4
. (7.88)
7.2.5 MultipleEnhanced Series
All circuits of P/O SL Luoconverters—multipleenhanced series—are derived from the
corresponding circuits of the main series by adding the DEC multiple ( j) times in circuits
of each stage. The ﬁrst three stages of this series are shown in Figures 7.13 through 7.15.
For ease of understanding, they are called the elementary multipleenhanced circuit, the
relift multipleenhanced circuit, and the triplelift multipleenhanced circuit, respectively,
and numbered n = 1, 2, and 3, respectively.
7.2.5.1 Elementary MultipleEnhanced Circuit
This circuit is derived from the elementary circuit of the main series by adding the DEC
multiple (j) times. Its circuit and switchon and switchoff equivalent circuits are shown in
Figure 7.13.
The output voltage is
V
O
=
j +2 −k
1 −k
V
in
. (7.89)
The voltage transfer gain is
G =
V
O
V
in
=
j +2 −k
1 −k
. (7.90)
322 Power Electronics
I
in D
1
L
1
L
1
V
1
V
C12
V
1
V
L1
V
in
V
1
L
1
V
in
C
1
C
11
(c)
(b)
(a)
C
1
C
12
C
2
C
2
C
11
C
1
C
11
C
1(2j–1)
C
1(2j–1)
C
12j
V
C1(2j–1)
D
1(2j–1)
D
12j
C
2
C
12
C
12j
V
C1
V
in
V
1
V
C11
+
+
+
–
+
–
+
– +
+
–
–
V
C2
V
C12
+
+
– –
–
–
–
–
– + V
C1(2j–1)
V
C12j
C
1(2j–1)
C
12j
– +
+
–
+
–
+
–
+
–
+
+
I
in
V
in
+
–
I
in
V
in
+
–
V
1
+
–
V
1
+
–
V
C1(2j–1)
V
C12j
+ +
– –
+
–
D
2
D
12
D
11
V
1
2.. j 1
S
R
I
O
I
O
I
O
V
O
V
C12j
R
V
O
R
V
O
FIGURE 7.13 Elementary multipleenhancedcircuit of P/OSLLuoconverters: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 246. With permission.)
The following relations are obtained:
i
in–off
= I
L1
= i
C11–off
+i
C1–off
=
2I
O
1 −k
, i
in–on
= i
L1–on
+i
C1–on
= I
L1
+
I
O
k
,
i
C1–on
=
1 −k
k
i
C1–off
=
I
O
k
, i
C1–off
= i
C2–off
=
I
O
1 −k
,
i
C2–off
=
k
1 −k
i
C2–on
=
k
1 −k
i
C11–on
=
I
O
1 −k
, i
C11–on
=
1 −k
k
i
C11–off
=
I
O
k
,
i
C11–off
= I
O
+i
C12–off
= I
O
+
k
1 −k
i
C12–on
=
I
O
1 −k
, i
C12–off
=
k
1 −k
i
C12–on
=
kI
O
1 −k
.
SuperLift Converters and Ultralift Converter 323
If inductance L
1
is large enough, i
L1
is nearly equal to its average current I
L1
. Therefore,
i
in–off
= I
L1
=
2I
O
1 −k
, i
in–on
= I
L1
+
I
O
k
=
_
2
1 −k
+
1
k
_
I
O
=
1 +k
k(1 −k)
I
O
.
Veriﬁcation: I
in
= ki
in–on
+(1 −k)i
in–off
=
_
1 +k
1 −k
+2
_
I
O
=
3 −k
1 −k
I
O
.
Considering
V
in
I
in
=
_
1 −k
2 −k
_
2
V
O
I
O
=
_
1 −k
2 −k
_
2
R,
the variation of current i
L1
is Δi
L1
= kTV
in
/L
1
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)TV
in
4L
1
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
1
. (7.91)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12j
=
I
O
kT
C
12j
=
k
fC
12j
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12j
. (7.92)
7.2.5.2 ReLift MultipleEnhanced Circuit
This circuit is derived fromthe relift circuit of the main series by adding the DEC multiple
(j) times in each stage circuit. Its circuit diagram and switchon and switchoff equivalent
circuits are shown in Figure 7.14.
The voltage across capacitor C
12j
is
V
C12j
=
j +2 −k
1 −k
V
in
. (7.93)
The output voltage across capacitor C
22j
is
V
O
= V
C22j
=
_
j +2 −k
1 −k
_
2
V
in
. (7.94)
The voltage transfer gain is
G =
V
O
V
in
=
_
j +2 −k
1 −k
_
2
. (7.95)
324 Power Electronics
I
in
V
in
+
+
–
–
D
1
L
1 L
2
C
1
C
11
C
3
C
21
C
2(2j–1) V
C2(2j–1)
V
C22j
V
C22
V
C12j
C
22j
V
C3
V
C21
C
1(2j–1) V
C1
+
–
+
–
+
–
+
–
+
–
–
+
+
–
+
–
+
–
+
V
C12
–
+
V
C2
–
+
–
V
C11
D
4
D
5
D
21
D
22
D
22j
D
2(2j–1)
D
2
D
12
D
11
V
1
(a)
D
1(2j–1)
D
12j
R
D
6
S
V
O
I
O
I
in
+
V
in
V
in
–
+
+
–
L
1
C
1
C
2
V
1
–
+
–
C
11
V
1
–
+
–
V
C1(2j–1)
+ +
–
V
C12j
V
C3
L
2
–
+ +
–
V
C21
– –
+
–
+
–
– –
C
1(2j–1)
C
12j
C
3
C
4
+
V
C4
C
21
C
2(2j–1)
V
C2(2j–1)
C
22j
V
C22j
(b) V
C12
R
V
O
I
O
C
22
V
C4
C
4
C
12j
D
3
C
12
C
2
V
L1
V
in
V
1
V
C12
V
C1(2j–1)
C
1(2j–1)
C
12j
C
3
C
22
C
22j
V
C22j
C
4 V
1
L
2
C
21
C
2(2j–1)
V
L2
–V
C21
V
C4
V
C22
V
C2(2j–1)
V
C3
V
1
C
11
C
12
C
1
C
2
I
in
+
+ –
– +
+
–
+
+
+
+
+
+
+ –
–
+
–
–
–
– +
–
–
V
C12j
+
–
V
in
–
– +
L
1
(c)
+
–
V
O
I
O
R
V
C1(2j–1)
FIGURE 7.14 Relift multipleenhanced circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 247. With permission.)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
3 −k
(1 −k)
2
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
2(3 −k)L
1
I
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
1
(7.96)
and the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
4L
2
I
O
=
k(1 −k)
2
4(3 −k)
R
f L
2
. (7.97)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
22j
=
I
O
kT
C
22j
=
k
fC
22j
V
O
R
.
SuperLift Converters and Ultralift Converter 325
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
22j
. (7.98)
7.2.5.3 TripleLift MultipleEnhanced Circuit
This circuit is derived from the triplelift circuit of the main series by adding the DEC
multiple (j) times in each stage circuit. Its circuit and switchon and switchoff equivalent
circuits are shown in Figure 7.15.
The voltage across capacitor C
12j
is
V
C12j
=
j +2 −k
1 −k
V
in
. (7.99)
The voltage across capacitor C
22j
is
V
C22j
=
_
j +2 −k
1 −k
_
2
V
in
. (7.100)
By the same analysis,
V
O
=
j +2 −k
1 −k
V
C22j
=
_
j +2 −k
1 −k
_
3
V
in
. (7.101)
I
in
I
in
V
in
V
L1
V
in
V
1
V
1
V
1
L
2
L
3
C
21
C
31
C
3(2j–1)
C
2(2j–1)
+
–
+
–
+ +
+
+
–
– –
–
–
V
C1(2j–1)
–
–
–
–
+
+
–
+
+
+
+ +
+
–
–
V
in
+
–
D
1
D
4
D
5
D
21
D
22
L
1
L
1
C
1
C
12
C
12j
C
3
C
22
C
22j
C
5
C
32
C
6
V
L3
V
C6
V
C32
V
C32j
V
C3(2j–1)
C
32j
V
C31
V
C5
C
4
C
11
C
1(2j–1)
C
2
C
1
C
11 C
1(2j–1)
C
3
C
21
C
2
C
12 V
C2
+
–
V
D12
+
–
V
C12
+
–
V
C4
+
–
+
–
V
C22
V
C22j
+
–
V
C6
+
–
V
C32
+
–
V
C32j
C
12j
V
D3
V
C1
+
–
+
–
+
–
V
C11
V
C3
+
–
+
–
+ +
– –
+
+
–
–
V
C21
L
2
C
4
C
22
C
22j
C
6 C
32
C
32j
D
7
D
8
D
31
C
31
D
3(2j–1)
D
32j
D
32
D
2
D
12
D
11
V
1 (a)
(c)
D
1(2j–1)
D
2(2j–1)
D
22j
C
2(2j–1)
D
12j
L
3 C
5 V
C5
V
C3(2j–1)
V
C3(2j–1)
V
C31
I
O
V
O
V
C2(2j–1)
D
6
S
R
I
in
V
in
+
+
–
+
–
–
V
in
V
1
V
1
+
–
V
1
+
–
+ +
–
–
V
C1(2j–1)
L
1
C
1
C
2
C
11
C
1(2j–1)
(b)
C
12j
V
C12j
V
C3
L
2
C
3
C
4
+
–
+
–
+
–
+
–
+
–
C
21
C
5
C
31
C
6
V
C4
V
C21 V
C2(2j–1)
C
2(2j–1)
V
C22j
+
–
V
C5
V
C6
+
–
+
–
+
–
+
–
C
22j
L
3
C
3(2j–1)
C
32j
V
C31 V
C3(2j–1)
V
C32j
R
V
O
I
O
V
C12
V
L2
V
C12j
V
C21
– +
+ +
+
+
+
–
+
–
– +
+ +
–
R
V
O
I
O
– –
– +
–
–
V
C2(2j–1)
V
C4
V
C3
V
C22 V
C22j
V
C11
FIGURE 7.15 Triplelift multipleenhanced circuit of P/O SL Luoconverters: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 248. With permission.)
326 Power Electronics
The voltage transfer gain is
G =
V
O
V
in
=
_
j +2 −k
1 −k
_
3
. (7.102)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
(2 −k)(3 −k)
(1 −k)
3
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
3 −k
(1 −k)
2
I
O
.
Δi
L3
=
V
2
L
3
kT, I
L3
=
2I
O
1 −k
.
Considering
V
in
I
in
=
_
1 −k
2 −k
_
2
V
O
I
O
=
_
1 −k
2 −k
_
2
R,
the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
2(2 −k)(3 −k)L
1
I
O
=
k(1 −k)
3
T
2(2 −k)(3 −k)L
1
I
O
(1 −k)
3
(2 −k)
2
(3 −k)
V
O
=
k(1 −k)
6
2(2 −k)
3
(3 −k)
2
R
f L
1
. (7.103)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
2(3 −k)L
2
I
O
=
k(1 −k)
2
T
2(3 −k)L
2
I
O
(1 −k)
2
(2 −k)(3 −k)
V
O
=
k(1 −k)
4
2(2 −k)(3 −k)
2
R
f L
2
. (7.104)
The variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
4L
3
I
O
=
k(1 −k)T
4L
3
I
O
1 −k
3 −k
V
O
=
k(1 −k)
2
4(3 −k)
R
f L
3
. (7.105)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
32j
=
I
O
kT
C
32j
=
k
fC
32j
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
32j
. (7.106)
SuperLift Converters and Ultralift Converter 327
7.2.5.4 HigherOrder Lift MultipleEnhanced Circuit
The higherorder lift multipleenhanced circuit can be derived from the corresponding
circuits of the main series converters by adding the DEC multiple (j) times in each stage
circuit. For the nthorder lift additional circuit, the ﬁnal output voltage is
V
O
=
_
j +2 −k
1 −k
_
n
V
in
.
The voltage transfer gain is
G =
V
O
V
in
=
_
j +2 −k
1 −k
_
n
. (7.107)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
2[2(2 −k)]
h(n−i)
(2 −k)
2(n−i)+1
(3 −k)
2u(n−i−1)
R
f L
i
, (7.108)
where
h(x) =
_
0 x > 0
1 x ≤ 0
is the Hong function
and
u(x) =
_
1 x ≥ 0
0 x < 0
is the unitstep function.
The variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n2j
. (7.109)
7.2.6 Summary of P/O SL LuoConverters
All circuits of P/O SL Luoconverters can be shown in Figure 7.16 as the family tree.
From the analysis in previous sections, the common formula to calculate the output
voltage can be presented as
V
O
=
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
_
2 −k
1 −k
_
n
V
in
main series,
_
2 −k
1 −k
_
n−1
_
3 −k
1 −k
_
V
in
additional series,
_
3 −k
1 −k
_
n
V
in
enhanced series,
_
4 −k
1 −k
_
n
V
in
reenhanced series,
_
j +2 −k
1 −k
_
n
V
in
multipleenhanced series.
(7.110)
328 Power Electronics
Quintuplelift
circuit
Quadruplelift
circuit
Triplelift
circuit
Relift circuit
Quintuplelift
additional circuit
Quadruplelift
additional circuit
Triplelift
additional circuit
Relift additional
circuit
Quintuplelift
enhanced circuit
Quadruplelift
enhanced circuit
Triplelift
enhanced circuit
Relift enhanced
circuit
Quintuplelift
reenhanced circuit
Quadruplelift
reenhanced circuit
Triplelift
reenhanced circuit
Relift
reenhanced circuit
Quintuplelift mulitple
enhanced circuit
Quadruplelift mulitple
enhanced circuit
Triplelift mulitple
enhanced circuit
Relift mulitple
enhanced circuit
Elementary mulitple
enhanced circuit
Elementary
reenhanced circuit
Elementary additional/enhanced
circuit
Elementary positive output superlift Luoconverter
Main
series
Additional
series
Enhanced
series
Reenhanced
series
Multipleenhanced
series
FIGURE 7.16 The family of P/O SL Luoconverters. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 255. With permission.)
The voltage transfer gain is
G =
V
O
V
in
=
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
_
2 −k
1 −k
_
n
main series,
_
2 −k
1 −k
_
n−1
_
3 −k
1 −k
_
additional series,
_
3 −k
1 −k
_
n
enhanced series,
_
4 −k
1 −k
_
n
reenhanced series,
_
j +2 −k
1 −k
_
n
multipleenhanced series.
(7.111)
In order to show the advantages of the SL Luoconverters, their voltage transfer gains can
be compared with that of other converters:
Buck converter: G = V
O
/V
in
= k.
Forward converter: G = V
O
/V
in
= kN, where N is the transformer turn’s ratio.
SuperLift Converters and Ultralift Converter 329
Cúkconverter: G = V
O
/V
in
= k/(1 −k).
Flyback converter: G = V
O
/V
in
= (k/(1 −k))N, where N is the transformer turn’s
ratio.
Boost converter: G = V
O
/V
in
= 1/(1 −k).
P/O Luoconverters:
G =
V
O
V
in
=
n
1 −k
. (7.112)
Assume that the conduction duty cycle k is 0.2; the output voltage transfer gains are listed
in Table 7.1. Similarly, for k = 0.5 and 0.8, the output voltage transfer gains are listed in
Tables 7.2 and 7.3.
7.3 N/O SL LuoConverters
The N/O SL Luoconverters were developed at the same time as the P/O SL Luo
converters. They too perform the SL technique. Only three circuits from each subseries
will be introduced in this section [1,2,5,6].
TABLE 7.1
Voltage Transfer Gains of Converters in the Condition k = 0.2
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.2
Forward converter 0.2N (N is the transformer turn’s ratio)
Cúkconverter 0.25
Flyback converter 0.25N (N is the transformer turn’s ratio)
Boost converter 1.25
P/O Luoconverters 1.25 2.5 3.75 5 6.25 1.25n
P/O SL Luoconverters—main
series
2.25 5.06 11.39 25.63 57.67 2.25
n
P/O SL
Luoconverters—additional
series
3.5 7.88 17.72 39.87 89.7 3.5 ×2.25
(n−1)
P/O SL
Luoconverters—enhanced
series
3.5 12.25 42.88 150 525 3.5
n
P/O SL
Luoconverters—reenhanced
series
4.75 22.56 107.2 509 2418 4.75
n
P/O SL
Luoconverters—multiple
( j = 4)enhanced series
7.25 52.56 381 2762 20,030 7.25
n
Source: Data from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters, p. 256. Boca Raton: Taylor &
Francis Group LLC.
330 Power Electronics
TABLE 7.2
Voltage Transfer Gains of Converters in the Condition k = 0.5
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.5
Forward converter 0.5N (N is the transformer turn’s ratio)
Cúkconverter 1
Flyback converter N (N is the transformer turn’s ratio)
Boost converter 2
P/O Luoconverters 2 4 6 8 10 2n
P/O SL Luoconverters—main
series
3 9 27 81 243 3
n
P/O SL
Luoconverters—additional
series
5 15 45 135 405 5 ×3
(n−1)
P/O SL
Luoconverters—enhanced
series
5 25 125 625 3125 5
n
P/O SL
Luoconverters—reenhanced
series
7 49 343 2401 16,807 7
n
P/O SL
Luoconverters—multiple
( j = 4)enhanced series
11 121 1331 14, 641 16 ×10
4
11
n
Source: Data fromLuo, F. L. andYe, H. 2006. Essential DC/DCConverters, p. 257. Boca Raton: Taylor &Francis
Group LLC.
7.3.1 Main Series
The ﬁrst three stages of N/O SL Luoconverters—main series—are shown in Figures 7.17
through 7.19. For ease of understanding, they are called the elementary circuit, the relift
circuit, andthe triplelift circuit, respectively, andare numberedn = 1, 2, and3, respectively.
7.3.1.1 N/O Elementary Circuit
The N/O elementary circuit and its equivalent circuits during switchon and switchoff
periods are shown in Figure 7.17.
The voltage across capacitor C
1
is chargedwithV
in
. The current ﬂowing throughinductor
L
1
increases along the slope V
in
/L
1
during the switchon period kT and decreases along
the slope −(V
O
−V
in
)/L
1
during the switchoff period (1 −k)T. Therefore, the variation of
current i
L1
is
Δi
L1
=
V
in
L
1
kT =
V
O
−V
in
L
1
(1 −k)T, (7.113)
V
O
=
1
1 −k
V
in
=
_
2 −k
1 −k
−1
_
V
in
. (7.114)
SuperLift Converters and Ultralift Converter 331
TABLE 7.3
Voltage Transfer Gains of Converters in the Condition k = 0.8
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.8
Forward converter 0.8N (N is the transformer turn’s ratio)
Cúkconverter 4
Flyback converter 4N (N is the transformer turn’s ratio)
Boost converter 5
P/O Luoconverters 5 10 15 20 25 5n
P/O SL Luoconverters—main
series
6 36 216 1296 7776 6
n
P/O SL
Luoconverters—additional
series
11 66 396 2376 14,256 11 ×6(n −1)
P/O SL
Luoconverters—enhanced
series
11 121 1331 14,641 16 ×10
4
11
n
P/O SL
Luoconverters—reenhanced
series
16 256 4096 65,536 104 ×10
4
16
n
P/O SL
Luoconverters—multiple
( j = 4)enhanced series
26 676 17, 576 46 ×10
4
12 ×10
6
26
n
Source: Data fromLuo, F. L. andYe, H. 2006. Essential DC/DCConverters, p. 257. Boca Raton: Taylor &Francis
Group LLC.
The voltage transfer gain is
G
1
=
V
O
V
in
=
2 −k
1 −k
−1. (7.115)
In the steady state, the average charge across the capacitor C
1
in a period should be zero.
The following relations are available:
kTi
C1–on
= (1 −k)Ti
C1–off
and i
C1–on
=
1 −k
k
i
C1–off
.
These relations are available for all the capacitors’ current in switchon and switchoff
periods.
The input current i
in
is equal to (i
L1
+i
C1
) during the switchon period and zero during
the switchoff period. The capacitor current i
C1
is equal to i
L1
during switchoff.
i
in–on
= i
L1–on
+i
C1–on
, i
L1–off
= i
C1–off
= I
L1
.
If inductance L
1
is large enough, i
L1
is nearly equal to its average current I
L1
. Therefore,
i
in–on
= i
L1–on
+i
C1–on
= i
L1–on
+
1 −k
k
i
C1–off
=
_
1 +
1 −k
k
_
I
L1
=
1
k
I
L1
and
I
in
= ki
in–on
= I
L1
. (7.116)
332 Power Electronics
I
in
I
in
V
in
+ +
+
–
–
–
V
in
+
–
V
in
V
L1
+
–
V
in
+
–
V
in
+
–
D
1
L
1
L
1
L
1
S
R
R
C
1
C
1
C
1
V
C1
V
C2
+
–
V
C2
+
–
D
2
(a)
(b)
(c)
V
O
+
–
V
O
I
O
I
O
R
+
–
V
C2
+
–
V
O
I
O
C
2
C
2
C
2
FIGURE 7.17 Elementary circuit of N/O SL Luoconverters—main series: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 264. With permission.)
Further,
i
C2–on
= I
O
, i
C2–off
=
k
1 −k
I
O
,
I
L1
= i
C2–off
+I
O
=
k
1 −k
i
C2–on
+I
O
=
1
1 −k
I
O
.
The variation ratio of inductor current i
L1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)TV
in
2L
1
I
O
=
k(1 −k)
G
1
R
2f L
1
. (7.117)
Usually ξ
1
is small (much lower than unity); this means that this converter works in the
CCM.
SuperLift Converters and Ultralift Converter 333
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
2
=
I
O
kT
C
2
=
k
fC
2
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
2
. (7.118)
7.3.1.2 N/O ReLift Circuit
The N/O relift circuit is derived from the N/O elementary circuit by adding the parts
(L
2
D
3
D
4
D
5
C
3
C
4
). Its circuit diagram and equivalent circuits during switchon and
switchoff periods are shown in Figure 7.18.
The voltage across capacitor C
1
is charged to V
in
. As described in the previous section,
the voltage V
1
across capacitor C
2
is V
1
= (1/(1 −k))V
in
.
I
in
I
in
V
in
V
1
V
1
V
1
V
1
V
L2
V
L1
V
C4
V
1
+V
in
V
in
V
1
V
C1
V
C2
V
C3
V
O
I
O
+
–
V
in
V
in
+
–
+
+V
1
+V
in
–
–
+
–
–
+
V
in
+
–
+
+
–
+
–
–
+
–
+
–
+
–
+
–
+
–
D
1
D
3
D
4
D
5 D
2
L
1
L
2
C
3
L
1
L
2
L
1
L
2
S
C
1
C
1
C
1
C
2
C
3
C
2
C
2
C
3
C
4
(a)
(b)
(c)
R
C
4
C
4
V
C4
V
O
I
O
I
O
+
–
+
–
R
V
C4
–
+
V
O R
FIGURE 7.18 Relift circuit of N/O SL Luoconverters—main series: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 265. With permission.)
334 Power Electronics
I
in
V
in
V
C1
V
C3
L
1
L
2
V
1
V
C5
V
2
C
1
C
3
C
5
R
L
3
I
O
+
+ +
+
–
+
+
–
– –
–
–
I
in
V
in
V
L1
V
1
V
2
V
1
V
L2
V
L3
V
1
V
1
+V
in
V
2
+V
in
V
1
+V
in
L
1
L
2
L
3
C
1
C
1
C
2
C
2
C
3
C
3
C
5
C
4
C
6
C
5
C
6
C
4
L
2
L
3
+
–
V
in
V
in +
+ –
–
V
1
+
+ –
+ –
–
V
2
–
+
V
C6
–
+
V
in
+
–
+
+
+
–
–
+
–
–
V
2
V
2
V
C6
+
–
S
D
3
D
6
D
4
C
4
D
5
D
7
D
8
D
6
D
2
C
2 V
C2
+
–
+
–
V
C4
V
O
I
O
+
–
V
O
I
O
+
–
V
O
V
C6
D
1
(a)
(b)
(c)
R
R
L
1
V
2
+V
in
FIGURE 7.19 Triplelift circuit of N/OSLLuoconverters—main series: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 266. With permission.)
The voltage across capacitor C
3
is charged with (V
1
+V
in
). The current ﬂowing through
inductor L
2
increases along the slope (V
1
+V
in
)/L
2
during the switchon period kT and
decreases along the slope −(V
O
−2V
1
−V
in
)/L
2
during the switchoff period (1 −k)T.
Therefore, the variation of current i
L2
is
Δi
L2
=
V
1
+V
in
L
2
kT =
V
O
−2V
1
−V
in
L
2
(1 −k)T, (7.119)
V
O
=
(2 −k)V
1
+V
in
1 −k
=
_
_
2 −k
1 −k
_
2
−1
_
V
in
. (7.120)
The voltage transfer gain is
G
2
=
V
O
V
in
=
_
2 −k
1 −k
_
2
−1. (7.121)
SuperLift Converters and Ultralift Converter 335
The input current i
in
is equal to (i
L1
+i
C1
+i
L2
+i
C3
) during the switchon period and is
zero during the switchoff period. In the steady state, the following relations are available:
i
in–on
= i
L1–on
+i
C1–on
+i
L2–on
+i
C3–on
,
i
C4–on
= I
O
, i
C4–off
=
k
1 −k
I
O
,
i
C3–off
= I
L2
= I
O
+i
C4–off
=
I
O
1 −k
, i
C3–on
=
I
O
k
,
i
C2–on
= I
L2
+i
C3–on
=
I
O
1 −k
+
I
O
k
=
I
O
k(1 −k)
, i
C2–off
=
I
O
(1 −k)
2
,
i
C1–off
= I
L1
= I
L2
+i
C2–off
=
I
O
1 −k
+
I
O
(1 −k)
2
=
2 −k
(1 −k)
2
I
O
, i
C1–on
=
2 −k
k(1 −k)
I
O
.
Thus,
i
in–on
= i
L1–on
+i
C1–on
+i
L2–on
+i
C3–on
=
1
k
(I
L1
+I
L2
) =
3 −2k
k(1 −k)
2
I
O
.
Therefore,
I
in
= ki
in–on
=
3 −2k
(1 −k)
2
I
O
.
Since
Δi
L1
=
V
in
L
1
kT, I
L1
=
2 −k
(1 −k)
2
I
O
,
Δi
L2
=
V
1
+V
in
L
2
kT =
2 −k
1 −k
kT
L
2
V
in
, I
L2
=
1
1 −k
I
O
.
Therefore, the variation ratio of current I
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
kTV
in
(2 −k/(1 −k)
2
)2L
1
I
O
=
k(1 −k)
2
(2 −k)G
2
R
2f L
1
. (7.122)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(2 −k)TV
in
2L
2
I
O
=
k(2 −k)
G
2
R
2f L
2
. (7.123)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
4
=
I
O
kT
C
4
=
k
fC
4
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
4
. (7.124)
336 Power Electronics
Example 7.3
An N/O relift circuit in Figure 7.18a has V
in
= 20V, all inductors have 10mH, all capacitors have
20μ F, R = 200Ω, f = 50kHz, and conduction duty cycle k = 0.6. Calculate the variation ratio
of current I
L1
, and the output voltage and its variation ratio.
SOLUTION
From Equation 7.122, we can obtain the variation ratio of current i
L1
:
ξ
1
=
k(1 −k)
3
(2 −k)
2
R
2f L
1
=
0.6(1 −0.6)
3
(2 −0.6)
2
200
2 ×50k ×10m
= 0.0039.
From Equation 7.120, we can obtain the output voltage:
V
O
=
_
_
2 −k
1 −k
_
2
−1
_
V
in
=
_
_
2 −0.6
1 −0.6
_
2
−1
_
×20 = 225V.
From Equation 7.124, its variation ratio is
ε =
k
2RfC
4
=
0.6
2 ×200 ×50k ×20μ
= 0.0015.
7.3.1.3 N/OTripleLift Circuit
The N/O triplelift circuit is derived from the N/O relift circuit by twice repeating the
parts (L
2
D
3
D
4
D
5
C
3
C
4
). Its circuit diagram and equivalent circuits during switchon
and switchoff periods are shown in Figure 7.19.
The voltage across capacitor C
1
is charged with V
in
. As described in the previous section,
the voltage V
1
across capacitor C
2
is V
1
= (((2 −k)/(1 −k)) −1)V
in
= (1/(1 −k))V
in
, and
the voltage V
2
across capacitor C
4
is
V
2
=
_
_
2 −k
1 −k
_
2
−1
_
V
in
=
3 −2k
(1 −k)
2
V
in
.
The voltage across capacitor C
5
is charged with (V
2
+V
in
). The current ﬂowing through
inductor L
3
increases along the slope (V
2
+V
in
)/L
3
during the switchon period kT and
decreases along the slope −(V
O
−2V
2
−V
in
)/L
3
during the switchoff period (1 −k)T.
Therefore, the variation of current i
L3
is
Δi
L3
=
V
2
+V
in
L
3
kT =
V
O
−2V
2
−V
in
L
3
(1 −k)T, (7.125)
V
O
=
(2 −k)V
2
+V
in
1 −k
=
_
_
2 −k
1 −k
_
3
−1
_
V
in
. (7.126)
The voltage transfer gain is
G
3
=
V
O
V
in
=
_
2 −k
1 −k
_
3
−1. (7.127)
SuperLift Converters and Ultralift Converter 337
The input current i
in
is equal to(i
L1
+i
C1
+i
L2
+i
C3
+i
L3
+i
C5
) duringthe switchonperiod
and is zero during the switchoff period. In the steady state, the following relations are
available:
i
in–on
= i
L1–on
+i
C1–on
+i
L2–on
+i
C3–on
+i
L3–on
+i
C5–on
,
i
C6–on
= I
O
, i
C6–off
=
k
1 −k
I
O
,
i
C5–off
= I
L3
= I
O
+i
C6–off
=
I
O
1 −k
, i
C5–on
=
I
O
k
,
i
C4–on
= I
L3
+i
C5–on
=
I
O
1 −k
+
I
O
k
=
I
O
k(1 −k)
, i
C4–off
=
I
O
(1 −k)
2
,
i
C3–off
= I
L2
= I
L3
+i
C4–off
=
2 −k
(1 −k)
2
I
O
, i
C3–on
=
2 −k
k(1 −k)
I
O
,
i
C2–on
= I
L2
+i
C3–on
=
2 −k
k(1 −k)
2
I
O
, i
C2–off
=
2 −k
(1 −k)
3
I
O
,
i
C1–off
= I
L1
= I
L2
+i
C2–off
=
(2 −k)
2
(1 −k)
3
I
O
, i
C1–on
=
(2 −k)
2
k(1 −k)
2
I
O
.
Thus,
i
in–on
= i
L1–on
+i
C1–on
+i
L2–on
+i
C3–on
+i
L3–on
+i
C5–on
=
1
k
(I
L1
+I
L2
+I
L3
)
=
7 −9k +3k
2
k(1 −k)
3
I
O
.
Therefore,
I
in
= ki
in–on
=
7 −9k +3k
2
(1 −k)
3
I
O
=
_
_
2 −k
1 −k
_
3
−1
_
I
O
.
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
(2 −k)
2
(1 −k)
3
I
O
,
Δi
L2
=
V
1
+V
in
L
2
kT =
2 −k
(1 −k)L
2
kTV
in
, I
L2
=
2 −k
(1 −k)
2
I
O
,
Δi
L3
=
V
2
+V
in
L
3
kT =
_
2 −k
1 −k
_
2
kT
L
3
V
in
, I
L3
=
I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
2(2 −k)
2
L
1
I
O
=
k(1 −k)
3
(2 −k)
2
G
3
R
2f L
1
. (7.128)
338 Power Electronics
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
in
2L
2
I
O
=
k(1 −k)
G
3
R
2f L
2
. (7.129)
The variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(2 −k)
2
TV
in
2(1 −k)L
3
I
O
=
k(2 −k)
2
(1 −k)G
3
R
2f L
3
. (7.130)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
6
=
I
O
kT
C
6
=
k
fC
6
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
6
. (7.131)
7.3.1.4 N/O HigherOrder Lift Circuit
The N/O higherorder lift circuit can be designed by just multiple repeating of the parts
(L
2
D
3
D
4
D
5
C
3
C
4
). For the nthorder lift circuit, the ﬁnal output voltage across capacitor
C
2n
is
V
O
=
__
2 −k
1 −k
_
n
−1
_
V
in
. (7.132)
The voltage transfer gain is
G
n
=
V
O
V
in
=
_
2 −k
1 −k
_
n
−1. (7.133)
The variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
n
(2 −k)
(n−1)
G
n
R
2f L
i
, (7.134)
ξ
2
=
Δi
L2
/2
I
L2
=
k(2 −k)
(3−n)
(1 −k)
(n−3)
G
n
R
2f L
i
, (7.135)
ξ
3
=
Δi
L3
/2
I
L3
=
k(2 −k)
(n−i+2)
(1 −k)
(n−i+1)
G
n
R
2f L
3
. (7.136)
The variation ratio of the output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
2n
. (7.137)
SuperLift Converters and Ultralift Converter 339
I
in
I
in
V
in
V
C1
V
1
+V
in
V
O
I
O
+
–
V
in
V
1
V
1
+
+ –
+
+
+
–
+
–
+
–
–
–
–
V
in
+
–
V
in
V
L1
+
+
–
–
V
C12
+
–
+
–
V
O
I
O
+
–
–
+
+
–
V
C1
+
–
V
C2
–
+
D
1
D
2
D
11
D
12
C
12
C
2
C
11
L
1
L
1
L
1
S
C
1
C
1
C
1
C
11
C
2
C
12
C
2
C
12
C
11
(a)
(b)
(c)
R
R
R
V
C4
V
in
V
1
+V
in
V
1
V
C12
I
O
V
O
V
1
FIGURE 7.20 Elementary additional circuit of N/OSLLuoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 274. With permission.)
7.3.2 N/O Additional Series
All circuits of the N/O SL Luoconverters—additional series—are derived from the corre
sponding circuits of the main series by adding a DEC. The ﬁrst three stages of this series
are shown in Figures 7.20 through 7.22. For ease of understanding, they are called the ele
mentary additional circuit, the relift additional circuit, and the triplelift additional circuit,
respectively, and are numbered n = 1, 2, and 3, respectively.
7.3.2.1 N/O Elementary Additional Circuit
This circuit is derived from the N/O elementary circuit by adding a DEC. Its circuit and
switchon and switchoff equivalent circuits are shown in Figure 7.20.
The voltage across capacitor C
1
is charged with V
in
. The voltage across capacitor C
2
is charged with V
1
and C
11
is charged with (V
1
+V
in
). The current I
L1
ﬂowing through
inductor L
1
increases with the slope V
in
/L
1
during the switchon period kT and decreases
with the slope −(6.V
1
−V
in
)/L
1
during the switchoff period (1 −k)T.
Therefore,
Δi
L1
=
V
in
L
1
kT =
V
1
−V
in
L
1
(1 −k)T, (7.138)
340 Power Electronics
I
in
V
in
V
C1
V
C2
V
C4
V
1
V
1
V
2
V
2
V
2
+
+
–
V
in
+
–
V
C3
V
C11
+ +
–
V
O
–
+
–
+
–
V
C2
V
C12
V
2
+V
in
V
1
+V
in
V
2
+V
in
+
+
–
+ –
V
2
+V
in
+ –
–
V
2
+
–
+
–
+
–
V
C12
+
–
–
D
1
D
11
D
12
D
2
D
3
D
4
D
5
L
1
L
1
L
2
L
2
S
C
1
C
1
C
1
C
11
C
2
C
3
C
4
C
12
V
1
V
1
V
L1
V
L2
C
2
C
2
C
3
C
4
C
11
C
12
C
3
C
11
C
12
C
4
(a)
I
in
V
in
+
–
(b)
L
1
L
2
V
in
V
in +
–
+
+
–
V
2
+
–
– +
–
–
(c)
R
I
O
V
O
–
+
R
I
O
V
C12
+
–
V
O
–
+
R
I
O
FIGURE 7.21 Relift additional circuit of N/OSLLuoconverters: (a) circuit diagram, (b) equivalent circuit during
switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 275. With permission.)
V
1
=
1
1 −k
V
in
=
_
2 −k
1 −k
−1
_
V
in
,
V
L1–off
=
k
1 −k
V
in
.
The output voltage is
V
O
= V
in
+V
L1
+V
1
=
2
1 −k
V
in
=
_
3 −k
1 −k
−1
_
V
in
. (7.139)
The voltage transfer gain is
G
1
=
V
O
V
in
=
3 −k
1 −k
−1. (7.140)
SuperLift Converters and Ultralift Converter 341
I
in
V
in
V
1
V
2
V
3
V
C1
+
+
–
V
in
V
in
+
–
V
3
+
–
V
1
+V
in
V
3
+ V
in
+
+
–
–
V
2
+ V
in
V
C12
+
+ –
–
V
C2
+
–
V
C4
+
–
V
C6
+
–
V
C12
+
–
V
C3
+
–
V
C5
+
–
V
C11
I
O
+
–
V
O
+
–
I
O
V
O
+
–
I
O
V
O
+
–
+
–
–
D
1
L
1
V
in
V
L1
V
1
+V
in
V
2
+V
in
V
3
+V
in
V
L2
V
L3
+
+
+
+
–
–
+
+
+ –
–
–
–
–
L
1
L
2
L
3
L
2
L
2
L
3
L
3
C
1
C
6
C
12
C
4
C
11
C
3
C
5
C
2
C
3
C
4
C
6
C
12
C
5
C
11
C
1
C
2
C
2
C
4
C
6
C
3
C
11
C
5
S
D
3
D
2
D
4
D
5
D
7
D
11
D
12
C
12
D
8
D
6
(a)
I
in
V
in
C
1
+
–
L
1
(b)
(c)
R
R V
1
V
1
V
1
V
2
–
+
V
C12
–
+
V
3
V
3
V
2
V
1
V
2
V
3
+
–
V
2
R
FIGURE 7.22 Triplelift additional circuit of N/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor p. 276. With permission.)
The following relations are obtained:
i
C12–on
= I
O
, i
C12–off
=
kI
O
1 −k
,
i
C11–off
= I
O
+i
C12–off
=
I
O
1 −k
, i
C11–on
= i
C2–on
=
I
O
k
,
i
C2–off
= i
C1–off
=
I
O
1 −k
, i
C1–on
=
I
O
k
,
I
L1
= i
C1–off
+i
C11–on
=
2I
O
1 −k
,
i
in
= I
L1
+i
C1–on
+i
C11–on
=
_
2
1 −k
+
1
k
+
1
k
_
I
O
=
2
k(1 −k)
I
O
.
342 Power Electronics
Therefore,
I
in
= ki
in
=
2
1 −k
I
O
=
_
3 −k
1 −k
−1
_
I
O
.
The variation ratio of current I
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)TV
in
4L
1
I
O
=
k(1 −k)
2G
1
R
2f L
1
. (7.141)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.142)
7.3.2.2 N/O ReLift Additional Circuit
The N/Orelift additional circuit is derivedfromthe N/Orelift circuit byaddinga DEC. Its
circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 7.21.
The voltage across capacitor C
1
is charged with V
in
. As described in the previous section,
the voltage across C
2
is V
1
= (1/(1 −k))V
in
.
The voltage across capacitor C
3
is charged with (V
1
+V
in
), the voltage across capacitor
C
4
is charged with V
2
, and the voltage across capacitor C
11
is charged with (V
2
+V
in
). The
current ﬂowing through inductor L
2
increases with (V
1
+V
in
) during the switchon period
kT and decreases with −(V
2
−2V
1
−V
in
) during the switchoff period (1 −k)T. Therefore,
Δi
L2
=
V
1
+V
in
L
2
kT =
V
2
−2V
1
−V
in
L
2
(1 −k)T, (7.143)
V
2
=
(2 −k)V
1
+V
in
1 −k
=
3 −2k
(1 −k)
2
=
_
_
2 −k
1 −k
_
2
−1
_
V
in
,
and
V
L2–off
= V
2
−2V
1
−V
in
=
k(2 −k)
(1 −k)
2
V
in
. (7.144)
The output voltage is
V
O
= V
2
+V
in
+V
L2
+V
1
=
5 −3k
(1 −k)
2
V
in
=
_
3 −k
1 −k
2 −k
1 −k
−1
_
V
in
. (7.145)
The voltage transfer gain is
G
2
=
V
O
V
in
=
2 −k
1 −k
3 −k
1 −k
−1. (7.146)
SuperLift Converters and Ultralift Converter 343
The following relations are obtained:
i
C12–on
= I
O
, i
C12–off
=
kI
O
1 −k
,
i
C11–off
= I
O
+i
C12–off
=
I
O
1 −k
, i
C11–on
= i
C4–on
=
I
O
k
,
i
C4–off
= i
C3–off
=
I
O
1 −k
, i
C3–on
=
I
O
k
,
I
L2
= i
C11–off
+i
C3–off
=
2I
O
1 −k
,
i
C2–on
= I
L2
+i
C3–on
=
1 +k
k(1 −k)
I
O
, i
C2–off
=
1 +k
(1 −k)
2
I
O
.
I
L1
= i
C1–off
= I
L2
+i
C2–off
=
3 −k
(1 −k)
2
I
O
, i
C1–on
=
3 −k
k(1 −k)
I
O
,
i
in
= I
L1
+i
C1–on
+i
C2–on
+i
C4–on
=
_
3 −k
(1 −k)
2
+
3 −k
k(1 −k)
+
1 +k
k(1 −k)
+
1
k
_
I
O
=
5 −3k
k(1 −k)
2
I
O
.
Therefore,
I
in
= ki
in
=
5 −3k
(1 −k)
2
I
O
=
_
3 −k
1 −k
2 −k
1 −k
−1
_
I
O
.
Analogously,
Δi
L1
=
V
in
L
2
kT, I
L1
=
3 −k
(1 −k)
2
I
O
,
Δi
L2
=
V
1
+V
in
L
2
kT =
2 −k
(1 −k)L
2
kTV
in
, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
2(3 −k)L
1
I
O
=
k(1 −k)
2
(3 −k)G
2
R
2f L
1
. (7.147)
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(2 −k)TV
in
4L
2
I
O
=
k(2 −k)
2G
2
R
2f L
2
. (7.148)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.149)
344 Power Electronics
7.3.2.3 TripleLift Additional Circuit
This circuit is derived from the N/O triplelift circuit by adding a DEC. Its circuit diagram
and equivalent circuits during switchon and switchoff periods are shown in Figure 7.22.
The voltage across capacitor C
1
is charged with V
in
. As described in the previous section,
the voltage across C
2
is V
1
= (1/(1 −k))V
in
and the voltage across C
4
is
V
2
=
3 −2k
1 −k
V
1
=
3 −2k
(1 −k)
2
V
in
.
The voltage across capacitor C
5
is charged with (V
2
+V
in
), the voltage across capacitor
C
6
is charged with V
3
, and the voltage across capacitor C
11
is charged with (V
3
+V
in
).
The current ﬂowing through inductor L
3
increases with (V
2
+V
in
) during the switchon
period kT and decreases with −(V
3
−2V
2
−V
in
) during the switchoff period (1 −k)T.
Therefore,
Δi
L3
=
V
2
+V
in
L
3
kT =
V
3
−2V
2
−V
in
L
3
(1 −k)T, (7.150)
V
3
=
(2 −k)V
2
+V
in
1 −k
=
7 −9k +3k
2
(1 −k)
3
V
in
=
_
_
2 −k
1 −k
_
3
−1
_
V
in
,
and
V
L3–off
= V
3
−2V
2
−V
in
=
k(2 −k)
2
(1 −k)
3
V
in
. (7.151)
The output voltage is
V
O
= V
3
+V
in
+V
L3
+V
2
=
11 −13k +4k
2
(1 −k)
3
V
in
=
_
3 −k
1 −k
_
2 −k
1 −k
_
2
−1
_
V
in
. (7.152)
The voltage transfer gain is
G
3
=
V
O
V
in
=
_
2 −k
1 −k
_
2
3 −k
1 −k
−1. (7.153)
The following relations are available:
i
C12–on
= I
O
, i
C12–off
=
kI
O
1 −k
,
i
C11–off
= I
O
+i
C12–off
=
I
O
1 −k
, i
C11–on
= i
C6–on
=
I
O
k
,
SuperLift Converters and Ultralift Converter 345
i
C6–off
= i
C5–off
=
I
O
1 −k
, i
C5–on
=
I
O
k
,
I
L3
= i
C11–off
+i
C5–off
=
2I
O
1 −k
,
i
C4–on
= I
L3
+i
C5–on
=
1 +k
k(1 −k)
I
O
, i
C4–off
=
1 +k
(1 −k)
2
I
O
.
I
L2
= i
C3–off
= I
L3
+i
C4–off
=
3 −k
(1 −k)
2
I
O
, i
C3–on
=
3 −k
k(1 −k)
I
O
,
i
C2–on
= I
L2
+i
C3–on
=
3 −k
k(1 −k)
2
I
O
, i
C2–off
=
3 −k
(1 −k)
3
I
O
,
I
L1
= i
C1–off
= I
L2
+i
C2–off
=
(3 −k)(2 −k)
(1 −k)
3
I
O
, i
C1–on
=
(3 −k)(2 −k)
k(1 −k)
2
I
O
,
i
in
= I
L1
+i
C1–on
+i
C2–on
+i
C4–on
+i
C6–on
=
_
(3 −k)(2 −k)
(1 −k)
3
+
(3 −k)(2 −k)
k(1 −k)
2
+
3 −k
k(1 −k)
2
+
1 +k
k(1 −k)
+
1
k
_
I
O
=
11 −13k +4k
2
k(1 −k)
3
I
O
.
Therefore,
I
in
= ki
in
=
11 −13k +4k
2
(1 −k)
3
I
O
=
_
3 −k
1 −k
_
2 −k
1 −k
_
2
−1
_
I
O
.
Analogously,
Δi
L1
=
V
in
L
2
kT, I
L1
=
(2 −k)(3 −k)
(1 −k)
3
I
O
,
Δi
L2
=
V
1
+V
in
L
2
kT =
2 −k
(1 −k)L
2
kTV
in
, I
L2
=
3 −k
(1 −k)
2
I
O
,
Δi
L3
=
V
2
+V
in
L
3
kT =
(2 −k)
2
(1 −k)
2
L
3
kTV
in
, I
L3
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
2(2 −k)(3 −k)L
1
I
O
=
k(1 −k)
3
(2 −k)(3 −k)G
3
R
2f L
1
, (7.154)
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)(2 −k)TV
1
2(3 −k)L
2
I
O
=
k(1 −k)(2 −k)
(3 −k)G
3
R
2f L
2
, (7.155)
and the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(2 −k)
2
TV
in
4(1 −k)L
3
I
O
=
k(2 −k)
2
2(1 −k)G
3
R
2f L
3
. (7.156)
346 Power Electronics
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.157)
7.3.2.4 N/O HigherOrder Lift Additional Circuit
The higherorder N/Olift additional circuit can be derived fromthe corresponding circuits
of the main series by adding a DEC. Each stage voltage V
i
(i = 1, 2, . . . , n) is
V
i
=
_
_
2 −k
1 −k
_
i
−1
_
V
in
. (7.158)
It means that V
1
is the voltage across capacitor C
2
, V
2
is the voltage across capacitor C
4
,
and so on.
For the nthorder lift additional circuit, the ﬁnal output voltage is
V
O
=
_
3 −k
1 −k
_
2 −k
1 −k
_
n−1
−1
_
V
in
. (7.159)
The voltage transfer gain is
G
n
=
V
O
V
in
=
3 −k
1 −k
_
2 −k
1 −k
_
n−1
−1. (7.160)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
n
2
h(1−n)
[(2 −k)
(n−2)
(3 −k)]
u(n−2)
G
n
R
f L
1
, (7.161)
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
(n−2)
(2 −k)
2
h(n−2)
(3 −k)
(n−2)
G
n
R
2f L
2
, (7.162)
ξ
3
=
Δi
L3
/2
I
L3
=
k(2 −k)
(n−1)
2
h(n−3)
(1 −k)
(n−2)
G
n
R
2f L
3
, (7.163)
where
h(x) =
_
0 x > 0
1 x ≤ 0
is the Hong function
and
u(x) =
_
1 x ≥ 0
0 x < 0
is the unitstep function,
SuperLift Converters and Ultralift Converter 347
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.164)
7.3.3 Enhanced Series
All circuits of the N/O SL Luoconverters—enhanced series—are derived from the corre
sponding circuits of the main series by adding the DEC in each stage circuit of all series
converters.
The ﬁrst three stages of this series are shown in Figures 7.20, 7.23, and 7.24. For ease
of understanding, they are called the elementary enhanced circuit, the relift enhanced
circuit, and the triplelift enhanced circuit, respectively, and are numbered n = 1, 2, and 3,
respectively.
7.3.3.1 N/O Elementary Enhanced Circuit
This circuit is derived from the N/O elementary circuit by adding a DEC. Its circuit and
switchon and switchoff equivalent circuits are shown in Figure 7.20.
The output voltage is
V
O
= V
in
+V
L1
+V
1
=
2
1 −k
V
in
=
_
3 −k
1 −k
−1
_
V
in
. (7.139)
The voltage transfer gain is
G
1
=
V
O
V
in
=
3 −k
1 −k
−1. (7.140)
7.3.3.2 N/O ReLift Enhanced Circuit
The N/O relift enhanced circuit is derived from the N/O relift circuit of the main series
by adding the DEC in each stage circuit. Its circuit diagram and switchon and switchoff
equivalent circuits are shown in Figure 7.23.
The voltage across capacitor C
12
is charged to
V
C12
=
3
1 −k
V
in
. (7.165)
The voltage across capacitor C
3
is charged with V
C12
, and the voltage across capacitors
C
4
and C
12
is charged with V
C4
V
C4
=
2 −k
1 −k
V
C12
=
2 −k
1 −k
3 −k
1 −k
V
in
. (7.166)
348 Power Electronics
I
in
V
in
V
L1
V
1 V
2
V
2
V
1
V
in
V
C1
V
C2
V
O
I
O
I
O
+
+
–
V
in
+
+
+
–
–
–
–
–
–
+
+
+
+ –
V
1
+ V
in
V
2
+
V
in
+
–
V
2
+ V
in
V
3
+
V
in
+
–
V
C3
+
–
–
+
–
+
–
V
in
+
–
I
in
V
in
+
–
+
–
+
–
+
–
+
–
–
+
V
C12
V
C4
V
C22
– –
+
–
+ +
D
1
D
11
D
2
D
3
D
4
V
1
C
2
D
12
D
22
C
12
C
22
D
21
D
5
C
4
L
1
L
1
L
2
L
1
L
2
V
L2
L
2
S
C
1
C
1
C
1
C
3
C
2
C
4
C
22
C
2
C
4
C
3 C
21
C
11
C
11
C
11
C
21
C
3
C
21
V
C11
V
C3
+
–
V
C21
(b)
(c)
(a)
R
V
1
V
1
C
12
–
+
V
C12
–
+
V
2
V
2
V
C22
–
+
V
O
I
O
–
+
V
O
R
–
+
V
C22
R V
C12
V
C3
C
12
C
22
FIGURE 7.23 Relift enhancedcircuit of N/OSLLuoconverters: (a) circuit diagram, (b) equivalent circuit during
switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 284. With permission.)
The current ﬂowing through inductor L
2
increases with V
C12
during the switchon period
kT and decreases with −(V
C21
−V
C4
−V
C12
) during the switchoff period (1 −k)T.
Therefore,
Δi
L2
=
kT
L
2
(V
C12
−V
in
) =
V
C21
−V
C4
−V
C12
L
2
(1 −k)T, (7.167)
V
C21
=
_
3 −k
1 −k
_
2
V
in
.
SuperLift Converters and Ultralift Converter 349
The output voltage is
V
O
= V
C21
−V
in
=
_
_
3 −k
1 −k
_
2
−1
_
V
in
. (7.168)
The voltage transfer gain is
G
2
=
V
O
V
in
=
_
3 −k
1 −k
_
2
−1. (7.169)
The following relations are obtained:
i
C22–on
= I
O
, i
C22–off
=
kI
O
1 −k
,
i
C21–off
= I
O
+i
C22–off
=
I
O
1 −k
, i
C21–on
= i
C4–on
=
I
O
k
,
i
C4–off
= i
C3–off
=
I
O
1 −k
, i
C3––on
=
I
O
k
,
I
L2
= i
C21–off
+i
C3–off
=
2I
O
1 −k
,
i
C12–on
= I
L2
+i
C3–on
=
1 +k
k(1 −k)
I
O
, i
C12–off
=
1 +k
(1 −k)
2
I
O
,
i
C11–off
= I
L2
+i
C12–off
=
3 −k
(1 −k)
2
I
O
, i
C2–off
=
3 −k
(1 −k)
2
I
O
,
i
C11–on
= i
C2–on
=
3 −k
k(1 −k)
I
O
,
I
L1
= i
C11–off
+i
C2–off
= 2
3 −k
(1 −k)
2
I
O
, i
C1–on
=
3 −k
k(1 −k)
I
O
,
i
in
= I
L1
+i
C1–on
+i
C11–on
+i
C12–on
+i
C21–on
=
4(2 −k)
k(1 −k)
2
I
O
.
Therefore,
I
in
= ki
in
=
4(2 −k)
(1 −k)
2
I
O
=
_
(3 −k)
2
(1 −k)
2
−1
_
I
O
.
Analogously,
Δi
L1
=
V
in
L
2
kT, I
L1
= 2
3 −k
(1 −k)
2
I
O
,
Δi
L2
=
V
C12
−V
in
L
2
kT =
2 +k
(1 −k)L
2
kTV
in
, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
4(3 −k)L
1
I
O
=
k(1 −k)
2
2(3 −k)G
2
R
2f L
1
. (7.170)
350 Power Electronics
The variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(2 +k)TV
in
4L
2
I
O
=
k(2 +k)
2G
2
R
2f L
2
. (7.171)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
22
=
I
O
kT
C
22
=
k
fC
22
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
22
. (7.172)
7.3.3.3 N/OTripleLift Enhanced Circuit
This circuit is derived from the N/O triplelift circuit of the main series by adding the
DEC in each stage circuit. Its circuit diagram and equivalent circuits during switchon and
switchoff periods are shown in Figure 7.24.
The voltage across capacitor C
12
is charged with V
C12
. As described in the previous
section, the voltage across C
C12
is V
C12
= ((3 −k)/(1 −k))V
in
and the voltage across C
4
and
C
C22
is
V
C22
=
3 −k
1 −k
V
C12
=
_
3 −k
1 −k
_
2
V
in
.
The voltage across capacitor C
5
is charged with V
C22
, and the voltage across capacitor C
6
is charged with V
C6
V
C6
=
2 −k
1 −k
V
C22
=
2 −k
1 −k
_
3 −k
1 −k
_
2
V
in
.
The current ﬂowing through inductor L
3
increases with V
C22
during the switchon period
kT and decreases with −(V
C32
−V
C6
−V
C22
) during the switchoff period (1 −k)T.
Therefore,
Δi
L3
=
kT
L
3
(V
C22
−V
in
) =
V
C31
−V
C6
−V
C22
L
3
(1 −k)T, (7.173)
V
C31
=
_
3 −k
1 −k
_
3
V
in
,
and
V
O
= V
C31
−V
in
=
_
_
3 −k
1 −k
_
3
−1
_
V
in
. (7.174)
The voltage transfer gain is
G
3
=
V
O
V
in
=
_
3 −k
1 −k
_
2
−1. (7.175)
SuperLift Converters and Ultralift Converter 351
(a)
(b)
(c)
I
in
V
in
V
1
V
C1
V
C12
V
C22
V
1
V
1
+ V
in
V
C4
V
C11
V
C3
V
C2
V
1
V
1
V
C12
+
+
–
V
in
+
–
+
+
+
–
–
–
–
–
–
–
+
+ –
–
–
–
+
+
+
+ –
–
+
R
+
+ +
–
+
–
+
–
V
C21
+
–
V
C5
V
C32
+
–
V
C6
+
–
V
C31
+
– –
+
–
V
C3
V
3
+
–
V
C5
+
–
V
3
+ V
in
+
–
–
+
–
+
V
2
+ V
in
V
3
C
32
V
C32
–
+
V
O
I
O
–
+
V
O
I
O
R
+
–
–
+
–
+
–
+
–
+
+
+
– –
I
O
V
C11
+
+
–
–
–
D
1
D
21
D
22
D
31
C
22
D
3
D
12
C
12
L
1
I
in
V
in
+
–
L
1
V
L1
V
1
V
2
+ V
in
V
1
V
2 V
C22
V
C5
V
2
L
1
L
2
L
3
L
2
L
2
L
3
L
3
C
1
C
1
C
2
C
1
C
12
C
4
C
6
C
5
C
22
C
2
C
3
C
5
C
31
C
31
C
32
V
C32
C
4
C
6
C
22
C
2
C
12
C
21
C
21
C
11
C
11
C
11
C
3
C
3
C
4
C
5
C
32
C
6
S
D
2
D
4
D
5
D
6
D
7
D
8
D
31
D
32
D
11
C
21
R
V
2
V
2
V
C22
V
in
V
L2
V
L3
V
C12
V
C3
V
3
V
3
+ V
in
V
3
V
4
+ V
in
FIGURE 7.24 Triplelift enhanced circuit of N/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 285. With permission.)
The following relations are obtained:
i
C32–on
= I
O
, i
C32–off
=
kI
O
1 −k
,
i
C31–off
= I
O
+i
C32–off
=
I
O
1 −k
, i
C31–on
= i
C6–on
=
I
O
k
,
i
C6–off
= i
C5–off
=
I
O
1 −k
, i
C6–on
= i
C5–on
=
I
O
k
,
I
L3
= i
C31–off
+i
C5–off
=
2I
O
1 −k
,
i
C22–on
= I
L3
+i
C5–on
=
1 +k
k(1 −k)
I
O
, i
C22–off
=
1 +k
(1 −k)
2
I
O
,
i
C21–off
= i
C4–off
= I
L3
+i
C22–off
=
3 −k
(1 −k)
2
I
O
, i
C4–on
=
3 −k
k(1 −k)
I
O
,
352 Power Electronics
I
L2
= i
C4–off
+i
C21–off
= 2
3 −k
(1 −k)
2
I
O
, i
C3–on
=
3 −k
k(1 −k)
I
O
,
i
C12–on
= I
L2
+i
C3–on
=
(3 −k)(2 −k)
k(1 −k)
2
I
O
, i
C12–off
=
(3 −k)(2 −k)
(1 −k)
3
I
O
,
i
C11–off
= I
L2
+i
C12–off
=
(3 −k)(4 −3k)
(1 −k)
3
I
O
, i
C11–on
=
(3 −k)(4 −k)
k(1 −k)
2
I
O
,
I
L1
= i
C11–off
+i
C1–off
= 2
(3 −k)(4 −k)
(1 −k)
3
I
O
, i
C1–on
= i
C2–on
=
(3 −k)(4 −k)
k(1 −k)
2
I
O
,
i
in
= I
L1
+i
C1–on
+i
C2–on
+i
C12–on
+i
C4–on
+i
C22–on
+i
C6–on
=
2(13 −12k +3k
2
)
k(1 −k)
3
I
O
.
Therefore,
I
in
= ki
in
= 2
13 −12k +3k
2
(1 −k)
3
I
O
=
_
_
3 −k
1 −k
_
3
−1
_
I
O
.
Analogously,
Δi
L1
=
V
in
L
2
kT, I
L1
=
2(4 −k)(3 −k)
(1 −k)
3
I
O
,
Δi
L2
=
V
1
+V
in
L
2
kT =
2 −k
(1 −k)L
2
kTV
in
, I
L2
= 2
3 −k
(1 −k)
2
I
O
,
Δi
L3
=
V
2
+V
in
L
3
kT =
(2 −k)
2
(1 −k)
2
L
3
kTV
in
, I
L3
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
4(4 −k)(3 −k)L
1
I
O
=
k(1 −k)
3
2(4 −k)(3 −k)G
3
R
2f L
1
, (7.176)
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)(2 −k)TV
1
4(3 −k)L
2
I
O
=
k(1 −k)(2 −k)
2(3 −k)G
3
R
2f L
2
, (7.177)
and the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(2 −k)
2
TV
in
4(1 −k)L
3
I
O
=
k(2 −k)
2
2(1 −k)G
3
R
2f L
3
. (7.178)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
32
=
I
O
kT
C
32
=
k
fC
32
V
O
R
.
SuperLift Converters and Ultralift Converter 353
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
32
. (7.179)
7.3.3.4 N/O HigherOrder Lift Enhanced Circuit
The higherorder N/Olift enhancedcircuit is derivedfromthe corresponding circuits of the
main series by adding the DEC in each stage of the circuit. At each stage, the ﬁnal voltage
V
Ci1
(i = 1, 2, . . . , n) is
V
Ci1
=
_
3 −k
1 −k
_
i
V
in
. (7.180)
For the nthorder lift enhanced circuit, the ﬁnal output voltage is
V
O
=
__
3 −k
1 −k
_
n
−1
_
V
in
. (7.181)
The voltage transfer gain is
G
n
=
V
O
V
in
=
_
3 −k
1 −k
_
n
−1. (7.182)
The variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n2
. (7.183)
7.3.4 ReEnhanced Series
All circuits of the N/O SL Luoconverters—reenhanced series—are derived from the
corresponding circuits of the main series by adding the DEC twice in circuits of each stage.
The ﬁrst three stages of this series are shown in Figures 7.25 through 7.27. For ease of
understanding, they are called the elementary reenhanced circuit, the relift reenhanced
circuit, and the triplelift reenhanced circuit, respectively, and are numbered n = 1, 2, and
3, respectively.
7.3.4.1 N/O Elementary ReEnhanced Circuit
This circuit is derived from the N/O elementary circuit by adding the DEC twice in each
stage circuit. Its circuit and switchon and switchoff equivalent circuits are shown in
Figure 7.25.
The voltage across capacitor C
1
is charged with V
in
. The voltage across capacitor C
12
is
charged with V
C12
.
The voltage across capacitor C
13
is charged with V
C13
.
V
C13
=
4 −k
1 −k
V
in
. (7.184)
354 Power Electronics
(a)
(b)
(c)
I
in
V
in
V
C1
V
O
I
O
I
O
+
–
V
in
+
–
I
in
V
in
V
in
V
1
V
L1
V
2
V
O
V
1
V
1
V
1
V
2
V
2
V
2
+ V
1
V
C14
V
in
V
C11
V
2
V
1
+V
in
+
–
+
–
–
+
+
+
+
+
– –
–
– –
+ +
+
+
+
+
–
I
O
V
O
+
–
+
–
+
+
–
–
–
–
–
–
+
–
V
C11
+
–
V
C13
+
–
V
C1
V
C12
–
+
–
–
D
1
D
2
D
11
D
12
D
13
D
14
C
12
C
14
C
2
C
2
C
2
C
12
C
14
C
12
C
11
C
13
C
14
C
13
C
11
C
11
L
1
L
1
L
1
S
C
1
C
1
C
1
C
13
R
V
C14
V
2
+V
1
V
C14
R
+
R
FIGURE 7.25 Elementary reenhanced circuit of N/O SL Luoconverters: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 292. With permission.)
The output voltage is
V
O
= V
C13
−V
in
=
_
4 −k
1 −k
−1
_
V
in
. (7.185)
The voltage transfer gain is
G
1
=
V
O
V
in
=
4 −k
1 −k
−1. (7.186)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
14
=
I
O
kT
C
14
=
k
fC
14
V
O
R
.
SuperLift Converters and Ultralift Converter 355
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
14
. (7.187)
7.3.4.2 N/O ReLift ReEnhanced Circuit
The N/Orelift reenhancedcircuit is derivedfromthe N/Orelift circuit byaddingthe DEC
twice in circuits of each stage. Its circuit diagram and switchon and switchoff equivalent
circuits are shown in Figure 7.26.
The voltage across capacitor C
13
is charged with V
C13
. As described in the previous
section, the voltage across C
13
is
V
C13
=
4 −k
1 −k
V
in
.
(a)
(b)
(c)
I
in
V
in
V
C1
V
O
I
O
+
–
I
in
V
in
V
1
+ V
in
V
2
+ V
1
V
1
V
2
V
3
V
4
V
3 V
4
V
4
+ V
3 V
C3
V
2
V
1
V
1
V
2
V
2
+ V
1
V
2
V
in
V
C11
V
C14
V
C3
V
C24
V
3
+ V
4
V
3
V
3
V
1
V
C14 C
4
C
22
C
23
C
24
L
1
L
1
L
2
L
2
C
1
C
2
V
L1
V
L2
V
4
V
4
V
C21
C
1
C
11
C
3
C
22
C
21
C
24
C
4
C
2
C
12
C
14
C
13
C
12
C
13
C
3
C
21
C
23
C
14
C
11
V
in
+
+
+
–
–
+ +
+
+
+ +
+
–
+
+
–
+
–
–
–
– +
–
–
–
–
+
+
–
– –
–
+
+
+
–
V
C3
+V
3
V
C24
R
+
+
–
–
–
–
–
+ +
–
–
–
+
+
–
V
O
I
O
+ +
–
V
O
I
O
+
–
+
–
V
C11
+ +
–
–
V
C2
V
C12
V
C13
+
–
V
C3
+
–
V
C21
+
–
V
C23
V
C14
V
C22
–
+
–
–
+ +
–
+ +
–
–
+
D
1
D
2
D
11
D
3
D
12
D
13
D
14
D
3
D
4
D
21
D
22
C
22
C
24
D
23
D
24
C
4
V
C4
C
2
C
12
C
14
C
21
C
11
C
13
L
1
S
C
1
R
V
C24
L
2
C
3
C
23
R
FIGURE 7.26 Relift reenhanced circuit of N/O SL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 293. With permission.)
356 Power Electronics
Analogously,
V
C23
=
_
4 −k
1 −k
_
2
V
in
. (7.188)
The output voltage is
V
O
= V
C23
−V
in
=
_
_
4 −k
1 −k
_
2
−1
_
V
in
. (7.189)
The voltage transfer gain is
G
2
=
V
O
V
in
=
_
4 −k
1 −k
_
2
−1. (7.190)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
24
=
I
O
kT
C
24
=
k
fC
24
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
24
. (7.191)
7.3.4.3 N/OTripleLift ReEnhanced Circuit
This circuit is derived fromthe N/Otriplelift circuit by adding the DECtwice in each stage
circuit. Its circuit diagram and equivalent circuits during switchon and switchoff periods
are shown in Figure 7.27.
The voltage across capacitor C
13
is
V
C13
=
4 −k
1 −k
V
in
.
The voltage across capacitor C
23
is
V
C23
=
_
4 −k
1 −k
_
2
V
in
.
Analogously, the voltage across capacitor C
33
is
V
C33
=
_
4 −k
1 −k
_
3
V
in
. (7.192)
The output voltage is
V
O
= V
C33
−V
in
=
_
_
4 −k
1 −k
_
3
−1
_
V
in
. (7.193)
SuperLift Converters and Ultralift Converter 357
(a)
(b)
(c)
V
in
V
C1
+
–
V
in
V
1
+V
in
V
2
+ V
1
+
–
V
in
+
+
+
–
+
–
V
C3
+
–
+
–
–
+
+
+
+
+
+
+ +
+
–
– –
–
–
–
+
–
+
–
V
4
+
–
V
3
+
C
22
+
–
–
–
+ +
+
+
–
–
V
C3
+V
3
+ +
– –
–
+
–
+
–
V
C3
+
–
V
C21
+
–
V
C23
+
–
V
C5
+
–
V
C33
I
O
I
O
I
in
R
V
O
+
+
–
V
C34
D
34
D
33
D
32
D
31 D
8
D
7
D
24
C
34
+
–
V
C6
+
–
D
23
D
22
V
C22
+
–
D
21
V
C4
+
–
D
13
D
12
D
2
D
1
C
2 V
C12
+
–
D
11
V
C2
+
–
V
C14
+
–
V
C24
+
–
–
V
C31
V
C32
C
32
C
6
C
24
D
5
D
4
D
14
C
4
C
14
C
12
C
22
+
–
V
C11
+
–
V
C13
+
–
C
11
C
11
C
12
C
4
C
22
C
24
C
6
C
13
C
14
C
21 C
5
C
31
C
33
C
23
C
13 L
1
L
1
V
L1 C
14
C
21
C
14
C
24
C
5
C
31
C
34
C
33
C
6
C
32
C
23
C
3
V
2
+V
1
V
C11
V
C14
V
C3
V
C21
V
C24
V
L3
V
5
V
6
V
6
V
6
V
C5
V
5
+ V
6
V
C34
V
C31
L
2
L
2
L
3
S
C
1
C
1
C
1
C
2
C
12
C
11
C
2
C
3
C
23 C
21
C
5
L
3
D
3
D
6
C
3
V
C13
V
1
+
–
+
–
V
C14
V
3
+
–
V
2
V
3
V
4
+ V
3
+
+
–
–
V
C5
V
5
V
O
V
5
V
6
V
C34
R
V
6
+ +
–
–
+
–
+
V
O
–
+
+
–
–
+ +
–
V
C5
+V
5
V
5
+ V
6
I
O C
31
C
32
C
33
C
34
V
4
V
1
V
2
V
4
V
C24
L
1
V
1
V
2
V
1 V
2
V
in
C
13
L
2
L
3
V
L2
V
3
V
4
V
3
+ V
4
R
FIGURE 7.27 Triplelift reenhanced circuit of N/OSL Luoconverters: (a) circuit diagram, (b) equivalent circuit
during switchon, and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 294. With permission.)
The voltage transfer gain is
G
3
=
V
O
V
in
=
_
4 −k
1 −k
_
3
−1. (7.194)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
34
=
I
O
kT
C
34
=
k
fC
34
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
34
. (7.195)
7.3.4.4 N/O HigherOrder Lift ReEnhanced Circuit
The higherorder N/O lift reenhanced circuit can be derived from the corresponding cir
cuits of the main series by adding the DEC twice in each stage circuit. At each stage, the
358 Power Electronics
ﬁnal voltage V
Ci3
(i = 1, 2, . . . , n) is
V
Ci3
=
_
4 −k
1 −k
_
i
V
in
. (7.196)
For the nthorder lift additional circuit, the ﬁnal output voltage is
V
O
= V
Cn3
−V
in
=
__
4 −k
1 −k
_
n
−1
_
V
in
. (7.197)
The voltage transfer gain is
G
n
=
V
O
V
in
=
_
4 −k
1 −k
_
n
−1. (7.198)
The variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n4
. (7.199)
7.3.5 N/O MultipleEnhanced Series
All circuits of the N/O SL Luoconverters—multipleenhanced series—are derived from
the corresponding circuits of the main series by adding the DEC multiple (j) times in each
stage circuit.
The ﬁrst three stages of this series are shown in Figures 7.28 through 7.30. For ease
of understanding, they are called the elementary multipleenhanced circuit, the relift
multipleenhanced circuit, and the triplelift multipleenhanced circuit, respectively, and
are numbered n = 1, 2, and 3, respectively.
7.3.5.1 N/O Elementary MultipleEnhanced Circuit
This circuit is derived from the N/O elementary circuit by adding the DEC multiple (j)
times. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 7.28.
The voltage across capacitor C
12j−1
is
V
C12j−1
=
j +2 −k
1 −k
V
in
. (7.200)
The output voltage is
V
O
= V
C12j−1
−V
in
=
_
j +2 −k
1 −k
−1
_
V
in
. (7.201)
The voltage transfer gain is
G
1
=
V
O
V
in
=
j +2 −k
1 −k
−1. (7.202)
SuperLift Converters and Ultralift Converter 359
(a)
(b)
(c)
I
in
V
in
V
C1
+
–
I
in
V
in
V
1
V
1
+
–
+
–
V
1
+ V
in
+
–
–
+
V
in
+
–
V
in
+
+
–
–
+
V
C12
–
+
–
V
C11
+
–
V
C1(2j–1)
+
R
–
V
C1(2j–1)
+
–
V
C2
–
+
V
C12
V
C12j
–
+
V
C12
–
+
V
C12j
R
V
C12j
R
–
+
V
O
I
O
–
+
–
+
V
O
I
O
–
+
–
+
+
–
D
1
D
12
C
12
C
12j
D
2
D
11
D
1(2j–1)
D
12j
C
11
L
1
L
1
V
in
V
L1
+
–
L
1
S
C
1
C
1
C
12
C
2
C
2
C
1
C
11
C
11
C
12
C
1(2j–1)
C
1(2j–1)
C
12j
C
12j
C
2
V
O
I
O
V
1
V
1
V
2
+ V
in
C
1(2j–1)
V
C1(2j–1)
FIGURE 7.28 Elementarymultipleenhancedcircuit of N/OSLLuoconverters: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 298. With permission.)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12j
=
I
O
kT
C
12j
=
k
fC
12j
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12j
. (7.203)
360 Power Electronics
(a)
(b)
(c)
I
in
V
in
V
C1
V
C2
V
O
V
O
I
O
I
O
+
–
I
in
V
in
V
L1
V
2
+V
in
V
in
V
in
V
1
+V
in
V
1
C
12
C
12
C
12j
C
22
C
4
C
22j
C
3
+
–
V
in
V
C12
V
C12j
V
C1(2j–1)
V
1
V
1
+ +
+ +
+
+
+ +
+
+
+ –
–
–
+ – –
–
–
–
+
–
–
–
–
–
–
–
+
–
+
–
+
–
+
–
–
+
V
C12
–
+ + +
V
C3
V
C4
V
C22
+
–
V
C21
+
–
+
–
V
C11
+
–
+
–
D
1
D
2
D
11
D
1(2j–1)
D
12j
D
12
C
12
C
12j
C
2
C
11
C
11
C
3
C
4
D
4
D
21
D
22
D
22j
C
22j
D
2(2j–1)
C
22
D
5
C
21
C
2(2j–1)
D
3
L
1
L
1
L
1
L
2
S
C
1
C
1
C
1
C
12
C
3
C
21
C
22j
C
22
C
2(2j–1)
C
12j
C
1(2j–1) C
11
C
4
C
2
C
2
R
V
C22j
V
C1(2j–1)
V
C12j
+
+
V
C1(2j–1) V
C3
C
21
V
C12j
–
+
+
–
V
C21
V
C22
V
22j
R
R
V
2
+
+
+
+ +
–
– –
I
O
V
O
–
+
–
+
+
–
–
–
C
1(2j–1)
V
1
L
2
C
1(2j–1)
C
2(2j–1)
V
2
V
L2j
V
C3
V
2
V
C21
V
C2(2j–1)
V
C22 V
C22j
L
2
V
2
V
C2(2j–1)
V
C2(2j–1)
FIGURE 7.29 Relift multipleenhanced circuit of N/O SL Luoconverters: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 299. With permission.)
7.3.5.2 N/O ReLift MultipleEnhanced Circuit
The N/Orelift multipleenhanced circuit is derived fromthe N/Orelift circuit by adding
the DEC multiple (j) times in circuits of each stage. Its circuit diagram and switchon and
switchoff equivalent circuits are shown in Figure 7.29.
The voltage across capacitor C
22j−1
is
V
C22j−1
=
_
j +2 −k
1 −k
_
2
V
in
. (7.204)
The output voltage is
V
O
= V
C22j−1
−V
in
=
_
_
j +2 −k
1 −k
_
2
−1
_
V
in
. (7.205)
SuperLift Converters and Ultralift Converter 361
(a)
(b)
(c)
+
_
_
V
in
+
_
V
in
V
L1
C
1
C
1
C
1
C
4
C
11
C
11
C
11
C
12
C
1(2j–1)
C
2(2j–1)
C
3(2j–1)
C
12j
V
C12
V
C3
V
12j
V
L2
V
L3
V
3
V
C32 V
C32j
C
12j
C
2
C
2
C
3
C
4
C
22
C
5
C
6
C
31
C
32j
C
32
D
11
D
3
C
3
C
21
C
32(2j–1)
C
2(2j–1)
C
4
C
5
C
6
C
31
C
32
D
4
D
21
D
22j
D
6
D
7
D
31
D
32
D
32j
C
32j
D
3(2j–1) D
8
D
22
D
2(2j–1)
C
22
C
22j
D
5
D
12
D
1(2j–1)
D
12j
C
12j
V
C1
V
C2 V
C12
D
1
D
2
C
2
C
1(2j–1)
C
12
L
1
L
1
L
1
V
1
L
2
L
2
L
3
L
3
L
2
L
3
S
+
_
V
in
+
_
V
in
+ + –
+
–
+
_
V
1
+
+
_
_
V
C12j
V
1
C
12
V
1
+V
in
V
C12
V
2
V
C1(2j–1)
+
_
+
_
V
2
V
C22
V
3
_
+
V
C22j
+
_
+
V
C3
_
+
V
C21
_
+
V
C2(2j–1)
_
+
V
C5
V
3
_
+
V
C32
_
+
V
C32j
_
+
V
C31
_
_
+
+
_
+
+ + +
– –
+
_
V
C11
+
_
+
_ _
+ +
_
+
_
+
+
–
+
–
+
–
_
+
V
C1(2j–1)
V
C3
V
C12j
V
C4
V
C5
V
C31
V
C6
V
C32
_
+
V
C3(2j–1)
V
C22
V
C21
V
(2j–1)
V
C22j
R
R
R
V
C32j
+
–
V
O
I
O
+
–
V
O
I
O
+
–
V
O
I
O
C
21
C
22j
C
21
C
3
C
5
C
6
C
32
C
32j
C
22
C
22j
V
C22j
V
3
C
31
C
1(2j–1)
C
3(2j–1)
V
C3(2j–1)
V
1
V
2
+V
in
+
+
–
–
+
+
–
–
+
–
V
C1(2j–1)
+ –
V
C21
+ –
V
C2(2j–1)
V
2
–
+
+ +
–
+
_
_
_
+
V
C5
V
C31
V
C3(2j–1)
–
+
–
+
–
+
V
C22
V
2
C
2(2j–1)
FIGURE 7.30 Triplelift multipleenhanced circuit of N/O SL Luoconverters: (a) circuit diagram, (b) equivalent
circuit during switchon, and (c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006.
Essential DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 300. With permission.)
The voltage transfer gain is
G
2
=
V
O
V
in
=
_
j +2 −k
1 −k
_
2
−1. (7.206)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
22j
=
I
O
kT
C
22j
=
k
fC
22j
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
22j
. (7.207)
7.3.5.3 N/OTripleLift MultipleEnhanced Circuit
This circuit is derived from the N/O triplelift circuit by adding the DEC multiple (j)
times in each stage circuit. Its circuit diagramand equivalent circuits during switchon and
switchoff periods are shown in Figure 7.30.
The voltage across capacitor C
32j−1
is
V
C32j−1
=
_
j +2 −k
1 −k
_
3
V
in
. (7.208)
362 Power Electronics
The output voltage is
V
O
= V
C32j−1
−V
in
=
_
_
j +2 −k
1 −k
_
3
−1
_
V
in
. (7.209)
The voltage transfer gain is
G
3
=
V
O
V
in
=
_
j +2 −k
1 −k
_
3
−1. (7.210)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
32j
=
I
O
kT
C
32j
=
k
fC
32j
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
32j
. (7.211)
7.3.5.4 N/O HigherOrder Lift MultipleEnhanced Circuit
The higherorder N/O lift multipleenhanced circuit is derived from the corresponding
circuits of the main series by adding the DEC multiple (j) times in each stage circuit. At
each stage, the ﬁnal voltage V
Ci2j−1
(i = 1, 2, . . . , n) is
V
Ci2j−1
=
_
j +2 −k
1 −k
_
i
V
in
. (7.212)
For the nthorder lift multipleenhanced circuit, the ﬁnal output voltage is
V
O
=
__
j +2 −k
1 −k
_
n
−1
_
V
in
. (7.213)
The voltage transfer gain is
G
n
=
V
O
V
in
=
_
j +2 −k
1 −k
_
n
−1. (7.214)
The variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n2j
. (7.215)
SuperLift Converters and Ultralift Converter 363
7.3.6 Summary of N/O SL LuoConverters
All circuits of the N/O SL Luoconverters can be shown in Figure 7.31 as the family tree.
From the analysis in previous sections, the common formula to calculate the output
voltage can be presented as
V
O
=
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
__
2 −k
1 −k
_
n
−1
_
V
in
main series,
_
_
2 −k
1 −k
_
n−1
_
3 −k
1 −k
_
−1
_
V
in
additional series,
__
3 −k
1 −k
_
n
−1
_
V
in
enhanced series,
__
4 −k
1 −k
_
n
−1
_
V
in
reenhanced series,
__
j +2 −k
1 −k
_
n
−1
_
V
in
multipleenhanced series.
(7.216)
Elementary additional/enhanced
circuit
Quintuplelift
circuit
Quintuplelift
additional circuit
Quintuplelift
enhanced circuit
Quintuplelift
reenhanced circuit
Quintuplelift mulitple
enhanced circuit
Quadruplelift
circuit
Quadruplelift
\additional circuit
Quadruplelift
enhanced circuit
Quadruplelift
reenhanced circuit
Quadruplelift mulitple
enhanced circuit
Triplelift
circuit
Triplelift
additional circuit
Triplelift
enhanced circuit
Triplelift
reenhanced circuit
Triplelift mulitple
enhanced circuit
Relift circuit
Relift additional
circuit
Relift enhanced
circuit
Relift
reenhanced circuit
Relift mulitple
enhanced circuit
Elementary mulitple
enhanced circuit
Elementary
reenhanced circuit
Negative output elementary superlift Luoconverter
Main
series
Additional
series
Enhanced
series
Reenhanced
series
Multipleenhanced
series
FIGURE 7.31 The family of N/OSLLuoconverters. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC
Converters. Boca Raton: Taylor & Francis Group LLC, p. 304. With permission.)
364 Power Electronics
The corresponding voltage transfer gain is
G =
V
O
V
in
=
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
_
2 −k
1 −k
_
n
−1 main series,
_
2 −k
1 −k
_
n−1
_
3 −k
1 −k
_
−1 additional series,
_
3 −k
1 −k
_
n
−1 enhanced series,
_
4 −k
1 −k
_
n
−1 reenhanced series,
_
j +2 −k
1 −k
_
n
−1 multipleenhanced series.
(7.217)
In order to show the advantages of N/O SL converters, their voltage transfer gains can
be compared with that of the buck converter, G = V
O
/V
in
= k.
Forward converter: G =
V
O
V
in
= kN (N is the transformer turn’s ratio),
Cúk converter: G =
V
O
V
in
=
k
1 −k
,
Flyback converter: G =
V
O
V
in
=
kN
1 −k
(N is the transformer turn’s ratio),
Boost converter: G =
V
O
V
in
=
1
1 −k
,
and
N/O Luoconverter: G =
V
O
V
in
=
n
1 −k
. (7.218)
Assume that the conduction duty cycle k is 0.2; the output voltage transfer gains are listed
inTable 7.4. Assume that the conductionduty cycle k is 0.5; the output voltage transfer gains
are listed in Table 7.5. Assume that the conduction duty cycle k is 0.8; the output voltage
transfer gains are listed in Table 7.6.
7.4 P/O Cascaded BoostConverters
SLLuoconverters largely increase the voltage transfer gainingeometric progression. How
ever, their circuits are a bit complex. We introduce a novel approach—P/O cascaded boost
converters—that implement the output voltage increasing ingeometric progressionas well,
but withasimpler structure. Theyalsoeffectivelyenhance the voltage transfer gaininpower
law. There are several subseries. As described in previous sections, only three circuits of
each subseries are introduced [1,2,7–9].
SuperLift Converters and Ultralift Converter 365
TABLE 7.4
Voltage Transfer Gains of Converters in the Condition k = 0.2
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.2
Forward converter 0.2N (N is the transformer turn’s ratio)
Cúkconverter 0.25
Flyback converter 0.25N (N is the transformer turn’s ratio)
Boost converter 1.25
N/O Luoconverters 1.25 2.5 3.75 5 6.25 1.25n
N/O SL converters—main series 1.25 4.06 10.39 24.63 56.67 2.25
n
−1
N/O SL converters—additional series 2.5 6.88 16.72 38.87 88.7 3.5 ×2.25
(n−1)
−1
Source: Data from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters, p. 305. Boca Raton: Taylor & Francis
Group LLC.
TABLE 7.5
Voltage Transfer Gains of Converters in the Condition k = 0.5
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.5
Forward converter 0.5N (N is the transformer turn’s ratio)
Cúkconverter 1
Flyback converter N (N is the transformer turn’s ratio)
Boost converter 2
N/O Luoconverters 2 4 6 8 10 2n
N/O SL converters—main series 2 8 26 80 242 3
n
−1
N/O SL converters—additional series 4 14 44 134 404 5 ×3
(n−1)
−1
Source: Data from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters, p. 305. Boca Raton: Taylor & Francis
Group LLC.
TABLE 7.6
Voltage Transfer Gains of Converters in the Condition k = 0.8
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.8
Forward converter 0.8N (N is the transformer turn’s ratio)
Cúkconverter 4
Flyback converter 4N (N is the transformer turn’s ratio)
Boost converter 5
N/O Luoconverters 5 10 15 20 25 5n
N/O SL converters—main series 5 35 215 1295 7775 6
n
−1
N/O SL converters—additional series 10 65 395 2375 14,255 11 ×6
(n−1)
−1
Source: Data fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters, p. 305. Boca Raton: Taylor &Francis
Group LLC.
366 Power Electronics
7.4.1 Main Series
The ﬁrst three stages of P/O cascaded boost converters—main series—are shown in
Figures 5.5, 7.32, and 7.33. For ease of understanding, they are called the elementary boost
converter, twostage circuit, and threestage circuit, respectively, and are numbered n = 1,
2, and 3, respectively.
7.4.1.1 Elementary Boost Circuit
The elementary boost converter is the fundamental boost converter; it is also introduced in
Section 5.2.2. Its circuit diagramand its equivalent circuits during switchon and switchoff
periods are shown in Figure 5.5. The output voltage is
V
O
=
1
1 −k
V
in
.
The voltage transfer gain is G = V
O
/V
in
= 1/(1 −k).
(a)
(b)
(c)
I
in
I
in
I
in
V
in
V
C1
V
O
I
O
I
O
+
–
V
in
+
–
V
in
V
L1
+
–
V
C1
+
–
V
C1
+
–
+
–
V
O
+
–
+
–
V
1
V
1
+
–
D
1
D
2
D
3
L
1
V
1
L
1
L
2
V
L2
L
1
S
C
1
C
1
C
1
C
2
C
2
C
2
R
V
C2
+
–
R
I
O
V
O
+
–
R
V
C2
+
–
V
C2
L
2
L
2
FIGURE 7.32 Twostage boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and (c) equiv
alent circuit during switchoff. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton:
Taylor & Francis Group LLC, p. 314. With permission.)
SuperLift Converters and Ultralift Converter 367
(a)
(b)
(c)
I
in
V
in
+
–
I
in
I
in
V
in
V
L2
V
L2
V
L1
V
C1
+
+
–
V
C1
+
–
V
C2
+
–
V
C2
C
3
+
–
V
C3
+
–
V
C3
+
–
–
V
in
+
–
V
O
+
–
V
C1
+
–
V
C1
+
–
V
C3
+
–
D
1
D
5
I
O
V
O
+
–
I
O
V
O
+
–
I
O
D
3
D
4
D
2
C
1
C
1
C
1
C
3
C
2
C
2
C
2
C
3
L
1
L
1
L
1
L
3
L
2
L
3
L
2
L
2
L
3
V
1
V
1
V
1
V
2
V
2
V
2
S
R
R
R
FIGURE 7.33 Threestage boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and (c) equiv
alent circuit during switchoff. (Reprinted fromLuo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca Raton:
Taylor & Francis Group LLC, p. 316. With permission.)
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
.
7.4.1.2 TwoStage Boost Circuit
The twostage boost circuit is derived from the elementary boost converter by adding
the parts (L
2
D
2
D
3
C
2
). Its circuit diagram and equivalent circuits during switchon and
switchoff periods are shown in Figure 7.32.
The voltage across capacitor C
1
is charged with V
1
. As described in the previous section,
the voltage V
1
across capacitor C
1
is V
1
= (1/(1 −k))V
in
.
The voltage across capacitor C
2
is chargedwith V
O
. The current ﬂowing through inductor
L
2
increases with V
1
during the switchon periodkT anddecreases with −(V
O
−V
1
) during
the switchoff period (1 −k)T. Therefore, the ripple of the inductor current i
L2
is
Δi
L2
=
V
1
L
2
kT =
V
O
−V
1
L
2
(1 −k)T, (7.219)
V
O
=
1
1 −k
V
1
=
_
1
1 −k
_
2
V
in
. (7.220)
368 Power Electronics
The voltage transfer gain is
G =
V
O
V
in
=
_
1
1 −k
_
2
. (7.221)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
I
O
(1 −k)
2
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
2L
1
I
O
=
k(1 −k)
4
2
R
f L
1
, (7.222)
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
2L
2
I
O
=
k(1 −k)
2
2
R
f L
2
, (7.223)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
2
. (7.224)
7.4.1.3 ThreeStage Boost Circuit
The threestage boost circuit is derived from the twostage boost circuit by twice repeating
the parts (L
2
D
2
D
3
C
2
). Its circuit diagram and equivalent circuits during switchon and
switchoff periods are shown in Figure 7.33.
The voltage across capacitor C
1
is charged with V
1
. As described in the previous section,
the voltage V
1
across capacitor C
1
is V
1
= (1/(1 −k))V
in
, andthe voltage V
2
across capacitor
C
2
is V
2
= (1/(1 −k))
2
V
in
.
The voltage across capacitor C
3
is chargedwith V
O
. The current ﬂowing through inductor
L
3
increases with V
2
during the switchon periodkT anddecreases with −(V
O
−V
2
) during
the switchoff period (1 −k)T. Therefore, the ripple of the inductor current i
L3
is
Δi
L3
=
V
2
L
3
kT =
V
O
−V
2
L
3
(1 −k)T, (7.225)
V
O
=
1
1 −k
V
2
=
_
1
1 −k
_
2
V
1
=
_
1
1 −k
_
3
V
in
. (7.226)
The voltage transfer gain is
G =
V
O
V
in
=
_
1
1 −k
_
3
. (7.227)
SuperLift Converters and Ultralift Converter 369
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
I
O
(1 −k)
3
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
I
O
(1 −k)
2
,
Δi
L3
=
V
2
L
3
kT, I
L3
=
I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
2L
1
I
O
=
k(1 −k)
6
2
R
f L
1
, (7.228)
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
2L
2
I
O
=
k(1 −k)
4
2
R
f L
2
, (7.229)
the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
2L
3
I
O
=
k(1 −k)
2
2
R
f L
3
, (7.230)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
3
. (7.231)
Example 7.4
A threestage boost converter in Figure 7.33a has V
in
= 20V, all inductors have 10mH, all capac
itors have 20μF, R = 400Ω, f = 50kHz, and conduction duty cycle k = 0.6. Calculate the
variation ratio of current I
L1
, and the output voltage and its variation ratio.
SOLUTION
From Equation 7.228, we can obtain the variation ratio of current i
L1
:
ξ
1
=
k(1 −k)
6
2
R
f L
1
=
0.6(1 −0.6)
6
2
400
50k ×10m
= 0.00098.
From Equation 7.226, we can obtain the output voltage:
V
O
=
_
1
1 −k
_
3
V
in
=
_
1
1 −0.6
_
3
×20 = 312.5V.
From Equation 7.231, its variation ratio is
ε =
k
2RfC
3
=
0.6
2 ×400 ×50k ×20μ
= 0.00075.
370 Power Electronics
7.4.1.4 HigherStage Boost Circuit
A higherstage boost circuit can be designed by just multiple repeating of the parts
(L
2
D
2
D
3
C
2
). For the nth stage boost circuit, the ﬁnal output voltage across capacitor
C
n
is
V
O
=
_
1
1 −k
_
n
V
in
.
The voltage transfer gain is
G =
V
O
V
in
=
_
1
1 −k
_
n
, (7.232)
the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
2
R
f L
i
, (7.233)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n
. (7.234)
7.4.2 Additional Series
All circuits of P/O cascaded boost converters—additional series—are derived from the
corresponding circuits of the main series by adding a DEC.
The ﬁrst three stages of this series are shown in Figures 7.34 through 7.36. For ease of
understanding, they are called the elementary additional circuit, the twostage additional
circuit, and the threestage additional circuit, respectively, and are numbered n = 1, 2, and
3, respectively.
7.4.2.1 Elementary Boost Additional (Double) Circuit
The elementary boost additional circuit is derived from the elementary boost converter by
adding a DEC. Its circuit and switchon and switchoff equivalent circuits are shown in
Figure 7.34.
The voltage across capacitors C
1
andC
11
is chargedwith V
1
andthe voltage across capaci
tor C
12
is chargedwithV
O
= 2V
1
. The current i
L1
ﬂowingthroughinductor L
1
increases with
V
in
during the switchon period kT and decreases with −(V
1
−V
in
) during the switchoff
period (1 −k)T. Therefore,
Δi
L1
=
V
in
L
1
kT =
V
1
−V
in
L
1
(1 −k)T (7.235)
V
1
=
1
1 −k
V
in
.
The output voltage is
V
O
= 2V
1
=
2
1 −k
V
in
. (7.236)
SuperLift Converters and Ultralift Converter 371
(a)
(b)
(c)
I
in
V
in
+
–
+
–
I
in
I
in
V
in
+
–
V
in
+
–
V
O
+
–
V
C12
V
C11
+
–
V
1
+
–
V
C11
V
L1
+
–
V
C11
+ –
V
1
C
12
C
11
C
12
C
12
+
–
D
1
D
11
D
12
I
O
I
O
I
O
C
1
C
11
C
11
C
1
L
1
L
1
V
L1
L
1
V
1
V
1
+
–
V
1 C
1
V
1
R
V
O
+
V
O
+
V
C12
+
–
R
V
C12
+
–
–
–
R
S
FIGURE 7.34 Elementary boost additional circuit: (a) circuit diagram, (b) equivalent circuit during switchon,
and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DCConverters.
Boca Raton: Taylor & Francis Group LLC, p. 319. With permission.)
The voltage transfer gain is
G =
V
O
V
in
=
2
1 −k
(7.237)
and
i
in
= I
L1
=
2
1 −k
I
O
. (7.238)
The variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)TV
in
4L
1
I
O
=
k(1 −k)
2
8
R
f L
1
. (7.239)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.240)
372 Power Electronics
7.4.2.2 TwoStage Boost Additional Circuit
The twostage additional boost circuit is derived fromthe twostage boost circuit by adding
a DEC. Its circuit diagram and switchon and switchoff equivalent circuits are shown in
Figure 7.35.
The voltage across capacitor C
1
is charged with V
1
. As described in the previous section,
the voltage V
1
across capacitor C
1
is V
1
= (1/(1 −k))V
in
.
The voltage across capacitors C
2
and C
11
is charged with V
2
and the voltage across capac
itor C
12
is charged with V
O
. The current ﬂowing through inductor L
2
increases with V
1
during the switchonperiodkT anddecreases with−(V
2
−V
1
) during the switchoff period
(1 −k)T. Therefore, the ripple of the inductor current i
L2
is
Δi
L2
=
V
1
L
2
kT =
V
2
−V
1
L
2
(1 −k)T, (7.241)
V
2
=
1
1 −k
V
1
=
_
1
1 −k
_
2
V
in
. (7.242)
The output voltage is
V
O
= 2V
2
=
2
1 −k
V
1
= 2
_
1
1 −k
_
2
V
in
. (7.243)
(a)
(b)
(c)
I
in
I
in
V
in
V
O
I
O
+
–
V
in
+
–
V
C1
+
+
– –
V
C1
+
V
C11
+
–
V
C2
+
–
+
–
V
O
I
O
+
–
+
–
D
1
V
1
V
1
V
2
V
2
+
–
V
C12
+
–
V
2
D
2
D
11
D
3
D
12
L
1
C
1
C
1
C
2
C
12
C
11
C
11
C
12
C
2
R
R
R
V
C12
L
2
L
1
L
2
I
in
V
in
+
–
V
C1
+
+
– –
– +
V
O
I
O
+
–
V
1
V
2
V
2
V
2 +
–
V
C12
V
L1
V
L2
C
12
L
1
C
1
C
2
C
11
L
2
S
FIGURE 7.35 Twostage additional boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and
(c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 321. With permission.)
SuperLift Converters and Ultralift Converter 373
(a)
(b)
(c)
V
O
I
O
V
in
V
C1
C
2
C
3
C
12
C
11
S
I
in
I
in
L
1
L
2
L
3
D
1
D
2
C
1
L
1
C
1
L
2
C
2
C
2
D
5
D
11
D
12
D
4
D
3
V
1
V
2
V
3
+
+
–
V
in
+
–
V
C1
V
1
V
2
V
3
+
–
L
3
V
2
+
–
C
11
V
3
+
–
C
12
I
O
V
3
V
C12
V
O R
+
+
–
–
+
–
I
in
V
L1
V
L2
V
L3
C
1
C
2
C
3
V
in
+
–
V
1
V
1
L
1
L
2
L
3
C
11
V
2
V
3
+
–
V
2
+
–
C
12 V
3
V
3 +
+ –
–
I
O
V
C12 R
+
–
V
O
+
–
–
V
C2
+
–
V
C3
+
–
V
C11
+
–
+
–
+
–
R
V
C12
FIGURE 7.36 Threestage additional boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon,
and (c) equivalent circuit during switchoff. (Reprinted fromLuo, F. L. andYe, H. 2006. Essential DC/DCConverters.
Boca Raton: Taylor & Francis Group LLC, p. 323. With permission.)
The voltage transfer gain is
G =
V
O
V
in
= 2
_
1
1 −k
_
2
. (7.244)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
2
(1 −k)
2
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
4L
1
I
O
=
k(1 −k)
4
8
R
f L
1
(7.245)
374 Power Electronics
and the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
4L
2
I
O
=
k(1 −k)
2
8
R
f L
2
. (7.246)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.247)
7.4.2.3 ThreeStage Boost Additional Circuit
This circuit is derivedfromthe threestage boost circuit by adding a DEC. Its circuit diagram
and equivalent circuits during switchon and switchoff periods are shown in Figure 7.36.
The voltage across capacitor C
1
is charged with V
1
. As described in the previous section,
the voltage V
1
across capacitor C
1
is V
1
= (1/(1 −k))V
in
, andthe voltage V
2
across capacitor
C
2
is V
2
= (1/(1 −k))
2
V
in
.
The voltage across capacitors C
3
and C
11
is charged with V
3
. The voltage across capacitor
C
12
is charged with V
O
. The current ﬂowing through inductor L
3
increases with voltage
V
2
during the switchon period kT and decreases with −(V
3
−V
2
) during the switchoff
period (1 −k)T. Therefore,
Δi
L3
=
V
2
L
3
kT =
V
3
−V
2
L
3
(1 −k)T, (7.248)
and
V
3
=
1
1 −k
V
2
=
_
1
1 −k
_
2
V
1
=
_
1
1 −k
_
3
V
in
. (7.249)
The output voltage is
V
O
= 2V
3
= 2
_
1
1 −k
_
3
V
in
. (7.250)
The voltage transfer gain is
G =
V
O
V
in
= 2
_
1
1 −k
_
3
. (7.251)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
2
(1 −k)
3
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2
(1 −k)
2
I
O
,
Δi
L3
=
V
2
L
3
kT, I
L3
=
2I
O
1 −k
.
SuperLift Converters and Ultralift Converter 375
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
4L
1
I
O
=
k(1 −k)
6
8
R
f L
1
, (7.252)
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
4L
2
I
O
=
k(1 −k)
4
8
R
f L
2
, (7.253)
and the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
4L
3
I
O
=
k(1 −k)
2
8
R
f L
3
. (7.254)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
12
=
I
O
kT
C
12
=
k
fC
12
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.255)
7.4.2.4 HigherStage Boost Additional Circuit
A higherstage boost additional circuit can be designed by just multiple repeating of the
parts (L
2
D
2
D
3
C
2
). For the nth stage additional circuit, the ﬁnal output voltage is
V
O
= 2
_
1
1 −k
_
n
V
in
.
The voltage transfer gain is
G =
V
O
V
in
= 2
_
1
1 −k
_
n
. (7.256)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
8
R
f L
i
(7.257)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
12
. (7.258)
376 Power Electronics
7.4.3 Double Series
All circuits of the P/O cascaded boost converters—double series—are derived from the
corresponding circuits of the main series by adding the DEC in each stage of the circuit.
The ﬁrst three stages of this series are shown in Figures 7.34, 7.37, and 7.38. For ease of
understanding, they are called the elementary double circuit, the twostage double cir
cuit, and the threestage double circuit, respectively, and are numbered n = 1, 2 and 3,
respectively.
7.4.3.1 Elementary Double Boost Circuit
From the construction principle, the elementary double boost circuit is derived from the
elementary boost converter by adding a DEC. Its circuit and switchon and switchoff
equivalent circuits are shown in Figure 7.34, which is the same as the elementary boost
additional circuit.
7.4.3.2 TwoStage Double Boost Circuit
The twostage double boost circuit is derivedfromthe twostage boost circuit by adding the
DEC in circuits of each stage. Its circuit diagram and switchon and switchoff equivalent
circuits are shown in Figure 7.37.
I
in
(a)
(b)
(c)
I
in
I
in
V
in
+
–
V
in
+ +
–
V
in
+
+
–
V
C1
C
12
+
–
V
C12 C
2
C
22
+
–
V
C2
+
–
V
C12
V
C22
+
–
–
–
+
–
+
–
V
O
+
–
V
O
+
–
+
–
L
1
L
1
V
1
+
–
+
–
V
2
+
–
R
V
2
V
1
C
1
C
12
C
2
C
22
L
2
C
11
C
21
V
1
L
1
V
L1
C
1
V
1
C
11
L
2
V
2
C
21
V
1
+
R
–
V
2
V
L2
V
2
2V1
2V1
2V1
D
1
D
2
D
11
D
12
V
C11
+
–
V
C1
C
12
C
2
C
22
+
–
V
C12
+
–
V
C2
R
+
–
V
C22
I
O
I
O
V
O
+
–
I
O
S
+
–
V
C21
L
2
D
3
D
21
C
1
C
11
C
21
D
22
V
1
FIGURE 7.37 Twostage double boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and (c)
equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 326. With permission.)
SuperLift Converters and Ultralift Converter 377
L
1
I
in
V
1
C
11
2V
1
2V
2
L
2 V
2
L
3
C
31
R
I
O
V
O
V
C32
V
3
V
3 C
3
C
32
V
C22
V
L3
V
2
V
2
V
L2
V
1
C
1 V
C12
V
C1
V
L1
V
in
C
22
C
2 C
12
+
+
+
+ + + +
+
+
+
+
–
–
–
– –
–
– –
–
–
–
V
3
C
21
(b)
(c)
V
1
V
2
2V
2
V
3
R
I
O
V
O
V
C32
V
3
V
3
2V
2
2V
1
V
1
L
1
V
1 V
in
I
in
V
2
V
2
L
2
L
3
C
32
C
3
C
22
C
2
C
12
C
1
C
31
C
21
C
11
+
+
+
+
+
+
+
+
+
+
+
–
–
–
–
–
–
–
–
–
–
–
2V
1
I
in
V
in
L
1
D
1
D
2
V
1
D
11
D
12
L
2 V
2
2V
2
D
3
D
4
D
21
D
22
D
5
V
3
D
31
C
31
V
C31
R
D
32
I
O
V
O
V
C32
V
C3
V
C22
V
C21
V
C2
V
C12
C
2
C
12
C
1
C
11
S
C
3 C
22
C
21
C
32
+
+
+
+
+
+
+
(a)
+
+ +
+
–
–
– – –
–
–
–
–
–
–
L
3
2V
1
V
C11
V
C1
FIGURE 7.38 Threestage double boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and
(c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 328. With permission.)
The voltage across capacitors C
1
and C
11
is charged with V
1
. As described in the previous
section, the voltage V
1
across capacitors C
1
and C
11
is V
1
= (1/(1 −k))V
in
. The voltage
across capacitor C
12
is charged with 2V
1
.
The current ﬂowing through inductor L
2
increases with 2V
1
during the switchon period
kT and decreases with −(V
2
−2V
1
) during the switchoff period (1 −k)T. Therefore, the
ripple of the inductor current i
L2
is
Δi
L2
=
2V
1
L
2
kT =
V
2
−2V
1
L
2
(1 −k)T, (7.259)
V
2
=
2
1 −k
V
1
= 2
_
1
1 −k
_
2
V
in
. (7.260)
The output voltage is
V
O
= 2V
2
=
_
2
1 −k
_
2
V
in
. (7.261)
The voltage transfer gain is
G =
V
O
V
in
=
_
2
1 −k
_
2
. (7.262)
378 Power Electronics
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
_
2
1 −k
_
2
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
8L
1
I
O
=
k(1 −k)
4
16
R
f L
1
(7.263)
and the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
4L
2
I
O
=
k(1 −k)
2
8
R
f L
2
. (7.264)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
22
=
I
O
kT
C
22
=
k
fC
22
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
22
. (7.265)
7.4.3.3 ThreeStage Double Boost Circuit
This circuit is derived from the threestage boost circuit by adding the DEC in each stage
circuit. Its circuit diagram and equivalent circuits during switchon and switchoff periods
are shown in Figure 7.38.
The voltage across capacitors C
1
and C
11
is charged with V
1
. As described in the previous
section, the voltage V
1
across capacitors C
1
and C
11
is V
1
= (1/(1 −k))V
in
, and the voltage
V
2
across capacitors C
2
and C
12
is V
2
= 2(1/(1 −k))
2
V
in
.
The voltage across capacitor C
22
is 2V
2
= (2/(1 −k))
2
V
in
. The voltage across capacitors
C
3
and C
31
is charged with V
3
. The voltage across capacitor C
12
is charged with V
O
. The
current ﬂowing through inductor L
3
increases with V
2
during the switchon period kT and
decreases with −(V
3
−2V
2
) during the switchoff period (−k)T. Therefore,
Δi
L3
=
2V
2
L
3
kT =
V
3
−2V
2
L
3
(1 −k)T (7.266)
and
V
3
=
2V
2
(1 −k)
=
4
(1 −k)
3
V
in
. (7.267)
The output voltage is
V
O
= 2V
3
=
_
2
1 −k
_
3
V
in
. (7.268)
SuperLift Converters and Ultralift Converter 379
The voltage transfer gain is
G =
V
O
V
in
=
_
2
1 −k
_
3
. (7.269)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
8
(1 −k)
3
I
O
Δi
L2
=
V
1
L
2
kT, I
L2
=
4
(1 −k)
2
I
O
Δi
L3
=
V
2
L
3
kT, I
L3
=
2I
O
1 −k
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
16L
1
I
O
=
k(1 −k)
6
128
R
f L
1
, (7.270)
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
8L
2
I
O
=
k(1 −k)
4
32
R
f L
2
, (7.271)
and the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
4L
3
I
O
=
k(1 −k)
2
8
R
f L
3
. (7.272)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
32
=
I
O
kT
C
32
=
k
fC
32
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
32
. (7.273)
7.4.3.4 HigherStage Double Boost Circuit
A higherstage double boost circuit can be derived from the corresponding main series
circuit by adding the DECin each stage circuit. For the nth stage additional circuit, the ﬁnal
output voltage is
V
O
=
_
2
1 −k
_
n
V
in
.
380 Power Electronics
The voltage transfer gain is
G =
V
O
V
in
=
_
2
1 −k
_
n
. (7.274)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
2 ×2
2n
R
f L
i
. (7.275)
The variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2Rf C
n2
. (7.276)
7.4.4 Triple Series
All circuits of the P/O cascaded boost converters—triple series—are derived from the cor
responding circuits of the double series by adding the DEC twice in circuits of each stage.
The ﬁrst three stages of this series are shown in Figures 7.39 through 7.41. To make it easy
to explain, they are called the elementary triple boost circuit, the twostage triple boost
circuit, and the threestage triple boost circuit, respectively, and are numbered n = 1, 2, and
3, respectively.
7.4.4.1 Elementary Triple Boost Circuit
From the construction principle, the elementary triple boost circuit is derived from the
elementary double boost circuit by adding another DEC. Its circuit and switchon and
switchoff equivalent circuits are shown in Figure 7.39.
The output voltage of the ﬁrststage boost circuit is V
1
, V
1
= V
in
/(1 −k).
The voltage across capacitors C
1
and C
11
is charged with V
1
and the voltage across capac
itors C
12
and C
13
is charged with V
C13
= 2V
1
The current i
L1
ﬂowing through inductor L
1
increases with V
in
during the switchon period kT and decreases with −(V
1
−V
in
) during
the switchoff period (1 −k)T. Therefore,
Δi
L1
=
V
in
L
1
kT =
V
1
−V
in
L
1
(1 −k)T, (7.277)
V
1
=
1
1 −k
V
in
.
The output voltage is
V
O
= V
C1
+V
C13
= 3V
1
=
3
1 −k
V
in
. (7.278)
The voltage transfer gain is
G =
V
O
V
in
=
3
1 −k
. (7.279)
SuperLift Converters and Ultralift Converter 381
I
in
(a)
(b)
(c)
I
in
I
in L
1
C
1
C
11
C
13
V
L1
V
1
V
1
2V
1
2V
1
V
in
L
1
C
1
S
C
11
C
12
C
13
D
1
D
11
D
12
D
13
D
14
2V
1
V
1
+
–
V
in
L
1
C
1
C
11
C
12
C
13
+
–
V
in
+
–
V
C1
V
C11
C
14
C
12
+
+
–
V
C12
R
+
–
–
V
C1
+
–
V
C11
+
–
V
C12
+
–
C
14
V
C13
+
–
V
C12
R
+
–
V
O
I
O
+
–
V
O
I
O
+
–
V
O
I
O
+
–
C
14
R
FIGURE 7.39 Elementary triple boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and (c)
equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 331. With permission.)
7.4.4.2 TwoStage Triple Boost Circuit
The twostage triple boost circuit is derived from the twostage double boost circuit by
adding another DECin circuits of each stage. Its circuit diagramand switchon and switch
off equivalent circuits are shown in Figure 7.40.
As described in the previous section, the voltage V
1
across capacitors C
1
and C
11
is V
1
=
(1/(1 −k))V
in
. The voltage across capacitor C
14
is charged with 3V
1
.
The voltage across capacitors C
2
and C
21
is charged with V
2
and the voltage across capac
itors C
22
and C
23
is charged with V
C23
= 2V
2
. The current ﬂowing through inductor L
2
increases with 3V
1
during the switchon period kT, and decreases with −(V
2
−3V
1
) during
the switchoff period (1 −k)T. Therefore, the ripple of the inductor current i
L2
is
Δi
L2
=
3V
1
L
2
kT =
V
2
−3V
1
L
2
(1 −k)T, (7.280)
V
2
=
3
1 −k
V
1
= 3
_
1
1 −k
_
2
V
in
. (7.281)
382 Power Electronics
V
in
+
(a)
(b)
(c)
I
in
S
L
1
D
1
C
1
L
2
R
V
O
–
+
I
O
C
11
D
11
C
12
D
12
C
13
D
13
C
14
D
14
D
2
C
21
D
21
C
22
D
22
C
23
D
23
C
24
D
24
D
3
C
2
–
V
1
2V
1
3V
1
V
2
2V
2
L
1
C
1
C
14
L
2
V
C14
+
–
+
–
V
in
I
in
R V
O
–
+
I
O
V
C24
+
–
C
24
C
12
V
C11
C
11
V
C1
+ +
– –
V
C13
C
13
V
C12
+ +
– –
C
22
V
C21
C
21
V
C2
+ +
– –
V
C23
C
23
V
C22
+ +
– –
C
2
2V
1
V
1
3V
1
V
2
2V
2
+
–
V
in
I
in
L
1
C
1
V
C1
+
–
V
L1
V
C12
C
12
+
–
C
11
V
C11
+ –
C
13
C
14
V
C14
+
–
V
C13
+ –
L
2
R V
O
–
+
I
O
C
2
+
–
V
C2
C
21
V
C21
– +
C
22
V
C22
+
–
C
23
C
24
V
C23
– +
V
C24
+
–
V
1
3
V1
2V
1
V
2
2V
2
FIGURE 7.40 Twostage triple boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and (c)
equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 333. With permission.)
The output voltage is
V
O
= V
C2
+V
C23
= 3V
2
=
_
3
1 −k
_
2
V
in
. (7.282)
The voltage transfer gain is
G =
V
O
V
in
=
_
3
1 −k
_
2
. (7.283)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
_
2
1 −k
_
2
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
2I
O
1 −k
.
SuperLift Converters and Ultralift Converter 383
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
2
TV
in
8L
1
I
O
=
k(1 −k)
4
16
R
f L
1
(7.284)
and the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)TV
1
4L
2
I
O
=
k(1 −k)
2
8
R
f L
2
. (7.285)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
22
=
I
O
kT
C
22
=
k
fC
22
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
22
. (7.286)
7.4.4.3 ThreeStage Triple Boost Circuit
This circuit is derived from the threestage double boost circuit by adding another DEC in
each stage circuit. Its circuit diagram and equivalent circuits during switchon and switch
off periods are shown in Figure 7.41.
As described in the previous section, the voltage V
2
across capacitors C
2
and C
11
is V
2
=
3V
1
= (3/(1 −k))V
in
, and the voltage across capacitor C
24
is charged with 3V
2
.
The voltage across capacitors C
3
and C
31
is charged with V
3
and the voltage across capac
itors C
32
and C
33
is charged with V
C33
= 2V
3
. The current ﬂowing through inductor L
3
increases with 3V
2
during the switchon period kT and decreases with −(V
3
−3V
2
) during
the switchoff period (1 −k)T. Therefore, the ripple of the inductor current i
L3
is
Δi
L3
=
3V
2
L
3
kT =
V
3
−3V
2
L
3
(1 −k)T (7.287)
and
V
3
=
3
1 −k
V
2
= 9
_
1
1 −k
_
3
V
in
. (7.288)
The output voltage is
V
O
= V
C3
+V
C33
= 3V
3
=
_
3
1 −k
_
3
V
in
. (7.289)
The voltage transfer gain is
G =
V
O
V
in
=
_
3
1 −k
_
3
. (7.290)
384 Power Electronics
V
in
+
I
in
(a)
(b)
(c)
S
L
2
R
C
21
D
21
C
22
D
22
C
23
D
23
C
24
D
24
D
3
C
2
–
L
1
D
1
C
1
C
11
D
11
C
12
D
12
C
13
D
13
C
14
D
14
D
2
L
3
D
5
C
3
C
31
D
31
C
32
D
32
C
33
D
33
C
34
D
34
V
O
–
+
I
O
D
4
V
1 2V
1
3V
1
V
2
2V
2
3V
2 V
3
2V
3
L
1
C
1
+
–
V
in
I
in
C
22
C
21
C
23
C
2
R V
O
–
+
I
O
C
34
C
14
L
2
C
12
C
11
C
13
C
32
C
3
C
31
L
3
C
24
C
33
V
1
2V
1
3V
1
V
2
2V
2
3V
2
V
3
2V
3
V
in
I
in
L
1
C
1
V
C1
V
L1
V
C12
C
12
C
11
V
C11
+ –
C
13
C
14
V
C14
V
C13
+ –
L
2
R V
O
–
+
I
O
C
2
V
C2
C
21
V
C21
– +
C
22
V
C22
C
23
C
24
V
C23
– +
V
C24
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
L
3
C
3 V
C3
V
C31 – +
C
31
C
32
C
33
V
C33
+ –
C
34
V
C32
V
C34
V
1
2V
1
3V
1
V
2
2V
2
3V
2
V
3
2V
3
FIGURE 7.41 Threestage triple boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and (c)
equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters. Boca
Raton: Taylor & Francis Group LLC, p. 335. With permission.)
Analogously,
Δi
L1
=
V
in
L
1
kT, I
L1
=
32
(1 −k)
3
I
O
,
Δi
L2
=
V
1
L
2
kT, I
L2
=
8
(1 −k)
2
I
O
,
Δi
L3
=
V
2
L
3
kT, I
L3
=
2
1 −k
I
O
.
Therefore, the variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
k(1 −k)
3
TV
in
64L
1
I
O
=
k(1 −k)
6
12
3
R
f L
1
, (7.291)
SuperLift Converters and Ultralift Converter 385
the variation ratio of current i
L2
through inductor L
2
is
ξ
2
=
Δi
L2
/2
I
L2
=
k(1 −k)
2
TV
1
16L
2
I
O
=
k(1 −k)
4
12
2
R
f L
2
, (7.292)
and the variation ratio of current i
L3
through inductor L
3
is
ξ
3
=
Δi
L3
/2
I
L3
=
k(1 −k)TV
2
4L
3
I
O
=
k(1 −k)
2
12
R
f L
3
. (7.293)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
32
=
I
O
kT
C
32
=
k
fC
32
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
32
. (7.294)
7.4.4.4 HigherStage Triple Boost Circuit
A higherstage triple boost circuit can be derived from the corresponding circuits of the
double boost series byaddinganother DECineachstage circuit. For the nthstage additional
circuit, the ﬁnal output voltage is
V
O
=
_
3
1 −k
_
n
V
in
.
The voltage transfer gain is
G =
V
O
V
in
=
_
3
1 −k
_
n
. (7.295)
Analogously, the variation ratio of current i
Li
through inductor L
i
(i = 1, 2, 3, . . . , n) is
ξ
i
=
Δi
Li
/2
I
Li
=
k(1 −k)
2(n−i+1)
12
(n−i+1)
R
f L
i
(7.296)
and the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n2
. (7.297)
7.4.5 Multiple Series
All circuits of P/Ocascadedboost converters—multiple series—are derivedfromthe corre
sponding circuits of the main series by adding the DECmultiple ( j) times in circuits of each
stage. The ﬁrst three stages of this series are shown in Figures 7.42 through 7.44. For ease of
understanding, they are called the elementary multiple boost circuit, the twostage multi
ple boost circuit, and the threestage multiple boost circuit, respectively, and are numbered
n = 1, 2, and 3, respectively.
386 Power Electronics
7.4.5.1 Elementary Multiple Boost Circuit
From the construction principle, the elementary multiple boost circuit is derived from the
elementary boost converter by adding the DEC multiple ( j) times in the circuit. Its circuit
and switchon and switchoff equivalent circuits are shown in Figure 7.42.
The voltage across capacitors C
1
and C
11
is charged with V
1
and the voltage across capac
itors C
12
and C
13
is charged with V
C13
= 2V
1
. The voltage across capacitors C
1(2j−2)
and
C
1(2j−1)
is charged with V
C1
(2j −1) = jV
1
. The current i
L1
ﬂowing through inductor L
1
increases with V
in
during the switchon period kT and decreases with −(V
1
−V
in
) during
the switchoff period (1 −k)T. Therefore,
Δi
L1
=
V
in
L
1
kT =
V
1
−V
in
L
1
(1 −k)T, (7.298)
V
1
=
1
1 −k
V
in
. (7.299)
V
in
+
–
I
in
S
L
1
D
1
C
1
C
11
D
11
C
12
D
12
D
1(2j–1)
V
1
2V
1
C
1(2j–1)
C
12j
D
12j(1+j)
R V
O
–
+
I
O
V
1
1 (a)
(b)
(c)
j 2...
V
in
+
–
I
in
L
1
C
1
C
12
V
C11
C
11
V
C1
+ +
– –
V
1
R V
O
–
+
I
O
C
12j
C
13
V
C12
+
–
2V
1
jV
1
C
12( j–1)
C
1(2j–1)
( j + 1)V
1
+
–
V
in
I
in L
1
C
1
V
C1
+
–
V
L1
R V
O
–
+
I
O
V
C12
C
12
+
–
C
11
V
C11
+ –
C
13
C
14
C
1(2j–1)
C
12j
V
1
2V
1
3V
1
(1+j )V
1
FIGURE 7.42 Elementary multiple boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and
(c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 338. With permission.)
SuperLift Converters and Ultralift Converter 387
The output voltage is
V
O
= V
C1
+V
C1(2j−1)
= (1 +j)V
1
=
1 +j
1 −k
V
in
. (7.300)
The voltage transfer gain is
G =
V
O
V
in
=
1 +j
1 −k
. (7.301)
7.4.5.2 TwoStage Multiple Boost Circuit
The twostage multiple boost circuit is derived from the twostage boost circuit by adding
multiple ( j) DECs in each stage of the circuit. Its circuit diagramand switchon and switch
off equivalent circuits are shown in Figure 7.43.
V
in
+
I
in
S
L
1
D
1
C
1
L
2
R V
O
–
+
I
O
C
11
D
11
C
12
D
12
C
1(2j–1)
D
1(2j–1)
C
12j
D
12j
D
2
C
21
D
21
C
22
D
22
C
2(2j–1)
D
2(2j–1)
C
24
D
22j
D
3
C
2 –
1 2... (a)
(b)
(c)
j j 2... 1
V
1
jV
1
(1+j)V
1
V
2
jV
2
(1+j)V
2
L
1
C
1
+
–
V
in
I
in
C
11
V
C1
+
–
+
–
C
12j
L
2
C
21
C
2
C
12(j–1)
V
O
–
I
O
R
+
V
C24
C
22j
C
22(j–1)
C
2(2j–1)
V
1
jV
1
(1+j)V
1
V
2
jV
2
(1+j)V
2
V
in
I
in L
1
C
1
V
C1
+
–
+
–
+
–
+
–
+
–
+
–
+
–
V
L1
V
C12
C
12
C
11
V
C11
+ –
C
1(2j–1)
C
1
L
2
R V
O
I
O
C
2
V
C2
C
21
V
C21
– +
C
22
V
C22
C
2(2j–1)
C
22j
V
C22j
V
1
(1+j)V
1
V
2
(1+j)V
2
FIGURE 7.43 Twostage multiple boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and
(c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 340. With permission.)
388 Power Electronics
The voltage across capacitors C
1
and C
11
is charged with V
1
= (1/(1 −k))V
in
. The voltage
across capacitor C
1(2j)
is charged with (1 +j)V
1
.
The current ﬂowing through inductor L
2
increases with (1 +j)V
1
during the switch
on period kT and decreases with −[V
2
−(1 +j)V
1
] during the switchoff period (1 −k)T.
Therefore, the ripple of the inductor current i
L2
is
Δi
L2
=
1 +j
L
2
kTV
1
=
V
2
−(1 +j)V
1
L
2
(1 −k)T, (7.302)
V
2
=
1 +j
1 −k
V
1
= (1 +j)
_
1
1 −k
_
2
V
in
. (7.303)
The output voltage is
V
O
= V
C1
+V
C1(2j−1)
= (1 +j)V
2
=
_
1 +j
1 −k
_
2
V
in
. (7.304)
The voltage transfer gain is
G =
V
O
V
in
=
_
1 +j
1 −k
_
2
. (7.305)
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
22j
=
I
O
kT
C
22j
=
k
fC
22j
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
22j
. (7.306)
7.4.5.3 ThreeStage Multiple Boost Circuit
This circuit is derived from the threestage boost circuit by adding multiple ( j) DECs in
circuits of each stage. Its circuit diagram and equivalent circuits during switchon and
switchoff periods are shown in Figure 7.44.
The voltage across capacitors C
1
and C
11
is charged with V
1
= (1/(1 −k))V
in
. The voltage
across capacitor C
1(2j)
is charged with (1 +j)V
1
. The voltage V
2
across capacitors C
2
and
C
2(2j)
is charged with (1 +j)V
2
.
The current ﬂowing through inductor L
3
increases with (1 +j)V
2
during the switch
on period kT and decreases with −[V
3
−(1 +j)V
2
] during the switchoff period (1 −k)T.
Therefore,
Δi
L3
=
1 +j
L
3
kTV
2
=
V
3
−(1 +j)V
2
L
3
(1 −k)T (7.307)
SuperLift Converters and Ultralift Converter 389
V
in
+
I
in
S
L
2
R
C
21
D
21
C
22
D
22
C
2(2j–1)
D
2(2j–1)
C
22j
D
22j
D
3
C
2
–
L
1
D
1
C
1
C
11
D
11
C
12
D
12
C
1(2j–1)
D
1(2j–1)
C
12j
D
12j
D
2
L
3
D
5
C
3
C
31
D
31
C
32
D
32
C
3(2j–1)
D
3(2j–1)
C
32j
D
32j
V
O
–
+
I
O
D
4
1
(a)
(b)
(c)
j 2 ...jV
1
1 2 ...jV
2
j 1 2 ...jV
3
j
V
1
(1 + j)V
1
V
2
(1+j )V
2
V
3
(1 + j )V
3
I
in
L
1
C
1
+
–
V
in
C
22( j–1) C
21
C
2(2j–1) C
2
R V
O
–
+
I
O
C
32j
C
12j
L
2
C
12( j–1)
C
11
C
1(2j–1)
C
32( j–1)
C
3
C
31
L
3
C
22j
C
3(2j–1)
V
1
jV
1
(1 + j)V
1
V
2
jV
2 (1 + j)V
2
V
3
jV
3
(1 + j)V
3
V
in
I
in
L
1
C
1
V
C1
V
L1
V
C12
C
12
C
11
V
C11
+ –
C
1(2j–1)
C
12j
L
2
R V
O
–
+
I
O
C
2
V
C2
C
21
V
C21
– +
C
22
V
C22
+
–
+
–
+
–
+
–
+
–
+
–
+
–
C
2(2j–1)
C
22j
L
3
C
3 V
C3
V
C31
– +
C
31
C
32
C
3(2j–1)
C
32j
V
C32
V
1
(1 + j)V
1
V
2
(1 + j)V
2
V
3
(1 + j)V
3
FIGURE 7.44 Threestage multiple boost circuit: (a) circuit diagram, (b) equivalent circuit during switchon, and
(c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 342. With permission.)
and
V
3
=
(1 +j)V
2
(1 −k)
=
(1 +j)
2
(1 −k)
3
V
in
. (7.308)
The output voltage is
V
O
= V
C3
+V
C3(2j−1)
= (1 +j)V
3
=
_
1 +j
1 −k
_
3
V
in
. (7.309)
The voltage transfer gain is
G =
V
O
V
in
=
_
1 +j
1 −k
_
3
. (7.310)
390 Power Electronics
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
32j
=
I
O
kT
C
32j
=
k
fC
32j
V
O
R
.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
32j
. (7.311)
7.4.5.4 HigherStage Multiple Boost Circuit
Ahigherstage multiple boost circuit is derived fromthe corresponding circuits of the main
series by adding multiple ( j) DECs in circuits of each stage. For the nth stage additional
circuit, the ﬁnal output voltage is
V
O
=
_
1 +j
1 −k
_
n
V
in
.
The voltage transfer gain is
G =
V
O
V
in
=
_
1 +j
1 −k
_
n
. (7.312)
Analogously, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
n2j
. (7.313)
7.4.6 Summary of P/O Cascaded Boost Converters
All circuits of the P/O cascaded boost converters can be shown in Figure 7.45 as the family
tree.
From the analysis of the previous two sections, the common formula to calculate the
output voltage can be presented as
V
O
=
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
_
1
1 −k
_
n
V
in
main series,
2 ∗
_
1
1 −k
_
n
V
in
additional series,
_
2
1 −k
_
n
V
in
double series,
_
3
1 −k
_
n
V
in
triple series,
_
j +1
1 −k
_
n
V
in
multiple ( j) series.
(7.314)
SuperLift Converters and Ultralift Converter 391
5 Stage boost
circuit
4 Stage boost
circuit
3 Stage boost
circuit
2 Stage boost
circuit
5 Stage additional
boost circuit
4 Stage additional
boost circuit
3 Stage additional
boost circuit
2 Stage additional
boost circuit
5 Stage double
boost circuit
4 Stage double
boost circuit
3 Stage double
boost circuit
2 Stage double
boost circuit
5 Stage triple
boost circuit
4 Stage triple
boost circuit
3 Stage triple
boost circuit
2 Stage triple
boost circuit
5 Stage multiple
boost circuit
4 Stage multiple
boost circuit
3 Stage multiple
boost circuit
2 Stage multiple
boost circuit
Elementary mulitple
boost circuit
Elementary triple
boost circuit
Elementary additional/double
boost circuit
Positive output elementary boost converter
Main
series
Additional
series
Double
series
Triple
series
Multiple
series
FIGURE 7.45 The family of P/O cascaded boost converters. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential
DC/DC Converters. Boca Raton: Taylor & Francis Group LLC, p. 344. With permission.)
The voltage transfer gain is
V
O
=
V
O
V
in
=
⎧
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎪
⎩
_
1
1 −k
_
n
main series,
2 ∗
_
1
1 −k
_
n
additional series,
_
2
1 −k
_
n
double series,
_
3
1 −k
_
n
triple series,
_
j +1
1 −k
_
n
multiple ( j) series.
(7.315)
392 Power Electronics
7.5 N/O Cascaded Boost Converters
This section introduces N/Ocascaded boost converters. Like P/Ocascaded boost convert
ers, these converters implement the SL technique [1,2].
7.5.1 Main Series
The ﬁrst three stages of the N/O cascaded boost converters—main series—are shown in
Figures 7.46 through 7.48. For ease of understanding, they are called the elementary boost
converter, the twostage boost circuit, and the threestage boost circuit, respectively, and
are numbered n = 1, 2, and 3, respectively.
7.5.1.1 N/O Elementary Boost Circuit
The N/O elementary boost converter and its equivalent circuits during switchon and
switchoff periods are shown in Figure 7.46.
The voltage across capacitor C
1
is charged with V
C1
. The current i
L1
ﬂowing through
inductor L
1
increases with V
in
during the switchon period kT and decreases with
C
1
D
1
S
R
V
in
+
(a)
(b)
(c)
V
O
+
–
–
I
in
I
O
L
1
R
V
in
+
_
+
_
I
in
V
O
I
O
L
1
C
1
V
C1
+
_
R
V
in
+
_
+
_
I
in
V
O
I
O
L
1
C
1
V
C1
+
_
FIGURE 7.46 N/O elementary boost converter: (a) circuit diagram, (b) equivalent circuit during switchon, and
(c) equivalent circuit during switchoff. (Reprinted from Luo, F. L. and Ye, H. 2006. Essential DC/DC Converters.
Boca Raton: Taylor & Francis Group LLC, p. 352. With permission.)
SuperLift Converters and Ultralift Converter 393
−(V
C1
−V
in
) during the switchoff period (1 −k)T. Therefore, the ripple of the inductor
current i
L1
is
Δi
L1
=
V
in
L
1
kT =
V
C1
−V
in
L
1
(1 −k)T, (7.316)
V
C1
=
1
1 −k
V
in
,
V
O
= V
C1
−V
in
=
k
1 −k
V
in
. (7.317)
The voltage transfer gain is
G =
V
O
V
in
=
1
1 −k
−1. (7.318)
The inductor average current is
I
L1
=
1
1 −k
V
O
R
. (7.319)
The variation ratio of current i
L1
through inductor L
1
is
ξ
1
=
Δi
L1
/2
I
L1
=
kTV
in
2L
1
V
O
/(1 −k)R
=
k(1 −k)
2G
R
f L
1
=
(1 −k)
2
2
R
f L
1
. (7.320)
Usually ξ
1
is small (much lower than unity); this means that this converter works in the
continuous mode.
The ripple voltage of output voltage v
O
is
Δv
O
=
ΔQ
C
1
=
I
O
kT
C
1
=
k
fC
1
V
O
R
,
since ΔQ = I
O
kT.
Therefore, the variation ratio of output voltage v
O
is
ε =
Δv
O
/2
V
O
=
k
2RfC
1
. (7.321)
7.5.1.2 N/OTwoStage Boost Circuit
The N/O twostage boost circuit is derived from the N/O elementary boost converter by
addingthe parts (L
2
D
2
D
3
C
2
). Its circuit diagramandequivalent circuits duringswitchon
and switchoff periods are shown in Figure 7.47.
The voltage across capacitor C
1
is charged with V
1
. As described in the previous section,
the voltage V
1
across capacitor C
1
is V
1
= (1/(1 −k))V
in
.
The voltage across capacitor C
2
is chargedwithV
C2
. The current ﬂowingthroughinductor
L
2
increases withV
1
duringthe switchonperiodkT anddecreases with−(V
C2
−V
1
) during
394 Power Electronics
C
1
D
1
S
R
V
in
+
(a)