8086 ARCHITECTURE

DIAGRAM 1 DIAGRAM 2 DIARGAM 3 .

DIAGRAM 4 DIAGRAM 5 .

REFER DIAGRAM 1 Figure shows a block diagram of the 8086 internal architecture. the 8086 microprocessor is internally divided into two separate functional units. and writes data to memory and I/O ports. reads data from memory and ports. As shown in the figure. The BIU fetches instructions. The EU executes . These are the Bus Interface Unit (BIU) and the Execution Unit (EU).

and bus control. the CS is multiplied by 1610 by the BIU for computing the 20-bit physical address. This is done in order to speed up program execution by overlapping instruction fetch with execution. The BIU’s instruction queue is a First-In First-out (FIFO) group of registers in which up to six bytes of instruction code are perfected from memory ahead of time. The 8086 can directly address four segments (256K byte within the1 Mbytes memory) at a particular time. Programs obtain access to code and data in the segments by changing the segment register contents to point to the desired segments. and address generation bus control circuitry to provide functions such as fetching and queuing of instructions. The BIU contains segment registers. the Stack Segment (SS) register. and the Extra Segment (ES) register. The BIU and EU function independently. The BIU contains a dedicated adder. If an instruction such as Jump or subroutine call is encountered. For example. the BIU first completes fetching and then services the EU : the queue allows the BIU to keep the EU supplied with perfected instructions without typing up the system bus. if [CS] = 456A16 and [IP] = 162016. then the 10-bit physical address is generated by the BIU as follows: .instructions that have already been fetched by the BIU. The BIU has four 16-bit segment registers. if the BIU’s is not full and if it can store at least two bytes and the EU does not request it to access memory. which is used to produce the 20-bit address. instruction pointer. if BIU is interrupted by EU for memory access while the BIU is in the process of fetching an instruction. This mechanism is known as pipelining. the Data Segment (DS) register. the BIU will reset the queue and begin refilling after passing the new instruction to the EU. the BIU may prefect instructions. the BIU does not perform any bus cycle. These are the Code Segment (CS) register. However. All program instructions must be located in main memory pointed to by the 16-bit CS register with a 16-bit offset in the segment contained in the 16-bit instruction pointer (IP). instruction queue. This means that all instructions of a program are relative to the contents of the CS register multiplied by 16 and then offset is added provided by the 16-bit contents of IP. The BIU interfaces the 8086 to the outside world. In other words. The BIU provides all external bus operations. If the queue is full and the EU does not request BIU to access memory. The bus control logic of the BIU generates all the bus control signals such as read and write signals for memory and I/O. The BIU computes the 20-bit physical address internally using the programmer-provided logical address (16-bit contents of CS and IP) by logically shifting the contents of CS four bits to left and then adding the 16-bit contents of IP. The 8086’s onemegabyte memory is divided into segments of up to 64K bytes each. On the other hand.

. 0002016 . partially overlapped. Typical examples of values of segments should then be selected based on physical addresses starting at 0000016 . and SEGMENTS 2 and 4 are disjoint. 0003016. the 20-bit physical stack address is calculated from BP and SS.SEGMENTS 1 an d 2 are partially overlapped. A physical memory location may be mapped into (contained in) one or more logical segments. The 16-bit contents of Source Index (SI) or Destination Index (DI) are used as offset for computing the 20-bit physical address. The segment can be continuous. and IP contains the distance or offset from this address to the next instruction byte to be fetched. operands for most instructions are fetched from this segment. Note that immediate data are considered as part of the code segment. fully overlapped. the CS contains the base or start of the current code segment. The SS register points to the current stack. or disjoint. REFER DIAGRAM 2 In the above SEGMENTS 0 and 1 are contiguous (adjacent) .. The programmer Can use the BP register instead of SP for accessing the stack using the based addressing mode. Every segment must start on 16-byte memory boundaries. Many applications can be written to simply initialize the segment and then forget them. The 20-bit physical stack address is calculated from SS and SP for stack instruction such as PUSH and POP. SEGMENTS 2 and 3 are fully overlapped. … FFFF016 . The ES register points to the extra segment in which data (in excess of 64k pointed to by DS) is stored. The DS register points to the current data segment. String instructions always use ES and DI to determine the 20-bit physical address for the destination. In this case. In the other words. 0001016 . An example of how five (segment 0 through segment 4) may be stored in physical memory are shown.Four times logically shifted [CS] to left = 456A016 + [IP] as offset = 162016 20-bit physical address = 46CC016 The BIU always inserts four Zeros for the lowest 4-bits of the 20-bit starting address (physical) of a segment.

BX register is called the base register. hanging the CPU if READY is not returned. BX. SI. Failure to comply with this guideline may result in an attempted opcode fetch from nonexistent memory. and DX can be used as two 8-bit registers (AH. This is the only generalpurpose register. BL. the 16bit register DX can be considered as two 8-bit registers DH (high byte of DX) and DL (low byte of DX). For example. DH. It should be pointed out that codes should not be written within 6 bytes of the end of physical memory. the AX is called the 16-bit accumulator while the AL is the 8bit accumulator. The BX register is similar to 8085 HL register. For example. CS. BX. the 8086 executes the next instruction. The 16-bit registers AX. The use of accumulator registers is assumed by some instructions. CX. Note that for string instructions. The general-purpose registers AX. BH. For example. In other words. CH. The EU has eight 16-bit general registers.or 8-bit data to or from and I/O port. Multiplication and division instructions also use AX or AL. . One example of four currently addressable segments is shown below : REFER DIAGRAM 3 The EU decodes and executes instructions. and DX are named after special functions carried out by each one of them. DL). DS and ES may point to the same segment in memory if a string located in that segment is used as a source segment in one string instruction and as a destination segment in another string instruction. If is zero. 8086 BH and BL are equivalent to 8085 H and L registers. All memory references utilizing these register contents for addressing use Ds as the default segment register. For example. The EU has a 16-bit ALU for performing arithmetic and logic operations. CX. The Input/Output (IN or OUT) instructions always use AX or AL for inputting/outputting 16. and loop instructions use the contents of CX as a counter.A segment can be pointed to by more than one segment register. the contents of which can be used for addressing 8086 memory. DX. The CX register is known as the counter register. BX. the instruction LOOP START will automatically decrement CX by 1 without affecting flags and will check if [CX]=0. and DI. BP. AL. CL. ES must point to a destination segment. SP. The AL register is the same as the 8085 A register. A decoder in the EU control system translates instructions. respectively. otherwise the 8086 branches to the label START. This is because some instructions such as shift rotate. These are AX.

The 8086 has three control bits in the flag register which can be set or reset by the programmer: setting DF (Direction Flag) to one causes string instructions to auto decrement and clearing DF to zero causes string instructions to auto increment. SP (stack pointer) and BP (base pointer). The SP contents are automatically updated (incremented or decremented) due to execution of POP or PUSH instruction. Setting IF (Interrupt Flag) to one causes the 8086 to recognize external mask able interrupts. any instruction may belong to one or more addressing modes. The two pointer registers. CF (Carry Flag) is set if there is a carry from addition or borrow from subtraction. Depending upon the data types used in the instruction and the memory addressing modes. REFER DIAGRAM4 The 8086 have six one-bit flags. or . the 8086 generate an internal interrupt after execution of each instruction. In this mode. are used to access data in stack segment. ADDRESSING MODES OF 8086 Addressing mode indicates a way of locating data or operands. An interrupt on overflow instructions is available which will generate an interrupt in this situation. AF (Auxiliary carry flag) is used by BCD bit) into the high nibble or a borrow from the high nibble into the low nibble of the low-order 8-bit of a 16-bit number. The FLAG register in the EU holds the status flags typically after an ALU operation. This offset is used by the instructions utilizing the based addressing mode. PF (Parity Flag) is set if the result has even parity. OF (Overflow Flag) is set if there is an arithmetic overflow. that is. if the size of the result exceeds the capacity of the destination location. PF is zero for odd parity of the result. ZF (Zero Flag) is set if the result is zero. The SP is used as an offset from the current SS during execution of instructions that involve stack segment in external memory. clearing IF to zero disables these interrupts. The user can write a service routine at the interrupt address vector to display the desired registers and memory locations.The data register DX is used to hold high 16-bit result (data) in 16* 16 multiplication or high 16-bit dividend (data) before a 32 ÷ 16 division and the 16-bit remainder after the division. ZF is zero for non-zero result. The base pointer contains an offset address in the current SS. Setting TF (Trace Flag) to one places the 8086 in the single-step mode. SF (Sign Flag) is set if the most significant bit of the result is one (Negative) and is cleared to zero for non-negative result. The user can thus debug a program.

Here. The default segment is either DS or ES. In this addressing mode. which after execution. except IP.some instruction may not belong to any of the addressing modes. data transfer and processor control instructions are sequential control flow instructions. whose effective address may be computed using 5000H as the offset address and content of DS as segment address. For example. The addressing modes for sequential control transfer instructions are explained as follows: 1. According to the flow of instruction execution. the data is stored in a register and it is referred using the particular register. INT. RET and JUMP instructions fall under this category. The data is supposed to be available at the address . is determined in an indirect way. Example: MOV AX. [5000H] Here. All the registers. 0005H is the immediate data. which contains data or operand. logical. 3. 4. we will present the addressing modes of the instructions depending upon their types. transfer control to some predefined address somehow specified in the instruction after their execution. Direct: In the direct addressing mode. here. a 16-bit memory address (offset) is directly specified in the instruction as a part of it. AX. The control transfer instructions. Example: MOV AX. is 10H*DS+5000H. 0005H In the above example. the arithmetic. the offset address of data is in either BX or SI or DI registers. Example: MOV BX. Thus the addressing modes describe the types of operands and the way they are accessed for executing an instruction. Sequential control flow instructions are the instructions. data resides in a memory location in the data segment. The effective address. The immediate data may be 8-bit or 16-bit in size. This mode of addressing is known as register indirect mode. the address of the memory location. 2. Register: In register addressing mode. transfer control to the next instruction appearing immediately after it (in the sequence) in the program. using the offset registers. Immediate: In this type of addressing. and appears in the form of successive byte or bytes. Register Indirect: Sometimes. CALL. the instructions may be categorized as (i) Sequential control flow instructions and (ii) Control transfer instructions. on the other hand. may be used in this mode. For example. immediate data is a part of instruction.

8. the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX. Register Relative: In this addressing mode. 50H [BX] [SI] Here. [BX] [SI] Here. [SI] Here. offset of the operand is stored in one of the index registers. DS and ES are the default segments for index registers SI and DI respectively. This mode is a special case of the above discussed register indirect addressing mode. 6. the addressing modes depend upon whether the destination location is within the same segment or a different one. 5. 7. The effective address. effective address is given as 10H*DS+50H+ [BX]. intersegment and intra-segment addressing modes. BP. by adding content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default segment register may be ES or DS. Relative Based Indexed: The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of contents of any one of the bases registers (BX or BP) and any one of the index registers. For the control transfer instructions. Example: MOV AX. Example: MOV AX. BX is a base register and SI is an index register. in this case. The effective address of the data is given as 10H*DS+ [BX]. 50H [BX] Here. [BX] Here. data is available at an offset address stored in SI in DS. Basically. Indexed: In this addressing mode. Based Indexed: The effective address of data is formed. SI and DI in the default (either DS or ES) segment. Example: MOV Ax. Example: MOV AX. 50H is an immediate displacement. BX is the base register and SI is the index register. . is computed as 10H*DS+ [SI]. It also depends upon the method of passing the destination address to the processor. The example given before explains this mode. viz. in a default segment. there are two addressing modes for the control transfer instructions. data is present in a memory location in DS whose offset address is in BX. The effective address is computed as 10H*DS+ [BX] + [SI].pointed to by the content of any of the above registers in the default data segment. The effective address of data is computed as 160H*DS+ [BX] + [SI] + 50H. Example: MOV AX. in this addressing mode.

If the destination location lies in the same segment.If the location to which the control is to be transferred lies in a different segment other than the current one. Intra-segment Indirect Mode: In this mode. the mode is called inter-segment mode. the branch address is found as the content of a register or a memory location. we term it as short jump and if it is of 16 bits (i. but it is passed to the instruction indirectly. Intra-segment direct mode: In this mode. The effective address to which the control will be transferred is given by the sum of 8 or 16 bit displacement and current content of IP. This addressing mode may be used in unconditional branch instructions. if the signed displacement (d) is of 8 bits (i. – 128<d<+128). In case of jump instruction. is in the same segment in which the control transfer instruction lies. Inter-segment Direct Inter-segment Inter-segment Indirect Modes for control Transfer instructions Intra-segment Intra-segment Direct Intra-segment Indirect Addressing Modes for Control Transfer Instruction 9. 10. the displacement to which the control is to be transferred. the displacement is computed relative to the content of the instruction pointer IP. the address to which the control is to be transferred lies in the same segment in which the control transfer instruction lies and appears directly in the instruction as an immediate displacement value. the mode is called intra-segment. In this addressing mode. –32768<+32768). Here. it is termed as long jump. .e.e.

and the Register/Memory (R/M) field and are defined as follows.e. contents of a memory block containing four bytes. These are the Mode (MOD) field.11. on the other hand. The 2-bit MOD field specifies whether the operand is in register or memory as follows: MOD 0 1 10 Interpretation Memory mode with no displacement follows except for 16-bit Displacement when R/M = 110 Memory mode with 8-bit displacement Memory mode with 16-bit displacement . REFER DIAGRAM5 The op code. register direction bit (D) and data size bit (W) in byte 1 are defined by Intel as follows:  Op code occupies six bits and it defines the operation to be carried out by the instruction. It defines whether the register operand in byte 2 is the source or destination operand. Inter-segment Indirect Mode: In this mode. the CS and IP of the destination address are specified directly in the instruction. Here. The general 8086instruction format is shown in the figure.  Data size bit (W) defines whether the operation to be performed is on 8or 16. Inter-segment Direct Mode: In this mode. The starting address of the memory block may be referred using any of the addressing modes. the address to which the control is to be transferred lies in a different segment and it is passed to the instruction indirectly. IP (MSB). the register (REG) field. IP (LSB). W = 0 indicates 8-bit operation while W = 1 specifies 16bit operation.  Register Direction bit (D) occupies one bit. 12. i. i. except immediate mode. this byte contains three fields.  The second byte of the instruction usually identifies whether one of the operands is in memory or whether both are registers. This addressing mode provides a means of branching from one code segment to another code segment. D = 0 indicates that the register is a source operand. D = 1 specifies that the register operand is the destination operand.e. 8086 INSTRUCTION FORMAT The 8086 instruction sizes vary from one to six bytes. CS (LSB) and CS (MSB) sequentially.bit data. the address to which the control is to be transferred is in a different segment.

If MOD selects memory mode. then R/M indicates how the effective address of the memory operand is to be calculated. BL. As an example.11 Register mode (no displacement) REG field occupies 3 bits. The R/M field along with the MOD field defines the second operand as shown below: DIAGRAM 6 MOD 11 -----------------------------------R/M W=0 W=1 000 001 010 011 100 101 110 AL CL DL BL AH CH DH AX CX DX BX SP BP SI Effective address calculation --------------------------------------------------------------R/M MOD=00 MOD=01 MOD=10 000 001 010 011 100 101 110 (BX)+(SI) (BX)+(SI)+D8 (BX)+(SI)+D16 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16 (SI) (SI)+D8 (SI)+D16 (DI) (DI)+D8 (DI)+D16 DIRECT (BP)+D8 (BP)+D16 ADDRESS 111 BH DI 111 (BX) (BX)+D8 (BX)+D16 In the above. then R/M identifies the second register operand. It defines the register for the first operand. Bytes 3 through 6 of an instruction are optional fields that normally contain the displacement value of a memory operand and/or the actual value of an immediate constant operand. which is specified as the source or destination by the D-bit (byte 1). consider the instruction MOV CH. If MOD = 11 (register-to-register mode). . The definition of REG and W fields are given below: REG 000 001 010 011 100 101 110 111 W=0 AL CL DL BL AH CH DH BH W=1 AX CX DX BX SP BP SL DI The R/M field occupies 3 bits. encoding of the R/M field depends on how the mode field is set.

The D-bit indicates whether the register specified by the REG field of byte 2 is a source or destination operand. therefore. The R/M field = 101 (base-2) specifies that the destination register is CH and. Let us define the BL in the REG field of byte 2. Hence the machine code for MOV CH. . MOD field is 11 (base2). In byte 2. The 6-bit op code for this instruction is 100010 (base-2). R/M = 101 (base-2). We will determine the machine code of this instruction. The W-bit of byte 1 is 0 since this is a byte operation. since the second operand is a register. D = 0 indicates that the REG field of the next byte is the source operand.This instruction transfers the 8-bit content of BL into CH. BL is 100010 11011101 BYTE 1 BYTE 2 = 89DD (base-16).

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