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VLSI Design

Dr. Bassel Soudan – University of Sharjah

1

MOS Transistor Capacitance

• • •

**Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important
**

– Creates channel charge necessary for operation

**Source and drain have capacitance to body
**

– Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion

VLSI Design

Dr. Bassel Soudan – University of Sharjah

2

**MOS Transistor Capacitance
**

Gate Source CGS CGD CGB CSB CDB

CSB Gate

Drain

Source CGS CGD CGB

Drain

CDB

VDD

VLSI Design

Dr. Bassel Soudan – University of Sharjah

3

Gate Capacitance

CGB =

ε OX WL

tOX

= COX WL

• • •

**Define Cpermicron = CoxL
**

– Typically about 2 fF/µm

Therefore, CGB = Cpermicron X W Realistically, there are additional capacitances. However, the above relationship is a polysilicon good approximation gate W of the gate t capacitance. SiO L

ox

n+

n+

gate oxide 2 (good insulator, εox = 3.9ε0)

p-type body

VLSI Design

Dr. Bassel Soudan – University of Sharjah

4

Diffusion Capacitance

• • •

**CSB, CDB Undesirable, called parasitic capacitance Capacitance depends on area and perimeter
**

– Comparable to CG for contacted diffusion – ½ CG for uncontacted – Varies with process

VLSI Design

Dr. Bassel Soudan – University of Sharjah

5

MOSFET Resistance

•

**The resistance of a MOSFET transistor must be determined from the Shockley I-V relationships.
**

– However, Ids(Vds, Vgs). – Therefore, R – the resistance to current moving from the drain to the source is:

⎛ ∂I ⎞ R = ⎜ ds ⎟ ⎜ ∂V ⎟ ⎝ ds ⎠

−1

•

However,

– Shockley models for MOSFET transistor are not accurate enough for modern transistors – Too complicated for hand analysis

VLSI Design

Dr. Bassel Soudan – University of Sharjah

6

Effective Resistance

•

**Simplification: treat transistor as resistor
**

– Replace with effective resistance R

• Ids = Vds/R

**– R averaged across switching range of digital gate
**

• Simulate the transistor driving a known capacitance and measure the time constant. • Too inaccurate to predict current at any given time

– But good enough to predict RC delay

VLSI Design

Dr. Bassel Soudan – University of Sharjah

7

RC Delay Model

•

**Use equivalent circuits for MOS transistors
**

– Ideal switch + capacitances and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C

• The PMOS resistance should actually be (k’n/k’p)R

• •

g

**Capacitance proportional to width Resistance inversely proportional to width
**

d R/k g kC s kC kC s k d kC g kC d s kC 2R/k g d k s

VLSI Design

Dr. Bassel Soudan – University of Sharjah

8

RC Values

• • •

Capacitance

– C = Cg = Cs = Cd = 2 fF/µm of gate width – Values similar across many processes

Resistance

– R ≈ 6 KΩ*µm in 0.6um process – Improves with shorter channel lengths

Unit transistors

– May refer to minimum contacted device (4/2 λ) – Or maybe 1 µm wide device – Doesn’t matter as long as you are consistent

9

VLSI Design

Dr. Bassel Soudan – University of Sharjah

Input Capacitance of the CMOS Inverter

•

**The input capacitance of the CMOS inverter can be written as:
**

– Cin = CGN + CGP = (WN + WP) Cpermicron – Cpermicron = COX X L:

• COX – the oxide capacitance which depends on the type of oxide used and is inversely dependent on the thickness of the oxide layer.

– COX is typically in the range of ~700aF/µm2 » a stands for atto – 10-18.

• L – the length of the channel.

VLSI Design

Dr. Bassel Soudan – University of Sharjah

10

Example

•

**Calculate the input capacitance for a CMOS inverter with the following characteristics:
**

– COX = 690 aF/µm2 – WN / LN = 4µm / 2µm – WP / LP = 8µm / 2µm

Using the expressions from above: Cin = (WN + WP) Cpermicron Cpermicron = L COX Cpermicron = 2µm X 690 aF/µm2 = 1.38 fF/µm Cin = (4µm + 8µm) X 1.38 fF/µm Cin = 16.56 fF

VLSI Design

Dr. Bassel Soudan – University of Sharjah

11

Inverter Delay Estimate

•

Estimate the delay of a fanout-of-1 inverter

A

2 Y 1

2 1

VLSI Design

Dr. Bassel Soudan – University of Sharjah

12

Inverter Delay Estimate

•

**Estimate the delay of a fanout-of-1 inverter
**

2C R 2C 2C Y 1 R C C

A

2 Y 1

2

C

VLSI Design

Dr. Bassel Soudan – University of Sharjah

13

Inverter Delay Estimate

•

**Estimate the delay of a fanout-of-1 inverter
**

2C R 2C 2C Y 1 R C R C C C 2C

A

2 Y 1

2

2C

C

VLSI Design

Dr. Bassel Soudan – University of Sharjah

14

Inverter Delay Estimate

•

**Estimate the delay of a fanout-of-1 inverter
**

2C R 2C 2C Y 1 R C R C C C 2C

A

2 Y 1

2

2C

C

d = 6RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

15

Delay Components

•

**Delay has two parts
**

– Parasitic delay – due to capacitances of the driving gate itself.

• 3 RC in the inverter example above. • Independent of load.

**– Effort delay – due to capacitances of the load gates.
**

• The other 3 RC in the inverter example above. • Depends on the number and type of driven gates.

VLSI Design

Dr. Bassel Soudan – University of Sharjah

16

Example: 3-input NAND

•

Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

VLSI Design

Dr. Bassel Soudan – University of Sharjah

17

Example: 3-input NAND

•

Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

VLSI Design

Dr. Bassel Soudan – University of Sharjah

18

Ex.: Capacitances of a 3-input NAND

•

Determine the parasitic capacitances of a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

2

2

2 3 3 3

VLSI Design

Dr. Bassel Soudan – University of Sharjah

19

3-input NAND Caps

•

Annotate the 3-input NAND gate with gate and diffusion capacitance.

2

2

2

3 3 3

VLSI Design

Dr. Bassel Soudan – University of Sharjah

20

3-input NAND Caps

•

**Annotate the 3-input NAND gate with gate and diffusion capacitance.
**

2C 2 2C 2 2C 2

2C 2C

2C 2C

2C 2C

3C 3C 3C

3 3 3

3C 3C 3C 3C

21

VLSI Design

Dr. Bassel Soudan – University of Sharjah

Combining Capacitances

• •

Capacitors on source diffusions of transistors connected to VDD or GND will be shorted out. The DC voltage on the second terminal of a capacitor is irrelevant to delay calculation.

– Therefore, all capacitors will be estimated as terminating to GND.

•

Combine parallel and series capacitances in the normal manner.

VLSI Design

Dr. Bassel Soudan – University of Sharjah

22

3-input NAND Caps

•

Annotate the 3-input NAND gate with gate and diffusion capacitance.

2 5C 5C 5C

VLSI Design

2

2 3 3 3 9C 3C 3C

Dr. Bassel Soudan – University of Sharjah

23

Elmore Delay

• • •

t pd ≈

ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder

∑

Ri −to − sourceCi

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

R1 R2 C1 R3 C2 C3 RN CN

nodes i

VLSI Design

Dr. Bassel Soudan – University of Sharjah

24

Example: 2-input NAND

•

Estimate worst-case rising and falling delay of 2input NAND driving h identical gates.

2 A B

2 2 2x

Y

h copies

VLSI Design

Dr. Bassel Soudan – University of Sharjah

25

Example: 2-input NAND

•

Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

2 A B

2 2 2x 6C 2C

Y 4hC

h copies

VLSI Design

Dr. Bassel Soudan – University of Sharjah

26

Example: 2-input NAND

•

Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

2 A B

2 2 2x 6C 2C

Y 4hC

h copies

R Y (6+4h)C

t pdr = ( 6 + 4h ) RC

Dr. Bassel Soudan – University of Sharjah

27

VLSI Design

Example: 2-input NAND

•

Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

2 A B

2 2 2x 6C 2C

Y 4hC

h copies

VLSI Design

Dr. Bassel Soudan – University of Sharjah

28

Example: 2-input NAND

•

Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

2 A B

2 2 2x 6C 2C

Y 4hC

h copies

x R/2

R/2 2C

Y (6+4h)C

t pdf = ( 2C ) ( R ) + ⎡( 6 + 4h ) C ⎤ ( R + R ) 2 ⎣ ⎦ 2 2 = ( 7 + 4h ) RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

29

Diffusion Capacitance

• • •

we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact

– Reduces output capacitance by 2C – Merged uncontacted diffusion might help too

2C Shared Contacted Diffusion Merged Uncontacted Diffusion 3C 3C 3C 2C Isolated Contacted Diffusion

2

2

2 3 3 3 7C 3C 3C

VLSI Design

Dr. Bassel Soudan – University of Sharjah

30

Layout Comparison

•

**Which layout is better?
**

VDD VDD

A

B

A

B

Y

Y

GND

VLSI Design

GND

Dr. Bassel Soudan – University of Sharjah

31

Determining the Total Delay for a Circuit

•

In order to determine the total delay for a circuit, one has to determine the delay of each stage and then calculate the total delay for all stages combined.

– Two delays: rising and falling.

•

**Example, using Elmore Delay Model, determine the total delay of the following circuit:
**

IN OUT 12 C

VLSI Design

Dr. Bassel Soudan – University of Sharjah

32

**Determine Transistor Sizes
**

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1 P: 4 N: 1

OUT 12 C

P: 2 N: 3 P: 2 N: 1

VLSI Design

Dr. Bassel Soudan – University of Sharjah

33

**Assume Logic Transition
**

PUN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PUN

P: 4 N: 1

PDN

1

PDN

0

OUT 12 C

P: 2 N: 3 P: 2 N: 1

VLSI Design

Dr. Bassel Soudan – University of Sharjah

34

**Determine Individual Stage Delays
**

PUN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PUN

P: 4 N: 1

PDN

1

PDN

0

OUT 12 C

P: 2 N: 3 P: 2 N: 1

R

3C

4(4C)

d = 19RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

35

**Determine Individual Stage Delays
**

PUN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PUN

P: 4 N: 1

PDN

1

OUT 12 C

PDN

0

P: 2 N: 3 P: 2 N: 1

R

6C

3C

d = 9RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

36

**Determine Individual Stage Delays
**

PUN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PUN

P: 4 N: 1

PDN

1

OUT 12 C

PDN

0

P: 2 N: 3 P: 2 N: 1

R

3C

5C + 5C + 3C = 13C

d = 16RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

37

**Determine Individual Stage Delays
**

PUN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PUN

P: 4 N: 1

PDN

1

OUT 12 C

PDN

0

P: 2 N: 3 P: 2 N: 1

R/2

R/2

4C

6C

12C

d = (R/2)4C + (R/2 + R/2) (6C + 12C) = 20RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

38

**Total Rising Output Delay
**

PUN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PUN

P: 4 N: 1

PDN

1

PDN

0

OUT 12 C

P: 2 N: 3 P: 2 N: 1

Tpdr =

19RC

+

9RC

+

16RC

+

20RC =

64RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

39

**Other Logic Transition
**

PDN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PDN

P: 4 N: 1

PUN

1

PUN

0

OUT 12 C

P: 2 N: 3 P: 2 N: 1

VLSI Design

Dr. Bassel Soudan – University of Sharjah

40

**Determine Individual Stage Delays
**

PDN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PDN

P: 4 N: 1

PUN

1

PUN

0

OUT 12 C

P: 2 N: 3 P: 2 N: 1

R

3C

4(4C)

d = 19RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

41

**Determine Individual Stage Delays
**

PDN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PDN

P: 4 N: 1

PUN

1

OUT 12 C

PUN

0

P: 2 N: 3 P: 2 N: 1

R/2

R/2

2C

6C

3C

d = (R/2)2C + (R/2 + R/2) (6C + 3C) = 10RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

42

**Determine Individual Stage Delays
**

PDN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PDN

P: 4 N: 1

PUN

1

OUT 12 C

PUN

0

P: 2 N: 3 P: 2 N: 1

R

3C

5C + 5C + 3C = 13C

d = 16RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

43

**Determine Individual Stage Delays
**

PDN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PDN

P: 4 N: 1

PUN

1

OUT 12 C

PUN

0

P: 2 N: 3 P: 2 N: 1

R

6C

12C

d = 18RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

44

**Total Falling Output Delay
**

PDN

IN

P: 2 N: 1 P: 2 N: 2 P: 2 N: 1

PDN

P: 4 N: 1

PUN

1

PUN

0

OUT 12 C

P: 2 N: 3 P: 2 N: 1

Tpdf =

19RC

+

10RC

+

16RC

+

18RC =

63RC

VLSI Design

Dr. Bassel Soudan – University of Sharjah

45

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