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Latches and Flip-Flops

Dr. Le Dung
Faculty of Electronics and Telecommunications Hanoi University of Science and Technology

Content
Memory element Latches Flip-Flops

Dr. Le Dung

Hanoi University of Science and Technology

A device with exactly two stable states


Bistable multivibrator circuit

2 stable states

Q1 on Q1 off

Q2 off Q2 on

as a memory element can store one bit

Dr. Le Dung

Hanoi University of Science and Technology

Memory element
Excitation inputs

1-state or 0-state

Q Q

1-state (set): Q=1, Q=0 0-state (reset): Q=0, Q=1 Inhibited-state: Q=Q

Latch
Set Reset Q
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Flip-Flop (with clock)


Set

Excitation inputs

Reset Clock Q
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Latches
SR latch (Set-Reset latch) + with NOR structure + with NAND structure Gated SR latch D latch (Delay or Data latch = transparent latch) Some applications of the latches (1) (2) (3)

Dr. Le Dung

Hanoi University of Science and Technology

Set-Reset Latch with NOR structure


S 0 0 1 1
SR=00 Latch

SR latch
S, R active High
SR=00 Latch

NOR structure

R 0 1 0 1

Q (next) Q (latch)* 0 (reset) 1 (set)


Q=Q=0
(Inhibited)

SR=10

Set
Q=1,Q=0

Reset
SR=01
Q=0,Q=1

* Latch = No change

SR=10
SR=11

SR=01

X
Q=Q

SR=11

State diagram (Moore)


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Inhibited
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Set-Reset Latch with NAND structure


S 0
SR latch
S, R active Low
SR=11 Latch SR=01 SR=11 Latch

R Q (next) 0 Q=Q=1
(Inhibited)

NAND structure

0 1 1

1 1 (set) 0 0 (reset) 1 Q (latch)*

Set
Q=1,Q=0

Reset
SR=10
Q=0,Q=1

* Latch = No change

SR=01
SR=00

SR=10

X
Q=Q

SR=00

State diagram (Moore)


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Inhibited
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SR latch timing diagram


NOR SR Latch

S, R active High
S 0 0 1 1 R 0 1 0 1 Q (next) Q (latch)* 0 (reset) 1 (set) Q=Q=0 (Inhibited)

(Illegal)

Q = S + RQ
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Dr. Le Dung

Gated SR Latch
E
Gated SR latch

S x 0 0 1 1

R x

Q (next) Q (hold)*

0 1 1 1

0 Q (latch) 1 0 (reset) 0 1 (set) 1


Inhibited

E,S,R active High

ESR=110 0xx, 110

* Hold = No action Reset


Q=0,Q=1

Set
Q=1,Q=0

ESR=101

0xx, 101

111

State diagram (Moore)


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X
Q=Q

111

Inhibited
9 Hanoi University of Science and Technology

D Latch
Data or Delay latch = transparent latch
ED=11 0x, 11

E 0 1 1

D x 0 1

Q (next) Q (hold)* 0 (reset=store 0) 1 (set=store 1)

Set
Q=1,Q=0

Reset
ED=10
Q=0,Q=1

0x, 10

Store 1

Store 0

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Some applications of the latches (1)


(App 1) Debounce a mechanical switch

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Some applications of the latches (2)


(App 2) LED detect alarm system

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Some applications of the latches (3)


(App 3) 74LS75 Quad D latch module with enable

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Flip-Flops
Clock signals Clocked flip-flops + Master-Slave Flip-Flop (Pulse-triggered FF) + Edge-triggered Flip-Flop SR Flip-Flop JK Flip-Flop D Flip-Flop T Flip-Flop Asynchronous set and reset (Preset and Clear) Some applications of the flip-flops(1) (2) (3)
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Clock signals

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Clocked Flip-Flops

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Master-Slave Flip-Flops

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Edge-triggered Flip-Flops

PGT detector

NGT detector

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SR Flip-Flop (active with PGT)

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SR Flip-Flop (active with NGT)

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JK Flip-Flop

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JK Flip-Flop (active with PGT)

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JK Flip-Flop (active with NGT)

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Internal Circuitry of JK Flip-Flop


Feedback

Feedback

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Pulse-triggered JK Flip-Flop

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D Flip-Flop

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Make D Flip-Flop from JK Flip-Flop

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T Flip-Flop (active with NGT)

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Clocked T Flip-Flop

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Asynchronous set and reset (1)

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Asynchronous set and reset (2)


JK-FF with Preset and Clear inputs

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Asynchronous set and reset (3)

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Asynchronous set and reset (4)


T-FF with Preset and Clear inputs

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Applications of the Flip-Flop


+ Thit k cc b m (Counter) + Thit k thanh ghi dch (Shift register) + Thit k mch dy + Cc ng dng khc

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Some applications of the Flip-Flop (1)


3 bits Up-Counter

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Some applications of the Flip-Flop (2)


Serial shift register

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