Lecture 0

VLSI Design
Introduction to the subject
Rajesh Ghongade VIIT

• Teaching Scheme
– Lectures: 3 Hrs/week – Practical: 2 Hrs/Week

• Examination Scheme
– Paper: 100 Marks – Practical: 50 Marks – Oral: 25 Marks

Unit-I
VHDL Modeling and Design Flow Introduction to VLSI: complete VLSI design flow (with reference to an EDA tool). Sequential, Data flow, and Structural Modeling. Functions. Procedures, attributes. Test benches, Synthesizable, and non synthesizable statements; packages and configurations Modeling in VHDL with examples of circuits such as counters, shift registers, bidirectional bus, etc.

Unit 2
FSM And Sequential Logic Principles Sequential Circuits, Meta-stability Synchronization, Design of Finite State Machines, and State minimization, FSM CASE STUDIES - Traffic Light control. Lift Control and UART STA and DTA

Unit 3
Programmable Logic Devices Introduction to the CPLDs, Study of architecture of CPLD. and Study of the Architecture of FPGA

Unit 4
System On Chip One, two phase clock, Clock distribution. Power distribution. Power optimization, SRC and DRC, Design validation, Global routing, Switch box routing. Off chip connections, I/O Architectures, Wire parasitics, EMI immune design. Study of memory-Basics of memory includes types of memory cells and memory architectures. Types of memory, based on architecture specific and application specific viz. SRAM, DRAM, SDRAM, FLASH, FIFO.

Unit 5
CMOS VLSI CMOS parasitics, equivalent circuit, body effect, Technology Scaling, A. parameter. Detail study of Inverter Characteristics, power dissipation, power delay product, CMOS combinational logic design and W/L calculations. Transmission gates, Introduction to CMOS layout.

Unit 6
Testability Need of Design for testability, Introduction to Fault Coverage, Testability. Design- forTestability, Controllability and Observability, Stuck-at Fault Model. Stuck-Open and Stuck-Short faults. Boundary Scan check. JTAG technology; TAP Controller and TAP Controller State Diagram. Scan path. Full and Partial scan. BIST

Text Books
1. John F. Wakerly, "Digital Design, Principles and Practices", Prentice Hall Publication 2. Neil H. E Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design". 3. Wayne Wolf, "Modern VLSI Design" 4. Sudhkar Yalamachalli, "Introductory VHDL from simulation to Synthesis"

Xilinx Data Manual "The Programmable Logic Data Book". 8. Stephen Brown and Zvonko Vranesic. 2005. Michael John Sebastian Smith. Prentice Hall. McGraw hill. Second Edition. "Application-Specific Integrated Circuits". "FPGA-Based System Design". 3. Miron Abramovici. 4.Reference Books 1. 2. Perry "VHDL" Charles Roth. Addison Wesley. McGraw-Hill. . Sung-Mo (Steve) kang. 5. 6. Tata McGraw-Hill Publication. " CMOS Digital Integrated Circuit". Yusuf Leblebici. Wayne Wolf. Jaico Publishing. "Fundamentals of Digital Logic with VHDL Design". 7. "Digital Systems Testing and Testable Design". "Digital System Design using VHDL".

and Implementation of: 1. Anyone of the three. Bi-directional buffer 8. Lift Controller /Traffic Light Controller/ UART. Ramp waveform generator using DAC 7. 2:4 Decoder. Displaying on 7-Segment display and threshold setting using keyboard 9. 8: 1 Multiplexer. Flip Flop. Comparator and Adder. Implementation of RAM/FIFO. Implementation of 4-bit RISC processor . Parity generator and Checker. Temperature sensing using ADC. 4. Synthesis. Shift Register and Counter 3. 6. 5.LIST OF EXPERIMENTS Any 8 assignments out of the following: Simulation. 2.

X – Implementation .2 – Synthesis • Xilinx Webpack 8.EDA Tools • Active-HDL 6.3 sp1 – (VHDL compiling and simulation) • Synpilfy Pro 8.

0 – Simulation • Synpilfy 8.Alternate EDA Tools • Libero Gold 6.2 – Synthesis .2 – (VHDL compiling & implementation) • Modelsim 6.

Hardware available • • • • Actel ProASIC PLUS evaluation board with APA300-PQ208 device Xilinx CPLD Dedicated Trainer XC 9572 PC 84 Xilinx FPGA Dedicated Trainer XC 2S50 – TQ 144(Spartan II) Universal Trainer kit (BASE UNIT) (ADD on Modules) – Xilinx CPLD Module • XC 95108 – PLCC 84 – Xilinx FPGA Module • XC V100E – PQ 240 XC (Virtex) – Altera Flex 10K Series FPGA – Atmel CPLD Device ATF 150 4AS / ATF 1508 AS PC 84 – Cypress CPLD Module Device CY37064V PC84 .

B.Ghongade .Lecture 1 Introduction to VLSI R.

science and technology of designing and fabricating integrated circuits with small-dimension electronic devices Areas of Microelectronics are : • • • • • • • VLSI Design VLSI CAD Tools Technology & Fabrication Physics Modeling and Simulation Characterization Testing Nearly all the advances in the modern day electronic systems and devices are a direct outcome of VLSI technology .Microelectronics Is the art.

• Die is an individual circuit or subsystem that is one of several identical chips that are produced after dicing up a wafer. • Wafer is a thin slice of semiconductor material on which semiconductor devices are made.Some keywords! • Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit. • Integrated circuit is a collection of one or more gates fabricated on a single silicon chip. • Chip is a small piece of semiconductor material upon which miniaturized electronic circuits can be built. people will think that you are an expert VLSI engineer!!! . If you use these key-words often. Also called a slice or substrate.

GAL Technology SSI MSI LSI VLSI Number of gates/transistors* per chip 1 to 20 100 to 1000 1000 to 10.000.000 * Examples 74XX series. the Medium Scale Integration.• The origin of this terminology can be traced as the logical extension to the integration techniques namely the Small Scale Integration.000* 10.000 to 100. flip-flops). advanced μC. MSI (multiplexers. 4xxx series 74XXX series.000/1. CPLD. PAL.000/100 to 100. SoC Year 60’s 70’s 80’s 90’s Dividing line between LSI and VLSI is somewhat fuzzy hence number of transistors provides a good criterion . SSI (the ICs which functioned as logic gates. 45XX series 8085. small memories. decoders).. FPGA. the Large Scale Integration LSI (early microprocessors.

co-founder of Intel. In fact the doubling period has shortened to a mere 12 months! .The advances in the integration techniques can be attributed directly to : •Advances in photolithography techniques •New designs of semiconductor devices •Newer methods of metallization The development of integration technology has followed the famous Moore’s Law. that “the number of transistors per chip would grow exponentially (double every 18 months)”. in the year 1965. It was stated by Gordon Moore.

Increasing transistor density .

The important factors that fuel the research in VLSI technology can be summarized as below: • • • • • • • • Increased functionality Higher reliability Small footprint Very low power consumption Increased speed of operation Re-programmability( except ASIC devices) Mass production Low cost .The number of transistors/gates that can fit in to the semiconductor die dictates the complexity of the functionality that the device can perform.

digital and mixed signal electronics. The current trend is to reduce the entire system design to a single chip solution called as system on chip (SoC) .VLSI is thus a technology that can be harnessed for various applications covering analog.

..Video circuits MPEG engine Power Management converter regulator on-chip power supply Applications multimedia computing communications biomedical ..Building blocks of VLSI system on chip Digital MCU/MPU Memory MEMS CCD sensors microtransformers microresonators RF/Analog Frequency generation mixers filters VCO LNA RF power amplifiers Opamps Mixed-Signal DSP Audio .

VLSI Design Process VLSI technology thus provides a platform for developing systems for various applications The integrated circuits so developed can be further classified as : .

ASIC • An Application Specific Integrated Circuit (ASIC) is a semiconductor device designed especially for a particular customer (versus a Standard Product. which is designed for general use by any customer) • The three major categories of ASIC Technology are : – Gate Array-Based – Standard Cell-Based – Full custom .

Gate Arrays • There are two types of gate arrays: – a channeled gate array – channel-less gate array • A channeled gate-array is manufactured with single or double rows of basic cells across the silicon • A basic cell consists of a number of transistors • The channels between the rows of cells are used for interconnecting the basic cells during the final customization process • A channel-less gate array is manufactured with a “sea” of basic cells across the silicon and there are no dedicated channels for interconnection • Gate arrays contain from a few thousand equivalent gates to hundreds of thousand of equivalent gates • Due to the limited routing space on channeled gate arrays. typically only 70% to 90% of the total number of available gates can be used .

• The library of cells provided by a gate array vendor will contain: – – – – primitive logic gates registers. specifying the width of a particular counter . hard-macros soft-macros Hard-macros and soft-macros are usually of MSI and LSI complexity. comparators and counters. for example. Hard macros are defined by the manufacturer in terms of cell primitives Soft-macros are characterized by the designer. such as multiplexers.

soft-macro libraries contain RAM functions that cannot be implemented efficiently in gate array devices. ALUs and microprocessors. • Additionally. ROM functions are more efficiently implemented in cell primitives .Standard Cell • Standard cell devices do not have the concept of a basic cell and no components are prefabricated on the silicon chip • The manufacturer creates custom masks for every stage of the device’s process which leads to a more efficient utilization of silicon as compared to gate arrays • Manufacturers supply hard-macro and soft-macro libraries containing elements of LSI and VLSI complexity. such as controllers.

The Characteristics of ASICs The remarks that follow further discuss some trade-offs of ASICs with respect to the following categories: • • • • • • • Complexity Silicon Efficiency Design Risks Prototype Turnaround NRE CAD / CAE Support Performance .

are capable of realizing functions that represent actual system building blocks and incorporate system memory functions on the same die The Array-Based memories do tend to be about 5 times less dense than Cell-Based memories because they are constructed out of the gates on the master slice. plus the associated interconnect capability Current Array-Based and Cell-Based chips accommodate as many as 20.Complexity • • • Complexity here means the number of transistors (or the amount of logic and/or memory) per given amount of area.000 usable logic gates on a single die Array-Based designs -especially in a Channel-Free Array technology . And full custom memories would provide much higher densities than do Array-Based memories But in fact many designers who are using the Array-Based technologies to get fast turn around tend to be using very small “scratch pad” or “cache” types of memories which fit very well into the ASIC concept • • .000.

• Cell-Based designs allow you to get more logic onto a chip in a given area. rather than on absolute highest density. Thus CellBased designs use silicon more efficiently than Array-Based designs .Silicon Efficiency • Array-Based technologies focus on fast implementation of logic integration onto a single chip. • Cell-Based designs feature transistors and routing tracks whose gradations of size are finer than those in Array-Based products.

– the technology chosen (# of masks required) – the amount of work to be done by the customer and by the silicon vendor – the need for special cells or procedures – the type of package required – the schedule the number of layers of metal –… .NRE • NRE (“Non-Recurring Engineering”) charges are the costs associated with developing an ASIC • NRE is based on a number of factors like: – the complexity of the design.

the higher will be the NRE .• The more work the silicon vendor does and the more special the requirements. the lower the NRE ! • Array-Based designs require the fewest number of design-specific masks and therefore offer the lowest NRE to prototypes. The more work the customer does. • Cell.Based designs require all masks to be generated for the chosen process and therefore the NRE charge will be higher for a Cell-Based design than for an Array-Based design .

Design Risks • The penalty for discovering a design error is higher for a Cell-Based ASIC than for an Array-Based ASIC • Mistakes after prototype fabrication in Array-Based designs usually only require that the metal mask layers be redone. On the other hand. design changes for a CellBased design may require that all masks be redone ! .

Prototype Turnaround Time (TAT) • Designs that require a complete mask set (CellBased) will always require more time to manufacture than designs which use a basic set of diffusion masks and only require customization at the metal layers (Array-Based) • This difference in time could be anywhere from one week to 4 weeks depending on how fast the silicon vendor can get masks from the mask shop and depending on how long the FAB cycle is for a given process .

CAD / CAE Support The use of EDA tools ensure: • Clean documentation • Reusable data • Functional verification • Easy modification • Automated rule check • Back-annotation (synchronization between schematic and layout) • Bill of material .

CMOS high power can cause accelerated junction temperatures which can slow down speed • One way to reduce the power and still maintain speed is to develop circuits such as differential pairs that do not switch from voltage rail to voltage rail . but the increased power requires larger power supplies and tends to heat up the junctions on silicon chips which slows the devices. • In today's most dominant ASIC technology .Performance • The two most critical parameters that have been used to measure the worth of new technologies have been speed and power • High power circuits are normally fast.

SYSTEM REQUIREMENTS ASIC Design Flow ARCHITECTURE DEFINITION AND LOGIC DESIGN LOGIC DIAGRAM/DESCRIPTION TECHNOLOGY DESIGN RULES DEVICE MODELS VLSI DESIGN AND LAYOUT DESIGN VERIFICATION FAIL DESIGN RULE CHECK SIMULATION (SPICE) PASS MASK GENERATION SILICON PROCESSING WAFER TESTING. RELIABILITY QUALIFICATION . PACKAGING.

INITIAL DESIGN REVIEW DESIGN LANDMARKS FRONT-END TOOLS ASIC Design Flow (detailed) FLOORPLANNING DESIGN ENTRY TEST& VERIFICATION TOOLS LAYOUT & PHYSICAL VERIFICATION TOOLS SIMULATION & POWER ANALYSIS LOGIC & TEST SYNTHESIS CLOCK PLANNING/ CLOCK TREE SYNTHESIS STATIC TIMING ANALYSIS GATE-LEVEL SIMULATION FORMAL VERIFICATION TEST STRUCTURE VERIFICATION POWER ESTIMATION PRE-LAYOUT TECHNOLOGY CHECKS TIMING ASSERTIO NS RELEASE TO LAYOUT TIMING DRIVEN LAYOUT/OPTIMIZATION STATIC TIMING ANALYSIS POST LAYOUT TECHNOLOGY CHECKS AUTOMATIC TEST-PATTERN GENERATION RELEASE TO MANUFACTURING .

Most of these devices use technology that also allows the function to be reprogrammed .Programmable logic device (PLD) • It is an integrated circuit able to implement combinational and/or sequential digital functions defined by the designer and programmed into this circuit • There are a wide variety of ICs that can have their logic function “programmed” into them after they are manufactured.

• Historically. IC manufacturers devised complex PLD (CPLD) architectures to achieve the required scale . Instead. a designer could accommodate any logic function up to a certain level of complexity using the well-known theory of logic synthesis and minimization • PLA structure was enhanced and PLA costs were reduced with the introduction of programmable array logic (PAL) devices • Today. programmable logic arrays (PLAs) were the first programmable logic devices • PLAs contained a two-level structure of AND and OR gates with user-programmable connections • Using this structure. such devices are generically called programmable logic devices (PLDs). the basic two-level AND-OR structure of PLDs could not be scaled to larger sizes. and are the “MSI” of the programmable logic industry • The ever-increasing capacity of integrated circuits created an opportunity for IC manufacturers to design larger PLDs for larger digital-design applications • However.

all on the same chip. • Compared to a CPLD. a field-programmable gate arrays (FPGA) contains a much larger number of smaller individual logic blocks. other IC manufacturers took a different approach to scaling the size of programmable logic chips. distributed interconnection structure that dominates the entire chip . In addition to the individual PLDs. and provides a large. providing a rich variety of design possibilities • CPLDs can be scaled to larger sizes by increasing the number of individual PLDs and the richness of the interconnection structure on the CPLD chip • At about the same time that CPLDs were being invented. the on-chip interconnection structure is also programmable.• A typical CPLD is merely a collection of multiple PLDs and an interconnection structure.

CPLD and FPGA .

. consider abstractly or theoretically.Top-Down design methodology • Means describing a complete system at an abstract level using hardware description language(HDL) and the use of EDA tools like partitioners and synthesizers • More time is spent on designing HDL models. considering different architectures and considering system test & testability issues. Practically no time is spent on designing at gate level ABSTRACT To consider a concept without thinking of a specific example.

Levels of behavioural abstraction INCREASING DETAILED REALIZATION & COMPLEXITY INCREASING BEHAVIOURAL ABSTRACTION SYSTEM CONCEPT ALGORITHM The process of formulating general concepts by abstracting common properties of instances RTL / DATAFLOW GATE TRANSISTOR / SWITCH .

This level completely ignores the hardware structure. The designer is aware of how data flows between hardware registers and how the data is processed in the design. However HDLs are not useful at this stage. Transistor (also called Switch) Level: This is the lowest level of abstraction. storage nodes. RTL (Register Transfer Level) (also called dataflow): At this level the module is designed by specifying the data flow between the registers. Algorithmic (also called behavioural) level: This is the highest level of abstraction provided by most HDLs. Design at this level is very similar to a conventional high level language programming like C. Gate Level: The module is implemented in terms of logic gates and interconnections between these gates. .• • • • • System Level: All the specifications (input and output) are described at this level. Design at this level requires knowledge of switch-level implementation details. A module can be implemented in terms of the desired deign algorithm without the concern of the hardware implementation details. Design at this level is similar to describing a design in terms of gate-level logic diagram. and the interconnections between them. It simply treats the design like a black box. A module can be implemented in terms of switches.

B.Lecture 2 Introduction to VHDL R.Ghongade .

PLD based design flow •A decision has to be arrived at regarding the selection of the type of a PLD since we have two options the CPLD and the FPGA •The selected device is then called the target device Steps involved: • • • • • • • • • Specifications Design Entry Compilation Functional Simulation/Verification Synthesis Post-synthesis simulation Implementation Timing Simulation Hardware Implementation .

SPECIFICATIONS HDL based design flow (STEP 1) CREATE A DIGITAL DESIGN BY VHDL CODE SCHEMATIC ENTRY STATE DIAGRAM (RTL Level) (STEP 2) COMPILATI ON Active-HDL Xilinx ISE Libero IDE FPGA Advantage Lattice ISP LEVER Netlist (Gate Level) (STEP 3) FUNCTIONAL SIMULATION Active-HDL Modelsim Xilinx XST Synplify Leonardo Spectrum Optimized Netli st (Gate Level) (STEP 4) (SPECIFY TARGET DEVICE) SYNTHESIS (STEP 5) SI MULATION (POST SYNTHESIS) Active-HDL Modelsim (STEP 6) IMPLEMENTATION PLACE & ROUTE Palace (STEP 7) SI MULATION (TIMING ASPECTS) Active-HDL Modelsim Xilinx IMPACT Actel Flash Pro (STEP 8) HARDWARE IMPLEMENTATION .

.DSL.) Structural VHDL (VITAL primitives) Target Device Library Synthesis (Synthesizer Tool) Post.. HEX..XNF..Simulation (VHDL Simulator) SDF (Delay Information) Device Programming JTAG-ISP VITAL Primitive Library Netlist (EDIF.Detailed HDL based design flow NETLIST Idea Placement & Routing (Device Vendor's Tool) Algorithmic Simulation (VHDL) Design Entry (Text Editor) Design Entry (Schematic) Back-annotation VHDL Template Model Generator Functional Simulation (VHDL Simulator) Test Vectors (Input Stimuli & Output Expected) Program Data (Fuse Map: JED.) TO PLACE & ROUTE Timing Analysis Chip .

Specifications • • • • It may again include the input. output and ambient specifications Target device may be finalized Choice of target device as CPLD or FPGA depends on various factors Specific type of device may be selected by comparing the specifications provided by the manufacturer in the datasheet and the actual design requirements • XILINX • LATTICE • LUCENT • ALTERA • ACTEL • CYPRESS • AT&T • AMD 5 15 5 31 Xilinx Actel Cypress Altera Lattice 11 6 3 24 AMD AT&T Others .

Design Entry • This is essentially the design entry point in an EDA tool • It can be done by the following means: • Block Diagram/Schematic capture • State Diagram entry • HDL code entry .

input.Block Diagram/Schematic capture • A schematic circuit is literally “drawn” in an appropriate graphical editor • The EDA tool associated with this task is called Schematic Capture Tool • An electrical rule check (ERC) is usually run • The main job of the ERC tool is to check for incorrect electrical connections for example if a VCC pin of an IC is accidentally shorted to ground. then the ERC tool will point out such a discrepancy • For this tool to be effective the IC pins have to be earlier declared as power. bidirectional etc. output. a set of components connected together • It is also possible to generate VHDL netlist .e. ground. • After removing the ERC errors a netlist is generated by the editor • A netlist is a text file showing the nets i.

Block Diagram/Schematic capture .

State Diagram entry • Many designs are most effectively described /designed by state diagram approach. • This method is preferred since it is a fast way of creating the design . • Effective for sequential designs • The EDA tools provide a graphical interface so that the designer can directly make an entry of the state diagram and generate the netlist.

State Diagram entry .

HDL code entry • • • • • A designer can enter his /her design using a hardware description language (HDL) The HDLs prominent in the industry are “VHDL” and “Verilog” There is another language that is recently making ground called as “System C” Being similar to C language gives it an advantage to be more user friendly and comfortable to designers familiar with C Using the code entry method is the most preferred one since it offers: – – – – Design flexibility Code re-use Easy modification Tighter control over resources • A netlist is again created by compiling the HDL code .

HDL code entry .

Compilation • At this stage the design is said to be at the Register Transfer Level (RTL) • All the data manipulation is done here at the register of the host CPU or we can say that the design is not in terms of the logic gates but “internal” to the environment • After successful compilation of the design using any one of the three methods a netlist is generated which is called the gate-level netlist • The design now is translated in terms of the logic gates and modular entities like multiplexers. Thus we now have the design at Gate-level . decoders.

Functional Simulation/Verification • There are two very different tasks in digital system development – Verification is the process of determining whether a design meets the specification and performance goals – It concerns the correctness of the initial design as well as the refinement processes – Testing is the process of detecting the physical defects of a die or a package that occurred during manufacturing .

Functional verification can thus be compared to the algorithm testing in conventional programming languages . There are two ways of functional verification: – Interactive mode • In the interactive mode the designer can change the input signals and observe the corresponding output behaviour of the design. This mode is attractive for larger designs. • • If any undesirable behaviour is observed. This method is becomes cumbersome for designs involving large number of inputs and outputs. – Batch mode • Batch mode uses the concept of test-benches (also a piece of VHDL code) that generates test patterns and checks the validity of the output.Functional Simulation/Verification • A functional test is done by simulating the gate-level design using logic simulators that may be available as a built-in feature of the EDA tool. the designer can correct the flaw by going back to the design entry level It is important here to note that none of the timing aspects have been considered during this simulation.

the synthesis tool can break down the four.Synthesis • Synthesis means to properly put together so as to make the whole complex design • At this stage it is necessary to specify the target device.input AND gate into two two-input AND gates and map correspondingly • Optimization is very important otherwise the design may get “blown-up” and the target device may prove too small for the design • Synthesis tools have built-in proprietary algorithms for optimization . since the synthesis tool (again dedicated software) requires knowing the resources available with the target device • Synthesis optimally maps the design functionality (at the gate-level) in to the actual devices available with the target device • For example if the design uses a four.input AND gate but since this is not available with the target device.

Post-synthesis simulation • After synthesis the design needs to be rechecked to confirm its functionality • Simulation at this level ensures that the mapped design behaves correctly as desired • A possibility may exist wherein. the synthesis tool may incorrectly recompose the design while mapping • Again timing parameters are ignored here .

– Place and route • Place and route is the phase where the tool completes the task of virtually placing the components of the design in to the target device and then wiring the individual modules to complete the design. . • Though it is a physical placement. Proprietary software tools are available for this task and may be quite costly. This phase is however optional. • Again this process may have two phases: – Physical synthesis • Physical synthesis means optimal relocation of the design into the target device. it still takes place in the virtual environment provided by the EDA tool • A physical map of the target device is loaded into the environment and the components are virtually fitted into the target device.Implementation • This is the process of physical placing of the design into the target device.

even though they appear to be functionally perfect! • Hence a simulation is necessary again to test the timing behaviour of the design. • Many synchronous circuits will fail if the timing aspects are ignored. • In fact the real-world behaviour of the device can be very accurately studied by the simulation with timing aspects . • The modules in the design now may be physically placed apart from each other.Timing Simulation • One most important change the design undergoes is after the implementation. • This factor introduces the delay aspect in the signal propagation. • This provides the designer with a better view of the design functionality.

Hardware Implementation • The final step in design is to “download” the functionality into the actual hardware i. the target device • The synthesis tool generates the output in terms of “bit-stream” that is used to configure the target device • Vendor specific tools can be used for downloading the bit-stream into the physical device .e.

• Hardware structure modeling – Hardware structure is capable of being modeled in a hardware description language irrespective of the design’s behaviour.HDL • • A hardware description language (HDL) is a software coding language used to model the intended operation of a piece of hardware There are two aspects to the description of hardware that an HDL facilitates: – true abstract behaviour modeling – hardware structure modeling • Abstract behaviour modeling – A hardware description language is declarative in order to facilitate the abstract description of hardware behaviour for specification purpose. This behaviour is not influenced by structural or design aspects of the hardware intent. .

VHDL • What is VHDL? – Digital system design using Hardware Description Language is an established methodology in EDA – VHDL stands for “VERY HIGH SPEED INTEGRATED CIRCUITS HARDWARE DESCRIPTION LANUAGE” EDA stands for “ELECTRONIC DESIGN AUTOMATION” .

FEATURES • VHDL is an amalgamation of following languages – Concurrent language – Sequential Language – Timing Specification – Simulation Language – Test Language .

• VHDL has got powerful language constructs – {if…else}. {with…select} etc • Design hierarchies to create modular designs • Supports Design Libraries • Facilitates device independent design and portability .

A B + X + C Z . X <= A + B .Concurrent Language • Concurrent statements execute at the same time in parallel as in hardware Z <= C + X .

X <= A + B. X <= A + B. ≠ Sequential statements are required to design sequential circuits .Sequential Language • Sequential statements execute one at a time in sequence • As the case with any conventional programming language the sequence of statements is important Z <= C + X . Z <= C + X .

end process . wait for 20 ns . clk <= ‘1’ . wait for 12 ns .Timing Specification • Providing timing attributes in a sequential digital design is of prime importance since the operations are synchronized to a common clock • Example: process begin clk <= ‘0’ . 0 20 32 52 64 84 ns Timing can be specified in a process only .

layout simulation • Any HDL should thus be equipped with simulation capability for verification and troubleshooting purposes .Simulation language • For analyzing a digital design it is important the design be simulated • Simulation has different flavours – Functional simulation – Post-synthesis simulation – Post.

Test Language • Testbench – It is a part of a VHDL module that generates a set of test vectors (test inputs) and sends them to the module being tested – It collects the responses generated by the module under test and compares them against a specification of correct results – Thus testbench is required to ensure that the design is correct and that the module is operating as desired Equivalent to checking of logical errors in any conventional programming language .

vhd Equivalent to mechanical test jigs used for testing functionality of mass produced pcbs as in TV sets or motherboards .vhd MODULE UNDER TEST ABC.Testbench use Test tst_a tst_b tst_c ABC_testbench.

half adder and OR gate A B Cin HALF ADDER HALF ADDER SUM OR CARRY Design hierarchy simplifies the design procedure and manageability in case of complex designs .Design Hierarchy • Hierarchy can be represented using VHDL • Example – A full adder which is the top level module being composed of three lower level modules that are.

Design Libraries • Design Unit – It is any block of VHDL code or collection of VHDL codes that may be independently analyzed and inserted into a design library • Design Library – It is a storage facility in which analysed VHDL descriptions are stored for repeated uses DESIGN UNIT 1 4 2 Analyze Design Library 3 5 Simulator .

‘Z’ • Example – Consider the truth-table for AND gate A 0 0 1 1 0 B 0 1 0 1 Z Y 0 0 0 1 ? HOW TO RESOLVE THIS CONDITION ? . ‘1’.e.Logic systems • Need for multi-valued logic system – Conventional logic systems have only three values i. ‘0’.

• For this problem a 9-valued logic system or package was developed that is called “STD_LOGIC_1164” and it is accepted as IEEE STD 1164-1993 • Multi-valued logic – Unknown: value was known but not anymore – Un-initialized: value was never known – High impedance: net has no driver – Drive strengths: handle different output drivers – Don’t care: value is immaterial .

Levels of abstraction • Different styles are adopted for writing VHDL code • Abstraction defines how much detail about the design is specified in a particular description • Four levels are: – – – – Layout level Logic level Register Transfer level Behavioral level BEHAVIORAL RTL LOGIC LAYOUT .

Layout Level • This is the lowest level and describes the CMOS layout level design on silicon .

Logic Level • Design has information about – Function – Architecture – Technology – Detailed timings • Layout information and analog effects are ignored .

Register Transfer Level • Using HDL every register in the design and the logic in between is defined • Design contains: – Architecture information – No details of technology – No specification of absolute timing delays .

Behavioral Level • Describing function of a design using HDL without specifying the architecture of registers • Contains timing information required to represent a function .

Basic building blocks of VHDL code • A VHDL design is composed of following blocks: – Library declarations – Entity – Architecture – Configuration .

Basic VHDL code LIBRARY DECLARATIONS ENTITY BASIC VHDL CODE ARCHITECTURE CONFIGURATION .

Library Package Detailed anatomy of VHDL code Functions Procedures Types Constants Components Generics Entity Ports Architecture (Style I) DATAFLOW Architecture (Style II) BEHAVIOURAL Architecture (Style III) STRUCTURAL Concurrent Statements Concurrent Statements Process Sequential Statements .

Lecture 3 Elements of VHDL R.Ghongade .B.

Basic building blocks LIBRARY DECLARATIONS ENTITY BASIC VHDL CODE ARCHITECTURE CONFIGURATION .

Overview .

Library • It is a collection of compiled VHDL units • It enables sharing of compiled designs and hides the source code from the users • Commonly used functions. procedures and user data types can be compiled into a user defined library for use with all designs • Library should be declared before each entity declaration even if it is in the same VHDL file .

Library • To declare a library (i.e. to make it visible to the design) two lines of code are needed . the other a use clause • A library structure can be as follows: LIBRARY PACKAGE FUNCTIONS PROCEDURES TYPES CONSTANTS COMPONENTS . one containing name of the library.

.indicates a comment USE work.all .all .end of statement or -. -.double dash (--) -.semicolon indicates USE IEEE.Library syntax LIBRARY library_name .package_parts . USE library_name.std_logic_1164. Example LIBRARY IEEE . -.package_name. -.declaration LIBRARY work .

This package defines numeric types and arithmetic functions for use with synthesis tools.SIGNED: represents a SIGNED number in vector form The base element type is type BIT.MATH_COMPLEX.all IEEE. This package defines a standard for designers to use in describing VHDL models that make use of common REAL constants and common REAL elementary mathematical functions. IEEE.Library details IEEE.all This package defines a standard for designers to use in describing VHDL models that make use of common COMPLEX constants and common COMPLEX mathematical functions and operators. Two numeric types are defined: -.NUMERIC_BIT.MATH_REAL.UNSIGNED: represents an UNSIGNED number in vector form -.all .

UNSIGNED: represents UNSIGNED number in vector form -. This package defines a standard for designers to use in describing the interconnection data types used in VHDL modeling.STD_LOGIC_ARITH. and STD_LOGIC_VECTOR. conversion.alll This package defines numeric types and arithmetic functions for use with synthesis tools. Defines multi-value logic types and related functions.NUMERIC_STD. INTEGER. UNSIGNED. STD_LOGIC.all .Library details IEEE. This package defines a set of arithmetic. IEEE. SMALL_INT.The base element type is type STD_LOGIC. STD_ULOGIC.all IEEE.STD_LOGIC_1164. and comparison functions for SIGNED.SIGNED: represents a SIGNED number in vector form -. Two numeric types are defined: -.

and comparison functions for STD_LOGIC_VECTOR.alll This package defines supplemental types.all IEEE.STD_LOGIC_SIGNED.all This package defines a set of unsigned arithmetic. IEEE.STD_LOGIC_TEXTIO.Library details IEEE. subtypes. This package defines a set of signed arithmetic.STD_LOGIC_UNSIGNED. This package overloads the standard TEXTIO procedures READ and WRITE. . and functions for the Std_logic_1164 Package. conversion and comparison functions for STD_LOGIC_VECTOR.STD_LOGIC_MISC.all IEEE. conversion. constants.

Entity – It is the design’s interface to the external circuitry – Equivalent to pinout /package of an IC – VHDL design must include one and only one entity per module – It can be used as a component in other entities after being compiled into a library .

Entity declaration • Defines the input and output ports of the design • Name of the entity can be anything other than the reserved VHDL word • Each port in the port list must be allotted: – a name ( should be self-explanatory that provides information about its function – data flow direction or mode – a type • Ports should be well documented with comments at the end of line providing additional information about the signal .

Entity syntax entity entity_name is port ( port_name : signal_mode signal_type . . port_name : signal_mode signal_type ) . port_name : signal_mode signal_type . end entity_name .

Modes • Ports in the portlist have modes which indicate the driver direction • Mode also indicates whether or not the port can be read from within the entity • Four modes are available: – Mode IN – Mode OUT – Mode INOUT – Mode BUFFER .

Drivers reside outside the entity ENTITY .• Mode IN Value can be read from but not assigned to (by the entity) Port signal A port ( A : in std_logic ) .

• Mode OUT Value can be assigned to but not read from (by the entity) port ( B : out std_logic ) . Port signal B Drivers reside inside the entity ENTITY .

Drivers reside both inside and outside the entity ENTITY . value can be assigned to as well as read from (by the entity) Port signal C port ( C : inout std_logic ) .• Mode INOUT Bi-directional .

• Mode BUFFER Output port with internal read capability Drivers reside inside the entity Port signal D port ( D : buffer std_logic ) . ENTITY DO NOT USE UNLESS REQUIRED Signal can be read inside the entity .

1Y . 2Y . 3B. 1 2 3 4 5 6 7 1A 1B 1Y 2A 2B 2Y GND VCC 4B 4A 4Y 3B 3A 3Y 14 13 12 11 10 9 8 . 3A. 2B . 2A . 4B : in std_logic . 4Y : out std_logic ) . 3Y.Entity example entity and_gate is port ( 1A . 1B . 4A : in std_logic . end and_gate .

Equal : out std_logic ) . Mode : in std_logic . Result : out std_logic_vector ( 3 downto 0 ) . Cout : out std_logic .Entity example entity ALU is port ( In1 : in std_logic_vector ( 3 downto 0) . In1 Cout ALU Result Equal In2 Op sel Mode Cin . -. -. in std_logic_vector ( 3 downto 0) .opn select Cin : in std_logic .2nd operand Opsel : in std_logic_vector ( 3 downto 0) .1st operand In2 . end ALU . -.

concurrent statements only end achitecture_name . .Architecture It specifies • Behaviour • Function • Relationship between inputs and outputs of an entity Syntax architecture achitecture_name of entity_name is [declarations] -.optional begin code -.

• Architecture can contain only concurrent statements • A design can be described in an architecture using various levels of abstraction • An entity can have more than one architectures since a function can be implemented in a number of ways • There can be no architecture without an entity .

b ) if a=‘1’ and b=‘1’ then c <= ‘1’ . else c <=‘0’ .Architectural bodies • Behavioural – It is the high-level description – It contains a set of assignment statements to represent behaviour – No need to focus on the gate-level implementation of a design Example: architecture behave of and_gate is begin process ( a. . end if . end behave . end process .

. end dataflow .• Dataflow – It uses concurrent signal assignment statements Example: architecture dataflow of and_gate is begin c<= a and b .

• Structural – Components from libraries are connected together – Designs are hierarchical – each component can be individually simulated – it makes use of component instantiation Top level design Functional units A B Cin SUM HALF ADDER HALF ADDER OR CARRY .

using configuration statement we can bind a particular architecture to the entity Syntax configuration CONFIGURATION_NAME of ENTITY_NAME is for ARCHITECTURE_NAME end for.Configuration • Since a number of architectures can exist for an entity . . end CONFIGURATION_NAME.

Next class Language elements .

Language Elements I R.B.Ghongade Lecture 4 .

• VHDL is a strongly typed language – Designers have to declare the type before using it • VHDL is not case sensitive ( but avoid mixed cases as a good programming practice) • VHDL supports a wide variety of data types and operators – OBJECTS – OPERATORS – AGGREGATES .

Objects • They are used to represent and store the data in the design being described • Object contains a value of specific type Class Object Data type SIGNAL COUNT : INTEGER This results in an object called COUNT that holds INTEGER value that belongs to class SIGNAL • The name given to the object is called as identifier • Do not use reserved words as identifiers .

• Each object has a data type and class • Class indicates how the object is used in the module and what can be done with that object • Type indicates what type of data the object contains • Each object belongs to one of the following class: – CONSTANT – SIGNAL – VARIABLE CLASS – FILES CONSTANT SIGNAL VARIABLE FILES .

Data Types • In order to write VHDL code efficiently it is necessary to study the specification and use of data types • Following are the categories of data types: – – – – – – – Pre-defined User defined Subtypes Arrays Port arrays Records Signed and unsigned .

BOOLEAN. REAL STD_LOGIC. INTEGER. UNSIGNED / data conversion functions Functions that allow operations with STD_LOGIC_VECTOR .Pre-defined data types • Specified by IEEE 1076 and IEEE 1164 Package standard std_logic_1164 std_logic_arith std_logic_signed std_logic_unsigned Library Type/Functions std ieee ieee ieee ieee BIT. STD_ULOGIC SIGNED.

X is declared as a onedigit SIGNAL of type BIT Y is 4-bit vector.BIT (and BIT_VECTOR): 2 level logic (‘0’. leftmost bit is MSB W is 8-bit vector. ‘1’) Examples: SIGNAL X : BIT . . SIGNAL W : BIT_VECTOR (0 to 7). rightmost bit is MSB SIGNAL Y : BIT_VECTOR (3 downto 0).

• To assign a value to the signal use the operator “ < = ” • Assignment examples: X <= ‘1’ .bit SIGNAL whose value is “0111” . X is a single bit SIGNAL whose value is ‘1’ Note that single quotes are used for a single bit Y is a 4. Y <= “0111” . Note that double quotes are used for vectors W is an 8. W <= “01110001” . MSB is ‘1’ .bit SIGNAL whose value is “0111001” .

STD_LOGIC (and STD_LOGIC_VECTOR): 8 valued logic (introduced in IEEE 1164 standard) Symbol ‘X’ ‘0’ ‘1’ ‘Z’ ‘W’ ‘L’ ‘H’ ‘-’ Description Remark Forcing unknown Synthesizable unknown Synthesizable logic ‘0’ Forcing low Synthesizable logic ‘1’ Forcing high High impedance Synthesizable tri-state buffer Weak unknown Weak low Weak high Don’t care .

However ‘0’. X is declared as a one-digit (scalar) SIGNAL of type STD_LOGIC SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0).Examples: SIGNAL X : STD_LOGIC . Y is 4-bit vector. leftmost bit is MSB for (optional) SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0) : = “0001” initial value use “ := ” Most of std_logic levels are intended for simulation only. ‘1’ and ‘Z’ are synthesizable with no restrictions .

then conflicting logic levels are resolved by using the shown table X 0 1 Z WL H X X X X X X X X X 0 X 0 X 0 0 0 0 X 1 X X 1 1 1 1 1 X Z X 0 1 Z WL H Z WX 0 1 W WWWX L X 0 1 L WL WX H X 0 1 H WWH X X X X X X X X X •The STD_ULOGIC has 9 valued logic levels : additional value is ‘U’ for “Un-resolved or ”Un-initialized” .• With respect to “weak” values. If any two std_logic signals are connected to the same node. they are resolved in favour of the “forcing” values in multiple-driven nodes.

483. FALSE 32-bit integers (from . UNSIGNED TRUE.647 Non-negative numbers (from 0 to 2.483.647 Real numbers (from -1.147. but accept arithmetic operations which are typical of INTEGER data type .0E38) Used to inform physical quantities like . Useful for simulation but not synthesizable Single ASCII character or a string of such characters.483. time.147.2.647 to + 2.• Other types BOOLEAN INTEGER NATURAL REAL Physical literals Character literals SIGNED. voltage etc. Not synthesizable They have appearance of STD_LOGIC_VECTOR.0E-38 to +1.147.

TYPE student_grade IS RANGE 0 to 100 . .User defined data types • VHDL allows user defined data types • Two categories of this data type are: – Integer – Enumerated • User defined integer type TYPE my_integer IS RANGE -32 to +32 .

typically used in state machines • The encoding of enumerated types is done sequentially and automatically • Since here there are 4 states only two bits are required hence “00” is assigned to first state ( idle). “01” to second state (forward) and so on.• User defined enumerated type TYPE my_logic IS (‘0’. An enumerated type. . ‘1’. forward. TYPE my_state IS ( idle. ‘Z’ ). stop) . backward.

backward) .Subtypes • A SUBTYPE is a TYPE with a constraint • Though operations between data of different types are not allowed. This means that the subtype sub_state =(idle. forward. they are allowed between the subtype and its corresponding base type SUBTYPE sub_state IS my_state RANGE idle to backward .

2-dimensional or 1D X 1D • Higher dimensional arrays are possible but not synthesizable 0 Scalar 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 1D 1 1 0 1 0 1 0 0 1D x 1D 2D data array .Arrays • Arrays are collections of objects of same type • Can be 1-dimensional.

To use an array : SIGNAL signal_name : type_name [:= initial_value] .Array syntax To specify an array : TYPE type_name IS ARRAY (specification) OF data_type .

TYPE matrix IS ARRAY (3 downto 0 ) OF row . 1D x 1D SIGNAL . SIGNAL X : matrix .Example : 1D x 1D array – We want to build an array containing 4 vectors. each of size 8 bits – we will call each vector as row and the complete array as matrix TYPE row IS ARRAY (7 downto 0 ) OF STD_LOGIC .

7 DOWNTO 0 ) OF STD_LOGIC .Example : 2D array – This array will be created with scalars only TYPE matrix2D IS ARRAY (0 TO 3. L M ROWS L M COLUMNS .

which will then be visible to the whole design (thus including the ENTITY) . we might need to specify the ports as arrays of vectors. • Since TYPE declarations are not allowed in an ENTITY.Port Arrays • In the specification of the input or output pins (PORTS) of a circuit (which is made in the ENTITY). the solution is to declare user-defined data types in a PACKAGE.

std_logic_1164. ---------------------------PACKAGE my_data_types IS TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(7 DOWNTO 0).. .Main code: ------------------------LIBRARY ieee. END mux. ..user-defined package --------------------------ENTITY mux IS PORT (inp: IN VECTOR_ARRAY (0 TO 3).. -------------------------------------------------.Package: -------------------------LIBRARY ieee. -------------------------------------------- .------. USE ieee.all.all. USE ieee.. END my_data_types. .all. USE work. -.my_data_types.std_logic_1164. ).

was created.483. . which goes from 0 to +2.647) • The data type was saved in a PACKAGE called my_data_types.147. with the only restriction that it must fall within the NATURAL range. called vector_array. a userdefined data type. which can contain an indefinite number of vectors of size eight bits each (NATURAL RANGE <> signifies that the range is not fixed.• As can be seen in the example above. and later used in an ENTITY to specify a PORT called inp • Notice in the main code the inclusion of an additional USE clause to make the user-defined package my_data_types visible to the design.

TYPE birthday IS RECORD day: INTEGER RANGE 1 TO 31. with the only difference that they contain objects of different types. month: month_name. END RECORD. .Records • Records are similar to arrays.

Signed and Unsigned data types • These types are defined in the std_logic_arith package of the ieee library Examples: SIGNAL x: SIGNED (7 DOWNTO 0). SIGNAL y: UNSIGNED (0 TO 3). .

For example. the std_logic_arith package. of the ieee library. must be declared . while ‘‘1101’’ signifies 13. • To use SIGNED or UNSIGNED data types. • If type SIGNED is used instead. the value can be positive or negative (in two’s complement format). Therefore.‘‘0101’’ would represent the decimal 5. while ‘‘1101’’ would mean 3. ‘‘0101’’ represents the decimal 5.• An UNSIGNED value is a number never lower than zero.

Next class Language Elements II .

B.Language Elements II R.Ghongade Lecture 5 .

Operators • VHDL provides several kinds of predefined operators – – – – – – Assignment operators Logical operators Arithmetic operators Relational operators Shift operators Concatenation operators .

and constants. or GENERIC Used also for establishing initial values Used to assign values to individual vector elements or with OTHERS . CONSTANT. variables.Assignment operators • Are used to assign values to signals. <= := => Used to assign a value to a SIGNAL Used to assign a value to a VARIABLE.

-.LSB is '1'.are '0' . the others -. -. -. Then the following assignments are legal: x <= '1'. VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0). the others are '0' w <= (0 =>'1'. -.SIGNAL x : STD_LOGIC."0000" is assigned to VARIABLE y using --":=" w <= "10000000".'1' is assigned to SIGNAL x using "<=" y := "0000". OTHERS =>'0'). SIGNAL w: STD_LOGIC_VECTOR(0 TO 7).LSB is '1'.

Logical operators • Used to perform logical operations. STD_LOGIC STD_ULOGIC BIT_VECTOR STD_LOGIC_VECTOR STD_ULOGIC_VECTOR . • The data must be of type: – – – – – BIT.

b)' .(a.(a'.(a.b) y <= NOT (a AND b).b)' y <= a NAND b.• The logical operators are: – NOT – – – – – – AND OR NAND NOR XOR XNOR The NOT operator has precedence over the others Examples: y <= NOT a AND b. -. -. -.

or REAL (the last cannot be synthesized directly). • Also. if the std_logic_signed or the std_logic_unsigned package of the ieee library is used.Arithmetic operators • Used to perform arithmetic operations. then STD_LOGIC_VECTOR can also be employed directly in addition and subtraction operations . The data can be of type INTEGER. SIGNED. UNSIGNED.

+ * / ** MOD REM ABS ( Addition) (Subtraction) (Multiplication) (Division) (Exponentiation) ( Modulus) ( Remainder) ( Absolute value) For mod. there generally is little or no synthesis support •There are no synthesis restrictions regarding addition and subtraction. rem. only static values of base and exponent are accepted •Regarding the mod and rem operators. and the same is generally true for multiplication •For division. only power of two dividers (shift operation) are allowed •For exponentiation. while y rem x returns the remainder of y/x with the signal of y •Finally. y mod x returns the remainder of y/x with the signal of x. abs . abs returns the absolute value .

Comparison operators = /= < > <= >= Equal to Not equal to Less than Greater than Less than or equal to Greater than or equal to Also called RELATIONAL operators .

Shift operators sll srl sla sra ror rol shift left logical shift right logical shift left arithmetic shift right arithmetic rotate left logical rotate right logical • LOGICAL • ARITHMETIC • ROTATE LOGICAL SHIFTING 0 ARITHMETIC SHIFTING (retains sign bit) 0 ROTATE .

.c. & d(2) . .Concatenation operator & Concatenation • Operands can be one-dimensional array type or element type • “ &” works on vectors only Example: SIGNAL SIGNAL BEGIN b <= a <= . ‘0’ & c(1) c & d .d : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) . . a : STD_LOGIC_VECTOR ( 5 DOWNTO 0 ) . b.

plus SIGNED and UNSIGNED Arithmetic Comparison Shift Concatenation . STD_LOGIC_VECTOR.Operator summary Operator type Logical Operators NOT./. ) Data types BIT. STD_ULOGIC_VECTOR INTEGER. ( . XNOR +.*. abs) =. UNSIGNED All above BIT_VECTOR Same as for logical operators. . NOR. STD_ULOGIC. sla. >. srl. AND. <=. XOR. rol.** (mod. rem . <. sra. BIT_VECTOR. /=. -. >= sll. . ror &. STD_LOGIC. SIGNED. AND OR.

etc.. /. using the same name as the pre-defined ones . for example) • For instance.. *. • We can define our own operators. the pre-defined ‘‘+’’ operator does not allow addition between data of type BIT.).Operator overloading • Operators can be user-defined • Let us consider the pre-defined arithmetic operators seen earlier (+. They specify arithmetic operations between data of certain types (INTEGER.

• For example, we could use ‘‘+’’ to indicate a new kind of addition, this time between values of type BIT_VECTOR. This technique is called operator overloading • Example: Consider that we want to add an integer to a binary 1-bit number. Then the following FUNCTION could be used
FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS BEGIN IF (b='1') THEN RETURN a+1; ELSE RETURN a; END IF; END "+";

A call to the function above could thus be the following: SIGNAL inp1, outp: INTEGER RANGE 0 TO 15; SIGNAL inp2: BIT; (...) outp <= 3 + inp1 + inp2; (...) • In ‘‘outp<=3+inp1+inp2;’’, the first ‘‘+’’ is the predefined addition operator (adds two integers), while the second is the overloaded user-defined addition operator (adds an integer and a bit).

Aggregates
• It assigns values to elements of an array
a <= (OTHERS => ‘0’ ) ; a <= “0000” ;

• We can assign values to some bits in a vector and use “OTHERS” clause to assign default values to remaining bits
a <= (0 => ‘1’, 2 => ‘1’, OTHERS => ‘0’ ) ; is equivalent to a <= “00101” ; Useful when we are dealing with large vectors

Classes re-visited
• Each object has a data type and class • Class indicates how the object is used in the module and what can be done with that object • Type indicates what type of data the object contains • Each object belongs to one of the following class: – CONSTANT CLASS – SIGNAL – VARIABLE

CONSTANT

SIGNAL

VARIABLE

Constants
• These are identifiers with fixed values • The value is assigned only once when declared • Values cannot be changed during simulation
CONSTANT bus_width : INTEGER :=16 ; CONSTANT CLK_PERIOD : TIME :=15 ns ;

• Constants make the design description more readable • Design changed at later time becomes easy

Signals
Example: architecture and_gate of myand is signal TEMP : STD_LOGIC ; begin U1 : AND2 portmap ( a, b, TEMP ) ; U2 : AND2 portmap (TEMP, c , d ) ;

Equivalent to wires within a circuit

end and_gate ;
TEMP

a b
AND2 d c AND2

• Thus signals are used :
– to connect design entities together and communicate changes in values within a design – instead of INOUT mode

• Each signal has a history of values i.e. they hold a list of values which include current value of the signal and a set of possible future values that can appear on the signal • Computed value is assigned to signal after specified delay called DELTA DELAY

Variables
• These are objects with single current value • They are used to store the intermediate values between the sequential statements • Variable assignment occurs immediately • Variables can be declared and used inside the process statement only. But they retain their value throughout the entire simulation

Example :
process ( a ) variable count : INTEGER : = 1 ; begin count : = count+ 1 ; end process ;

count contains the total number of events that occurred on signal a

Next class Language elements III .

Ghongade Lecture 6 .B.Language Elements III R.

Attributes • An attribute is data that are attached to VHDL objects or predefined data about VHDL objects • Examples are the current drive capability of a buffer or the maximum operating temperature of the device • Types are – Data Attributes – Signal Attributes – User-defined Attributes .

synthesizable data attributes are the following: • d’LOW : Returns lower array index • d’HIGH : Returns upper array index • d’LEFT : Returns leftmost array index • d’RIGHT : Returns rightmost array index • d’LENGTH : Returns vector size • d’RANGE : Returns vector range • d’REVERSE_RANGE: Returns vector range in reverse order .Data Attributes The pre-defined.

d'RIGHT=0. d'RANGE=(7 downto 0). d'LEFT=7. Then: d'LOW=0. d'LENGTH=8. d'REVERSE_RANGE=(0 to 7) . d'HIGH=7.Example Consider the following signal: SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0).

column) : Returns value in the position specified.If the signal is of enumerated type. then: • d’VAL(pos) : Returns value in the position specified • d’POS(value) : Returns position of the value specified • d’LEFTOF(value) : Returns value in the position to the left of the value specified • d’VAL(row. etc There is little or no synthesis support for enumerated data type attributes .

etc.Signal Attributes Let us consider a signal s Then: • s’EVENT : Returns true when an event occurs on s • s’STABLE : Returns true if no event has occurred on s • s’ACTIVE : Returns true if s = ‘1’ • s’QUIET <time> : Returns true if no event has occurred during the time specified • s’LAST_EVENT : Returns the time elapsed since last event • s’LAST_ACTIVE: Returns the time elapsed since last s=‘1’ • s’LAST_VALUE : Returns the value of s before the last event. .

.with IF WAIT UNTIL (clk'EVENT AND clk='1'). -. when a rising edge occurs on clk) IF (clk'EVENT AND clk='1'). AND if such event is upward (in other words.call to a function .with WAIT IF RISING_EDGE(clk). -.EVENT attribute -..STABLE --attribute used -..EVENT --attribute used -. They return TRUE when an event (a change) occurs on clk...Example All four assignments shown below are synthesizable and equivalent. -. -.used with IF IF (NOT clk'STABLE AND clk='1')..

value: ‘0’. ‘‘00 11 10 01’’. 27. etc.User-defined Attributes • VHDL also allows the construction of user-defined attributes • To employ a user-defined attribute. FUNCTION. STD_LOGIC_VECTOR. SIGNAL. . where: attribute_type: any data type (BIT. etc. it must be declared and specified Attribute Declaration: ATTRIBUTE attribute_name: attribute_type Attribute Specification: ATTRIBUTE attribute_name OF target_name: class IS value. . INTEGER.) class: TYPE. etc.

-. ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3.Example ATTRIBUTE number_of_inputs: INTEGER.. -.returns 3 . inputs <= nand3'number_of_inputs.. .attribute call.

Generics • As the name suggests. GENERIC is a way of specifying a generic parameter • a static parameter that can be easily modified and adapted to different applications • The purpose is to make the code more flexible and reusable • must be declared in the ENTITY • More than one GENERIC parameter can be specified in an ENTITY .

). ARCHITECTURE my_architecture OF my_entity IS .. whose default value is 8.. Therefore. PORT (. its value will be assumed to be 8 ENTITY my_entity IS GENERIC (n : INTEGER := 8. of type INTEGER. END my_entity. . whenever n is found in the ENTITY itself or in the ARCHITECTURE (one or more) that follows. Example The GENERIC statement below specifies a parameter called n..Syntax GENERIC (parameter_name : parameter_type := parameter_value).. END my_architecture. vector: BIT_VECTOR := "00001111").

VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH. .. .. sel) VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0)..Example ARCHITECTURE generic_decoder OF decoder IS BEGIN PROCESS (ena.

there are three types of delay that are encountered – Inertial delay – Transport delay – Delta delay .Delays in VHDL • In VHDL.

Inertial Delay • Inertial delay is the default in VHDL • Behaves similarly to the actual device • Output signal of the device has inertia. which must be overcome for the signal to change value • The inertial delay model is by far the most commonly used in all currently available simulators .

std_logic_1164.LIBRARY IEEE.ALL. ENTITY buf IS PORT ( a : IN std_logic. END buf. USE IEEE. PORT ( b : OUT std_logic). END buf. Due to inertial delay pulse is swallowed up Inertial delay prevents prolific propagation of spikes throughout the circuit . ARCHITECTURE buf OF buf IS BEGIN b <= a AFTER 20 ns.

Transport Delay • It represents a wire delay in which any pulse. no matter how small. wire delays on a PCB. and path delays on an ASIC . is propagated to the output signal delayed by the delay value specified • Especially useful for modeling delay line devices.

LIBRARY IEEE. ARCHITECTURE delay_line OF delay_line IS BEGIN b <= TRANSPORT a AFTER 20 ns.std_logic_1164. END delay_line. END delay_line. USE IEEE. ENTITY delay_line IS PORT ( a : IN std_logic.ALL. Pulse is simply delayed . PORT ( b : OUT std_logic).

zero delay events must be ordered to produce consistent results .Delta delay • These are used since the PC that processes and simulates a concurrent phenomenon is basically a sequential machine • The simulation program mimics concurrency by scheduling events in some order • Simulation deltas are used to order some types of events during a simulation • Specifically.

Circuit that shows the difference! A Assumptions Zero delay components CLK=‘1’ A=‘1’ CLK B E DFF F D Q D C CLK Q' .

Problem when no delta delay concept is used A A 1) A becomes 0 2) Evaluate inverter 3) B <= 1 4) Evaluate AND with C=1 DFF DFF F D D Q Q CLK CLK B B E E 5) D<=1 6) Evaluate NAND 7) C<=0 8) Evaluate AND 9) D<=0 C C CLK CLK Q' Q' D Unwanted D assertion .

Problem when no delta delay concept is used A 1) A becomes 0 2) Evaluate inverter 3) B <= 1 CLK B E DFF F F D Q 4) Evaluate NAND 5) C<=0 6) Evaluate AND 7) D<=0 C CLK Q' D .

simulation deltas are an infinitesimal amount of time used as a synchronization mechanism when 0 delay events are present. .Delta delay use 10 ns Delta 1 Delta 2 Delta 3 Delta 4 11 ns A<=0 Evaluate inverter B<=0 Evaluate AND Evaluate NAND D<= 1 C <=0 Evaluate AND D<= 0 To summarize.

Concurrent Statements and Constructs .

Combinational vs. Sequential Logic The output of the circuit depends solely on the current inputs Output does depend on previous inputs hence storage elements are required input output Combinational Logic input Combinational Logic output Present State Storage Elements Next State .

Concurrent Code • Consider the following statement: X=X+Y. In conventional software X and Y are register locations hence contents of X and Y are added and stored in X Register X Register Y + .

Difference in VHDL • In VHDL the same statement will mean a feedback in a purely combinational logic which is invalid X Y + .

. or PROCEDURE are sequential • Concurrent code is also called dataflow code • Order does not matter • We can only build combinational logic circuits with concurrent code • Concurrent assignment produces one driver for each assignment statement a z z <= a.• VHDL code is inherently concurrent (parallel) • Only statements placed inside a PROCESS. FUNCTION.

z <= c and d. begin z <= a and b.c.a.d : std_logic . with a hi-impedance state a b ? c d z .Multiple driver assignment architecture ABC of XYZ is signal z. . Care has to be taken to handle such conditions . .b.

Next Class Concurrent constructs .

Ghongade Lecture 7 .Concurrent Constructs R.B.

Types of concurrent constructs • when … else • with … select These constructs need not be in the process .

. depending on the values of Boolean conditions which are tested in sequence • Equivalent to a process containing an if statement Syntax [Label:] Target <= [Options] Expression [after TimeExpression] when Condition else Expression [after TimeExpression] when Condition else ..when…else • A concurrent statement which assigns one of several expressions to a signal. . Expression [after TimeExpression] [when Condition].

end generate – begin – HERE .end Rules: • The reserved word guarded may only appear in a signal assignment within a guarded block.end block – begin – HERE .Where to use ? architecture – begin – HERE . A guarded assignment only executes when the guard expression on the surrounding block is true • An Expression on the right hand side may be replaced by the reserved word “unaffected” .

although processes can be easier to read and maintain in some cases • A conditional assignment is a neat way to convert from a Boolean condition to the type Std_logic . because the conditions are tested in sequence Remarks: • Conditional and selected signal assignments are a concise way to describe combinational logic in Register Transfer Level descriptions.Synthesis • Conditional signal assignments are synthesized to combinational logic • The Expressions on the right hand side are multiplexed onto the Target signal • The resulting logic will be priority encoded.

c MUX21 b z s2 a MUX21 s1 .Example z <= a when s1=‘1’ else b when s2=‘1’ else c .

control in1 out1 . end tri_buff .Example (Tri-state Buffer) architecture tri_buff of tri_buff_part is begin out1 <= in1 when control=‘1’ else ‘z’.

• Equivalent to a process containing a case statement Syntax [Label:] with Expression select Target <= [Options] Expression [after TimeExpression] when Choices. Expression [after TimeExpression] when Choices.with…select • A concurrent statement which assigns one of several expressions to a signal. depending on the value of the expression at the top. . Expression when others.

Where to use ? architecture – begin – HERE – end block – begin – HERE – end generate – begin – HERE – end Rules: • Every case of the Expression at the top must be covered once and only once by the choices • An Expression on the right hand side may be replaced by the reserved word “unaffected” • All possible choices must be enumerated • “others” clause is important since we have 9valued logic .

Synthesis • Selected signal assignments are synthesized to combinational logic • The Expressions on the right hand side are multiplexed onto the Target signal Remarks: • Conditional and selected signal assignments are a good way to describe combinational logic in Register Transfer Level descriptions .

a.std_logic z <= a when “00” .Assumptions begin -.-.z are with control select -.Example (Multiplexer) architecture mux41 of mux is -.c. -.d.b. d when “11” .std_logic_vector(1 downto 0) c when “10” . a b c d z MUX41 control . end mux41 . ‘Z’ when others .control is b when “01” .

Block • There are two types of blocks – Simple – Guarded .

Simple block • The BLOCK statement. with the purpose of turning the overall code more readable and more manageable (which might be helpful when dealing with long codes) . in its simple form. represents only a way of locally partitioning the code • It allows a set of concurrent statements to be clustered into a BLOCK.

END BLOCK block2 ... block2: BLOCK BEGIN . block1: BLOCK BEGIN . General form of architecture using block for partitioning ARCHITECTURE example .... END BLOCK block1 . .Syntax label: BLOCK [declarative part] BEGIN (concurrent statements) END BLOCK label... BEGIN .. . ... END example ...

[more concurrent statements of top block] END BLOCK label1.• Block can be nested inside another block Syntax label1: BLOCK [declarative part of top block] BEGIN [concurrent statements of top block] label2: BLOCK [declarative part nested block] BEGIN (concurrent statements of nested block) END BLOCK label2. .

. which includes an additional expression. called guard expression • A guarded statement in a guarded BLOCK is executed only when the guard expression is TRUE Syntax label: BLOCK (guard expression) [declarative part] BEGIN (concurrent guarded and unguarded statements) END BLOCK label.Guarded block • A guarded BLOCK is a special kind of BLOCK.

END latch. END BLOCK b1. with a guarded BLOCK even sequential circuits can be constructed LIBRARY ieee.std_logic_1164. q: OUT STD_LOGIC). Latch . USE ieee. ARCHITECTURE latch OF latch IS BEGIN b1: BLOCK (clk='1') BEGIN q <= GUARDED d.• Even though only concurrent statements can be written within a BLOCK. clk: IN STD_LOGIC.all. ENTITY latch IS PORT (d. END latch.

END DFF.LIBRARY ieee.all. while q <= GUARDED '0‘ WHEN rst='1' is a guarded statement.std_logic_1164. ENTITY DFF IS PORT (d. q: OUT STD_LOGIC). In it. rst: IN STD_LOGIC. clk'EVENT AND clk='1' is the guard expression. ARCHITECTURE DFF OF DFF IS BEGIN b1: BLOCK (clk’EVENT AND clk='1') BEGIN q <= GUARDED ‘0’ WHEN rst=‘1’ ELSE d. q<='0' will occur when the guard expression is true and rst is ‘1’ DFF . Therefore. USE ieee. clk. Here. is designed. with synchronous reset. END DFF. END BLOCK b1. a positive-edge sensitive D-type flip-flop.

Homework Problems 1)Generic encoder 2) 8.bit ALU .

For ALU in problem 2 sel Operation 0000 y <= a 0001 y <= a+1 0010 y <= a-1 0011 y <= b 0100 y <= b+1 0101 y <= b-1 0110 y <= a + b 0111 y <= a + b + cin 1000 y <= NOT a 1001 y <= NOT b 1010 y <= a AND b 1011 y <= a OR b 1100 y <= a NAND b 1101 y <= a NOR b 1110 y <= a XOR b 1111 y <= a XNOR b Function Transfer a Increment a Decrement a Transfer b Increment b Decrement b Add a and b Add a and b with carry Complement a Complement b AND OR NAND NOR XOR XNOR Logic Arithmetic Unit .

3) Priority Encoder The circuit must encode the address of the input bit of highest order that is active. ‘‘000’’ should indicate that there is no request at the input (no bit active) .

Expected waveform for Problem 3 .

Next Class Component Instantiation DO NOT MISS IN ANY CASE ! .

Ghongade Lecture 8.Component Instantiation R.10 .9.B.

Component • A component is analogous to a chip socket. and is associated with a (lower level) entity and architecture during elaboration using information from a configuration. but they must have the same names . • A component declaration is similar in form to an entity declaration. in that it includes the required ports and parameters of the component • The difference is that it refers to a design described in a separate VHDL file • The ports and parameters in the component declaration may be a subset of those in the component file. it gives an indirect way to use one hierarchical block within another • A component is instantiated within an architecture.

Component can be declared in the main code itself .

Component can be declared in a package .

output_name : OUT STD_LOGIC).begin . bidir_name : INOUT STD_LOGIC. PORT (input_name.begin .end architecture . output_name. END COMPONENT.<HERE> .end generate . parameter_name : integer := default_value).<HERE> .is .<HERE> .<HERE> . input_name : IN STD_LOGIC. bidir_name.end block .end .Syntax : COMPONENT component_name GENERIC ( parameter_name : string := default_value .begin . Where : package .

and generics and ports must also match in name. mode and type Synthesis: • A component without a corresponding design entity is synthesized as a black box In VHDL'93. It is possible instead to directly instantiate an entity within an architecture. . components are not necessary. the component name must match the name of the corresponding entity to be used in its place.Rules: • For default configuration.

. end component . port (Clock.Example component Counter generic (N: INTEGER). Enable: in Std_logic. Q: buffer Std_logic_vector (N-1 downto 0)). Reset.

a direct instantiation of an entity bypasses the component and configuration .Instantiation • A concurrent statement used to define the design hierarchy by making a copy of a lower level design entity within an architecture • In VHDL'93.

InstanceLabel: configuration ConfigurationName [GenericMap] [PortMap].end block – begin .<HERE> . InstanceLabel: entity EntityName[(ArchitectureName)] [GenericMap] [PortMap].end . Where: architecture – begin .Syntax: InstanceLabel: [component] ComponentName [GenericMap] [PortMap].<HERE> .end generate – begin .<HERE> .

architecture or configuration must be compiled into a library before the corresponding instance can be compiled • However.Counter(RTL) port map (Clk. . N2. G2: entity WORK.Rules: • An entity. Rst.2 ns) port map (N1. N3). Count). an instance of a component can be compiled before the corresponding design entity has even been written Example : G1: NAND2 generic map (1.

but may also appear in a configuration Syntax generic map ([Formal =>] Actual..Generic Map • Used to define the values of generics • Usually given in an Instance.. .) Formal = {either} Name FunctionCall Actual = Expression .

<HERE> .Where : Label : ComponentName <HERE> port map (…). port – begin .end Rules : The two forms of syntax (ordered list or explicitly named choices) can be mixed. but the ordered list must come before the named choices A generic map does not end with a semicolon! .use . for .<HERE> port map (…) block – generic (…).

N3). begin G1: NAND2 generic map (1. N6). port (A. F : out STD_LOGIC). end Structure.8 NS) port map (N1. G2: NAND2 generic map (TPLH => 2 NS. . 2. TPHL: TIME := 0 NS). N2. end component. B: in STD_LOGIC. TPHL => 3 NS) port map (N4.9 NS.Example: architecture Structure of Ent is component NAND2 generic (TPLH. N5.

Port Map • A port map is typically used to define the interconnection between instances in a structural description (or netlist) • A port map maps signals in an architecture to ports on an instance within that architecture • Port maps can also appear in a configuration or a block .

for .)..use .begin .generic map (…) <HERE>. . .Syntax: port map ([Formal =>] Actual.port (…) .end . <HERE>. block .. Formal = {either} Name FunctionCall Actual = {either} Name FunctionCall open Where: Label : ComponentName generic map (…) <HERE>.

but the ordered list must come before the named ports • Within an instance.Rules: • The two forms of syntax (ordered list or explicitly named ports) can be mixed. this is called implicitly as values are passed out Use the port names rather than order to improve readability and reduce the risk of making connection errors . the formals are ports on the component or entity being instanced. the actuals are ports on the component • If the actual is a conversion function. this is called implicitly as values are passed in • If the formal is a conversion function. the formals are ports on the entity. the actuals are signals visible in the architecture containing the instance • Within a configuration.

. RST.default value Q: out Std_logic_vector(3 downto 0)). -.. G1: COUNTER port map (Clk32MHz.. open. end component.unconnected Q(1 downto 0) => Cnt2. G2: COUNTER port map ( RESET => RST. RESET: in Std_logic.-. -. CLK => Clk32MHz. UpDown: in Std_logic := '0'. -.Positional association. Q(2) => open.... Q(3) => Q2MHz. Count). UpDown => open).Example: component COUNTER port (CLK..Named association (order doesn't matter). .

Top Level Entity and Lower Level Entity RST RESET Clk32MHz Q2MHz CLK Cnt2 TOP LEVEL ENTITY Updown COUNTER (LOWER LEVEL ENTITY) Q COUNT .

RESET => RST CLK => Clk32MHz RST Q(3) => Q2MHz TOP LEVEL ENTITY Clk32MHz Q2MHz RESET RESET CLK Q Updown G1 CLK Q(3) Updown G2 Cnt2 Q(0) COUNT UpDown => open .

in2. b => in2 . b : in std_logic. temp2 : std_logic. c : out std_logic). end ND4. U3 : ND2 port map (a => temp1 . . U2 : ND2 port map (a => in3 . b => temp2 . b => in4 . c => temp2). end component .A still simpler example entity ND4 is port (in1. c => z). begin U1 : ND2 port map (a => in1 . z : out std_logic). c => temp1).in3. architecture ND4_CI of ND4 is component ND2 port (a .in4 : in std_logic . end ND4_CI . signal temp1.

infers… ND4 IN1 a c b IN2 U1 a c => temp1 for U1 a => temp1 for U3 c b IN3 U3 Z a c b IN4 U2 c => temp2 for U2 b => temp2 for U3 .

Generate statement • A concurrent statement used to create regular structures or conditional structures during elaboration • Used to create multiple copies of components . processes or blocks • It provides a compact description of regular structures such as memories . registers and counters .

• Two flavours of generate statement are: – for … generate • Number of copies is determined by a discrete range – if … generate • Zero or one copy is made conditionally • Range must be a computable integer in any of the following forms: – integer_expression to integer_expression – integer_expression downto integer_expression – Each integer_expression evaluates to an integer .

. . begin] ConcurrentStatements... end generate [Label]... Label: if Condition generate [Declarations...Syntax : Label: for ParameterName in Range generate [Declarations. begin] ConcurrentStatements.. end generate [Label].

<HERE> . but not all synthesis tools support generate! .e.end block – begin .Where: architecture – begin . i.end Rules : • The Range and Condition must both be static.<HERE> . they cannot include signals • The Label at the beginning of the generate statement cannot be omitted Synthesis: • Synthesis is straightforward.end generate – begin .<HERE> .

C(k). PCOUT .C(k+1).SUM(k). . end generate GK . PSUM : out std_logic) . -. -.cin is declared in entity GK : for k in 3 downto 0 generate FA :full_add port map(A(k). end component . PC : in std_logic . cout <= c(4) . begin c(0) <= cin . signal c: std_logic_vector(4 downto 0).B(k).cout is declared in entity end ABC . PB .Example: architecture ABC of full_add4 is component full_add port (PA .

infers… A(3) B(3) A(2) B(2) A(1) B(1) A(0) B(0) Cout FA3 C(3) FA2 C(2) FA1 C(1) FA0 Cin SUM(3) SUM(2) SUM(1) SUM(0) .

Q : out std_logic) . GK1_3 : if k > 0 generate DFILPFLOP : DFF port map (Q(k-1). clock . end generate GK . CLK : in std_logic . Q(k)). end generate GK1_3 . begin GK : for k in 0 to 3 generate GK0 : IF k=0 generate DFILPFLOP : DFF port map (count . end SHIFTER_ARCH . end generate GK0 . . end component .Another example architecture SHIFTER_ARCH of SHIFTER is component DFF port (D . Q(k)). clock .

infers… CLOCK COUNT DF0 DF1 DF2 DF3 Q(0) Q(1) Q(2) Q(3) .

Ways to describe a circuit! • Three types of descriptions possible with VHDL – Structural – Dataflow – Behavioral .

you have to first manually design the circuit. which is the lowest level. • Use VHDL to specify the components and gates that are needed by the circuit and how they are connected together by following your circuit exactly • Synthesizing a structural VHDL description of a circuit will produce a netlist that is exactly like your original circuit • The advantage of working at the structural level is that you have full control as to what components are used and how they are connected. • But you need to first come up with the circuit and so the full capabilities of the synthesizer are not utilized .Structural Method • At the structural level.

you use the built-in logical functions of VHDL in signal assignment statements to describe a circuit. This is like having only 2-input gates to work with ! All the statements use in the structural and dataflow level are executed concurrently .Dataflow Method • At the dataflow level. which again you have to first design manually • Boolean functions that describe a circuit can be easily converted to signal assignment statements using the built-in logical functions • The only drawback is that the built-in logical functions such as the AND and OR function only take two operands.

WHILE LOOP. and variable assignments • The statements are enclosed in a process block and are executed sequentially . IF THEN ELSE.Behavioral Method • Describing a circuit at the behavioral level is most similar to writing a computer program • You have all the standard high-level programming constructs such as the FOR LOOP. CASE.

segment display decoder a I3 I2 I1 I0 segs(6) {seg 'a'} segs(5) {seg 'b'} segs(4) {seg 'c'} segs(3) {seg 'd'} segs(2) {seg 'e'} segs(1) {seg 'f'} segs(0) {seg 'g'} f g e d b BCD to 7-segment display decoder c .Example BCD to 7.

Truth-table .

Logic Equations a = I 3 + I1 + ( I 2 b = I 2 + ( I1 ' ' ' ' I0 ) I0) ' ' ' c = I 2 + I1 + I 0 d = I1I 0 + I 2 I 0 + I 2 I1 + I 2 I1 I 0 e = I1I 0 + I 2 I 0 ' ' ' ' ' ' ' f = I 3 + I 2 I1 + I 2 I 0 + I1 I 0 g = I 3 + ( I 2 ⊕ I1 ) + I1I 0 ' .

Logic gates .

. i2: IN BIT. END Dataflow. END myand2.o: OUT BIT). END Dataflow.Structural VHDL description ENTITY myxnor2 IS PORT(i1.o: OUT BIT). ARCHITECTURE Dataflow OF myand2 IS BEGIN o <= i1 AND i2. i2: IN BIT. END myxor2. ARCHITECTURE Dataflow OF myxnor2 IS BEGIN o <= not(i1 XOR i2). i2: IN BIT. ENTITY myxor2 IS PORT(i1. ARCHITECTURE Dataflow OF myxor2 IS BEGIN o <= i1 XOR i2. ENTITY myand2 IS PORT(i1. END myxnor2.o: OUT BIT). END Dataflow.

i2: IN BIT. . ARCHITECTURE Dataflow OF myor3 IS BEGIN o <= i1 OR i2 OR i3. ARCHITECTURE Dataflow OF myor2 IS BEGIN o <= i1 OR i2. o: OUT BIT). i3: IN BIT. END myor3. ENTITY myor2 IS PORT(i1. END Dataflow. END myand3.o: OUT BIT). END Dataflow.o: OUT BIT). i3: IN BIT. END Dataflow. END myor2. ENTITY myor3 IS PORT(i1. i2.ENTITY myand3 IS PORT(i1. ARCHITECTURE Dataflow OF myand3 IS BEGIN o <= (i1 AND i2 AND i3). i2.

ENTITY inv IS PORT (i: IN BIT.ENTITY myor4 IS PORT(i1. END Dataflow. i4: IN BIT. o: OUT BIT). i2. END myor4. END Dataflow. . i3. o: OUT BIT). ARCHITECTURE Dataflow OF inv IS BEGIN o <= not i. END inv. ARCHITECTURE Dataflow OF myor4 IS BEGIN o <= i1 OR i2 OR i3 OR i4.

c. END COMPONENT.o: OUT BIT).LIBRARY ieee. END COMPONENT. i2: IN BIT. . END COMPONENT. ARCHITECTURE Structural OF bcd IS COMPONENT inv PORT (i: IN BIT .std_logic_1164. COMPONENT myxor2 PORT(i1. END COMPONENT. USE ieee.o: OUT BIT). f. b. END COMPONENT. g: OUT BIT).all. COMPONENT myor4 PORT(i1. END COMPONENT. END COMPONENT. COMPONENT myor2 PORT(i1. COMPONENT myxnor2 PORT(i1. i2. i1.o: OUT BIT).o: OUT BIT). i2: IN BIT.o: OUT BIT). i3. COMPONENT myand3 PORT(i1.o: OUT BIT). i3: IN BIT. END bcd. i4: IN BIT. COMPONENT myor3 PORT(i1. e. i2: IN BIT.o: OUT BIT). i2. d. i2: IN BIT. COMPONENT myand2 PORT(i1. ENTITY bcd IS PORT(i0. END COMPONENT. i3: IN BIT.o: OUT BIT). i2. a. i2. i3: IN BIT.

e).z: BIT. m). . U16: myOR2 port map(s. U22: myAND2 port map(i1. x). y. l. U19: myAND2 port map(k. BEGIN U1: INV port map(i2. n.y.w. w. s). U20: myOR4 port map(i3. p). END Structural.m. U6: myXNOR2 port map(i1. U11: myAND2 port map(j.SIGNAL j. U17: myAND2 port map(i2. a). U13: myOR4 port map(x. g). d).n. l. n). q). U4: myXNOR2 port map(i2. z. f). l.k). r).u. i1. i0. v.l.r. o.j). U18: myAND2 port map(i2. c). i0.q.k.p.t. t. U12: myAND3 port map(i2. z).s. U21: myXOR2 port map(i2. v). l. t). i1.o. y). k. q. U10: myAND2 port map(j. U2: INV port map(i1.v. U9: myAND2 port map(i1. k. i1. r. U7: myOR2 port map(j. U15: myAND2 port map(j. b). U8: myOR3 port map(i2.l). U3: INV port map(i0. p. w). U23: myOR3 port map(i3. o). l. l. U14: myAND2 port map(i1. l. k.x. i0. m. U5: myOR3 port map(i3. i0.

seg e Segs(6) <= I(3) OR (I(2) AND NOT I(1)) -. -.all. END bcd. -.seg g END Dataflow.seg a Segs(2) <= (NOT I(2)) OR NOT (I(1) XOR I(0)). Segs(7) <= I(3) OR (I(2) XOR I(1)) OR (I(1) AND NOT I(0)). ENTITY bcd IS PORT ( I: IN STD_LOGIC_VECTOR (3 DOWNTO 0). USE ieee.seg f OR (I(2) AND NOT I(0)) OR (NOT I(1) AND NOT I(0)). Segs: OUT std_logic_vector (1 TO 7)).seg d OR (NOT I(2) AND I(1)) OR (I(2) AND NOT I(1) AND I(0)).seg c Segs(4) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)) -.Dataflow VHDL description LIBRARY ieee. ARCHITECTURE Dataflow OF bcd IS BEGIN Segs(1) <= I(3) OR I(1) OR NOT (I(2) XOR I(0)). -. Segs(5) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)).seg b Segs(3) <= I(2) OR (NOT I(1)) OR I(0). -.std_logic_1164. . -.

"1111111" when "1000".Behavioral VHDL description library IEEE. "1110011" when "1001". architecture Behavioral of BCD is begin with I select Segs <= "1111110" when "0000". "0110000" when "0001". "0000000" when others. use IEEE. .STD_LOGIC_1164. "1111001" when "0011". entity BCD is port( I : in STD_LOGIC_VECTOR(3 downto 0). segs : out STD_LOGIC_VECTOR(6 downto 0) ). end Behavioral. "1110000" when "0111".all. end BCD. "1011111" when "0110". "1011011" when "0101". "0110011" when "0100". "1101001" when "0010".

Output .

Assignment No 3 Equations for carry_generate(G) and carry_propagate(P) for ALU 74181 hsi si xi yi xi-1 x0 yi-1 y0 c0 Carry Lookahead Logic ci g i= x i . y i pi=xi + yi ci+1= gi + pi . ci .

p1.p0.c0 .p2.p2.p1.c0 c3= g2 + p2 . g1 + p2.p0.c1= g0 + p0 .g0+p3. g0 + p1.c0 c4= g3 + p3 .p0.p1.p2.g1+p3.g0+p2. c0 Additional Information c2= g1 + p1 .p1. g2 + p3.

P_L outputs G_L= (g3+p3.p2.g1+p3.p2.Equations for implementation of G_L .g0)’ P_L=(p3.p2.p0)’ Implement the Carry_Generate and Carry_Propagate outputs also to complete the ALU assignment .g2+p3.p1.p1.

Next Class Sequential Statements .

3.1.0.FA GK.FA GK.FA GK.‘generate’d doubt ! fulladder PA PB PC PCOUT PSUM [1] [0] [1] [1] [1] fulladder PA PB PC PCOUT PSUM [2] [1] [2] [2] [2] fulladder PA PB PC PCOUT PSUM [3] [2] [3] [3] [3] fulladder PA PB PC PCOUT PSUM [4] [3] [4] [3:0] COUT SUM[3:0] A[3:0] B[3:0] Cin [3:0] [3:0] [0] [0] GK.FA GK.FA GK : for k in 3 downto 0 generate = GK : for k in 0 to 3 generate .1.FA GK.FA A[3:0] B[3:0] Cin [3:0] [3:0] [0] [0] fulladder PA PB PC PCOUT PSUM [1] [0] [1] [1] [1] fulladder PA PB PC PCOUT PSUM [2] [1] [2] [2] [2] fulladder PA PB PC PCOUT PSUM [3] [2] [3] [3] [3] fulladder PA PB PC PCOUT PSUM [4] [3] [4] [3:0] COUT SUM[3:0] GK.0.2.2.FA GK.3.

Ghongade Lecture 12 .B.Sequential Statements R.

Sequential Statements • VHDL code is inherently concurrent • Sections of code that are executed sequentially are : – PROCESS – FUNCTION – PROCEDURE • One important aspect of sequential code is that it is not limited to sequential logic • We can build sequential circuits as well as combinational circuits • Sequential code is also called behavioral code • Thus a PROCESS is a concurrent statement which describes behaviour .

• Sequential statements are allowed only inside PROCESSES. or PROCEDURES • Sequential statements are: – IF – WAIT – CASE – LOOP • VARIABLES are also restricted to be used in sequential code only VARIABLE can never be global. FUNCTIONS. so its value can not be passed out directly .

ENTITY or ARCHITECTURE (in its declarative part). while a VARIABLE can only be declared inside a piece of sequential code • SIGNAL is global while VARIABLE is local • The value of a VARIABLE can never be passed out of the PROCESS directly. then it must be assigned to a SIGNAL • Update of VARIABLE is immediate whereas new value for SIGNAL is generally only guaranteed to be available after the conclusion of the present run of the PROCESS • Assignment operator for SIGNAL is “<= “ while that for VARIABLE is “ : = “ . if necessary.SIGNALS and VARIABLES revisited ! • VHDL has two ways of passing non-static values around: by means of a SIGNAL or by means of a VARIABLE • A SIGNAL can be declared in a PACKAGE.

Process • A PROCESS is a sequential section of VHDL code • It is characterized by the presence of IF. and is executed every time a signal in the sensitivity list changes (or the condition related to WAIT is fulfilled) . CASE. or LOOP. and by a sensitivity list (except when WAIT is used) • A PROCESS must be installed in the main code. WAIT.

<HERE> .<HERE> .end architecture .begin .begin .<HERE> .begin .end block .<HERE> . Where entity .Syntax [label:] [postponed] PROCESS (sensitivity list) [VARIABLE name type [range] [:= initial_value.]] BEGIN (sequential code) END [postponed] PROCESS [label].end generate .begin .end “POSTPONED” is a reserved VHDL word .

before simulation starts • A postponed process is not executed until the final simulation cycle of a particular simulation time. and thus sees the stable values of signals and variables A process with neither a sensitivity list nor a wait will loop forever ! .Rules • A process must contain either a sensitivity list or wait statements. but not both • Every process executes once during initialization.

if clk is a signal to be monitored.Using EVENT attribute • To construct a synchronous circuit. monitoring a signal (clock. for example) is necessary • A common way of detecting a signal change is by means of the EVENT attribute • For instance. then clk ’ EVENT returns TRUE when a change on clk occurs (rising or falling edge) .

Be careful about the spelling of elsif and end if ...] end if [Label]. [elsif Condition then SequentialStatements.IF construct • A sequential statement which executes one branch from a set of branches dependent upon the conditions.......] . {any number of elsif parts} [else SequentialStatements. which are tested in sequence Syntax [Label:] if Condition then SequentialStatements.

where outputs remain unchanged for certain input conditions. This can be avoided by using a case statement instead . and to flip-flops in clocked processes • In some circumstances. synthesize to transparent latches in unclocked processes. nested if statements synthesize to multiple logic levels.Synthesis • Assignments within if statements generally synthesize to multiplexers • Incomplete assignments.

ELSIF (x=y AND w='0') THEN temp := "11110000".• A set of elsif branches can be used to impart priority to the conditions tested first • To decode a value without giving priority to certain conditions. use a case statement instead Example IF (x<y) THEN temp:="11111111". . ELSE temp:=(OTHERS =>'0').

the output must copy the input at either the positive or negative transition of the clock signal (rising or falling edge) If rst = ‘1’. q = d) at the positive edge of clk . the output must copy the input (that is. Otherwise. In it.regardless of the status of clk.D Flip-Flop with asynchronous reset • A D-type flip-flop is the most basic building block in sequential logic circuits. then the output must be q = ‘0’ .

std_logic_1164. ARCHITECTURE behavior OF dff IS BEGIN PROCESS (clk. USE ieee. . END IF. rst) BEGIN IF (rst='1') THEN q <= '0'. clk. END PROCESS. ENTITY dff IS PORT (d. END dff. q: OUT STD_LOGIC). ELSIF (clk'EVENT AND clk='1') THEN q <= d. rst: IN STD_LOGIC.LIBRARY ieee.all. END behavior.

Output clk d rst D[0] R Q[0] q q .

Changing the statement ELSIF (clk'EVENT AND clk=‘0') THEN clk d rst D[0] R Q[0] q q .

One Digit counter example Progressive 1-digit decimal counter (0 -> 9 ->0) Single bit input (clk) and a 4-bit output (digit). .

END counter. USE ieee. BEGIN IF (clk'EVENT AND clk='1') THEN temp := temp + 1. IF (temp=10) THEN temp := 0. END counter.LIBRARY ieee. digit <= temp. digit : OUT INTEGER RANGE 0 TO 9). END IF.all. END PROCESS count. END IF. ARCHITECTURE counter OF counter IS BEGIN count: PROCESS (clk) VARIABLE temp : INTEGER RANGE 0 TO 10. .std_logic_1164. ENTITY counter IS PORT (clk : IN STD_LOGIC.

Output In a counter like circuits always use comparison statements with constant values This ensures simple comparator inference as against full comparator inference for comparison with unknown values .

un9_temp clk temp_3[1] count.temp[3:0] + [29:32] un2_temp[29:32] Extra Hardware 0 [29] 0 1 [3] temp_3[3] .[3] [1] [32] digit[3:0] [0] [31] [29] [31] 0 0 1 [1] [3] [1] [32] D[3:0] Q[3:0] [3:0] [3:0] 1 count.un1_temp 0 1 [1] [3] [30] [1] [32] D[3:0] Q[3:0] [3:0] [3:0] 1 temp_3[1] clk count. [3] [30] [1] [32] [29:32] 1010 digit[3:0] < 0 [31] count.temp[3:0] + [29] [31:32] un2_temp[29:32] [29] 0 0 1 [3] temp_3[3] Changing the statement IF (temp>=10) THEN temp := 0.

..Next Class Sequential Statements cont.

Ghongade Lecture 13 .Sequential Statements II R.B.

Wait statement
• The operation of WAIT is sometimes similar to that of IF • PROCESS cannot have a sensitivity list when WAIT is employed • Three flavours of WAIT statements are:
– WAIT UNTIL – WAIT ON – WAIT FOR

Syntax

WAIT UNTIL signal_condition;
• The WAIT UNTIL statement accepts only one signal, thus being more appropriate for synchronous code than asynchronous • Since the PROCESS has no sensitivity list in this case, WAIT UNTIL must be the first statement in the PROCESS • The PROCESS will be executed every time the condition is met

Example ( 8-bit register )
PROCESS -- no sensitivity list BEGIN WAIT UNTIL (clk'EVENT AND clk='1'); IF (rst='1') THEN op <= "00000000"; ELSIF (clk'EVENT AND clk='1') THEN op <= inp; END IF; END PROCESS;

Output and Inference

Output changes only with clk

clk inp[7:0] rst

[7:0] [7:0]

D[7:0] R

Q[7:0]

[7:0] [7:0]

op[7:0]

op[7:0]

Syntax

WAIT ON signal1 [, signal2, ... ];

• The WAIT ON statement accepts multiple signals • The PROCESS is put on hold until any of the signals listed changes

Example ( 8-bit register )
PROCESS BEGIN WAIT ON clk, rst; IF (rst='1') THEN op <= "00000000"; ELSIF (clk'EVENT AND clk='1') THEN op <= inp; END IF; END PROCESS;

Output and Inference

Output changes with clk and rst

clk inp[7:0] rst

[7:0] [7:0]

D[7:0] R

Q[7:0]

[7:0] [7:0]

op[7:0]

op[7:0]

DFF revisited with WAIT!
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dff IS PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; ARCHITECTURE dff OF dff IS BEGIN PROCESS BEGIN WAIT ON rst, clk; IF (rst='1') THEN q <= '0'; ELSIF (clk'EVENT AND clk='1') THEN q <= d; END IF; END PROCESS; END dff;

Output and Inference

clk d rst

D[0] R

Q[0]

q

q

Infers exactly the same hardware as the earlier design
As a homework problem repeat the one digit counter with WAIT statement

• WAIT FOR is intended for simulation only (waveform generation for test-benches) .Syntax WAIT FOR time.

which should be used when no action is to take place • CASE allows multiple assignments for each test condition while WHEN allows only one . so the keyword OTHERS is often helpful • Another important keyword is NULL (the counterpart of UNAFFECTED).Case statement • CASE is another statement intended exclusively for sequential code • The CASE statement (sequential) is very similar to WHEN (combinational) • All permutations must be tested.

.. Choices = Choice | Choice | . {any number of when parts} end case [Label]. when Choices => SequentialStatements.... .. Choice = {either} ConstantExpression Range others {the last branch} .Syntax [Label:] case Expression is when Choices => SequentialStatements...

<HERE>else .=> .<HERE> .=> .<HERE>end loop-<HERE>-end .Where process – begin .end function – begin .<HERE> .when .end if – then .<HERE> .elsif – then .<HERE> .end case .<HERE> .<HERE> .end procedure – begin .

physical. integer.Rules • The Expression must not be enclosed in parenthesis • The type of the Expression must be enumeration. or a one dimensional array • Every case of the Expression must be covered once and only once by the Choices .

e.Synthesis • Assignments within case statements generally synthesize to multiplexers • Incomplete assignments (i. where outputs remain unassigned for certain input conditions) in unclocked processes synthesize to transparent latches • Incomplete assignments in clocked processes synthesize to recirculation around registers .

.Mop up the rest null. end case. when 1 => A <= '1'. D <= '1'. when 2 to 15 is Select a single value More than one statement in a branch => -.Select a range of ADDRESS -.ADDRESS values B <= '1'.Pick out several -.values C <= '1'. C <= '1'. --B <= '1'. when 16 | 20 | 24 => -. when others => -.Example case ADDRESS when 0 => -A <= '1'.

digit counter with SSD output a f g e d CLK COUNTER DIGIT 2 7 BITS DIGIT 1 a b f g e d b c c RST Progressive 2-digit decimal counter (0-> 99-> 0) .2 . with external asynchronous reset plus binary-coded decimal (BCD) to seven-segment display (SSD) conversion .

rst : IN STD_LOGIC. temp2 := temp2 + 1. BEGIN IF (rst='1') THEN temp1 := 0.all. USE ieee. ELSIF (clk'EVENT AND clk='1') THEN temp1 := temp1 + 1. digit2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)). . END counter. ARCHITECTURE counter OF counter IS BEGIN PROCESS (clk. ENTITY counter IS PORT (clk.std_logic_1164. IF (temp1=10) THEN temp1 := 0. IF (temp2=10) THEN temp2 := 0. END IF. digit1. END IF. temp2 := 0. END IF. VARIABLE temp2: INTEGER RANGE 0 TO 10. rst) VARIABLE temp1: INTEGER RANGE 0 TO 10.LIBRARY ieee.

--5B WHEN 6 => digit2 <= "1011111". CASE temp2 IS WHEN 0 => digit2 <= "1111110". --6D WHEN 3 => digit2 <= "1111001". --5F WHEN 7 => digit2 <= "1110000". --33 WHEN 5 => digit1 <= "1011011". --79 WHEN 4 => digit1 <= "0110011". END counter. --7F WHEN 9 => digit2 <= "1111011". --5F WHEN 7 => digit1 <= "1110000". --30 WHEN 2 => digit1 <= "1101101". --70 WHEN 8 => digit1 <= "1111111". --7B WHEN OTHERS => NULL. --7F WHEN 9 => digit1 <= "1111011". --7E WHEN 1 => digit2 <= "0110000". --33 WHEN 5 => digit2 <= "1011011". --7B WHEN OTHERS => NULL. --79 WHEN 4 => digit2 <= "0110011". END CASE. --70 WHEN 8 => digit2 <= "1111111". --7E WHEN 1 => digit1 <= "0110000". . --5B WHEN 6 => digit1 <= "1011111". END CASE. --6D WHEN 3 => digit1 <= "1111001". --30 WHEN 2 => digit2 <= "1101101". END PROCESS.CASE temp1 IS WHEN 0 => digit1 <= "1111110".

Output .

Inference DO NOT TRY TO WORK OUT HOW THIS CIRCUIT WORKS !!! .

Next Class Test !!! .

Sequential Statements III R.Ghongade Lecture 14 .B.

LOOP is intended exclusively for sequential code.Loop statement • LOOP is useful when a piece of code must be instantiated several times • Like IF. or PROCEDURE. FUNCTION. so it too can only be used inside a PROCESS. • There are several ways of using LOOP • A loop is an infinite loop (and thus an error) unless it contains an exit or wait statement . and CASE. WAIT.

Syntax [label:] LOOP (SequentialStatements) END LOOP [label]. FOR / LOOP: The loop is repeated a fixed number of times [label:] FOR identifier IN range LOOP (sequential statements) END LOOP [label]. . WHILE / LOOP: The loop is repeated until a condition no longer holds [label:] WHILE condition LOOP (sequential statements) END LOOP [label].

NEXT: Used for skipping loop steps [label:] NEXT [loop_label] [WHEN condition]..WAIT : Continue looping until. . EXIT: Used for ending the loop [label:] EXIT [label] [WHEN condition].

six times) FOR i IN 0 TO 5 LOOP x(i) <= enable AND w(i+2). where choice is an input (non-static) parameter. y(0. i) <= w(i). is generally not synthesizable . • One important remark regarding FOR / LOOP is that both limits of the range must be static • Thus a declaration of the type "FOR i IN 0 TO choice LOOP".Example of FOR / LOOP: The loop will be repeated unconditionally until i reaches 5 (that is. END LOOP.

. EXIT WHEN Reset = '1'. (other statements) END LOOP. Div2 <= NOT Div2.Example of WHILE / LOOP: WHILE (i < 10) LOOP WAIT UNTIL clk'EVENT AND clk='1'. In this example. END LOOP. LOOP will keep repeating while i < 10 Example of WAIT in LOOP : LOOP WAIT UNTIL Clock = '1'.

but rather a definite exit (that is. the LOOP statement will be considered as concluded). END LOOP. END CASE.Example of EXIT : FOR i IN data'RANGE LOOP CASE data(i) IS WHEN '0' => count:=count+1. the loop will end as soon as a value different from ‘0’ is found in the data vector . In this case. EXIT implies not an escape from the current iteration of the loop. even if i is still within the data range. WHEN OTHERS => EXIT.

. -. NEXT causes LOOP to skip one iteration when i = skip .Example with NEXT: FOR i IN 0 TO 15 LOOP NEXT WHEN i=skip.) END LOOP.jumps to next iteration (..

Some tools do allow loops containing wait statements to describe implicit finite state machines.Synthesis • Not generally synthesizable. but this is not a recommended practice .

Example : 8-bit unsigned Carry Ripple Adder LOWER LEVEL a b TOP LEVEL cin + cout a a0 b0 a1 b1 c1 c2 c7 b a7 b7 c8 cout s cin c0 + + + s0 s1 s s7 sj = aj XOR bj XOR cj cj+1 = (aj AND bj) OR (aj AND cj) OR (bj AND cj) .

std_logic_1164. END PROCESS. cin: IN STD_LOGIC. FOR i IN 0 TO length-1 LOOP s(i) <= a(i) XOR b(i) XOR carry(i). cout <= carry(length). ARCHITECTURE adder OF adder IS BEGIN PROCESS (a. ENTITY adder IS GENERIC (length : INTEGER := 8). PORT ( a. b.LIBRARY ieee. BEGIN carry(0) := cin. END adder. s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0). cin) VARIABLE carry : STD_LOGIC_VECTOR (length DOWNTO 0). b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0). END LOOP. cout: OUT STD_LOGIC). USE ieee. .all. END adder. carry(i+1) := (a(i) AND b(i)) OR (a(i) AND carry(i)) OR (b(i) AND carry(i)).

Output .

starting from the left end 0 0 0 1 1 0 0 0 3 2 1 0 .Example: Leading Zeros The circuit should count the number of leading zeros in a binary vector.

END LOOP. zeros: OUT INTEGER RANGE 0 TO 8). END PROCESS.std_logic_1164. END LeadingZeros. ENTITY LeadingZeros IS PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0).LIBRARY ieee. WHEN OTHERS => EXIT. . END behavior.all. USE ieee. BEGIN count := 0. ARCHITECTURE behavior OF LeadingZeros IS BEGIN PROCESS (data) VARIABLE count: INTEGER RANGE 0 TO 8. zeros <= count. FOR i IN data'RANGE LOOP CASE data(i) IS WHEN '0' => count := count + 1. END CASE.

Output Modify the design for trailing zeros ! .

Ghongade Lecture 15 .Comparison between Concurrent and Sequential Constructs R.B.

the general tendency is for a circuit synthesized from a VHDL code based on IF not to differ from that based on CASE . after optimization.CASE versus IF • Though in principle the presence of ELSE in the IF/ELSE statement might infer the implementation of a priority decoder (which would never occur with CASE). this will generally not happen • When IF (a sequential statement) is used to implement a fully combinational circuit. a multiplexer might be inferred instead • Therefore.

Same inference ! ---. END CASE.With CASE: -----------CASE sel IS WHEN "00" => x<=a. WHEN "10" => x<=c.With IF: -------------IF (sel="00") THEN x<=a. . WHEN OTHERS => x<=d. ELSIF (sel="10") THEN x<=c. ELSE x<=d. ELSIF (sel="01") THEN x<=b. WHEN "01" => x<=b. ---.

FUNCTIONS. or PROCEDURES Yes Any NULL .CASE versus WHEN • CASE and WHEN are very similar. However. or PROCEDURES Yes for WITH/SELECT/WHEN One UNAFFECTED CASE Sequential Only inside PROCESSES. the other is sequential (CASE) WHEN Statement type Usage All permutations must be tested Max. # of assignments per test No-action keyword Concurrent Only outside PROCESSES. FUNCTIONS. while one is concurrent (WHEN).

b WHEN "001". END CASE.With WHEN: ---------------WITH sel SELECT x <= aWHEN "000". . WHEN "010" => x<=c. c WHEN "010".With CASE: ---------------CASE sel IS WHEN "000" => x<=a. WHEN "001" => x<=b.Same functionality ! ---. ---. WHEN OTHERS => NULL. UNAFFECTED WHEN OTHERS.

the complete truth-table should be clearly specified in the code .Using Sequential Code to Design Combinational Circuits • Sequential code can be used to implement either sequential or combinational circuits • Registers are for sequential circuits necessary. so will be inferred by the compiler • This should not happen for combinational circuits • Also for a combinational circuit.

that is. make sure that. the circuit’s complete truth-table can be obtained (indeed. this is true for both sequential as well as concurrent code) . by looking at the code.Rules to be followed while using sequential code for designing combinational circuits • Rule 1: Make sure that all input signals used (read) in the PROCESS appear in its sensitivity list • Rule 2: Make sure that all combinations of the input/output signals are included in the code.

• Failing to comply with rule 1 will generally cause the compiler to simply issue a warning saying that a given input signal was not included in the sensitivity list. however. and then proceed as if the signal were included. Even though no damage is caused to the design in this case. it is a good design practice to always take rule 1 into consideration • With respect to rule 2. the consequences can be more serious because incomplete specifications of the output signals might cause the synthesizer to infer latches in order to hold their previous values .

should be equal to ‘0’ when sel = ‘‘00’’. on the other hand. should be equal to the input selected by sel. that is. y. or ‘1’ if sel = ‘‘01’’ .Bad Combinational Design x should behave as a multiplexer.

all.std_logic_1164. END example. d: IN STD_LOGIC. x. ELSIF (sel=1) THEN x<=b. c. END example. USE ieee. b. sel) BEGIN IF (sel=0) THEN x<=a.LIBRARY ieee. ARCHITECTURE example OF example IS BEGIN PROCESS (a.y: OUT STD_LOGIC). . d. ELSIF (sel=2) THEN x<=c. y<=‘1’. b. END PROCESS. c. y<=‘0’. ENTITY example IS PORT (a. END IF. sel: IN INTEGER RANGE 0 TO 3. ELSE x<=d.

must be included for other conditions of sel i.e. 2 & 3 .Output Value of y remains ‘1’ which is not expected Cure for the problem: y<='X'.

-.. -. -.No feedback end process..Gives pure combinational logic process (Inputs) -.Some templates for use! process (Inputs) -.Outputs assigned for all input conditions .Gives transparent latches + logic .Latched actions end if.All inputs in sensitivity list begin . -.. -....All inputs in sensitivity list begin if Enable = '1' then . end process.

Gives flipflops + logic . end process. -.Test clock edge only .Clock and reset only in -.process (Clock) -.... -.Asynchronous actions elsif Rising_edge(Clock) then -.Test clock edge -.Synchronous actions end if. -..Clock only in sensitivity list begin if Rising_edge(Clock) then -...Gives flipflops + logic process (Clock. Reset) -. -.sensitivity list begin if Reset = '0' then -.only .Synchronous actions end if.asynchronous reset . -.Test active level of -. end process.

. -. -.. .Synchronous actions end process.No sensitivity list begin wait until Rising_edge(Clock).Gives flipflops + logic .process -.

data_out. on the other hand. at the next rising edge of clk the vector present at data_in must be stored in the position specified by addr The output. an address bus (addr). a data output bus (data_out).Implementing RAM • • • The circuit has a data input bus (data_in). plus clock (clk) and write enable (wr_ena) pins When wr_ena is asserted. must constantly display the data selected by addr .

. ENTITY ram IS GENERIC ( bits: INTEGER := 8. clk: IN STD_LOGIC.all.# of bits per word words: INTEGER := 16). END PROCESS.# of words in the memory PORT ( wr_ena. END ram. SIGNAL memory: vector_array.std_logic_1164. -. END ram. addr: IN INTEGER RANGE 0 TO words-1. BEGIN PROCESS (clk. data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0). data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)).LIBRARY ieee. END IF. -. data_out <= memory(addr). END IF. wr_ena) BEGIN IF (wr_ena='1') THEN IF (clk'EVENT AND clk='1') THEN memory(addr) <= data_in. ARCHITECTURE ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR (bits-1 DOWNTO 0). USE ieee.

Output [3:0] ram1 RADDR[3:0] DATA[7:0] WADDR[3:0] WE[0] CLK DOUT[7:0] [7:0] [7:0] data_in[7:0] addr[3:0] wr_ena clk [7:0] [7:0] [3:0] [3:0] data_out[7:0] memory[7:0] .

B.17 . Functions and Procedures R.Packages.Ghongade Lecture 16.

Fundamental units of VHDL code COVERED SO FAR .

Packages • Frequently used pieces of VHDL code are usually written in the form of COMPONENTS. code sharing. it can also contain TYPE and CONSTANT definitions • A package is split into a declaration and a body • The package declaration defines the external interface to the package. the package body typically contains the bodies of any functions or procedures defined in the package declaration . or PROCEDURES • Such codes are then placed inside a PACKAGE and compiled into the destination LIBRARY • Packages allow code partitioning. FUNCTIONS. FUNCTIONS. and code reuse • Besides COMPONENTS. and PROCEDURES.

.. end [package body] [PackageName]... {body} package body PackageName is Declarations.Syntax {declaration} package PackageName is Declarations. end [package] [PackageName]..

functions and components are best put in a package . the declaration and body must conform. the parameters must be identical between the two • Only definitions placed in the package declaration are visible outside the package Common. shared declarations of types. i. procedures.e.REMEMBER THIS ! • Where a function or procedure is placed in a package. constants. subtypes.

green.std_logic_1164. TYPE color IS (red.all. st4). CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111". st2. END my_package.A simple package LIBRARY ieee. PACKAGE my_package IS TYPE state IS (st1. so a PACKAGE BODY is not necessary . st3. USE ieee. The example above shows a PACKAGE called my_package. It contains only TYPE and CONSTANT declarations. blue).

green. Therefore. PACKAGE BODY my_package IS FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS BEGIN RETURN (s'EVENT AND s='1'). st2. PACKAGE my_package IS TYPE state IS (st1. USE ieee.all. END my_package. blue). st3. a PACKAGE BODY is now needed This function returns TRUE when a positive edge occurs on clk . • • • This example contains. besides TYPE and CONSTANT declarations. CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111". st4).Example LIBRARY ieee. END my_package. FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN. END positive_edge.std_logic_1164. TYPE color IS (red. a FUNCTION.

.all). USE work. we have to add a new USE clause to the main code (USE work.my_package.• Any of the PACKAGES in the previous examples can now be compiled. as shown below: LIBRARY ieee.all. . ARCHITECTURE .. ENTITY ....all.my_package.std_logic_1164. becoming then part of our work LIBRARY (or any other) • To make use of it in a VHDL code... . USE ieee...

and thus employ the same sequential statements (IF. for they are the only pieces of sequential VHDL code. CASE. their purpose is to store commonly used pieces of code. that is. FUNCTIONS & PROCEDURES are intended mainly for LIBRARY allocation. WAIT is not allowed) • PROCESS is intended for immediate use in the main code. • A FUNCTION or PROCEDURE can also be installed in the main code itself .Functions & Procedures • FUNCTIONS and PROCEDURES are collectively called subprograms • They are very similar to a PROCESS . so they can be reused or shared by other projects. and LOOP.

operators. sequential statements to define new mathematical or logical functions • Also used to define bus resolution functions.Functions • Used to group together executable. the function must be split into a declaration and a body . and conversion functions between data types • When defined in a package.

. or <parameter list> = SIGNAL signal_name : signal_type .Syntax: Function Body FUNCTION function_name [<parameter list>] RETURN data_type IS [declarations] BEGIN (sequential statements) END function_name. <parameter list> = [CONSTANT] constant_name : constant_type .

end package body .<HERE> .end process .end architecture –is .<HERE> .<HERE> .begin .<HERE> .begin .begin .begin.end Function Body is NOT allowed inside a Package .<HERE> .Where :(FUNCTION DECLARATION) package .<HERE> .end block .begin .end procedure – is .<HERE> .begin .end entity – is .end generate .<HERE> .end function – is .<HERE> .begin .

Rules : • The function_name may be an identifier or an operator • Functions cannot assign signals or variables defined outside themselves. nor can then contain wait statements • A function must execute a return statement • Pure functions cannot have side effects they must do nothing but return a value .

etc.• There can be any number of such parameters (even zero).) • No range specification should be included (for example.STD_LOGIC. whose type is specified by data_type . INTEGER. can only be CONSTANT (default) or SIGNAL (VARIABLES are not allowed). or TO/DOWNTO when using STD_LOGIC_VECTOR) • On the other hand. do not enter RANGE when using INTEGER. there is only one return value. • Their types can be any of the synthesizable data types (BOOLEAN.

". it cannot include a constraint • Variables defined inside a function are initialized each time the function is called • The declaration and body must conform.REMEMBER THIS ! • The return type must be a name.e. the parameters and return type must be identical between the two • The function declaration ends with a ". whereas the function body has is at the corresponding point in the syntax . i.

and c) • a and b are CONSTANTS (notice that the word CONSTANT can be omitted.Synthesis : • Each call to a function is synthesized as a separate block of combinational logic Example : FUNCTION f1 (a. while c is a SIGNAL. for it is the default object). SIGNAL c: STD_LOGIC_VECTOR) RETURN BOOLEAN IS BEGIN (sequential statements) END f1. receives three parameters (a. named f1. • The function. • a and b are of type INTEGER. b. • The output parameter (there can be only one) is of type BOOLEAN . while c is of type STD_LOGIC_VECTOR • Notice that neither RANGE nor DOWNTO was specified. b: INTEGER.

compares x to the -.Function Call • A function is called as part of an expression.returns the largest of a -. -.(expression appears by -.and b -.(expression appears by itself) IF x > maximum(a.. -.statement) . b -. -.itself) y <= maximum(a.converts a to an integer -.(expression associated to a -.. b).largest of a. b) . The expression can obviously appear by itself or associated to a statement (either concurrent or sequential) Examples of function calls: x <= conv_integer(a).

• It is similar to the IF (clk’EVENT and clk = ‘1’) statement -----. IF positive_edge(clk) THEN.Function body: ----------------------------FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS BEGIN RETURN (s'EVENT AND s='1'). .Function call: ----------------------------.. -----... ... END positive_edge..Function positive_edge( ) • The FUNCTION below detects a positive (rising) clock edge.

Function locations PACKAGE + (PACKAGE BODY) LIBRARY FUNCTION/PROCEDURE LOCATION ENTITY MAIN CODE ARCHITECTURE DECLARATIVE PART .

which must contain the body of each FUNCTION (or PROCEDURE) declared in the declarative part of the PACKAGE • . and code sharing purposes).• Though a FUNCTION is usually placed in a PACKAGE (for code partitioning. code reuse. it can also be located in the main code (either inside the ARCHITECTURE or inside the ENTITY) When placed in a PACKAGE. then a PACKAGE BODY is necessary.

q: OUT STD_LOGIC). ENTITY dff IS PORT ( d. END dff.FUNCTION Located in the Main Code LIBRARY ieee. END PROCESS. ELSIF positive_edge(clk) THEN q <= d. END IF. rst) BEGIN IF (rst='1') THEN q <= '0'. .std_logic_1164.all. USE ieee. clk. END my_arch. END positive_edge. rst: IN STD_LOGIC. ARCHITECTURE my_arch OF dff IS FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS BEGIN RETURN s'EVENT AND s='1'. BEGIN PROCESS (clk.

PACKAGE BODY my_package IS FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS BEGIN RETURN s'EVENT AND s='1'.FUNCTION Located in a PACKAGE LIBRARY ieee. . END my_package. END my_package.all.std_logic_1164. PACKAGE my_package IS FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN. USE ieee. END positive_edge.

END my_arch.all. USE ieee. rst) BEGIN IF (rst='1') THEN q <= '0'. WORK DESIGN SPACE SHOULD BE VISIBLE TO THE TOP-LEVEL ENTITY ENTITY dff IS PORT ( d. END PROCESS. . USE work. q: OUT STD_LOGIC).all.my_package. clk.LIBRARY ieee. rst: IN STD_LOGIC. END dff. ARCHITECTURE my_arch OF dff IS BEGIN PROCESS (clk.std_logic_1164. END IF. ELSIF positive_edge(clk) THEN q <= d.

END my_package. BEGIN IF (vector ( vector'HIGH )='1') THEN result:=1. PACKAGE my_package IS FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER.std_logic_1164. END my_package. FOR i IN (vector'HIGH-1) DOWNTO (vector'LOW) LOOP result:=result*2. PACKAGE BODY my_package IS FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER RANGE 0 TO 2**vector'LENGTH-1.Function conv_integer( ) LIBRARY ieee. ELSE result:=0. IF(vector(i)='1') THEN result:=result+1. conv_integer( ) function converts a STD_LOGIC_VECTOR value into an INTEGER value .all. END LOOP. END conv_integer. USE ieee. END IF. RETURN result. END IF.

Algorithm 3 2 1 0 vector’LENGTH=4 vector’HIGH=3 vector ( vector'HIGH )= 0 0 Iteration 1: 1 0 1 vector Since ‘ vector ( vector'HIGH )= 0 ’ 3 downto 0 ( i = 2 to start with ) result=0 result= 0 x 2 result= 0 + 1 Iteration 2: result= 1 x 2 result= 2 + 0 Iteration 3: result= 2 x 2 result= 4 + 1 RETURNED : result = 5 since vector(2)= 1 ( i = 1) since vector(1)= 0 ( i = 0) since vector(0)= 1 .

ARCHITECTURE my_arch OF conv_int2 IS BEGIN y <= conv_integer(a).my_package. USE ieee.all. .std_logic_1164. END conv_int2.LIBRARY ieee. y: OUT INTEGER RANGE 0 TO 15). USE work.all. END my_arch. ENTITY conv_int2 IS PORT ( a: IN STD_LOGIC_VECTOR(0 TO 3).

PROCEDURE • A PROCEDURE is very similar to a FUNCTION and has the same basic purposes • A procedure can return more than one value • Like a FUNCTION. two parts are necessary to construct and use a PROCEDURE: – the procedure itself (procedure body) – procedure call .

<parameter list> = SIGNAL signal_name: mode type. . <parameter list> = VARIABLE variable_name: mode type.Procedure Body PROCEDURE procedure_name [<parameter list>] IS [declarations] BEGIN (sequential statements) END procedure_name. <parameter list> = [CONSTANT] constant_name: mode type.

The same is true for a PROCEDURE. but then the PROCEDURE must be declared in a PROCESS. contrary to a function. or INOUT parameters. Moreover. OUT. VARIABLES. besides WAIT.• • • A PROCEDURE can have any number of IN. and COMPONENTS are not synthesizable when used in a FUNCTION. whereas for output signals (mode OUT or INOUT) the default is VARIABLE WAIT. with the exception that a SIGNAL can be declared. which can be SIGNALS. For input signals (mode IN). the default is CONSTANT. any other edge detection is also not synthesizable with a PROCEDURE (that is. SIGNAL declarations. a synthesizable procedure should not infer registers) . or CONSTANTS.

however. a. x (mode OUT. and c (mode IN) a is a CONSTANT of type BIT. for it is the default object (recall. type INTEGER) • . • • The PROCEDURE has three inputs.. SIGNAL b.Example PROCEDURE my_procedure ( a: IN BIT. SIGNAL y: INOUT INTEGER RANGE 0 TO 99) IS BEGIN . that for outputs the default object is VARIABLE) There are also two return signals. type BIT_VECTOR) and y (mode INOUT. SIGNAL x: OUT BIT_VECTOR(7 DOWNTO 0). c: IN BIT.. b. Notice that the word CONSTANT can be omitted for input parameters. also of type BIT. END my_procedure. while b and c are SIGNALS.

which is called as part of an expression.associated to another -. in2. out1. 1n3. a PROCEDURE call is a statement on its own • It can appear by itself or associated to a statement (either concurrent or sequential) Examples of procedure calls: compute_min_max(in1. 1n3.statement .procedure call -. in2. out1.statement by itself divide (dividend. out2). -.Procedure Call • Contrary to a FUNCTION. -. quotient.statement by itself IF (a>b) THEN compute_min_max(in1. -. remainder). divisor. out2).

B.22 .21.SIMULATION ISSUES R.Ghongade Lecture 20.

SIMULATION ISSUES • • • • SIMULATION SIMULATION PROCESS DELAY MODELING TYPES OF SIMULATION .

that use models to replicate how a device will perform in terms of timing and results .Simulation • Simulation is a functional emulation of a circuit design through software programs.

Simulation • Simulation eliminates the time-consuming need for constant physical prototyping • Simulation can be performed during ALL stages of verification • Motivation of simulation comes from the need to verify that the HDL code is correctly implementing the design • Simply verify that the design meets its required specification .

Flavours of Simulation • Functional Simulation: Is functional verification of the design without any delays • Pre.Layout simulation: Is functional verification of the design including logic cell delays • Post.Layout simulation: Is performed after physical place and route( interconnect delays are taken into account) .

Simulation at different Levels 1 2 3 4 0 a1 Vcc1 b1 b2 a2 b3 a3 a4 GND b4 0 5 6 7 8 1 2 3 4 0 a1 Vcc1 b1 a2 b2 a3 b3 GND b4 a4 0 5 6 7 8 0 1 2 3 4 a1 a2 a3 a4 GND 0 Vcc1 b1 b2 b3 b4 5 6 7 8 1 2 3 4 0 a1 Vcc1 b1 a2 b2 a3 b3 a4 GND b4 0 Register 5 6 7 8 A D Q1 Q4 ENB Long card Module Subsystem Chip System .

Comparison for simulation Module Difficult Higher Low level Low Early Bug correction time Time in project Subsystem Chip System Easier Low All kinds Higher Late Stimuli Development Simulation Efficiency Nature of detected problems .

Steps in simulation ELABORATION INITIALISATION EXECUTION .

then the compiler flags off an error message * Else the compiler generates an intermediate MECHANISM code SEMANTICS SCIENCE OF MEANING SYNTAX OF LANGUAGE .Steps in Simulation • COMPILATION * Checks VHDL source code to check syntax and semantic rules of VHDL * If a syntax or semantic error occurs.

. * Ports are created for each instance of a component * Memory storage is allocated for the required signal * Interconnections among the port signals are specified * Mechanism is established for executing the VHDL process in proper sequence .Steps in Simulation • ELABORATION cont..

..Steps in Simulation cont. • INITIALIZATION * Initial values preset in the declarations statements are assigned to signals/variables .

ASSIGN.Steps in Simulation • EXECUTION cont. * Every process is executed until it suspends.. * Simulator accepts simulation commands like: RUN.WATCH .. Signal values are updated only after this. which control the simulation of the system * Simulation ends when all signals have been updated and new values have been assigned to the signals .

SIMULATION PROCESS BASIC DEFINITIONS •EVENT A CHANGE ON COMPONENT OUTPUT THAT WILL BE PROPAGATED •TRANSACTION A CHANGE ON COMPONENT INPUT THAT DOES NOT PROPAGATE .

SIMULATION PROCESS BASIC DEFINITIONS •SCHEDULING FUTURE EVENTS GENERATED BY EVALUATION OF A PROCESS •EVALUATION CALCULATING THE OUTPUTS OF COMPONENTS BASED ON INPUTS AND CURRENT STATE cont. .

SIMULATION PROCESS Time Jargon Real Time (As it happens…) Simulation Time (Relative to some arbitrary t=0) .

all gate outputs are set to an unknown value Two queues are set up SIGNALS TO BE UPDATED PROCESSES TO BE EXECUTED .SIMULATION PROCESS Simulation executes as follows: At t=0 .

SIMULATION PROCESS • When Simulation time is incremented : • Signal is updated • All processes sensitive to that signal are placed on the process execution queue One loop is called DELTA CYCLE • Each resumed process is executed until it suspends • Effects of the logic changes that have occurred as a result of process execution are evaluated • Simulation time is set to the next event in queue or halted if simulation time gets exhausted .

SIMULATION DELTA • What is simulation delta? •Several logic changes occur simultaneously in a circuit (concurrent operations) •But simulator being run by a sequential machine. hence it cannot process events concurrently. time is frozen within the simulator. •To take care this. •The real time the simulator takes to complete all concurrent operations in the queue is called SIMULATION DELTA .

SIMULATION DELTA Zero simulation time t=0 ns t=1 ns t=2 ns t=3 ns t=4 ns Many delta cycles can occur Real Time The minimum time interval possible for the simulator is assumed to be 1 ns here .

SIMULATION DELTA • SUMMARY Simulation deltas allow ordering of events that occur at the same simulation time during simulation Simulation deltas are infinitesimal amount of time used as synchronism mechanism when zero delay events are present .

DELAY MODELING Delays are timing parameters given by the user for modeling physical characteristics of hardware Types of delays INERTIAL DELAY TRANSPORT DELAY Delays are specified in signal assignment statements only Delays should NOT be used in variable assignments .

no output change occurs .INERTIAL DELAY • It is used to model the inherent inertia of physical devices • Example: – The input value must be stable for a specified minimum pulse duration before the value is allowed to propagate to the output – If the input is not stable for the specified limit.

wires and interconnect delays • Signal value is assigned with a specified delay independent of the width of the input waveform .e..TRANSPORT DELAY • It represents pure propagation delay i.

DELAYS 10 ns X 10 ns 3 ns 6 ns 2 ns Z1 Z2 Z3 .

TYPES OF SIMULATION • • • • • • FUNCTIONAL SIMULATION BEHAVIORAL SIMULATION STATIC TIMING SIMULATION GATE-LEVEL SIMULATION SWITCH-LEVEL SIMULATION TRANSISTOR-LEVEL OR CIRCUITLEVEL SIMULATION .

TYPES OF SIMULATION • FUNCTIONAL SIMULATION It ignores timing aspects Verifies only the functionality of the design • BEHAVIORAL SIMULATION A given functionality is modeled using HDL Timing aspects are considered .

TYPES OF SIMULATION • STATIC TIMING SIMULATION A built in tool that computes delay for each timing path Does not require input stimuli • GATE-LEVEL SIMULATION Is used to check the timing performance of design Delay parameters of logic cells are used to verify things .

TYPES OF SIMULATION • SWITCH-LEVEL SIMULATION Is one level below the gate level simulation It models transistors as switches It provides more accurate timing predictions than gate-level simulation .

Circuit is described in terms of resistances. capacitances and voltage and current sources A set of mathematical equations relating current and voltages is setup and solved numerically Gives analog results and is most accurate Requires large amount of computing resources .TYPES OF SIMULATION • TRANSISTOR-LEVEL SIMULATION Requires transistor models.

And finally!! Simulation time depends on : • Simulation levels of logic • Physical Memory of PC • Speed of PC .

THANK YOU !!!

Test benches in VHDL

R.B.Ghongade Lecture 18,19

Copyright, R.B.Ghongade

Introduction
• A design is always incomplete without verification • There are several ways to verify VHDL designs • Test benches are one of them • Test benches are also called Test cases

• A testbench is an environment, where a design ( called design or unit under test UUT) is checked
– applying signals (stimuli) – monitoring its responses by signal probes and monitors

• A testbench substitutes the design’s environment in such a way that the behaviour of the design can be observed and analyzed.

A testbench always consists of following elements:
– a socket for the unit under test (UUT) – a stimuli generator (a subsystem that applies stimuli to UUT, either generating them internally or reading from an external source) – tools for observing UUT responses to the stimuli

Concept of Testbench

Elements of a VHDL Test Bench
• A VHDL test bench is just another specification with its own • entity • architecture • In addition, it has special structure with some elements that are characteristic to this type of specification: • Test bench entity has no ports, • UUT component instantiation - the relationship between the test bench and UUT is specified through component instantiation and structural-type specification, • Stimuli - it is a set of signals that are declared internally in the test bench architecture and assigned to UUT's ports in its instantiation. The stimuli are defined as waveforms in one or more behavioral processes.

Using Test Benches
• The design must be verifiable. • It is much more convenient to use a test bench for design verification. • Writing a test bench -> very complex task • Therefore some guidelines for future stimuli development should be written as you progress with the design. • It is the test bench which is simulated, not the unit under test. • The UUT is only one of the components instantiated in a test bench. • There is no limitation on the test bench size. • The only limitation is the VHDL simulator used capability.

test Designthe system behave as aset should "does bench specification can input (and state) contain such set of be written expected?" Remember that thean It will contain the stimuli and answer signal values that test bench much received from simulating covers as is The design instantiation of the designed processlife situations as possible. consists of design and VERIFICATION real (unit under test). will receive an answer toeach new design When Specification stimuli are stimuli block. The specified. phase. Test bench Specifications Test bench Simulation .determined reliable only to the extent It is the verification system The objective of the first one is phases by thebench and not designand will test bench accuracy that test VHDL specification that meets the to create a new coverage area. during be simulated The better a test bench Stimuli Definitions the verification system requirements.Writing stimuli can is performed Simulation of the test benchbe the last DESIGN phase of a design process. Here you concurrently with writing specifications for the question. is. the more confident you can be that your system is properly designed.

Example : Multiplexer .

Example : J-K FlipFlop .

Closer look at Testbench UUT: 2.bit Multiplexer .

Testbench .

Waveforms .

Testbench : Using assert…report .

Waveforms .

Error Report .

.SUMMARY • A Test bench thus is an effective builtin tool for verifying VHDL designs •Troubleshooting becomes easier and faster because of the ASSERT…REPORT clause •Automation of verification is possible because of the seamless integration of language elements.

Synthesis Issues R.Ghongade Lecture 19 .B.

Agenda • • • • • • What is synthesis ? Synthesis Tools : Expectations Synthesis Tools : Features Hardware modeling examples Good coding Practices Synthesis guidelines .

What is synthesis ? • Synthesis is an automatic process that converts user’s hardware description into structural logic description • When we use VHDL as textual file. the process is called VHDL Synthesis • Synthesis is a means of converting HDL into real world hardware • Synthesis tools generate a gate-level netlist for the target technology .

a b x x a b a b c d LUT x c d c d • Synthesis is target device technology specific • Synthesizer will try to use the best architectural resource available with the target .What is synthesis ? SYNTHESIS = TRANSLATION + OPTIMIZATION x <= ( a and b ) or ( c and d ).

Several steps work out behind the scene! Translation Optimization Hardware Description . other operations and memory elements Mapping Gate Level – Technology Specific • Translation ( language synthesis ) : Design at higher level of description is compiled into known language elements • Optimization : Algorithms are applied to make the design compact and fast • Design is mapped using architecture specific techniques .written with hardware in mind Mix of Boolean .

Synthesis process – design flow HDL behavioral description Netlist RTL Synthesis RTL Optimization Logic extraction High-level description with Boolean equations Structured Boolean equations Logic Optimization Structured Boolean equations Technology mapping Gate-level optimization Optimized Netlist .

It is split into two phases – Flattening – Structuring • • . timing and area information of all usable gates of the target technology must be available. This removes the redundant logic and reduces the space requirement Technology Mapping: This is the process of transforming technology independent netlist into technology dependent one. During mapping .Synthesis process • Translation : Inputs are transformed into a description based Boolean equations – If the input data consists of gate level netlist then it is necessary to extract Boolean equations to determine functionality of all used gates Technology independent logic optimization: This process aims to improve structure of Boolean equations by applying rules of Boolean algebra .

These equations reflect two level logic in SOP form.Flattening • The aim is to generate Boolean equations for each output of module in such a way that the output value is a direct function of inputs. • Resulting equations do not imply any structure • Good optimization results are obtained • Caution: In case of structured logic this process would destroy the characteristic structure and its associated properties . carry look ahead adder • Flattening cannot be applied to every logic circuit because the number of product terms may become very large .g. e.

g. the resulting area is reduced . the sub-functions are substituted into original equations • Compared to the logic before structuring.C’) and use X everywhere • Finally .B’. If (A’.C’) occurs 10 times then the tool may assign X= (A’.Structuring • New intermediate variables are inserted during the structuring process • E.B’.

review CONSTRAINT(area . SOP form •Structuring is the opposite of flattening. its adds structure to the generic design by extracting common logic factors and representing them as intermediate nodes to produce compact logic . generic .Synthesis process. speed) DESIGN LIBRARIES •Translation process converts RTL to a Boolean form •Optimization is done on the converted Boolean equations •Optimized logic is mapped to technology library SYNTHESIS NETLIST REPORT •Flattening is a process where all the design hierarchy is removed. the entire design is transformed into a flat .

Synthesis tool : expectations
A good synthesis tool should
– perform technology specific optimizations i.e. vendor specific FPGAs and CPLds – have best optimization techniques – allow designer control – have broad language coverage – provide user friendly debugging environment – have fast compile times – provide clean and seamless link with backend tools

Synthesis Tools - features
Tool cost depends on features provided by it Desirable features are: – Replicating the logic – Duplicate flip-flops, remove unused logic – optimization across design hierarchy – resource sharing of adders , incrementors, multipliers – automatic RAM inference (RAM logic is automatically mapped to technology specific RAM cells)

Replicate logic
– Replicate logic to meet fan-out demands – E.g. WR’ may be connected to 100 points hence add buffers to split internally
BUF BUF BUF BUF BUF BUF

Duplicating logic
• We can duplicate the logic which generates the signal , for minimizing fan-out • Trade-off : Loading effect of signals is reduced hence lowering propagation delay but at the cost of logic and interconnect complexity
D Q D Q

D

Q

Resource sharing
• Some synthesis tools automatically perform a limited amount of resource sharing ( for arithmetic expressions that are mutually exclusive) • Consider the code:
ADDSEL: process( sel, a ,b,c,d) begin if (sel=‘1’ ) then y<= a + b ; else y<= c + d ; end if ; end process ADDSEL ;

Resource sharing
a a c

+
b c y b d sel

+

y

+
d

sel

Before resource sharing

After resource sharing

An adder requires more floor space than a multiplexer

Simulation vs. Synthesis
• Some simulation constructs are not supported by synthesis tools
– e.g. wait statements

• Synthesis tools ignore initial values • Care should be taken so that simulationsynthesis mismatch does not occur

Using Signals or Variables
• Variables are used only for convenience of describing behaviour • Variables are used and declared in a process however it cannot be used to communicate between processes • Variable assignments are done immediately and are executed sequentially • Variables may or may not represent physical wires • Signal assignments are done at the end of process • Signals represent physical wires in the circuit

Using Signals or Variables
• Use variables in combinational processes because there is less simulation overhead • Order dependency
– Signal assignments are order independent – Variable assignments are order dependent – Signal assignments under a clocked process are translated into registers – Variable assignments under a clocked process may or may not be translated into registers

to . before being written x : = a and b . x. d) variable y.Signals or Variables process (clk. begin if (clk=‘1’ and clk’event) then z1<= y . end process . w : std_logic . end if. variables are read y : = x . a. memory element z2<= w . b. this infers a w : = c and d . c. .

Hardware inferred .

w : std_logic . end process . x. b. memory element end if. to . this infers a w := c and d . a. c. begin if (clk='1' and clk'event) then x := a and b . .Same process with order of statements changed process (clk. y := x . d) variable y. variables are read z1<= y . before being written z2<= w .

Hardware inferred .

Hardware modeling examples “For loop” process(word) variable result : std_logic. end loop. op<=result. end process. . begin result:='0'. for i in 0 to 7 loop result := result xor word(i).

4) when others => NULL. 2) when others => y<= ‘Z’. when “010” => y<= data(2). 1) when others => y<= ‘0’. end case.Multiplexer optimization The hardware inferred depends on the condition given in the “when others” clause case sel is when “000” => y<= data(0). when “001” => y<= data(1). when “011” => y<= data(3). 3) when others => y<= ‘X’. .

Case 2 when others => y<= ‘Z’. .Case 1 when others => y<= ‘0’.

Case 4 when others => NULL. .Case 3 when others => y<= ‘X’.

Xilinx Virtex series has built-in RAM • Coding for performance : – common mistake is to ignore hardware and start coding as if programming. To achieve best performance the designer must think about hardware .g.Good coding practices • Good coding style means that the synthesis tool can identify constructs within your code that it can easily map to technology features • All programmable devices may have their unique architectural resources e.

Good coding practices • Improve performance by – avoiding unnecessary priority structures in logic – optimizing logic for late arriving signals – structuring arithmetic for performance – avoiding area inefficient code – buffering high fan-out signals .

Good coding practices • Use “constants” to enhance readability and code maintenance • Comparison with a constant is preferred since it is much “cheaper” to implement • To avoid accidental latches – specify all clauses of “if” and “case” statements – specify all outputs • Use “case” rather than “if-then-else” whenever possible • Use parentheses for better operation • Never use mode “buffer” .

Design constraints • Constraining designs: – constraints are means of communicating our requirements to the synthesis and back-end tools • Categories of constraints are : – Timing constraints • • • • maximum frequency duty cycle input delays output delays – Layout constraints .

the ability to obtain the design performance objectives decrease – Run times increase .Design constraints • Avoid over-constraining the design • Consequences of over-constraining are: – Design performance suffers: • critical timing paths get the best placement and fastest routing options • as the number of critical paths increase .

else the synthesis tool will infer a 32-bit port • Avoid mixed clock edges – if a large number of both positive and negative edge flip-flops are required they should be placed in different modules . the range should be specified.Synthesis guidelines • Simulate your design before synthesis • Avoid combinational loops in processes • If a port is declared to be an integer data type.

CPU resources and memory • separate random logic from structured logic • separate timing-sensitive modules from area -sensitive ones .Synthesis guidelines • For best results: – use technology primitives (macros) from the target technology libraries wherever possible – try small designs on target technology to find its limitations and strengths – Partition the design correctly • eliminate glue logic at the top level • partition block size based on the logic function.

Next class CPLDs and FPGAs .

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