Reg. No.: Question Paper Code: Q 2159 B.E/B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2009.

Sixth Semester Electroni cs and Communication Engineering CS 1251 â COMPUTER ARCHITECTURE (Regulation 2004) ( Common to Fourth Semester Computer Science and Engineering and Information Techn ology) (Also common to B.E. (Part-time) Fifth Semester - ECE and Third Semester Computer Science and Engineering- Regulation 2005) Time: Three hours marks Answe r ALL questions. PART A â (10 x 2 = 20 marks) 1. 2. 3. 4. 5. 6. 7. State the operati on involved in the execution of ADD Rl, R0 instruction. What is meant by Central Processing Unit (CPU)? Define overflow rule in addition and subtraction. Recode the multiplier 101100 for booth's multiplication. What is pipelining? Compare h orizontal and vertical format. Calculate the effective address time if average p age-fault service time of 20 ms and a memory access time of 80 ns. Let us assume the probability of a page fault 10%. What is data stripping? What is interrupt? What do you mean by DMA? Maximum: 100 8. 9. 10.

Describe the algorithm for integer division with suitable example? Or (b) 13. Or (b) 15. (a) Explain the various b asic instruction operations with an example. . O (b) Explain USB pr otocols in detail. Or (b) 14. (a) Explain the function of each functional unit in the computer system with suitable diagram. (a) Discuss the different mapping techniques used in c ache memories. (a) Explain in detail the principle o f carry-look-ahead adder. Or (b) 12. Explain the various types hazards and the solutions to overcome them in detail. Explain in detail about internal organization o f memory chip.PART B â (5 x 16 = 80 marks) 11. Explain the Device configuration in PCI bus. (a) Explain Basic Operation of a four stage pipelining with a neat diagram.

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