DIGITAL LOGIC FAMILIES
Digital Logic Families
ICs are also classified based on their specific circuit technology, known as digital logic family. Each family has its own basic electronic components (NAND, NOR, and NOT gates), used to build complex digital circuits. Various digital logic families have been introduced and used over the years. (in chronological order) RTL: Resistor-Transistor Logic DTL: Diode-Transistor Logic TTL: Transistor-Transistor Logic ECL: Emitter-coupled Logic MOS: Metal-Oxide Semiconductor CMOS: Complementary MOS ◦ Low power dissipation, currently the MOST DOMINANT BiCMOS: Bipolar CMOS ◦ CMOS and TTL for additional current/speed GaAs: Gallium-Arsenide
Defining Characteristics of Digital Logic Families
Fan-in: # of gate inputs. Fan-out: # of standard loads a gate’s output can drive. Noise margin: max external noise tolerated. Power dissipation: power consumed by the gate (dissipated as heat). Propagation delay: time required for an input signal change to be observed at an output line.
Propagation Delay One of the most important design parameters (if not THE most important!) The maximum propagation delay (tpd) determines the circuit’s speed. tPHL: high-to-low propagation time tPLH: low-to-high propagation time tpd = max(tPHL, tPLH)
The Power dissipation of a logic gate is the product of the direct current (dc) voltage supply (VCC) and the average supply current (ICC). The average ICC is determined based on a 50% duty cycle, i.e. the state is LOW 50% of the time and HIGH 50% of the time.
The fan-out of a gate is the maximum number of inputs of the same IC family series that the gate can drive while maintaining the its output levels within specified limits. In short, it specifies the maximum load that a given gate can handle. If this limit is exceeded that the operation of the gate degrades and become unpredictable.
Figure of merit
A Figure of merit is a quantity used to characterize the performance of a device relative to other devices of the same type. It is often used as a marketing tool to convince consumers to choose a particular brand. Power - Delay Product: Another Important Parameter = (Average Power Diss)x(Propagation Delay)
Fan-in The number of standard loads drawn by an input to ensure reliable operation. Most inputs have a fan-in of 1.
Logic Threshold Voltage Levels
VCC: The voltage applied to the power pin(s). In most cases the voltage the device needs to operate at. VIH: [Voltage Input High] The minimum positive voltage applied to the input which will be accepted by the device as a logic high. VIL: [Voltage Input Low] The maximum positive voltage applied to the input which will be accepted by the device as a logic low. VOL: [Voltage Output Low] The maximum positive voltage from an output which the device considers will be accepted as the maximum positive low level. VOH: [Voltage Output High] The maximum positive voltage from an output which the device considers will be accepted as the minimum positive high level. VT: [Threshold Voltage] The voltage applied to a device which is "transition-Operated", which cause the device to switch. May also be listed as a '+' or '-' value.
NoiseMargin Logic Noise Margin is the difference between what the driver IC outputs as a valid logic voltage and what the receiver IC expects to see as a valid logic voltage. There are two different types of noise margin, one for a logic high value  and one for a logic low value . For a valid logic low, the worst case noise margin for the circuit is the maximum low level voltage which may be output from the driver; minus, the maximum low level voltage which may be seen at the receiver IC
Noise Margin Output high = VOH [driving device] - VIH [receiving device] Noise Margin Output low = VIL [receiving device] - VOL [driving device] The higher the numbers the better, with negative numbers indicating in-operability. Use Minimum numbers for output High, and maximum numbers for Output Low.
Diode Logic makes use of the fact that the electronic device known as a diode will conduct an electrical current in one direction, but not in the other. In this manner, the diode acts as an electronic switch.
To the left you see a basic Diode Logic OR gate. We'll assume that a logic 1 is represented by +5 volts, and a logic 0 is represented by ground, or zero volts. In this figure, if both inputs are left unconnected or are both at logic 0, output Z will also be held at zero volts by the resistor, and will thus be a logic 0 as well. However, if either input is raised to +5 volts, its diode will become forward biased and will therefore conduct. This in turn will force the output up to logic 1. If both inputs are logic 1, the output will still be logic 1. Hence, this gate correctly performs a logical OR function.
To the right is the equivalent AND gate. We use the same logic levels, but the diodes are reversed and the resistor is set to pull the output voltage up to a logic 1 state. For this example, +V = +5 volts, although other voltages can just as easily be used. Now, if both inputs are unconnected or if they are both at logic 1, output Z will be at logic 1. If either input is grounded (logic 0), that diode will conduct and will pull the output down to logic 0 as well. Both inputs must be logic 1 in order for the output to be logic 1, so this circuit performs the logical AND function.
Resistor-Transistor Logic . Consider the most basic transistor circuit, such as the one shown to the left. We will only be applying one of two voltages to the input I: 0 volts (logic 0) or +V volts (logic 1). We'll assume an ordinary NPN transistor here, with a reasonable dc current gain, an emitter-base forward voltage of 0.65 volt, and a collector-emitter saturation voltage no higher than 0.3 volt. In standard RTL ICs, the base resistor is 470 and the collector resistor is 640.
•When the input voltage is zero volts (actually, anything under 0.5 volt), there is no forward bias to the emitter-base junction, and the transistor does not conduct. Therefore no current flows through the collector resistor, and the output voltage is +V volts. Hence, a logic 0 input results in a logic 1 output
The gate to the right is a DL OR gate followed by an inverter such as the one we looked at in the page on resistor-transistor logic. The OR function is still performed by the diodes. However, regardless of the number of logic 1 inputs, there is certain to be a high enough input voltage to drive the transistor into saturation. The advantage of this circuit over its RTL equivalent is that the OR logic is performed by the diodes, not by resistors. A disadvantage of this circuit is the input resistor to the transistor. Its presence tends to slow the circuit down, thus limiting the speed at which the transistor is able to switch states.
Transistor-Transistor Logic: With the rapid development of integrated circuits (ICs), new problems were encountered and new solutions were developed. One of the problems with DTL circuits was that it takes as much room on the IC chip to construct a diode as it does to construct a transistor. Well, looking at the DTL NAND gate to the right, we might note that the opposed diodes look pretty much like the two junctions of a transistor. In fact, if we were to have an inverter, it would have a single input diode, and we just might be able to replace the two opposed diodes with an NPN transistor to do the same job.
The designers of commercial TTL IC gates reduced that problem by modifying the output circuit. The result was the "totem pole" output circuit used in most of the 7400/5400 series TTL ICs. The final circuit used in most standard commercial TTL ICs is shown to the right. The number of inputs may vary — a commercial IC package might have six inverters, four 2-input gates, three 3-input gates, or two 4input gates. An 8-input gate in one package is also available. But in each case, the circuit structure remains the same.
In the TTL NAND gate of Figure 1, applying a logic '1' input voltage to both emitter inputs of T1 reverse-biases both baseemitter junctions, causing current to flow through R1 into the base of T2, which is driven into saturation. When T2 starts conducting, the stored base charge of T3 dissipates through the T2 collector, driving T3 into cut-off. On the other hand, current flows into the base of T4, causing it to saturate and pull down the output voltage Vo to logic '0', or near ground. Also, since T3 is in cut-off, no current will flow from Vcc to the output, keeping it at logic '0'. Note that T2 always provides complementary inputs to the bases of T3 and T4, such that T3 and T4 always operate in opposite regions, except during momentary transition between regions.
CMOS Logic: CMOS logic is a newer technology, based on the use of complementary MOS transistors to perform logic functions with almost no current required. This makes these gates very useful in battery-powered applications. The fact that they will work with supply voltages as low as 3 volts and as high as 15 volts is also very helpful. CMOS gates are all based on the fundamental inverter circuit shown to the left. Note that both transistors are enhancement-mode MOSFETs; one N-channel with its source grounded, and one P-channel with its source connected to +V. Their gates are connected together to form the input, and their drains are connected together to form the output.
When input A is grounded (logic 0), the N-channel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the P-channel MOSFET is forward biased, so it has a channel enhanced within itself. This channel has a resistance of about 200 , connecting the output line to the +V supply. This pulls the output up to +V (logic 1). When input A is at +V (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state.
This concept can be expanded into NOR and NAND structures by combining inverters in a partially series, partially parallel structure. The circuit to the right is a practical example of a CMOS 2-input NOR gate. In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be off, so there will be no ground connection. However, if either input goes high, that Pchannel MOSFET will turn off and disconnect the output from +V, while that N-channel MOSFET will turn on, thus grounding the output.