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chapter 3 part1 03-09-2001

chapter 3 part1 03-09-2001

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Published by: Mahesha Nb on Dec 05, 2011
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Chapter 3 CMOS processing technology

(How to make a CMOS?)

● Si + impurity

acceptors(p-type) donors (n-type)

● p-type + n-type => pn junction (I-V)

3.1.1 (Wafer)
● Wafer = A disk of silicon (0.25 mm - 1 mm thick), (75 mm to 230 mm in diameters) ● Czochralski method (Fig.3.1) - Crucible:甘堝 - Ingot:鑄塊,錠 ● Controlled amount of impurities are added to the melt to provide the crystal with the required electrical properties.

3.1.2 Oxidation (produce SiO2)
● Oxidation of silicon is achieved by heating silicon wafer in an oxidizing atmosphere such as oxygen or water vapor. A. Wet Oxidation : Water Vapor -> rapid process (900º-1000ºc) B. Dry Oxidation : pure oxygen -> slow process (1200ºc) ● SiO2 layer grows almost equally in both vertical directions. ● Check “SiO2” (field oxide) in Fig3.2


Diffusion : at temp. 2 . patterning "windows" in a mask material on the surface of the wafer 2.3. forming regions with varying doping concentration. > 800ºc Impurities will diffuse from areas of high concentration to area of low concentration.Function : form a barrier against doping impurities (selective diffusion) very important!! steps 1. The polymerized areas may be removed with an organic solvent.Time and temperature of “deposition” and “diffusion”. 3. 2. A.1.The injected impurities will travel below the surface of the Si. B. Use a acid resistant coating (photoresist)(PR) which can be polymerized by ultraviolet (UV) light. ● Mask: Implantation occurs/not occurs Deposition .3 Epitaxy. Deposition : Evaporate dopant material onto the silicon surface followed by a thermal cycle (to drive the impurity from the Si surface into the bulk) C.silicon Nitride (Si3N4) (SiN) . phosphorous : donors ● Amount is controlled by 1. Ion-implantation.remove any undesired mask materials.Common materials used as masks include: 1. polysilicon (polycrystalline silicon) 3. Deposition. silicon dioxide (SiO2) 4. Epitaxy (長晶): grow a single crystal film on the silicon surface. B. ● SiO2 is removed using an etching technique. D. and Diffusion ● To generate silicon that contains varying portions of donor or acceptor impurities. photoresist 2. =>It's important once the doped areas have been put in place. A. ● Impurities: Boron : acceptors Arsenic.energy and time of “Ion implantation”. to keep the remaining process steps at as low a temperature as possible. Ion implantation : subject the Si substrate to highly energized donor or acceptor atoms. subjecting exposed areas to a dopant source.

*Note diffraction around the edges of the mask patterns (= 0. Etching of exposed SiO2 then may proceed. precise) Electron beam lithography (EBL) (watch Fig.3) 3 .8um) *Alternative approach : (high cost. A-B-C "Positive resist" "Negative resist" = unexposed PR is dissolved by the solvent.C.3.

1.4 Silicon gate process ● Si -> Single-crystal form Poly crystalline form (polysilicon) Polysilicon is used as interconnect wires in silicon IC's and as the gate electrode on MOS transistors. in CMOS. => Can be used as the "mask" for drain & source ● Polysilicon is formed when silicon is deposited on SiO2 or other surfaces. For example. 4 . undoped polysilicon is deposited on the gate insulator.3.

3.SiO2 1. 2. Gate-oxide (thinox) Field-oxide (thick) Self-aligned process (source & drain donor extend over the gate) "Field device" or "Parasitic MOS transistors" 5 . 4.

6 & Fig.1 Basic n-well CMOS process 1.3. Silicon-on-insulator (SOI) 3. Twin-tub process 4. Create the n-type well for the p-channel device. 3. n-well process 2.2 CMOS Process Technology 1. Start with a lightly doped p-type substrate (wafer) 2. p-well process 3. Build the n-channel transistor in the "native" p-substrate (watch Fig.3.2.7) 4.3. CMOS process and layout drawing conventions 6 .

n-well-shallow is better n-well. n-tub (for p-device) Grow SiO2/SiN Channel-stop implant : prevent conduction between unrelated transistor ←Grow field oxide (LOCOS) (bird’s break)→smaller L ←adjust threshold voltage ←add polysilicon etch 7 .

N+ mask (self-aligned by poly) Light-Doped Drain (LDD) P+ mask (LDD is not required) Grow SiO2 Etch SiO2 (Define contact cut) Add metal (circuit connectivity) 8 .

body ties. "body effect".Place p+ region in the p-type substrate (Vss contacts) ● p-well process 1. tub ties) 1. and the "gain" of n.● Substrate contact (well contacts.n-well <-> p-well in process 3.n-well process is more popular in recent years (p-well process is popular in the past) 2. 9 . p devices independently. Make it possible to optimize "Vt".The device in the substrate has better characteristics -> p-well process has better p devices than the n devices -> note p-devices have lower gain than the n devices -> n-well process exacerbates the difference <-> p-well process balance the diffusion ● Twin-tub CMOS process 1.Place n+ region in the n-well (VDD contacts) 2. Provide separate optimization of the n-type and p-type transistors 2.

3. With accurately determined dopant concentrations c.3. Epitaxy" a. Electrical properties are determined by the dopant and its concentration in Si C. Metallization ● Balanced performance of n. Steps: A. Starting material: an n+ or p+ substrate with lightly doped . Source & drain implantations d."epitaxial" or "epi" layer -> to protect "latch up" B. Thin-Oxide construction c. Process sequence a.10) 10 . Contact cut definition e. (substrate contacts are included in Fig. Grow high-purity silicon layers of controlled thickness b. Tub formation b. p – devices can be constructed.

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