Chapter 3 CMOS processing technology
(How to make a CMOS?)
● Si + impurity
acceptors(p-type) donors (n-type)
● p-type + n-type => pn junction (I-V)
● Wafer = A disk of silicon (0.25 mm - 1 mm thick), (75 mm to 230 mm in diameters) ● Czochralski method (Fig.3.1) - Crucible:甘堝 - Ingot:鑄塊，錠 ● Controlled amount of impurities are added to the melt to provide the crystal with the required electrical properties.
3.1.2 Oxidation (produce SiO2)
● Oxidation of silicon is achieved by heating silicon wafer in an oxidizing atmosphere such as oxygen or water vapor. A. Wet Oxidation : Water Vapor -> rapid process (900º-1000ºc) B. Dry Oxidation : pure oxygen -> slow process (1200ºc) ● SiO2 layer grows almost equally in both vertical directions. ● Check “SiO2” (field oxide) in Fig3.2
Epitaxy (長晶): grow a single crystal film on the silicon surface. phosphorous : donors ● Amount is controlled by 1. subjecting exposed areas to a dopant source.silicon Nitride (Si3N4) (SiN) . and Diffusion
● To generate silicon that contains varying portions of donor or acceptor impurities. Deposition : Evaporate dopant material onto the silicon surface followed by a thermal cycle (to drive the impurity from the Si surface into the bulk) C. The polymerized areas may be removed with an organic solvent. > 800ºc Impurities will diffuse from areas of high concentration to area of low concentration. B. to keep the remaining process steps at as low a temperature as possible.1.3. silicon dioxide (SiO2) 4. A. =>It's important once the doped areas have been put in place. Diffusion : at temp. 3. Use a acid resistant coating (photoresist)(PR) which can be polymerized by ultraviolet (UV) light. ● Mask: Implantation occurs/not occurs Deposition . Ion implantation : subject the Si substrate to highly energized donor or acceptor atoms.
. D.Common materials used as masks include: 1. Ion-implantation. 2. patterning "windows" in a mask material on the surface of the wafer 2.Function : form a barrier against doping impurities (selective diffusion) very important!! steps 1.energy and time of “Ion implantation”. polysilicon (polycrystalline silicon) 3. ● SiO2 is removed using an etching technique. A. forming regions with varying doping concentration.Time and temperature of “deposition” and “diffusion”. B. Deposition.remove any undesired mask materials. ● Impurities: Boron : acceptors Arsenic.The injected impurities will travel below the surface of the Si. photoresist 2.3 Epitaxy.
*Note diffraction around the edges of the mask patterns (= 0.C. A-B-C "Positive resist" "Negative resist" = unexposed PR is dissolved by the solvent.3)
. Etching of exposed SiO2 then may proceed.8um) *Alternative approach : (high cost.3. precise) Electron beam lithography (EBL) (watch Fig.
. in CMOS. For example.1.4 Silicon gate process
● Si -> Single-crystal form Poly crystalline form (polysilicon) Polysilicon is used as interconnect wires in silicon IC's and as the gate electrode on MOS transistors. undoped polysilicon is deposited on the gate insulator.3. => Can be used as the "mask" for drain & source ● Polysilicon is formed when silicon is deposited on SiO2 or other surfaces.
4. 3. Gate-oxide (thinox) Field-oxide (thick) Self-aligned process (source & drain donor extend over the gate) "Field device" or "Parasitic MOS transistors"
3. Create the n-type well for the p-channel device. 3. Start with a lightly doped p-type substrate (wafer) 2.3. Build the n-channel transistor in the "native" p-substrate (watch Fig.6 & Fig.2. n-well process 2.7) 4.3.1 Basic n-well CMOS process
1. Twin-tub process 4.2 CMOS Process Technology
1. p-well process 3.3. CMOS process and layout drawing conventions
n-well-shallow is better n-well. n-tub (for p-device)
Channel-stop implant : prevent conduction between unrelated transistor
←Grow field oxide
(LOCOS) (bird’s break)→smaller L ←adjust threshold voltage
←add polysilicon etch
N+ mask (self-aligned by poly)
Light-Doped Drain (LDD)
P+ mask (LDD is not required)
Grow SiO2 Etch SiO2 (Define contact cut)
Add metal (circuit connectivity)
Place n+ region in the n-well (VDD contacts) 2.
.Place p+ region in the p-type substrate (Vss contacts)
● p-well process 1.The device in the substrate has better characteristics -> p-well process has better p devices than the n devices -> note p-devices have lower gain than the n devices -> n-well process exacerbates the difference <-> p-well process balance the diffusion
● Twin-tub CMOS process
1. Make it possible to optimize "Vt".● Substrate contact (well contacts. "body effect". and the "gain" of n.n-well <-> p-well in process 3. p devices independently.n-well process is more popular in recent years (p-well process is popular in the past) 2. tub ties) 1. Provide separate optimization of the n-type and p-type transistors 2. body ties.
. Contact cut definition e. p – devices can be constructed. Metallization ● Balanced performance of n. Process sequence a. (substrate contacts are included in Fig. Source & drain implantations d."epitaxial" or "epi" layer -> to protect "latch up" B. Grow high-purity silicon layers of controlled thickness b. Electrical properties are determined by the dopant and its concentration in Si C. Thin-Oxide construction c.3. With accurately determined dopant concentrations c. Tub formation b. Starting material: an n+ or p+ substrate with lightly doped .3. Epitaxy" a.