# 4-Bit ALU

Specifications
Functionality: AND, OR , XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 µm ×400µm

Prepared by: Christie Ma, Manjul Mishra, Ka Yung Presented to : Dr. David Parent Date: 7th May, 2003

1

Highlights
• Introduction- How does the circuit work • Approach for the design • Individual blocks – AND gate, OR gate, XOR gate, Full Adder, and 4-to-1 MUX • Wiring of 1-bit and 4-bit ALU • Verification of functionality – test vectors • Post extracted simulation with propagation delay • Power consumption • Conclusions

2

Circuit Functionality
S1
A0 B0 A0 B0

S0

A0 B0
A0 B0 C0

4:1 MUX

F0
Control signal S1 S0 Operation

Block diagram for 1-bit ALU

0

0

A and B

0 1 1

1 0 1

A or B A xor B A add B
3

Block Diagram for 4-Bit ALU
S1 S0

A0 B0 C0
A1 B1

1-bit ALU
Cout0

F0

1-bit ALU
Cout1

F1

A2 B2

1-bit ALU
Cout2

F2

A3 B3

1-bit ALU
Cout3

F3

4

Design Flow
Sketch schematic according to Boolean Algebra Find Euler Path Draw stick diagram Verify functionality Calculate Wn Wp for each block Run DRC, LVS, extracted simulation for 4-bit ALU Measure power used

Measure delay time

Run Spice simulation to fix Wn, Wp
Draw schematic for each block Layout for small blocks Route four 1-bit ALUs to form a 4-bit ALU Run DRC, LVS, extracted simulation for 1-bit ALU

Run DRC, LVS, extracted simulation for small blocks Route small blocks together to form 1-bit ALU
5

AND2 schematic Wp=5.15 m 6 .4 m Wn=15.

AND2 Layout & LVS Report 7 .

85 m Wn=10.OR2 Schematic Wp=8.4m Wp=5.25 m 8 .2 m Wn=14.

OR2 Layout & LVS Report 9 .

10 Wn=23.XOR2 Schematic Wp=15. using one AOI21 and one NOR gate.9m Y = A xor B = AB’ + A’B = (AB + A’B’)’ AOI21 = (AB + C)’ if C = A’B’ C = (A+B)’ C = A nor B Therefore.4m . we can implement XOR gate without using any INV.

XOR2 Layout & LVS 11 .

Full Adder Schematic Cout=AB+ACin+ BCin = AB+Cin(A+B) Sum= ABCin + (A+B+Cin)Cout’ Wp=6.15m Wn=3.6m 12 .

Full Adder LVS Report 14 .

4-to-1 MUX schematic F0= S1’ S0’Y00+ S1’S0Y01 +S1S0’Y10+S1S0Y11 F0= S0’(S1’Y00+S1Y10)+S0(S1’Y01+S1Y11) Wp=9.9 m 2-to-1 MUX 2-to-1 MUX 2-to-1 MUX Therefore. we need three 2-to-1MUXs to build a 4-to-1 MUX 2-to-1 MUX schematic Wn=6.45 m 15 .

4-to-1 MUX schematic (cont.) 16 .

4-to-1 MUX Layout 3 One 2-to-1 MUX Three 2-to-1 MUXs to form a 4-to-1MUX 17 .

4-to-1 MUX LVS Report 18 .

1-bit ALU schematic 19 .

1-bit ALU Layout AND OR XOR ADDER 4-to-1 MUX 20 .

1-bit ALU LVS Report 21 .

4-bit ALU Schematic 22 .

4-bit ALU Layout Area = 197m  347.4 m 23 .

4-bit ALU LVS Report 24 .

Test Vectors • Walking ones for inputs on all operations (1-8) • Testing for Cout and Cin (9. 10) 25 .

Ax = 0.Simulation Results A3 = 1. Bx = 0 26 .

Ax = 0.Simulation Results A2 = 1. Bx = 0 27 .

Simulation Results A1 = 1. Bx = 0 28 . Ax = 0.

Ax = 0. Bx = 0 29 .Simulation Results A0 = 1.

Simulation Results B3 = 1. Bx = 0 30 . Ax = 0.

Ax = 0. Bx = 0 31 .Simulation Results B2 = 1.

Simulation Results B1 = 1. Bx = 0 32 . Ax = 0.

Ax = 0. Bx = 0 33 .Simulation Results B0 = 1.

Simulation Results (Cout) A3 = 1. B3 = 1 34 .

B0 =1 35 . A0 =1.Simulation Results (Cin) C0 = 1.

1ps 36 .Propagation Delay for AND gate 274.

Propagation Delay for OR gate 237.9 ps 37 .

Propagation Delay for XOR gate 226.7ps 38 .

Propagation Delay for Full Adder 39 495.5 ps .

4 ps 40 .Propagation Delay for 4-to-1 MUX 330.

Propagation Delay For 4-bit ALU (when S1=S0=0 AND Operation) t F2 = 705.2ps 41 .9ps t F3 = 698.

S0=1 OR Operation) t F2 = 693.Propagation delay For 4-bit ALU ( when S1=0.8 ps t F3 = 673.2 ps 42 .

Propagation Delay for 4-bit ALU (when S1=1.7 ps 43 .2 ps t F3 = 678. S0=0 XOR Operation) t F2 = 661.

Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation) t F0 = 987.383 ns 44 .9 ps t F1 = 1.

949 ns 45 .Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation) t F2= 1.484 ns t F3 = 1.

Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation) t Cout3 = 1.339 ns 46 .

Power Simulation for 4-bit ALU (when S1=S0=0 AND Operation) Power = 26.8 mW 47 .

S0=1 OR Operation) Power = 26.69 mW 48 .Power Simulation For 4-bit ALU ( when S1=0.

S0=0 XOR Operation) Power = 21.38mW 49 .Power Simulation for 4-bit ALU (when S1=1.

Power Simulation for 4-bit ALU (when S1=S0=1 Add Operation) Power = 23.35mW 50 .

0 ns 30 mW 200 µm ×400µm Our circuit 1.4µm 51 .95ns 26.8 mW 197 µm ×347.Conclusions • We meet the specifications! Specifications Largest Propagation delay Maximum Power Area 2.