2011 Texas Instrements Placement Paper - Electronics:1. (steeper transition) by: 1. Increasing W/L of PMOS transistor 2. Increasing W/L of NMOS transistor 3.

Increasing W/L of both transistors by the same factor 4. Decreasing W/L of both transistor by the same factor 2. Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is 1. 2. 3. 4. 4 5 6 7

3. Consider a two-level memory hierarchy system M1 & M2. M1 is accessed first and on miss M2 is accessed. The access of M1 is 2 nanoseconds and the miss penalty (the time to get the data from M2 in case of a miss) is 100 nanoseconds. The probability that a valid data is found in M1 is 0.97. The average memory access time is: 1. 4.94 nanoseconds 2. 3.06 nanoseconds 3 . 5.00 nanoseconds 4.. 5.06 nanoseconds

4. Interrupt latency is the time elapsed between: 1.Occurrence of an interrupt and its detection by the CPU 2. Assertion of an interrupt and the start of the associated ISR 3. Assertion of an interrupt and the completion of the associated ISR 4. Start and completion of associated ISR 5. Which of the following is true for the function (A.B + A’.C + B.C) 1.This function can glitch and can be further reduced 2. This function can neither glitch nor can be further reduced 3. This function can glitch and cannot be further reduced 4. This function cannot glitch but can be further reduced 6. For the two flip-flop configuration below, what is the relationship of the output at B to the clock frequency?

Addressing mode specification for both source operands 9. the output Yn of any stage N is 1 if the total number of 1s at the inputs starting from the first stage to the Nth stage is odd. One NOR gate and one NAND gate 3. 3 register operands 4. If each net can be stuck-at either values 0 and 1. What is the instruction op-code length in bits? 32 24 30 36 10. with 50% duty cycle 3. 0 2. The optimal logic structure for the box consists of: 1. Output frequency is 1/4th the clock frequency. and such that up-to all nets in it can be faulty? 1. The CPU has 16 registers and supports 5 addressing modes. N and 2^N 3. in how many ways can the circuit be faulty such that only one net in it can be faulty. with 25% duty cycle 4. The voltage on Node B is: 1.1.One AND gate and one NOR gate 2.Consider a circuit with N logic nets. Output frequency is 1/4th the clock frequency.2 and 2N 2. –10 8. One XOR gate 11. with 50% duty cycle 2. The instruction type (one among 250) 2. Each instruction op-code has these fields: 1. Output frequency is 1/3rd the clock frequency. Output frequency is equal to the clock frequency 7. (Each identical box in the iterative network has two inputs and two outputs). Two XNOR gates 4. In the iterative network shown. 10 3. A conditional register specification 3.A CPU supports 250 instructions. 2N and 3^N-1 .

This scheme is called the M-out-of-N coding scheme. II only 14. I3 and I4.I1-start---I2-start---I2-end---I4-start---I3-start---I3-end---I4-end---I1-end From this sequence. If the set-up time is 2 ns. and N=8. c.A CPU supports 4 interrupts. Close to 70% 4. what is the maximum frequency of operation for the circuit? a. 1. Combinational circuits may have feedback. consider that the number of unique words represent able in the latter representation with N bits is 2^N. 2N and 3N 12.I1. b. Close to 50% 3. In the circuit shown. Combinational circuits have a ‘memory-less’ property. I2 > I1. III. d. Both combinational and sequential circuits must be controlled by an external clock. all the flip-flops are identical. I and II only 4. If M=N/2.4. what can we infer about the interrupt routines? 1. we observe the following sequence of entry into and exit from the interrupt service routine: 1. sequential circuits do not. clock->Q delay is 3 ns and hold time is 1 ns. Which of the following statements is/are true? I. I2. in a word of N bits. I4 > I3 > I2 > I1 3. I3 > I4 > I1 . I3 > I4 > I2 > I1 2. II and III only 3. Close to 100% 15. what is the efficiency of this coding scheme as against the regular binary number representation scheme? (As a hint. sequential circuits do not. II.Consider an alternate binary number representation scheme. I only 2. wherein the number of ones M.Close to 30% 2. is always the same. It supports priority of interrupts. Hence the efficiency is 100%) 1. During a certain period of time. Nested interrupts are allowed if later interrupt is higher priority than previous one. 200 MHz 333 MHz 250 MHz None of the above 13.

For the circuit shown below. 3-input NAND 19. then what is the wattage required for the heating element? [Assume: Boiling point of water is 100 C. He begins running in the direction of the train and the only other open door in his train is located 50 mts behind the door from where he jumped. Data given is insufficient 2. and an output of double the frequency (function F2). I decide to build myself a small electric kettle to boil my cup of tea. (but does not halt) at a small wayside station that has a 100 mts long platform. I2 > I1.The athletics team from REC Trichy is traveling by train. The train slows down. 5 m/s 4. 10 m/s 18. He is now just 50 mts from the other end of the platform where the train is moving out. Data given is insufficient 2. He jumps out just as his compartment enters the platform and spends 5 secs buying his newspaper that is at the point where he jumped out. 300 W 4. He spends another 5 secs buying the idlis. 2-input AND + 2-input OR 2. 800 W 3. . 2-input XOR + inverter 4.Make the following assumptions *He always runs at his peak speed uniformly * The train travels at uniform speed * He does not wait (other than for the idlis & newspaper) or run baclwards 1.4. He then sprints along the platform to buy idlis that is another 50 mts. 1000 W 5. 1 Calorie (heat required to change 1 gm of water by 1 C)= 4 joules. 250 W 17.4 m/s 3. so that it produces an output of the same frequency (function F1). 1 ml of water weighs 1 gm. what should the function F be. Assuming that typical tap water temperature is 25 C and I want the water boiling in exactly one minute. 2-to-1 multiplexer 3. I need 200 ml of water for my cup of tea. At what(uniform) speed should the train be traveled if he just misses jumping into the open door at the very edge of the platform? 1.5 m/s 5. 7.] 1. The sprinter (who can run 100 mts in 10 sec) decides to jump down and get a newspaper and some idlis.State which of the following gate combinations does not form a universal logic set: 1. I3 > I4 > I2 > I1 16.

c. b. In the circuit given below. None of the above 20. 2V 2. the output depends on the present state as well as the inputs. It is a Moor machine with three states 21. y= ! (b+ac) 2.What is the functionality represented by the following circuit? 1.The value (0xdeadbeef) needs to stored at address 0x400. the switch is opened at time t=0. F1=AND gate and F2=XOR gate 4. For a Moore FSM. FSMs have a few characteristics. y= ! (a(b+c)) 4. Voltage across the capacitor at t=infinity is: 1. An autonomous FSM has no inputs.The information available is insufficient 3. It has two states and is autonomous 2. 5V 4.1. d. y= ! (a+bc) 3. For a Mealy FSM. be ef fe ed ef be eb da de ad da eb ad de ed fe . It is a Mealy machine with three states 4. 7V 22. Which of the statements best describes the FSM below? 1. and detects a particular sequence of inputs leading it to state Sc. which is the reset state.F1=NAND gate and F2= AND gate 3. y= ! (a+b+c) 23. the output depends on the present state alone. 3V 3. F1= NOR gate and F2= OR gate 2. Which of the below ways will the memory look like in a big endian machine: 0x403 0x402 0x401 0x400 a.The FSM (finite state machine) below starts in state Sa.

A write operation followed by a read operation in the next cycle. 2 2. 3. In a given CPU-memory sub-system. Accesses to memories in two consecutive cycles can therefore result in incorrect data transfer. Which of the following access mechanisms guarantees correct data transfer? 1. 6 3. } 1. return(fib(n-1) + fib(n-2)). all accesses to the memory take two cycles. None of the above 25. Save of each registers costs 1 cycle (so does restore).The maximum number of unique Boolean functions F(A. realizable for a two input (A. 120 2.B).24. A NOP between every successive reads & writes 4. 8 Category SubCategory Location Company IT Placement Papers Bangalore Texas Instruments . 2.An architecture saves 4 control registers automatically on function entry (and restores them on function return).B) and single output (Z) circuit is: 1.Void fib(int n) { if((n==0) || (n==1)) return 1. How many cycles are spent in these tasks (save and restore) while running the following un-optimized code with n=5: 1. A read operation followed by a write operation in the next cycle. 125 4. 80 3. 128 26.TI .

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