07TC551

USN R. V. COLLEGE OF ENGINEERING
Autonomous Institution under VTU V Semester B. E. Examinations Dec-09/Jan-10 Telecommunication Engineering

COMPUTER ORGANIZATION AND ARCHITECTURE
Time: 03 Hours Maximum Marks: 100 Instructions to candidates: Answer any Five full Questions by selecting Three questions from Part-A and Two questions from Part-B.

8 b Using Booth’s algorithm find the product of -13 and +11. 0 8 3 a Describe in detail the interrupt hardware with neat diagram and also 1 explain the enabling and disabling of interrupt. 0 8 c Explain the Sequential binary multiplier with the help of a block 0 diagram. b Describe the different modes of addressing with examples. 0 b Explain in detail the magnetic hard disc with neat diagram. 2 b What is DMA? Explain DMA controller with suitable diagram. 0 6 c Write a note on non-restoring algorithm 0 6 7 a Describe in detail the floating point arithmetic 0 6 b Explain in detail the hard wired control logic with neat diagram.A 1 a Explain the functional units of a Computer with a neat diagram. b Write short notes on i) INTEL Processor ii) Motorola Processor . 6 1 0 1 0 8 a Explain the concept of micro programmed control unit. 1 0 PART –B 6 a Design a carry look ahead adder and explain its operation with neat 0 diagram. b Explain the Virtual memory address translation with neat diagram. 0 8 0 6 0 6 5 a What is Interleaving? Describe the types of interleaving with neat 1 diagrams. c Distinguish between i) Pipelining and Superscalar ii) CISC and RISC 0 6 0 6 0 8 2 a Explain i) Byte addressability 0 ii) Big endian assignment 6 iii) Little endian assignment b What is the difference between a subroutine and Interrupt service 0 routine? 6 c Describe in detail the stack frame with suitable diagram. c Describe the Synchronous and Asynchronous DRAMS. 0 8 4 a Describe the Cache and its mapping functions with suitable diagram.PART.

Sign up to vote on this title
UsefulNot useful