This action might not be possible to undo. Are you sure you want to continue?

# LIST OF EXPERIMENTS AS PER VTU SYLLABUS

1. Wiring of RC coupled Single stage FET & BJT amplifier and determination of the gain, Frequency response, input and out put impedances. 2. Wiring of BJT Darlington Emitter follower with and without bootstrapping and Determination of the gain, input and output impedances (Single circuit) (One Experiment). 3. Wiring of a two stage BJT Voltage series feed back amplifier and determination of the Gain, frequency response, input and output impedances with and without feedback (One Experiment). 4. Wiring and Testing for the performance of BJT-RC Phase shift Oscillator for f0 <= 10 KHz 5. Testing for the performance of BJT-Hartley & Colpitts Oscillators for RF range f0>=100 KHz. 6. Testing for the performance of BJT -Crystal Oscillator for f0 > 100 KHz. 7. Diode clipping (Single/Double ended) circuits for peak clipping, peak detection 8. Testing of Clamping circuits: positive clamping /negative clamping. 9. Testing of a transformer less Class - B push pull power amplifier and determination of its Conversion efficiency. 10. Testing of Half wave, Full wave and Bridge Rectifier circuits with and without Capacitor Filter. Determination of ripple factor, regulation and efficiency. 11. Verification of Thevinin‘s Theorem and Maximum Power Transfer theorem for DC Circuits. 12. Characteristics of Series and Parallel resonant circuits.

1

CYCLE OF EXPERIMENTS

CYCLE - I 1. Testing of diode clipping circuits for single ended positive & negative clipping (Series /Parallel). a) Peak clipping. b) Peak voltage detection a) Testing of Double ended clipping: i) Symmetric. ii) Clipping at two independent levels. b) Testing of clamping circuits: i) Positive clamping. ii) Negative clamping Testing of Rectifier circuit: determine ripple factor, regulation, efficiency for a Half wave rectifier with and without filter. Verification of Thevinin’s Theorem and Maximum Power Transfer theorem for DC circuits. CYCLE - II 5. 6. 7. 8 9 Wiring of RC coupled single stage amplifier & determine the gain, frequency response, input & output impedances (With BJT or FET) Testing of Rectifier circuit : determine ripple factor, regulation, efficiency for Full wave center tapped rectifier with and without filter Testing of Rectifier circuit: determine ripple factor, regulation, efficiency for Full wave bridge rectifier with and without filter. Wiring of BJT Darlington Emitter follower & determine the gain, input & output impedances without bootstrapping Wiring of BJT Darlington Emitter follower & determine the gain, input & output impedances With bootstrapping CYCLE - III 10 11. Characteristics of resonant circuits :-> a) Series resonant. b) Parallel resonant Wiring & testing for the performance of BJT-RC phase shift oscillator for range f0 <= 10kHz

2. 3. 4.

12.

Wiring & testing for the performance of Oscillator for RF oscillator for RF range f0 >= 100kHz. a) Hartley oscillator. b) Colpitts oscillator. Testing for the performance of BJT – crystal oscillator for f0 > 100kHz.

13

2

CYCLE - IV 14 Wiring of a two stage BJT voltage series feedback amplifier and determine the gain, frequency response, input & output impedances .a) With the Feedback. b) without the feedback. Testing of a transformer less Class –B push pull amplifier and determine its conversion efficiency.

15

3

EXPERIMENT: 1 DIODE CLIPPING CIRCUITS AIM: Testing of diode clipping circuits for single ended positive & negative clipping (Series /Parallel (Shunt)). a) Peak clipping. b) Peak voltage detection APPARATUS REQUIRED: Power supply (0- 30V), Signal Generator, CRO, Diode: BY127/IN4007 and resistor (10kΩ). THEORY: Clippers are networks that employ diodes to clip away portions of an input signal without distorting the remaining part of the applied waveform. These clipper circuits transfer a selected portion of the input waveform to the output. Diode clipping circuits are used to prevent a wave form from exceeding some particular limit either negative or positive or both. This is achieved by connecting the diode in serial or in parallel circuit. Variable DC voltage is connected in the circuit to achieve required level of clipping. By using different level DC voltages, it is possible to get different level of clipping in positive and negative side. These clipper circuits are also called as limiters. Following are few types of clipper circuits 1. Single ended (positive or negative ) and double ended clipping 2. Series or parallel based on the construction. a) PEAK CLIPPING CIRCUIT (DIODE SHUNT CLIPPING) Case 1: Positive peak Clipper Circuit diagram Input and output waveform Transfer characteristics

Case 2: Negative peak clipper Circuit diagram

Input and output waveform

Transfer characteristics

4

2. Let the output voltage be clipped to say -3V. PROCEDURE: 1. internal resistance of diode : .4v. To get the transfer characteristics: Connect the input wave to X-channel & output wave to the Y-channel . R = √ (10x 10 x106 ) =10 kΩ.Vref= . b) PEAK VOLTAGE DETECTION (DIODE SHUNT DETECTION) Case 1: Positive peak detection Circuit diagram Input and output waveform Transfer characteristics 5 . Switch on the signal generator and measure the voltage of 10V p-p sine wave with frequency 1 kHz using CRO.6V Therefore Vref= Vo (Max) – Vf =2.e. Connect input from signal generator and output should be connected to CRO (select DC knob) 4. Rig up the circuit as shown in the diagram 3. Vo (Max)=Vref +Vf. The value of resistor(R) is chosen for all cases as. 5.R =√(Rf x Rr) Where Rf = diode forward resistance. Note: For Case 2 only the sign of the Vref changes i. Vo (Max) = +3V.4v.2.then select X-Y mode on the CRO. Compare input & output wave form for the designed value of clipping and draw it on the tracing sheet.DESIGN: For case 1. Where Vf=Knee voltage for silicon diode is 0. Let the output voltage be clipped to say +3V. Vo (Min) = -Vref -Vf. 10 ohms. Vo (Min) = -3V. Rr = 10MΩ.take the same on the tracing sheet.

Case 2: Negative peak detection Circuit diagram Input and output waveform Transfer characteristics Note: Design and Procedure is same as previous RESULT: The clipper circuits are tested for out put wave form and transfer characteristics are matching with the expected ones with respect to the designed value of clipping for different cases. (Signature of the Staff with Date) 6 .

CRO.R =√(Rf x Rr) Where Rf = diode forward resistance.2. CIRCUIT DIAGRAM: a) DOUBLE ENDED CLIPPING Case i) Symmetric Circuit diagram Input and output waveform Transfer characteristics DESIGN: Let the output voltage be clipped to say +/-3V. diode: BY127/IN4007. R = √ (10x 10 x106 ) =10 kΩ.Clamper is a circuit that "shifts" a signal to a different dc level without changing the appearance of the applied signal The different types of clampers are positive negative and biased clampers A clamping network must have a capacitor. Vref2= .4v. 7 . internal resistance of diode : . THEORY (for clamping) :. the level of swing can be varied.EXPERIMENT: 2 DIODE CLIPPING & CLAMPING CIRCUITS AIM: a) Testing of Double ended clipping: i) Symmetric.4v The value of resistor(R) is chosen for all cases as. ii) Clipping at two independent levels. 10 ohms. Where Vf=Knee voltage for silicon diode is 0.6V Therefore Vref1= Vo (Max) – Vf = +2.30V).conducting. By connecting suitable DC voltage in series with the diode. Vo (Min) = -Vref2-Vf.i. resistor of 10kΩ and capacitor of 1µF. Rr = 10MΩ.Vo (Max) = +3V & Vo (Min) = -3V. APPARATUS REQUIRED: Power supply (0. The magnitude R and C must be chosen such that the time constant RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval the diode is non.. Vo (Max)=Vref1 +Vf. b) Testing of clamping circuits:-Positive clamping & Negative clamping. Signal Generator.e.. a diode and a resistive element.

6V Therefore Vref1= Vo (Max) – Vf = 3. i.Case ii) Clipping at two independent levels Circuit diagram Input and output waveform Transfer characteristics DESIGN: Let the output voltage be clipped to say +4v and +2v.Vo (Max) = +4V . FOR EXERCISE: Circuit diagram Input and output waveform Transfer characteristics 8 . Where Vf=Knee voltage for silicon diode is 0.e. Vref2=2.4v To find Vref2: Vo (Min) = Vref2 -Vf :.6 v Note: Procedure for both cases is similar as experiment 1. Vo (Min) = +2V Vo (Max)=Vref1 +Vf.

6 for silicon diode Vref=3.6 for silicon diode Then. 2. Switch on the signal generator and measure the voltage of 10V p-p sine wave with frequency 1 kHz using CRO. Rig up the circuit as shown in the diagram 3. where Vf is knee voltage = 0. Vo = Vref + Vf.6v Case ii) Negative clamping Circuit diagram Input and output waveform DESIGN: Suppose if the output has to clamp for Vo= -3V From the circuit. Vref= -3.6v PROCEDURE :( same for both cases) 1.b) CLAMPING CIRCUITS Case i) Positive clamping Circuit diagram Input and output waveform DESIGN: Suppose if the output has to clamp for Vo=+3V Then Vo =Vref – Vf. RESULT: The theoretical design values are matching to practical waveforms (Signature of the Staff with Date) 9 . Connect input from signal generator and output should be connected to CRO (select DC knob) 4. where Vf is knee voltage = 0. Compare input & output wave form for the designed value of clamping and draw it on the tracing sheet.

efficiency for a Half wave rectifier with and without filter. Diode (BY 127) and capacitor. CIRCUIT DIAGRAM : Input and output waveform 10 . THEORY: Rectifier is a device which converts Ac signal to DC signal. thus the diode acts as a switch and the source voltage appears across the load resistor. The half wave rectifier with filter can be used for Peak detection. In half.wave rectification. Ammeter (0 to 100mA). APPARATUS REQUIRED: Transformer (TR: 12-0-12). Fullwave rectifier with centre tap transformer and Fall wave bridge rectifier. the rectifier or diode conducts current only during the positive/negative half cycles of the ac input supply. There are three types: Half wave rectifier. CRO. Therefore current always flows in one direction in a half wave rectifier. Resistors. regulation. Voltmeter (0 to 25V).EXPERIMENT: 3 HALFWAVE RECTIFIER CIRCUIT AIM: Testing of Rectifier circuit: determine ripple factor.

Vo(dc) = Average value of dc output Vo(ac) = rms value of ac component of the output voltage Ripple factor.7/√2 =11.DESIGN: Vin(ac) = rms value of input(secondary of the transformer).1V Use 12v-0-12v transformer( Connect two end terminals of transformer secondary) Let Idc =100mA So RL =5V/100mA =50 Ω/5 Watts With Filter: Vdc = Vm .Vr(p-p)/2 Let Ripple factor. r = rms value of ac component / Value of dc component = Vo(ac)/Vo(dc) % Efficiency η = output power /Input power =Idc2 * 100 /( Iac2+ Idc2)) % Regulation = [(Vnl –Vfl)/Vfl]*100 Find Vin (ac) (Transformer secondary voltage) Let Vo(dc) = 5V dc Vm = Vo(dc) x π = 15.7V Vin(ac rms) = Vm/√2 = 15.2456) = 470 µF TABULAR COLUMN: With out C-filter Vnl = V (With load RL removed). Vfl = V (With load RL at maximum) (If requires. reduce RL to limit Idc to 100mA) % Regulation = Ripple = Vo(ac)/Vo(dc) Efficiency = Idc2 / ( Iac2 + Idc2) (RL+DRB)Ω 50 +20 50 +40 Iac(mA) Idc(mA) Vo(dc) Vo(ac ) 11 . r = 0.2456 r = 1 / (2 x√3 f x RL x C) C = 1/ (2 x√3 f x RL x r) =1/ (2 x√3 x 50 x 50x 0.

now we can calculate regulation using the formula % Regulation = [(Vnl –Vfl)/Vfl]*100 5.Vfl.Vnl. Note down readings as in the tabular column for different values of output resistor (RL) and find out ripple factor and efficiency.e. RESULT: Parameter Ripple Factor Regulation Efficiency Theoretical value With ‘C’ Without ‘C’ 0.note down the output DC voltage i.2456 1. Switch on the input ac signal and connect the output to CRO. put the designed value of RL=50Ω .21 40. Rig up the circuit as shown in the diagram 2.With C-filter (RL+DRB)Ω (50 + 0 )Ω Ripple = Vo(ac)/Vo(dc) Efficiency = Idc2 / ( Iac2 + Idc2) Iac(mA) Idc(mA) Vo(dc) Vo(ac ) PROCEDURE: 1.note down the output DC voltage i. Repeat the steps 1.Then open the load resistance (RL & DRB) .6 Practical value With ‘C’ Without ‘C’ (Signature of the Staff with Date) 12 . To calculate load regulation. 4.2 & 3 by connecting the suitable capacitor across the load and a separate tabular column should be maintained. take the same on the tracing sheet 3.e.

The Thevenin’s resistance is the resistance seen at output terminal when all the voltage sources are replaced by short and current sources are replaced by open circuit. and the value of R is V divided by the current with the terminals short circuited. A resistance load. The value of V is the open circuit voltage at the terminals. THEORY: Any combination of batteries and resistances with two terminals can be replaced by a single voltage source V and a single series resistor R. The Thevenin’s voltage is the open circuit voltage at output terminal with load disconnected. ammeter and voltmeter. APPARATUS REQUIRED: DC Power Supply (0to 30V). resistors. Maximum power transfer theorem is used to find the value of the load resistance for which there would be maximum amount of power transfer from source to load.EXPERIMENT: 4 THEVININ’S THEOREM & MAXIMUM POWER TRANSFER THEOREM AIM: Verification of Thevinin’s Theorem and Maximum Power Transfer theorem for DC circuits. a) THEVININ’S THEOREM CIRCUIT DIAGRAM: Figure 1: T-network Figure 2: Figure 3: Vth = volts and Rth = Ω Parameter Initial value Final value Vdc Idc 13 . being connected to a DC network. receives maximum power when the load resistance is equal to the internal resistance (Thevenin‘s equivalent resistance) of the source network as seen from the load terminals.

2. note down the value of Vdc and Idc. EXERCISE: Conduct same experiment for π and lattice networks. (Signature of the Staff with Date) 14 . Note down the value of Vdc by removing RL from figure 1.PROCEDURE: 1. Vary the RL (DRB) from 500Ω to 2000Ω in steps of 100 Ω and note down the values of Idc. 3. 3. 2. note down the value of Vdc and Idc. Connect the circuit as in figure 3. 5.that is the value of Vth. (Above procedure holds good for any type of networks) b) MAXIMUM POWER TRANSFER THEOREM CIRCUIT DIAGRAM IDEAL GRAPH: TABULAR COLUMN: RL(Ω) 500 800 1000 1300 1500 1800 2000 2500 Ic(mA) P= RL x Idc2(mW) PROCEDURE: 1. Connect circuit as shown in the figure 1. RESULT: Hence the Thevinins and maximum power transfer theorem is proved. set the DC voltage to10v by measuring through multimeter. 4.calculate the value of Rth=Vdc/Idc. Connect the circuit as in figure 2.these values should match the initial values of Vdc & Idc. Note the initial values of Vdc & Idc from figure 1. Plot the graph of Power v/s RL and indicate the point at which the maximum power transferred at RL=R (source resistance) on the graph. Connect components as shown in the diagram and set the input voltage to 5v.

To fix the boundaries of frequency where the gain is relatively high and constant. frequency response. Signal generator. The multiplier 0. DC power supply (0-30v) and CRO. the gain drops due to increasing reactance of coupling capacitor. Capacitors. This is illustrated in the Ideal graph. The frequency response is a graph of the gain (in decibels) versus the frequency (in logarithmic scale). cut-off. Resistors. medium and high frequency regions. . Since the coupling from one stage to next stage can be achieved by a coupling capacitor followed by a connection to a shunt resistor such amplifiers are called resistance capacitance (RC) coupled amplifiers. the gain drops due to the increased flow of the a. break or half power frequencies. As the frequency increases. COMPONENTS REQUIRED: NPN transistor (SL100).707Amid is chosen to be the voltage gain at the cut-off levels.e. in the high frequency range. band. the capacitive reactance reduces and the gain increases. 0.c signal through CE.EXPERIMENT: 5 RC COUPLED AMPLIFIER AIM: Wiring of RC coupled single stage amplifier & determine the gain. THEORY: In RC coupled amplifier the input capacitor is used to couple the input signal to the base of first transistor. In the low frequency range. CIRCUIT DIAGRAM: 15 . The corresponding frequencies f1 and f2 are generally called the corner. This characteristic can be subdivided into low.input & output impedances (With BJT or FET). source capacitance and emitter capacitor. After this if the frequency is increased further.707 is chosen because at this level the output power is half the mid-band power output. When an ac signal is applied to the input of the first stage it is amplified with a phase reversal by the transistor. i.

07 K Rc =1 K Ω To find R1 & R2: VB=Vbe+VE=0. Xcc1 =1/ (2π*f*Cc1).1 µ F To design: Xcc1 = (Hie||Rb)/10. at f=100 Hz.9v Ib=Ic/ β=0.5Rc)-6-1.2/Ic=1.2 V RE =1.5m =0. CE: Let Xce= RE /10.045mA Assume 10Ib flows thro` R1 & 9Ib flows thro` R2 Then R1=(Vcc-VB)/10Ib=22KΩ and R2=VB/9Ib=4. β=100(SL 100) To find RE : Choose VE=Vcc/10=12/10 =1.Ic=4.2=0 Rc=1.2 V VE=Ie* RE =1.DESIGN: Let Vcc=12 V.2=1.7+1.7 K Ω RE =270 Ω To find Bypass cap.2/4. Cc1=? Xcc2 = (Rc||Rl)/10.Vre=0 12-(4. Xcc2 =1/ (2π*f*Cc2).CE=10/2π*100*270=59 µF micro farad Choose CE =47µF (electrolytic) To find Cc1 and CC2: assume CC1 & CC2= 0. 1/2π*f* CE= RE /10 Therefore.Vce.5 mA.267 K To find RC: Choose Vce=Vcc/2 =12/2=6 V Apply KVL in CE loop: Vcc-(IcRc). Cc2=? TABULAR COLUMN: Vi (P-P) = Frequency (Hz) 100 200 400 500 800 1K 2K 5K 10K 20K 50K 100K 200K 500K 700K 900K 1M Output Voltage(Vo) (P-P) (Volts) volts Voltage Gain= Vo / Vi Gain =20 log (Vo / Vi) dB 16 .

3. Vary the input sine wave frequency from 100 Hz to 1 MHz in suitable steps. by applying Vcc=12v.PROCEDURE: 1.6v as designed. Note down output voltage amplitude at each step using CRO. Connect the circuit as shown above without applying Vin. 2. 17 . 2.keeping Vin same(20mV). check the DC voltage conditions Vce =6v and Vbe =0. 3. IDEAL GRAPH (FREQUENCY RESPONSE): TO FIND INPUT RESISTANCE: PROCEDURE: 1. Measure the sine wave signal of amplitude 20 mV from signal generator using CRO and apply to the circuit.W product from the plot.B. Put the frequency of the input in midband (around 10kHz). Connect a DRB(value should be Zero) in series for the existing RC coupled amplifier circuit as shown above.Plot Gain in dB versus frequency on the semi log graph. the current value of DRB is the Input Resistance. 4. determine Bandwidth and G. Caluculate the gain in decibels (dBs). Increase the value of DRB linearly such that the output voltage should be half of its initial value.note down the value of output voltage.

3. 2. keeping Vin same (20mV). RESULT: Thus the RC Coupled Amplifier has following features. the current value of DRB is the output Resistance. Connect a DRB (value should be maximum) in parallel for the existing RC coupled amplifier circuit as shown above. note down the value of output voltage. Put the frequency of the input in midband (around 10 kHz).TO FIND OUTPUT RESISTANCE: PROCEDURE: 1. Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance value (Signature of the Staff with Date) 18 . Decrease the value of DRB linearly such that the output voltage should be half of its initial value.

EXPERIMENT: 6 FULL WAVE CENTER TAPPED RECTIFIER AIM: Testing of Rectifier circuit: determine ripple factor. the rectified load current flows during both the half cycles. regulation. Because of the center tapping. As a result. efficiency for Full wave center tapped rectifier with and without filter. each of these rectifiers has an input voltage equal to half the secondary voltage. Voltmeter (0 to 25V). Resistors. THEORY: A full wave rectifier is equivalent to two half wave rectifiers. CIRCUIT DIAGRAM: 19 . Diodes (BY 127) and capacitor. Ammeter (0 to 100mA). CRO. APPARATUS REQUIRED: Transformer (TR: 12-0-12). Diode D1 conducts in the positive half cycle and D2 conducts in the negative half cycle.

7/√2 =11. r = 0.1V(12v-0-12v) ( For center tap circuit . connect two end terminals of transformer secondary to anode of the two diodes and consider center tap as ground potential. Vfl = V ( With load RL at maximum) % Regulation = Ripple = Vo(ac)/Vo(dc) Efficiency = Idc2 / ( Iac2 + Idc2) (RL+DRB)Ω 100 + 20 100 + 40 Iac(mA) Idc(mA) Vo(dc) Vo(ac ) 20 . Vo(dc) = Average value of input Vo(ac) = rms value of ac component of the output voltage Ripple factor.0615) = 470 µF TABULAR COLUMN: With out C-filter Vnl = V ( With load RL removed ). Let Idc =100mA Then RL =10V/100mA =100 Ω/10 watts With Filter : Vdc=Vm-Vr(p-p)/2 Let Ripple factor.0615 r = 1 / (4 x√3 f x RL x C) C = 1/ (4 x√3 f x RL x r) =1/ (4 x√3 x 50 x 100x 0. r = rms value of ac component / Value of dc component = Vo(ac)/Vo(dc) % Efficiency η = output power /Input power =Idc2 * 100 /( Iac2+ Idc2)) x100 % Regulation = [(Vnl –Vfl)/Vfl]*100 Find Vin (ac) (Transformer secondary voltage) Let Vo(dc) = 10V dc Vm = Vo(dc) x π/2 = 15.7V Vin(rms) = Vm/√2 = 15.DESIGN: Vin(ac) = rms value of input.

now we can calculate regulation using the formula % Regulation = [(Vnl –Vfl)/Vfl]*100 5.Vfl. RESULT: Parameter Ripple Factor Regulation Efficiency Theoretical value With ‘C’ Without ‘C’ 0.e.e. Repeat the steps 1.With C-filter Ripple = Vo(ac)/Vo(dc) Efficiency = Idc2 / ( Iac2 + Idc2) (RL+DRB)Ω ( 100 + 0) Iac(mA) Idc(mA) Vo(dc) Vo(ac ) PROCEDURE: 1.note down the output DC voltage i. To calculate load regulation.0615 0.Vnl. 4.483 81. put the designed value of RL=100Ω .note down the output DC voltage i. Note down readings as in the tabular column for different values of output resistor (RL) and find out ripple factor and efficiency. Rig up the circuit as shown in the diagram 2.Then open the load resistance (RL & DRB) .2 & 3 by connecting the suitable capacitor across the load and a separate tabular column should be maintained.2 Practical value With ‘C’ Without ‘C’ (Signature of the Staff with Date) 21 . take the same on the tracing sheet 3. Switch on the input ac signal and connect the output to CRO.

As a result.EXPERIMENT: 7 FULL WAVE BRIDGE RECTIFIER AIM: Testing of Rectifier circuit: determine ripple factor. Ammeter (0 to 100mA). Diodes (BY 127) and capacitor. CRO. Resistors. Diodes D1 and D3 conduct on the positive half cycle and D2 and D4 conduct on the negative half cycle. i. Voltmeter (0 to 25V). Vfl = V ( With load RL at maximum) % Regulation = Ripple = Vo(ac)/Vo(dc) Efficiency = Idc2 / ( Iac2 + Idc2) (RL+DRB)Ω 100 + 20 100 + 40 Iac(mA) Idc(mA) Vo(dc) Vo(ac ) 22 . The disadvantage is it uses four diodes. APPARATUS REQUIRED: Transformer (TR: 12-0-12).except circuit diagram everything is same. procedure and out put waveform is similar to Experiment 6. THEORY: The bridge rectifier is similar to a full wave rectifier because it produces a full wave output voltage. The advantage is the PIV of diodes is Vm. TABULAR COLUMN: With out C-filter Vnl = V ( With load RL removed ). regulation. CIRCUIT DIAGRAM: Note: The design.e. instead of 2Vm in Full wave rectifier with center tap transformer. the rectified load current flows between both half cycles in one direction. efficiency for Full wave bridge rectifier with and without filter.

0615 0.With C-filter Ripple = Vo(ac)/Vo(dc) Efficiency = Idc2 / ( Iac2 + Idc2) (RL+DRB)Ω 100 + 0 Iac(mA) Idc(mA) Vo(dc) Vo(ac ) RESULT: Parameter Ripple Factor Regulation Efficiency Theoretical value With ‘C’ Without ‘C’ 0.2 Practical value With ‘C’ Without ‘C’ (Signature of the Staff with Date) 23 .483 81.

Ie = Ic = 5 mA VRe = Vcc . CRO and signal generator. 1 2 f CE x 0.47 F) 24 .14 x 1000 x 0. Therefore the result is that the emitter current of the first transistor is the base current of the second transistor. same (approximately) current flows through R1 & R2.2 x 1500) = 0.EXPERIMENT: 8 DARLINGTON EMITTER FOLLOWER WITHOUT BOOTSTRAP AIM: Wiring of BJT Darlington Emitter follower & determine the gain. But unfortunately this is not possible because the leakage current is high which is not desired. input & output impedances without bootstrapping.let VR1 = VR2=6v.1 R i.Vce= 12 – 3 = 9V Re= VR3 / Ie = 9V / (5 mA) = 1800 (use 2.1 Ri = 1/(2 x 3.53F(use 0. Resistors. Using emperical relations: IR1=IR2=Ic/85 R1=R2=6v/60µA=100kΩ To find Cc: XcC 0.2kΩ) VCC = VR1 +VR2 . i. In order to improve the values of the circuit current gain and input impedance this cascaded arrangement is done. IeQ=5mA (Q point of transistor Q2). THEORY: The circuit diagram shows the direct coupling of two stage emitter follower.Vce = 3V. COMPONENTS REQUIRED: Transistors (SL100).5 K and f = 1KHz.2 Ri (Ri = R1|| R2 || hie = hie) Choose Ri = 1. Capacitors. Actually the connection of one more stage should increase the input impedance and the current gain. DC power supply. Cc 1 / 2 f x 0.e. The current gain of the pair is equal to the product of individual current gains CIRCUIT DIAGRAM: DESIGN: Let Vcc =12 V .

Connect the circuit as shown above 2. Note down output voltage amplitude at each step using CRO. Plot Gain in dB versus frequency on the semi log graph. determine Bandwidth and G.PROCEDURE: 1. Measure the sine wave signal of amplitude 1V peak to peak from signal generator using CRO and apply to the circuit. Vary the input sine wave frequency from 1 Hz to 1 MHz in suitable steps. 4.B. Calculate the gain in decibels (dBs). 3. TABULAR COLUMN: Vi (P-P) = Frequency (Hz) 1 3 5 8 100 200 400 500 800 1K 10K 100K 200K 500K 700K 900K 1M IDEAL GRAPH (FREQUENCY RESPONSE): Output Voltage(Vo) (P-P) (Volts) volts Voltage Gain= Vo / Vi Gain =20 log (Vo / Vi) dB 25 .W product from the plot.

RESULT: Thus the Darlington Emitter follower without bootstrap has following features. Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance value (Signature of the Staff with Date) 26 . TO FIND OUTPUT RESISTANCE: PROCEDURE: 1.note down the value of output voltage. Connect a DRB(value should be Zero) in series for the existing Darlington Emitter follower circuit as shown above. 2. the current value of DRB is the Input Resistance. Put the frequency of the input in midband (around 10 kHz). Connect a DRB (value should be maximum) in parallel for the existing Darlington Emitter follower circuit as shown above. Decrease the value of DRB linearly such that the output voltage should be half of its initial value.TO FIND INPUT RESISTANCE: PROCEDURE: 1. keeping Vin same (1V). Put the frequency of the input in midband (around 10 kHz). Increase the value of DRB linearly such that the output voltage should be half of its initial value.keeping Vin same(1V). 3. the current value of DRB is the output Resistance. 2.note down the value of output voltage. 3.

COMPONENTS REQUIRED: Transistors (SL100). Capacitors.EXPERIMENT: 9 DARLINGTON EMITTER FOLLOWER WITH BOOTSTRAP AIM: Wiring of BJT Darlington Emitter follower & determine the gain. 27 . CIRCUIT DIAGRAM: Note: Except circuit diagram (additional one Resistance & one Capacitor) everything is same as previous experiment. DC power supply. input & output impedances with bootstrapping. Resistors. CRO and signal generator.

Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance Value (Signature of the Staff with Date) 28 .TABULAR COLUMN: Vi (P-P) = Frequency (Hz) 1 3 5 8 100 200 400 500 800 1K 10K 100K 200K 500K 700K 900K 1M Output Voltage(Vo) (P-P) (Volts) volts Voltage Gain= Vo / Vi Gain =20 log (Vo / Vi) dB RESULT: Thus the Darlington Emitter follower with bootstrap has following features.

Resonance condition can be achieved either by keeping network elements same and varying frequency or by keeping frequency same and varying the frequency dependent circuit elements. Capacitor or Decade Capacitance Box (DCB). a) SERIES RESONANT CIRCUIT CIRCUIT DIAGRAM: IDEAL GRAPH: c) PARALLEL RESONANT CIRCUIT CIRCUIT DIAGRAM: IDEAL GRAPH: DESIGN: (same for both) Let fr=5kHz and C=0. when an inductance coil and capacitance are connected either in series or parallel across an alternating supply of varying frequency. THEORY: Resonance is a phenomenon and study of AC circuits. b) Parallel resonant COMPONENTS REQUIRED: Signal generator.1µF We know that Resonant frequency. Inductor or Decade inductance Box (DIB). 29 .fr = 1/ (2π√LC) Then L=0. Resonance circuits are classified into two categories: Series resonance circuit and Parallel resonance circuit. Band width and Q-factor of resonant circuits: a) Series resonant. resistor.EXPERIMENT: 10 RESONANT CIRCUITS AIM: To plot the frequency response and determine Resonance frequency. Ammeter. choose a current limiter R=100 Ω.01 H.

2. An Input of 10 Vp-p sine wave signal from signal generator is applied. 4. The frequency response plot is plotted Iac v/s frequency.5K 5K 5. Note: we can also calculate Q-factor=(Wr*L)/R.Bandwidth(BW)=f2-f1 and Q-factor=fo/BW are calculated.where Wr=2πfr RESULT: Parameter Resonant frequency Band width Q-factor Series Resonance Parallel Resonance Iac(mA) b) Parallel Resonance Frequency(Hz) 500 1K 2K 4K 4.5K 5K 5. Connections are made as shown in the diagram. The Input frequency is varied from 500 Hz to 10kHz and the corresponding Iac readings are noted down in the tabular column.5K 6K 8K 10k Iac(mA) (Signature of the Staff with Date) 30 .TABULAR COLUMN: a) Series Resonance Frequency(Hz) 500 1K 2K 4K 4.from the plot the resonant frequency(fo). 3.5K 6K 8K 10k PROCEDURE: (same for both) 1.

.7=2.R1=3. The major application of this oscillator is in low frequency audio range CIRCUIT DIAGRAM: DESIGN: Given Vcc=+12 v. then R1=23.e.44R2 If R2=6.7v Then by using previous equation.3k Ω (use 22k Ω) Use CE = 47µF. 31 .Potentiometer.Capacitors. each RC network provides 600 phase shift.EXPERIMENT: 11 RC PHASE SHIFT OSCILLATOR AIM:Wiring & testing for the performance of BJT-RC phase shift oscillator for range f0 <= 10kHz (i.Vce=6v.8kΩ. Co=0.Ic=4mA and hfe=100 Let Ve=2v.454.2) The total phase shift should be 3600. RE=Ve/(Ie orIc)=500(use 470 Ω) Applying KVL to CE loop Vcc-IcRc-Vce-Ve=0 Rc=( Vcc -Vce-Ve)/ Ic =1kΩ From the circuit Vb(voltage across R2)=(VccxR2)/(R1xR2) and Vb=Vbe+Ve=2+0. For RC-network: fo=1/(2лRC√(6+4K)). RC phase shift Oscillator basically consists of an amplifier and feed back network consisting of resistors and capacitors in ladder fashion. Then C= 0.where A is the gain of the amplifier stage and β is the gain of the feedback.47µF.Let fo=2kHz and R=2. THEORY: The basic criterion to be followed by any network to get oscillations is the Barkhausen criteria: it states two conditions. The transistor (CE) amplifier provides 1800 degree phase shift and the other 1800 phase shift is provided by RC feed back network i.1)Aβ>=1. COMPONENTS REQUIRED:NPN transistor (SL100).2KΩ Where K=Rc/R=0. DC power supply (0-30v) and CRO.01µF.e. 2 kHz).Resistors.

RL (10k pot) in the feedback path is varied till stable oscillations are observed on the CRO. RESULT: Parameter Frequency Theoretical value Practical value (Signature of the Staff with Date) 32 . EXERCISE: The lissageous patterns representing different phase shifts from input to output of RC network (one stage provides 600 ) can be observed on the CRO. 2) The DC voltages Ve=2v.then connect RC network. 3) The potentiometer. where T is time period of the output signal. Vce=6v are measured using multimeter.OUTPUT WAVEFORM: PROCEDURE: 1) Connections are made as shown in the circuit diagram without connecting RC network. 4) The output signal is traced into a tracing sheet and the frequency=(1/T)Hz of same is measured.

Here the tank circuit consists of 2 capacitors in series and one capacitor.5 kHz and C=0. b) Colpitts oscillator. The amplifier is single stage amplifier and has 1800 phase shift. CE=47µF. sustained oscillation occurs at the output. THEORY: In phase shift oscillator.When the feedback is adjusted so that 1.8KΩ.i. The oscillators that employ L&C elements are called tuned oscillators. L1= L2=100 µH Note:Biasing circuit design for BJT amplifier is same for both Hartley oscillator and Colpitts oscillator. A Hartley oscillator has an Potential divider biased BJT amplifier and LC feedback circuit. RE=470Ω. Inductors. So this tank circuit provides 1800 phase shift due to inductor & capacitor connection to make total phase shift of the circuit as 3600 at the frequency of oscillations. Colpitts oscillator is similar to the Hartley oscillator except the change in the tank circuit. If f=112. feedback circuit to have inductor and capacitors. Capacitors.01µF Then using above equation.which is same as RC phase shift oscillator. RC circuit is used to get the oscillation whose frequency is in the audio range. To get higher frequency of oscillation. Cc1=Cc2=0.EXPERIMENT: 12 HARTLEY OSCILLATOR AND COLPITTS OSCILLATOR AIM: Wiring & testing for the performance of Oscillator for RF oscillator for RF range f0 >= 100 kHz: a) Hartley oscillator. DC power supply (0-30v) and CRO. potentiometer. Resistors. R2=6. R1=22kΩ. 33 . Its feedback or tank circuit consists of 2 inductor in series and one capacitor in parallel.47µF. COMPONENTS REQUIRED: NPN transistor (SL100). f 1/ 2 LC For Hartley oscillator L =L1+L2. a) HARTLEY OSCILLATOR CIRCUIT DIAGRAM: DESIGN: The frequency of the oscillations. Rc=1KΩ.e.Hartley and Colpitts oscillators belong to LC tuned oscillator.

OUTPUT WAVEFORM: PROCEDURE: (same for both Hartley oscillator and Colpitts oscillator) 1) Connections are made as shown in the circuit diagram without connecting tank circuit. f 1/ 2 LC For Colpitts Oscillator C= C1C2/(C1+C2) If f=100. 4) The output signal is traced into a tracing sheet and the frequency= (1/T) Hz of same is measured. 3) The potentiometer (1k pot) is varied till stable oscillations are observed on the CRO. RESULT: Parameter Frequency (KHz) Type Hartley Oscillator Colpitts Oscillator Theoretical value Practical value (Signature of the Staff with Date) 34 .65 kHz. where T is time period of the output signal.b) COLPITTS OSCILLATOR CIRCUIT DIAGRAM: DESIGN: The frequency of the oscillations. L=5mH. C1=C2=1000pF. 2) The DC voltages Ve=2v. Then by using above equation. Vce=6v are measured using multimeter and then connect tank circuit.

EXPERIMENT: 13 CRYSTAL OSCILLATOR AIM: Testing for the performance of BJT – crystal oscillator for f0 > 100 kHz (2MHz). RE=470Ω. C2=0. potentiometer (1K). Since the parallel resonant frequency of a crystal is slightly higher than its series resonant frequency.i. Rc=1KΩ. and use C1=300pF.1µF. In the series mode crystal offers minimum impedance at resonance and in parallel mode it offers maximum impedance and is inductive. Capacitors. COMPONENTS REQUIRED: Crystal (2MHz). DC power supply (0-30v) and CRO. which cannot be achieved through LC or RC circuits.CE=47µF. A crystal can be operated in the series resonant or parallel resonant mode. THEORY: Crystal oscillators are made from quartz (piezoelectric material). The procedure of conduction is same as experiment 12. Resistors. RESULT: Parameter Frequency Theoretical value Practical value (Signature of the Staff with Date) 35 . stable and fixed values of frequencies in the order of few Mega Hertz. R2=6. the method of connection is important.8KΩ.e. CIRCUIT DIAGRAM: Note:Biasing circuit design for BJT amplifier is same as RC phase shift oscillator. R1=22kΩ. They are used for generating accurate. NPN transistor (SL100).

7=2.44R2 If R2=R4=4.EXPERIMENT: 14 VOLTAGE SERIES FEEDBACK AMPLIFIER AIM: Wiring of a two stage BJT voltage series feedback amplifier and determine the gain. DC power supply.7kΩ. CRO and signal generator. a) Without the feedback CIRCUIT DIAGRAM: DESIGN: Given Vcc=+12 v. Resistors. Ci=Cc= Co=0. a) Without the feedback. b) With the Feedback COMPONENTS REQUIRED: Transistors (SL100). The characteristics of this circuit are: Input impedance is high (MΩ) and Output impedance is low as in the order of hundreds of ohms. The proper use of negative feedback is the significant improvement in the frequency response (as in ideal graph) and in the linearity of operation of the feedback amplifier compared with that of the amplifier without feedback. In this amplifier the feed back voltage is in series with the source voltage.18 kΩ (use 15 kΩ) Use CE1 = CE2=47µF. then R1=R3=16.Vce=6v. frequency response. THEORY: The bipolar transistor common emitter amplifier can be used as voltage-series feed back amplifier. Rf1=330Ω 36 . The other advantage of negative feedback is it increases the input resistance and decreases the output resistance of the amplifier. R1=3. input & output impedances.Ic=4mA and hfe=100.47µF.7v Then by using previous equation. RE1= RE2=Ve/(Ie orIc)=500(use 470 Ω) Applying KVL to CE loop Vcc-IcRc-Vce-Ve=0 Rc1=Rc2=( Vcc -Vce-Ve)/ Ic =1kΩ From the circuit Vb(voltage across R2)=(VccxR2)/(R1xR2) and Vb=Vbe+Ve=2+0. Let Ve=2v. Capacitors.

Vary the input sine wave frequency from 100 Hz to 1 MHz in suitable steps.B. 3. 2.Note: For with feedback the only Rf =10kΩ will be the additional component. 4. b) With the feedback CIRCUIT DIAGRAM: PROCEDURE: (same for both with and without feedback) 1. IDEAL GRAPH: Note: To find input and out put impedances. the procedure is same as followed in RC coupled amplifier for both with and without feedback.Plot Gain in dB versus frequency on the semi log graph.W product from the plot. by applying Vcc=12v for both stages.6v as designed. check the DC voltage conditions Vce =6v and Vbe =0. Connect the circuit as shown above without applying Vin. determine Bandwidth and G. Measure the sine wave signal of amplitude 20 mV from signal generator using CRO and apply to the circuit. 37 . Caluculate the gain in decibels (dBs). Note down output voltage amplitude at each step using CRO.

Vi (P-P) = Frequency (Hz) 100 200 400 500 800 1K 2K 5K 10K 20K 50K 100K 200K 500K 700K 900K 1M b) With the Feedback :.TABULAR COLUMN: a) Without the Feedback :.Vi (P-P) = Frequency (Hz) 100 200 400 500 800 1K 2K 5K 10K 20K 50K 100K 200K 500K 700K 900K 1M Output Voltage(Vo) (P-P) (Volts) Voltage Gain= Vo / Vi volts Output Voltage(Vo) (P-P) (Volts) Voltage Gain= Vo / Vi volts Gain =20 log (Vo / Vi) dB Gain =20 log (Vo / Vi) dB 38 .

RESULT: Thus the voltage series feedback amplifier with and without the feedback has following features: Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance . Without the feedback With the feedback (Signature of the Staff with Date) 39 .

This causes a distortion called crossover distortion. Ammeter.EXPERIMENT: 15 CLASS –B PUSH PULL AMPLIFIER AIM: Testing of a transformer less Class –B push pull amplifier and determine its conversion efficiency. the NPN transistor conducts and during the negative half cycle PNP transistor conducts. During the positive half cycle of the input signal. CRO and signal generator.During this interval no transistors conducts . such an amplifier uses two transistors. THEORY: In a transformer less Class B push pull power amplifier two complementary symmetric transistor stages are used to avoid the use of a centre tapped transformer at the input and output stages. Resistors (fixed and DRB). The transistors conduct only if the input voltage crosses the threshold voltage of 0. DC power supply.7v. in which a transistor conducts for a half cycle. CIRCUIT DIAGRAM: OUTPUT WAVEFORM: 40 . COMPONENTS REQUIRED: Transistors (SL100 and SK100). It is basically a class –B amplifier. For complete conduction.

TABULAR COLUMN: RL(DRB) Ω Vo(p-p)v 100 200 Idc Pdc=VccX Idc Pac=[Vo(p-p)/2√2] 2/RL Conversion efficiency. 5 kHz and apply it as input (Vi) to the circuit.PROCEDURE: 1) Connect circuit as shown in the diagram. 4) By varying the Value of DRB (RL). note down the value of Vo(p-p) across DRB also note the value of Idc. 2) Measure a sine wave signal of 5v. η =Pac/Pdc RESULT: The value of conversion efficiency of a transformer less Class –B push pull Amplifier is: (Signature of the Staff with Date) 41 .then calculate conversion efficiency. 3) Observe the crossover distorted sine wave as shown on the CRO. takedown same waveform on the tracing sheet.