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SECTION  A
1. Fill in the blanks:
(i) For the digital in figure, the expression for the output f is _________
(ii) In interleaved memory organization, consecutive words are stored in
consecutive memory modules in ________ interleaving, whereas consecutive
words are stored within the module in ________ interleaving.
(iii) Consider the number given by the decimal expression:
3 2
16 * 9 16 *7 16 *5 3 + + +
The number of 1’s in the unsigned binary representation of the number is
________.
(iv) Using the 8087 arithmetic coprocessor with the 8087 CPU requires that the
8087 CPU is operated ________.
(v) When two 4bit binary number
3 2 1 0 3 2 1 0
and A a a a a B b b b b = = are multiplied,
the digit
1
c of the product C is given by _________
(vi) Consider the following PASCAL program segment:
if i mode 2 = 0 then
while i > = 0 do
begin
i:=i div 2;
if i mod 2 < > 0 do then i:=i – 1
else i:=i – 2
end
An appropriate loopinvariant for the whileloop is ______
(vii) The minimum number of comparisons required to sort 5 elements is _____
a b
x
y
f
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(viii) The weighted external path length of the binary tree in figure is _____
(ix) If the binary tree in figure is traversed in inorder, then the order in which the
nodes will be visited is ______
(x) Consider the following recursive definition of fib:
fib (n) : = if n = 0 then 1
else if n = 1 than 1
else fib (n – 1) + fib ( n – 2)
The number of times fib is called (including the first call) for an evaluation of
fib (7) is ___________
(xi) The arithmetic expression : ( ) * / ** a b c d e f + − is to be evaluated on a two
address machine, where each operands, the number of registers required to
evaluate this expression is ______. The number of memory access of
operand is __________.
(xii) A given set of processes can be implemented by using only
parbegin/parend statement, if the precedence graph of these processes is
________
(xiii) The number of integertriples (i.j.k) with 1 ≤ i.j.k ≤ 300 such that i + j + k is
divisible by 3 is ________
(xiv) If the longest chain in a partial order is of length n then the partial order
can be written as a ______ of n antichains.
(xv) The maximum number of possible edges in an undirected graph with a
vertices and k components is ________.
15
9
10
7
5
4
2
1
4
6
7
3
5
2
8
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2. Match the pairs in the following questions by writing the corresponding letters
only.
(i)
(A) IEEE 488 (P) specifies the interface for connecting a single device
(B) IEEE 796 (Q) specifies the bus standard for connecting a computer to other
devices including CPU’s
(C) IEEE 696 (R) specifies the standard for an instrumentation bus
(D) RS232C (S) specifies the bus standard for the “backplane” bus called multibus.
(ii) For the 8086 microprocessor:
(iii)
(A) Buddy system (P) Runtime type specification
(B) Interpretation (Q) Segmentation
(C) Pointer type (R) Memory allocation
(D) Virtual memory (S) Garbage collection
(iv)
(A) The number distinct binary trees with n nodes
(P)
!
2
n
(B) The number of binary strings of length of 2n with an equal number
of 0’s and 1’s
(Q)
3n
n
 

\ ¹
(C) The number of even permutations of n objects
(R)
2n
n
 

\ ¹
(D) The number of binary strings of length 6m which are palindromes
with 2n 0’s.
(S)
1 2
1
n
n n
 

+
\ ¹
(A) RQ/GT (P) Used by processor for holding the bus for consecutive instruction
cycles.
(B) LOCK (Q) Used for extending the memory or I/O cycle times
(C) HOLD (R) Used for getting hold of processor bus in minimum bus mode
(D) READY (S) Used for requesting processor bus in minimum bus mode.
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3. Choose the correct alternatives (more than one may be correct) and write the
corresponding letters only:
(i) The advantages of CMOS technology over a MOS is:
(a) lower power dissipation
(b) greater speed
(c) smaller chip size
(d) fewer masks for fabrication
(e) none of the above
(ii) Advantage of synchronous sequential circuits over asynchronous ones is:
(a) faster operation
(b) ease of avoiding problems due to hazards
(c) lower hardware requirement
(d) better noise immunity
(e) none of the above
(iii) The total size of address space is a virtual memory systems is limited by
(a) the length of MAR
(b) the available secondary storage
(c) the available main memory
(d) all of the above
(e) none of the above
(iv) The TRAP interrupt mechanism of the 8085 microprocessor:
(a) executes an instruction supplied by an external device through the INTA
signal
(b) executes an instruction from memory location 20H
(c) executes a NOP
(d) none of the above
(v) The ALE line of an 8085 microprocessor is used to:
(a) latch the output of an I/O instruction into an external latch
(b) deactivate the chipselect signal from memory devices
(c) latch the 8 bits of address lines AD7AD0 into an external latch
(d) find the interrupt enable status of the TRAP interrupt
(e) None of the above
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(vi) Kruskal’s algorithm for finding a minimum spanning tree of a weighted graph
G with vertices and m edges has the time complexity of:
(a)
( )
2
O n
(b) ( ) O mn
(c) ( ) O m n +
(d) ( ) log O m n
(e)
( )
2
O m
(vii) The following sequence of operations is performed on a stack:
PUSH (10), PUSH (20), POP, PUSH (10), PUSH (20), POP, POP, POP,
PUSH (20), POP
The sequence of values popped out is:
(a) 20, 10, 20, 10, 20
(b) 20, 20, 10, 10, 20
(c) 10, 20, 20, 10, 20
(d) 20, 20, 10, 20, 10
(viii) Consider the following Pascal function:
function X (M:integer) : integer;
var i:integer;
begin
i = 0;
while i*i<M do i; =i+1
X;=i
end
The function call X(N), if N is positive, will return
(a)
( )
N
(b)
( )
1 N +
(c) N
(
¸ ¸
(d) 1 N
(
+
¸ ¸
(e) None of the above
(ix) A “link editor” is a program that:
(a) matches the parameters of the macrodefinition with locations of the
parameters of the macro call
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(b) matches external names of one program with their location in other
programs
(c) matches the parameters of subroutine definition with the location of
parameters of subroutine call.
(d) acts as link between text editor and the user
(e) acts as a link between compiler and user program.
(x) Indicate all the true statements from the following:
(a) Recursive descent parsing cannot be used for grammar with left recursion.
(b) The intermediate form the representing expressions which is best suited for
code optimization is the post fix form.
(c) A programming language not supporting either recursion or pointer type
does not need the support of dynamic memory allocation.
(d) Although C does not support call by name parameter passing, the effect can
be correctly simulated in C.
(e) No feature of Pascal violates strong typing in Pascal.
(xi) Indicate all the false statements from the statements given below:
(a) The amount of virtual memory available is limited by the availability of
secondary storage.
(b) Any implementation of a critical section requires the use of an indivisible
machineinstruction, such as testandset.
(c) The LRU page replacement policy may cause hashing for some type of
programs.
(d) The best fit techniques for memory allocation ensures the memory will never
be fragmented.
(xii) If
1 2 3
, and F F F are propositional formulae such that
1 2 3 1 1 2
and ~ F F F F F F ∧ → ∧ → are both tautologies, then which of the
following is true:
(a) Both
1 2
and F F are tautologies
(b) The conjunction
1 2
F F ∧ is not satisfiable
(c) Neither is tautologous
(d) Neither is satisfiable
(e) None of the above
(xiii) Let ( ) 1 1 0 *, 11*0 and t 1*0 r s = + = = be three regular expressions. Which
one of the following is true?
(a) ( ) ( ) ( ) ( ) and L s L r L s L t ⊆ ⊆
(b) ( ) ( ) ( ) ( ) and L r L s L s L t ⊆ ⊆
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(c) ( ) ( ) ( ) ( ) and L s L t L s L r ⊆ ⊆
(d) ( ) ( ) ( ) ( ) and L t L s L s L r ⊆ ⊆
(e) None of the above
(xiv)Which one of the following is the strongest correct statement about a finite
language over some finite alphabet ? ∑
(a) It could be undecidable
(b) It is Turingmachine recognizable
(c) It is a contextsensitive language
(d) It is a regular language
(e) None of the above
4. Give short answers to the following questions:
(i) Convert the following Pascal statement to a single assignment statement:
if x > 5 they y:=true
else y:=false;
(ii) Convert the Pascal statement repeat S
until B; into an equivalent Pascal
statement that uses the while construct.
(iii) Obtain the optimal binary search tree with equal probabilities for the
identifier set ( ) ( )
1 2 3
, , if, stop,while a a a =
(iv) If a finite axiom system A for a theory is complete and consistent, then is
every subsystem of A complete and consistent? Explain briefly.
SECTION – B
5. (a) Analyse the circuit in figure and complete the following table:
a b
n
Q
0 0
0 1
1 0
1 1
Q
a
b
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(b) Find the minimum sum of products form of the logic function.
( ) ( ) ( ) , , , 0,2, 8,10,15 3,11,12,14 f A B C D m d = +
∑ ∑
Where m and d denote the minterms and don’t cares respectively.
(c) Find the maximum clock frequency at which the counter in figure, can be
operated. Assume that the propagation delay through each flipflop and AND
gate is 10 ns. Also assume that the setup time for the JK inputs of the flip
flops is negligible.
6. (a) Using D flipflop and gates, design a parallelin/serialout shift register that
shifts data from left to right with the following input lines:
(i) Clock CLK
(ii) Three parallel data inputs A, B, c
(iii) Serial input S
(iv) Control input load / SHIFT .
(b) Design a 1024 bit serialin/serialout unidirectional shift register using a 1K ×
1 bit RAM with data input ,
in
D data output
out
D and control input
READ/ WRITE . You may assume that availability of standard SSI and MSI
components such as gates, registers and counters.
7. It is required to design a hardwired controller to handle the fetch cycle of a single
address of an indexed instruction should be derived in the fetch cycle itself.
Assume that the lower order 8 bits of an instruction constitute the operand field.
(a) Give the register transfer sequence for realizing the above instruction fetch
cycle.
(b) Draw the logic schematic of the hardwired controller including the date path.
8. (a) Consider an 8085 based system operating with the following specification:
Crystal frequency : 6 MHz
ROM map : 0000 through 07FF
J0 Q0
K0 CK
J1 Q1
K1 CK
J2 Q2
K2 CK
Clock
1
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PORTDATE OUTPUT
WROF PORT 40 H
INTERRUPT
BUFFULL
STROBEINPUT FROM DEVICE
RAM map : 1000 through 17 FF:
ROM requires one wait state.
RAM requires no wait state.
Determine the instruction cycle time for each of the following instructions:
(i) ORI A, 22
(ii) DCR M
Assume the following initial conditions of the CPU registers (in hex) for each
of the instructions:
A = 55, B = AA, C = F7, D = 10, H = 10, L = FF, PC = 0200, SP = 17FO.
(b) Developing an output port interface (draw a block schematic) for an 8085
based system with a demultiplexed address bus which incorporates a
handshake protocol as per the timing diagram given in figure. The interface
should include a status input port at I/O address 40H which reads the
INTERRUPT and BUFFFULL signals through the most significant bit and the
least significant bit, respectively. The output data port is at the same I/O
address 40H and is activated by a write operation. Assume the availability of
SSI and MSI level components only.
Write a short program segment which performs a 200 H byte programmed
I/O data transfer to the device from memory address 3400 H,
9. (a) Consider the following pseudocode
(all data items are of type integer):
Procedure P (a, b, c);
a:=2;
c:=a+b;
end {P}
begin
x:=1
y:=5;
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z:=100;
P(x,x*y,z);
Write (‘x=’,x,z=’,z)
end:
Determine its output, if the parameters are passed to the procedure P by (i)
value, (ii) reference and (iii) name.
(b) For the following pseudocode, indicate the output, if
(i) static scope rules and (ii) dynamic scope rules are used
Var, a, b : inteer;
Procedure P;
a:=5; b:=10
end {P};
procedure Q;
var a, b : integer;
P;
end {Q};
begin
a:=1; b:=2;
Q;
Write (‘a =’, a, ‘b=’,b)
end.
10. Consider the following grammar for arithmetic expression using binary operators
– and/which are not associative:
( )
E E T T
T
T
F F
F E id
→ −
→
→
(E is the start symbol)
(a) Is this grammar unambiguous? If so, what is the relative precedence
between – and/if not, give an unambiguous grammar that gives/precedence
over 
(b) Does the grammar allow expressions with redundant parentheses as in
(id/id) or in id(id/id)? If so, convert the grammar into one which does not
generate expressions with redundant parentheses. Do this with minimum
number of changes to the given production rules and adding at most one
more production rule.
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11. Consider the following scheme for implementing a critical section in a situation
with three processes and .
j k
P P
;
i
P
repeat
flag [i]:=true;
while flag [j] or flag [k] do
case turn of
j : if flag [j] then
begin
flag [i]:=false;
while turn ≠ i do skip;
flag [i] : true
end;
k : if flag [k] then
begin
flag [i]:=false,
while turn ≠ i do skip;
flag [i]:=true
end
end
critical section
if turn = i then turn:=j;
flag [i]:=false
noncritical section
until false;
(a) Does the scheme ensure mutual exclusion in the critical section? Briefly
explain.
(b) Is there a situation in which a waiting process can never enter the critical
section? If so, explain and suggest modifications to the code to solve this
problem.
12. Suppose, a database consists of the following relations:
SUPPLIER (SCODE, SNAME, CITY)
PART (PCODE, PNAME, PDESC, CITY)
PROJECTS (PRCODE, PRNAME, CITY)
SPRR (SCODE, PCODE, PRCODE, QJY)
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(a) Write SQL programs corresponding to the following queries:
(i) Print PCODE value for parts supplied to any project in DELHI by a supplier
in DELHI.
(ii) Print all triples (CITY, PCODE, CITY), such that a supplier in the first city
supplies the specified part to a project in the second city, but do not print
triples in which the two CITY values are the same.
(b) Write algebraic solutions to the following:
(i) Get SCODE values for suppliers who supply to both projects PR1 and PR2.
(ii) Get PRCODE values for projects supplied by at least one supplier not in
the same city.
13. Give an optimal algorithm is pseudocode for sorting a sequence of n numbers
which has only k distinct numbers (k is not known a Priori. Give a brief analysis
for the timecomplexity of your algorithm).
14. Consider the binary tree in Figure:
(a) What structure is represented by the binary tree?
(b) Give the different steps for deleting the node with key 5 so that the structure
is preserved.
(c) Outline a procedure in pseudocode to delete an arbitrary node from such a
binary tree with n nodes that preserves the structure. What is the worstcase
timecomplexity of your procedure?
15. (a) Show that the product of the least common multiple and the greatest
common divisor of two positive integers a and b is a*b.
(b) Consider the following first order formula:
( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ( ) ( ) ( )
( ) ( )
, , ~ ,
, , ,
~ ,
Ax Ey R x y Ax Ay R x y R y x
Ax Ay Az R x y R y z R x z
Ax R x x
∧ →
∧ ∧ →
∧
5
7 13
1
18
20
25
27
11 9 15 17
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(Auniversal quantifier and Eexistential quantifier)
Does it have finite models?
Is it satisfiable? Is so, give a countable model for it.
16.
(a) Find the number of binary strings w of length 2n with an equal number os 1’s
and 0’s, and the property that every prefix and w has atleast as many 0’s as
1’s.
(b) Show that all vertices in an undirected finite graph cannot have distinct
degrees, if the graph has at least two vertices.
17. (a) Show that Turing machines, which have a read only input tape and constant
size work tape, recognize preasely the class or regular languages.
(b) Let L be the language of all binary strings in which the third symbol from the
right is
1
. a Give a nondeterministic finite automaton that recognizes L. How
many states does the minimized equivalent deterministic finite automaton
have? Justify your answer briefly?
if the precedence graph of these processes is ________ (xiii) The number of integertriples (i.gateforum.com (viii) The weighted external path length of the binary tree in figure is _____ 15 9 10 2 4 5 7 (ix) If the binary tree in figure is traversed in inorder.j. Join All India Mock GATE Classroom Test Series . Percentile. the number of registers required to evaluate this expression is ______.GATE CS . For more details.com Think GATE Think GATE Forum . and more.2007 conducted by GATE Forum in over 25 cities all over India.k ≤ 300 such that i + j + k is divisible by 3 is ________ (xiv) If the longest chain in a partial order is of length n then the partial order can be written as a ______ of n antichains. (xii) A given set of processes can be implemented by using only parbegin/parend statement.gateforum.com Join discussion of this test paper at http://forum. visit www. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. All India Rank. interaction with IISc alumni in our online discussion forums.1991 www.k) with 1 ≤ i. then the order in which the nodes will be visited is ______ 7 3 1 5 6 8 2 4 (x) Consider the following recursive definition of fib: fib (n) : = if n = 0 then 1 else if n = 1 than 1 else fib (n – 1) + fib ( n – 2) The number of times fib is called (including the first call) for an evaluation of fib (7) is ___________ (xi) The arithmetic expression : ( a + b ) * c − d / e * *f is to be evaluated on a twoaddress machine.j. The number of memory access of operand is __________.gatementor. where each operands. (xv) The maximum number of possible edges in an undirected graph with a vertices and k components is ________.
interaction with IISc alumni in our online discussion forums. and more. (ii) For the 8086 microprocessor: (P) Used by processor for holding the bus for consecutive instruction cycles.GATE CS .com Think GATE Think GATE Forum .2007 conducted by GATE Forum in over 25 cities all over India. (i) (A) IEEE 488 (B) IEEE 796 (C) IEEE 696 (D) RS232C www. All India Rank.com Join discussion of this test paper at http://forum.com Match the pairs in the following questions by writing the corresponding letters only. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. visit www. Percentile. Join All India Mock GATE Classroom Test Series .gatementor.gateforum. (A) RQ/GT (B) LOCK (C) HOLD (D) READY (iii) (A) Buddy system (B) Interpretation (C) Pointer type (D) Virtual memory (iv) (P) Runtime type specification (Q) Segmentation (R) Memory allocation (S) Garbage collection (A) The number distinct binary trees with n nodes (B) The number of binary strings of length of 2n with an equal number of 0’s and 1’s (C) The number of even permutations of n objects (P) n! 2 3n (Q) n 2n (R) n (S) 1 2n n +1 n (D) The number of binary strings of length 6m which are palindromes with 2n 0’s.gateforum. (P) specifies the interface for connecting a single device (Q) specifies the bus standard for connecting a computer to other devices including CPU’s (R) specifies the standard for an instrumentation bus (S) specifies the bus standard for the “backplane” bus called multibus.1991 2. (Q) Used for extending the memory or I/O cycle times (R) Used for getting hold of processor bus in minimum bus mode (S) Used for requesting processor bus in minimum bus mode. For more details.
2007 conducted by GATE Forum in over 25 cities all over India. interaction with IISc alumni in our online discussion forums. Percentile. All India Rank.com Join discussion of this test paper at http://forum.com Think GATE Think GATE Forum .gateforum. and more.gatementor.com Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: (i) The advantages of CMOS technology over a MOS is: (a) lower power dissipation (b) greater speed (c) smaller chip size (d) fewer masks for fabrication (e) none of the above (ii) Advantage of synchronous sequential circuits over asynchronous ones is: (a) faster operation (b) ease of avoiding problems due to hazards (c) lower hardware requirement (d) better noise immunity (e) none of the above (iii) The total size of address space is a virtual memory systems is limited by (a) the length of MAR (b) the available secondary storage (c) the available main memory (d) all of the above (e) none of the above (iv) The TRAP interrupt mechanism of the 8085 microprocessor: (a) executes an instruction supplied by an external device through the INTA signal (b) executes an instruction from memory location 20H (c) executes a NOP (d) none of the above (v) The ALE line of an 8085 microprocessor is used to: (a) latch the output of an I/O instruction into an external latch (b) deactivate the chipselect signal from memory devices (c) latch the 8 bits of address lines AD7AD0 into an external latch (d) find the interrupt enable status of the TRAP interrupt (e) None of the above Join All India Mock GATE Classroom Test Series . Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus.gateforum. www.GATE CS . visit www. For more details.1991 3.
PUSH (20). POP The sequence of values popped out is: (a) 20. 20. 20. 20. 20 (c) 10. visit www. 20. begin i = 0. 10 (viii) Consider the following Pascal function: function X (M:integer) : integer.=i end The function call X(N). will return (a) (b) ( N) ( N) +1 (c) N (d) N + 1 (e) None of the above (ix) A “link editor” is a program that: (a) matches the parameters of the macrodefinition with locations of the parameters of the macro call Join All India Mock GATE Classroom Test Series . POP.gatementor. POP. =i+1 X. Percentile. 20 (b) 20.com Join discussion of this test paper at http://forum. while i*i<M do i. interaction with IISc alumni in our online discussion forums. 10. 10.com (vi) Kruskal’s algorithm for finding a minimum spanning tree of a weighted graph G with vertices and m edges has the time complexity of: (a) O n2 ( ) (b) O ( mn ) (c) O ( m + n ) (d) O ( m log n ) (e) O m2 ( ) (vii) The following sequence of operations is performed on a stack: PUSH (10). and more. 20. 10. 20 (d) 20. POP. For more details. PUSH (20). var i:integer.2007 conducted by GATE Forum in over 25 cities all over India.gateforum. All India Rank. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. POP. PUSH (10). 20.gateforum. 10. 10.com Think GATE Think GATE Forum . if N is positive.1991 www. 10.GATE CS . PUSH (20).
(xii) If F1 .com Think GATE Think GATE Forum . (e) No feature of Pascal violates strong typing in Pascal. (d) The best fit techniques for memory allocation ensures the memory will never be fragmented. then such which of that the F1 ∧ F2 → F3 and F1 ∧ F1 →~ F2 are www. All India Rank. (x) Indicate all the true statements from the following: (a) Recursive descent parsing cannot be used for grammar with left recursion.gateforum. visit propositional both formulae tautologies. For more details. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus.com (b) matches external names of one program with their location in other programs (c) matches the parameters of subroutine definition with the location of parameters of subroutine call. Which one of the following is true? (a) L ( s ) ⊆ L ( r ) and L ( s ) ⊆ L ( t ) (b) L ( r ) ⊆ L ( s ) and L ( s ) ⊆ L ( t ) Join All India Mock GATE Classroom Test Series . (d) Although C does not support call by name parameter passing.GATE CS .gateforum. (b) The intermediate form the representing expressions which is best suited for code optimization is the post fix form.com Join discussion of this test paper at http://forum. (d) acts as link between text editor and the user (e) acts as a link between compiler and user program. such as testandset.gatementor. (b) Any implementation of a critical section requires the use of an indivisible machineinstruction. interaction with IISc alumni in our online discussion forums. (c) The LRU page replacement policy may cause hashing for some type of programs. (xi) Indicate all the false statements from the statements given below: (a) The amount of virtual memory available is limited by the availability of secondary storage.2007 conducted by GATE Forum in over 25 cities all over India. and more.1991 www. (c) A programming language not supporting either recursion or pointer type does not need the support of dynamic memory allocation. F2 and F3 are following is true: (a) Both F1 and F2 are tautologies (b) The conjunction F1 ∧ F2 is not satisfiable (c) Neither is tautologous (d) Neither is satisfiable (e) None of the above (xiii) Let r = 1 (1 + 0 ) *. Percentile. the effect can be correctly simulated in C. s = 11 * 0 and t = 1 * 0 be three regular expressions.
visit www.1991 (c) L ( s ) ⊆ L ( t ) and L ( s ) ⊆ L ( r ) (d) L ( t ) ⊆ L ( s ) and L ( s ) ⊆ L ( r ) (e) None of the above www. SECTION – B 5.com Think GATE Think GATE Forum . and more. interaction with IISc alumni in our online discussion forums.gateforum.2007 conducted by GATE Forum in over 25 cities all over India. (iii) Obtain the optimal binary search tree with equal probabilities for the identifier set ( a1 .com (xiv)Which one of the following is the strongest correct statement about a finite language over some finite alphabet ∑ ? (a) It could be undecidable (b) It is Turingmachine recognizable (c) It is a contextsensitive language (d) It is a regular language (e) None of the above 4.GATE CS . Percentile.gateforum. then is every subsystem of A complete and consistent? Explain briefly.while ) (iv) If a finite axiom system A for a theory is complete and consistent. (ii) Convert the Pascal statement repeat S until B.com Join discussion of this test paper at http://forum. a2 . into an equivalent Pascal statement that uses the while construct. For more details. (a) Analyse the circuit in figure and complete the following table: a 0 0 1 1 b 0 1 0 1 Qn a Q b Join All India Mock GATE Classroom Test Series . Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. stop. All India Rank. Give short answers to the following questions: (i) Convert the following Pascal statement to a single assignment statement: if x > 5 they y:=true else y:=false.gatementor. a3 ) = (if.
c (iii) Serial input S (iv) Control input load / SHIFT . Percentile. Also assume that the setup time for the JK inputs of the flipflops is negligible.1991 www.com (b) Find the minimum sum of products form of the logic function.com Think GATE Think GATE Forum .12. D ) = ∑ m (0.2007 conducted by GATE Forum in over 25 cities all over India. Assume that the lower order 8 bits of an instruction constitute the operand field. 2. (c) Find the maximum clock frequency at which the counter in figure. data output Dout and control input READ/ WRITE .gateforum. B. All India Rank. You may assume that availability of standard SSI and MSI components such as gates. visit www. (b) Draw the logic schematic of the hardwired controller including the date path. design a parallelin/serialout shift register that shifts data from left to right with the following input lines: (i) Clock CLK (ii) Three parallel data inputs A.gateforum.15) + ∑ d (3. 8. For more details. 1 J0 Q0 J1 Q1 J2 Q2 K0 CK K1 CK K2 CK Clock 6. registers and counters. interaction with IISc alumni in our online discussion forums.gatementor. C .GATE CS .11. can be operated.14) Where m and d denote the minterms and don’t cares respectively. It is required to design a hardwired controller to handle the fetch cycle of a single address of an indexed instruction should be derived in the fetch cycle itself.com Join discussion of this test paper at http://forum. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. 8. (a) Give the register transfer sequence for realizing the above instruction fetch cycle. (a) Consider an 8085 based system operating with the following specification: Crystal frequency : 6 MHz ROM map : 0000 through 07FF Join All India Mock GATE Classroom Test Series . and more. (a) Using D flipflop and gates. Assume that the propagation delay through each flipflop and AND gate is 10 ns. (b) Design a 1024 bit serialin/serialout unidirectional shift register using a 1K × 1 bit RAM with data input Din .10. f ( A. 7. B.
a:=2.gateforum. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus.gatementor. and more. b.com Think GATE Think GATE Forum . Assume the availability of SSI and MSI level components only.2007 conducted by GATE Forum in over 25 cities all over India. PORTDATE OUTPUT WR OF PORT 40 H INTERRUPT BUFFULL STROBE INPUT FROM DEVICE 9. c:=a+b. The output data port is at the same I/O address 40H and is activated by a write operation.com Determine the instruction cycle time for each of the following instructions: (i) ORI A. 22 (ii) DCR M Assume the following initial conditions of the CPU registers (in hex) for each of the instructions: A = 55. (a) Consider the following pseudocode (all data items are of type integer): Procedure P (a.GATE CS . For more details.com Join discussion of this test paper at http://forum. All India Rank. c). (b) Developing an output port interface (draw a block schematic) for an 8085 based system with a demultiplexed address bus which incorporates a handshake protocol as per the timing diagram given in figure. Percentile. D = 10. visit www. Write a short program segment which performs a 200 H byte programmed I/O data transfer to the device from memory address 3400 H. B = AA. SP = 17FO. PC = 0200. H = 10. RAM requires no wait state.1991 RAM map : 1000 through 17 FF: ROM requires one wait state. interaction with IISc alumni in our online discussion forums. Join All India Mock GATE Classroom Test Series . www. C = F7. L = FF. respectively. The interface should include a status input port at I/O address 40H which reads the INTERRUPT and BUFFFULL signals through the most significant bit and the least significant bit.gateforum. end {P} begin x:=1 y:=5.
Percentile. b : integer. Consider the following grammar for arithmetic expression using binary operators – and/which are not associative: E → E −T T T → T F F F → ( E ) id (E is the start symbol) (a) Is this grammar unambiguous? If so. a. indicate the output. visit www. procedure Q.com Determine its output. convert the grammar into one which does not generate expressions with redundant parentheses. a.GATE CS . Procedure P.b) end. (ii) reference and (iii) name. P. 10. (b) For the following pseudocode.z) end: www.x*y. end {Q}.x.gateforum. b:=10 end {P}. var a. what is the relative precedence between – and/if not. Q.z). and more.gatementor. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. P(x. All India Rank. give an unambiguous grammar that gives/precedence over (b) Does the grammar allow expressions with redundant parentheses as in (id/id) or in id(id/id)? If so. begin a:=1. interaction with IISc alumni in our online discussion forums.com Join discussion of this test paper at http://forum.z=’. if the parameters are passed to the procedure P by (i) value. b:=2. Do this with minimum number of changes to the given production rules and adding at most one more production rule.2007 conducted by GATE Forum in over 25 cities all over India.gateforum. b : inteer. ‘b=’.com Think GATE Think GATE Forum . For more details. Join All India Mock GATE Classroom Test Series . if (i) static scope rules and (ii) dynamic scope rules are used Var. Write (‘x=’. Write (‘a =’. a:=5.1991 z:=100.
PCODE. repeat flag [i]:=true. (a) Does the scheme ensure mutual exclusion in the critical section? Briefly explain.gateforum.com Join discussion of this test paper at http://forum. and more. flag [i] : true end.com Consider the following scheme for implementing a critical section in a situation with three processes Pj and Pk . PDESC. CITY) PART (PCODE. 12. while turn ≠ i do skip. All India Rank.2007 conducted by GATE Forum in over 25 cities all over India. CITY) SPRR (SCODE. CITY) PROJECTS (PRCODE.GATE CS .gateforum. For more details. interaction with IISc alumni in our online discussion forums. visit www. k : if flag [k] then begin flag [i]:=false. PNAME. SNAME.1991 11.com Think GATE Think GATE Forum . Pi . PRNAME. PRCODE. www. QJY) Join All India Mock GATE Classroom Test Series . while turn ≠ i do skip. Percentile. while flag [j] or flag [k] do case turn of j : if flag [j] then begin flag [i]:=false. explain and suggest modifications to the code to solve this problem. a database consists of the following relations: SUPPLIER (SCODE.gatementor. (b) Is there a situation in which a waiting process can never enter the critical section? If so. flag [i]:=false noncritical section until false. flag [i]:=true end end critical section if turn = i then turn:=j. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. Suppose.
(ii) Get PRCODE values for projects supplied by at least one supplier not in the same city. y ) →~ R ( y. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. Give a brief analysis for the timecomplexity of your algorithm). CITY). Consider the binary tree in Figure: 1 14.1991 www.com Think GATE Think GATE Forum .gateforum. What is the worstcase timecomplexity of your procedure? 15. 18 5 20 7 13 25 27 11 9 15 17 (a) What structure is represented by the binary tree? (b) Give the different steps for deleting the node with key 5 so that the structure is preserved. (c) Outline a procedure in pseudocode to delete an arbitrary node from such a binary tree with n nodes that preserves the structure. (a) Show that the product of the least common multiple and the greatest common divisor of two positive integers a and b is a*b. y ) ∧ ( Ax ) ( Ay ) ( R ( x. and more.com (a) Write SQL programs corresponding to the following queries: (i) Print PCODE value for parts supplied to any project in DELHI by a supplier in DELHI.2007 conducted by GATE Forum in over 25 cities all over India.gateforum. (b) Write algebraic solutions to the following: (i) Get SCODE values for suppliers who supply to both projects PR1 and PR2. but do not print triples in which the two CITY values are the same. y ) ∧ R ( y . PCODE. (ii) Print all triples (CITY. All India Rank. x ) Join All India Mock GATE Classroom Test Series . x ) ) ∧ ( Ax ) ( Ay ) ( Az ) ( R ( x.gatementor. such that a supplier in the first city supplies the specified part to a project in the second city. interaction with IISc alumni in our online discussion forums.GATE CS . Give an optimal algorithm is pseudocode for sorting a sequence of n numbers which has only k distinct numbers (k is not known a Priori. z ) ) ∧ ( Ax ) ~ R ( x. z ) → R ( x. Percentile.com Join discussion of this test paper at http://forum. 13. visit www. (b) Consider the following first order formula: ( Ax ) ( Ey ) R ( x. For more details.
GATE CS .gateforum.com (a) Find the number of binary strings w of length 2n with an equal number os 1’s and 0’s.2007 conducted by GATE Forum in over 25 cities all over India.com Think GATE Think GATE Forum . For more details. which have a read only input tape and constant size work tape. if the graph has at least two vertices. visit www.gatementor. Question Papers including section tests and full tests are designed by IISc alumni according to the latest syllabus. Give a nondeterministic finite automaton that recognizes L. www. interaction with IISc alumni in our online discussion forums.1991 (Auniversal quantifier and Eexistential quantifier) Does it have finite models? Is it satisfiable? Is so. and more.gateforum.com Join discussion of this test paper at http://forum. (b) Show that all vertices in an undirected finite graph cannot have distinct degrees. Percentile. All India Rank. 17. (b) Let L be the language of all binary strings in which the third symbol from the right is a1. and the property that every prefix and w has atleast as many 0’s as 1’s. How many states does the minimized equivalent deterministic finite automaton have? Justify your answer briefly? Join All India Mock GATE Classroom Test Series . recognize preasely the class or regular languages. give a countable model for it. (a) Show that Turing machines. 16.
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