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8051

8051

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05/05/2012

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Sections

  • 8051 Basic Component
  • Other 8051 featurs
  • External code memory
  • External data memory
  • Register Banks
  • The 8051 Assembly Language
  • Overview
  • Stacks
  • Stack
  • Stack (push,pop)
  • Exchange Instructions
  • Rotate
  • Swap
  • Shift/Mutliply Example
  • Infinite Loops
  • Re-locatable Code
  • Jump table
  • Conditional jumps
  • Why Subroutines?
  • Interrupt Sources
  • Interrupt Process
  • Interrupt Priorities
  • Interrupt SFRs

The 8051 Microcontroller

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-1

8051 Basic Component
4K bytes internal ROM 128 bytes internal RAM Four 8-bit I/O ports (P0 - P3). Two 16-bit timers/counters One serial interface
CPU I/O Port RAM ROM Serial Timer COM Port

A single chip Microcontroller

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-2

Block Diagram
External Interrupts

Interrupt Control

4k ROM

128 bytes RAM

Timer 1 Timer 2

CPU

OSC

Bus Control

4 I/O Ports

Serial

P0 P2 P1 Addr/Data
hsabaghianb @ kashanu.ac.ir

P3

TXD RXD
Microprocessors 1-3

Other 8051 featurs  only 1 On chip oscillator (external crystal)  6 interrupt sources (2 external .ir Microprocessors 1-4 .WR  Code memory is selectable by EA (internal or external)  We may have External memory as data and code hsabaghianb @ kashanu.ac. Reset)  64K external code (program) memory(only read)PSEN  64K external data memory(can be read and write) by RD. 3 internal.

Embedded System (8051 Application)  What is Embedded System? An embedded system is closely integrated with the main system It may not interact directly with the environment For example – A microcomputer in a car ignition control  An embedded product uses a microprocessor or microcontroller to do one task only  There is only one application software that is typically burned into ROM hsabaghianb @ kashanu.ir Microprocessors 1-5 .ac.

Examples of Embedded Systems Keyboard Printer video game player MP3 music players Embedded memories to keep configuration information Mobile phone units Domestic (home) appliances Data switches Automotive controls hsabaghianb @ kashanu.ir Microprocessors 1-6 .ac.

ir Microprocessors 1-7 . the amount of ROM and RAM. simulator. packaging. debuggers. the number of I/O ports and timers. size. technical support  wide availability and reliable sources of the microcontrollers hsabaghianb @ kashanu. C compilers.Three criteria in Choosing a Microcontroller  meeting the computing needs of the task efficiently and cost effectively  speed.ac. emulator. power consumption  easy to upgrade  cost per unit  availability of software development tools  assemblers.

0v) 8951 8952 8953 8955 898252 891051 892051 hsabaghianb @ kashanu.Comparison of the 8051 Family Members  ROM type            8031 80xx 87xx 89xx no ROM mask ROM EPROM Flash EEPROM  89xx  Example (AT89C51.ir Microprocessors 1-8 .ac.AT89S51)  AT= ATMEL(Manufacture)  C = CMOS technology  LV= Low Power(3.AT89LV51.

ir Microprocessors 1-9 .Comparison of the 8051 Family Members 89XX 8951 8952 8953 ROM 4k 8k 12k RAM 128 256 256 Timer 2 3 3 Source Int 6 8 9 IO pin 32 32 32 Other WD 8955 898252 891051 892051 20k 8k 1k 2k 256 256 64 128 3 3 1 2 8 9 3 6 32 32 16 16 WD ISP AC AC WD: Watch Dog Timer AC: Analog Comparator ISP: In System Programable hsabaghianb @ kashanu.ac.

ir Microprocessors 1-10 .ac.8051 Internal Block Diagram hsabaghianb @ kashanu.

ac.ir Microprocessors 1-11 .8051 Schematic Pin out hsabaghianb @ kashanu.

8051 Foot Print P1.4 (T1)P3.2(AD2) P0.4(AD4) P0.1 P1.4(A12) P2.5 P1.ir .6 (RD)P3.3(A11) P2.3(AD3) P0.4 P1.3 P1.1 (INT0)P3.2 (INT1)P3.1(A9) P2.0(AD0) P0.5(A13) P2.1(AD1) P0.ac.7(AD7) EA/VPP ALE/PROG PSEN P2.5(AD5) P0.7(A15) P2.0(A8) Microprocessors 1-12 hsabaghianb @ kashanu.3 (T0)P3.6(AD6) P0.2 P1.6 P1.5 (WR)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8051 (8031) (8751) (8951) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.7 RST (RXD)P3.0 (TXD)P3.6(A14) P2.2(A10) P2.0 P1.

General Purpose I/O  Or high byte of the address bus for external memory design Port 3 (pins 10-17):P3(P3.7)  Only 8-bit R/W .P3)  Port 0 (pins 32-39):P0(P0.    Each port can be used as input or output (bi-direction) hsabaghianb @ kashanu.General Purpose I/O Port 2 (pins 21-28):P2(P2.General Purpose I/O  Or acts as a multiplexed low byte address and data bus for external memory design  Port 1 (pins 1-8) :P1(P1.0~P0.0~P3.IMPORTANT PINS (IO Ports)  One of the most useful features of the 8051 is that it contains four I/O ports (P0 .0~P1.0~P2.7)  General Purpose I/O  if not using any of the internal peripherals (timers) or external interrupts.7)  8-bit R/W .7)  8-bit R/W .ac.ir Microprocessors 1-13 .

Port 3 Alternate Functions hsabaghianb @ kashanu.ac.ir Microprocessors 1-14 .

8051 Port 3 Bit Latches and I/O Buffers hsabaghianb @ kashanu.ac.ir Microprocessors 1-15 .

X Clk Q P1.ac.ir Microprocessors 1-16 .Hardware Structure of I/O Pin Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch D Q P1.X pin M1 TB1 Read pin hsabaghianb @ kashanu.

ac.ir Microprocessors 1-17 .Hardware Structure of I/O Pin  Each pin of I/O ports Internally connected to CPU bus A D latch store the value of this pin Write to latch=1:write data into the D latch 2 Tri-state buffer: TB1: controlled by “Read pin” Read pin=1:really read the data present at the pin TB2: controlled by “Read latch” Read latch=1:read value from internal latch A transistor M1 gate Gate=0: open Gate=1: close hsabaghianb @ kashanu.

X pin output 1 TB1 Read pin hsabaghianb @ kashanu.ac. write a 1 to the pin Internal CPU bus Write to latch D Q Vcc 1 0 M1 P1. output pin is 1.X Clk Q P1.X Read latch TB2 Vcc Load(L1) 2.Writing “1” to Output Pin P1.ir Microprocessors 1-18 .

write a 0 to the pin Internal CPU bus Write to latch D Q ground 0 1 M1 P1.Writing “0” to Output Pin P1.X pin output 0 TB1 Read pin hsabaghianb @ kashanu. output pin is 1.X Clk Q P1.ac.X Read latch TB2 Vcc Load(L1) 2.ir Microprocessors 1-19 .

#0FFH Internal CPU bus TB2 Load(L1) 1 1 Vcc 2.P1 external pin=High D Q P1.X pin Write to latch Clk Q 0 M1 TB1 Read pin 3.ir Microprocessors 1-20 .ac.X P1.Reading “High” at Input Pin Read latch 1. MOV A. Read pin=1 Read latch=0 Write to latch=1 hsabaghianb @ kashanu. write a 1 to the pin MOV P1.

MOV A.P1 external pin=Low D Q P1.ac.X P1. write a 1 to the pin MOV P1.Reading “Low” at Input Pin Read latch 1.ir Microprocessors 1-21 . Read pin=1 Read latch=0 Write to latch=1 8051 IC hsabaghianb @ kashanu.#0FFH Internal CPU bus TB2 Load(L1) 1 0 Vcc 2.X pin Write to latch Clk Q 0 M1 TB1 Read pin 3.

2 8751 P0.Port 0 with Pull-Up Resistors Vcc 10 K P0.5 P0.7 hsabaghianb @ kashanu.4 8951 P0.6 P0.0 DS5000 P0.ac.1 P0.ir Microprocessors 1-22 Port 0 .3 P0.

the read signal for external program memory (active low). active low to access external program memory locations 0 to 4K  RXD.ir Microprocessors 1-23 . Address Latch Enable.IMPORTANT PINS PSEN (out):  ALE (out):  EA (in): Program Store Enable.TXD: UART pins for serial I/O on Port 3  XTAL1 & XTAL2: Crystal inputs for internal oscillator. to latch address outputs at Port0 and Port2 External Access Enable. hsabaghianb @ kashanu.ac.

 GND(pin 20):ground  XTAL1 and XTAL2(pins 19. Way 1:using a quartz crystal oscillator Way 2:using a TTL oscillator Example 4-1 shows the relationship between XTAL and the machine cycle.ir Microprocessors 1-24 . The voltage source is +5V.ac.18): These 2 pins provide external clock. hsabaghianb @ kashanu.Pins of 8051  Vcc(pin 40): Vcc provides supply voltage to the chip.

XTAL Connection to 8051 Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND hsabaghianb @ kashanu.ir Microprocessors 1-25 .ac.

N C EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 GND hsabaghianb @ kashanu.ir Microprocessors 1-26 .XTAL Connection to an External Clock Source Using a TTL oscillator XTAL2 is unconnected.ac.

machine cycle = 1 / 1.0592 MHz / 12 = 921.0592 MHz (b) XTAL = 16 MHz.333 MHz.6 kHz.6 kHz = 1.333 MHz = 0.ir .75 s Microprocessors 1-27 hsabaghianb @ kashanu.ac.085 s (b) 16 MHz / 12 = 1.      Solution: (a) 11.Machine cycle    Find the machine cycle for (a) XTAL = 11. machine cycle = 1 / 921.

ir Microprocessors 1-28 .Pins of 8051  RST(pin 9):reset  input pin and active high(normally low).ac. Upon applying a high pulse to RST.  power-on reset. The high pulse must be high at least 2 machine cycles. Reset values of some 8051 registers  power-on reset circuit hsabaghianb @ kashanu. the microcontroller will reset and all values in registers will be lost.

Power-On RESET
Vcc

31 10 uF 30 pF

EA/VPP X1

X2 RST 9
8.2 K

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-29

RESET Value of Some 8051 Registers:

Register PC

Reset Value 0000

ACC
B PSW SP

0000
0000 0000 0007

DPTR
RAM are all zero
hsabaghianb @ kashanu.ac.ir

0000


Microprocessors 1-30

Pins of 8051
 /EA(pin 31):external access  There is no on-chip ROM in 8031 and 8032 .  The /EA pin is connected to GND to indicate the code is stored externally.  /PSEN & ALE are used for external ROM.  For 8051, /EA pin is connected to Vcc.  “/” means active low.  /PSEN(pin 29):program store enable  This is an output pin and is connected to the OE pin of the ROM.  See Chapter 14.

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-31

hsabaghianb @ kashanu.Pins of 8051  ALE(pin 30):address latch enable It is an output pin and is active high.ac.ir Microprocessors 1-32 . 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.

ac.ir Microprocessors 1-33 .Address Multiplexing for External Memory Figure 2-7 Multiplexing the address (low-byte) and data bus hsabaghianb @ kashanu.

ir Microprocessors 1-34 .ac.Address Multiplexing for External Memory Figure 2-8 Accessing external code memory hsabaghianb @ kashanu.

hsabaghianb @ kashanu.ir Microprocessors 1-35 .ac.

ir Microprocessors 1-36 .ac.Accessing External Data Memory Figure 2-11 Interface to 1K RAM hsabaghianb @ kashanu.

Timing for MOVX instruction hsabaghianb @ kashanu.ac.ir Microprocessors 1-37 .

0 P2.7 A8 A15 8051 hsabaghianb @ kashanu.External code memory WR RD PSEN ALE P0.7 OE CS A0 A7 G D 74LS373 D0 EA D7 P2.ir ROM Microprocessors 1-38 .ac.0 P0.

7 WR RD G D 74LS373 CS A0 A7 D0 EA D7 P2.ac.0 P2.7 A8 A15 8051 hsabaghianb @ kashanu.ir RAM Microprocessors 1-39 .0 P0.External data memory WR RD PSEN ALE P0.

ir Microprocessors 1-40 .Overlapping External Code and Data Spaces hsabaghianb @ kashanu.ac.

Overlapping External Code and Data Spaces WR RD PSEN ALE P0.7 A8 A15 8051 hsabaghianb @ kashanu.ir RAM Microprocessors 1-41 .ac.7 WR RD G D 74LS373 CS A0 A7 D0 EA D7 P2.0 P2.0 P0.

ac. and  executed from RAM as code. This allows a program to be downloaded from outside into the RAM as data. hsabaghianb @ kashanu.ir Microprocessors 1-42 .Overlapping External Code and Data Spaces Allows the RAM to be  written as data memory. and  read as data memory as well as code memory.

ac.ir Microprocessors 1-43 .hsabaghianb @ kashanu.

ac.ir Microprocessors 1-44 .On-Chip Memory Internal RAM hsabaghianb @ kashanu.

ac.2.ir Microprocessors 1-45 .Registers 1F Bank 3 18 17 Four Register Banks Each bank has R0-R7 Selectable by psw.3 Bank 2 10 0F Bank 1 08 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0 Bank 0 hsabaghianb @ kashanu.

ac.Bit Addressable Memory 2F 2E 2D 7F 78 20h – 2Fh (16 locations X 8-bits = 128 bits) Bit addressing: mov C. 23h. 1Ah or mov C.ir Microprocessors 1-46 .2 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 0F 07 06 05 04 03 02 01 1A 10 08 00 hsabaghianb @ kashanu.

Addresses 80h – FFh Direct Addressing used to access SPRs hsabaghianb @ kashanu.ac.Special Function Registers DATA registers CONTROL registers Timers Serial ports Interrupt system Analog to Digital converter Digital to Analog converter Etc.ir Microprocessors 1-47 .

Bit Addressable RAM Figure 2-6 Summary of the 8051 on-chip data memory (RAM) hsabaghianb @ kashanu.ir Microprocessors 1-48 .ac.

ir Microprocessors 1-49 .Bit Addressable RAM Figure 2-6 Summary of the 8051 on-chip data memory (Special Function Registers) hsabaghianb @ kashanu.ac.

ir Microprocessors 1-50 .hsabaghianb @ kashanu.ac.

Register Banks  Active bank selected by PSW [RS1.ir Microprocessors 1-51 . hsabaghianb @ kashanu.RS0] bit  Permits fast “context switching” in interrupt service routines (ISR).ac.

hsabaghianb @ kashanu.ac.ir Microprocessors 1-52 .

8051 CPU Registers
A (Accumulator) B PSW (Program Status Word) SP (Stack Pointer) PC (Program Counter) DPTR (Data Pointer)

Used in assembler instructions

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-53

Registers

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-54

Registers
A B R0 R1 R2 R3 R4 R5 R6 R7 PC PC

DPTR

DPH

DPL

Some 8051 16-bit Register

Some 8-bit Registers of the 8051

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-55

ir Microprocessors 1-56 .ac.The 8051 Assembly Language hsabaghianb @ kashanu.

Overview Data transfer instructions Addressing modes Data processing (arithmetic and logic) Program flow instructions hsabaghianb @ kashanu.ac.ir Microprocessors 1-57 .

ac.accumulator and byte hsabaghianb @ kashanu.move from stack .decrement Exchange instructions XCH a.increment stack .exchange accumulator and byte .exchange low nibbles of . stack pointer . byte .move byte .Data Transfer Instructions MOV dest. source Stack instructions PUSH byte POP byte dest  source pointer.ir Microprocessors 1-58 . on stack to byte. byte XCHD a.

put 11hex in the R4 register .put 7521 hex in DPTR .#7521h .put 11 decimal in b register .put 0 in the accumulator . #11 .B = 00001011 mov DPTR.ir Microprocessors 1-59 . #11h mov B.Addressing Modes Immediate Mode – specify data by its value mov A.A = 00000000 .DPTR = 0111010100100001 hsabaghianb @ kashanu. #0 mov R4.ac.R4 = 00010001 .

ir Microprocessors 1-60 .#21H MOV DPH.#MYDATA ~ ~ 0RG 200H MYDATA:DB “IRAN” hsabaghianb @ kashanu. #75 COUNT EGU 30 ~ ~ mov R4. #COUNT MOV DPTR.ac.#7521h MOV DPL.Addressing Modes Immediate Mode – continue MOV DPTR.

DPH Note that MOV R4.A A.ac.R7 DPTR.ir Microprocessors 1-61 .Addressing Modes Register Addressing – either source or destination is one of CPU register MOV MOV ADD ADD MOV MOV MOV R0.R7 A.DPL R.R7 is incorrect hsabaghianb @ kashanu.#25F5H R5.R4 A.

ir Microprocessors 1-62 . .ac.a 0D0h. . Mov Mov Mov Mov a. . 70h R0.Direct Mode – specify data by its 8-bit address Usually for 30h-7Fh of RAM .a copy contents of RAM at 70h to a copy contents of RAM at 70h to a put contents of a at 56h to a put contents of a into PSW Addressing Modes hsabaghianb @ kashanu.40h 56h.

2    MOV A.4 MOV A.R4 MOV A.ir Microprocessors 1-63 .Addressing Modes Direct Mode – play with R0-R7 by direct address MOV A.Put 5 in R2 .#5 MOV R2.R6 .Put content of RAM at 5 in R2 MOV R2.ac.R7 MOV R7.7 MOV 7.5 hsabaghianb @ kashanu.

memory at 3C gets #3 . M[3C]  3 . #3 . #0 mov r0. use register bank 0 . #0x9000 movx a. a  M[9000] Uses DPTR register for 16-bit addresses: mov dptr. dptr  9000h .Addressing Modes Register Indirect – the address of the source or destination is specified in registers Uses registers R0 or R1 for 8-bit address: mov psw. @dptr Note that 9000 is an address in external memory hsabaghianb @ kashanu. #0x3C mov @r0.ir Microprocessors 1-64 .ac.

ac.Use Register Indirect to access upper RAM block (+8052) hsabaghianb @ kashanu.ir Microprocessors 1-65 .

#5 movc a.ir Microprocessors 1-66 . #4000h mov a.ac. @a + dptr .a  M[4005] hsabaghianb @ kashanu.Addressing Modes Register Indexed Mode – source or destination address is the sum of the base address and the accumulator(Index) Base address can be DPTR or PC mov dptr.

#5 movc a.a  M[1008] PC  Table Lookup  MOVC only can read internal code memory Microprocessors 1-67 hsabaghianb @ kashanu.ac.ir .Addressing Modes Register Indexed Mode continue  Base address can be DPTR or PC ORG 1000h 1000 1002 1003 mov a. @a + PC Nop .

00h  Also this 3 instruction 070B E9 070C 89E0 070E 89E0 mov a.ir Microprocessors 1-68 .r1 mov acc.00h mov acc.ac.00h mov 0e0h.Acc Register  A register can be accessed by direct and register mode  This 3 instruction has same function with different code 0703 E500 0705 8500E0 0708 8500E0 mov a.r1 hsabaghianb @ kashanu.r1 mov 0e0h.

a mov 80h.r4  P0~P3 – are direct address 0704 F580 0706 F580 0708 859080 mov p0.ac.r4 mov 0f0h.….ir Microprocessors 1-69 . psw.00h mov b.SFRs Address  B – always direct mode .) hsabaghianb @ kashanu.except in MUL & DIV 0703 8500F0 0706 8500F0 0709 8CF0 070B 8CF0 mov b. tmod.00h mov 0f0h.p1  Also other SFRs (pcon.a mov p0.

PCON. P0~P3. …) are accessible by name and direct address But both of them Must be coded as direct address hsabaghianb @ kashanu.SFRs Address All SFRs such as (ACC.ac. B. TMOD. PSW.ir Microprocessors 1-70 .

#3dh Immediate data .8051 Instruction Format immediate addressing Op code add a.machine code=243d Direct addressing Op code mov r3.0E8h hsabaghianb @ kashanu.ac.machine code=ABE8 Microprocessors 1-71 .ir Direct address .

a r5.ir Microprocessors 1-72 .r1 a.r0 a.EA .a r1.r5 a.Ef = = = = = 1110 1110 1110 1110 1110 1000 1001 1010 1101 1111 hsabaghianb @ kashanu.a r2.a .a r5.ac.r7 r0.E8 .ED .8051 Instruction Format  Register addressing Op code 070D 070E 070F 0710 0711 0712 0713 0714 0715 0716 0717 E8 E9 EA ED EF 2F F8 F9 FA FD FD n n n mov mov mov mov mov add mov mov mov mov mov a.E9 .r7 a.r2 a.

@dptr @dptr.ac.a @r0.ir .@r1 a.@a+dptr a.@r1 Microprocessors 1-73 hsabaghianb @ kashanu. i = 0 or 1 070D 070D 070E 070F 0710 0711 0712 E7 93 83 E0 F0 F2 E3 mov movc movc movx movx movx movx a.@a+pc a.8051 Instruction Format  Register indirect addressing Op code mov a.a a. @Ri i .

ir Microprocessors 1-74 .8051 Instruction Format  relative addressing Op code Relative address here: sjmp here .ac.next=706h 0700 0700 0702 0703 0704 0705 E106 00 00 00 00 hsabaghianb @ kashanu.machine code=80FE(FE=-2) Range = (-128 ~ 127)  Absolute addressing (limited in 2k current mem block) A10-A8 Op code 1 2 3 4 5 6 7 8 A7-A0 org 0700h ajmp next nop nop nop nop next: end 07FEh .

next=0707h hsabaghianb @ kashanu.ir Microprocessors 1-75 .8051 Instruction Format Long distance address Op code A15-A8 A7-A0 Range = (0000h ~ FFFFh) 0700 0700 0703 0704 0705 0706 1 2 3 4 5 6 7 8 org 0700h ajmp next nop nop nop nop next: end 020707 00 00 00 00 .ac.

ac.ir Microprocessors 1-76 . hsabaghianb @ kashanu.Stacks pop push stack pointer stack Go do the stack exercise…..

M[SP]  M[55] M[41]  M[55] b  M[55] pop b Note: can only specify RAM or SFRs (direct mode) to push or pop.ir Microprocessors 1-77 . not a hsabaghianb @ kashanu. must use acc. . . Initialize SP SP  SP+1. Therefore.implied  Direct addressing mode must be used in Push and Pop mov sp.ac. . to push/pop the accumulator.Stack  Stack-oriented data transfer  Only one operand (direct addressing)  SP is other operand – register indirect . #0x40 push 0x55 .

is .b Microprocessors 1-78 hsabaghianb @ kashanu.is .Stack (push.is .is invalid invalid invalid correct correct correct .pop)  Therefore Push Push Push push Push Push Push Push Push Pop Pop Push Pop a r0 r1 acc psw b 13h 0 1 7 8 0e0h 0f0h .ac.acc .is .ir .is .

.4] a[3.ir Microprocessors 1-79 ... a  M[30] a  R0 a  M[R0] exchange “digit” a[7.0] R0[7.4] R0[3.ac.. R0 . 30h XCH a. . R0 XCH a.0] Only 4 bits exchanged hsabaghianb @ kashanu. . .Exchange Instructions two way data transfer XCH a. @R0 XCHD a.

Bit-Oriented Data Transfer  transfers between individual bits.7 hsabaghianb @ kashanu.ir Microprocessors 1-80 .ac. P0.  Carry flag (C) (bit 7 in the PSW) is used as a singlebit accumulator  RAM bits in addresses 20-2F are bit addressable mov C.0 mov C. 67h mov C. 2ch.

etc) Notice that all 4 parallel I/O ports are bit addressable. 98. 90. 88. hsabaghianb @ kashanu. (80.ac.ir Microprocessors 1-81 .SFRs that are Bit Addressable SFRs with addresses ending in 0 or 8 are bit-addressable.

Data Processing Instructions Arithmetic Instructions Logic Instructions hsabaghianb @ kashanu.ac.ir Microprocessors 1-82 .

ir Microprocessors 1-83 .Arithmetic Instructions Add Subtract Increment Decrement Multiply Divide Decimal adjust hsabaghianb @ kashanu.ac.

byte Description add A to byte. byte ADDC A.ac. byte INC A INC byte INC DPTR subtract with borrow increment A increment byte in memory increment data pointer DEC A DEC byte MUL AB DIV AB decrement accumulator decrement byte multiply accumulator by b register divide accumulator by b register DA A decimal adjust the accumulator Microprocessors 1-84 hsabaghianb @ kashanu.Arithmetic Instructions Mnemonic ADD A.ir . put result in A add with carry SUBB A.

a  a + byte + C These instructions affect 3 bits in PSW: C = 1 if result of add is greater than FF AC = 1 if there is a carry out of bit 3 OV = 1 if there is a carry out of bit 7.ir Microprocessors 1-85 . a  a + byte addc a.ac. byte . but not from bit 6. or visa versa.ADD Instructions add a. hsabaghianb @ kashanu. byte .

ir Microprocessors 1-86 .ac.Instructions that Affect PSW bits hsabaghianb @ kashanu.

AC.ADD Examples mov a. OV flags after the second instruction is executed? C = 1 AC = 1 OV = 0 hsabaghianb @ kashanu.ac. #3Fh add a.ir Microprocessors 1-87 . #D3h 0011 1111 1101 0011 0001 0010  What is the value of the C.

Signed Addition and Overflow 2’s 0000 … 0111 1000 … 1111 complement: 0000 00 0 1111 0000 1111 7F 127 80 -128 FF -1 0011 1111 (positive) 1101 0011 (negative) 0001 0010 (never overflows) 0111 1111 (positive 127) 0111 0011 (positive 115) 1111 0010 (overflow cannot represent 242 in 8 bits 2’s complement) 1000 1111 1101 0011 0110 0010 (negative 113) (negative 45) (overflow) hsabaghianb @ kashanu.ac.ir Microprocessors 1-88 .

Y mov Z. a end hsabaghianb @ kashanu.----------------------------------------------------------------org 00h ljmp Main .Addition Example .ir Microprocessors 1-89 . Computes Z = X + Y .-----------------------------------------------------------------X equ 78h Y equ 79h Z equ 7Ah . X add a.----------------------------------------------------------------org 100h Main: mov a.ac. Adds values at locations 78h and 79h and puts them in 7Ah .

Y+1 mov Z+1. X+1 adc a.ir Microprocessors 1-90 . a end hsabaghianb @ kashanu.----------------------------------------------------------------org 00h ljmp Main . a mov a.Z are 16 bit) .Y.ac.The 16-bit ADD example .-----------------------------------------------------------------X equ 78h Y equ 7Ah Z equ 7Ch . Computes Z = X + Y (X. X add a. Y mov Z.----------------------------------------------------------------org 100h Main: mov a.

ir .A  A – 4F – C Notice that There is no subtraction WITHOUT borrow. if a subtraction without borrow is desired.ac. it is necessary to clear the C flag. #0x4F .A  A – 4F Microprocessors 1-91 . byte subtract with borrow Example: SUBB A. #0x4F hsabaghianb @ kashanu.Subtract SUBB A. Example: Clr c SUBB A. Therefore.

hsabaghianb @ kashanu.  Notice we can only INCREMENT the data pointer. not decrement.ac.ir Microprocessors 1-92 .Increment and Decrement INC A INC byte increment A increment byte in memory INC DPTR DEC A DEC byte increment data pointer decrement accumulator decrement byte  The increment and decrement instructions do NOT affect the C flag.

use add rather than increment to affect C . a .Example: Increment 16-bit Word Assume 16-bit word in R3:R2 mov a. #0 mov r3. #1 mov r2.ir Microprocessors 1-93 . r3 addc a. add C to most significant byte hsabaghianb @ kashanu.ac. a mov a. r2 add a.

Multiply When multiplying two 8-bit numbers. the size of the maximum product is 16-bits FF x FF = FE01 (255 x 255 = 65025) MUL AB .ac. BA  A * B Note : B gets the High byte A gets the Low byte hsabaghianb @ kashanu.ir Microprocessors 1-94 .

used to indicate a divide by zero condition. C – set to zero hsabaghianb @ kashanu.ac.ir Microprocessors 1-95 .Division Integer Division DIV AB . divide A by B A  Quotient(A/B) B  Remainder(A/B) OV .

decimal adjust a Used to facilitate BCD addition. #29h add a. Adds “6” to either high or low nibble after an addition to create a valid BCD number. a  a + 6 = 52 hsabaghianb @ kashanu.ir Microprocessors 1-96 .Decimal Adjust DA a .ac. #23h mov b. Example: mov a. a  23h + 29h = 4Ch (wanted 52) . b DA a .

ac. NOT)  Clear  Rotate  Swap Logic instructions do NOT affect the flags in PSW hsabaghianb @ kashanu.ir Microprocessors 1-97 . OR.Logic Instructions  Bitwise logic operations  (AND. XOR.

ir .Bitwise Logic ANL  AND ORL  OR XRL  XOR CPL  Complement Examples: 00001111 ANL 10101100 00001100 00001111 ORL 10101100 10101111 00001111 XRL 10101100 10100011 CPL 10101100 01010011 Microprocessors 1-98 hsabaghianb @ kashanu.ac.

byte direct. reg. indirect. immediate byte.Address Modes with Logic ANL – AND ORL – OR XRL – eXclusive oR a.ac. a direct byte. reg. #constant CPL – Complement a ex: cpl a hsabaghianb @ kashanu.ir Microprocessors 1-99 .

#0x40 .ir Microprocessors 1-100 .PSW AND 11100111  Force individual bits high. anl PSW. without affecting other bits. #0xE7 .ac.PSW OR 00011000  Complement individual bits xrl P1.P1 XRL 01000000 hsabaghianb @ kashanu.Uses of Logic Instructions  Force individual bits low. orl PSW. #0x18 .

ac.ir Microprocessors 1-101 .Other Logic Instructions CLR RL RLC RR RRC SWAP – – – – – clear rotate left rotate left through Carry rotate right rotate right through Carry swap accumulator nibbles hsabaghianb @ kashanu.

ac.CLR ( Set all bits to 0) CLR CLR CLR CLR A byte Ri @Ri (direct mode) (register mode) (register indirect mode) hsabaghianb @ kashanu.ir Microprocessors 1-102 .

a 01111000 Microprocessors 1-103 .#0xF0 RR a . a 11110000 .Rotate Rotate instructions operate only on a RL a Mov a.#0xF0 RR a hsabaghianb @ kashanu. a 11110000 .ir . a 11100001 RR a Mov a.ac.

ac. a  BD (10111101). #14h rrc a C . C0 .ir Microprocessors 1-104 . a  01011110. c  1 . #0A9h add a. #3ch setb c rlc a .Rotate through Carry RRC a mov a. C1 C RLC a mov a. a  01111001. a  A9 . C1 hsabaghianb @ kashanu. a  3ch(00111100) .

.ac. shift right is divide by 2 mov clr rlc rlc rrc a.Rotate and Multiplication/Division Note that a shift left is the same as multiplying by 2. . . A C A A A 00000011 0 00000110 00001100 00000110 (3) (6) (12) (6) hsabaghianb @ kashanu.ir Microprocessors 1-105 . . #3 C a a a .

a  27h .ir Microprocessors 1-106 . #72h swap a .ac.Swap SWAP a mov a. a  27h hsabaghianb @ kashanu.

ir Microprocessors 1-107 . bit CLR C CLR bit CPL C CPL bit SETB C SETB bit  “bit” can be any of the bit-addressable RAM locations or SFRs. bit ORL C.Bit Logic Operations  Some logic operations can be used with single bit operands ANL C.ac. hsabaghianb @ kashanu.

Shift/Mutliply Example Program segment to multiply by 2 and add 1.ir Microprocessors 1-108 .ac. hsabaghianb @ kashanu.

ac.ir Microprocessors 1-109 .Program Flow Control Unconditional jumps (“go to”) Conditional jumps Call and return hsabaghianb @ kashanu.

AJMP <address 11> . Long jump . LJMP <address 16> . Long hsabaghianb @ kashanu.ir Microprocessors 1-110 . relative address is 8-bit 2’s complement number.Unconditional Jumps SJMP <rel addr> Short jump. or 128 locations back. so jump can be up to 127 locations forward.ac. JMP @A + DPTR indexed jump Absolute jump to anywhere within 2K block of program memory .

ac.ir Microprocessors 1-111 .7 mov p1.Infinite Loops Start: mov C. p3.6. C sjmp Start Microcontroller application programs are almost always infinite loops! hsabaghianb @ kashanu.

C ljmp Start end Re-locatable (machine code) org 8000h Start: mov C.Re-locatable Code Memory specific NOT Re-locatable (machine code) org 8000h Start: mov C.7.6 mov p3.ir Microprocessors 1-112 . C sjmp Start end hsabaghianb @ kashanu.7. p1.6 mov p3. p1.ac.

Jump_table: ajmp case0 ajmp case1 ajmp case2 ajmp case3 hsabaghianb @ kashanu.#jump_table Mov a.ac.ir Microprocessors 1-113 ..Jump table Mov dptr.#index_number Rl a Jmp @a+dptr ..

loop: mov a. else goto next instruction  There is no zero flag (z)  Content of A checked for zero on time hsabaghianb @ kashanu. a . Otherwise.ir Microprocessors 1-114 . goto loop. . program execution continues with the next instruction. if a=0. P1 jz loop mov b.ac.Conditional Jump  These instructions cause a jump to occur only if a condition is true.

ac.ir Microprocessors 1-115 . <rel addr> Compare A and memory.<rel addr> JBC <bir>. jump if not equal hsabaghianb @ kashanu. direct. <rel addr> JNB <bit>. <rel addr> Jump if C = 1 Jump if C != 1 Jump if bit = 1 Jump if bit != 1 Jump if bit =1. bit &clear CJNE A.Conditional jumps Mnemonic JZ <rel addr> JNZ <rel addr> Description Jump if a = 0 Jump if a != 0 JC <rel addr> JNC <rel addr> JB <bit>.

ac.6 mov A.Example: Conditional Jumps if (a = 0) is true send a 0 to LED else send a 1 to LED jz led_off Setb P1.6 sjmp skipover led_off: clr P1. P0 skipover: hsabaghianb @ kashanu.ir Microprocessors 1-116 .

<rel addr> hsabaghianb @ kashanu.More Conditional Jumps Mnemonic CJNE A.ir Microprocessors 1-117 . jump if not equal CJNE @Rn. <rel addr> Decrement Rn and then jump if not zero Decrement memory and then jump if not zero DJNZ direct. jump if not equal Compare Rn and data. #data <rel addr> Description Compare A and data. #data <rel addr> Compare Rn and memory.ac. #data <rel addr> CJNE Rn. jump if not equal DJNZ Rn.

..Iterative Loops For A = 0 to 4 do {…} clr a loop: . inc a cjne a..ac.. ..ir Microprocessors 1-118 . .. loop For A = 4 to 0 do {…} mov R0. djnz R0.. #4.. loop hsabaghianb @ kashanu. #4 loop: .

back1 end mov a.#10h mov r2.#0aah mov b.#12h Back: add a.#0h mov r4.ir Microprocessors 1-119 .next mov b.#05 djnz r4.#10h Back1:mov r6.back2 djnz b.a inc r0 djnz r2.ac.Iterative Loops(examples) mov a.#25h mov r0.#5 Again: mov @ro.#00h cjne a.a end hsabaghianb @ kashanu.#50h mov b.again end mov a.#01h next: nop end mov a.#50h.back mov r5.#50 Back2:cpl a djnz r6.

stack  PC .ac. stack  PC . but Call pushes PC on stack before branching acall <address ll> . PC  address 16 bit lcall <address 16> hsabaghianb @ kashanu. PC  address 11 bit .ir Microprocessors 1-120 .Call and Return Call is similar to a jump.

ir Microprocessors 1-121 .Return Return is also similar to a jump. PC  stack hsabaghianb @ kashanu. but Return instruction pops PC from stack to get address to jump to ret .ac.

Subroutines
call to the subroutine Main: ... acall sublabel ... ... ... ... the subroutine ret

sublabel:

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-122

Initializing Stack Pointer
 SP is initialized to 07 after reset.(Same address as R7)  With each push operation 1st , pc is increased  When using subroutines, the stack will be used to store the PC, so it is very important to initialize the stack pointer. Location 2Fh is often used.

mov SP, #2Fh

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-123

Subroutine - Example
push b mov b,a mul ab pop b ret  8 byte and 11 machine cycle square:

square: inc a movc a,@a+pc ret table: db 0,1,4,9,16,25,36,49,64,81  13 byte and 5 machine cycle

hsabaghianb @ kashanu.ac.ir

Microprocessors 1-124

3 end . Port 3 is an input .1.2. Program to compute square root of value on Port 3 . #0x0F lcall sqrt mov P1.3. #0xFF mov a.1. (bits 3-0) and output on Port 1.3..ir . @a + PC ret db 0.3.3.1. P3 anl a.ac.2.2.3.2. a sjmp loop inc a movc a. org 0 ljmp Main Main: loop: mov P3.3.4 of A reset service main program sqrt: subroutine data Microprocessors 1-125 Sqrs: hsabaghianb @ kashanu.2.Subroutine – another example . Clear bits 7.

hsabaghianb @ kashanu. It saves code space when subroutines can be called many times in the same program. This is useful for breaking a large design into manageable parts.Why Subroutines? Subroutines allow us to have "structured" assembly language programs.ir Microprocessors 1-126 .ac.

ir Microprocessors 1-127 .#0ffh back1: mov r7.#0ffh .#0aah Back1:mov p0.a lcall delay1 cpl a sjmp back1 Delay1:mov r0.back1.1cycle Here: djnz r0.2cycle ret .#0ffh.example of delay mov a.ac.2cycle ret .here .2cycle end Delay=1+255*2+2=513 cycle Delay2: mov r6.2cycle djnz r6.1cycle Here: djnz r7.here .2cycle end Delay=1+(1+255*2+2)*255+2 =130818 machine cycle hsabaghianb @ kashanu.

R5.ac. R7.6 org ooh ljmp Main org 100h clr GREEN_LED acall Delay cpl GREEN_LED sjmp Again reset service Main: Again: main program Delay: Loop1: Loop0: mov mov mov djnz djnz djnz ret END R7.ir Microprocessors 1-128 . #02 #00h #00h $ Loop0 Loop1 subroutine hsabaghianb @ kashanu.Long delay Example GREEN_LED: equ P1. R5. R6. R6.

#10h Loop1: clr a movc a.Example . Move string from code memory to RAM org 0 mov dptr.ir Microprocessors 1-129 .@a+dptr jz stop mov @r0.ac.0 end hsabaghianb @ kashanu.a inc dptr inc r0 sjmp loop1 Stop: sjmp stop . on-chip code memory used for string org 18h String: db „this is a string‟.#string mov r0.

#0ffh mov p0. p0:input p1:output mov a.a setb p2.#45h .p0 mov p1.2 mov a.enable strobe hsabaghianb @ kashanu.a mov a.ir Microprocessors 1-130 .3 .a sjmp back back: Again: request setb p1.Example .3 clr p2.again .ac.wait for data mov p0.data jnb p1.2.

2 acall delay sjmp back back: setb p1.Example .ir .2 acall delay Clr p1.ac. duty cycle 50% back: cpl p1.2 acall delay sjmp back Microprocessors 1-131 hsabaghianb @ kashanu.

2 acall delay acall delay Clr p1.ac.ir Microprocessors 1-132 . duty cycle 66% back: setb p1.2 acall delay sjmp back hsabaghianb @ kashanu.Example .

8051 timer hsabaghianb @ kashanu.ir Microprocessors 1-133 .ac.

R0 mov R0. R1 addc a. a mov a. b mov R1. #2 mov b. #20 mul ab add a. a mov R1. #16 mul ab mov R0. #12 mov b. a end hsabaghianb @ kashanu.6 NEXT: reti return Microprocessors 1-134 . b mov a.ir Program Execution interrupt ISR: inc r7 mov a.ac.r7 jnz NEXT cpl P1.Interrupts … mov a.

ac. programmable counter array. more external interrupts. ADC.Interrupt Sources Original 8051 has 5 sources of interrupts      Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full. buffer empty. etc) Enhanced version has 22 sources  More timers. another serial port (UART) hsabaghianb @ kashanu.ir Microprocessors 1-135 .

ac.ir Microprocessors 1-136 . the PC is popped from the stack and program execution resumes where it left off.Interrupt Process If interrupt event occurs AND interrupt flag for that event is enabled. AND interrupts are enabled. 3. 2. then: 1. Program execution continues at the interrupt vector address for that interrupt. Current PC is pushed on stack. hsabaghianb @ kashanu. When a RETI instruction is encountered.

Priority can also be set to “high” or “low”.ir Microprocessors 1-137 . All interrupts have a default priority order.Interrupt Priorities What if two interrupt sources interrupt at the same time? The interrupt with the highest PRIORITY gets serviced first.ac. hsabaghianb @ kashanu.

Interrupt SFRs Interrupt enables for the 5 original 8051 interrupts: Timer 2 Serial (UART0) Timer 1 Global Interrupt Enable – External 1 must be set to 1 for any Timer 0 1 = Enable interrupt to be enabled External 0 0 = Disable hsabaghianb @ kashanu.ac.ir Microprocessors 1-138 .

ac. hsabaghianb @ kashanu. External Interrupt 0: Timer 0 overflow: External Interrupt 1: Timer 1 overflow: Serial : Timer 2 overflow(8052+) 0003h 000Bh 0013h 001Bh 0023h 002bh Note: that there are only 8 memory locations between vectors.Interrupt Vectors Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.ir Microprocessors 1-139 .

at Main program . hsabaghianb @ kashanu.. it is common to put JUMP instructions at the vector address.ir Microprocessors 1-140 ...Interrupt Vectors To avoid overlapping Interrupt Service routines. and subroutines. Interrupt service routine ..ac.. reti . . Can go after main program . This is similar to the reset vector. at EX7 vector . Main program . org 009B ljmp EX7ISR cseg at 0x100 Main: .. EX7ISR:. ...

#18h mov R0.ir Microprocessors 1-141 .go on then off 10 times hsabaghianb @ kashanu. bank 3. Loop0 djnz R7.initialize counter .6 djnz R0.EX7 ISR to blink the LED 5 times. Loop2 pop PSW reti .ac. Loop1 cpl P1. R5-R7.select register bank 3 . #00h djnz R5.delay a while . #02h mov R6. . $ djnz R6.Example Interrupt Service Routine .Modifies R0. #10 mov R7.---------------------------------------------------- ISRBLK: Loop2: Loop1: Loop0: push PSW mov PSW. .complement LED value .save state of status word . #00h mov R5.

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