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CELL LIBRARY DESIGN
BY TEAM N8 MOHAMED RASHID KARIM RAJESH MANGALORE ANAND SUMANTH SHIVALINGAIAH UMAMAESH BALASHANMUGHAM VASILIS MYLONAKIS
M S c MI C RO E L E CT RO NI CS S YS T E M DE S I G N S CH O O L O F E L E C T R O NI C S A N D CO MP UT E R S CI E NC E U NI V E R S I T Y O F S O UT H A M PT O N , S O UT H A MP T O N
5 Three – input Scan Multiplexer 2.3 Raw D-type Flip Flop 2.14 Two – input Nor 2.6 Standard Multiplexer 2.11 Inverter 2.7 Full Adder 2.8 Half Adder 2.12 Buffer 2.17 Three – input Nand 2.15 Two – input And 2.19 Four – input Nand 2.2 ScannableRegister 2. INTRODUCTION 2.10 Right End 2. DATASHEETS 2.18 Three – input Nor 2.4 Two – input Scan Multiplexer 2.1 Scannable D-type Flip Flop 2.20 Tristate Buffer () () () () () () () () () Page 2 () () () () () () () () () () () () .9 Left Buffer 2.Cell Library Design TABLE OF CONTENTS 1.13 Two – input Nand 2.16 Two – input Or 2.
APPENDIX B () () () () () Page 3 . SUMMARY 4.21 TieHigh.Cell Library Design 2. RowCrosser 3. REFERENCES 5. APPENDIX A 6. TieLow.
XOR. This flow of skillsets can be visualized in three levels. switching. contents of the Cell Library can vary from the fundamental building blocks of logic gate family like INVERTER. Circuit Level: Realising behaviour of logical families with timing. Device Level: This involves studies in independent particle approximation by itself. NAND. INRODUCTION Microelectronics design usually requisites theoretical expertize from understanding fundamental physics to engineering implementation of complex systems. layouts. and RTL considerations. ENCODER. FLIPFLOPS. Some cases. NOR. OR. XNOR to complex logical implementations like MUX. FIGURE 1: Abstract levels of Microelectronics System Design  Cell Library Design is one such part in System Level which has common logic gate families circuit symbols. Based on the requirements. Cell Library is adopted by most of the hardware designers in industries to build architecture of some standard cells and re-use it with minimal changes so as to lessen cost and time taken to build cells from root level. This semi -custom design model of Cell Library in VLSI provides range of the support for all the designs whe re designers choose their right choice and implement with less effort.Cell Library Design 1. Page 4 . optimized and characterized designs. schematic designs. or in turn influences from ions  to solid state device characteristics. AND. stick diagrams. System Level: Building custom designs in analogue or digital domain and simulating functionality of systems in structural and behaviour modular styles. Cell Libraries are utilized as reference manual to understand standard functionality of devices better.
The specified Gate level schematics are transformed to layout by drawing Stick Diagrams.35um]. I0 Scan ScanReturn Test Clock nReset Vdd! N-well I1 O P-well GND! FIGURE 2: Generic view of any cell designed in the report Page 5 . and PMOS by p-diffusion layer represented as yellow.35u CMOS Technology. Length of pmos a nd nmos. Cell design is carried out in MAGIC as the VLSI Layout tool platform at 0.e. Wp=2. power rails to 1. Width of nmos. The working floor in the Layout was set to GRID 12 to align cell width. Each cell has common alignment to origin (0. When complexity of the circuit increases. NMOS by n-diffusion layer represented as gr een. The inputs and outputs are represented by polysilicon and metal for other c onnections. Gate -level schematics. Wn=1. 0) as shown below [3 ]. Layout Diagrams. Metal1 is used as horizontal connections whereas Metal2 for vertical Input and Output connections. but width varies from one another to ensure proper placing and routing between interconnecting cells . Stick Diagrams. Lp=Ln=0. The heights of all cells are same 585 magic units. detailed information of each individual cells design ed by the team is given with respect to the Cell specifications. All the transistors size is fixed throughout design: [Width of pmos. i. the transistors sharing common gate connection: Gate Matrix style often gives more efficient use of area. and Characterisation of some standard designs with H-Spice as well as Verilog simulation are described along with final results. The placement of the transistors from the schematic to stick diagram is implemented by using Gate Matrix Style. although multiple transistors are allowed to use same polysilicon column in Stick Diagrams shown in this report .2um.Cell Library Design In this Report. The contacts are used to draw connections to power rail (Vdd!) Ground rail (GND!) as well as other sources.0um.2um. The MOSFET’s are developed by placing polysilicon in between diffusion layers. It’s a technique which uses Boolean expressions to determine gate arrays to optimize layout.
for any cell. rise time. Drive Inverters drive the inputs and Load Inverters load the outputs. Page 6 . The propagation delay.Cell Library Design The characterization of cells designed requires real -time simulation under faulty circumstances to determine their performance capabilities in hierarchical conditions. The NC-Verilog digital simulator simulates the behaviour of a digital circuit to compute values of corresponding to each input and output states. Therefore. and fall-time delays are extracted for each output with HSpice simulations. Cell designs may be simulated using HSpice (analogue simulation) or System Verilog (digital simulation) .
TRUTH TABLE CELL SYMBOL CELLABSTRACT A B Y A 0 0 1 1 B 0 1 0 1 Y 0 1 A XOR2 B GATE LEVEL CIRCUIT DIAGRAM Y Scan ScanReturn Test Clock nReset Vdd! 30.7 VERILOG SIMULATION WAVEFORM Page 7 . then it results 0 as output.9 197. 0) or (1.e. 1).6µm2 MEASUREMENT OF PARAMETERS INPUT V/S OUTPUT A=>Y B=>Y Propagation Delay(ps) Rise Time 260.2µm AREA = 4413.7 256. DATASHEETS Cell Name: XOR2 Cell Designer: Rajesh Mangalore Anand Description: It is a 2 input logical gate that functions as exclusive OR.6 Fall Time 198. i. if two of the inputs are (0 .Cell Library Design 2.65µm N-well 1 A P-well 0 B GND! Y 7.
TRUTH TABLE CELL SYMBOL CELL ABSTRACT A B S C A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1 A HALF ADDER B Scan ScanReturn Test Clock C nReset Vdd! 30.1 VERILOG SIMULATION WAVEFORM Page 8 .1 Fall time 221. when both inputs are 1 and 1.8 186.8µm C AREA = 6620. and only CARRY=1.5 192. adding 0 and 1(vice-versa).8 232.Cell Library Design Cell Name: HALFADDER Cell Designer: Rajesh Mangalore Anand Description: It is a 2 input logical circuit that generates only SUM=1.6 219.3 223.5 184.4µm2 MEASUREMENT OF PARAMETERS INPUT V/S OUTPUT A=>S B=>S A=>C B=>C Propagation Delay(ps) Rise Time 198.65µm N-well S GATE LEVEL CIRCUIT DIAGRAM A B S P-well GND! 10.
2µm2 MEASUREMENT OF PARAMETERS INPUT V/S OUTPUT A=>Y ENABLE=>Y Propagation Delay(ps) Rise Time 263.0 143.4µm AREA = 5149.65µm N-well 1 A Y ENABLE GND! P-well 8.8 222.Cell Library Design Cell Name: TRISTATE BUFFER Cell Designer: Rajesh Mangalore Anand Description: It is a three state logic gate in which output follow the respective input only when ENABLE is HIGH.7 VERILOG SIMULATION WAVEFORM Page 9 . TRUTH TABLE CELL SYMBOL CELL ABSTRACT A 0 1 0 1 ENABLE 0 0 1 1 Y Z Z 0 GATE LEVEL CIRCUIT DIAGRAM A ENABLE Y A TRISTATE BUFFER ENABLE Scan ScanReturn Test Y Clock nReset Vdd! 30.3 Fall Time 188.
8µm AREA = 2942.Cell Library Design Cell Name: NAND2 Cell Designer: Rajesh Mangalore Anand Description: It is a 2 input negated logic gate of 2 inputs AND gate that outputs 0 only when two inputs are 1. TRUTH TABLE CELL SYMBOL CELL ABSTRACT A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 A NAND2 B Y Scan ScanReturn Test Clock nReset Vdd! A B Y 30.5 Fall Time 125.3 VERILOG SIMULATION WAVEFORM Page 10 .65µm GATE LEVEL CIRCUIT DIAGRAM N-well A B Y GND! P-well MEASUREMENT OF PARAMETERS 4.7 121.4µm2 INPUT V/S OUTPUT A=>Y B=>Y Propagation Delay(ns) Rise Time 126.6 134.
Vdd! Scan ScanReturn Test Clock nReset Vdd! 30.“Vdd”. Row-crosser is a connective “cross” port that allows connection between two cell channels above or below it.65µm N-well 6µm cross AREA = 3678µm2 P-well GND! 6µm AREA = 3678µm2 Page 11 .Cell Library Design Cell Name: TIEHIGH. TIELOW.65µm N-well GND! Scan ScanReturn Test Clock nReset Vdd! 30. and TieLow with ground rail “GND!” respectively. TieHigh is associated with power rail . ROWCROSSER Cell Designer: Rajesh Mangalore Anand Description: These are special standard cells facilitate in overcoming Electrostatic Discharging and also involves in Automatic Routing and Placing.65µm N-well P-well P-well GND! GND! 6µm AREA = 3678µm2 Scan ScanReturn Test Clock nReset Vdd! 30.
mag cell was underpinning as more time was spent to make it error-free. FIGURE 3: Characterization of any cell Propagation delays of output with respect to input for every cell were calculated and tabulated for loaded circuits as shown below . Clearing “Sanity Checks” for all. whereas XP_4 warned less spacing of p-active in p-wells. FIGURE 4: Propagation Delay calculation  All individual cells designed later were butted based on the specified order to form all. Overall. Each team member played an important role in working better Cell design. Perhaps.mag (parent cell). With efficient use of Euler paths to deduce “Gate Level Circuit diagram” to “Stick Diagram”. but resolved commandingly. Care was taken to generate output for all possible gray code inputs. and sub-cells. Characterization of cells was prime stage to know drive and load capabilities . R_27 showed that metal2 via is left alone in power rails. Design Rule Check (DRC) from Cadance Virtuoso and Mentor calibre was a new environment to work on as team had new experience in sorting out errs. SUMMARY Each extracted cell (. smaller layout with least number of line of diffusions in transistors were designed. Having brief description of errors in laboratory.ext format) was transformed to simulate in “SystemVerilog” mode as well as “Spice” mode. XP_6 was solved by placing at least one p-well strap in p-well. These consist of paints. labels. more emphasis would have been given in lessening the overall area of all.mag cell. Page 12 .Cell Library Design 3. it was a fruitful team effort to make Cell Design Data book. The behaviour of each cell was thus analysed graphically.
with all teammates’ presence. rigthend): Mohamed Rashid Karim Vasilis Mylonakis Sumanth Shivalingaiah Rajesh Mangalore Anand Umamahesh Balashanmugham The Stick Diagram preparation.mag combing all cells was done by one. As a result. However. Cell Characterization. but timely. took time. thoroughly by respective designers. each member in our team was given clear idea what is expected from and how deadline is to be met! Team meetings were held regularly to discuss the progress of each work and suggestions were shared.Cell Library Design 4. Analogue Simulation (Hspice) as well as Digital Simulation (SystemVerilog) for above major cells was done by each of member as shown above respectively. smux3): Full Adder (fulladder): Half Adder (halfadder): End of Row Cells (leftbuf. Layout Floor planning. There was room for each member to give relevant ideas. and criticize design rule violations which were accepted sportively. encourage challenging tasks. basic cells were taken up in such a way that work is distributed equally amongst all. The major cells were classified as below: Raw D-Type (rdtype): Two Scan Multiplexer (smux2. the team cleared all errs to finish with error-free cell library. still many errors existed while butting all cells together. lots of care was taken while designing each cell. At last. APPENDIX A The division of labour in a team is always a tough task to work towards an objective till it is achieved. the cell library was created before the deadline and submitted. execution to simulation. Though. and references to appendices. creating all. Design Rule Check (DRC) in Cadence Virtuoso and Mentor This crucial task Calibre was very important stage to assess and correct flaw prone cells. Although. The Cell Design work carried out was documented with all technical evidences of each individual cell from introduction to layout. Datasheets of each cell was prepared Page 13 . optimization to characterization.
Cell Library Design DIVISION OF LABOUR TASK ECS ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 rdtye smux2 smux3 mux2 fulladder halfadder xor2 inv nand2 nand3 nand4 nor2 nor3 and2 or2 trisbuf buffer leftbuf rigthend tiehigh tielow rowcrosser scandtype scanreg Verilog simulation Hspice characterization Final Report(words) Final Report(Figures) OVERALL EFFORT 100 100 100 100 100 100 100 20 20 30 20 20 PERCENTAGE EFFORT ON EACH TASK rma1g11 ss11g11 100 100 100 100 20 20 30 20 20 umb1g11 100 100 100 100 100 20 20 20 20 20 mrk1g11 100 50 50 20 20 10 20 20 vme2g11 100 100 100 100 100 50 50 20 20 10 20 20 Page 14 .
we are only looking for the characteristics of primary inputs A. four loaded inverters for two outputs Sum (S) and Carry (C). but not the behaviour of inverters.e. APPENDIX B Cell Name: HALF ADDER The Boolean expression for Half Adder has two parts for Sum and Carry . This equation is realized in the circuit using Euler Paths shown below. C of the cell under test. B and outputs S. STICK DIAGRAM CIRCUIT SCHEMATIC A B S C A B S C CIRCUIT FOR LOADED SIMULATION: Circuit shown below has two driving inverters for two inputs A and B.i. When simulating this circuit. Page 15 . Sum=A+B: Carry= AB.Cell Library Design 5.
mt0 is used to calculate rise and fall delays.0 166. slew rate.6 HSpice Simulation Waveform Page 16 . Spice file (. whereas. . They are: Fall Time Propagation Delay: Measuring the change in output signal due to input signal fall at Vdd*50% of ouput to Vdd*50% of input Rise Time Propagation Delay: Measuring the change in output signal due to input signal rise at Vdd*50% of ouput to Vdd*50% of input Here.4 Fall Time 174.Cell Library Design RESULTS OF LOADED SIMULATION: HSpice simulator is used to evaluate behavioural characteristics like rise time. frequency and many more .sp) helps to prepare all input and output waveforms and also in calculating propagation delays.tr0 file displays specified waveforms. The numerical calculations of propagation delay are tabulated in the HALFADDER Datasheet has two parameters. we calculate the Time Delay in two terms as explained below.sp file Time Delay (ps) OUTPUT S C Rise Time 228. Fall Time Delay: Measuring the output signal triggered when signal falls at Vdd*10% and Vdd*90% Rise Time Delay: Measuring the output signal triggered when signal rises at Vdd*10% and Vdd*90% Note: Vdd is set to 3. duty cycle. <cellname>.3V when written in .7 242. cat.
Design of semi-custom IC. 3.soton.Cell Library Design 6. Harvard University. http://users. Nanyang Technological University. Massachusetts. HSPICE Simulation and Analysis User Guide by Synopsys 5. 2. by Efthimios Kaxiras. Page 17 . Atomic and Electronic Structure of solids.ac.uk/bim/notes 4. Zhou Xing.ecs. REFERENCES: 1. by Dr.
Cell Library Design Page 18 .
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