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# Name: Rajat Chowdhry Roll Number: 520810922 Learning Centre: 2017 Subject: Digital System Assignment No.

: 1 Date of Submission at the Learning Centre: 19thDec,2008

Ques. 1

Convert the following octal number to decimal

a) 73.24(8) b) 276(8) c) 0.3456(8) d) 24.87(8)

Sol.

a) 73.24(8) = Weight Method = = = = 7 X 81 + 3 X 80 + 2 X 8-1 + 4 X 8-2 7 X 8 + 3 X 1 + 2 X 0.125 + 4 X 0.015625 56 + 3 + 0.25 + 0.0625 59.3125 Weight Method

b) 276(8) = = = = =

2 X 82 + 7 X 81 + 6 X 80 2 X 64 + 7 X 8 + 6 X 1 128 + 56 + 6 190

c) 0.3456(8) = = = = =

Weight Method

3 X 8-1 + 4 X 8-2 + 5 X 8-3 + 6 X 8-4 3 X 0.125 + 4 X 0.015625 + 5 X 0.001953125 + 6 X 0.000244140625 0.375 + 0.0625 + 0.009765625 + 0.00146484375 0.44873046875

d) 24.87(8) = = = = =

Weight Method

2 X 81 + 4 X 80 + 8 X 8-1 + 7 X 8-2 2 X 8 + 4 X 1 + 8 X 0.125 + 7 X 0.015625 16 + 4 + 1 + 0.109375 21.109375

Ques. 2

Prove that

a) a + bc = (a+b) . (a+c)

b) a + a b = a +b.

Sol.

a) a + bc = (a+b) . (a+c)

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

bc 0 0 0 1 0 0 0 1

a+bc 0 0 0 1 1 1 1 1

a+b 0 0 1 1 1 1 1 1

a+c 0 1 0 1 1 1 1 1

(a+b). (a+c) 0 0 0 1 1 1 1 1

Therefore, a + bc = (a+b) . (a+c)

b) a + a b = a +b. a 0 0 1 1 b 0 1 0 1 a 1 1 0 0

ab

a + ab 0 1 1 1

a+b 0 1 1 1

0 1 0 0

Therefore, a + a b = a +b.

Ques. 3

Use Boolean algebra to simplify the logic function and realize the given f= a b c + a b c + a c + bc +abc.

function and minimized function using discrete gates.

Sol.

f= a b c + a b c + a c + bc +abc f= b ( ac + a c ) + a c + bc +abc f= b (1) + a c + bc +abc f= b + a c + bc +abc

Ques. 4 gate.

Reduce the following expression using K map and implement using universal

1. 2.

f= f=

∑(0,2,3,5,6,7,8,9,11,13 ,15 )

m

∑(2,3,5,6,7,9,11,13 ,14 )

m

Sol. 1. f=

∑(0,2,3,5,6,7,8,9,11,13 ,15 )

m

f= bd + ad + a b + a c

2.

f=

∑(2,3,5,6,7,9,11,13 ,14 )

m

f= a c + bc d + b c d + a b d

Ques. 5

Describe the operations performed by the following arithmetic circuits. Half adder Full adder Half subtractor Full subtractor

Ans.

The operations performed by the following arithmetic circuits. HALF ADDER FULL ADDER HALF SUBTRACTOR FULL SUBTRACTOR

1. 2. 3. 4.

Half Adder : These operations were carried by a logic circuit called half adder which accepts two binary digits as its input and produces two binary digits on its output terminals known as submit and carry bit. Full Adder : The full adder accepts three one bit inputs and generates a Sum and a Carry output. Full adder thus accepts one more input for handling carry bits generated during multiple bit addition. i.e. when we want to add two binary numbers, each having two or more bits, the LSBs can be added by using half adder. The carry resulted from the addition of the LSBs is carried forward to the next significant bit addition. Thus the addition requires two bits of the inputs and one carry thus generated in the previous LSB addition. Half Subtractor : It is used to subtract the LSB of the subtrahend from the LSB of the minuend when a binary number is to be subtracted from the other. A logic circuit is

called half adder, which accepts two binary digits as its input and produces two binary digits on its output terminals known as difference bit and borrow bit. Full Subtractor : Half subtractor can be used only for single bit subtraction. If there is borrow during the subtraction of the LSBs, it affects the subtraction in the next higher bit. A logic circuitry, which performs the subtraction of two bits with borrow generated if any, during the previous LSB subtraction, is known as full subtractor.

Ques. 6 Ans.

Explain Master Slave J-K Flip Flop.

Master-slave FFs were developed to make the synchronous operation more predictable. A known time delay is introduced between the time that the FF responds to a clock pulse and the time response appears at its output. It is also known as pulse triggered flip-flop due to the fact that the length of the time required for its output to change state equal the width of one clock pulse. A master-slave FF actually consists of two FFs. One is known as master and the other as slave. Control inputs are applied to the master FF prior to the clock pulse. On the rising edge of the clock pulse output of the master is defined by the control inputs.