Central Processing Unit (CPU

)

Instruction Set Summary
The following table defines the special characters used to describe the effects of instruction execution on the status bits in the condition codes register (SXHINZVC column).

Table 5 Condition Code Changes
Special Character 0 1 Description Status bit not affected by operation. Status bit cleared by operation. Status bit set by operation. Status bit affected by operation.

||

Status bit may be cleared or remain set, but is not set by operation. Status bit may be set or remain cleared, but the final state is not defined. Status bit may be changed by operation but the final state is not defined. Status bit used for a special purpose.

>
||
? !

>

Source Form ABA ABX ABY ADCA #opr8i ADCA opr8a ADCA opr16a ADCA oprx0_xysppc ADCA oprx9,xysppc ADCA oprx16,xysppc ADCA [D,xysppc] ADCA [oprx16,xysppc]

Operation Add B to A; (A)+(B)⇒A

Address Mode INH

Machine Coding (Hex) 18 06 1A E5 19 ED 89 ii 99 dd B9 hh ll A9 xb A9 xb ff A9 xb ee ff A9 xb A9 xb ee ff OO Pf Pf

Access Detail

SXHINZVC
– – ∆ – ∆ ∆ ∆ ∆ – – – – – – – – – – – – – – – – – – ∆ – ∆ ∆ ∆ ∆

Add B to X; (X)+(B)⇒X; assembles as IDX LEAX B,X Add B to Y; (Y)+(B)⇒Y; assembles as IDX LEAY B,Y Add with carry to A; (A)+(M)+C⇒A or IMM (A)+imm+C⇒A DIR EXT IDX IDX1 IDX2 [D,IDX] [IDX2]

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

MC9S12DP256 — Revision 1.1 26 Central Processing Unit (CPU) MOTOROLA

xysppc ANDB [D. (B)•(M)⇒B or (B)•imm⇒B – – – – ∆ ∆ 0 – AND with CCR. same as LSLB Arithmetic shift left D.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc ASL [D. (A)•(M)⇒A or (A)•imm⇒A – – – – ∆ ∆ 0 – AND with B.xysppc] ANDB [oprx16.xysppc ADDA oprx16. (A)+(M)⇒A or (A)+imm⇒A IMM DIR EXT IDX IDX1 IDX2 [D.xysppc] ADDB [oprx16.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc ADDD [D.xysppc] ADDD [oprx16.xysppc ANDB oprx16. (B)+(M)⇒B or (B)+imm⇒B – – ∆ – ∆ ∆ ∆ ∆ Add to D.IDX] [IDX2] INH INH INH 0 C b7 A b0 b7 B b0 – – ∆ – ∆ ∆ ∆ ∆ Add to B.Central Processing Unit (CPU) Instruction Set Summary Source Form ADCB #opr8i ADCB opr8a ADCB opr16a ADCB oprx0_xysppc ADCB oprx9.1 MOTOROLA Central Processing Unit (CPU) 27 .xysppc] ANDA #opr8i ANDA opr8a ANDA opr16a ANDA oprx0_xysppc ANDA oprx9.xysppc ADDB [D.xysppc ADCB oprx16.xysppc] ANDCC #opr8i ASL opr16a ASL oprx0_xysp ASL oprx9.xysppc] ADDA [oprx16.xysppc ADDB oprx16.xysppc] ADDB #opr8i ADDB opr8a ADDB opr16a ADDB oprx0_xysppc ADDB oprx9. (CCR)•imm⇒CCR Arithmetic shift left M. (B)+(M)+C⇒B or IMM (B)+imm+C⇒B DIR EXT IDX IDX1 IDX2 [D.xysppc ADDA [D.xysppc ADCB [D.xysppc] ADDA #opr8i ADDA opr8a ADDA opr16a ADDA oprx0_xysppc ADDA oprx9.xysppc] ANDB #opr8i ANDB opr8a ANDB opr16a ANDB oprx0_xysppc ANDB oprx9.IDX] [IDX2] IMM EXT IDX IDX1 IDX2 [D.xysppc ASL oprx16.xysppc ANDA [D.xysppc ANDA oprx16.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D. same as LSLD – – – – ∆ ∆ ∆ ∆ MC9S12DP256 — Revision 1.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc] ASLA ASLB ASLD Operation Address Mode Machine Coding (Hex) C9 ii D9 dd F9 hh ll E9 xb E9 xb ff E9 xb ee ff E9 xb E9 xb ee ff 8B ii 9B dd BB hh ll AB xb AB xb ff AB xb ee ff AB xb AB xb ee ff CB ii DB dd FB hh ll EB xb EB xb ff EB xb ee ff EB xb EB xb ee ff C3 jj kk D3 dd F3 hh ll E3 xb E3 xb ff E3 xb ee ff E3 xb E3 xb ee ff 84 ii 94 dd B4 hh ll A4 xb A4 xb ff A4 xb ee ff A4 xb A4 xb ee ff C4 ii D4 dd F4 hh ll E4 xb E4 xb ff E4 xb ee ff E4 xb E4 xb ee ff 10 ii 78 hh ll 68 xb 68 xb ff 68 xb ee ff 68 xb 68 xb ee ff 48 58 59 Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPwO rPw rPwO frPwP fIfrPw fIPrPw O O O SXHINZVC – – ∆ – ∆ ∆ ∆ ∆ Add with carry to B.xysppc ADDD oprx16.xysppc] ADDD #opr16i ADDD opr8a ADDD opr16a ADDD oprx0_xysppc ADDD oprx9.xysppc] ASL [oprx16.xysppc] ANDA [oprx16. same as LSLA Arithmetic shift left B.xysppc] ADCB [oprx16. (A:B)+(M:M+1)⇒A:B or (A:B)+imm⇒A:B – – – – ∆ ∆ ∆ ∆ AND with A.IDX] [IDX2] Add to A. same as LSL 0 C b7 b0 ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ – – – – ∆ ∆ ∆ ∆ Arithmetic shift left A.

then (PC)+2+rel⇒PC Branch if < 0.xysppc ASR [D.xysppc. then (PC)+2+rel⇒PC REL REL REL INH REL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Branch if higher. msk8 BCLR opr16a. if Z | (N⊕V)=0.xysppc BITA oprx16. if C=1.xysppc] ASRA ASRB BCC rel8 BCLR opr8a. (B)•(M) or (B)•imm – – – – ∆ ∆ 0 – Branch if ≤ 0.xysppc. if C=0. then REL (PC)+2+rel⇒PC. then (PC)+2+rel⇒PC Branch if minus. msk8 BCLR oprx9.xysppc] BITB [oprx16. unsigned. then (PC)+2+rel⇒PC. REL then (PC)+2+rel⇒PC Branch if higher or same. signed. msk8 BCLR oprx16.IDX] [IDX2] INH INH REL Machine Coding (Hex) 77 hh ll 67 xb 67 xb ff 67 xb ee ff 67 xb 67 xb ee ff 47 57 24 rr 4D dd mm 1D hh ll mm 0D xb mm 0D xb ff mm 0D xb ee ff mm 25 rr 27 rr 2C rr 00 2E rr 22 rr 24 rr Access Detail rPwO rPw rPwO frPwP fIfrPw fIPrPw O O PPP (branch) P (no branch) rPwO rPwP rPwO rPwP frPwPO PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) VfPPP PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) PPP (branch) P (no branch) SXHINZVC – – – – ∆ ∆ ∆ ∆ b7 b0 C Arithmetic shift right A Arithmetic shift right B Branch if C clear. msk8 BCLR oprx0_xysppc. same as BCC Bit test A. msk8 BCS rel8 BEQ rel8 BGE rel8 BGND BGT rel8 BHI rel8 BHS rel8 Operation Arithmetic shift right M Address Mode EXT IDX IDX1 IDX2 [D. (A)•(M) or (A)•imm IMM DIR EXT IDX IDX1 IDX2 [D. if C=1.xysppc] ASR [oprx16. same as BCS Branch if lower or same. (M)•(mask byte)⇒M IDX IDX1 IDX2 Branch if C set.IDX] [IDX2] REL BITA #opr8i BITA opr8a BITA opr16a BITA oprx0_xysppc BITA oprx9. signed. if Z | (N⊕V)=1.xysppc BITA [D. then (PC)+2+rel⇒PC Enter background debug mode Branch if > 0. same as BHS – – – – – – – – – – – – ∆ ∆ 0 – DIR EXT Clear bit(s) in M. if N⊕V=0. if REL C=0.xysppc] BITA [oprx16. if N⊕V=1.unsigned. then (PC)+2+rel⇒PC – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Branch if lower. if N=1. then (PC)+2+rel⇒PC Branch if not equal to 0. if C | Z=0.xysppc BITB [D. if Z=1. then (PC)+2+rel⇒PC REL REL REL REL MC9S12DP256 — Revision 1. if C | Z=1. unsigned. then (PC)+2+rel⇒PC.Central Processing Unit (CPU) Source Form ASR opr16a ASR oprx0_xysppc ASR oprx9. then (PC)+2+rel⇒PC Branch if ≥ 0.1 28 Central Processing Unit (CPU) MOTOROLA .IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc BITB oprx16.xysppc] BLE rel8 BLO rel8 BLS rel8 BLT rel8 BMI rel8 BNE rel8 85 ii 95 dd B5 hh ll A5 xb A5 xb ff A5 xb ee ff A5 xb A5 xb ee ff C5 ii D5 dd F5 hh ll E5 xb E5 xb ff E5 xb ee ff E5 xb E5 xb ee ff 2F rr 25 rr 23 rr 2D rr 2B rr 26 rr – – – – ∆ ∆ 0 – Bit test B. signed. if Z=0.xysppc ASR oprx16.xysppc] BITB #opr8i BITB opr8a BITB opr16a BITB oprx0_xysppc BITB oprx9. same as BLO Branch if equal. then (PC)+2+rel⇒PC. unsigned.signed.

IDX] [IDX2] INH INH IMM IMM DIR EXT IDX IDX1 IDX2 [D. rel8 BRSET oprx16.xysppc.xysppc. assembles as ANDCC #$FE – – – – – – – – BVC rel8 BVS rel8 CALL opr16a. subroutine address⇒PC Compare A to B. if (M)•(mask byte)=0.xysppc] REL REL EXT IDX IDX1 IDX2 [D.xysppc CMPA oprx16. (PPG)⇒MSP.xysppc CLR [D. msk8. msk8 BSET opr16a. then (PC)+2+rel⇒PC Call subroutine in expanded memory.xysppc. rel8 BSET opr8. page CALL [D. rel8 BRCLR oprx9. then (PC)+2+rel⇒PC Address Mode REL REL DIR EXT IDX IDX1 IDX2 REL DIR EXT IDX IDX1 IDX2 DIR EXT IDX IDX1 IDX2 REL Machine Coding (Hex) 2A rr 20 rr 4F dd mm rr 1F hh ll mm rr 0F xb mm rr 0F xb ff mm rr 0F xb ee ff mm rr 21 rr 4E dd mm rr 1E hh ll mm rr 0E xb mm rr 0E xb ff mm rr 0E xb ee ff mm rr 4C dd mm 1C hh ll mm 0C xb mm 0C xb ff mm 0C xb ee ff mm 07 rr Access Detail PPP (branch) P (no branch) PPP rPPP rfPPP rPPP rfPPP PrfPPP P rPPP rfPPP rPPP rfPPP PrfPPP rPwO rPwP rPwO rPwP frPwPO SPPP SXHINZVC – – – – – – – – – – – – – – – – – – – – – – – – Branch never Branch if bit(s) set. $00⇒M Clear A. page CALL oprx16.xysppc. rel8 BRCLR oprx16. xysppc] CBA CLC CLI CLR opr16a CLR oprx0_xysppc CLR oprx9. rel8 BRSET opr16a. (M) | (mask byte)⇒M – – – – ∆ ∆ 0 – Branch to subroutine.xysppc] CMPA [oprx16. pg⇒PPAGE register. if N=0. assembles as ANDCC #$FD – – – – – – 0 – – – – – ∆ ∆ ∆ ∆ Compare A. msk8. (A)–(B) Clear C. (PC)+2+rel⇒PC Branch if V clear. msk8. if V=0. RTNH:RTNL⇒MSP:MSP+1.xysppc. rel8 BRCLR opr16a. then (PC)+2+rel⇒PC – – – – – – – – – – – – – – – – Set bit(s) in M. assembles as ANDCC #$EF Clear M. rel8 BRSET oprx9. if (M)•(mask byte)=0. msk8.IDX] [IDX2] 28 rr 29 rr 4A hh ll pg 4B xb pg 4B xb ff pg 4B xb ee ff pg 4B xb 4B xb ee ff 18 17 10 FE 10 EF 79 hh ll 69 xb 69 xb ff 69 xb ee ff 69 xb 69 xb ee ff 87 C7 10 FD 81 ii 91 dd B1 hh ll A1 xb A1 xb ff A1 xb ee ff A1 xb A1 xb ee ff PPP (branch) P (no branch) PPP (branch) P (no branch) gnSsPPP gnSsPPP gnSsPPP fgnSsPPP fIignSsPPP fIignSsPPP OO P P PwO Pw PwO PwP PIfw PIPw O O P P rPf rPO rPf rPO frPP fIfrPf fIPrPf – – – – – – – – – – – – – – – – – – – – – – – – – – – – ∆ ∆ ∆ ∆ – – – – – – – 0 – – – 0 – – – – – – – – 0 1 0 0 Clear I. page CALL oprx9. msk8 BSET oprx0_xysppc.Central Processing Unit (CPU) Instruction Set Summary Source Form BPL rel8 BRA rel8 BRCLR opr8a. msk8 BSET oprx9. rel8 BRSET oprx0_xysppc.1 MOTOROLA Central Processing Unit (CPU) 29 . (SP)–1⇒SP.xysppc CLR oprx16.xysppc] CLRA CLRB CLV CMPA #opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xysppc CMPA oprx9. (SP)–2⇒SP. $00⇒B Clear V. msk8.xysppc CMPA [D. (SP)–2⇒SP. then (PC)+2+rel⇒PC Branch if V set. msk8. if V=1. rel8 BRCLR oprx0_xysppc. then (PC)+2+rel⇒PC Branch always Branch if bit(s) clear. msk8 BSET oprx16. $00⇒A Clear B. msk8.xysppc] CALL [oprx16. (A)–(M) or (A)–imm MC9S12DP256 — Revision 1. RTNH:RTNL⇒MSP:MSP+1. msk8.IDX] [IDX2] INH IMM IMM EXT IDX IDX1 IDX2 [D.xysppc. page CALL oprx0_xysppc.xysppc. msk8 BSR rel8 Operation Branch if plus.xysppc. msk8. msk8. rel8 BRN rel8 BRSET opr8.xysppc] CLR [oprx16.

xysppc] CMPB [oprx16. (B)–(M) or (B)–imm Address Mode IMM DIR EXT IDX IDX1 IDX2 [D.xysppc CPD oprx16. rel9 Decrement and branch if not equal to 0.xysppc] CPY [oprx16.xysppc] CPD [oprx16.1 30 Central Processing Unit (CPU) MOTOROLA .Central Processing Unit (CPU) Source Form CMPB #opr8i CMPB opr8a CMPB opr16a CMPB oprx0_xysppc CMPB oprx9. then branch 04 lb rr – – – – – – – – MC9S12DP256 — Revision 1. (Y)–(M:M+1) or (Y)–imm IMM DIR EXT IDX IDX1 IDX2 [D.xysppc CPX oprx16. if (counter)=0.xysppc CPX [D.xysppc CPY [D.xysppc COM [D. (A)=$FF–(A)⇒A Complement B.xysppc] COM [oprx16. rel9 Operation Compare B. (B)=$FF–(B)⇒B Compare D.xysppc CPY oprx16.IDX] [IDX2] INH INH IMM DIR EXT IDX IDX1 IDX2 [D.IDX] [IDX2] Decimal adjust A for BCD Decrement and branch if equal to 0.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc] CPS [oprx16. (9-bit) if (counter)≠0. (SP)–(M:M+1) or (SP)–imm – – – – ∆ ∆ ∆ ∆ Compare X. (A:B)–(M:M+1) or (A:B)–imm – – – – ∆ ∆ ∆ ∆ Compare SP.xysppc] CPS #opr16i CPS opr8a CPS opr16a CPS oprx0_xysppc CPS oprx9.xysppc CPD [D. (counter)–1⇒counter.xysppc CPS oprx16.xysppc] COM opr16a COM oprx0_xysppc COM oprx9. REL (counter)–1⇒counter.IDX] [IDX2] EXT IDX IDX1 IDX2 [D.xysppc] CPY #opr16i CPY opr8a CPY opr16a CPY oprx0_xysppc CPY oprx9.xysppc] CPX #opr16i CPX opr8a CPX opr16a CPX oprx0_xysppc CPX oprx9.xysppc CPS [D.xysppc] CPX [oprx16.xysppc CMPB oprx16. (M)=$FF–(M)⇒M – – – – ∆ ∆ 0 1 Complement A.xysppc CMPB [D.IDX] [IDX2] Compare Y.IDX] [IDX2] Machine Coding (Hex) C1 ii D1 dd F1 hh ll E1 xb E1 xb ff E1 xb ee ff E1 xb E1 xb ee ff 71 hh ll 61 xb 61 xb ff 61 xb ee ff 61 xb 61 xb ee ff 41 51 8C jj kk 9C dd BC hh ll AC xb AC xb ff AC xb ee ff AC xb AC xb ee ff 8F jj kk 9F dd BF hh ll AF xb AF xb ff AF xb ee ff AF xb AF xb ee ff 8E jj kk 9E dd BE hh ll AE xb AE xb ff AE xb ee ff AE xb AE xb ee ff 8D jj kk 9D dd BD hh ll AD xb AD xb ff AD xb ee ff AD xb AD xb ee ff 18 07 04 lb rr Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf rPwO rPw rPwO frPwP fIfrPw fIPrPw O O PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf OfO PPP (branch) PPO (no branch) PPP (branch) PPO (no branch) SXHINZVC – – – – ∆ ∆ ∆ ∆ Complement M. (X)–(M:M+1) or (X)–imm IMM DIR EXT IDX IDX1 IDX2 [D.xysppc] COMA COMB CPD #opr16i CPD opr8a CPD opr16a CPD oprx0_xysppc CPD oprx9. then branch INH REL (9-bit) – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ? ∆ – – – – – – – – DBNE abdxysp.xysppc COM oprx16.xysppc] DAA DBEQ abdxysp.

(X)–1⇒X Decrement Y. (M:M+1)]⇒D. (Y)–1⇒Y – – – – – – – – – – – – – ∆ – – – – – – – ∆ – – – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ Extended divide.xysppc] EMINM oprx0_xysppc EMINM oprx9. (MX:MX+1)×(MY:MY+1)+ (M~M+3)⇒M~M+3. V. V.xysppc] EMAXM [oprx16. put smaller of 2 unsigned 16-bit values in D.IDX] [IDX2] 88 ii 98 dd B8 hh ll A8 xb A8 xb ff A8 xb ee ff A8 xb A8 xb ee ff – – – – ∆ ∆ 0 – MC9S12DP256 — Revision 1. (A)⊕(M)⇒A or (A)⊕imm⇒A EORA #opr8i EORA opr8a EORA opr16a EORA oprx0_xysppc EORA oprx9.xysppc] EORA [oprx16.IDX] [IDX2] IDX IDX1 IDX2 [D. (M:M+1)]⇒M:M+1. remainder⇒D Extended divide.SP Decrement X.IDX] [IDX2] INH INH IDX INH INH Machine Coding (Hex) 73 hh ll 63 xb 63 xb ff 63 xb ee ff 63 xb 63 xb ee ff 43 53 1B 9F 09 03 11 18 14 18 12 hh ll Access Detail rPwO rPw rPwO frPwP fIfrPw fIPrPw O O Pf O O ffffffffffO OffffffffffO ORROfffRRfWWP SXHINZVC – – – – ∆ ∆ ∆ – Decrement A. C bits reflect result of internal compare [(D)–(M:M+1)] Extended minimum in M. (D)×(Y)⇒Y:D.xysppc DEC [D. MAX[(D). MIN[(D). V.1 MOTOROLA Central Processing Unit (CPU) 31 .xysppc EMAXM oprx16. C bits reflect result of internal compare [(D)–(M:M+1)] Extended multiply.xysppc EMINM oprx16. unsigned.xysppc EMINM [D. MIN[(D).xysppc] EMIND [oprx16. N.xysppc] IMM DIR EXT IDX IDX1 IDX2 [D. (D)×(Y)⇒Y:D. put smaller of 2 unsigned 16-bit values in M. C bits reflect result of internal compare [(D)–(M:M+1)] Extended maximum in M. 16 by 16 to 32-bit EMAXD oprx0_xysppc EMAXD oprx9. (M:M+1)]⇒M:M+1.IDX] [IDX2] IDX IDX1 IDX2 [D.xysppc] EMAXM oprx0_xysppc EMAXM oprx9. 16 by 16 to 32-bit Exclusive OR A. (SP)–1⇒SP.xysppc EMIND oprx16. MAX[(D). C bits reflect result of internal compare [(D)–(M:M+1)] Extended minimum in D.xysppc EMAXD oprx16.IDX] [IDX2] IDX IDX1 IDX2 [D. 32 by 16 to INH 16-bit.IDX] [IDX2] INH INH 18 1A xb 18 1A xb ff 18 1A xb ee ff 18 1A xb 18 1A xb ee ff 18 1E xb 18 1E xb ff 18 1E xb ee ff 18 1E xb 18 1E xb ee ff 18 1B xb 18 1B xb ff 18 1B xb ee ff 18 1B xb 18 1B xb ee ff 18 1F xb 18 1F xb ff 18 1F xb ee ff 18 1F xb 18 1F xb ee ff 13 18 13 ORPf ORPO OfRPP OfIfRPf OfIPRPf ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ORPf ORPO OfRPP OfIfRPf OfIPRPf ORPW ORPWO OfRPWP OfIfRPW OfIPRPW ffO OfO OffO (if followed by page 2 instruction) P rPf rPO rPf rPO frPP fIfrPf fIPrPf – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ – ∆ – – – – ∆ ∆ – ∆ Extended multiply.Central Processing Unit (CPU) Instruction Set Summary Source Form DEC opr16a DEC oprx0_xysppc DEC oprx9. (Y:D)÷(X)⇒Y.xysppc EMAXD [D. signed. Special signed.xysppc EORA oprx16. V.xysppc] EMUL EMULS IDX IDX1 IDX2 [D. (A)–1⇒A Decrement B. Z. N. 16 by 16 to 32-bit Extended maximum in D.xysppc DEC oprx16. (M)–1⇒M Address Mode EXT IDX IDX1 IDX2 [D. assembles as LEAS –1.xysppc EMAXM [D. remainder⇒D Extended multiply and accumulate.xysppc EMIND [D. Z.xysppc] DEC [oprx16. 32 by 16 to INH 16-bit. (Y:D)÷(X)⇒Y. put larger of 2 unsigned 16-bit values in D.xysppc] EMINM [oprx16. N.xysppc] EMIND oprx0_xysppc EMIND oprx9. unsigned. put larger of 2 unsigned 16-bit values in M. (B)–1⇒B Decrement SP. N.xysppc] EMAXD [oprx16. (M:M+1)]⇒D. Z. signed.xysppc EORA [D.xysppc] DECA DECB DES DEX DEY EDIV EDIVS EMACS opr16a Operation Decrement M. Z.

xysppc] LBCC rel16 18 10 18 15 72 hh ll 62 xb 62 xb ff 62 xb ee ff 62 xb 62 xb ee ff 42 52 1B 81 08 02 06 hh ll 05 xb 05 xb ff 05 xb ee ff 05 xb 05 xb ee ff 17 dd 16 hh ll 15 xb 15 xb ff 15 xb ee ff 15 xb 15 xb ee ff 18 24 qq rr – – – – – ∆ 0 ∆ – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ – Increment A. remainder⇒D Increment M.IDX] [IDX2] INH INH IDX INH INH EXT IDX IDX1 IDX2 [D. then branch INH B7 eb P – – – – – – – – FDIV IBEQ abdxysp. (D)÷(X)⇒X. 16 by 16-bit. then branch Integer divide. 16 by 16-bit. r1 and r2 same size or $00:(r1)⇒r2. rel9 Increment and branch if not equal to 0. (A)+1⇒A Increment B.1 32 Central Processing Unit (CPU) MOTOROLA .abcdxysp Exchange register contents. RTNH:RTNL⇒MSP:MSP+1. r2=8-bit Fractional divide. (D)÷(X)⇒X. (9-bit) if (counter)≠0.xysppc] INCA INCB INS INX INY JMP opr16a JMP oprx0_xysppc JMP oprx9.xysppc] JSR [oprx16. (Y)+1⇒Y Jump.xysppc INC oprx16. same as LBHS – – – – – – – – MC9S12DP256 — Revision 1.xysppc INC [D.Central Processing Unit (CPU) Source Form EORB #opr8i EORB opr8a EORB opr16a EORB oprx0_xysppc EORB oprx9. No extensions or indirect addressing allowed. 16 by 16-bit. if (counter)=0. subroutine address⇒PC – – – – – – – – Long branch if C clear. assembles as LEAS 1. IDX 16-bit. (SP)+1⇒SP.xysppc EORB oprx16. subroutine address⇒PC – – – – – – – – – – – – – ∆ – – – – – – – ∆ – – – – – – – – – – Jump to subroutine. (counter)+1⇒counter.xysppc] INC [oprx16. (SP)–2⇒SP. (X)+1⇒X Increment Y. remainder⇒D Integer divide.IDX] [IDX2] REL 04 lb rr – – – – – – – – IDIV IDIVS INC opr16a INC oprx0_xysppc INC oprx9. (B)⊕(M)⇒B or (B)⊕imm⇒B Address Mode IMM DIR EXT IDX IDX1 IDX2 [D. EXG abcdxysp.xysppc JSR oprx16.xysppc] JSR opr8a JSR opr16a JSR oprx0_xysppc JSR oprx9. r1=8-bit. (B)+1⇒B Increment SP.SP Increment X.IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D. initialize B with fractional part of lookup value. then (PC)+4+rel⇒PC.xysppc] JMP [oprx16. if C=0. (M:M+1)+[(B)× ((M+2:M+3)–(M:M+1))]⇒D – – – – ∆ ∆ – ∆ Before executing ETBL.xysppc] EORB [oprx16. (r1)⇔(r2).xysppc JSR [D. INH (D)÷(X)⇒X.xysppc JMP [D. remainder⇒D Increment and branch if equal to 0.xysppc] ETBL oprx0_xysppc Operation Exclusive OR B. (M)+1⇒M INH EXT IDX IDX1 IDX2 [D.IDX] [IDX2] Machine Coding (Hex) C8 ii D8 dd F8 hh ll E8 xb E8 xb ff E8 xb ee ff E8 xb E8 xb ee ff 18 3F xb Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf ORRffffffP SXHINZVC – – – – ∆ ∆ 0 – Extended table lookup and interpolate.xysppc JMP oprx16. r2=16-bit or (r1L)⇔(r2).xysppc EORB [D. r1=16-bit. initialize index register to point to first table entry (M:M+1). unsigned. signed. rel9 INH REL (9-bit) 18 11 04 lb rr OffffffffffO PPP (branch) PPO (no branch) PPP (branch) PPO (no branch) OffffffffffO OffffffffffO rPwO rPw rPwO frPwP fIfrPw fIPrPw O O Pf O O PPP PPP PPP fPPP fIfPPP fIfPPP SPPP SPPP PPPS PPPS fPPPS fIfPPPS fIfPPPS OPPP (branch) OPO (no branch) – – – – – ∆ ∆ ∆ – – – – – – – – IBNE abdxysp. REL (counter)+1⇒counter.

if C=0. if REL Z | (N⊕V)=1. REL then (PC)+4+rel⇒PC. if C=1. then (PC)+4+rel⇒PC Long branch if V set. (M)⇒A or imm⇒A REL REL REL REL REL REL REL REL IMM DIR EXT IDX IDX1 IDX2 [D. same as LBLO Long branch if equal. if V=0. then (PC)+4+rel⇒PC Long branch if plus. if N=1. unsigned. if N=0. same as LBCC REL REL LBLE rel16 LBLO rel16 Long branch if ≤ 0. REL if C | Z=1.xysppc] LDAA [oprx16.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D. signed.xysppc] 18 23 qq rr 18 2D qq rr 18 2B qq rr 18 26 qq rr 18 2A qq rr 18 20 qq rr 18 21 qq rr 18 28 qq rr 18 29 qq rr 86 ii 96 dd B6 hh ll A6 xb A6 xb ff A6 xb ee ff A6 xb A6 xb ee ff C6 ii D6 dd F6 hh ll E6 xb E6 xb ff E6 xb ee ff E6 xb E6 xb ee ff – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ∆ ∆ 0 – Load B. signed.xysppc LDAA oprx16. then (PC)+4+rel⇒PC Address Mode REL REL REL Machine Coding (Hex) 18 25 qq rr 18 27 qq rr 18 2C qq rr 18 2E qq rr 18 22 qq rr 18 24 qq rr Access Detail OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) OPPP OPO OPPP (branch) OPO (no branch) OPPP (branch) OPO (no branch) P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf SXHINZVC – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Long branch if > 0. then (PC)+4+rel⇒PC Long branch always Long branch never Long branch if V clear. same as LBCS Long branch if lower or same. then (PC)+4+rel⇒PC Load A. if V=1. then (PC)+4+rel⇒PC Long branch if ≥ 0. if N⊕V=1. then (PC)+4+rel⇒PC.xysppc LDAA [D. then (PC)+4+rel⇒PC Long branch if higher or same. if C | Z=0. unsigned. if Z=0. if C=1. unsigned.1 MOTOROLA Central Processing Unit (CPU) 33 . unsigned.IDX] [IDX2] 18 2F qq rr 18 25 qq rr – – – – – – – – – – – – – – – – LBLS rel16 LBLT rel16 LBMI rel16 LBNE rel16 LBPL rel16 LBRA rel16 LBRN rel16 LBVC rel16 LBVS rel16 LDAA #opr8i LDAA opr8a LDAA opr16a LDAA oprx0_xysppc LDAA oprx9. if Z=1. then (PC)+4+rel⇒PC Long branch if not equal to 0.Central Processing Unit (CPU) Instruction Set Summary Source Form LBCS rel16 LBEQ rel16 LBGE rel16 LBGT rel16 LBHI rel16 LBHS rel16 Operation Long branch if C set.then (PC)+4+rel⇒PC Long branch if < 0. signed. then (PC)+4+rel⇒PC Long branch if minus.then (PC)+4+rel⇒PC. signed.xysppc LDAB oprx16. then (PC)+4+rel⇒PC Long branch if lower.xysppc LDAB [D.xysppc] LDAB #opr8i LDAB opr8a LDAB opr16a LDAB oprx0_xysppc LDAB oprx9. if N⊕V=0.xysppc] LDAB [oprx16. (M)⇒B or imm⇒B – – – – ∆ ∆ 0 – MC9S12DP256 — Revision 1. then (PC)+4+rel⇒PC Long branch if higher. if REL Z | (N⊕V)=0.

same as ASLD C b7 A b0 b7 B b0 – – – – ∆ ∆ ∆ ∆ LSR opr16a LSR oprx0_xysppc LSR oprx9. same as ASL 0 C b7 b0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – ∆ ∆ ∆ ∆ Logical shift left A.xysppc] LDS [oprx16.Central Processing Unit (CPU) Source Form LDD #opr16i LDD opr8a LDD opr16a LDD oprx0_xysppc LDD oprx9. same as ASLB Logical shift left D.xysppc] LDD [oprx16.IDX] [IDX2] INH INH 74 hh ll 64 xb 64 xb ff 64 xb ee ff 64 xb 64 xb ee ff 44 54 rPwO rPw rPwO frPwP fIfrPw fIPrPw O O – – – – 0 ∆ ∆ ∆ MC9S12DP256 — Revision 1. (M:M+1)⇒SP or imm⇒SP – – – – ∆ ∆ 0 – Load X.xysppc LDY oprx16. effective address⇒Y Logical shift left M. (M:M+1)⇒X or imm⇒X – – – – ∆ ∆ 0 – Load Y.xysppc LEAS oprx16.xysppc] LDX #opr16i LDX opr8a LDX opr16a LDX oprx0_xysppc LDX oprx9.xysppc] LDY [oprx16.xysppc LDS oprx16.xysppc LDD [D.1 34 Central Processing Unit (CPU) MOTOROLA . (M:M+1)⇒A:B or imm⇒A:B Address Mode IMM DIR EXT IDX IDX1 IDX2 [D. same as ASLA Logical shift left B.xysppc] LDY #opr16i LDY opr8a LDY opr16a LDY oprx0_xysppc LDY oprx9.xysppc LEAY oprx0_xysppc LEAY oprx9. effective address⇒X Load effective address into Y.xysppc] LSRA LSRB Logical shift right M 0 b7 b0 C Logical shift right A Logical shift right B EXT IDX IDX1 IDX2 [D.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc LDD oprx16.xysppc LDY [D.xysppc LEAY oprx16.xysppc] LSLA LSLB LSLD Operation Load D.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc LSR oprx16.xysppc] LSR [oprx16.xysppc] LSL [oprx16.IDX] [IDX2] INH INH INH 0 Machine Coding (Hex) CC jj kk DC dd FC hh ll EC xb EC xb ff EC xb ee ff EC xb EC xb ee ff CF jj kk DF dd FF hh ll EF xb EF xb ff EF xb ee ff EF xb EF xb ee ff CE jj kk DE dd FE hh ll EE xb EE xb ff EE xb ee ff EE xb EE xb ee ff CD jj kk DD dd FD hh ll ED xb ED xb ff ED xb ee ff ED xb ED xb ee ff 1B xb 1B xb ff 1B xb ee ff 1A xb 1A xb ff 1A xb ee ff 19 xb 19 xb ff 19 xb ee ff 78 hh ll 68 xb 68 xb ff 68 xb ee ff 68 xb 68 xb ee ff 48 58 59 Access Detail PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf Pf PO PP Pf PO PP Pf PO PP rOPw rPw rPOw frPPw fIfrPw fIPrPw O O O SXHINZVC – – – – ∆ ∆ 0 – Load SP.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.xysppc] LEAS oprx0_xysppc LEAS oprx9.xysppc LSL oprx16.xysppc LDS [D.xysppc LSR [D.xysppc LDX [D. (M:M+1)⇒Y or imm⇒Y – – – – ∆ ∆ 0 – Load effective address into SP.xysppc LDX oprx16.xysppc] LDX [oprx16.xysppc LSL [D.IDX] [IDX2] IDX IDX1 IDX2 IDX IDX1 IDX2 IDX IDX1 IDX2 EXT IDX IDX1 IDX2 [D.xysppc] LDS #opr16i LDS opr8a LDS opr16a LDS oprx0_xysppc LDS oprx9.xysppc LEAX oprx0_xysppc LEAX oprx9.xysppc LSL opr16a LSL oprx0_xysppc LSL oprx9. effective address⇒SP Load effective address into X.xysppc LEAX oprx16.

IDX] [IDX2] IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX IMM-EXT IMM-IDX EXT-EXT EXT-IDX IDX-EXT IDX-IDX INH EXT IDX IDX1 IDX2 [D.xysppc MAXA oprx16. (M)]⇒A. oprx0_xysppc byte-move. first operand MOVB opr16a. (M1)⇒M2.xysppc] MAXA [oprx16.Central Processing Unit (CPU) Instruction Set Summary Source Form LSRD Operation Logical shift right D 0 b7 A b0 b7 B b0 C Address Mode INH Machine Coding (Hex) 49 O Access Detail SXHINZVC – – – – 0 ∆ ∆ ∆ MAXA oprx0_xysppc MAXA oprx9.xysppc] 18 19 xb 18 19 xb ff 18 19 xb ee ff 18 19 xb 18 19 xb ee ff 18 1D xb 18 1D xb ff 18 1D xb ee ff 18 1D xb 18 1D xb ee ff 18 0B ii hh ll 18 08 xb ii 18 0C hh ll hh ll 18 09 xb hh ll 18 0D xb hh ll 18 0A xb xb 18 03 jj kk hh ll 18 00 xb jj kk 18 04 hh ll hh ll 18 01 xb hh ll 18 05 xb hh ll 18 02 xb xb 12 70 hh ll 60 xb 60 xb ff 60 xb ee ff 60 xb 60 xb ee ff 40 50 A7 OrPf OrPO OfrPP OfIfrPf OfIPrPf OrPw OrPwO OfrPwP OfIfrPw OfIPrPw OPwP OPwO OrPwPO OPrPw OrPwP OrPwO OPWPO OPPW ORPWPO OPRPW ORPWP ORPWO O rPwO rPw rPwO frPwP fIfrPw fIPrPw O O O – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ MOVB #opr8. MIN[(A). C bits reflect result of internal compare [(A)–(M)] IDX IDX1 IDX2 [D. MAX[(A).xysppc] MEM Maximum in A: put larger of 2 unsigned 8-bit values in A.xysppc] MAXM oprx0_xysppc MAXM oprx9. (M)]⇒M. V. (A)=current crisp input value. unsigned.IDX] [IDX2] 18 18 xb 18 18 xb ff 18 18 xb ee ff 18 18 xb 18 18 xb ee ff 18 1C xb 18 1C xb ff 18 1C xb ee ff 18 1C xb 18 1C xb ee ff 01 OrPf OrPO OfrPP OfIfrPf OfIPrPf OrPw OrPwO OfrPwP OfIfrPw OfIPrPw RRfOw – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ Determine grade of membership. Z. put larger of 2 unsigned 8-bit values in M. opr16a specifies byte to move MOVB opr16a. oprx0_xysppc Move word.xysppc MINM oprx16. MOVW opr16a.xysppc] MAXM [oprx16.xysppc NEG [D.IDX] [IDX2] IDX IDX1 IDX2 [D. opr16a MOVB oprx0_xysppc.xysppc] MINA [oprx16. Z. MAX[(A). oprx0_xysppc specifies word to move MOVW oprx0_xysppc.xysppc MAXA [D. (M)]⇒M. oprx0_xysppc MOVB oprx0_xysppc. opr16a (M1:M1+1)⇒M2:M2+1. oprx0_xysppc MUL NEG opr16a NEG oprx0_xysppc NEG oprx9.xysppc] NEGA NEGB NOP Multiply.xysppc] MINM oprx0_xysppc MINM oprx9. 0–(M)⇒M or (M)+1⇒M – – – – – – – – – – – – – – – – – – – – – – – ∆ – – – – ∆ ∆ ∆ ∆ Negate A.xysppc NEG oprx16. C bits reflect result of internal compare [(A)–(M)] Maximum in M.xysppc MINA [D. N. N. if (A)<P1 or (A)>P2 then µ=0. S1. MIN[(A).1 MOTOROLA Central Processing Unit (CPU) 35 . 0–(B)⇒B or (B)+1⇒B No operation – – – – – – – – MC9S12DP256 — Revision 1. X points at fuzzy input (RAM location) Minimum in A. (A)×(B)⇒A:B Negate M. V. (M)]⇒A. put smaller of 2 unsigned 8-bit values in A. 0–(A)⇒A or (A)+1⇒A Negate B. $FF]. C bits reflect result of internal compare [(A)–(M)] Minimum in N. X points at 4-byte data describing trapezoidal membership function (P1.IDX] [IDX2] INH INH INH – – ? – ? ? ? ? MINA oprx0_xysppc MINA oprx9.IDX] [IDX2] IDX IDX1 IDX2 [D. N. C bits reflect result of internal compare [(A)–(M)] IDX IDX1 IDX2 [D. opr16a MOVW #opr16i.xysppc] MINM [oprx16. else µ= MIN[((A)–P1)×S1. put smaller of 2 unsigned 8-bit values in M. opr16a MOVW oprx0_xysppc. Special µ (grade)⇒MY. N. opr16a Move byte.xysppc MAXM oprx16.xysppc] NEG [oprx16.xysppc MINM [D. oprx0_xysppc 16-bit word-move. memory-to-memory MOVW #oprx16.xysppc MAXM [D. Z. V. S2). V. first operand MOVW opr16a. P2. (P2–(A))×S2. (X)+4⇒X. (Y)+1⇒Y. Z. 8 by 8-bit. memory-to-memory 8-bit MOVB #opr8i.xysppc MINA oprx16.

(MSP)⇒B. (SP)–2⇒SP.Central Processing Unit (CPU) Source Form ORAA #opr8i ORAA opr8a ORAA opr16a ORAA oprx0_xysppc ORAA oprx9. (SP)+1⇒SP Pull CCR. (SP)+1⇒SP Pull B.xysppc] ORCC #opr8i PSHA PSHB PSHC PSHD PSHX PSHY PULA PULB PULC PULD PULX PULY REV Operation OR accumulator A. (B) | (M)⇒B or (B) | imm⇒B – – – – ∆ ∆ 0 – OR CCR. (YH:YL)⇒MSP:MSP+1 Pull A. (SP)+1⇒SP Pull D. (SP)–1⇒SP. (SP)–2⇒SP.xysppc ORAB [D. store to rule outputs unless fuzzy output is already larger Special 18 3B ORf(t^Tx)O* or ORf(r^ffRf)O** ffff+ORft^*** ffff+ORfr^**** – – ? – ? ? ∆ ! *When weighting is not enabled. (SP)+2⇒SP Pull X.xysppc ORAA [D.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D. REVW Rule evaluation. **** These are additional cycles caused by an interrupt when weighting is enabled: ffff is the exit sequence and ORfr^ is the re-entry sequence.xysppc] ORAB #opr8i ORAB opr8a ORAB opr16a ORAB oprx0_xysppc ORAB oprx9. rule weights optional. **When weighting is enabled.xysppc ORAA oprx16. (MSP:MSP+1)⇒A:B.xysppc ORAB oprx16. The ^ denotes a check for pending interrupt requests. The ^ denotes a check for pending interrupt requests. (CCR) | imm⇒CCR Push A. (B)⇒MSP ⇑ – ⇑ ⇑ ⇑ ⇑ ⇑ ⇑ – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆ – – – – – – – – – – – – – – – – – – – – – – – – – – ? – ? ? ∆ ? Push CCR.1 36 Central Processing Unit (CPU) MOTOROLA . (SP)–1⇒SP. ***These are additional cycles caused by an interrupt when weighting is not enabled: ffff is the exit sequence and ORft^ is the re-entry sequence. (A:B)⇒MSP:MSP+1 Push X. MC9S12DP256 — Revision 1.xysppc] ORAB [oprx16. (A)⇒MSP Push B. (MSP:MSP+1)⇒XH:XL. (MSP:MSP+1)⇒YH:YL. (SP)+2⇒SP Rule evaluation. find smallest rule input. (XH:XL)⇒MSP:MSP+1 Push Y. (CCR)⇒MSP INH Push D. the t^Tx loop is executed once for each element in the rule list. the t^Tx loop is replaced by r^ffRf. weighted. (MSP)⇒A. (SP)+2⇒SP Pull Y.IDX] [IDX2] IMM INH INH Machine Coding (Hex) 8A ii 9A dd BA hh ll AA xb AA xb ff AA xb ee ff AA xb AA xb ee ff CA ii DA dd FA hh ll EA xb EA xb ff EA xb ee ff EA xb EA xb ee ff 14 ii 36 37 39 3B 34 35 32 33 38 3A 30 31 18 3A Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P Os Os Os OS OS OS ufO ufO ufO UfO UfO UfO Orf(t^tx)O* ff+Orft^** SXHINZVC – – – – ∆ ∆ 0 – OR accumulator B. **These are additional cycles caused by an interrupt: ff is the exit sequence and Orft^ is the re-entry sequence. (MSP)⇒CCR. store to rule outputs unless fuzzy output is already larger INH INH INH INH INH INH INH INH INH Special *The t^tx loop is executed once for each element in the rule list. find smallest rule input. (SP)–2⇒SP. (A) | (M)⇒A or (A) | imm⇒A Address Mode IMM DIR EXT IDX IDX1 IDX2 [D. unweighted. (SP)–1⇒SP.xysppc] ORAA [oprx16.

xysppc] SEC SEI SEV SEX abc. assembles as ORCC #$01 Set I. (SP)+1⇒SP.(SP)+4⇒SP Return from subroutine.xysppc] SBCA [oprx16.xysppc SBCB [D.(SP)+4⇒SP.xysppc ROR oprx16. INH (MSP)⇒CCR.IDX] [IDX2] INH INH EXT IDX IDX1 IDX2 [D. (MSP:MSP+1)⇒PCH:PCL.xysppc SBCA oprx16. assembles as ORCC #$02 Sign extend.Central Processing Unit (CPU) Instruction Set Summary Source Form ROL opr16a ROL oprx0_xysppc ROL oprx9. (MSP:MSP+1)⇒XH:XL.IDX] [IDX2] IMM IMM IMM INH 18 16 82 ii 92 dd B2 hh ll A2 xb A2 xb ff A2 xb ee ff A2 xb A2 xb ee ff C2 ii D2 dd F2 hh ll E2 xb E2 xb ff E2 xb ee ff E2 xb E2 xb ee ff 14 01 14 10 14 02 B7 eb OO P rPf rPO rPf rPO frPP fIfrPf fIPrPf P rPf rPO rPf rPO frPP fIfrPf fIPrPf P P P P – – – – ∆ ∆ ∆ ∆ – – – – ∆ ∆ ∆ ∆ Subtract with carry from B. (SP)+1⇒SP. (SP)+2⇒SP Subtract B from A.(SP)+2⇒SP. $00:(r1)⇒r2 if r1 bit 7 is 0 or $FF:(r1)⇒r2 if r1.IDX] [IDX2] INH INH INH Machine Coding (Hex) 75 hh ll 65 xb 65 xb ff 65 xb ee ff 65 xb 65 xb ee ff 45 55 76 hh ll 66 xb 66 xb ff 66 xb ee ff 66 xb 66 xb ee ff 46 56 0A Access Detail rPwO rPw rPwO frPwP fIfrPw fIPrPw O O rPwO rPw rPwO frPwP fIfrPw fIPrPw O O uUnfPPP SXHINZVC – – – – ∆ ∆ ∆ ∆ C b0 Rotate left A Rotate left B Rotate right M b0 b7 – – – – ∆ ∆ ∆ ∆ C Rotate right A Rotate right B Return from call. (SP)+2⇒SP – – – – – – – – RTI Return from interrupt.dxysp INH IMM DIR EXT IDX IDX1 IDX2 [D.xysppc ROR [D.xysppc] SBCB #opr8i SBCB opr8a SBCB opr16a SBCB oprx0_xysppc SBCB oprx9. 8-bit r1 to 16-bit r2. (B)–(M)–C⇒B or (B)–imm–C⇒B – – – – ∆ ∆ ∆ ∆ Set C.xysppc SBCA [D. assembles as ORCC #$10 Set V. alternate mnemonic for TFR r1. bit 7 is 1. r2 – – – – – – – 1 – – – 1 – – – – – – – – – – 1 – – – – – – – – – MC9S12DP256 — Revision 1.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D. (MSP:MSP+1)⇒PCH:PCL.xysppc] SBCB [oprx16. (MSP)⇒PPAGE.1 MOTOROLA Central Processing Unit (CPU) 37 .xysppc] ROL [oprx16.xysppc] ROLA ROLB ROR opr16a ROR oprx0_xysppc ROR oprx9.xysppc] RORA RORB RTC Rotate left M b7 Operation Address Mode EXT IDX IDX1 IDX2 [D. RTS 3D UfPPP – – – – – – – – SBA SBCA #opr8i SBCA opr8a SBCA opr16a SBCA oprx0_xysppc SBCA oprx9. (MSP:MSP+1)⇒B:A.xysppc] ROR [oprx16.(SP)+2⇒SP. (A)–(M)–C⇒A or (A)–imm–C⇒A INH 0B uUUUUPPP or uUUUUfVfPPP* ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆ *RTI takes 11 cycles if an interrupt is pending.xysppc SBCB oprx16. (MSP:MSP+1)⇒PCH:PCL.xysppc ROL oprx16.xysppc ROL [D. (MSP:MSP+1)⇒YH:YL. (A)–(B)⇒A Subtract with carry from A.

xysppc SUBA [D.xysppc STD oprx16. (A)⇒M Address Mode DIR EXT IDX IDX1 IDX2 [D.IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D. (A:B)⇒M:M+1 – – – – ∆ ∆ 0 – Stop processing. (B)⇒M – – – – ∆ ∆ 0 – Store D.xysppc STY [D.xysppc STS [D.xysppc] STX opr8a STX opr16a STX oprx0_xysppc STX oprx9.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D.IDX] [IDX2] INH Machine Coding (Hex) 5A dd 7A hh ll 6A xb 6A xb ff 6A xb ee ff 6A xb 6A xb ee ff 5B dd 7B hh ll 6B xb 6B xb ff 6B xb ee ff 6B xb 6B xb ee ff 5C dd 7C hh ll 6C xb 6C xb ff 6C xb ee ff 6C xb 6C xb ee ff 18 3E Access Detail Pw PwO Pw PwO PwP PIfw PIPw Pw PwO Pw PwO PwP PIfw PIPw PW PWO PW PWO PWP PIfW PIPW OOSSSSsf (enter stop mode) fVfPPP (exit stop mode) ff (continue stop mode) OO (if stop mode disabled by S=1) PW PWO PW PWO PWP PIfW PIPW PW PWO PW PWO PWP PIfW PIPW PW PWO PW PWO PWP PIfW PIPW P rPf rPO rPf rPO frPP fIfrPf fIPrPf SXHINZVC – – – – ∆ ∆ 0 – Store accumulator B.xysppc] STAB opr8a STAB opr16a STAB oprx0_xysppc STAB oprx9.Central Processing Unit (CPU) Source Form STAA opr8a STAA opr16a STAA oprx0_xysppc STAA oprx9. stop all clocks Store SP.xysppc SUBA oprx16. (YH:YL)⇒MSP:MSP+1.xysppc] SUBA [oprx16. (SP)–2⇒SP.xysppc] STY opr8a STY opr16a STY oprx0_xysppc STY oprx9.xysppc] DIR EXT IDX IDX1 IDX2 [D. RTNH:RTNL⇒MSP:MSP+1. (XH:XL)⇒MSP:MSP+1.IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D. (SP)–2⇒SP.xysppc STS oprx16. (SP)–2⇒SP. (YH:YL)⇒M:M+1 – – – – ∆ ∆ 0 – Subtract from A.xysppc] STX [oprx16.xysppc] STAA [oprx16.xysppc STAA [D.xysppc STD [D.xysppc STX oprx16. (SP)–2⇒SP.xysppc STAB [D. (A)–(M)⇒A or (A)–imm⇒A – – – – ∆ ∆ ∆ ∆ MC9S12DP256 — Revision 1.xysppc STAA oprx16. (B:A)⇒MSP:MSP+1.IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D.IDX] [IDX2] DIR EXT IDX IDX1 IDX2 [D.xysppc] STY [oprx16.xysppc STY oprx16.xysppc STAB oprx16. (SPH:SPL)⇒M:M+1 – – – – – – – – STS opr8a STS opr16a STS oprx0_xysppc STS oprx9.IDX] [IDX2] 5F dd 7F hh ll 6F xb 6F xb ff 6F xb ee ff 6F xb 6F xb ee ff 5E dd 7E hh ll 6E xb 6E xb ff 6E xb ee ff 6E xb 6E xb ee ff 5D dd 7D hh ll 6D xb 6D xb ff 6D xb ee ff 6D xb 6D xb ee ff 80 ii 90 dd B0 hh ll A0 xb A0 xb ff A0 xb ee ff A0 xb A0 xb ee ff – – – – ∆ ∆ 0 – Store X.xysppc] STOP Operation Store accumulator A. (SP)–1⇒SP.xysppc] STD [oprx16.xysppc STX [D.xysppc] STAB [oprx16.xysppc] STS [oprx16.xysppc] STD opr8a STD opr16a STD oprx0_xysppc STD oprx9. (CCR)⇒MSP. (XH:XL)⇒M:M+1 – – – – ∆ ∆ 0 – Store Y.xysppc] SUBA #opr8i SUBA opr8a SUBA opr16a SUBA oprx0_xysppc SUBA oprx9.1 38 Central Processing Unit (CPU) MOTOROLA .

(trap vector)⇒PC Test M.xysppc SUBD oprx16.xysppc SUBD [D. (A:B)–(M:M+1)⇒A:B or (A:B)–imm⇒A:B – – – – ∆ ∆ ∆ ∆ Software interrupt. (XH:XL)⇒MSP:MSP+1.Central Processing Unit (CPU) Instruction Set Summary Source Form SUBB #opr8i SUBB opr8a SUBB opr16a SUBB oprx0_xysppc SUBB oprx9. (SP)–2⇒SP. (SP)–2⇒SP.xysppc SUBB [D. RTNH:RTNL⇒MSP:MSP+1. (A)–0 Test B. Reset uses a variation of VfPPP. (B:A)⇒MSP:MSP+1.xysppc] SUBB [oprx16.rel9 TBL oprx0_xysppc TBNE abdxysp. then (PC)+2+rel⇒PC Table lookup and interpolate. (r1)⇒r2. (SP)–1⇒SP.xysppc] SUBD [oprx16.IDX] [IDX2] INH Machine Coding (Hex) C0 ii D0 dd F0 hh ll E0 xb E0 xb ff E0 xb ee ff E0 xb E0 xb ee ff 83 jj kk 93 dd B3 hh ll A3 xb A3 xb ff A3 xb ee ff A3 xb A3 xb ee ff 3F Access Detail P rPf rPO rPf rPO frPP fIfrPf fIPrPf PO RPf RPO RPf RPO fRPP fIfRPf fIPRPf VSPSSPSsP* SXHINZVC – – – – ∆ ∆ ∆ ∆ Subtract from D. (A)⇒B Transfer A to CCR. assembles as TFR CCR .abcdxysp INH INH INH REL (9-bit) IDX REL (9-bit) INH 18 0E B7 02 18 0F 04 lb rr 18 3D xb 04 lb rr B7 eb OO P OO PPP (branch) PPO (no branch) ORfffP PPP (branch) PPO (no branch) P – – – – ∆ ∆ 0 – ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆ – – – – ∆ ∆ 0 – – – – – – – – – – – – – ∆ ∆ – ∆ – – – – – – – – – – – – – – – – or ∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆ TPA TRAP trapnum INH INH B7 20 18 tn tn = $30–$39 or tn = $40–$FF P OVSPSSPSsP – – – – – – – – – – – 1 – – – – TST opr16a TST oprx0_xysppc TST oprx9.xysppc TST [D.xysppc SUBB oprx16. (CCR)⇒MSP. (SP)–2⇒SP. r2=8-bit Transfer CCR to A. 8-bit. then (PC)+2+rel⇒PC Transfer register to register.xysppc] TSTA TSTB Test A.xysppc] SWI Operation Subtract from B. r2=16-bit or (r1L)⇒r2.xysppc] SUBD #opr16i SUBD opr8a SUBD opr16a SUBD oprx0_xysppc SUBD oprx9. r1 and r2 same size or $00:(r1)⇒r2. (B)–0 EXT IDX IDX1 IDX2 [D. TAB TAP TBA TBEQ abdxysp.IDX] [IDX2] IMM DIR EXT IDX IDX1 IDX2 [D. (M)+[(B)×((M+1)–(M))]⇒A Test and branch if not equal to 0. (B:A)⇒MSP:MSP+1. (SWI vector)⇒PC Transfer A to B. (YH:YL)⇒MSP:MSP+1. (YH:YL)⇒MSP:MSP+1.xysppc] TST [oprx16.xysppc TST oprx16.rel9 TFR abcdxysp. (SP)–2⇒SP. CCR Transfer B to A. (SP)–2⇒SP.IDX] [IDX2] INH INH F7 hh ll E7 xb E7 xb ff E7 xb ee ff E7 xb E7 xb ee ff 97 D7 rPO rPf rPO frPP fIfrPf fIPrPf O O – – – – ∆ ∆ 0 0 MC9S12DP256 — Revision 1. (CCR)⇒MSP. if (register)≠0.A Trap unimplemented opcode. (M)–0 – – – 1 – – – – *The CPU also uses VSPSSPSsP for hardware interrupts and unimplemented opcode traps. 1⇒I.1⇒I.1 MOTOROLA Central Processing Unit (CPU) 39 . (SP)–2⇒SP. (B)–(M)⇒B or (B)–imm⇒B Address Mode IMM DIR EXT IDX IDX1 IDX2 [D. assembled as TFR A. (SP)–1⇒SP. (SP)–2⇒SP. RTNH:RTNL⇒MSP:MSP+1. (CCR)⇒A. (SP)–2⇒SP. r1=8-bit. (A)⇒CCR. if (register)=0. (XH:XL)⇒MSP:MSP+1. (B)⇒A Test and branch if equal to 0. r1=16-bit.

**The frr^ffff sequence is the loop for one iteration of SOP and SOW recovery. Y points at first element in Fi list. (CCR)⇒MSP Address Mode INH INH INH INH INH Machine Coding (Hex) B7 75 B7 76 B7 57 B7 67 3E P P P P Access Detail SXHINZVC – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – OSSSSsf (before interrupt) fVfPPP (after interrupt) or – – – 1 – – – – or – 1 – 1 – – – – WAV Calculate weighted average. X. sum of Special products (SOP) and sum of weights (SOW)* 18 3C Of(frr^ffff)O** SSS+UUUrr^*** – – ? – ? ∆ ? ? ∑ Si Fi ⇒ Y:D i=1 B B ∑ Fi ⇒ X i=1 *Initialize B. XGDX XGDY Exchange D with X. (SP)–2⇒SP. (Y)⇒SP. (B:A)⇒MSP:MSP+1. (D)⇔(Y). (SP)–2⇒SP. ***These are additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence.Central Processing Unit (CPU) Source Form TSX TSY TXS TYS WAI Operation Transfer SP to X. (SP)⇒X.Y Transfer X to SP. wavr* Resume executing interrupted WAV Special 3C UUUrr^ffff(frr^ ffff)O** SSS+UUUrr^*** – – ? – ? ∆ ? ? *wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0. RTNH:RTNL⇒MSP:MSP+1. The ^ denotes a check for pending interrupt requests. assembles as TFR Y. All Si and Fi elements are 8-bit values.SP Transfer Y to SP. Y INH INH B7 C5 B7 C6 P P – – – – – – – – – – – – – – – – MC9S12DP256 — Revision 1. assembles as EXG D. X Exchange D with Y. (SP)–2⇒SP. **The frr^ffff sequence is the loop for one iteration of SOP and SOW accumulation. assembles as TFR X. assembles as EXG D. (X)⇒SP. (SP)⇒Y. X points at first element in Si list. (SP)–2⇒SP.X Transfer SP to Y. (SP)–1⇒SP.SP Wait for interrupt. (D)⇔(X). assembles as TFR SP. The ^ denotes a check for pending interrupt requests. and Y: B= number of elements. (XH:XL)⇒MSP:MSP+1. ***These are additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence. (YH:YL)⇒MSP:MSP+1. assembles as TFR SP.1 40 Central Processing Unit (CPU) MOTOROLA . Intermediate values use six stack bytes.

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