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立 成 功 大 學 電 機 工 程 學 系 碩 士 論 文

正交分頻多工技術之電力線通訊系統研究 與 FPGA 實現
Study and FPGA Implementation of Powerline Communication System using OFDM Signals
研 究 生:許世杰 指導教授:蘇賜麟 Student:Shih-Chieh Hsu Advisor:Szu-Lin Su

Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C. Thesis for Master of Science June, 2004

中華民國九十三年六月

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正交分頻多工技術之電力線通訊系統研究與 FPGA 硬體 實現
許世杰* 蘇賜麟**

國立成功大學電機工程系碩士班通訊與網路組

摘要
電力線遍及每一個有人存在的角落,就其分佈密度而言,電力線網路是世界上 最大的網路,只要將裝置插進牆壁上插座,即可同時獲取電源又能傳輸資料,是個 完美的通訊平台。雖然有很多人懷疑使用電力系統作為網際網路傳輸媒介之可靠性 及實用性,但電力線通訊技術將來如有重大的突破想必一定能使人類的通訊更加方 便。 本 論 文 著 重 於 電 力 線 通 訊 系 統 之 實 體 層 硬 體 實 現 , 參 考 HomePlug 1.0 Specification 所定義之實體層通訊技術(正交分頻多工之技術),內容包含有 OFDM symbol timing 同步 Sampling Clock Offset 所造成的影響與錯誤控制編碼 系統在 SPW 、 。 上模擬完成確定可行後,再進行硬體實作,硬體實作方面採用 Xilinx 公司之 VirtexE 型號之 FPGA 來實現,設計流程採硬體描述語言(Verilog)之設計方式,並設計 A/D 、 D/A 轉換器、濾波器與放大器電路,以架構完整之基頻通訊系統。

* 作者 ** 指導教授

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and implement with the hardware description language (Verilog).0 Specification. First. we adopt the FPGA of VirtexE Family of Xilinx Inc. It’s indeed a perfect communication platform. power line network is actually the biggest network all over the world.C Abstract Power line is found almost everywhere. According to the distributed density. are designed to construct the complete baseband communication system. filter. then the information will be transmitted over the power line channel and power will be also supplied simultaneously. R. amplifier and etc. The contents are composed of OFDM symbol timing synchronization. We just plug the device into outlets. Taiwan.O. * ** The Author The Advisor ii . The circuits of A/D. Tainan. In the hardware implementation.Study and FPGA Implementation of Powerline Communication System using OFDM Signals Shih-Chieh Hsu * Szu-Lin Su** Department of Electrical Engineering National Cheng Kung University. although many people doubt its reliability and practicability to make use of power line system as the communication medium of internet network. It must be more convenient for our communication in the future if we make a significant breakthrough on the technique of power line communication. we finish the system simulation in SPW and confirm that the system is practical with the hardware implementation. D/A. This thesis focuses on the implementation of the physical layer of powerline communication system according to HomePlug 1. the effect of sampling clock offset and error control code.

致 謝 感謝指導教授 蘇賜麟老師的悉心指導,本論文才得以順利完成。並感謝口試委 員林茂昭教授、呂忠津教授、蘇育德教授及鐘嘉德教授的批評與指教,使本論文更臻 完善;此外並且感謝實驗室的學長、同學及學弟們,在這些日子來互相鼓勵,尤其是 古耀揚、翁立昌的協助。感謝學長黃健華及蘇益生在模擬上的幫助與學弟正雄及信源 在理論與實作上的幫忙。在研究所的求學生涯,和這一群伙伴們分享著快樂及甘苦, 都將是人生中美好的回憶。 最後,要向我親愛的家人與女友致上最深的謝意,感謝你們的鼓勵與關心,使我 充滿著信心來迎接未來的挑戰。 iii .

............................................................................. 12 3......................................4 Attenuation ........................................................................................................................................3 Channel Noises........................................................................................ 7 2.... 10 3....................................................................... 4 2..............................................................................................................................2 System Specification ............................ 6 2.................................. 10 3......2....... ii Contents................................. 23 iv .................Contents 摘要................. 1 1................2............................................................................................................... 13 3....................2.........6 Signal Generation...............5 Mapping and Demapping ....................................................... 3 Chapter 2 Channel Characteristics of Power Line ...................................................................................... vii Chapter 1 Introduction ........... 16 3....................................................2 Impedance of Residential Power Line Channel ............................................................................................................................................4 Preamble...............1 Intra-Building Power Line Circuit .................................1 Overview of Power Line Communications........................................................................... 17 3.....................................................3 OFDM Symbols .................................................5 Multipath Effect ....................................................................................0 Standard ................................. i Abstract ...........................2......................................................3 Interleaver........................................... 9 Chapter 3 Homeplug 1.......................................1 Scrambler ......2 Outlines ............. 18 3........................................................................................................................................ 13 3.................................................................................... iiiv List of Tables ....................................................... 20 3......................2............................................ 4 2.................................................................................. 4 2.....................................................................2.................................... 22 Chapter 4 Description of the implemented system .......... 1 1.......................................................... 15 3..........................................................................3 Simulation .............2 Convolutional Encoder/ Viterbi Decoder ............2..................1 Basic Principle of OFDM................... vi List of Figures .......

....4 Upsampling ........... 28 5..........7 Smooth Filter......................................................... 39 v ........................................................................................ 30 5................................ 33 5................................................................... 24 4............3 Effect of Sampling Clock Offset .............................................................................. 27 Chapter 5 Hardware Design and Implementation ........ 28 5...... 30 5..... 31 5........ 23 4......................5 Digital to Analog Converter Circuit .............1................................2 The Protocol of the Transmission Interface ....................1.................................................................................................... 32 5.......................................................... 32 5.............................................................. 33 Chapter 6 Conclusion ......................................1......1.........................6 Analog to Digital Converter Circuit ..................1.........1........................................1.2 Implementation............................ 28 Bibliography.............2 Symbol Timing Synchronization..................................................................................................................................1...............................1 Testing Environment ........................................................1 System specifications .....................................................................8 Coupling Circuit........................... 38 5....1 Hardware Design..........3 The Architecture of the FFT........4...... 29 5.................................................................................................................................

...................................... 2 Table 3....................5 Encoding table ....................2 OFDM symbol specifics... 17 Table 3........................ 18 Table 3.................................................List of Tables Table 1.................................................3 Phase vector......................................................................................................................................1 Shift table for ROBO interleaver......................................................................................................... 19 Table 3..........................4 Modulation scheme ..............1 Transmit spectrum limits .. 19 Table 4.................................. 16 Table 3............1 System parameter specification.............................................................................. 24 vi ....................

................7 Indoor attenuation....................................................... 3............................5 Memory structure for Viterbi decoder...................... 2............................List of Figures Fig.................................................... 3.................13 BER vs............ 15 Fig................. 3.1 EN 50065-1 signal levels representation compliant for A......................................................... 3................3 Power line impedance............................6 Equivalent circuit of a differential length ∆z of a transmission line.................. 3...................5 Compound of various noises is measured in power spectrum.............. Eb/N0 under an AWGN channel...................2 An example of OFDM Transceiver...........................................1 The OFDM transceiver over power line channel for the implementation system......................... 16 Fig.. 23 vii ................................................................................................. 14 Fig................ ....................................................... 22 Fig........... 12 Fig.......... C and D bands......8 Outdoor attenuation.... .......................... 5 Fig..1 (a) Residential power and (b) Commercial/industrial three-phase power delivery scheme..................................................... ...................... constraint length=7 convolutional encoder................ 3..........................................2 Transmit spectrum mask... 3......... 2 Fig....................10 Signal structure...11 (a) DBPSK and ROBO (b) DQPSK...................................................................3 Data Scrambler.........................1 FFT-based OFDM System................ B.... 2....................... ..... 4......... 2......7 Bit interleaver................ 6 Fig.................... 2...... 14 Fig.......... 8 Fig............................................... 20 Fig................ 20 Fig... 8 Fig.......4 Coupling factor due to Impedance mismatch...... ...................2 Measurement result of the overall coupling loss in our laboratory.......................................... .............. 8 Fig................................ 3............ 1... 2........... ... 3 Fig............................................................... ........ 3.... 3.................4 rate-1/2..........8 ROBO interleaver.... 5 Fig................. 13 Fig... 3.................... 3.......... 2.... ......................... ...... 18 Fig................................. 5 Fig...... 7 Fig....................................................... 13 Fig.... 12 Fig...........9 OFDM symbol timing.............................. 17 Fig................... 1..............6 Path trace-back circuitry.......................................... 2..................... 3............ 2...................12 Signal generation....................

................................... 5.............4 Radix-4 architecture...... 5.......................... 36 Fig.................................................................. ............... 4.... 33 Fig........5 FFT processor.......................... 5..............19 BER versus Eb/N0 for DBPSK under an AWGN channel.................9 Input configuration of the AC-coupling and dual supply amplifier.. a hard-decision Viterbi decoder and interleaver scheme (f) ROBO..... 5.... ....... 34 Fig.............15 Measurement result with a hard-decision Viterbi decoder....... ..... 5................................................. 5...... 5........................ ...... . 26 Fig....................11 Coupling circuit....... 29 Fig............ 4.................... 32 Fig............................ 4........................4 Synchronization method.......5 Flow chart of the synchronization method...........................................Fig....... ... 5......................... 5..... 5............ 29 Fig.......................................................... ................ 37 Fig.... .13 (a) Power spectrum of noises (b) Power spectrum of the received signal for receiver over power line channel.. 23 Fig. 5..... 5...... ........................................... 5...........1 Testing environment..................... 31 Fig...7 Digital lowpass filter.16 (a) DBPSK scheme (b) ROBO scheme (c) DBPSK and a hard-decision Viterbi decoder scheme (d) ROBO and a hard-decision Viterbi decoder scheme scheme (e) DBPSK.................................................. 36 Fig...................................16 ..... 5............................................... 31 Fig...........3 CRC .......... 4....14 (a) A frame in the transmitter (b) A frame in the receiver.............. 5.................17 (a) Digital and DAC circuits (b) Amplifier circuit in the transmitter........... 37 viii .........................8 Difference amplifier provides differential to single-ended conversion........ 29 Fig........................ 5. 5...........................................................................................................12 Power spectrum of OFDM signal (DC~10MHz).................. 31 Fig........... 34 Fig.6 Differential detection in the time domain.......................... 5........2 Transmission timing diagram in the transmitter........10 Smoothing filter............... 30 Fig........ 4................. 25 Fig........................................................................ 27 Fig. ....................18 (a) Digital and ADC circuits (b) Amplifier circuit in the receiver.......... 35 Fig............. a hard-decision Viterbi decoder and interleaver scheme............. 26 Fig....................2 Signal structure........ 30 Fig................................................... .. 5............. ...........................3 Autocorrelation for the entire frame..............................................................6 System for sampling rate increase by 2......... 32 Fig.......................... 35 Fig...........................

As compared with radio. and forcing devices to transmit for less than a second. the data rates are limited to several kbits/s [1].6MHz and 10MHz to home access and the range 1 . As the degree of automation of distribution networks increase. It assigns the frequencies comprised between 1. but they can almost reach all the equipment connected to the power lines. respecting security times. such as the impulsive interference. The purpose of the subband B. For example. In the beginning. some kinds of the noise. it defines the access protocol for the C band that a device has to use.Chapter 1 Introduction Chapter 1 Introduction 1. C and D. But there are also some difficulties in the use of power line channels. they do not need any special infrastructure (such as base stations). In Europe.1. The band is divided into four subbands called A. C. Power line communication (PLC) systems have a long history. This has caused a lot of manufactures to develop their products. communication facilities are needed for the medium voltage (MV) and low voltage (LV) power levels. The standards of powerline communications are divided into the following two groups. and D is for the general use. various impedance. therefore. However. all countries that belong to CENELEC organization have to fit EN 50065-1 that regulates powerline communication. It restricts both the maximum signal amplitude (134 dBµV ) and the frequency rang (3 kHz to 148. The future ETSI TS 101 867 recommendation will regulate the transmission over mains used for Powerline Telecommunications (PLC) devices oriented to home Internet access. EN 50062 does not specify the type of modulation that the user has to use. power line communication systems offer several advantages.1 Overview of Power Line Communications A power line system is used not only for the transmission of power but also as a medium for data communication and the control of electric appliances. loading effects of electrical appliances. and so on.5 kHz) composed of the four subbands shown in Fig 1. they are well established on high voltage (HV) power lines for the measurement of loading and automation. B. attenuation.

according to HomePlug 1.49 MHz to 20. Table 1.5 Fig. 1.2.1 EN 50065-1 signal levels representation compliant for A.1 and Fig. In America. the frequency range from 4.Chapter 1 Introduction comprised between 10MHz and 30MHz for the sole purpose of distributing this signal to homes [2].7 MHz is defined.0 Spec. and the power spectrum density of signal is shown in Table 1. The Maximum PHY Layer payload rate of approximately 13 Mbps with an effective throughput is comparable to 10BASE-T Ethernet. B. defined by HomePlug Powerline Alliance composed of North American countries.1 Transmit spectrum limits Voltage 134dB µV 120dB µV 116dB µV Licensed operators Users Industrial use Broad band modu lation Regular use D-Band A-Band B-Band C-Band 3 9 Frequency(KHz) 95 125 140 148. 1. C and D bands. 2 .

2 Transmit spectrum mask. A brief conclusion is made in Chapter 6.0 Standard is described in Chapter 3 and the description of the implemented system is shown in Chapter 4. We will discuss symbol timing synchronization and the effect caused by the clock frequency offset.Chapter 1 Introduction Fig. A traditional frequency shift key (FSK) modulation scheme has poor efficiency. 4] over the power line channel.0 Specification to achieve the excellent bandwidth efficiency and the communication reliability over power line channel. The OFDM system with the channel coding is very robust in presence of narrowband interferers. Homeplug 1. In this thesis. 1. Modulation schemes have been shown in paper [1] that MV system uses Orthogonal Frequency Division Multiplex (OFDM). impulsive noise and frequency selective fading (high group delay distortion). Hardware design and implementation are shown in Chapter 5. whereas LV system is based on fast frequency hoping spread spectrum (SS-FFH) modulation. it implies that data rate is decreased and the bandwidth efficiency is low. 1. In Chapter 2. Direct Sequence spread spectrum (DSSS) modulation scheme is also used in [3. 3 . Although spread spectrum techniques provide processing gain.2 Outlines This thesis describes the OFDM system architecture for the implementation. we adopt OFDM technique according to HomePlug 1. and Quadrature Amplitude Modulation (QAM) has higher noise sensibility than the spread spectrum modulations. the channel characteristic is described.

1a [6]. as a function of frequency. 2. The noises on residential power line channel can be categorized into five types: colored background noise.3 [8]. narrow-band noise. and frequency. 2. The measurement result of the overall coupling loss in our laboratory is shown in Fig.2. Commercial and industrial buildings are typically supplied with three-phase power as shown in Fig. multipath model is proposed in [5]. for the 36 sampled lines is shown in Fig. but the change of the frequency response of power line channel is slow. and mean values of absolute impedance. Channel characteristics of power line vary with the environment. receiver’s input impedance must be matched to the power line characteristic impedance. periodic asynchronous noise and asynchronous aperiodic impulsive noise. 2. To guarantee maximum power transfer between transmitter and receiver. The frequency-varying channel impedance at different environment will result in coupling loss due to mismatch between transmitter/receiver and power line channel. time.Chapter 2 Channel Characteristics of Power Line Chapter 2 Channel Characteristics of Power Line The well-known issues of power line communication include severe attenuation. 4 . A composite plot of the minimum.1b. maximum. Therefore. 2.1 Intra-Building Power Line Circuit The power in residential houses or apartment units is typically supplied from a distribution transformer as shown in Fig.2 Impedance of Residential Power Line Channel From circuit theory we know that a maximum transfer of power from a given voltage source to a load occurs under matched conditions when the load impedance is the complex conjugate of the source impedance [7]. 2. Multiple echoes of the transmitted signal are received due to the impedance mismatches resulted from various loads connected to the power network. periodic synchronous impulsive noise. variable line impedance and various noises. 2.

2.1 (a)Residential power and (b)Commercial/industrial three-phase power delivery scheme.3 Power line impedance.2 Measurement result of the overall coupling loss in our laboratory. Fig.Chapter 2 Channel Characteristics of Power Line (a) (b) Fig. Fig. 2. 2. 5 .

we can find that the compound of various noises in low frequency is larger than in high frequency. zChannel + zTx (2. (2. z Rx + zChannel (2. 2.4.1) And coupling factor g out is the degree of coupling the signal from the power line channel with impedance zChannel into receiver with input impedance z Rx and is given as g out = 1 + rRx where rRx = z Rx − zChannel . Those noises can be categorized into the following five types [13]: Type A: Colored background noise significantly increases toward lower frequency.4 Coupling factor due to impedance mismatch [9].2) The overall coupling factor ginout is given as ginout = gin gout . 2.3) The measurement results of coupling factor caused by impedance mismatch is shown Fig. Type C: Periodic synchronous impulsive noise is caused by silicon controlled 6 . Type B: Narrow-band noise originates from amateur and short wave radio. 2.3 Channel Noises Fig.Chapter 2 Channel Characteristics of Power Line In [4].5 is measured from DC to 10MHz in our laboratory for various outlets. the degree of coupling the signal from transmitter with output impedance zTx into the power line channel with impedance zChannel is given as coupling factor gin g in = 1 + rTx whererTx = zChannel − zTx . 2. in Fig.

Type E: Asynchronous aperiodic impulsive noise is caused by switching transient phenomena using the some appliances.7 and Fig. Type D: Periodic asynchronous impulsive noise is not relative to 50/60Hz AC source. etc.8 [12]. which power spectrum density exhibit a series of harmonics based on 50/60 Hz. 7 . which caused by monitors of PCs or TV at multiples of the 15.4 Attenuation There are two major causes of high frequency attenuation in a powerline communications channel. (2. case a case b case c Fig. it can be given as α = Re[ (R + jωL)(G + jωC)]. 2. 2. 2.Chapter 2 Channel Characteristics of Power Line rectifiers (SCR) within DC power supplies or light dimmers. section.734-kHz horizontal line scanning frequency [10].4) The second is attenuation due to the multipath effect described in the following The measurements of line attenuation in a low-voltage power line network in Germany are shown as Fig. 2. 2.6 shows the equivalent electric circuit of such a line segment [7].5 Compound of various noises is measured in power spectrum. The attenuation of a traveling wave on a transmission line is the real part of the propagation constant. Fig. The first is attenuation due to ohmic effect in the materials that make up the physical channel.

Fig.8 Outdoor attenuation. 2. Fig 2.Chapter 2 Channel Characteristics of Power Line Fig. 8 .6 Equivalent circuit of a differential length ∆z of a transmission line. 2.7 Indoor attenuation.

2 and 1) gi = Weighting factor can be interpreted as the reflection/transmission factors for path i di = length of path i ti = delay of path i 9 .Chapter 2 Channel Characteristics of Power Line 2. a0 . (2. but additional paths must also be considered. A generalized multipath signal propagation model of transfer function is given as H ( f ) = ∑ gi ( f ) e i =1 N jθ gi e − ( a0 + a1 f k ) di e −2 π f τ i . The result is a multipath scenario with frequency selective fading analyzed in [5].a1 = attenuation parameters k = exponent of the attenuation factor(usual value between 0.5 Multipath Effect The heterogeneous structure of power line network with numerous branches and impedance mismatching causes various reflections.5) where i = Number of the path. The phenomenon means that signal propagation does not only have a direct line-of-sight path between transmitter and receiver. These reflections can leads to attenuation rates of 40 dB/km or more [11].

the destroyed bits can be reconstructed with proper forward error correction coding. 3. we only focus on the physical layer and discuss the system performance.1 Basic Principle of OFDM There are several advantages of the OFDM system as compared to traditional single carrier or spread spectrum systems: It achieves a much higher bandwidth efficiency than spread spectrum systems. For example. It is more effective against intersymbol interference (ISI) or group delay distortion cause by the transmission channel than narrowband system because of a longer symbol duration. It allows a flexible allocation and use in a given channel bandwidth. With the flexible choice..0 Spec. In this thesis. Because jammers destroy a few carriers.0 Standard Medium access control (MAC) and physical layer specifications are composed in the Homeplug 1. Furthermore. It is robust for narrowband interference. But there are a few disadvantages of the OFDM system in particular: 10 . it is possible to use two or more noncontiguous subbands for the transmission of a data stream.0 Standard Chapter 3 Homeplug 1. ISI can be completely eliminated by inserting a cyclic prefix between the symbols. the available signal to noise ratio can be allocated optimally for each carrier.Chapter 3 Homeplug 1. It can be made robust against impulsive noise with interleaver and forward error correction coding scheme. Each of the carriers can be modulated individually with different modulation schemes.

several sequential streams of data are transmitted simultaneously with individual sub-band of the entire available bandwidth. The complex values are modulated in a baseband by the inverse-fast Fourier transform (IFFT) and converted back to serial data for transmission. guard time.0 Standard It is more sensitive to inter-channel interference (ICI) resulted from carrier frequency offset and clock frequency offset than a single carrier system. modulation type per subcarrier and type of forward error correction coding. such as 16 QAM or 32 QAM. we can insert an one-tap equalizer between signal demapper and FFT to correct channel distortion. Furthermore. The tap coefficients of the filter are estimated depended on channel information. Fig. The complexity of an OFDM receiver is higher than that of a simple FSK receiver.1) where X [k ] ≡ k data symbol f k ≡ k ∆f . In OFDM system design. because of high peak to average power ratio of an MCM system. 3. Transmitter output back off is higher than a single carrier system. symbol duration. we will have th 1 x[n] = x(nTs ) = N ∑ X [k ]e k =0 N −1 j 2π kn N (3. which illustrates that the incoming serial data is first converted from serial to parallel and grouped into X bits to feed signal mapper to determine complex value of the signal constellation of the corresponding subcarrier.2) where Ts ≡ sampling time. 11 . The receiver performs the inverse process of the transmitter to obtain the information. A Cyclic prefix is inserted between symbols to avoid intersymbol interference (ISI) and interchannel interference (ICI) caused by multipath. In a parallel data transmission system.1 is typical FFT-based OFDM system. symbols are transmitted sequentially with the entire available bandwidth. The OFDM signal x(t ) is obtained by adding the N subcarriers modulated waveforms and given as 1 N −1 x(t ) = ∑ X [k ]e j 2π fk t N k =0 (3. In a conventional serial data system.Chapter 3 Homeplug 1. By sampling x(t ) at t = nTs . subcarrier spacing. we can consider the number of subcarriers. ∆f is subcarrier spacing .

Forward error correction coding (FEC) is applied to the data in the communication packet.0 Standard X bits x[n] d0 Serial Data Input S/P Converter Signal Mapper d1 IFFT d N −1 P/S Cyclic Prefix D/A LPF Channel d0 Serial Data Output P/S Converter Signal Demapper d1 FFT d N −1 S/P Cyclic Prefix Removal LPF A/D Fig.Chapter 3 Homeplug 1. DQPSK and ROBO.2 An example of OFDM transceiver.0 specification places 128 evenly spaced carriers into the frequency band from DC to 25MHz. 12 . 3.1 FFT-based OFDM System. An example of OFDM transceiver is shown in Fig 3. Every carrier can be modulated with BPSK.7MHz) to carrier information. DBPSK. 3.2 System Specification The OFDM system specified in the Homeplug 1. 3. The 84 carriers of these are used for subcarrier index from numbers 23 to 106(or approximately 4.2. Scrambler Convolutional Encoder Bit Interleaver ROBO Interleaver Mapping IFFT Insert Preamble Cyclic Prefix RC Shaping AFE Channel AFE DeScrambler Viterbi Decoder DeInterleaver Demapping FFT Cyclic Prefix Removal Synchronization Detection Fig.49 MHz to 20.

3. 3.0 Standard 3. constraint length=7 convolutional encoder (Fig. 3.1 Scrambler The data scrambler block scrambles the given data to attain a random distribution.2.2.4). 3. The bits in the scrambler shall all be initialized to all ones at the start of process and is shown in Fig.3 Data scrambler. 3.Chapter 3 Homeplug 1.4 Rate-1/2. 13 . x7 x6 x 5 x4 x3 x2 x1 Scrambled Data Out Fig. 3. The generator polynomial is given as S ( x) = x 7 + x 4 + 1. constraint length=7 convolutional encoder.2 Convolutional Encoder/ Viterbi Decoder The bit stream at the output of the scramble block shall be encoded with a standard rate=1/2. The generator polynomial is given as G1 = 7 ' b1111001 G 2 = 7 ' b1011011 X I Y Fig.

FILO block is identical to the trace-back function. In a Viterbi decoder. 3. M em 0 M em 1 M em2 M em3 ACS FILO Idle TB Time TB ACS FILO Idle Idle TB ACS FILO FILO Idle TB ACS Fig. the convolutional encoder shall insert six zero tail bits which are required to return the convolutional encoder to the zero state.6 Path trace-back circuitry. LSB M SB address RAM Fig. 3. This improves the error probability of the convolutional decoder. The TB is trace-back function that uses a digital technique to trace paths back through the underlying code trellis. 3. 14 . namely register exchange method and traceback method. Fig.6). except that the feedback to the shift register is also the output of decoded data. The ACS makes add-compare-select decisions and stores one bit of binary data for each state at each time. This technique uses the contents of a shift register as an address for the memory and uses the output of the RAM to update the contents of the register (Fig.0 Standard When the last bit of data to the convolutional encoder has been received.Chapter 3 Homeplug 1. there are two known memory structure techniques for the storage of survivor sequences from which the decoded information sequence is retrieved.5 Memory structure for Viterbi decoder.5 is the memory structure of traceback method. 3.

7 column-wise. starting in row zero (going from left to right). 15 . and wrapping around to the top (if necessary). The non-interleaved data is written into this matrix row-wise. The number of rows used is equal to 2 times the number of usable carriers per OFDM symbol. Both interleaver methods are illustrated below with an example in which all 84 carriers are usable. The first such matrix (of size up to 168x20) holds the first half of the DQPSK bits. The ROBO Interleaver adds redundancy and shall only be used to interleave data for ROBO modulation.7. Between reading each column a shift of 8 row positions is applied: the first column is read starting in row 0. The matrix fill procedure for DQPSK is similar to the one for DBPSK. Data is read out of the matrix of Fig. going down the column. 3. 3.7) are required to accommodate the doubling in input elements. producing two equal length vectors. All other modulation schemes shall use the Bit Interleaver.3 Interleaver Two separate interleavers are specified. starting at a given element. For DBPSK mode interleaving of a 40 symbol PHY transmission block. the second column is read starting in row 8. and the second matrix holds the second half of DQPSK bits.7 Bit interleaver. 3.Chapter 3 Homeplug 1. The elements of these two matrices are read out in the same order as described for DBPSK. except that two matrices (as depicted in Fig. one 168 x 20 bit matrix is used. the third column is read starting in row 16.0 Standard 3. as illustrated in Fig. Fig.2. 3.

the OFDM signal in the time domain is multiplied by a raised cosine window to reduce the paper of out-of-channel energy. Finally. each logical bit at the input of the interleaver is represented with 4 bits at the output of the interleaver.9 and specifics is identified in Table 3. a 40 symbol PHY transmission block of up to 3360 bits can only hold up to 840 input bits. A shift is applied to the starting row between each read pass as specified in Table 3. Data streams are modulated onto the subcarrier waveforms using a 256-point Inverse Fast Fourier Transform (IFFT).0 Standard The ROBO interleaver additionally introduces redundancy by a factor of four. in ROBO mode.2. Fig. 3.e.8 ROBO interleaver. The last 172 time samples of the IFFT interval are inserted in a guard interval at the front of the IFFT interval to create a cyclic extended OFDM symbol of 428 time samples. i. Table 3.2. as illustrated in Fig.1 Shift table for ROBO interleaver 3..1 . Thus.3 OFDM Symbols The OFDM symbol timing is represented in Fig. 3.8.Chapter 3 Homeplug 1. The interleaved redundant output vector is obtained by reading the interleaver matrix 4 consecutive times. 3. 16 .

4 Preamble The SYNCP symbol consists of the initial phase vector defined in Table 3.3. frame control and data structure is shown in Fig.10.2 OFDM symbol specifics Symbol Description IFFT Interval Cyclic Prefix Interval Extended Symbol Interval Rolloff Interval( β =0.03125 ) Symbol Period Time samples 256 172 428 8 420 T T prefix TE βT Ts 3.Chapter 3 Homeplug 1. The preamble consists of six SYNCP symbols followed by one and a half SYNCM (SYNCP multiplied by -1) symbols with no cyclic prefix between adjacent symbols. The preamble. 17 . 3.2.9 OFDM symbol timing. 3. The preamble signal with the specific phase vector can get a small peak to average power ratio (PAPR) 5.0 Standard Ts T p r e fix TE T βT Fig.14 dB. Table 3.

5 Mapping and Demapping In Table 3.5 is encoding table for BPSK. Table 3.2. For the schemes they can 18 .4. DQPSK and ROBO. ROBO modulation is a robust form of DBPSK that provides the extensive time and frequency diversity to improve the ability of the system to operate under adverse conditions. 3.0 Standard Table 3.Chapter 3 Homeplug 1. For the BPSK scheme we can use directly the constellation position to decide the information bits. The first data symbol shall use the phase vector of the last frame control symbol as its reference. 3. Each frame control symbol shall use the phase vector (defined in Table 3. DBPSK.10 Signal structure.3 Phase vector Subcarrier index Phase Subcarrier index Phase Subcarrier index Phase Subcarrier index Phase Φk ( π ) 0 0 15 15 14 13 12 11 9 7 6 3 1 15 12 9 6 3 15 12 9 Φk ( π ) 4 0 11 7 2 13 8 3 13 7 2 11 5 15 8 1 10 3 11 4 12 Φk ( π ) 4 12 3 11 2 9 0 7 13 3 10 15 5 11 0 5 10 15 3 8 12 Φk ( π ) 0 4 7 11 14 1 4 7 9 11 14 15 1 3 4 5 6 7 7 8 8 k 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 k 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 k 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 k 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 SYNCM SYNCP SYNCP SYNCP SYNCP SYNCP SYNCP SYNCM GI FC1 GI FC2 GI FC3 GI FC4 GI D1 Fig. modulation scheme is shown.3) as its coherent phase reference.

0 Standard be demodulated by using the Equation (3... 3. Ds (k ) is the demapped signal of the k th subcarrier in the s th symbol. Ds (k ) = Ys (k )Y *s −1 (k ) k = 23.106 for DBPSK . Table 3. 24. Initial phases of the first symbol are obtained from the preamble...Chapter 3 Homeplug 1.3) Ys (k ) is the output signal of FFT for the k th subcarrier in the s th symbol.4 Modulation scheme Information Type Frame Control Data Bits per Carrier 1 1 2 Modulation Type Coherent BPSK DBPSK DQPSK Table 3.5 Encoding table BPSK Input bit DBPSK and ROBO Output phase Input bit DQPSK Output phase Output phase Input bit θd 0 θd 0 θd 00 01 Φk Φk Φk Φk + π / 2 Φk + π Φ k + 3π / 2 1 Φk + π 1 Φk + π 11 10 19 . We can decide the information bits according to the individual area in Fig.3). DQPSk (3.11.

0 Standard (a) (b) Fig.2.Chapter 3 Homeplug 1. 3.12 Signal generation.6 Signal Generation In Fig. 3. 3. 3.4) d [0] 23 d [83] * 106 IFFT 150 * 233 S [255] Fig. the IFFT output can be formulated as S [ n] = 2 ∑ d [ k − 23]cos( k = 23 106 2π kn ) 256 S [0] (3.12. 20 .11 (a) DBPSK and ROBO (b) DQPSK.

5 − 0.5 − 0.5cos( ) 8 ⎩ (3.5 ⋅ 256 − 1 The frame control symbol is given as S[n] = w[n] × ∑ cos( k = 23 106 2π k (n − 172) + Φk + θd ) 256 for 0 ≤ n ≤ 428 -1 (3.5cos( ) ⎪ 8 ⎪ w[n] = ⎨ 1 ⎪ π (n − (172 + 256)) ⎪0.5 ⋅ 256 − 7 ≤ n ≤ 7.5cos( ) ⎪ 8 ⎪ w[n] = ⎨ 1 .5 − 0.5cos( ) 8 ⎩ 0≤n≤7 8 ≤ n ≤ 172 + 256 − 8 . 172 + 256 − 7 ≤ n ≤ 172 + 256 − 1 The data symbol is given as ( Φ prev k is the phase of the previous symbol of the same subcarrier k) S[n] = w[n] × ∑ cos( k = 23 106 2π k (n − 172) + Φ prev k + θ d ) 256 for 0 ≤ n ≤ 428 -1 (3.6) where πn ⎧ 0.5 − 0.5cos( ) ⎪ 8 ⎪ 1 w[n] = ⎨ ⎪ π (n − 7.5 − 0.5 ⋅ 256) ⎪0.0 Standard The preamble is given as S [n] = sign × w[n] × ∑ cos( k = 23 106 2π kn + Φk ) 256 for 0 ≤ n ≤ 7.5 × 256 -1 where 0 ≤ n ≤ 6 ⋅ 256 − 1 ⎧1 sign = ⎨ ⎩ −1 6 ⋅ 256 ≤ n ≤ 7. 7.5 − 0.5 ⋅ 256 − 1 πn ⎧ 0.7) where πn ⎧ 0.Chapter 3 Homeplug 1.5) 0≤n≤7 8 ≤ n ≤ 7.5cos( ) 8 ⎩ 21 .5 ⋅ 256 − 8 . ⎪ π (n − (172 + 256)) ⎪0.

and even DBPSK is much better than BPSK in the simulation system. 13. But that only affects the first symbol in DBPSK scheme.Chapter 3 Homeplug 1.3 Simulation The BER v. 3. Eb/N0 under an AWGN channel. therefore. Eb/N0 curve under an AWGN channel is shown in Fig.0 Standard 3. 22 . the phases estimated for those subcarriers in the entire frame are always inaccurate in BPSK scheme. The coding gain obtained in the traditional coherent system is not the same as in the simulation system. We can find that BER of the DBPSK scheme is close to BER of the BPSK scheme.s. Its reason can be explained that the soft value that Viterbi decoder obtains in the simulation system is more incorrect than in the traditional coherent system. The reason of the difference of BER between both in ROBO scheme and in DBPSK scheme under an AWGN channel is explained that the effect of the phase provided by each subcarrier is not all absolutely positive. Fig. The reason is that the initial phases obtained from the preamble for some subcarriers are inaccurate.13 BER vs.

2 Signal structure. Because it is difficult that the real OFDM signal is given by using a very high order or sharp LPF (Low Pass Filter). The SYNCP symbol is composed of the initial phase vector defined in Table 3. 4. We transmit 2048-points preamble signal used for the synchronization before twenty data symbols (Fig. 23 .1. SYNCP SYNCP SYNCP SYNCP SYNCP SYNCP SYNCM SYNCM GI D0 GI D1 GI D19 Preamble Data Fig.1 System specifications A block diagram of the transceiver over power line channel is shown as Fig.2). 4. 4.0 Specification.Chapter 4 Description of the implemented system Chapter 4 Description of the implemented system 4. 4.1.2 according to HomePlug 1.1 The OFDM transceiver over power line channel for the implementation system. Scramble FIFO & Constellation mapping IFFT Cyclic extension Upsampling & LPF DAC & filters Analog Front End Preamble Insertion Frame synchronization Powerline channel FIFO Constellation demapping & FFT Descramble Decyclic extension ADC & filters Analog Front End Fig. The parameter specification of the system for the implementation is defined in the Table 4. we adopt the up-sampling method to achieve our purpose.

Alternatively. The cross-correlation sequence is given as: M −1 m=0 C[n] = ∑ y[n + m]cm (4. Data rate 3. which is real-valued in the baseband OFDM PLC system.2Mbps 4.2 Symbol Timing Synchronization The accuracy of symbol timing depends on the relative length of the guard interval and channel delay spread. since the samples will no longer be free of ISI [14].6 MHz (subcarrier index from 23 to 106) Modulation scheme DBPSK Bit Resolution(ADC & 10bits DAC) Max.1 System parameter specification Sampling rate 16MHz FFT Length 256 Cyclic Prefix Interval 164 OFDM Symbol Period 420 Subcarrier spacing 62. Some algorithms exploit repeated transmission of a known sequence which is generated at the beginning of each frame.1) where y[n] denotes the received sequence. On the other hand.Chapter 4 Description of the implemented system Table 4. we can tolerate symbol timing errors up to the difference between the two lengths. If the length of cyclic prefix is longer than the length of channel response.2) 24 .4 to 6. the receiver performs cross-correlation operation between the known symbols and the received symbols and then the peak of the magnitude of the cross-correlation sequence can be found. if the channel delay spread is equal to the cyclic prefix duration. The autocorrelation sequence is performed over a window of 2M samples and given as [15] r[n] = ∑ y[n + m] y[n + m + M ] m =0 M −1 (4. any shift from the ideal synchronization position will decrease the error rate performance of the system.5kHz Used frequency band 1. The symbol timing can be extracted by performing an autocorrelation operation on the received signal in the time domain and identifying the point where the sequence reaches its maximum value.

Therefore. The gray part is the pilots got from the preamble and is taken as initial phase references. compared with the transmitter.3 Autocorrelation for the entire frame ( r[n] = ∑ y[n + m] y[n + m + 256] ). The synchronization process will be described as follows (Fig. In the implementation system. the starting position of FFT window is in the center of the cyclic prefix as the channel is ideal. 4. 4. Symbol timing synchronization: When r[n] is less than threshold th over the duration of M sampling points. That means phase of each symbol in constellation diagram is compared with the phase on the same subcarrier of the previous OFDM symbol. the minimum value of r[n] can be found. as depicted in Fig. 4.6. Fig.5. In our implementation system. the symbol timing has been decided. When we find the minimum value.Chapter 4 Description of the implemented system where cm ’s are the transmitted preamble samples which are known at the receiver.4): Signal detection: r[n] is bigger than threshold th1 over the certain sampling duration to ensure that the signal we wanted is received and then the signal detection stage enters the stage of symbol timing synchronization.3 to find the minimum value. We can decide the FFT window according to the flow chart in Fig. 4. the phase offset of each subcarrier for the preamble in the receiver is given as 2 π ⋅1 7 4 ⋅ k 256 e − j where k ≡ subcarrier index. 4. m=0 255 25 . Finish: We do not care the phase offset caused by symbol timing error because of the use of the differential detection in the time domain. we exploit the autocorrelation sequence shown in Fig.

Start sum>th1 over the certain sampling duration N Y sum<th N Y count=M-1 N Y count1=0 N Y count1. 4. 4.5 Flow chart of the synchronization method.4 Synchronization method.Chapter 4 Description of the implemented system Preamble t3 t3 t2 th1 + w h ere : t1 = th e certa in d uration from su m less tha n th to m in im u m o f sum t 2 = b a ckw ard d ura tion t 3 = cyclic extensio n d u ra tion + + + + + _ th _ symbol1 M symbol2 t t1 t1 M Fig.Y count++ End N sum<temp_sum count1=count temp_sum=sum Fig. 26 .

Chapter 4 Description of the implemented system Fig.1. 27 . the ICI term I k ' is actually near zero. 4. the phase error caused by the second ICI term is maybe larger than the first 2πε k N in Equation 4.. As a result of using the differential detection in our implementation system.3) The result of the FFT output is given as 1 X [k ] = N ' ∑ r[n]e n =0 N −1 −j 2π k ' n N = 1 X [k ' ]e N − j( 2πε k ' N −1 − j −j N ∑e n =0 2π ((1+ξ ) k − k ' ) n N + 1 N ∑ X [k ]e ' k =0 k ≠k ' N −1 2πε k ' N −1 − j −j N ∑e n =0 2π ((1+ξ ) k − k ' ) n N =X [k ' ]e 2πε k ' N −1 ' )k ) +πξ ( N N ⋅ sin(πξ k ) +I ' πξ k ' ) k N sin( N ' (4.4).4) where k ' is the subcarrier index in the receiver and I k ' is the term of ICI. (4. ' However.. 4.03 ⋅ k N 256 for ξ = 50 ppm between the two adjacent OFDM symbols.. the phase error is left over 2πε k ' 2π ⋅420⋅ξ ⋅k ' 'o = ≈ 0.6 Differential detection in the time domain. N − 1.3 Effect of Sampling Clock Offset The received discrete signal with timing offset ε and sampling clock offset ξ can be formulated as r[n] = ∑ X [ k ]e k =0 N −1 j 2π ((1+ξ ) n −ε ) k N n = 0. If ξ is relatively small enough.

1. 28 . coupling circuits and the interface of parallel port in PC. The Virtex-E device provides the internal block RAMs. 5.1 Testing Environment The method of transmission is based on the frame structure.Chapter 5 Hardware Design and Implementation Chapter 5 Hardware Design and Implementation A detailed description of the hardware architecture and software structure is introduced in this chapter. The PC transmits bits of the fixed length to the modulator. amplifiers. Finally. digital Delay-Locked Loops (DLLs) and Coregen IP functions to design our system easily. The data are modulated to analog signal by the modulator.1 Hardware Design We implement the PLC communication system with both the hardware device of the Virtex-600E FPGA and the software tool of the ISE 5. 5. The receiver performs the inverse process of the transmitter to obtain the transmitted data. The hardware of PLC system is composed of the Virtex-E FPGA. and then the signal is received over power line channel by the demodulator. a smoothing filter. analog to digital and digital to analog converters.1. we will demonstrate the efforts of the implementation for our PLC system.

1. CE(PC) RDY(modulator) Tx_clk(PC) D0(PC) 0 1 2 1679 1680 1695 0 1 2 Fig. CRC .2 The Protocol of the Transmission Interface The transmission protocol is defined by ourselves. as depicted in Fig.16 Polynomial : G(x) = x16 + x12 + x 5 +1 ones complement Fig. 5. the PC sends the clock enable (CE) signal to talk the modulator and then the modulator sends the ready (RDY) signal to the PC to start the transmission. 5. The CRC-16 is an error-checking code which ensures the transmission reliability between the PC and the modulator and is shown in Fig.2 Transmission timing diagram in the transmitter.Chapter 5 Hardware Design and Implementation PC Tx Printer port Modulator Analog Front End PC Rx Printer port Demodulator Powerline channel Analog Front End Fig.2.3. 5. After sending the 1680 bits. 5. the 16 check bits are sent.3 CRC . 29 .5. In this example.16 Polynomial : G(x) = x16 + x12 + x5 +1 . 5.1 Testing environment.

Fig.4 Radix-4 architecture. The system for sampling rate increase by 2 is illustrated in Fig. The 256-point FFT employs a Cooley-Tukey radix-4 decimation-in-frequency (DIF) FFT [17] to compute the DFT of a complex sequence.1. 5.5 FFT processor.5.Chapter 5 Hardware Design and Implementation 5. 5. FFT Processor Input/Working memory 0 Input data Input/Working memory 1 Radix-4 processor Bit inverted order Processor Output Memory Output data Coefficients Memory Fig.1. 5.3 The Architecture of the FFT [16] The input/output data are a vector of 256 complex values represented as 16-bit 2’s complement numbers. After the initial memory load operation a new transform result can be generated every 768 clock cycles. The lowpass filter is designed with the Kaiser Window FIR and is shown in Fig.4 Upsampling We will refer to the operation of increasing the sampling rate as upsampling. A radix-4 architecture is shown in Fig. An entire FFT architecture is shown in Fig.7. 30 . which performs the operations of the complex addition and multiplication. 5.4. 5. 5. 5.6.

5. The DAC circuit of differential configuration using an OP amplifier is shown in Fig. 5. Fig. 31 .1.8.Chapter 5 Hardware Design and Implementation x[ n] Sampling period T ↑2 Lowpass filter Gain=2 Cutoff= π 2 x '[n] Sampling period T/2 Fig.8 Difference amplifier provides differential to single-ended conversion. 5. 5. Fig.6 System for sampling rate increase by 2. 5.5 Digital to Analog Converter Circuit [18] The advanced segmentation architecture of the DAC900 is optimized to provide a high Spurious-Free Dynamic Range(SFDR) for single-tone. as well as for multi-tone signals-essential when used for the transmit signal path of communication systems.7 Digital lowpass filter.

Fig.Chapter 5 Hardware Design and Implementation 5.9 Input configuration of the AC-coupling and dual supply amplifier.1.7 Smooth Filter The smoothing filter is a second-order Butterworth lowpass filter. 5.6 Analog to Digital Converter Circuit [19] The ADS826 is a pipelined architecture and include a 10-bit quatizer. and a high-accuracy internal reference.10 Smoothing filter. high-bandwidth track-and-hold. Fig.9 shows typical connections for the analog input in case the selected amplifier operates on dual supplies. The circuit provided in Fig. 5. 5. 32 . 5.1.

1. 5. In Fig. C1 1uF Outlet TX Signal C1 1uF Outlet 0 Fig. we can find that error bits in the numbers from 23 to 31 and from 92 to 106 are more than the others.17 and 5. we show the measurement result with a hard-decision Viterbi decoder. 5.8 Coupling Circuit The analog-front-end (AFE) circuit is composed of a high pass filter and a transformer. Because there are man-made errors composed of a poor performance of printed circuit board.11 Coupling circuit. 5.6MHz. 33 . 5.13(a)(b).13(a)(b). and the signal bandwidth is from 1.14 are Graphical User Interfaces (GUIs) in both the transmitter and receiver. Therefore. The BER versus Eb/N0 curve is measured under an AWGN channel for our PLC system and shown in Fig. This result can be interrupted in Fig. 5. In Fig. 5. Frames in Fig.16(a)(b)(c)(d)(e)(f).18. Spectrums of noises and the received signal over power line channel are shown in Fig. we adopt the channel interleaver that scrambles the order of data arrangement to overcome the burst errors that are not expected by a Viterbi decoder. We can find that it is not enough to transmit data only with hard-decision Viterbi decoder because there are successive errors caused by the severe channel.4MHz to 6. Printed circuit boards are shown in Fig.14(b).Chapter 5 Hardware Design and Implementation 5. some kinds of results are shown in Fig.19. 5. 5.2 Implementation The system architecture described in chapter 4 has been implemented with Verilog language in Virtex FPGA and efforts of implementation are demonstrated.12. the result of our measurement under an AWGN channel for the practical system is different from the result for the simulation system. The 110V 60Hz sinewave in the power line channel is filtered by the high pass filter. 5. measurement errors and inaccurate full-scale range of ADC. 5. In another severe environment of power line. 5. Power spectrum of OFDM signal is shown in Fig.15.

Chapter 5 Hardware Design and Implementation Fig. 5. 5.13 (a) Power spectrum of noises (b) Power spectrum of the received signal for receiver over power line channel. 34 . (a) (b) Fig.12 Power spectrum of OFDM signal (DC~10MHz).

Chapter 5 Hardware Design and Implementation (a) (b) Fig.15 Measurement result with a hard-decision Viterbi decoder. (a) (b) 35 . 5. 5. Fig.14 (a) A frame in the transmitter (b) A frame in the receiver.

a hard-decision Viterbi decoder and interleaver scheme (f) ROBO.17 (a) Digital and DAC circuits (b) Amplifier circuit in the transmitter. (a) (b) Fig. 5. a hard-decision Viterbi decoder and interleaver scheme. 36 . 5.Chapter 5 Hardware Design and Implementation (c) (d) (e) (f) Fig.16 (a) DBPSK scheme (b) ROBO scheme (c) DBPSK and a hard-decision Viterbi decoder scheme (d) ROBO and a hard-decision Viterbi decoder scheme scheme (e) DBPSK.

18 (a) Digital and ADC circuits (b) Amplifier circuit in the receiver.Chapter 5 Hardware Design and Implementation (a) (b) Fig. Fig. 5.19 BER versus Eb/N0 for DBPSK under an AWGN channel. 5. 37 .

10 and the measurement result of the implementation system is shown in chapter 5. OFDM signals can achieve a much higher bandwidth efficiency and eliminate the ISI caused by multipath effect with cyclic prefix. 3. The more accurate initial phases obtained from the preamble will be provided to improve the system performance in the coherent modulation scheme. 38 . The simulation result is shown in Fig. the reliability of system will be improved by using the techniques of equalizer and adaptive modulation in the receiver. In the long run. constraint length K=7) as the channel code. we have implemented a powerline communication system using OFDM technique according to the HompePlug Spec.Chapter 6 Conclusion Chapter 6 Conclusion In this thesis. We also adopt the standard convolutional encoder(rate-1/2. we will estimate the channel to obtain the channel information and avoid the bad bands accordingly. and ran the simulation with the SPW tool. In the future..

“Nature of Power Line Medium 39 . Transmission and Distribution Conference.H. [4]Rice B. IEEE Transactions on . Engstrom.. Volume: 31 . 4.. April 2002 Pages:553 – 559. Donaldson R.F. 22-25 Sept. [8]J. Pages:854 – 862. Widmer H. [5]Zimmermann M. Rubio E. Volume: 50 . vol. Aug.. Volume: 2 .. 1996 Pages:809 . Communications. Issue: 4 . “Characterization and modeling of in-building power lines for high-speed data transmission” Power Delivery. Guan Y. Issue: 3 . “Embedded powerline DSP modem for domotic SNMP networking in European countries”. Lie T. [2]Cortes F.. Malack and J.Jan 2003 Pages:69 – 77...L. IEEE Transactions on . J. no... Electromagnetic Compatibility.Volume: 48 . 1989.. Dostert K. [9]Tang L. Kaltenschnee T. IEEE Transactions on .EMC-18. [11]Robert G. Chen S. IEEE 4th International Symposium on . [7]David K..Issue: 4 . “MV and LV powerline communications: new proposed IEC standards”.L.EMC-28..H. 1996. Nov 2002. “RF Impedance of United States and European Power Lines”.T. Hauser A. February 1976. pp. April 1999 IEEE. Aldis J. “Direct-Sequence Spread-Spectrum Modem for Data Communications Over Power-Lines”. IEEE Transaction on Electromagnetic Compatibiltiy.J. Gunawan E. IEEE Conference.Issue: 1 .A. Cheng.L. “Technical Cosiderations for Wideband Powerline Communication – A Summary”.M.220-230.T. vol. Addison Wesley.Volume: 18 . [12]Weilin Liu. Goiser.W. “A multiple-sequence spread spectrum system for powerline communications”. “Field and Wave Electromagnetics”.. MILCOM 97. [6]Chan M....1052-1056. 1989 Pages:320 – 323. Second Edition. “A multipath model for the powerline channel”... and interarrival distributions for noise impulses on intrabuilding power line communication networks”. “Amplitude.. 1997. IEEE Transaction on Electromagnetic Compatibiltiy.Bibliography Bibliography [1]Ramseler S.. [10]Chan M.. Donaldson R. “Attenuation of Communication Signals on Residential and Commercial Intrabuilding Power-Distribution Circuits”.815 vol.L. 2002. Valdovinos A. pp.36-38.-P. Consumer Electronics.W. Olsen. no. pp. Arzberger M.1. Novermber 1986.R.. width. So P. [3]A.M. Spread Spectrum Techniques and Applications Proceedings.2. IEEE Transactions on .

com/docs/prod/folders/print/dac900. Morikura M. “Synchronization in OFDM Powerline Communication System in Presence of Narrowband Interferences”. [15]Mizoguchi M. Comput. [13]Matthias Goetz.W. April 1965. Takanashi H. “An Algorithm for the Machine Calculation of Complex Fourier Series”.. Texas Instruments Inc. [19]“ADS826: 10-Bit. 60MHz Sampling Analog-To-Digital Converter (Rev. Cooley and J. Institute of Industrial Information Systems. http://focus. 165MSPS Digital-to-Analog Converters (Rev. [16]San Jose.html. IEEE. 2003. Kumagai T. Onizawa T. “High-Performance 256-point complex FFT/IFFT V1.. B)”..com/docs/prod/folders/print/ads826... Texas Instruments Inc. W. Tukey.0”.297-301.ti.Bibliography and Design Aspects for Broadband PLC System”. “A Fast Burst Synchronization Scheme for OFDM”. Math. http://focus. “Power Line Channel Characteristics and Communication System Considerations”. [14]Aghajeri S. [17]J. Klaus Dostert. B)”. [18]“DAC900: 10-Bit.1998... Xilinx Inc. Shafiee H. 2000. University of Karlsruhe. International Zurich Seminar on Broadband Communications. 10. Vol. IEEE.html.. Manuel Rapp. 40 .. pp. 2001.ti.

作者簡歷 姓名:許世杰 生日:68 年 8 月 14 日生 籍貫:台灣省彰化縣 學歷:省立彰化高級中學(民國 86 年 6 月畢業) 國立成功大學電機工程學系(民國 90 年 6 月畢業) 國立成功大學電機所通訊組(民國 93 年 6 月畢業) .

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