Cmos Vlsi Design: Dr. Lynn Fuller

CMOS VLSI DESIGN
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING
CMOS VLSI DESIGN

Dr. Lynn Fuller
Webpage: http://people.rit.edu/~lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu
Rochester Institute of Technology Microelectronic Engineering
12-31-2007 cmosvlsi2007.ppt
Page 1
December 31, 2007 Dr. Lynn Fuller
CMOS VLSI DESIGN
OUTLINE Design Approach Process Technology MOSIS Design Rules Primitive Cells, Basic Cells, Macro Cells Projects Maskmaking References Homework
Page 2
CMOS VLSI DESIGN
THE NEED FOR CAD
With millions of transistors per chip it is impossible to design with no errors without computers to check layout, circuit performance, process design, etc.
Page 3
CMOS VLSI DESIGN
COMPARISON OF DESIGN METHODOLOGIES Full Custom Design Direct control of layout and device parameters Longer design time but faster operation more dense Standard Cell Design Easier to implement Limited cell library selections Gate Array or Programmable Logic Array Design Fastest design turn around Reduced Performance
Page 4
CMOS VLSI DESIGN
STAGES IN THE CAD PROCESS
Problem Specification Behavioral Design Functional and Logic Design Circuit Design Physical Design (Layout) Fabrication Technology CAD (TCAD) Packaging Testing
Page 5
CMOS VLSI DESIGN
DESIGN HEIRARCHY - LEVELS OF ABSTRACTION A=B+C if (A) then X: = Y

ALU RAM
Behavioral Model Block-Functional Model Gate-Level Model Transistor level Model Geometric Model
Page 6
CMOS VLSI DESIGN
PROCESS SELECTION It is not necessary to know all process details to do CMOS integrated circuit design. However the process determines important circuit parameters such as supply voltage and maximum frequency of operation. It also determines if devices other than PMOS and NMOS transistors can be realized such as poly-to-poly capacitors and EEPROM transistors. The number of metal interconnect layers is also part of the process definition.
Page 7
CMOS VLSI DESIGN
RIT SUB CMOS RIT Sub CMOS 150 mm wafers Nsub = 1E15 cm-3 Nn-well = 3E16 cm-3 Xj = 2.5 m Np-well = 1E16 cm-3 Xj = 3.0 m LOCOS Field Ox = 6000 Xox = 150 Lmin= 1.0 m LDD/Side Wall Spacers Vdd = 5 Volts, Vto= +/- 1 Volt Two Layer Metal
Long Channel Behavior
Page 8
CMOS VLSI DESIGN
RIT SUB CMOS NMOSFET

N+ Poly 0.75 m Aluminum
PMOSFET
6000 Field Oxide p+ well contact N+ D/S LDD LDD P+ D/S
P-well
N-well
n+ well contact
Channel Stop
N-type Substrate 10 ohm-cm
Page 9
CMOS VLSI DESIGN
RIT ADVANCED CMOS VER 150 RIT Advanced CMOS 150 mm Wafers Nsub = 1E15 cm-3 or 10 ohm-cm, p L Nn-well = 1E17 cm-3 Xj = 2.5 m Np-well = 1E17 cm-3 Xj = 2.5 m Shallow Trench Isolation Long Field Ox (Trench Fill) = 4000 Channel Dual Doped Gate n+ and p+ Behavior Xox = 100 Lmin = 0.5 m , Lpoly = 0.35 m, Leff = 0.11 m LDD/Nitride Side Wall Spacers Vdd = 3.3 volts TiSi2 Salicide Tungsten Plugs, CMP, 2 Layers Aluminum Vto=+- 0.75 volts
Page 10
CMOS VLSI DESIGN
RIT ADVANCED CMOS NMOSFET

N+ Poly
PMOSFET
P+ Poly
p+ well contact
N+ D/S LDD
P+ D/S
P-well N-well
LDD
n+ well contact
Page 11
CMOS VLSI DESIGN
LAMBDA, Lmin, Ldrawn, Lmask, Lpoly, Lint, Leff, L

Ldrawn Lmask Lpoly Gate Source at 0 V Lambda = design rule parameter, , ie 0.25m 0.50m Lmin = min drawn poly length, 2 Lmask = ? Depends on +/-bias 1.00m x 5 Lresist after photo (resist trimming??) 0.50m Lpoly after poly etch 0.40m Lpoly after poly reoxidation 0.35m Drain at 3.3V Lint Leff L 0.30m 0.20m 0.11m Ldrawn = what was drawn Internal Channel Length, Lint =distance between junctions, including under diffusion Effective Channel Length, Leff = distance between space charge layers,Vd = Vs= 0 Channel Length,Rochester Institute of Technology L, = distance between space charge layers, when Vd= what it is Microelectronic Engineering Extracted Channel Length Parameters = anything that makes the fit good (not real)
Page 12
CMOS VLSI DESIGN
MOSIS TSMC 0.35 2POLY 4 METAL PROCESS

http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html#tech-codes
Page 13
CMOS VLSI DESIGN
MOSIS TSMC 0.35 2-POLY 4-METAL LAYERS

MASK MENTOR LAYER NAME NAME N WELL ACTIVE POLY N PLUS P PLUS CONTACT METAL1 VIA METAL2 N_well.i Active.i Poly.i N_plus_select.i P_plus_select.i Contact.i Metal1.i Via.i Metal2.i GDS # 42 43 46 45 44 25 49 50 51 Active_contact.i 48 poly_contact.i 47 COMMENT
Page 14
CMOS VLSI DESIGN
MORE LAYERS USED IN MASK MAKING

LAYER NAME cell_outline.i alignment nw_res active_lettering channel_stop pmos_vt LDD p plus n plus GDS COMMENT 70 81 82 83 84 85 86 87 88 Not used Placed on first level mask Placed on nwell level mask Placed on active mask Overlay/Resolution for Stop Mask Overlay/Resolution for Vt Mask Overlay/Resolution for LDD Masks Overlay/Resolution for P+ Mask Overlay/Resolution for N+ Mask
Page 15
CMOS VLSI DESIGN
OTHER LAYERS Design Layers

N-WELL (42) ACTIVE (43) POLY (46) P-SELECT (44) N-SELECT (45) CC (25) METAL 1 (49) VIA (50) METAL 2 (51)
Other Design Layers

P+ Resolution (87) STI Resolution (82) Stop Resolution (84) Vt Resolution (85) Active Resolution (83) N+ Resolution (88)
2.0 1.5 1.0 2.0 1.5 1.0
81 43 STI 46 42 44 49 45
85
84
2.0 1.5 1.0 2.0 1.5 1.0
Nmos Vt 87 Poly
2.0 1.5 1.0 2.0 1.5 1.0
88
25
Active 83
Stop
P+
N+
Page 16
CMOS VLSI DESIGN
LAMBDA BASED DESIGN RULES The design rules may change from foundry to foundry or for different technologies. So to make the design rules generic the sizes, separations and overlap are given in terms of numbers of lambda (). The actual size is found by multiplying the number by the value for lambda. For example: RIT PMOS process = 10 m and minimum metal width is 3 so that gives a minimum metal width of 30 m. The RIT CMOS process (single well) has = 4 m and the minimum metal width is also 3 so minimum metal is 12 m but if we send our CMOS designs out to industry might be 0.8 m so the minimum metal of 3 corresponds to 2.4 m. In all cases the design rule is the minimum metal width = 3
Page 17
CMOS VLSI DESIGN
LAYOUT RULES
Perfect Overlay
Slight Overlay Not Fatal
Misalignment Fatal
Layout rules prevent slight misalignment from being fatal.

Page 18
CMOS VLSI DESIGN
MOSIS LAMBDA BASED DESIGN RULES http://www.mosis.com/design/rules/

Well 10 6 3 n+ 5 Diff Potential 9 Same Potential n-Substrate (Outside well) contact to poly 2 2 2 2 1 3 1
Page 19
Active in p-well 3 n+ p+ 3 5 p+ 3 n+ well edge
Poly Active Poly Poly 3 2 2 2
active 1 3
metal
2 2 p select
If = 1 m then contact is 2 m x 2 m
CMOS VLSI DESIGN
MOSIS LAMBDA BASED DESIGN RULES http://www.mosis.com/design/rules/

2 1 2 metal two
MOSIS Educational Program

4
Instructional Processes Include: AMI = 0.8 m SCMOS Rules AMI = 0.35 m SCMOS Rules Research Processes: go down to poly length of 65nm
Page 20
CMOS VLSI DESIGN
MOSIS REQUIREMENTS MOSIS requires that projects have successfully passed LVS (Layout Versus Schematic) and DRC (Design Rule Checking). Our MENTOR tools for LVS and DRC (as they are set up) require separate N-select and P-select levels in order to know an NMOS transistor from a PMOS transistor. Although either an N-well, Pwell or both will work for a twin well process, we have set up our DRC to look for N-well.
Page 21
CMOS VLSI DESIGN
RIT PROCESSES At RIT we use the SMFL-CMOS or Sub-CMOS processes for most designs. In these processes the minimum poly length is 2m and 1m respectively. We use scalable MOSIS design rules with lambda equal to 1m and 0.5m. These processes use one layer of poly and two layers of metal. The examples on the following pages are designs that could be made with either of the above processes. As a result the designs are generous, meaning that larger than minimum dimensions are used. For example = 1m and minimum poly is 2 but biased to 2.5m because our poly etch is isotropic. (alternatively this biasing could be done at mask making) The design approach for digital circuits is to design primitive cells and then use the primitive cells to design basic cells which are then used in the project designs. A layout approach is also used that Rochester Institute of Technology Microelectronic Engineering allows for easy assembly of these cells into more complex cells.
Page 22
CMOS VLSI DESIGN
PRIMITIVE CELLS Primitive Cells Inverter NOR2 NOR3 NOR4 NAND2 NAND3 NAND4 Etc.
Page 23
CMOS VLSI DESIGN
CMOS INVERTER
Vin +V
Idd
Vout
PMOS
Vin Vout
NMOS
CMOS
TRUTH TABLE VIN 0 1 VOUT 1 0
W = 40 m Ldrawn = 2.5m Lpoly = 1.0m Leff = 0.35 m

Page 24
CMOS VLSI DESIGN
NOR and NAND

VA VB VA +V 0 0 1 1 VOUT VA VB VA 0 0 1 1 VB 0 1 0 1 VOUT 1 1 1 0 VOUT
VB 0 1 0 1
VOUT 1 0 0 0
+V
VOUT
VA
VOUT VB
VA
VB
Page 25
CMOS VLSI DESIGN
OTHER LOGIC GATES

AND VA VB VA 0 0 1 1 VB 0 1 0 1 VA VOUT VB VOUT 0 0 0 1 VA 0 0 1 1 VB 0 1 0 1 VOUT OR 3 INPUT AND VA VB VC VOUT 3 INPUT OR VA VB VC VOUT
VOUT VA VB VC VOUT 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1
VA VB VC VOUT 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1
Page 26
CMOS VLSI DESIGN
MORE PRIMITIVE CELLS
Page 27
CMOS VLSI DESIGN
MORE PRIMITIVE CELLS
Page 28
CMOS VLSI DESIGN
BASIC CELLS Basic Cells XOR D FF JK FF Data Latch
XOR
Input A
Port in
A B
AB XOR
Port out
Input B
Port in
XOR = AB+AB A B AB
Page 29
CMOS VLSI DESIGN
XOR
Page 30
CMOS VLSI DESIGN
XOR
Page 31
CMOS VLSI DESIGN
FILP-FLOPS
R 0 0 1 1 S 0 1 0 1 Q Qn-1 1 0
INDETERMINATE
R RS FLIP FLOP S D FLIP FLOP
QBAR
Q DATA CLOCK Q=DATA IF CLOCK IS HIGH IF CLOCK IS LOW Q=PREVIOUS DATA VALUE
QBAR
Page 32
CMOS VLSI DESIGN
EDGE TRIGGERED D FLIP FLOP
Page 33
CMOS VLSI DESIGN
EDGE TRIGGERED D FLIP FLOP
Page 34
CMOS VLSI DESIGN
T FLIP FLOP
TOGGEL FLIP FLOP T Q T QBAR 0 0 1 1 Qn-1 0 1 0 1 Q 0 1 1 0
Q: TOGGELS HIGH AND LOW WITH EACH INPUT
Page 35
CMOS VLSI DESIGN
JK FLIP FLOP
Page 36
CMOS VLSI DESIGN
PROJECTS Multiplexer Full Adder Binary Counter
I0 A I1 I2 B I3
B A
ABI0 ABI1 ABI2 ABI3
4:1 Multiplexer
Page 37
CMOS VLSI DESIGN
MULTIPLEXER
Page 38
CMOS VLSI DESIGN
DE MULTIPLEXER
Q0 Q1 Q2
De-multiplexer
I B
Q3
Q0 = ABI so that when or when
I=0 Q0 =0 I=1 Q0 = 1
similarly for Q1, Q2 and Q3 Q1 = ABI

INPUTS OUTPUTS A B Q0 Q1 Q2 Q3 0 0 I 0 0 0 0 1 0 I 0 0 1 0 0 0 I 0 1 1 0 0 0 I
Page 39
CMOS VLSI DESIGN
DE MULTIPLEXER
Page 40
CMOS VLSI DESIGN
FULL ADDER
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
CIN SUM COUT 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1
COUT
SUM
A
Cin
Page 41
CMOS VLSI DESIGN
FULL ADDER
Page 42
CMOS VLSI DESIGN
8-BIT BINARY COUNTER

42 41 43 44 45 46 47 48 49 50 51 52 53 54 55 40 56 57
Page 43
CMOS VLSI DESIGN
8-BIT BINARY COUNTER
Page 44
CMOS VLSI DESIGN
FILE FORMATS
Mentor- ICGraph files (filename.iccel), all layers, polygons with up to 200 vertices GDS2- CALMA files (old IC design tool) (filename.gds), all layers, polygons MEBES- files for electron beam maskmaking tool, each file one layer, trapezoids only
Page 45
RIT SUB-CMOS PROCESS NMOSFET

N+ Poly
PMOSFET
LVL 6 P-LDD LVL 1 n-WELL
0.75 m Aluminum 6000 Field Oxide
p+ well N+ D/S LDD contact P-well Channel Stop
N-well
LDDP+ D/S n+ well contact
LVL 7 N-LDD LVL 2 - ACTIVE
N-type Substrate 10 ohm-cm

POLY CC ACTIVE P SELECT
LVL 8 - P+ D/S LVL 3 - STOP
LVL 9 - N+ D/S LVL 4 - PMOS VT
METAL
LVL 5 - POLY
LVL 8 - CC
N SELECT N-WELL 11 PHOTO LEVELS

LVL 9 - METAL
RIT ADVANCED CMOS

NMOSFET N+ Poly PMOSFET P+ Poly
LVL 1 - STI LVL 7 - PLDD
p+ well contact
N+ D/S P-well LDD N-well LDD
P+ D/S
LVL 2 - NWell
LVL 8 - NLDD
n+ well contact
12 PHOTO LEVELS + 2 FOR EACH ADDITIONAL METAL LAYER POLY CC ACTIVE P SELECT
LVL 3 - Pwell
LVL 9 N+D/S
LVL 4 - VTP
LVL 10 P+D/S
METAL N SELECT N-WELL
LVL 5 - VTN
LVL 11 - CC
LVL 6 - POLY
LVL 12 METAL 1
CMOS VLSI DESIGN
OTHER MASKMAKING FEATURES Fiducial Marks-marks on the edge of the mask used to align the mask to the stepper Barcodes Titles Alignment Keys- marks on the die from a previous level used to align the wafer to the stepper CD Resolution Targets- lines and spaces Overlay Verniers- structures that allow measurement of x and y overlay accuracy Tiling Optical Proximity Correction (OPC)
Page 48
CMOS VLSI DESIGN
REFERENCES 1. Silicon Processing for the VLSI Era, Volume 1 Process Technology, 2nd, S. Wolf and R.N. Tauber, Lattice Press. 2. The Science and Engineering of Microelectronic Fabrication, Stephen A. Campbell, Oxford University Press, 1996. 3. MOSIS Scalable CMOS Design Rules for Generic CMOS Processes, www.mosis.org, and http://www.mosis.com/design/rules/
Page 49
CMOS VLSI DESIGN
HOMEWORK - CMOS VLSI DESIGN 1. Sketch and label the seven layout layers of a CMOS 2-input OR gate that uses the MOSIS lambda based design rules and uses minimum area. Calculate the area of the smallest rectangle to enclose the design in m2 . 2. What lithographic layers are not drawn by the designer in the Adv-CMOS process? How are they created? 3. For the p-well CMOS layout shown below sketch the crossection A-A just after level 5 lithography. A 4. Does the designer draw the alignment marks, fiducial marks, resolution and overlay features?
A
Page 50

Cmos Vlsi Design: Dr. Lynn Fuller

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CMOS VLSI DESIGN

ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING

CMOS VLSI DESIGN

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

THE NEED FOR CAD

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

STAGES IN THE CAD PROCESS

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

DESIGN HEIRARCHY - LEVELS OF ABSTRACTION A=B+C if (A) then X: = Y

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

Long Channel Behavior

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

RIT SUB CMOS NMOSFET

6000 Field Oxide p+ well contact N+ D/S LDD LDD P+ D/S

N-type Substrate 10 ohm-cm

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

RIT ADVANCED CMOS NMOSFET

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

LAMBDA, Lmin, Ldrawn, Lmask, Lpoly, Lint, Leff, L

CMOS VLSI DESIGN

MOSIS TSMC 0.35 2POLY 4 METAL PROCESS

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

MOSIS TSMC 0.35 2-POLY 4-METAL LAYERS

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

MORE LAYERS USED IN MASK MAKING

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

OTHER LAYERS Design Layers

Other Design Layers

Rochester Institute of Technology Microelectronic Engineering

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

December 31, 2007 Dr. Lynn Fuller

CMOS VLSI DESIGN

Slight Overlay Not Fatal