VLSI USING VERILOG HDL

AN ON-CAMPUS TECHNICAL TRAINING PROGRAMME

SUBMITTED BY :
Aakansha Barnwal,VII sem.,E.C.E.,I.E.T.,Alwar.

ACKNOWLEDGEMENT
Before, I get to think of things, I would like to add a few heart felt words for the people who are related directly or indirectly to me during the course of my training programme which titles "VLSI using Verilog HDL module". First of all, I would like to thank respected, Mr. Vinit Mahajan, (trainer) who gave me the opportunity to carry out this training under his guidance. He provided me with all the necessary, which were required for the completion of my training. I also thank my college library staffs for providing me with the books related to the training. I also thank my college management for providing me with such an interesting training programme. A grateful acknowledgement goes to my project mates, who helped me with timely suggestions during the entire period of references and data collections. Above all without God's grace nothing was possible.

INDEX • • • • • • • • • • • • • • • • • • Introduction History of VLSI Emergence of HDLs Hierarchical modelling concepts Verilog HDL syntax and semantics Modules and ports Gate level modelling Data level modelling Verilog operators Verilog behavioral modelling Tasks and functions Switch level modelling Art of writing test benches Logic synthesis with verilog HDL Verilog HDL synthesis Modelling memories and FSM Applications of Verilog HDL Conclusion .

clk. A hardware description language is a language used to describe a digital system. always @ (posedge clk) begin q <= d. clk. by using a HDL one can describe any hardware (digital) at any level. . end endmodule One can describe a flip-flop as explained in above figure as well as one can describe a complicated design having 1 million gates. q_bar. q. input d. ouput q. This just means that. q_bar). Verilog is one of the HDL languages available in the industry for designing the hardware.INTRODUCTION Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). q_bar <= !d. Source code: module d_ff ( d.

this led to the evolution of CAD (computer aided design) techniques. called MSI (medium scale integration) chips. Because of the complexity of these circuits.000 transistors. The earliest digital circuits were designed with vacuum tubes and transistors. designers could design single chips with more than 100. Then there came LSI (large scale integration) chips. The first integrated (IC) chips were SSI (small scale integration) chips where the gate count was very small. Integrated circuits were then invented where logic gates were placed on a single chip. Computer aided techniques became critical for verification and design of VLSI digital circuits. As designers got larger and more complex. Designers could iron out functional bugs in the architecture before the chip was designed further. At this point. With the advent of VLSI (very large scale integration) technology. This led to the emergence of HDLs which came into existence after circuitry got complex. design processes started getting very complicated. designers were able to place circuits with hundreds of gates on a chip. logic simulation assumed an important role in the design process. . As technologies became sophisticated. it was not possible to verify these circuits on the breadboard. The emergence of HDLs is described in the next topic which is the same “emergence of HDLs”.HISTORY OF VLSI Digital circuit design has evolved rapidly over the last 25 years.

Thus. HDLs were for simulation of system boards. PALs (Programmable Array Logics). Designers no longer had to manually place gates to build digital circuits. The details of gate and their interconnections to implement the circuit were automatically extracted by logic synthesis tools from the RTL description.Emergence of HDLs In the digital design field. Both Verilog and VHDL simulators to simulate large digital circuits quickly gained acceptance from designers. Thus Hardware Description Languages (HDLs) came into existence. interconnect buses. Digital circuits could be described at a register transfer level (RTL) by use of an HDL. Pascal and C were being used to describe computer programs that were sequential in nature. designers felt the need for a standard language to describe digital circuits similar to the programming languages such as FORTRAN. FPGAs (Field Programmable Gate Arrays). Hardware Description Languages such as Verilog HDL and VHDL became popular. Verilog HDL originated in 1983 at Gateway Design Automation. VHDL was developed under contract from DARPA. Thus. Later. logic synthesis pushed the HDLs into the forefront of digital design. HDLs also began to be used for system-level design. HDLs allowed the designers to model the concurrency of processes found in hardware elements. . the designers had to specify how the data flows between registers and how the design processes the data.

a combination of top-down and bottom-up flows is used. There are two basic types of design methodologies: a top-down design methodology and a bottom-up design methodology. which are the cells that cannot further be divided. Figure shows Top-down design methodology In a bottom-up design methodology. . We build bigger cells. Figure shows bottom-up design methodology Typically. Design architects define the specification of the top-level block. In a top-down design methodology. we first identify the building blocks that are available to us. They build higherlevel cells by using these leaf cells.Hierarchical Modelling Concepts Before we discuss the details of the Verilog language. we must first understand the basic hierarchical modelling concepts in digital design. we define the top-level block and identify the sub-blocks necessary to build the top-level block. using these building blocks. We further subdivide the sub-blocks until we come to leaf cells. Logic designers decide how the design should be structured by breaking up the functionality into blocks and sub-blocks. These cells are then used for higherlevel blocks until we build the top-level block in the design.

we break bigger building blocks into smaller ones until we decide that we cannot break up the blocks any further. Figure shows design hierarchy for ripple counter. Then we implement the counter with T_FFs which we build from D_FFs and an additional inverter gate. Thus. Thus.g.To illustrate these hierarchical modelling concepts. we could build D_FF from and and or gates. e. the ripple carry counter is built in a hierarchical fashion by using building blocks. In the top-down methodology. we first have to specify the functionality of the ripple carry counter. which is the top-level block.. A bottom-up methodology flows in the opposite direction. Figure shows 4-bit ripple carry counter. let us consider the design of a negative edge 4-bit ripple counter. We combine small building blocks and build bigger building blocks. The diagram for the design hierarchy is shown below. or we could build a .

the bottom-up flow meets the top-down flow at the level of the D_FF. . Thus.custom D_FF from transistors.

These levels of abstraction can be defined as follows: 1. Abstraction levels of VERILOG Verilog is both a behavioural and a structural language.Modules Verilog provides the concept of module. This level is Register-transfer level. 3. An additional level is also there which is used very frequently in digital design. …. but hides the internal implementation. endmodule. <module internals> …. o BEHAVIOURAL LEVEL:This is the highest level of abstraction provided by Verilog HDL. Behavioural or algorithmic level. Typically. This allows the designers to modify module internals without affecting the rest of the design. o GATE LEVEL:- . o DATAFLOW LEVEL:At this level the module is designed by specifying the data flow. 4. Verilog provides four levels of abstraction. 2. …. Gate level. Designing at this level is very similar to C programming. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs). Dataflow level. Syntax:module <module_name> (<module_terminal_list>). A module can be an element or a collection of lower-level design blocks. The designer is aware of how data flows between hardware registers and how the data is processed in the design. elements are grouped into modules to provide common functionality that is used at many places in design. Switch level. A module is the basic building block in Verilog.

o REGISTER TRANSFER LEVEL:This is an additional level which is frequently used in Verilog. Modern definition of a RTL code is “Any code that is synthesizable is called RTL code”. An explicit clock is used. Designs using the register-transfer level specify the characteristics of a circuit by operations and the transfer of data between the registers. and the interconnections between them.The module is implemented in terms of logic gates and interconnections between these gates. . o SWITCH LEVEL:This is the lowest level of abstraction provided by Verilog. storage nodes. Design at this level is similar to describing a design in terms of a gate-level logic diagram. A module can be implemented in terms of switches. Design at this level requires knowledge of switch-level implementation details. operations are scheduled to occur at certain times. RTL design contains exact timing possibility.

In our case various blocks are registers. counters. decoders.etc. Lets assume that we have to design a microprocessor. reset and required test vectors. which generates clk. High level design means splitting the design into blocks based on their function. Instruction Decode. It contains details of state machines. designer describes how each block is implemented. Memory Interface. . Internal registers. o SIMULATION:Simulation is a process of verifying the functional characteristics of models at any level of abstraction. ALU. o Micro Design/Low level design:Low level design or Micro design is the phase in which. Mux. o HIGH-LEVEL DESIGN:This is the stage at which various blocks are defined in the design and how they communicate. A sample testbench for a counter is as shown below. to achieve simulation we need to write a testbench.DESIGN AND TOOL FLOW o SPECIFICATION:This is the stage at which we define what are the important parameters of the system/design that you are planning to design.

This is also called as SDF simulation or gate simulation.Figure shows sample testbench of a counter. Here we include the gate delays and wire delays and see if DUT (Device Under Test) works at rated clock speed. which is done after synthesis or after P&R (Place and Route). There is another kind of simulation known as timing simulation. o SYNTHESIS:Synthesis is the process of constructing a gate level netlist from a register-transfer level model of a circuit described in Verilog HDL. . Figure shows 4 bit up counter waveform.

o PLACE AND ROUTE:- . also do the minimal amount of timing analysis to see if the mapped design meeting the timing requirements. Synthesis tool after mapping the RTL to gates.Figure shows the synthesis process.

4.c. or binary format. The underscore (_) is legal anywhere in the number except as the first character. octal.Figure shows sample microprocessor placement. Verilog HDL Syntax and Semantics  NUMBERS IN VERILOG:Constant numbers can be specified in decimal. 3. Radix is a case and hex digits (a. or hexadecimal.b. In a radix pf binary. decimal. o INTEGER NUMBERS:Verilog HDL allows integer numbers to be specified as 1. octal.f) are insensitive. 2. Spaces are allowed between the size. radix and value. When used in a number. Negative numbers are represented in 2‟s complement form. hexadecimal. where it is ignored.e.d. the question mark (?) character is the Verilog alternative for the z character. Figure shows the place and route for J-K Flip-Flop. Sized or Unsized numbers (unsized size is 32 bits). Syntax : <size>‟<radix><value> o REAL NUMBERS:- .

 HIERARCHICAL IDENTIFIERS:Hierarchical path names are based on the top module identifier followed by module instant identifiers. Real numbers cannot contain „Z‟ and „X‟.1. Inout [range_val:range_var]list _of_identifiers. Real numbers are rounded off to the nearest integer. separated by periods.<value> <mantissa>E<exponent> 5. 4. 2. o Registers – represent variables used to store data. 3. Verilog converts real numbers to integers to integers by rounding. Output [range_val:range_var]list _of_identifiers. o All but the top-level modules in a hierarchy have ports. <value>. The port declaration syntax is : Input [range_val:range_var]list _of_identifiers. o Ports can be associated by order or by name. You declare ports to be input. o GATE PRIMITIVES:- . Real numbers may b specified in either decimal or scientific notation. Verilog supports real constants and variables.  DATATYPES:Verilog language has two primary data types o Nets – represents structural connections between components. output or inout.  PORTS:o Ports allow communication between a module and its environment.

Figure showing the gate primitives. o TRANSMISSION GATE PRIMITIVES:- Figure showing transmission gate primitives. o SWITCH PRIMITIVES:- .

Y.  DESIGNING USING PRIMITIVES: AND GATE from NAND GATE Verilog code:module and_from_nand(X.F).Y. . input X. nand U1(X. endmodule.W.W). nand U2(W.Y. output F.Figure showing switch primitives. Similarly many programs can be done by using Verilog. Many designs can be made using Verilog HDL language. wire W.F).

>> . +. *.Modulus % Add./. -. /.Divide.||(logical or)  BITWISE OPERATORS:~.|.>.&&(logical and).^.!==.|.-. ~.^~or ~^  SHIFT OPERATORS:<<. <<.Subtract.~^  REDUCTION OPERATORS:&.% (the modulus operator)  RELATIONAL OPERATORS:<.Shift +.!=  LOGICAL OPERATORS:!(logic negation).>=(greater than equal to)  EQUALITY OPERATORS:===. !.>>  CONCATENATION OPERATORS:{ and }  CONDITIONAL OPERATORS:Cond_expr? True_expr : false_expr.^. -.<=(less than equal to).==.VERILOG OPERATORS  ARITHMETIC OPERATORS:+.&.~&. Multiply.^~.*. OPERATOR PRECEDENCE OPERATORS SYMBOLS Unary.~|.

|| ?: . ~| &&. !=. Equality Reduction Logic Condition <. <=. !=== &. >=. ===. ^. >. ==. |. !&.Relation. ^~.

<exprssion>. Syntax: repeat (<number>)<statement>  While: Executes as long as an expression evaluates true. Syntax: for (<initial assignment>. and  Always: executes over and over again.VERILOG BEHAVIOURAL MODELLING  PROCEDURAL BLOCKS:There are two types of procedural blocks  Initial: executes once in the starting at time zero. those statements must be enclosed within   Sequential begin-end block Parallel fork-join block  LOOPING STATEMENTS:Verilog has four looping statements like any other programming language.  Forever : forever loop executes continually syntax: forever <statement>  Repeat: Executes for a fixed number of time. Syntax: while (<expression>)<statement>  For: It is same as used in other programming languages.<step assignment>)<statement> . If the procedural block contains more then one statement.

There are less chances of faults in the design which are designed using Verilog. Verilog HDL is a very useful language used for hardware designing. . Verilog provides designers to put their own designs and can easily simulate and synthesize the designs and then can implement it . Verilog HDL is a hardware description language which provided the RTL description of the designs for the digital designs. So it helped in reducing faults also. Overall.CONCLUSION It can be concluded from above that Verilog HDL is a language which is user-friendly and economic.

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