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A Low Voltage, Rail-to-Rail, Class AB CMOS Amplifier With High Drive and Low Output Impedance Characteristics
Gabriel A. Rincon-Mora, Member, IEEE, and Richard Stair, Member, IEEE
Abstract-- This paper describes a CMOS rail-to-rail class AB operational amplifier designed to have extremely low output impedance and large current-drive capability. The amplifier uses an innovative output stage, having both source follower and common source stages working simultaneously throughout the output common-mode range. The source follower ensures low output impedance, which enables it to drive relatively large load capacitors, while the common-source gain stage provides high current drive. Furthermore,
the circuit is fully functional with supplies as low as 1.5 V.
The amplifier is capable of
driving a maximum output current of ±7 mA with only 140 µA of quiescent current, making it power efficient and, therefore, appropriate for low voltage battery -powered applications.
Index Terms-- Class AB, rail-to-rail, low output impedance, low voltage, operational amplifier, power efficient. I - INTRODUCTION Class AB output stages are increasingly popular in today’s low voltage battery-powered electronics where amplifier applications demand high efficiency as well as rail-to-rail operation. In the era of portable equipment, low supply vo ltage and low power consumption are intrinsic traits . Performance requirements are also becoming more stringent, leaving the designer with more difficult specifications to fulfill and less flexibility with which to do it. For instance, low output impedance is generally desired, but classical source-follower configurations are not allowed in low voltage applications. Dynamic range is already limited by low battery voltages and source followers take too much of that range away to be viable solutions. In fact, most low voltage class AB output stages have inherently high output impedance because they necessarily employ common-source configurations [2-4]. On the other hand, amplifiers with source follower output stages typically suffer from output voltage swing limitations, which are severe in low voltage applications. Ideally, though, one would like to combine the characteristics of sourcefollowers and common-source gain stages in the same circuit to achieve low output impedance, rail-to-rail operation, and high current-drive capability. The one previously reported topology that implements this combination is not a low voltage solution and, moreover, has load-range
The basic circuit topology of the proposed amplifier is presented in Section II. conclusions are drawn in Section V. simulated results are presented and discussed. The voltage amplifier with gain AV drives the output stage with separate dual in-phase signals. In light of today’s market. II . In Section IV. In this output stage. and the output stage. are connected in a common-source configuration. Section III discusses the circuit realization. detailing the input stage. The amplifier described in this paper. allowing the output to reach the supply rails as in most lowvoltage class AB output stages. by approximately the loop gain. Finally. The Common-Mode Feedback (CMFB) circuit insures that the drivers operate in true class AB mode. and a low side driver (LSD) circuit. however. The two feedback loops lower the effective output impedance of the output stage. MPD in the HSD and MND in the LSD. It performs this 3 . The circuit is subsequently compared to other state-of-the-art designs. and compensation are also discussed in this section while highlighting optimum operating conditions. already the reciprocal of the transconductance. capable of sinking large amounts of load current. the output is also connected to source-followers.limitations . The high current devices. combines common-source gain stages and source-followers to achieve true class AB operation with low output impedance while still producing a rail-to-rail output voltage swing. however. the gain stage.PROPOSED ARCHITECTURE The basic circuit topology of the class AB amplifier is shown in Fig. Common-mode feedback. the amplifier is designed to operate with low supply voltages and low quiescent current.loop feedback networks. Both the HSD and the LSD circuits are closed. The output stage consists of a high side driver (HSD) circuit. which is capable of sourcing large amounts of current to load ZL. rail-to-rail control. 1.
Subsequently. The ac and dc analysis of the high side driver is analogous to the LSD counterpart. When VIN decreases. MPB. VOUT is lowered until the gate-source voltage of MNF once again reaches its steady-state value. the current difference. I1 . To demonstrate how the feedback loop operates. however. causes MND to sink additional current. 2(b) shows the ac equivalent circuit used to determine the output resistance. is that the driver circuit behaves similarly to a simple source. thereby increasing the voltage at the gate of MND which. in that the output impedance is roughly two orders of magnitude below that of a classical source-follower. gmF is the transconductance of M . more of I1 is steered into MPB. 2(a) shows a more detailed circuit diagram of the LSD circuit. flows through source-follower transistor MNF and into driver transistor MND. ro2 is the output resistance of current source I . and MND. which is comprised of MNF. the gate of the high current transistor is controlled indirectly through the feedback loop. with respect to forward gain.I2 .follower transistor. assuming all devices are biased in the saturation region. a fast transient decrease in voltage at VIN is considered. Then. It is the corresponding test current. Current I1 is designed to be greater than I2 . Fig. The overall result. Unlike most class AB output stages. The CMFB circuit essentially controls the quiescent biasing conditions of the power transistors. by a factor of (1+ gmDro2 ). One important differenc e exists. The feedback loop effectively reduces the output impedance of the driver. It g mF Vt + g mF Vt ro 2 g mD g mF (1 + g mD ro 2 ) (1) where Vt is an ac test voltage applied to the output. already 1/gmF. which is given by RO = Vt Vt 1 = = .task by sensing the respective output currents and feeding a control signal back to the main forward loop. and gmD is the NF 2 transconductance of MND. Fig. without the CMFB portion. 4 . in turn.
which flows through bias resistor RB1 and is mirrored to flow through bias resistor RB2 . With the help of the CMFB circuit and replication circuits in the input and gain stages. only a brief intuitive description is offered here. gain stage. provided that the rail-to-rail supply voltage is greater than about 1. and (3) in the transition region where both differential pairs conduct current. output drivers.To drive the HSD and LSD. They are designed to provide enough headroom from either supply rail to insure that all current sources stay in the saturation region. 4 shows a simplified diagram of the input stage. Since a detailed analysis of a similar input stage is presented in . while the NMOS counterpart handles input voltages up to the positive supply. The circuit is biased from a 2 µA current source. The PMOS and the NMOS differential input pairs operate in parallel. The following section describes the circuit operation of each stage. A. 5 .5 V. These resistors provide dc bias voltages for cascode transistors throughout the entire circuit. The PMOS pair accommodates input voltages down to the negative supply. These include when the input voltage is (1) low enough such that only the PMOS differential pair conducts. It allows rail-to-rail input common-mode range with supply voltages as low as about 1.CIRCUIT IMPLEMENTATION The complete circuit diagram for the class AB amplifier. including the input stage. Input Stage The input stage of the operational amplifier is similar to the bipolar input stage reported in . dual in-phase signals are required. Three regions of input common. 3. III .mode operation exist. and CMFB circuit is shown in Fig.5 V. (2) high enough such that only the NMOS pair conducts. these two signals are generated. Fig.
the effective input common. For supply voltages above 2 V. and MN04.mode range limits.Both input pairs conduct current in the transition region. MN03 . the resulting input common. level-shift voltages are developed across resistors RS1 through RS4 . MP03 .7 V. in the end. The input impedance of the input stage.5 V and the input voltage is 0. 3 dynamically control the actual magnitude of the level-shift voltage by transferring the appropriate amount of MP06 ’s current into the levelshift resistors. For example.mode input signal determines the state of current IX by turning it on only when both differential pairs approach their common. The common. For the NMOS pair. Similarly.length modulation effects and transistor mismatches . both MP013 and MN011 conduct current and IX is established. current IX in Fig.VSS < VT N + VT P + 4VDS . either or both MP013 and MN011 would be cut off since both NMOS and PMOS differential pair current source voltages cannot simultaneously approach their triode regions. For the case of lower supply voltages. 4 is zero. 3.mode voltage of the PMOS pair is decreased. 6 . Level shifting the inputs circumvents the condition near the middle of the input range where both input pairs are non-operational. is only compromised by the mirroring inaccuracies of MP08 . only when both differential pairs’ current sources approach the triode region will current IX be established. if the supply voltage is 4 V. which occurs when VCC . so long as the total supply voltage is greater than about 2 V. If the supply voltage is 1.mode voltage is increased thereby insuring proper operation with the given headroom. for example. In other words. resulting from channel. a state that is determined by the reference voltages impressed on resistors RV1 and RV2 in Fig. (2) Comparators MN011-MN012 and MP013-MP014 in Fig. The input resistance of the amplifier remains high because the current sourced into the resistors is simultaneously sunk at the other end.
The circuit transconductance is given by Iβ gm = 2 Iβ Iβ where β Ν is made to equal β P ( ß = k ′ W L ). The gain stage consists of cascode transistors MP12 -MP14 and MN13 -MN15 along with current sources MP10 . and all of MP02 ’s current flows into the PMOS pair. however. This topology is commonly used in bipolar rail-to-rail input stages to achieve constant transconductance over the common. respectively. B. MP11 and MN10-MN12 . at input voltages near VCC. ↑ ICMR transition region . At common.mode input range. The output currents from the PMOS and the NMOS input pairs are split by MP011 . ↓ ICMR (3) 7 . Instead. Conversely. Gain Stage The amplifier uses a folded-cascode current-summing gain stage with two output branches to provide dual in-phase output voltages for the class AB output stage.to-rail CMOS input stages. 3 senses the input vo ltage and functions as a currentsteering switch to regulate the amount of tail current in each input pair. the transconductance varies by the square root of two over the entire input range. and are summed into the gain stage’s high impedance output nodes. This is less variation than constant current rail. MP09 conducts and transfers all of MP02 ’s current to the NMOS pair via MN06 and MN07. MP012 and MP13 . In CMOS circuits.The input stage also includes circuitry to stabilize transconductance over the commonmode input range. MP14 .mode input voltages near VSS. Transistor MP09 in Fig. such as the one reported in . the dominant high impedance nodes of the main loop. the resulting transconductance is not constant because of the nonlinear dependence of transconductance upon quiescent current. MP09 is off.
Transistors MNCMR. In this case. The magnitude of the steady-state driver quiescent current is thus determined by the current flowing through RCMR and MNCMR. forcing them to flow through resistors RCMN and RCMP . MNCMN. Output Stage with Common Mode Feedback The inputs to the high side and low side output drivers in Fig. the voltage drops across RCMN and RCMP are not equal. 8 . The outputs of the drivers share a common connection. biased from ICM1. The amplifier. in essence. in the form of voltages across resistors RCMN and RCMP . respectively.C. Currentcontrolled currents IDP and IDN sink currents proportional to the driver currents. A simplified diagram of the common. 5. Current sources MP210 and MP211 bias the low side driver while MN215 and MN216 bias the high side driver. In a steady-state no. senses the lower of the two currents. regulates to the lower of the two currents to a point established by ICM2. compares this voltage to a reference voltage and feeds back an error signal to the gain stage. as discussed in Section II. and MNCMP are designed to nominally have equal gate-source voltages. indicating equal amounts of current through both drivers. The loop then. 3 are the gates of MPF and MNF. and directs the signal to the input of amplifier Av .mode feedback circuit forces the voltage across RCMN or RCMP to be equal to the voltage across reference resistor RCMR.mode feedback circuit is shown in Fig.load condition. which is the output of the operational amplifier. both MNCM1 and MNCM2 conduct current and insure class AB operation. The source follower pair. in turn. the voltage drops across R CMN and R CMP are roughly equal. Consequently. The voltage imbalance causes the source follower corresponding to the larger voltage drop to cut off. When the output stage is sourcing or sinking load current. the common. The gates of bias transistors MNB and MPB are tied to the same bias points as the cascode transistors in the amplifier gain stage.
and the common. if the output voltage is near the high end of the output voltage range. MN217 starts to conduct less current and.mode transistors M and MP28 for biasing. Device MN217 is sized such that this condition occurs just before MPF turns off such that the alternative signal path exists before the source 9 . and are current mirrors designed to reproduce a small fraction of the driver currents (MND and MPD). An alternative signal path is therefore generated and control of MPD is guaranteed throughout the output voltage range. MP23. as previously discussed. and MP24 start conducting current. thereby modulating the voltage at the inputs of the HSD and LSD circuits and controlling the driver currents. with common. when the output is within 1. as the output voltage decreases.5 V of VSS.5 V above VSS. and the HSD circuit operates normally. the common. MN217 senses the voltage at the input of the HSD and. 3.mode feedback signal propagates through the source follower and the localized feedback loop to control the driver current. the HSD functions normally. MN219 . the gate-source voltage of MN217 is large. CMFB control is lost.follower MPF cuts off. Rail-to-Rail Control In the HSD.In Fig.mode error signal must have an alternative path to control the driver current (MPD). when the output voltage is approximately 1. breaking the HSD loop. Transistors MN217-MN219 and MP23-MP24 provide this alternative path. transistors MN218 . The P26 P27 differential outputs of the error amplifier force a differential current back into the gain stage. then. Just before this happens. On the other hand. However. otherwise. D. The CMFB amplifier is made up of input pair M and MP29 . which is turned around by current mirror MN25-MN26 before being applied to RCMP . the HSD input p-type source. at the point where its current is less than that of MP22 . Device MNDS mirrors MND's current and MPDS mirrors MPD's current. MP24 is off. dependent current sources IDP and IDN correspond to MN26 and MNDS.
designed to be non-dominant. g mNFg mNDrds −N 20 10 (7) . as defined in Equation (1) and given by p2 ≈ where 1 . Its frequency is determined by the load capacitor and the effective output impedance. the dominant low frequency pole must be the high. at the gates of MNF and MPF. E. by inspecting Equations (1) and (5) more carefully. The output constitutes the second non-dominant pole. Compensation Since the amplifier topology consists of a single high. (6) A third. Compensation capacitors CC2 and CC3 are placed on these nodes to the supplies to insure that these nodes are the dominant poles in the main feedback loop.follower path desists.impedance gain stage. The impedance can be estimated by Ro LSD ≈ [1 + s (rds −N 20C GS− ND ) ] . Intuitively. but these operate in parallel. high impedance nodes. In the end.impedance node. Two of these nodes exist in this case. A complementary control circuit is similarly used in the LSD counterpart. MN217 functions as a linear transconductance amplifier when the output voltage is below 1. it is evident that the impedance increases at a frequency roughly defined by RDS-N20 and CGS-ND.5 V. pole is introduced by the driver loops at the gates of MND and MPD. 2π(Ro LSD Ro HSD ) C L (4) Ro LSD ≈ 1 g mNFg mND rds − N 20 (5) and Ro HSD ≈ 1 g mPFg m P Drds −P 20 . so they may be treated as a single node for this analysis.
at the gates of MNF and MPF. this pole cannot be too low. The CMFB loop has two high impedance nodes. though. the ac signals propagate through the drivers via source followers MNF and MPF. to insure stability of the local loops. The gates of MNCMP and MNCMN constitute the third non-dominant poles of this loop. which lead to the low impedance sources of MPB and MNB and. Capacitors CC1 and CC4 were added for this reason. Simultaneously. Miller compensation is used to split the two poles. and one within the drivers themselves. However.In other words. 11 . to the high impedance gates of MND and MPD. Resistors RC1 and RC2 were added to bring the Right-Half Plane (RHP) zeros back into the Left-Half Plane (LHP) to help optimize phase margin. for this loop to be stable. the pole at this node is made dominant. being the only high impedance node in the loop. ultimately. The reason behind resis tors RC1 and RC2 and their connections to the gates of MNF and MPF have to do with the stability of the CMFB circuit. no high impedance poles are added thereby preserving the stability conditions of the CMFB loop.to-rail control circuit (MN217 and MP214 ) are used. to insure stability of the overall loop. otherwise overall phase margin of the main loop is compromised. Ro LSD increases thereby establishing an additional pole in the main forward loop. It is noted that when the alternative signal paths in the rail. Resistance Ro LSD behaves in a similar fashion. before converting it to a current back in the CMFB circuit. Since their respective resistances and associated capacitor va lues are low. at the gates of MND and MPD. at frequencies greater than the aforementioned pole. which is why CC1 and CC4 are connected back to the gates of MPF and MNF. For the CMFB circuit. they are easily kept at high frequencies. Thus. the one shared with the main loop.
when the input voltage is lower than 3. Closer inspection of the output stage and rail-to-rail control circuitry reveals this condition is attainable only when the total supply voltage is greater than about 3. VCC − VSS ≥ 2VT N + 2VT P + 4VDS . the supply voltage should be roughly greater than 3. Similarly.F. (9) Coincidentally. For the HSD to function as described in Section II.2 V. otherwise. as mandated by M P214 and M . VOUT must be at least VT N + VTP below VCC. either the HSD or LSD must be functioning regardless of output voltage.2 V. Optimum Operation The amplifier’s closed. for this approximation to be valid over the entire output voltage range. g mFro 2 g mD A V (8) where R O-LSD and R O-HSD are the output resistance of the LSD and HSD circuits.2 V. as mandated by MPF and MN217 . VOUT must be at least VT N + VTP greater than VSS. since the output node is still part of the CMFB feedback loop through the alternate CMFB path. Otherwise the follower would be cut off and the alternate NF CMFB path would be activated. the output resistance of the drivers degrade since the localized feedback look is broken. Clearly.loop output impedance can be estimated by dividing the result of Equation (1) by the gain of the main feedback loop. the circuit still has very low output impedance. Thus. RO − CL ≈ RO − LSD // RO − HSD AV ≤ 1 . 12 . respectively. even in the middle of the range where the limitation is worst. to insure that one driver circuit is always on. This requires that the supply voltage be large enough to allow the HSD to assume control of the output before the LSD cuts off. in the LSD. and vice versa.
less variable. which are present due to modulation of the common. which is important in battery-operated environments. 13 .mode input voltage. Fig.IV . Since g is relatively constant.mode voltage. since a single gain-stage topology was used. 8.5 V supply in Fig. in other words. the estimated peak transconductance was not attained.mode output voltage. the gain m variations mostly reflect changes in the output impedance of the gain stage. Open. best efficiency. Since the region for which both differential pairs conducted was narrow. Fig. 8(a) shows how the circuit gain varies with common. Other parameters were similar. The left side of the hump is the region where the PMOS differential pair is conducting and the right side is where the NMOS pair is conducting. The proposed circuit has the best peak output-current performance as well as the lowest quiescent-current flow. These plots demonstrate the true class AB behavior of the output stage over the full range of supply voltages. The ac characteristics of the amplifier are shown in Fig. 6(b). 7 as a function of the input common. response was shown. a lower. 6 shows the current through driver transistors M and MPD as a function of ND common. As predicted. It is also capable of working down to supply voltages of 1. the lowest of the competing amplifiers surveyed. with a 1. A summary of this comparison is given in Table 1.loop gain was lower in the proposed circuit. Fig. 6(a) and a 6 V supply in Fig.mode feedback signal.5 V. 8(b) shows supply rejection as a function of frequency for several different output voltages. however.SIMULATED RESULTS The amplifier was simulated and compared with other state-of-the-art class AB amplifiers. transconductance increases when both input pairs conduct and the peak gm is exhibited. instead. The input stage transconductance is shown in Fig.
rail-to-rail. the pulse goes from –1 to 1 V and the output is connected to a 350 Ω / 100 pF load to ground to show the circuit’s behavior as it is forced to quickly go from sinking to sourcing current. The DC output resistance is on the order of hundreds of micro-ohms in Figs.5 V supply and the amplifier’s rail.to-rail input/output operation with low quiescent 14 .2 V. The propagation delay of the circuit was roughly between 2 and 2. Novel high side and low side output drivers. with a maximum output current of ±7 mA with a ±3 V supply. MND and MPD.mode output voltage and load current. 10 as a function of common. utilizing source followers in conjunction with common source drivers.to-rail input pulse with a 1.to-rail response when loaded with 10 kΩ and 100 pF. A typical quiescent current of less than 140 µA was achieved over the full output current range.to-rail operation. 10(a) and (b). 9(b).5 V. The circuit’s output impedance is shown in Fig. even when there is little current being sourced or sunk. In Fig.Fig. for the case of higher supply voltages. the output impedance is increased by approximately an order of magnitude when the supply voltage is dropped to 1. is achieved at supply voltages greater than 3. The amplifier is fully functional with supplies as low as 1. Low voltage rail. while still allowing rail. V . with regards to output impedance. These figures are designed to show how the output impedance remains low throughout the operating range of voltages and loads. 9(a) shows a rail. class AB amplifier with high output drive and low output impedance was presented.CONCLUSIONS A CMOS low voltage. 9 shows the amplifier’s response to a pulse on the input when configured for unity gain.5 µs. were shown to significantly lower the output impedance of the amplifier. showing very stable characteristics. In Fig 10(c). The output voltage is limited only by the required drain-source voltages of the driver transistors. Fig.5 V and optimum operation.
current flow and high output current make it ideal for battery-powered applications where efficiency is paramount for battery life and extended dynamic range is intrinsic for performance. 15 .
Maris. “Compact Low-Voltage Power-Efficient Operational Amplifier Cells for VLSI”. pp. Klaas-Jan de Langen. Johan H.REFERENCES  Soundarapandian Karthikeyan. 1989. IEEE J. 33. vol. Feb. Francisco Duque-Carrillo. Circuits and Systems II. 466-473. 31. IEEE J. Solid-State Circuits. Ausin. Joseph N. Geiger. “Low Voltage Analog Circuit Design Based on Biased Inverting Opamp Configuration”. J. 33-44. 1990. 1482-1496. Valverde. Jose M. 2000. Jose L. Allen. pp. Erik J. Phillip E. 1551-1559. Solid-State Circuits. Analysis and Design of Analog Integrated Circuits. IEEE J. Gray and Robert G. F. pp. Meyer. vol. McGraw-Hill. IEEE Trans. 1991. and Edward K. Solid-State Circuits. vol. pp. vol. 35. IEEE J. 47. Huijsing. IEEE J. 1993. Anilkumar Tamineedi. 1998 Randall L. Jeroen Fonderie. “1-V Rail-to. Paul R. 1996. 1825-1833. Dominguez. “A Low-Output-Impedance Fully Differential Op Amp with Large Output Swing and Continuous-Time Common-Mode Feedback”. 146-156. VLSI Design Techniques for Analog and Digital Circuits. “1-V Operational Amplifiers with Rail-to-Rail Input and Output Ranges”. Dec. vol. and Johan H. pp. Siamak Mortezapour. and Miguel A. Solid-State Circuits. Strader. pp. Noel R. March 2000.        16 . 24. John Wiley & Sons. Oct. 26. Babanezhad. Guido Torelli. 176-184. Huijsing. Solid-State Circuits. Satoshi Sakurai and Mohammed Ismail. pp. Schnitger. Lee. Marinus M. vol. Dec.Rail Operational Amplifiers in Standard CMOS Technology”. “Robust Design of Rail-to-Rail CMOS Operational Amplifiers for a Low Power Supply Voltage”. Jan.
0 5 VDD VSS VDD VSS VDD .0 -0.4 75 100  5 714 ±4.5 140 ±7. Parameter Minimum supply voltage Supply current Peak output current Input offset voltage CM input range Output voltage range (Iout = 0 mA) Output voltage range (Iout = ±4.0. RL = 10 kΩ) Unity.3 VSS + 0.3 -48 300 80 65 0.0 mA) THD (1 kHz.2 VSS VDD VSS VDD .0.4 100 100  1.Table 1.8 230 1.3 VSS + 0.2 6 VDD VSS VDD VSS N/A N/A -41 4000 67 86 4.3 N/A 500 70 95 0.gain frequency Phase margin Open-loop gain Slew rate Power supply rejection Max capacitive load max min max min max min Proposed Amplifier 1. 1 V.5 N/A N/A Units V µA mA mV V V V V V V dB kHz ° dB V/µs dB pF 17 . Summary of class AB amplifier performance.5 VDD-1.
1. 18 .VCC MPD HSD MPF A CMFB + VIN - AV A ZL MNF LSD MND VSS CMFB VOUT Fig. Circuit topology of the proposed class AB amplifier.
VCC I1 VBIAS ro1 MPB MNF VIN MNF It VOUT MND Vt I2 VSS (a) (b) MND gmF Vt MPB gmF Vtro2 gmF Vtro2 gmD ro2 Fig. 2. (a) Simplified circuit diagram of the low side output driver (LSD) and (b) the ac equivalent circuit used to calculate its output impedance. 19 .
3. Complete circuit diagram for the class AB amplifier. 20 .Biasing VCC MP01 MP02 2µ A Input Stage MP06 MP03 MP08 MP04 MP05 MP07 Gain Stage MP10 MP11 Output Stage Rail-to-Rail Control MP22 MP21 MP23 MP24 Common Mode Feedback Circuit MP25 RCMP MP20 MN219 RCMN RCMR RB2 MP14 MN218 MPD MPDS MP09 MP12 RC1 CC1 MNCMN MNCMP MNCMR MP13 MN013 MN014 RV1 MPF MN217 MNB MP26 MP27 MP28 MP29 RS1 CC2 MN216 MN215 + VIN RS4 CC3 MP010 MP011 MP012 MN011 MN012 MP013 MP014 MN14 MN13 RB1 MN15 RC2 MND CC4 MP210 RS2 RS3 V OUT MP211 MPB MP214 MNF MN214 MN213 MN212 MNDS MN03 MN05 MN04 MN06 MN07 MN09 MN08 RV2 MN11 MN20 MN10 MN12 MN21 MP212 MP213 MN26 MN23 MN24 MN22 MN25 MN28 MN27 MN29 MN210 MN02 MN01 MN010 VSS Fig.
Simplified schematic diagram of the amplifier input stage.VCC IBIAS IX IX=f(VINCM) MN1 MN2 + VIN RS2 MP1 MP2 R S4 RS1 RS3 To Gain Stage IX VSS IX IBIAS Fig. 4. 21 .
Simplified schematic diagram of the common. 5. 22 .mode feedback circuit.VCC RCMP RCMR RCMN MNCM2 MNCM1 M NCMR AV + To Gain Stage IDP ICM1 VSS IDN ICM2 Fig.
5 0. (a) VIN = ±0.5 1.7 -0.3 0.75 V and (b) VIN = ±3 V.80 70 60 VIN = 1.1 0. Class AB output stage driver currents vs. 23 . common mode output voltage.5 -0.0E-03 VIN = 6 V I (A) 1.5 -1.5 -0. 6.5 VCM (V) (b) Fig.0E-02 1.1 0.0E-05 1.3 -0.5 0.5 V RL = 10 kΩ IMND IMPD I (µ A) 50 40 30 20 10 0 -0.0E-06 -2.7 VCM (V) (a) 1.5 2.0E-04 IMND IMPD RL = 350 Ω 1.
1.9 -2.2 gm (normalized) 1.5 2.5 -0.05 1 0.15 1. Input stage transconductance gm vs. common mode input voltage VCM.25 1. 7.5 VCM (V) Fig.5 1. 24 .5 -1.5 0.1 1.95 0.
5V Vo = 2. (a) AC gain and phase characteristics of the class AB amplifier.0E+02 1.Gain (dB) and Phase (degrees) 200 150 100 50 0 -50 Vo = 0V Vo = -2.0E+07 -100 1.0E+07 0 1.0E+02 1.5V VIN = 6 V RL = 1 kΩ C L = 100 pF 1.0E+04 1.0E+03 1.0E+04 1.0E+06 1.0E+00 Frequency (Hz) (a) 160 140 120 Vo = 1 V Vo = 2 V Vo = 3 V Vo = 4 V PSR (dB) 100 80 60 40 20 IL = 1 mA VCC = 5 V 1.0E+03 1.0E+05 1.0E+01 1.0E+00 Frequency (Hz) (b) Fig. and (b) Power supply rejection vs. frequency for several different common mode output voltages. 8.0E+01 1. 25 .0E+05 1.0E+06 1.
5 0 -0.8 -1 0 10 20 30 40 50 60 70 80 Time (µ S) (a) 1.6 -0.4 -0.5 0 10 20 30 VIN VOUT C L = 100 pF RL = 350 Ω VIN = ±3 V VOUT (V) Time (µ S) (b) 40 50 60 70 80 Fig. (a) Unity.75 V VOUT (V) 0. 26 .2 0 -0.5 -1 -1.1 0.4 VIN VOUT CL = 100 pF RL = 10 kΩ VΙΝ = ±0. 9.5 1 0.2 -0.6 0.gain rail-to-rail step response of the amplifier with minimum supply voltage and (b) step response with maximum supply voltage.8 0.
common.5 0.5 1.0E-03 -0.mode output voltage VOCM for a 350 Ω load with ±3 V supply. (a) Amplifier output impedance Zo vs. 27 .0E-04 1.5 VO C M (V) (a) 1.0E-05 -2.3 0.0E+00 1.0E-02 1. load current IL with ±3 V supply.1.0E+00 RL = 350 Ω C L = 100 pF 1.0E-02 f = 1 kHz DC Zo ( Ω) 1. and (c) output impedance Zo vs.3 -0.0E-04 1. (b) output impedance Zo vs.5 2. common mode output voltage VOCM with ±0.0E-03 1.7 VOCM (V) (c) Fig.75 V supply.0E-05 -7 -5 -3 -1 1 3 5 7 IL (mA) (b) 1.5 -0.0E+01 RL = 10 kΩ C L = 100 pF 1.0E-03 1.0E+00 DC f = 1 kHz Zo ( Ω) 1.0E-02 1.0E-01 1.1 0.5 -0. 10.5 -1.1 0.7 -0.0E-01 1.0E-01 C L = 100 pF Vo = 0 V f = 1 kHz DC Zo ( Ω ) 1.5 0.
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