3-BIT RIPPLE COUNTER USING T-FF - USE INSTANTIATION TECHNIQUE T-FLIPFLOP library IEEE; use IEEE.STD_LOGIC_1164.

ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC; qb : out STD_LOGIC); end tff; architecture Behavioral of tff is begin process(clk,rst) begin if(rst='1')then q<='1'; qb<='0'; elsif (clk'event and clk='1')then qb<= t; q<= not t; end if; end process; end Behavioral; 3-BIT RIPPLE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

end ripplecount. qb : out STD_LOGIC). end component. q=> ncount(1). bit1: tff port map (clk => ncount(0). bit2: tff port map (clk => ncount(1). clk : in STD_LOGIC. architecture structural of ripplecount is component tff Port ( t : in STD_LOGIC. rst : in STD_LOGIC. rst=> rst. rst=> rst. rst : in STD_LOGIC. end structural. t=> ncount(0). t=> ncount(2). rst=> rst.entity ripplecount is Port ( clk : in STD_LOGIC. qb=> count(1)). q=> ncount(2). q=> ncount(0). count : out STD_LOGIC_VECTOR (2 downto 0)). qb=> count(2)). qb=> count(0)). . t=> ncount(1). q : out STD_LOGIC. signal ncount : STD_LOGIC_VECTOR (2 downto 0). begin bit0: tff port map (clk => clk.

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