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Introduction to Microelectronics

Over the past ﬁve decades, microelectronics has revolutionized our lives. While beyond the realm of possibility a few decades ago, cellphones, digital cameras, laptop computers, and many other electronic products have now become an integral part of our daily affairs. Learning microelectronics can be fun. As we learn how each device operates, how devices comprise circuits that perform interesting and useful functions, and how circuits form sophisticated systems, we begin to see the beauty of microelectronics and appreciate the reasons for its explosive growth. This chapter gives an overview of microelectronics so as to provide a context for the material presented in this book. We introduce examples of microelectronic systems and identify important circuit “functions” that they employ. We also provide a review of basic circuit theory to refresh the reader’s memory.

**1.1 Electronics versus Microelectronics
**

The general area of electronics began about a century ago and proved instrumental in the radio and radar communications used during the two world wars. Early systems incorporated “vacuum tubes,” amplifying devices that operated with the ﬂow of electrons between plates in a vacuum chamber. However, the ﬁnite lifetime and the large size of vacuum tubes motivated researchers to seek an electronic device with better properties. The ﬁrst transistor was invented in the 1940s and rapidly displaced vacuum tubes. It exhibited a very long (in principle, inﬁnite) lifetime and occupied a much smaller volume (e.g., less than 1 cm3 in packaged form) than vacuum tubes did. But it was not until 1960s that the ﬁeld of microelectronics, i.e., the science of integrating many transistors on one chip, began. Early “integrated circuits” (ICs) contained only a handful of devices, but advances in the technology soon made it possible to dramatically increase the complexity of “microchips.”

Example 1.1

Today’s microprocessors contain about 100 million transistors in a chip area of approximately 3 cm 3 cm. (The chip is a few hundred microns thick.) Suppose integrated circuits were not invented and we attempted to build a processor using 100 million “discrete” transistors. If each device occupies a volume of 3 mm 3 mm 3 mm, determine the minimum volume for the processor. What other issues would arise in such an implementation? The minimum volume is given by 27 mm3 108 , i.e., a cube 1.4 m on each side! Of course, the

1

Solution

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wires connecting the transistors would increase the volume substantially. In addition to occupying a large volume, this discrete processor would be extremely slow; the signals would need to travel on wires as long as 1.4 m! Furthermore, if each discrete transistor costs 1 cent and weighs 1 g, each processor unit would be priced at one million dollars and weigh 100 tons!

Exercise

How much power would such a system consume if each transistor dissipates 10 W?

This book deals with mostly microelectronics while providing sufﬁcient foundation for general (perhaps discrete) electronic systems as well.

**1.2 Examples of Electronic Systems
**

At this point, we introduce two examples of microelectronic systems and identify some of the important building blocks that we should study in basic electronics. 1.2.1 Cellular Telephone Cellular telephones were developed in the 1980s and rapidly became popular in the 1990s. Today’s cellphones contain a great deal of sophisticated analog and digital electronics that lie well beyond the scope of this book. But our objective here is to see how the concepts described in this book prove relevant to the operation of a cellphone. Suppose you are speaking with a friend on your cellphone. Your voice is converted to an electric signal by a microphone and, after some processing, transmitted by the antenna. The signal produced by your antenna is picked up by the your friend’s receiver and, after some processing, applied to the speaker [Fig. 1.1(a)]. What goes on in these black boxes? Why are they needed?

Transmitter (TX) Microphone ? ? (a) (b) Figure 1.1 (a) Simpliﬁed view of a cellphone, (b) further simpliﬁcation of transmit and receive paths. Receiver (RX) Speaker

Let us attempt to omit the black boxes and construct the simple system shown in Fig. 1.1(b). How well does this system work? We make two observations. First, our voice contains frequencies from 20 Hz to 20 kHz (called the “voice band”). Second, for an antenna to operate efﬁciently, i.e., to convert most of the electrical signal to electromagnetic radiation, its dimension must be a signiﬁcant fraction (e.g., 25) of the wavelength. Unfortunately, a frequency range of 20 Hz to 20 kHz translates to a wavelength1 of 1:5 107 m to 1:5 104 m, requiring gigantic antennas for each cellphone. Conversely, to obtain a reasonable antenna length, e.g., 5 cm, the wavelength must be around 20 cm and the frequency around 1.5 GHz.

1 Recall that the wavelength is equal to the (light) velocity divided by the frequency.

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How do we “convert” the voice band to a gigahertz center frequency? One possible approach is to multiply the voice signal, xt, by a sinusoid, A cos2fc t [Fig. 1.2(a)]. Since multiplication in the time domain corresponds to convolution in the frequency domain, and since the spectrum

x (t )

Voice Signal

A cos( 2 π f C t )

Output Waveform

t

(a)

t

t

X (f )

Voice Spectrum −20 kHz +20 kHz 0

Spectrum of Cosine

Output Spectrum

f

−fC

0

+fC f

−fC

0

+fC

f

(b)

Figure 1.2 (a) Multiplication of a voice signal by a sinusoid, (b) equivalent operation in the frequency domain.

of the sinusoid consists of two impulses at fc , the voice spectrum is simply shifted (translated) to fc [Fig. 1.2(b)]. Thus, if fc = 1 GHz, the output occupies a bandwidth of 40 kHz centered at 1 GHz. This operation is an example of “amplitude modulation.”2 We therefore postulate that the black box in the transmitter of Fig. 1.1(a) contains a multiplier,3 as depicted in Fig. 1.3(a). But two other issues arise. First, the cellphone must deliver

Power Amplifier

A cos( 2 π f C t )

(a)

Oscillator (b)

Figure 1.3 (a) Simple transmitter, (b) more complete transmitter.

a relatively large voltage swing (e.g., 20 Vpp ) to the antenna so that the radiated power can reach across distances of several kilometers, thereby requiring a “power ampliﬁer” between the multiplier and the antenna. Second, the sinusoid, A cos 2fc t, must be produced by an “oscillator.” We thus arrive at the transmitter architecture shown in Fig. 1.3(b). Let us now turn our attention to the receive path of the cellphone, beginning with the simple realization illustrated in Fig. 1.1(b). Unfortunately, This topology fails to operate with the principle of modulation: if the signal received by the antenna resides around a gigahertz center frequency, the audio speaker cannot produce meaningful information. In other words, a means of

2 Cellphones in fact use other types of modulation to translate the voice band to higher frequencies. 3 Also called a “mixer” in high-frequency electronics.

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translating the spectrum back to zero center frequency is necessary. For example, as depicted in Fig. 1.4(a), multiplication by a sinusoid, A cos2fc t, translates the spectrum to left and right by

Output Spectrum Received Spectrum Spectrum of Cosine

−fC

0

+fC

f

−fC

0

+fC f (a)

−2 f C

0

+2 f C

f

Low−Noise Amplifier Low−Pass Filter Low−Pass Filter

Amplifier

oscillator (b)

oscillator (c)

Figure 1.4 (a) Translation of modulated signal to zero center frequency, (b) simple receiver, (b) more complete receiver.

fc , restoring the original voice band. The newly-generated components at 2fc can be removed

by a low-pass ﬁlter. We thus arrive at the receiver topology shown in Fig. 1.4(b). Our receiver design is still incomplete. The signal received by the antenna can be as low as a few tens of microvolts whereas the speaker may require swings of several tens or hundreds of millivolts. That is, the receiver must provide a great deal of ampliﬁcation (“gain”) between the antenna and the speaker. Furthermore, since multipliers typically suffer from a high “noise” and hence corrupt the received signal, a “low-noise ampliﬁer” must precede the multiplier. The overall architecture is depicted in Fig. 1.4(c). Today’s cellphones are much more sophisticated than the topologies developed above. For example, the voice signal in the transmitter and the receiver is applied to a digital signal processor (DSP) to improve the quality and efﬁciency of the communication. Nonetheless, our study reveals some of the fundamental building blocks of cellphones, e.g., ampliﬁers, oscillators, and ﬁlters, with the last two also utilizing ampliﬁcation. We therefore devote a great deal of effort to the analysis and design of ampliﬁers. Having seen the necessity of ampliﬁers, oscillators, and multipliers in both transmit and receive paths of a cellphone, the reader may wonder if “this is old stuff” and rather trivial compared to the state of the art. Interestingly, these building blocks still remain among the most challenging circuits in communication systems. This is because the design entails critical trade-offs between speed (gigahertz center frequencies), noise, power dissipation (i.e., battery lifetime), weight, cost (i.e., price of a cellphone), and many other parameters. In the competitive world of cellphone manufacturing, a given design is never “good enough” and the engineers are forced to further push the above trade-offs in each new generation of the product. 1.2.2 Digital Camera Another consumer product that, by virtue of “going electronic,” has dramatically changed our habits and routines is the digital camera. With traditional cameras, we received no immediate

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feedback on the quality of the picture that was taken, we were very careful in selecting and shooting scenes to avoid wasting frames, we needed to carry bulky rolls of ﬁlm, and we would obtain the ﬁnal result only in printed form. With digital cameras, on the other hand, we have resolved these issues and enjoy many other features that only electronic processing can provide, e.g., transmission of pictures through cellphones or ability to retouch or alter pictures by computers. In this section, we study the operation of the digital camera. The “front end” of the camera must convert light to electricity, a task performed by an array (matrix) of “pixels.”4 Each pixel consists of an electronic device (a “photodiode” that produces a current proportional to the intensity of the light that it receives. As illustrated in Fig. 1.5(a), this current ﬂows through a capacitance, CL , for a certain period of time, thereby developing a

25

Amplifier

00 C ol

um

ns

Light

I Diode CL

Photodiode (a) (b)

V out

2500 Rows

Signal Processing (c)

Figure 1.5 (a) Operation of a photodiode, (b) array of pixels in a digital camera, (c) one column of the array.

proportional voltage across it. Each pixel thus provides a voltage proportional to the “local” light density. Now consider a camera with, say, 6.25-million pixels arranged in a 2500 2500 array [Fig. 1.5(b)]. How is the output voltage of each pixel sensed and processed? If each pixel contains its own electronic circuitry, the overall array occupies a very large area, raising the cost and the power dissipation considerably. We must therefore “time-share” the signal processing circuits among pixels. To this end, we follow the circuit of Fig. 1.5(a) with a simple, compact ampliﬁer and a switch (within the pixel) [Fig. 1.5(c)]. Now, we connect a wire to the outputs of all 2500 pixels in a “column,” turn on only one switch at a time, and apply the corresponding voltage to the “signal processing” block outside the column. The overall array consists of 2500 of such columns, with each column employing a dedicated signal processing block.

Example 1.2

A digital camera is focused on a chess board. Sketch the voltage produced by one column as a function of time.

4 The term “pixel” is an abbreviation of “picture cell.”

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Solution

The pixels in each column receive light only from the white squares [Fig. 1.6(a)]. Thus, the

V column V column t

(a) (b) (c) Figure 1.6 (a) Chess board captured by a digital camera, (b) voltage waveform of one column.

column voltage alternates between a maximum for such pixels and zero for those receiving no light. The resulting waveform is shown in Fig. 1.6(b).

Exercise

Plot the voltage if the ﬁrst and second squares in each row have the same color.

What does each signal processing block do? Since the voltage produced by each pixel is an analog signal and can assume all values within a range, we must ﬁrst “digitize” it by means of an “analog-to-digital converter” (ADC). A 6.25 megapixel array must thus incorporate 2500 ADCs. Since ADCs are relatively complex circuits, we may time-share one ADC between every two columns (Fig. 1.7), but requiring that the ADC operate twice as fast (why?). In the extreme case,

ADC

Figure 1.7 Sharing one ADC between two columns of a pixel array.

we may employ a single, very fast ADC for all 2500 columns. In practice, the optimum choice lies between these two extremes. Once in the digital domain, the “video” signal collected by the camera can be manipulated extensively. For example, to “zoom in,” the digital signal processor (DSP) simply considers only

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a section of the array, discarding the information from the remaining pixels. Also, to reduce the required memory size, the processor “compresses” the video signal. The digital camera exempliﬁes the extensive use of both analog and digital microelectronics. The analog functions include ampliﬁcation, switching operations, and analog-to-digital conversion, and the digital functions consist of subsequent signal processing and storage. 1.2.3 Analog versus Digital Ampliﬁers and ADCs are examples of “analog” functions, circuits that must process each point on a waveform (e.g., a voice signal) with great care to avoid effects such as noise and “distortion.” By contrast, “digital” circuits deal with binary levels (ONEs and ZEROs) and, evidently, contain no analog functions. The reader may then say, “I have no intention of working for a cellphone or camera manufacturer and, therefore, need not learn about analog circuits.” In fact, with digital communications, digital signal processors, and every other function becoming digital, is there any future for analog design? Well, some of the assumptions in the above statements are incorrect. First, not every function can be realized digitally. The architectures of Figs. 1.3 and 1.4 must employ low-noise and power ampliﬁers, oscillators, and multipliers regardless of whether the actual communication is in analog or digital form. For example, a 20-V signal (analog or digital) received by the antenna cannot be directly applied to a digital gate. Similarly, the video signal collectively captured by the pixels in a digital camera must be processed with low noise and distortion before it appears in the digital domain. Second, digital circuits require analog expertise as the speed increases. Figure 1.8 exempliﬁes this point by illustrating two binary data waveforms, one at 100 Mb/s and another at 1 Gb/s. The ﬁnite risetime and falltime of the latter raises many issues in the operation of gates, ﬂipﬂops, and other digital circuits, necessitating great attention to each point on the waveform.

10 ns

x 1 (t )

1 ns

t

x 2 (t )

t

Figure 1.8 Data waveforms at 100 Mb/s and 1 Gb/s.

1.3 Basic Concepts

Analysis of microelectronic circuits draws upon many concepts that are taught in basic courses on signals and systems and circuit theory. This section provides a brief review of these concepts so as to refresh the reader’s memory and establish the terminology used throughout this book. The reader may ﬁrst glance through this section to determine which topics need a review or simply return to this material as it becomes necessary later. 1.3.1 Analog and Digital Signals An electric signal is a waveform that carries information. Signals that occur in nature can assume all values in a given range. Called “analog,” such signals include voice, video, seismic, and music

This section serves as a review and can be skipped in classroom teaching.

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waveforms. Shown in Fig. 1.9(a), an analog voltage waveform swings through a “continuum” of

V (t (

V ( t ( + Noise

t

t

(a)

(b)

Figure 1.9 (a) Analog signal , (b) effect of noise on analog signal.

values and provides information at each instant of time. While occurring all around us, analog signals are difﬁcult to “process” due to sensitivities to such circuit imperfections as “noise” and “distortion.”5 As an example, Figure 1.9(b) illustrates the effect of noise. Furthermore, analog signals are difﬁcult to “store” because they require “analog memories” (e.g., capacitors). By contrast, a digital signal assumes only a ﬁnite number of values at only certain points in time. Depicted in Fig. 1.10(a) is a “binary” waveform, which remains at only one of two levels for

V (t (

ZERO

ONE

V ( t ( + Noise

T

T

(a)

t

(b)

t

Figure 1.10 (a) Digital signal, (b) effect of noise on digital signal.

each period, T . So long as the two voltages corresponding to ONEs and ZEROs differ sufﬁciently, logical circuits sensing such a signal process it correctly—even if noise or distortion create some corruption [Fig. 1.10(b)]. We therefore consider digital signals more “robust” than their analog counterparts. The storage of binary signals (in a digital memory) is also much simpler. The foregoing observations favor processing of signals in the digital domain, suggesting that inherently analog information must be converted to digital form as early as possible. Indeed, complex microelectronic systems such as digital cameras, camcorders, and compact disk (CD) recorders perform some analog processing, “analog-to-digital conversion,” and digital processing (Fig. 1.11), with the ﬁrst two functions playing a critical role in the quality of the signal.

Digital Processing and Storage

Analog Signal

Analog Processing

Analog−to−Digital Conversion

Figure 1.11 Signal processing in a typical system.

It is worth noting that many digital binary signals must be viewed and processed as analog waveforms. Consider, for example, the information stored on a hard disk in a computer. Upon retrieval, the “digital” data appears as a distorted waveform with only a few millivolts of amplitude

5 Distortion arises if the output is not a linear function of input.

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**(Fig. 1.12). Such a small separation between ONEs and ZEROs proves inadequate if this signal
**

~3 mV Hard Disk

t

Figure 1.12 Signal picked up from a hard disk in a computer.

is to drive a logical gate, demanding a great deal of ampliﬁcation and other analog processing before the data reaches a robust digital form. 1.3.2 Analog Circuits Today’s microelectronic systems incorporate many analog functions. As exempliﬁed by the cellphone and the digital camera studied above, analog circuits often limit the performance of the overall system. The most commonly-used analog function is ampliﬁcation. The signal received by a cellphone or picked up by a microphone proves too small to be processed further. An ampliﬁer is therefore necessary to raise the signal swing to acceptable levels. The performance of an ampliﬁer is characterized by a number of parameters, e.g., gain, speed, and power dissipation. We study these aspects of ampliﬁcation in great detail later in this book, but it is instructive to brieﬂy review some of these concepts here. A voltage ampliﬁer produces an output swing greater than the input swing. The voltage gain, Av , is deﬁned as

Av = vvout :

in

(1.1)

In some cases, we prefer to express the gain in decibels (dB):

**Av jdB = 20 log vvout :
**

in

(1.2)

For example, a voltage gain of 10 translates to 20 dB. The gain of typical ampliﬁers falls in the range of 101 to 105 . A cellphone receives a signal level of 20 V, but it must deliver a swing of 50 mV to the speaker that reproduces the voice. Calculate the required voltage gain in decibels.

Example 1.3

Solution

We have

Av = 20 log 50 mV 20 V 68 dB:

(1.3) (1.4)

Exercise

What is the output swing if the gain is 50 dB?

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In order to operate properly and provide gain, an ampliﬁer must draw power from a voltage source, e.g., a battery or a charger. Called the “power supply,” this source is typically denoted by VCC or VDD [Fig. 1.13(a)]. In complex circuits, we may simplify the notation to that shown in

Amplifier

**VCC V in Vout V CC V in Vout
**

Ground (a) (b) (c) Figure 1.13 (a) General ampliﬁer symbol along with its power supply, (b) simpliﬁed diagram of (a), (b) ampliﬁer with supply rails omitted.

V in

Vout

Fig. 1.13(b), where the “ground” terminal signiﬁes a reference point with zero potential. If the ampliﬁer is simply denoted by a triangle, we may even omit the supply terminals [Fig. 1.13(c)], with the understanding that they are present. Typical ampliﬁers operate with supply voltages in the range of 1 V to 10 V. What limits the speed of ampliﬁers? We expect that various capacitances in the circuit begin to manifest themselves at high frequencies, thereby lowering the gain. In other words, as depicted in Fig. 1.14, the gain rolls off at sufﬁciently high frequencies, limiting the (usable) “bandwidth”

Amplifier Gain

High−Frequency Roll−off

Frequency

Figure 1.14 Roll-off an ampliﬁer’s gain at high frequencies.

of the circuit. Ampliﬁers (and other analog circuits) suffer from trade-offs between gain, speed and power dissipation. Today’s microelectronic ampliﬁers achieve bandwidths as large as tens of gigahertz. What other analog functions are frequently used? A critical operation is “ﬁltering.” For example, an electrocardiograph measuring a patient’s heart activities also picks up the 60-Hz (or 50-Hz) electrical line voltage because the patient’s body acts as an antenna. Thus, a ﬁlter must suppress this “interferer” to allow meaningful measurement of the heart. 1.3.3 Digital Circuits More than 80 of the microelectronics industry deals with digital circuits. Examples include microprocessors, static and dynamic memories, and digital signal processors. Recall from basic logic design that gates form “combinational” circuits, and latches and ﬂipﬂops constitute “sequential” machines. The complexity, speed, and power dissipation of these building blocks play a central role in the overall system performance. In digital microelectronics, we study the design of the internal circuits of gates, ﬂipﬂops, and other components. For example, we construct a circuit using devices such as transistors to

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**realize the NOT and NOR functions shown in Fig. 1.15. Based on these implementations, we
**

NOT Gate NOR Gate

A

Y =A

A B

Y =A +B

Figure 1.15 NOT and NOR gates.

then determine various properties of each circuit. For example, what limits the speed of a gate? How much power does a gate consume while running at a certain speed? How robustly does a gate operate in the presence of nonidealities such as noise (Fig. 1.16)?

?

Figure 1.16 Response of a gate to a noisy input.

**Consider the circuit shown in Fig. 1.17, where switch S1 is controlled by the digital input. That
**

RL A S1 V DD Vout

Example 1.4

Figure 1.17

is, if A is high, S1 is on and vice versa. Prove that the circuit provides the NOT function. If A is high, S1 is on, forcing Vout to zero. On the other hand, if A is low, S1 remains off, drawing no current from RL . As a result, the voltage drop across RL is zero and hence Vout = VDD ; i.e., the output is high. We thus observe that, for both logical states at the input, the output assumes the opposite state.

Solution

Exercise

Determine the logical function if S1 and RL are swapped and Vout is sensed across RL .

The above example indicates that switches can perform logical operations. In fact, early digital circuits did employ mechanical switches (relays), but suffered from a very limited speed (a few kilohertz). It was only after “transistors” were invented and their ability to act as switches was recognized that digital circuits consisting of millions of gates and operating at high speeds (several gigahertz) became possible. 1.3.4 Basic Circuit Theorems Of the numerous analysis techniques taught in circuit theory courses, some prove particularly important to our study of microelectronics. This section provides a review of such concepts.

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I1 I2

In

Ij

Figure 1.18 Illustration of KCL.

Kirchoff’s Laws The Kirchoff Current Law (KCL) states that the sum of all currents ﬂowing into a node is zero (Fig. 1.18):

X

j

Ij = 0:

(1.5)

KCL in fact results from conservation of charge: a nonzero sum would mean that either some of the charge ﬂowing into node X vanishes or this node produces charge. The Kirchoff Voltage Law (KVL) states that the sum of voltage drops around any closed loop in a circuit is zero [Fig. 1.19(a)]:

2

V2

1

V2 V3

3 1

2 3

V1

V1

V3 V4

4

V4

4

(a)

(b)

Figure 1.19 (a) Illustration of KVL, (b) slightly different view of the circuit .

X

j

Vj = 0;

(1.6)

where Vj denotes the voltage drop across element number j . KVL arises from the conservation of the “electromotive force.” In the example illustrated in Fig. 1.19(a), we may sum the voltages in the loop to zero: V1 + V2 + V3 + V4 = 0. Alternatively, adopting the modiﬁed view shown in Fig. 1.19(b), we can say V1 is equal to the sum of the voltages across elements 2, 3, and 4: V1 = V2 + V3 + V4 . Note that the polarities assigned to V2 , V3 , and V4 in Fig. 1.19(b) are different from those in Fig. 1.19(a). In solving circuits, we may not know a priori the correct polarities of the currents and voltages. Nonetheless, we can simply assign arbitrary polarities, write KCLs and KVLs, and solve the equations to obtain the actual polarities and values.

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Example 1.5

The topology depicted in Fig. 1.20 represents the equivalent circuit of an ampliﬁer. The dependent current source i1 is equal to a constant, gm ,6 multiplied by the voltage drop across

v in v out RL

rπ

vπ i 1

g vπ R L m

v out

Figure 1.20

**r . Determine the voltage gain of the ampliﬁer, vout =vin .
**

We must compute vout in terms of vin , i.e., we must eliminate v from the equations. Writing a KVL in the “input loop,” we have

Solution

vin = v ;

and hence gm v

(1.7)

= gmvin . A KCL at the output node yields

gm v + vout = 0: R

L

It follows that

(1.8)

vout = ,g R : m L vin

Note that the circuit ampliﬁes the input if gm RL sign simply means the circuit “inverts” the signal.

(1.9)

1. Unimportant in most cases, the negative

Exercise

Repeat the above example if r

! infty.

Example 1.6

Figure 1.21 shows another ampliﬁer topology. Compute the gain.

rπ

vπ i 1

g vπ R L m

v out

v in

Figure 1.21

6 What is the dimension of

gm ?

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Noting that r in fact appears in parallel with vin , we write a KVL across these two components:

Solution

vin = ,v :

The KCL at the output node is similar to (1.8). Thus,

(1.10)

vout = g R : vin m L

Interestingly, this type of ampliﬁer does not invert the signal.

(1.11)

Exercise

Repeat the above example if r

! infty.

Example 1.7

A third ampliﬁer topology is shown in Fig. 1.22. Determine the voltage gain.

rπ vπ i 1 g vπ m

v in

RE

v out

Figure 1.22

We ﬁrst write a KVL around the loop consisting of vin , r , and RE :

Solution

vin = v + vout : v + g v = vout : r m RE

(1.12)

That is, v = vin , vout . Next, noting that the currents v =r and gm v ﬂow into the output node, and the current vout =RE ﬂows out of it, we write a KCL: (1.13)

Substituting vin , vout for v gives

vin r + gm = vout R1 + r1 + gm ; E

and hence

1

(1.14)

1 vout = r + gm 1 1 vin RE + r + gm

(1.15)

1. 2006] June 30.3 Basic Concepts 15 r E = r 1 + gmg rRR : + 1 + m E (1. The equivalent impedance. more importantly. 2007 at 13:42 15 (1) Sec. vThev . Would such an ampliﬁer prove useful at all? In fact. Thevenin’s theorem states that a (linear) one-port network can be replaced with an equivalent circuit consisting of one voltage source in series with one impedance. 1.8 Suppose the input voltage source and the ampliﬁer shown in Fig. voltage. provide additional insight into the operation of a circuit.24(a)]. 1. Thevenin and Norton Equivalents While Kirchoff’s laws can always be utilized to solve any circuit.23 (a) Thevenin equivalent circuit.16) Note that the voltage gain always remains below unity.20 are placed in a box and only the output port is of interest [Fig. is obtained by leaving the port open and computing the voltage created by the actual circuit at this port. Exercise Repeat the above example if r ! infty. 1. Illustrated in Fig. The impedance is computed by applying a voltage source across the port and obtaining the resulting current. the term “port” refers to any two nodes whose voltage difference is of interest. Example 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We also call ZThev the impedance “seen” when “looking” into the output port [Fig. is determined by setting all independent voltage and current sources in the circuit to zero and calculating the impedance between the two nodes.cls v. (b) computation of equivalent impedance.23(b)]. A few examples illustrate these principles. Solution We must compute the open-circuit output voltage and the impedance seen when looking into the . this topology exhibits some important properties that make it a versatile building block. The above three examples relate to three ampliﬁer topologies that are studied extensively in Chapter 5. Determine the Thevenin equivalent of the circuit. ZThev .23(a). 1. the Thevenin and Norton theorems can both simplify the algebra and. The equivalent Vj i X v Port j ZT v he X ZT v he v Th ev (a) (b) Figure 1.

and write sp vout = . Also.24(b). since both terminals of r are tied to ground. Determine the Solution Shown in Fig. vX . across the output port. 1. With the Thevenin equivalent of a circuit available.25(a) is the overall circuit arrangement that must solve.gmRL vin R R+ R sp L = . 1.17) (1.24(a) and Eq. we set vin to zero. As shown in Fig.24(c).9): vThev = vout = . iX . 1 Introduction to Microelectronics iX RL vX − g m R Lv in v in rπ vπ i 1 g vπ m R L v out v in = 0 r π vπ i 1 g vπ m RL (a) (b) (c) Figure 1. apply a voltage source.18) To calculate ZThev . 1.” Example 1.24 output port. Exercise Repeat the above example if r ! 1. In this case. note that the current source gm v remains in the circuit because it depends on the voltage across r . Rsp .25(b)]. 1. we greatly simplify the circuit [Fig. The Thevenin voltage is obtained from Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The circuit thus reduces to RL and v iX = RX : L That is. whose value is not known a priori. Replacing the section in the dashed box with its Thevenin equivalent from Fig.24(b)? We must again eliminate v . v = 0 and gm v = 0. we can readily analyze its behavior in the presence of a subsequent stage or “load.22) . and determine the current drawn from the voltage source.21) (1.20) Figure 1.gm RLvin : (1.19) RThev = RL : (1. 1. Fortunately.9 The ampliﬁer of Fig.cls v. How do we solve the circuit of Fig. we call RThev (= RL ) the “output impedance” of the circuit. setting vin to zero means replacing it with a short circuit. (1. (1.gmvin RL jjRsp : (1. 1. 2007 at 13:42 16 (1) 16 Chap.24(c) depicts the Thevenin equivalent of the input voltage source and the ampliﬁer.20 must drive a speaker having an impedance of voltage delivered to the speaker. 2006] June 30. 1.

Solution The open-circuit output voltage is simply obtained from (1. Consequently.23) + + m L To calculate the Thevenin impedance. we recognize that the two terminals of r rπ vπ i 1 g vπ m iX RL v X vX RL Figure 1. and iX ﬂow into this node and the current vX =RL ﬂows out of it.26 are tied to those of vX and hence v = . r m X RL (1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.vX : v + g v + i = vX .16): + r L vThev = r 1 1 gmg rRR vin : (1.10 Determine the Thevenin equivalent of the circuit shown in Fig. 2007 at 13:42 17 (1) Sec. Example 1.25 (a) (b) Exercise Repeat the above example if r ! 1.3 Basic Concepts RL 17 v in rπ vπ i 1 g vπ R L m v out R sp − g m R Lv in v out R sp Figure 1. 1.26.22 if the output port is of interest.25) or . gm v . To eliminate v .cls v.24) We now write a KCL at the output node. we set vin to zero and apply a voltage source across the output port as depicted in Fig. 1. 1. (1. 2006] June 30. The currents v =r .

vX + iX = RL : (1.26) .1 vX r + gm .

RThev = vX i X (1.20 if the output port is of interest.28 across RL is now forced to zero. The equivalent current. shorting the port of interest and computing the current that ﬂows through it. 1. this resistor carries no current. 2006] June 30. A KCL at the output node thus yields iNor = . 1. ZNor = ZThev . 1. iNor .27) (1.29) . ZNor .28) = r + 1r+RL r R : gm L Exercise What happens if RL = 1? Norton’s theorem states that a (linear) one-port network can be represented by one current source in parallel with one impedance (Fig. The equivalent impedance. Since the voltage i Nor v in rπ vπ i 1 g vπ R L m (a) Short Circuit Solution g v m in RL (b) Figure 1. 2007 at 13:42 18 (1) 18 Chap. Example 1.28(a). As depicted in Fig. Of course. is determined by setting all independent voltage and current sources in the circuit to zero and calculating the impedance seen at the port.cls v. we short the output port and seek the value of iNor .27 Norton’s theorem.11 Determine the Norton equivalent of the circuit shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1 Introduction to Microelectronics That is.gmv (1. is obtained by Port j Z No r No r i Figure 1.27).

1. .gm RL vin .29(b).30) Also. Thus. Exercise Repeat the above example if a resistor of value R1 is added between the top terminal of vin and the output node. 2007 at 13:42 19 (1) Sec. 1. 1.28(b). we observe that the ﬂow of iNor through RL produces a voltage of .cls v.29 Also. yielding iNor = v + gmv : r (1.8.gmvin : (1. 1.29(a). we note that RL carries no current. from Example 1. The Norton equivalent therefore emerges as shown in Fig. v in rπ vπ i 1 g vπ m ( 1 + g m ) vin rπ Solution r π RL r π + (1+ g mr π ) R L RL i Nor (a) (b) Figure 1.22 if the output port is interest. the same as the output voltage of the original circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4 Chapter Summary 19 = . Example 1.31) iNor = r + gm vin : With the aid of Fig. 1. vin = v (why?). 2006] June 30. To check the validity of this model. RNor (= RThev = RL . Shorting the output port as illustrated in Fig.12 Determine the Norton equivalent of the circuit shown in Fig.

1 (1. we construct the Norton equivalent depicted in Exercise What happens if r = infty? 1.32) RThev found in Example 1.10. . etc. digital cameras. laptop computers.4 Chapter Summary Electronic functions appear in many devices. including cellphones.

Thevenin’s theorem reduces a one-port circuit to a voltage source in series with an impedance.” analog circuits ﬁnd wide application in most of today’s electronic systems. . Analog circuits process signals that can assume various values at any time. Norton’s theorem allows simplifying a one-port circuit to a current source in parallel with an impedance. 2006] June 30. Kirchoff’s voltage law (KVL) states that the sum of all voltages around any loop is zero. The voltage gain of an ampliﬁer is deﬁned as vout =vin and sometimes expressed in decibels (dB) as 20 logvout =vin . digital circuits deal with signals having only two levels and switching between these values at known points in time. Kirchoff’s current law (KCL) states that the sum of all currents ﬂowing into any node is zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1 Introduction to Microelectronics Ampliﬁcation is an essential operation in many analog and digital systems. Despite the “digital revolution. By contrast. Similarly.cls v. 2007 at 13:42 20 (1) 20 Chap.

). This chapter accomplishes this task. just as we need to eat our broccoli before having desert.” which also serves as diode. we deal with the the “pn junction. Next.1 1 As design managers often say. the ﬂow of current) in them. we begin with the concept of semiconductors and study the movement of charge (i. Our treatment of device physics must contain enough depth to provide adequate understanding. but must also be sufﬁciently brief to allow quick entry into circuits.. In this chapter.. a good understanding of the internal operation of devices is necessary. and formulate its behavior.e. so that a circuit using such a device can be analyzed easily. The outline is shown below. voltage or current sources. etc. Our ultimate goal is to represent the device by a circuit model (consisting of resistors. then you lose to your competitor. The electronics industry continues to place greater demands on circuits. we do face a dilemma. Our ultimate objective in this chapter is to study a fundamentally-important and versatile device called the “diode. we should emphasize at the outset that a good understanding of devices is essential to our work.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. Thus.g. one cannot design a high-performance automobile without a detailed knowledge of the engine and its limitations. “If you do not push the devices and circuits to their limit but your competitor does. Semiconductors Charge Carriers Doping Transport of Carriers PN Junction Structure Reverse and Forward Bias Conditions I/V Characteristics Circuit Models It is important to note that the task of developing accurate models proves critical for all microelectronic devices.” 21 . While this book deals with the analysis and design of circuits. 2007 at 13:42 21 (1) 2 Basic Physics of Semiconductors Microelectronic circuits are based on complex semiconductor structures that have been under active research for the past six decades. The situation is similar to many other engineering problems.” However. calling for aggressive designs that push semiconductor devices to their limits.cls v. capacitors. we must develop a basic understanding of “semiconductor” materials and their current conduction mechanisms before attacking diodes. Nonetheless. e.

On the other hand. (c) we determine current ﬂow mechanisms.1 Outline of this section. 2. (b) we examine means of modifying the density of charge carriers to create desired current ﬂow properties. and how complete this shell is. and chloride has seven valence electrons. These steps naturally lead to the computation of the current/voltage (I/V) characteristics of actual diodes in the next section. This outline represents a logical thought process: (a) we identify charge carriers in solids and formulate their role in current ﬂow. 2007 at 13:42 22 (1) 22 Chap. ready to relinquish it. ing a number of elements with three to ﬁve valence electrons.1 Semiconductor Materials and Their Properties Since this section introduces a multitude of concepts. possibly displaying interesting chemical and physical properties. called “valence” electrons.2 Section of the periodic table. neon exhibits a complete outermost shell (with eight electrons) and hence no tendency for chemical reactions. 2. The above principles suggest that atoms having approximately four valence electrons fall somewhere between inert gases and highly volatile elements. eager to receive one more.1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. it is useful to bear a general outline in mind: Charge Carriers in Solids Crystal Structure Bandgap Energy Holes Modification of Carrier Densities Intrinsic Semiconductors Extrinsic Semiconductors Doping Transport of Carriers Diffusion Drift Figure 2. 2006] June 30.” The atom’s chemical activity is determined by the electrons in the outermost shell.2 is a section of the periodic table containIII IV V Boron (B) Aluminum (Al) Galium (Ga) Carbon (C) Silicon (Si) Germanium (Ge) Phosphorous (P) Arsenic (As) Figure 2. sodium has only one valence electron. silicon merits a detailed analysis. For example. As the most popular material in microelectronics. Shown in Fig.1 Charge Carriers in Solids Recall from basic chemistry that the electrons in an atom orbit the nucleus in different “shells.2 2 Silicon is obtained from sand after a great deal of processing. Both elements are therefore highly reactive. . 2 Basic Physics of Semiconductors 2.cls v.

(c) free electron released by thermal energy. at higher temperatures. (b) covalent bonds between atoms. Holes When freed from a covalent bond. 2. one hole has moved from left to right. However. before t = t1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2.3 (a) Silicon atom. 2006] June 30. First.4 Movement of electron through crystal. each atom shares one valence electron with its neighbors. it is the free electron that actually moves in the crystal. In other words. Looking at the three “snapshots. 2.3(c)] until they fall into another incomplete bond. Bandgap Energy We must now answer two important questions. Why do we bother with the concept of the hole? After all. we say an “electron-hole pair” is generated when an electron is freed. 2. the valence electrons are conﬁned to their respective covalent bonds. an electron leaves bond number 3 and falls into the hole in bond number 2. or. This view of current ﬂow by holes proves extremely useful in the analysis of semiconductor devices. 2. the silicon crystal behaves as an insulator for T ! 0K . Called a “hole.4. 2007 at 13:42 23 (1) Sec. If processed properly. at t = t3 .3(b)].” we can say one electron has traveled from right to left.3(a)]. refusing to move freely. requiring another four to complete its outermost shell. We will hereafter use the term “electrons” to refer to free electrons. As a result. a minimum energy is required to . con material can form a “crystal” wherein each atom is surrounded by exactly four others [Fig. Thus. the siliCovalent Bond Si Si Si Si Si Si Si Si Si Si Si Si Si e Si Si Free Electron (a) (b) (c) Figure 2.cls v. occasionally breaking away from the bonds and acting as free charge carriers [Fig. an electron breaks away from bond number 2 and recombines with the hole in bond number 1.3(b) plays a crucial role in semiconductor devices. But. consider the time evolution illustrated in Fig. thereby completing its own shell and those of the neighbors. alternatively. in fact. an electron leaves a “void” behind because the bond is now incomplete. electrons gain thermal energy. To appreciate the usefulness of holes. 2. does it carry current in response to a voltage? At temperatures near absolute zero. Similarly. Suppose covalent bond number 1 contains a hole after losing an electron some time t = t1 1 Si Si Hole Si Si Si Si Si Si Si Si Si 2 Si t = t2 Si Si Si Si Si t = t3 Si 3 Si Si Si Figure 2.1 Semiconductor Materials and Their Properties 23 Covalent Bonds A silicon atom residing in isolation contains four valence electrons [Fig. and an “electron-hole recombination” occurs when an electron “falls” into a hole. The uniform crystal depicted in Fig. does any thermal energy create free electrons (and holes) in silicon? No. At t = t2 .” such a void can readily absorb a free electron if one becomes available. The “bond” thus formed between atoms is called a “covalent bond” to emphasize the sharing of valence electrons.

materials having a larger Eg exhibit a smaller ni . we have ni T = 300 K = 1:08 1010 electrons=cm3 ni T = 600 K = 1:54 1015 electrons=cm3 : (2. 2006] June 30. Determine the density of electrons in silicon at T Since Eg Example 2. we recognize that only one in 5 1012 atoms beneﬁt from a free electron at room temperature. n= ni .3). i. the number of electrons per unit volume. do not despair! We next introduce a means of making silicon more useful.Eg =2kT . The exponential dependence of ni upon Eg reveals the effect of the bandgap energy on the conductivity of the material. and write for silicon: E ni = 5:2 1015T 3=2 exp .. Fortunately. have a small bandgap. 2. this minimum is a fundamental property of the material. typically ranging from 1 eV to 1.1.1) where k = 1:38 10.5 eV.g.” suffering from a very high resistance. but a higher T yields more electrons.5 eV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the electron density. on the other hand. a hole is left behind. To simplify future derivations.3) Since for each free electron. noting that silicon has 5 1022 atoms=cm3 . silicon still seems a very poor conductor.kTg electrons=cm3 2 (2. 2 Basic Physics of Semiconductors dislodge an electron from a covalent bond.3 The second question relates to the conductivity of the material and is as follows. Also. ni . the density of holes is also given by (2. Conductors. as T ! 0. it is possible to modify the resistivity of silicon by replacing some of the atoms in the crystal with atoms of another material.2) and (2.. Finally.cls v. is equal 3 The unit eV (electron volt) represents the energy necessary to move one electron across a potential difference of 1 V. In other words. Eg = 2:5 eV for diamond. The derivation can be found in books on semiconductor physics. we consider the density (or concentration) of electrons. Eg = 1:12 eV. 2007 at 13:42 24 (1) 24 Chap. Exercise Repeat the above exercise for a material having a bandgap of 1. we postulate that the number of electrons depends on both Eg and T : a greater Eg translates to fewer electrons. As expected. Note that 1 eV= 1:6 10. [1].e.2) (2. = 1:12 eV= 1:792 10. Called the “bandgap energy” and denoted by Eg . The ni values obtained in the above example may appear quite high.19 J. For silicon. for example. semiconductors exhibit a moderate Eg . . But. so do T 3=2 and exp . How many free electrons are created at a given temperature? From our observations thus far.2 Modiﬁcation of Carrier Densities Intrinsic and Extrinsic Semiconductors The “pure” type of silicon studied thus far is an example of “intrinsic semiconductors. but. e.19 J. thereby bringing ni toward zero. Insulators display a high Eg .1 Solution = 300 K (room temperature) and T = 600 K.23 J/K is called the Boltzmann constant. In an intrinsic semiconductor.

” Providing many more free electrons than in the intrinsic state. four electrons with the neighboring silicon atoms. Thus. np = n2 : i (2. 2.cls v. i (2. np = n2 . The controlled addition of an “impurity” such as phosphorus to an intrinsic semiconductor is called “doping. then the density of free electrons rises by the same amount.” more speciﬁcally. Example 2.1) for silicon]. the doped silicon crystal is now called “extrinsic. how about these densities in a doped material? It can be proved that even in this case. 2.g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.” This electron is free to move.5 Loosely-attached electon with phosphorus doping. if N phosphorus atoms are uniformly introduced in each cubic centimeter of a silicon crystal.4) We return to this equation later. How can atoms and increase n? np remain constant while we add more donor Equation (2.1 Semiconductor Materials and Their Properties 25 to the hole density. serving as a charge carrier.” and phosphorus itself a “dopant. Solution Exercise Why can we not say that n + p should remain constant? Example 2. Recall from Fig. the electron and hole densities in an intrinsic semiconductor are equal. The quantity ni represents the densities in the intrinsic semiconductor (hence the subscript i) and is therefore independent of the doping level [e. leaving the ﬁfth electron “unattached. 2006] June 30. p. (2.5) reveals that p must fall below its intrinsic level as more n-type dopants are added to the crystal. Eq.2 The above result seems quite strange. The doping density is .5) where n and p respectively denote the electron and hole densities in the extrinsic semiconductor. Thus. What happens if some P atoms are introduced in a silicon crystal? As illustrated in Fig. But. each P atom shares Si Si Si Si P e Si Si Figure 2.3 A piece of crystalline silicon is doped uniformly with phosphorus atoms. 2. 2007 at 13:42 25 (1) Sec..2 that phosphorus (P) contains ﬁve valence electrons. As remarked earlier. an “n-type” semiconductor to emphasize the abundance of free electrons. This occurs because many of the new electrons donated by the dopant “recombine” with the holes that were created in the intrinsic material.5.

If an intrinsic semiconductor is doped with a density of ND ( ni ) donor atoms per cubic centimeter.cls v.9) (2. the fourth bond contains a hole. For example.10) . ready to absorb Si Si Si B Si Si Si Figure 2.2 suggests that a boron (B) atom—with three valence electrons—can form only three complete covalent bonds in a silicon crystal (Fig. the resulting current predominantly consists of electrons.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Exercise At what doping level does the hole density drop by three orders of magnitude? This example justiﬁes the reason for calling electrons the “majority carriers” and holes the “minority carriers” in an n-type semiconductor. N boron atoms contribute N boron holes to the conduction of current in silicon.8) Note that the hole density has dropped below the intrinsic level by six orders of magnitude.6 Available hole with boron doping. providing holes as majority carriers. 2007 at 13:42 26 (1) 26 Chap. then we may obtain many incomplete covalent bonds. 2006] June 30. The addition of 1016 P atoms introduces the same number of free electrons per cubic centimeter. thereby exchanging the roles of electrons and holes.5) that (2. The boron atom is called an “acceptor” dopant. Let us formulate our results thus far. the table in Fig. Since this electron density exceeds that calculated in Example 2. 2. we can assume Solution n = 1016 electrons=cm3 It follows from (2. then the mobile charge densities are given by Majority Carriers : n ND Minority Carriers : p Ni : D n2 (2. In other words.7) (2. 2. Indeed. Thus. The structure in Fig. 2.6) p = ni n = 1:17 104 holes=cm3 2 (2. We may naturally wonder if it is possible to construct a “p-type” semiconductor. 2 Basic Physics of Semiconductors 1016 atoms/cm3 . if we can dope silicon with an atom that provides an insufﬁcient number of electrons.6 therefore exempliﬁes a p-type semiconductor.1 by six orders of magnitude.2) and (2.6). Determine the electron and hole densities in this material at the room temperature. a free electron. if a voltage is applied across this piece of silicon. As a result.

2.12) Since typical doping densities fall in the range of 1015 to 1018 atoms=cm3 . 2.11) (2. some early diodes and transistors were based on germanium (Ge) rather than silicon. i. the above expressions are quite accurate.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2. 2007 at 13:42 27 (1) Sec.7 Summary of charge carriers in silicon. 2006] June 30. Intrinsic Semiconductor Si Si Covalent Bond Si Valence Electron Extrinsic Semiconductor Silicon Crystal Silicon Crystal N D Donors/cm Si Si Si n−Type Dopant (Donor) Si P e Si 3 N A Acceptors/cm Si Si B Si Free Majority Carrier Si 3 Si Si Si p−Type Dopant (Acceptor) Free Majority Carrier Figure 2.1. illustrating the types of charge carriers and their densities in semiconductors.e. Example 2.7 summarizes the concepts introduced in this section.2 as semiconductors and dopants? Solution Yes.1 Semiconductor Materials and Their Properties 27 Similarly. we are ready to examine the movement of charge in semiconductors.4 Is it possible to use other elements of Fig. the mechanisms leading to the ﬂow of current. arsenic (As) is another common dopant. . for example. Exercise Can carbon be used for this purpose? Figure 2.3 Transport of Carriers Having studied charge carriers and the concept of doping.. Also. for a density of NA ( ni ) acceptor atoms per cubic centimeter: Majority Carriers : p NA Minority Carriers : n Ni : A n2 (2.

since electrons move in a direction opposite to the electric ﬁeld. 2 Basic Physics of Semiconductors Drift We know from basic physics and Ohm’s law that a material can conduct current in response to a potential difference and hence an electric ﬁeld. ! (2. 2007 at 13:42 28 (1) 28 Chap.8. we must express the velocity vector as ! ve = . the charge carriers are E Figure 2.cls v. In other words. where L is the length. accelerated by the ﬁeld and accidentally collide with the atoms in the crystal. Thus. 2006] June 30. Of course. For example in silicon. eventually reaching the other end and ﬂowing into the battery. forcing some to ﬂow from one end to the other. v .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As shown in Fig.5 ! (2.16) A uniform piece of n-type of silicon that is 1 m long senses a voltage of 1 V. E .”5 Semiconductors behave in a similar manner. E = 10. 000 V/cm and hence v = n E = 1:35 107 cm/s. to distance: Vab 4 Recall that the potential (voltage) difference. and that of holes. if electrons ﬂow from point A to point B . Solution 5 The convention for direction of current assumes ﬂow of positive charge from a positive voltage to a negative voltage. (2. electrons take 1 m=1:35 107 cm=s = 7:4 ps to cross the 1-m length. open) experiences. on the other hand. and hence (2.8 Drift in a semiconductor. p = 480 cm2 =V s. is equal to the negative integral of the electric ﬁeld. the current is considered to have a direction from B to A. leading to a constant velocity for the carriers. ba Edx. the mobility of electrons.13) v = E.14) where is called the “mobility” and usually expressed in cm2 =V s. The acceleration due to the ﬁeld and the collision with the crystal counteract. to be proportional to the electric ﬁeld strength. with respect .6 We expect the velocity. V . Determine the velocity of the electrons. 2.n E : For holes. R = .4 The ﬁeld accelerates the charge carriers in the material. we have E = V=L. Movement of charge carriers due to an electric ﬁeld is called “drift. n = 1350 cm2 =V s. Since the material is uniform. Thus. 6 This phenomenon is analogous to the “terminal velocity” that a sky diver with a parachute (hopefully.15) ! vh = p E : Example 2. E : v E.

2. and the negative sign accounts for the fact that electrons carry negative charge.9 Current ﬂow in terms of charge density. 2007 at 13:42 29 (1) Sec. (2. and since W h is the cross section area of the bar. n q denotes the charge density in coulombs. (2. the current is equal to the total charge enclosed in v meters of the bar’s length. we have: I = . Eq.19 C. v = . and is expressed in A=cm2 . We may loosely say. the current passing through a unit cross section area.18) where Jn denotes the “current density. Let us now reduce Eq.v W h n q. v m/s.e.1 Semiconductor Materials and Their Properties 29 Exercise What happens if the mobility is halved? With the velocity of carriers known. Since the bar has a width of W . 2. Assuming the electrons move with a velocity of v meters W t = t1 L h t = t1 + 1 s x1 V1 x x1 V1 x Figure 2. In the presence of both electrons and holes. (2.18) is modiﬁed to Jtot = n E n q + p E p q = qn n + p pE: (2. In other words. “the current is equal to the charge velocity times the charge density.cls v.” i. Equivalently. and negative or positive signs are taken into account properly.. 2006] June 30.17) to a more convenient form. we write Jn = n E n q.17) where v W h represents the volume.” with the understanding that “current” in fact refers to current density. how is the current calculated? We ﬁrst note that an electron carries a negative charge equal to q = 1:6 10. .n E . we note that the total charge in v meters passes the cross section in 1 second. Since for electrons.19) (2. Now suppose a voltage V1 is applied across a uniform semiconductor bar having a free electron density of n (Fig. considering a cross section of the bar at x = x1 and taking two “snapshots” at t = t1 and t = t1 + 1 second.9).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. a hole carries a positive charge of the same value. (2.20) This equation gives the drift current density in response to an electric ﬁeld E in a semiconductor having uniform electron and hole densities.

2.24) For example. it is desired to obtain equal electron and hole drift currents. vsat (Fig. v varies “sublinearly” at high electric ﬁelds.23) (2. yielding (2. Called “velocity saturation.21) n = p : p n We also recall that np = n2 . This conﬁrms our earlier notion of majority carriers in 3 semiconductors having typical doping levels of 1015 -1018 atoms=cm . Thus. How should the carrier densities be chosen? Solution We must impose n n = p p. . if the electric ﬁeld approaches sufﬁciently high levels. n =p = 1350=480 = 2:81.26) Since p and n are of the same order as ni . limiting the performance of circuits.25) (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and hence (2. In reality. i (2. Exercise How should the carrier densities be chosen so that the electron drift current is twice the hole drift current? Velocity Saturation We have thus far assumed that the mobility of carriers in semiconductors is independent of the electric ﬁeld and the velocity rises linearly with E according to v = E .10). In order to represent velocity saturation.22) r p = n ni p r p n = ni : n p = 1:68ni n = 0:596ni: (2.” this effect manifests itself in some modern transistors. 2007 at 13:42 30 (1) 30 Chap. equal electron and hole drift currents can occur for only a very lightly doped material. 2 Basic Physics of Semiconductors Example 2. As a result. .6 In an experiment. we must modify v = E accordingly. as a ﬁeld-dependent parameter. v no longer follows E linearly. This is because the carriers collide with the lattice so frequently and the time between the collisions is so short that they cannot accelerate much.cls v. A simple approach is to view the slope. eventually reaching a saturated level. in silicon. 2006] June 30. The expression for must This section can be skipped in a ﬁrst reading.

2006] June 30.cls v..34) (2. If the low-ﬁeld mobility is equal to 1350 cm2 =V s and the saturation velocity of the carriers 107 cm/s. In other words. where 0 is the “low-ﬁeld” mobility and b a proportionality factor. but approach a constant value for small E . = 1 +0bE . Solution We have E=V L It follows that (2. (2. Thus. Also.29) and hence b = 0 =vsat . 2007 at 13:42 31 (1) Sec.e.28) v = 1 + 0bE E: Since for E ! 1. 2. (2.33) (2.32) = 50 kV=cm: = 0 1 + 0 E vsat 0 = 7:75 = 174 cm2 =V s: (2.2 m long sustains a voltage of 1 V.30) A uniform piece of semiconductor 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.31) (2. v ! vsat . i.35) . calculate the maximum allowable voltage such that the effective mobility is only 10% lower than 0 . we have vsat = b0 . v= Example 2. We may consider “effective” mobility at an electric ﬁeld E .27) as the (2. determine the effective mobility.1 Semiconductor Materials and Their Properties Velocity 31 vsat µ2 µ1 E Figure 2.10 Velocity saturation. therefore gradually fall toward zero as E rises.7 0 E: 1 + 0 E vsat (2.

then 0:90 = and hence 0 .11 Diffusion in a semiconductor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Even in the absence of an electric ﬁeld.12.cls v.38) = 823 V=cm: 10. a nonuniform charge proﬁle is created along the x-axis. Suppose a drop of ink falls into a glass of water.4 cm = 16:5 mV. another mechanism can lead to current ﬂow. most importantly. Introducing a high local concentration of ink molecules. This mechanism is called “diffusion. 2. The reader may raise several questions at this point. thereby carrying an electric current so long as the nonuniformity is sustained.” that is. What serves as the source of carriers in Fig. Example 2. Exercise At what voltage does the mobility fall by 20%? Diffusion In addition to drift. Semiconductor Material Injection of Carriers Nonuniform Concentration Figure 2. patience is a virtue and we will answer these questions in the next section.37) (2. Figure 2. 2 Basic Physics of Semiconductors If the mobility must remain within 10% of its low-ﬁeld value. Explain how the current ﬂows. 2007 at 13:42 32 (1) 32 Chap. A source on the left continues to inject charge carriers into the semiconductor. Diffusion is therefore distinctly different from drift.2 m experiences such a ﬁeld if it sustains a voltage of 823 V=cm 0:2 This example suggests that modern (submicron) devices incur substantial velocity saturation because they operate with voltages much greater than 16. the ink molecules tend to ﬂow from a region of high concentration to regions of low concentration. the carriers move toward regions of low concentration. .5 mV.36) sat E = 1 v 9 (2. why should we care?! Well. A device of length 0. 1 + 0 E vsat 0 (2. and the carriers continue to “roll down” the proﬁle. the drop begins to “diffuse.8 A source injects charge carriers into a semiconductor bar as shown in Fig. 2006] June 30.11? Where do the charge carriers go after they roll down to the end of the proﬁle at the far right? And.11 conceptually illustrates the process of diffusion.” A similar phenomenon occurs if charge carriers are “dropped” (injected) into a semiconductor so as to create a nonuniform density. 2.

2007 at 13:42 33 (1) Sec.cls v. two symmetric proﬁles may develop in both positive and negative directions along the x-axis.qDp dx : (2.39) where n denotes the carrier concentration at a given point along the x-axis.40) I = AqDn dn . assuming current ﬂow only in the x direction. (2.42) dp Jp = .1 Semiconductor Materials and Their Properties Injection of Carriers 33 0 x Figure 2. As with the convention used for the drift current. We call dn=dx the concentration “gradient” with respect to x.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.41) where Dn is a proportionality factor called the “diffusion constant” and expressed in cm2 =s. 2. If each carrier has a charge equal to q . For example. obtaining the current density as Jn = qDn dn : dx Similarly.12 Injection of carriers into a semiconductor. Dn = 34 cm2 =s (for electrons). we normalize the diffusion current to the cross section area. Exercise Is KCL still satisﬁed at the point of injection? Our qualitative study of diffusion suggests that the more nonuniform the concentration. and Dp = 12 cm2 =s (for holes). dx (2. in intrinsic silicon. More speciﬁcally.43) . Eq. 2006] June 30. the larger the current.39) can be written as I Aq dn : dx Thus. leading to current ﬂow from the source toward the two ends of the bar. dx (2. and the semiconductor has a cross section area of A. a gradient in hole concentration yields: (2. Solution In this case. (2. we can write: I dn .

2 Basic Physics of Semiconductors With both electron and hole concentration gradients present. the total current density is given by dp Jtot = q Dn dn . 2006] June 30.cls v. 2007 at 13:42 34 (1) 34 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.9 . Dp dx : dx Example 2.

14 Current resulting from an exponential diffusion proﬁle. (2.10 Repeat the above example but assume an exponential gradient (Fig. 2.. nx = N exp . N Injection 0 L x Figure 2.47) . 2.e.qDn N : L The current is constant along the x-axis. i.11 again. Example 2.x . Solution We have Jn = qDn dn dx (2. While obvious.13). Exercise Repeat the above example for holes. this observation prepares us for the next example.14): N Injection 0 L x Figure 2.45) (2. Suppose the electron concentration is equal to N at x = 0 and falls linearly to zero at x = L (Fig. L d (2.46) = . all of the electrons entering the material at x = 0 successfully reach the point at x = L. 2.44) Consider the scenario depicted in Fig. Determine the diffusion current.13 Current resulting from a linear diffusion proﬁle.

Drift Current Diffusion Current E Jn = q n µn E Jp = q p µp E dn dx dp Jp = − q Dp dx Jn = q Dn Figure 2. . Exercise At what value of x does the current density drop to 1% its maximum value? Einstein Relation Our study of drift and diffusion has introduced a factor for each: n (or p ) and Dn (or Dp ). What happens to these electrons? Does this example violate the law of conservation of charge? These are important questions and will be answered in the next section.. some electrons vanish while traveling from x = 0 to the right.50) Called the “Einstein Relation.49) Ld Ld Interestingly.7 Solution We have Jn = qDn dn (2. Note that kT=q 26 mV at T = 300 K. (1) The device ﬁnds application in many electronic systems. That is.15 summarizes the charge transport mechanisms studied in this section.cls v. (2) The pn junction is among the simplest semiconductor devices.48) dx = ..2 PN Junction 35 where Ld is a constant.15 Summary of drift and diffusion mechanisms.” this result is proved in semiconductor physics texts. the current is not constant along the x-axis. e.g.2 We begin our study of semiconductor devices with the pn junction for three reasons. It can be proved that and D are related as: D = kT : q (2.qDn N exp .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thus providing a 7 The factor PN Junction Ld is necessary to convert the exponent to a dimensionless quantity. Figure 2. 2007 at 13:42 35 (1) Sec. [1]. 2006] June 30. 2. e.g.x : (2. in adapters that charge the batteries of cellphones. 2. respectively.

a large excess of electrons. (2.e. indicating that our objective is to develop circuit models that can be used in analysis and design.2. Since we must deal with both electron and hole concentrations on each side of the junction.11) and (2. We say the junction is in “equilibrium. Example 2. PN Junction in Equilibrium Let us ﬁrst study the pn junction with no external connections. The sharp concentration gradient for both electrons and holes across the junction leads to two large diffusion currents: electrons ﬂow from the n side to the p side. (3) The pn junction also serves as part of transistors. recognizing that one side contains a large excess of holes and the other. In this section. this condition provides insights that prove useful in understanding the operation under nonequilibrium as well.cls v.3 and ND Determine the hole and electron concentrations on the two sides.18. and holes ﬂow in the opposite direction. the terminals are open and 2. We also use the term “diode” to refer to pn junctions. A pn junction employs the following doping levels: NA = 1016 cm.16 PN junction. we introduce the notations shown in Fig. 2007 at 13:42 36 (1) 36 Chap.16 and called a “pn junction. we express the concentrations of holes and electrons on the p side Solution . Depicted in Fig. i.1 no voltage is applied across the device. 2006] June 30. The p and n sides are called the “anode” and n p Cathode Anode Si Si P e Si B Si (a) Si Si Si Si (b) Figure 2. and an electric ﬁeld or a concentration gradient leads to the movement of these charge carriers. We have thus far seen that doping produces free electrons or holes in a semiconductor. 2. We begin by examining the interface between the n and p sections. the ”cathode. The following outline shows our thought process. From Eqs. 2.12).17 Outline of concepts to be studied.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. An interesting situation arises if we introduce n-type and p-type dopants into two adjacent sections of a piece of semiconductor.” respectively.” While seemingly of no practical value. 2 Basic Physics of Semiconductors good entry point into the study of the operation of such complex structures as transistors.11 = 51015 cm.3 ..” this structure plays a fundamental role in many semiconductor devices. we study the properties and I/V characteristics of pn junctions. PN Junction in Equilibrium Depletion Region Built−in Potential PN Junction Under Reverse Bias Junction Capacitance PN Junction Under Forward Bias I/V Characteristics Figure 2.

58) (2.51) (2. Exercise Repeat the above example if ND drops by a factor of four.3 5 = 2:3 104 cm.52) (2. This is because.59) (2.2 PN Junction n Majority Carriers 37 p pp np Majority Carriers nn pn Minority Carriers Minority Carriers Figure 2.57) (2. 2006] June 30. The diffusion currents transport a great deal of charge from each side to the other. nn : Concentration of electrons on n side pn : Concentration of holes on n side pp : Concentration of holes on p side np : Concentration of electrons on p side respectively as: pp NA np Ni n2 = 1016 cm.53) (2. the concentrations on the n side are given by nn ND pn N i n2 = 5 1015 cm. However. another effect dominates the situation and stops the diffusion currents well before this point is reached.60) 1010 cm. the device cannot carry a net current indeﬁnitely.54) (2. We must now answer an important question: what stops the diffusion currents? We may postulate that the currents stop after enough free carriers have moved across the junction so as to equalize the concentrations on the two sides.3 : D Note that the majority carrier concentration on each side is many orders of magnitude higher than the minority carrier concentration on either side. 2007 at 13:42 37 (1) Sec. but they must eventually decay to zero.56) (2.3 : A Similarly.18 .3 (2.3 2 = 1:08 1015 cm.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 1:1 104 cm.55) 1010 . . 2.cls v.3 (2. if the terminals are left open (equilibrium condition).3 2 = 1:081016 cmcm .

20. and the diffusion currents continue to expose more ions as time progresses. a positive ion is left behind.. i. 2.e. with the formation of the depletion region. .19 Evolution of charge concentrations in a pn junction.8 Interestingly. 2.” t=0 n − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − t = t1 p n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − t= p + + + + + + + + + + + + + + + + + + + + + + + + + + + + n − − − − − − + − − −+ − − − + − − − − − − + − − − − − − + + + + + + − − − − − − − − − − + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + p + + + + + + + + + + + + + + + + + + + + + + + + Free Free Electrons Holes Positive Negative Donor Acceptor Ions Ions Depletion Region Figure 2. the junction is suddenly formed at t = 0. i. In this illustration. the ﬁeld tends to force positive charge ﬂow from n − − − − − − − − − − − − − − − − − − − − − − − − E + + + + + + + + + + − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + Figure 2.cls v. we can say. the drift currents resulting from the electric ﬁeld exactly cancel the diffusion currents due to the gradients. At x = a. Sketch the electric ﬁeld as a function of x. 2. Beginning at x . in equilibrium. the negative and positive charge exactly cancel each other and E = 0.19.e. the depletion region has a width of b on the n side and a on the p side. an electric ﬁeld emerges as shown in Fig. Now recall from basic physics that a particle or object carrying a net (nonzero) charge creates an electric ﬁeld around it. left to right whereas the concentration gradients necessitate the ﬂow of holes from right to left (and electrons from left to right). the magnitude of E rises as x approaches zero. i. 2 Basic Physics of Semiconductors To understand this effect.21.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As we pass x = 0. Alternatively. the negative acceptor atoms begin to contribute negatively to the ﬁeld. 2007 at 13:42 38 (1) 38 Chap. At x . In the junction shown in Fig. we recognize that for every electron that departs from the n side. each positive donor ion contributes to the electric ﬁeld. 2006] June 30. we note that the absence of net charge yields E = 0.b. Example 2. We therefore surmise that the junction reaches equilibrium once the electric ﬁeld is strong enough to completely stop the diffusion currents.. the junction evolves with time as conceptually shown in Fig..12 Solution 8 The direction of the electric ﬁeld is determined by placing a small positive test charge in the region and watching how it moves: away from positive charge and toward negative charge. Thus. the immediate vicinity of the junction is depleted of free carriers and hence called the “depletion region.b.20 Electric ﬁeld in a pn junction. Consequently. E falls.e.

p + Idi . and each current term contains the proper polarity.p j = jIdi . This condition. we have (2.62) can be written as dp qp pE = qDp dx . 2007 at 13:42 39 (1) Sec.63).2 PN Junction n − − − − − − − − − − N − − D − − − − − − − − − − E + + + + + + + + + + 0 − − − − − − − − − − 39 p + + + + + + + + + + + NA + + + + + + + + + + a x −b E −b 0 a x Figure 2. however. allows an unrealistic phenomenon: if the number of the electrons ﬂowing from the n side to the p side is equal to that of the holes going from the p side to the n side.64) dp .63) Built-in Potential The existence of an electric ﬁeld within the depletion region suggests that the junction may exhibit a “built-in potential. From our observation regarding the drift and diffusion currents under equilibrium.n j = jIdi . and since (2. then each side of this equation is zero while electrons continue to accumulate on the p side and holes on the n side.p + Idrift.n j = jIdi .65) . using (2. we can compute this potential.61) where the subscripts p and n refer to holes and electrons.62) (2.p p dV = Dp dx : dx Dividing both sides by p and taking the integral.66) . 2.n j: (2.n j.cls v. (2.p j jIdrift. Since the electric ﬁeld E = .21 Electric ﬁeld proﬁle in a pn junction. Exercise Noting that potential voltage is negative integral of electric ﬁeld with respect to distance. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.” In fact.p Zx x1 2 dV = Dp Z pp dp pn p. (2. we may be tempted to write: jIdrift. We must therefore impose the equilibrium condition on each carrier: jIdrift.62) or (2. plot the potential as a function of x. we obtain (2.dV=dx. respectively.

from Einstein’s relation. Determine the Solution = 300 K = 1:08 1010 cm.68) Exercise Writing Eq.70) (2. p V x2 .71) 1016 4 16 V0 26 mV ln 2 1:08 1010 210 768 mV: Exercise By what factor should ND be changed to lower V0 by 20 mV? .3 . (2. (2. using (2.64) for electron drift and diffusion currents.50). (2.3 .22). Eq. Recall from Example 2. (2. we can replace Dp =p with kT=q : p jV0 j = kT ln pp : q n (2.3 and ND built-in potential at room temperature (T = 300 K). Thus. 2007 at 13:42 40 (1) 40 n nn pn Chap. respectively (Fig. 2. Finally. V x1 = .10) for pp and pn yields V0 = kT ln NA ND : q n2 i (2. and carrying out the integration. A silicon pn junction employs NA = 2 1016 cm. 2 p Basic Physics of Semiconductors pp np x1 x2 x Figure 2. Dp ln pp : p n where pn and pp are the hole concentrations at x1 and x2 .22 Carrier proﬁles in a pn junction.11) and (2. derive an equation for V0 in terms of nn and np . Thus.67) The right side represents the voltage difference developed across the depletion region and will be denoted by V0 . 2006] June 30.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.13 = 4 1016 cm. this equation plays a central role in many semiconductor devices.1 that ni T Example 2. Also.69) Expressing the built-in potential in terms of junction parameters.

sometimes called the “potential barrier. 2006] June 30. But.2 interesting and useful conditions.9 With no current conduction.3.74) Exercise How much does V0 change if NA or ND is increased by a factor of three? An interesting question may arise at this point.23. the depletion region be widened.72) (2. VR enhances the ﬁeld. the barrier rises even higher than that in equilibrium. Used as a noun or a verb. We note that in Fig. a higher electric ﬁeld can be sustained only if a larger amount of ﬁxed charge is provided. thus prohibiting the ﬂow of current. What happens to the diffusion and drift currents? Since the external voltage has strengthened the ﬁeld. However. How is that possible? We observe that the builtin potential is developed to oppose the ﬂow of diffusion currents (and is. VT ln NAn2ND n = VT ln 10 60 mV at T = 300 K: i i (2. We say the junction is under “reverse bias” to emphasize the connection of the positive voltage to the n terminal. in fact. 2. where the voltage source makes the n side more positive than the p side. This phenomenon is in contrast to the behavior of a uniform conducting material. which exhibits no tendency for diffusion and hence no need to create a built-in voltage. the junction carries a negligible current under reverse bias. 2.69) reveals that V0 is a weak function of the doping levels. the current is not exactly zero. E is directed from the n side to the p side.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 PN Junction 41 Equation (2.14 Solution We can write V0 = VT ln 10NA2 ND . the term “bias” indicates operation under some “desirable” conditions. a reverse-biased pn junction does not seem particularly useful. but it sustains a voltage. as VB increases. How much does V0 change if NA or ND is increased by one order of magnitude? Example 2.2.2. The junction carries no net current (because its terminals remain open).73) (2.”). Let us ﬁrst determine whether the external voltage enhances the built-in electric ﬁeld or opposes it.cls v. Let us begin by applying an external voltage across the device as shown in Fig. We wish to reexamine the results obtained in equilibrium for the case of reverse bias.23. an important observation will prove otherwise. 2007 at 13:42 41 (1) Sec. requiring that more acceptor and donor ions be exposed and. . ! Since under equilibrium. we can now study its behavior under more 2. 9 As explained in Section 2. We will study the concept of biasing extensively in this and following chapters. therefore. PN Junction Under Reverse Bias Having analyzed the pn junction in equilibrium. In other words. 2. more positive charge appears on the n side and more negative charge on the p side.

We also assume the charge in the depletion region equivalently resides on each plate. 2. revealing that the capacitance of the structure decreases as the two plates move away from each other. But. Returning to Fig. In essence.24(a)]. the device operates as a capacitor [Fig.23. we can view the conductive n and p sections as the two plates of the capacitor. the conceptual diagram of Fig.cls v. since any two parallel plates can form a capacitor. 2 Basic Physics of Semiconductors + + + + + + + + + + − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + p + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + − − − − − − − − − − − − − − − VR Figure 2.23 PN junction under reverse bias. 2. After all.24 Reduction of junction capacitance with reverse bias.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.75) . (2.24(b) for increasing values of VR . reverse-biased pn junctions exhibit a unique property that becomes useful in circuit design. V R2 + + + + + + + + + + + + + + + − − − − − − − − − − − − − − − n − − − − − − − − − − − − − − − − − − − − − − − − − − − − V R1 + + + + + + + + + + − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + + + + + n − − − − − − − − − − − − − − − − p + + + + + + + + + + + + + + + + + + + + − − − − − V R1 (a) V R2 (more negative than V R1 ) (b) Figure 2. so does the width of the depletion region. Thus. The reader may still not ﬁnd the device interesting.24(a) can be drawn as in Fig. 2. 2007 at 13:42 42 (1) 42 n − − − − − − − − − − − − − − − − − − − − − − − − n − − − − − − − − − − − − − − − − Chap. we recognize that. 2. The junction therefore displays a voltage-dependent capacitance. 2006] June 30. It can be proved that the capacitance of the junction per unit area is equal to Cj = r Cj0 1 . That is. the use of a pn junction for this purpose is not justiﬁed. VR V0 . as VR increases.

15 = 9 1015 cm.10 Plotted in Fig. (2.g.79) (2.14 F/cm.2 PN Junction 43 where Cj 0 denotes the capacitance corresponding to zero bias (VR = 0) and V0 is the built-in potential [Eq. 11. we deal with very small devices and may rewrite this result as Cj0 = 0:265 fF=m2 .3.19 C.83) 10 The dielectric constant of materials is usually written in the form r 0 . Cj indeed decreases as VR increases. where 1 fF (femtofarad) = 10. Example 2.) The value of Cj 0 is in turn given by r q NN Cj0 = si A D 2 NA + ND V0 1. we have r q NN 1 D Cj0 = si N A N V 2 A+ D 0 = 2:65 10.25 Junction capacitance under reverse bias.15 F.14 F/cm). . 2.7). and 0 the dielectric constant of vacuum (8:85 10. For VR (2. 2006] June 30. (2. 1 + VR V 0 (2. 2007 at 13:42 43 (1) Sec.81) = 1 V. Determine the Solution We ﬁrst obtain the built-in potential: V0 = VT ln NA ND n2 = 0:73 V: i Thus.69)].cls v.82) Cj = r Cj 0 = 0:172 fF=m2 : (2.8 F=cm2 : (2.77) (2. where r is the “relative” dielectric constant and a dimensionless factor (e. Cj 0 VR Figure 2. (This equation assumes VR is negative for reverse bias.80) In microelectronics. 2. for VR (2.25. A pn junction is doped with NA = 2 1016 cm.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.78) = 0 and q = 1:6 10.76) where si represents the dielectric constant of silicon and is equal to 11:7 8:85 10..3 and ND capacitance of the device with (a) VR = 0 and VR = 1 V.

88) (2. (2. 2006] June 30.16 A cellphone incorporates a 2-GHz oscillator whose frequency is deﬁned by the resonance frequency of an LC tank (Fig.jC!res .89) . as demonstrated by the following example.86) L = 11:9 nH: If VR goes to 2 V. a voltage-dependent capacitor leads to interesting circuit topologies. Thus. Assume the circuit operates at 2 GHz at a reverse voltage of 0 V. 2007 at 13:42 44 (1) 44 Chap.84) = 0. Cj = 0:265 fF/m2 . Compare the The variation of the capacitance with the applied voltage makes the device a “nonlinear” capacitor because it does not satisfy Q = CV . Solution Recall from basic circuit theory that the tank “resonates” if the impedances of the inductor and the capacitor are equal and opposite: jL!res = . If the tank capacitance is realized as the pn junction of Example 2. the resonance frequency is equal to fres = 21 p 1 : LC At VR (2.tot VR = 2 V = r Cj0 1 + 0:2 73 = 274 fF: 2000 m2 (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Oscillator C VR L Figure 2.26 Variable capacitor used to tune an oscillator.87) Cj. calculate the change in the oscillation frequency while the reverse voltage goes from 0 to 2 V.85) (2. Nonetheless. 2. and the junction area is 2000 m2 . 2 Basic Physics of Semiconductors Exercise Repeat the above example if the donor concentration on the results in the two cases.cls v.1 . N side is doubled. we obtain (2. yielding a total device capacitance of Cj.26).15.tot VR = 0 = 0:265 fF=m2 2000 m2 = 530 fF: Setting fres to 2 GHz. Example 2.

the external voltage. etc. 2007 at 13:42 45 (1) Sec.” We also wish to compute the resulting current in terms of the applied voltage and the junction parameters. In forward bias. If light of sufﬁcient energy is applied to a pn junction. microprocessors. (2. We say the pn junction operates as a “photodiode. As a result. tends to create a ﬁeld directed from the p side toward the n side—opposite to the built-in ﬁeld that was developed to stop the diffusion currents.2 GHz. ultimately arriving at a circuit model. Another interesting application of reverse-biased diodes is in digital cameras (Chapter 1). .2. we have fres VR = 2 V = 2:79 GHz: (2. assuming the junction area is still 2000 m2 but the inductor value is scaled to reach 5. We therefore surmise that VF in fact lowers the potential barrier by weakening the ﬁeld.27). From our study of the device in equilibrium and reverse bias. (2. electrons are dislodged from their covalent bonds and hence electron-hole pairs are created. we note that the potential barrier developed in the depletion region determines the device’s desire to conduct. Note that we have tacitly developed a circuit model for the device under this condition: a simple capacitance whose value is given by Eq.3 Our objective in this section is to show that the pn junction carries a current if the p side is raised to a more positive voltage than the n side (Fig.84). a reverse-biased pn junction carries a negligible current but exhibits a voltagedependent capacitance. 2006] June 30. Repeat the above example for this frequency. 2. 2.75). Exercise Some wireless systems operate at 5. n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − PN Junction Under Forward Bias p + + + + + + + + + + + + + + + + + + + + + + + + + + + + VF Figure 2.27 PN junction under forward bias. a current ﬂows through the diode that is proportional to the light intensity. With a reverse bias.cls v.90) An oscillator whose frequency can be varied by an external voltage (VR in this case) is called a “voltage-controlled oscillator” and used extensively in cellphones. personal computers.” 2.2 GHz. In summary. thus allowing greater diffusion currents. VF . This condition is called “forward bias.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 PN Junction 45 Using this value along with L = 11:9 nH in Eq. the electrons are attracted to the positive battery terminal and the holes to the negative battery terminal.

94) NA 0 exp VF . (b) the “thermal voltage” ( 26 mV at T = 300 K). for the electron concentration on the p side: np ND exp VF .f . pn.96) .28(a)] and VT n nn. leading to a proportional change in the diffusion currents.e (it can be proved that pp.e p pp.f to be much higher than pn. 1: V VT exp V 0 T 11 The width of the depletion region actually decreases in forward bias but we neglect this effect here.91) = kT=q is called VF (a) Figure 2.e pp. VF .e = V0 .11 We can express the change in the hole concentration on the n side as: pp.93) (2. 1: VT exp V VT (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As the junction goes from equilibrium to forward bias. In other words.28 Carrier proﬁles (a) in equilibrium and (b) under forward bias. the potential barrier is lowered by an amount equal to the applied voltage: pn. we begin with Eq.e np.f np. Figure 2. the minority carrier concentration on the p side rises rapidly with the forward bias voltage while the majority carrier concentration remains relatively constant. Since the exponential denominator drops considerably.e 0 . In forward bias.f pn. np and pn increase dramatically.e np.92) pn = pn.f pn. 2007 at 13:42 46 (1) 46 Chap.e pn.95) Similarly. we expect pn.e NA ). 2006] June 30. exp V0 exp V VT T (2.f pp. This statement applies to the n side as well.f (2.e = pp. 2.cls v.e nn.f = where the subscript f denotes forward bias. (2.68) for the built-in voltage and rewrite it as pn.f n p pp.28(b) illustrates the results of our analysis thus far. VF : exp V T (2. 2 Basic Physics of Semiconductors To derive the I/V characteristic in forward bias.f pp.f V0 . V exp V T where the subscript e emphasizes equilibrium conditions [Fig. (2.

Diffusion lengths are typically in the range of tens of micrometers.17 A: (2. = 1:6 10. This observation reminds us of Example 2. (2. what happens to the carriers and how can the current remain constant along the x-axis? Interestingly.. Ln = 20 m. it can be proved that [1] (2.19 C. An interesting question that arises here is: are the minority carrier concentrations constant along the x-axis? Depicted in Fig.” respectively. respectively. Determine IS for the junction of Example 2. Dn = 34 cm2 =s. implying that the charge carriers do not ﬂow deep into the p and n sides and hence no net current results! Thus. as the electrons enter the p side and roll down the gradient. 2.29(a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.99) In this equation.29(b) so that diffusion can occur. the exponential term in Eq.98) where IS is called the “reverse saturation current” and given by n IS = Aqn2 NDL + NDp : i A n D Lp (2. ni = 1:08 1010 electrons=cm3 [Eq. 1. the minority carrier concentrations must vary as shown in Fig. such a scenario would suggest that electrons continue to ﬂow from the n side to the p side.98) must assume very large values so as to yield a useful amount (e. they gradually recombine with the holes. (2. 1: V V VT VT exp V 0 exp V 0 T T Itot = IS exp VF . 2006] June 30. Exercise What junction area is necessary to raise IS to 10. 2. we have Solution IS = 1:77 10. 1 mA) for Itot . 2007 at 13:42 47 (1) Sec.cls v. . Using q Example 2. Itot NA exp VF . and Dp = 12 cm2 =s.15 A. i The increase in the minority carrier concentration suggests that the diffusion currents must rise by a proportional amount above their equilibrium value.13 at T and Lp = 30 m. and Ln and Lp are electron and hole “diffusion lengths.2 PN Junction 47 Note that Eq. i.10 and the question raised in conjunction with it: if the minority carrier concentration falls with x.97) Indeed. A similar situation exists for holes. but exhibit no tendency to go beyond x = x2 because of the lack of a gradient. Note that the ﬁrst and second terms in the parentheses correspond to the ﬂow of electrons and holes. (2.g. 1 + ND exp VF .e.17 = 300K if A = 100 m2 . V T (2. which are abundant in this region.. 2.100) Since IS is extremely small.69) indicates that expV0 =VT = NA ND =n2 .2)]. A is the cross section area of the device.

.f − x1 x2 VF (a) x1 x2 VF (b) x Figure 2.f nn. the two components add up to Itot .f pn. the current consists of mostly minority carriers.101) where ID and VD denote the diode current and voltage. i.101) also holds in reverse bias. prohibiting current ﬂow.cls v.f np. We hereafter assume expVD =VT 1 in the forward bias region. the applied voltage enhances the ﬁeld. on the other hand. 2006] June 30.f − − − np.f pp. Similarly. At each point along the x-axis.2. 2. As expected.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VD = 0 yields ID = 0. but towards the far contacts.30 Minority and majority carrier currents. If VD 0 and jVD j reaches several VT . It can be proved that Eq. Thus.e.102) . In forward bias. 1.29 (a) Constant and (b) variable majority carrier proﬁles ioutside the depletion region. respectively.IS : (2. for negative VD . We hereafter write the junction equation as: ID = IS exp VD .30). it is primarily comprised of majority carriers (Fig. 2. (2.f pn. 2007 at 13:42 48 (1) 48 Chap.f x + + + + pp.4 I/V Characteristics Let us summarize our thoughts thus far. V T (2. In reverse bias. raising the diffusion currents substantially. 2 Basic Physics of Semiconductors n Electron Flow − ++ − + −− + Hole Flow p n Electron Flow − ++ − + − Hole Flow p nn. then expVD =VT 1 and ID . the exponential term grows rapidly and ID IS expVD =VT . in the immediate vicinity of the depletion region. the holes entering the n side recombine with the electrons. (Why is this expected?) As VD becomes positive and exceeds several VT . n −− − − −− − − −− ++ + + + + ++ ++ p −− − − − − −− −− + ++ + ++ + + ++ x VF Figure 2. the external voltage opposes the built-in potential.

105) Exercise How many of these diodes must be placed in parallel to obtain a current of 100 A with a . Determine the forward bias current of the composite device for VD = 300 mV and 800 mV at T = 300 K.17. the total current is equal to ID. revealing why IS is called the “reverse saturation current.32 employs the doping levels described in Example 2.” Note that IS and hence the junction current are proportional to the device cross section area [Eq.31 I-V characteristic of a pn junction.cls v. 2. Thus. 2006] June 30. 2. From Example 2. For example.103) (2. 2007 at 13:42 49 (1) Sec. two identical devices placed in parallel (Fig. view the current under reverse bias as “leakage. We therefore Reverse Bias Forward Bias ID VD VT VD I S exp −IS Figure 2.tot VD = 800 mV = 82 A: (2.31 plots the overall I/V characteristic of the junction.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.13. for VD (2.18 Each junction in Fig.32) behave as a single junction with twice the IS . Example 2. (2. A n p 2A n n A VF VF p p Figure 2.tot VD = 300 mV = 2IS exp VD .32 Equivalence of parallel devices to a larger device.17 indicates that IS is typically very small.” Example 2. IS Solution = 1:77 10. 1 VT = 3:63 pA: Similarly. 2.104) = 800 mV: ID.17 A for each junction.99)].2 PN Junction 49 Figure 2.

Exercise By what factor does the current change if the voltages changes by 120 mV? Example 2.112) (2. Suppose we wish to increase the current by a factor of 10. 2007 at 13:42 50 (1) 50 Chap. meaning VD changes by 60 mV for a decade (tenfold) change in ID .113) .e.106) = VT ln ID + VT ln 10 IS = VD + VT ln 10: IS (2.111) (b) From the above example.110) (2. (b) Determine the change in VD if ID is maintained constant. 2006] June 30.. 2 Basic Physics of Semiconductors voltage of 750 mV. Assume ID IS expVD =VT . (a) Determine the change in ID if VD is maintained constant. We say the device exhibits a 60-mV/decade characteristic.20 The cross section area of a diode operating in the forward bias region is increased by a factor of 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. How much change in VD is required? Solution Let us ﬁrst express the diode voltage as a function of its current: We deﬁne I1 = 10ID and seek the corresponding voltage.108) (2. (2.cls v.19 A diode operates in the forward bias region with a typical current level [i. the new current is given by ID1 = 10IS exp VD VT = 10ID : I VD1 = VT ln 10D IS = VT ln ID . More generally. (a) Since IS Solution A. Example 2.109) Thus. VD1 : V = V ln 10ID D1 T VD = VT ln ID : I S (2. the diode voltage must rise by VT ln 10 60 mV (at T = 300 K) to accommodate a tenfold increase in the current.107) (2. an n-fold change in ID translates to a change of VT ln n in VD . ID IS expVD =VT ]. VT ln 10: IS (2.

21 . intuitive understanding of the operation of a complex circuit. We say the junction operates as an open circuit if VD VD. Consider the circuit of Fig. Neglecting the leakage current in reverse bias. if we indeed intend to use this simple approximation.on .16 A and (b) a constant-voltage model with VD.cls v. only the switch turns on and the battery always resides in series with the switch. 2007 at 13:42 51 (1) Sec.33(b). The resulting characteristic is illustrated in Fig. why did we study the physics of semiconductors and pn junctions in such detail? The developments in this chapter are representative of our treatment of all semiconductor devices: we carefully analyze the structure and physics of the device to understand its operation. VD falls in the range of 700 .on .on and as a constant voltage source if we attempt to increase VD beyond VD.800 mV. 2. 2006] June 30. Calculate IX for VX = 3 V and VX = 1 V using (a) an exponential model with IS = 10. Exercise A diode in forward bias with ID IS expVD =VT undergoes two simultaneous changes: the current is raised by a factor of m and the area is increased by a factor of n.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. while more accurate models reveal the true performance. Constant-Voltage Model The exponential I/V characteristic of the diode results in nonlinear equations. different levels of accuracy) prove essential to the analysis and design of circuits. the voltage source placed in series with the switch in the off condition helps simplify the analysis of circuits: we can say that in the transition from off to on. For this reason.on (a) VD (b) V D. Fortunately. inevitably. Example 2. Determine the change in the device voltage. With typical current levels and areas. While not essential. making the analysis of circuits quite difﬁcult. Reverse Bias ID V D. and we seek to approximate the resulting model. thus arriving at progressively simpler representations.on Forward Bias V D. we often approximate the forward bias voltage by a constant value of 800 mV (like an ideal battery). 2.2 PN Junction 51 Thus.on = 800 mV. we derive the circuit model shown in Fig. A number of questions may cross the reader’s mind at this point. Device models having different levels of complexity (and. we construct a “physics-based” circuit model. 2. the above examples imply that the diode voltage is a relatively weak function of the device current and cross section area. 2.33 Constant-voltage diode model. Simple models allow a quick. why do we subject the diode to such a seemingly inaccurate approximation? Second. Note that the current goes to inﬁnity as VD tends to exceed VD.on because we assume the forward-biased diode operates as an ideal voltage source. considering the device fully off if VD 800 mV.on Figure 2.34. First.33(a) with the turn-on voltage denoted by VD. a tenfold increase in the device area lowers the voltage by 60 mV if ID remains constant.

117) (2. IX = VX R VD 1 3 V . Following the same procedure for VX have = 1 V. 0:799 V 1k = 2:201 mA: 0 IX = 1 V . VD . 2006] June 30.116) (2. 2 Basic Physics of Semiconductors VX D1 R 1 = 1 kΩ VD Figure 2.119) (2.115) This equation must be solved by iteration: we guess a value for VD . 0:75 V = 1k = 2:25 mA: Thus.126) . we have VX = IX R 1 + VD VD = VT ln IIX : S (2. (a) Noting that ID Solution = IX . we can obtain a more accurate value for IX : (2.114) (2. determine the new value of VD from VD = VT lnIX =IS and iterate.125) (2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34 Simple circuit using a diode.k :75 V 1 = 0:25 mA.cls v.122) We note that the value of IX rapidly converges.120) IX = 3 V . compute the corresponding IX from IX R1 = VX . (b) A constant-voltage model readily IX = 2:2 mA for VX = 3 V IX = 0:2 mA for VX = 1 V: (2. we (2.118) VD = VT ln IX IS = 799 mV: With this new value of VD .121) (2.123) (2. Let us guess VD = 750 mV and hence . (2. (2.124) which yields VD gives = 0:742 V and hence IX = 0:258 mA. 2007 at 13:42 52 (1) 52 IX Chap.

Exercise Repeat the above example if the cross section area of the diode is increased by a factor of 10. thus lowering the resistance of the air and creating a tremendous current.35 Reverse breakdown characteristic. The breakdown resulting from a high voltage (and hence a high electric ﬁeld) can occur in any material. enormous current is observed.3 Reverse Breakdown 53 The value of IX incurs some error.” 2. but it is obtained with much less computational effort than that in part (a). 2.35 plots the device I/V characteristic. provide no loosely-connected carriers. The breakdown phenomenon in pn junctions occurs by one of two possible mechanisms: “Zener effect” and “avalanche effect.36(a)]. However. Once freed. therefore.1 Zener Breakdown The depletion region in a pn junction contains atoms that have lost an electron or a hole and.31 that the pn junction carries only a small. (2. displaying this effect. A common example is lightning. in which case the electric ﬁeld in the air reaches such a high level as to ionize the oxygen molecules. 2006] June 30. However.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.76) translates to high doping levels on both sides of the junction (why?).cls v. relatively constant current in reverse bias. 2.” this type of breakdown appears for reverse bias voltages on the order of 3-8 V. This section can be skipped in a ﬁrst reading. 2. ID V BD VD Breakdown Figure 2.3. . eventually “breakdown” occurs and a sudden. a narrow depletion region is required. the electrons are accelerated by the ﬁeld and swept to the n side of the junction. as the reverse voltage across the device increases. This effect occurs at a ﬁeld strength of about 106 V/cm (1 V/m).3 Reverse Breakdown Recall from Fig. a high electric ﬁeld in this region may impart enough energy to the remaining covalent electrons to tear them from their bonds [Fig. 2007 at 13:42 53 (1) Sec. 2. Called the “Zener effect. In order to create such high ﬁelds with reasonable voltages. which from Eq. Figure 2.

2007 at 13:42 54 (1) 54 Chap. Zener diodes with 3. For this reason. i Charge carriers move in semiconductors via two mechanisms: drift and diffusion. an avalanche effect takes place. Called “impact ionization.3. For example. It also contains a small number of free electrons at room temperature. a “hole” is left behind. 2. each carrier entering the depletion region experiences a very high electric ﬁeld and hence a large acceleration. An interesting contrast between Zener and avalanche phenomena is that they display opposite temperature coefﬁcients (TCs): VBD has a negative TC for Zener effect and positive TC for avalanche effect. . rapidly raising the number of free carriers. For doped or undoped semiconductors.36 (a) Release of electrons due to high electric ﬁeld. 2.” this phenomenon can lead to avalanche: each electron freed by the impact may itself speed up so much in the ﬁeld as to collide with another atom with sufﬁcient energy. in an n-type material. i n ND and hence p n2 =ND . For example. The bandgap energy is the minimum energy required to dislodge an electron from its covalent bond.cls v. (b) avalanche effect. The Zener and avalanche breakdown effects do not damage the diodes if the resulting current remains below a certain limit given by the doping levels and the geometry of the junction.5-V rating ﬁnd application in some voltage regulators. np = n2 . these two electrons may again acquire energy and cause more ionizing collisions. To increase the number of free carriers. thereby freeing one more covalent-bond electron. Now. But. Even though the leakage current is very small.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Both the breakdown voltage and the maximum allowable reverse current are speciﬁed by diode manufacturers.2 Avalanche Breakdown Junctions with moderate or low doping levels ( 1015 cm3 ) generally exhibit no Zener breakdown. 2 Basic Physics of Semiconductors n Si E Si Si e Si Si Si e Si p n e e e e e E p e e e e Si e e Si Si VR (a) VR (b) Figure 2. semiconductors are “doped” with certain impurities. thus gaining enough energy to break the electrons from their covalent bonds.4 Chapter Summary Silicon contains four atoms in its last orbital. When an electron is freed from a covalent bond. as the reverse bias voltage across such devices increases. 2006] June 30. addition of phosphorous to silicon increases the number of free electrons because phosphorous contains ﬁve electrons in its last orbital. The two TCs cancel each other for VBD 3:5 V.

and forward bias. (b) What doping level is necessary to provide a current density of 1 mA/m2 under these conditions? Assume the hole current is negligible.4 Chapter Summary 55 The drift current density is proportional to the electric ﬁeld and the mobility of the carriers and is given by Jtot = q n n + p pE . Under forward bias. Problems 1. a constantvoltage model may be used in some cases to estimate the circuit’s response with less mathematical labor.3 . The electric ﬁeld in the depletion results in a built-in potential across the region equal to kT=q lnNA ND =n2 . 1 . typically in the range of 700 to 800 mV. (a) Calculate ni at 300 K and 600 K and compare the results with those obtained in Example 2. they leave ionized atoms behind. 2 (2.cls v. The diffusion current density is proportional to the gradient of the carrier concentration and given by Jtot = q Dn dn=dx . (b) Repeat (a) for T = 400 K assuming for simplicity that mobility does not change with temperature.3 . 2. Under a high reverse bias voltage. the junction carries negligible current and operates as a capacitor. The pn junction can be considered in three modes: equilibrium. An n-type piece of silicon experiences an electric ﬁeld equal to 0. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The electric ﬁeld created in the depletion region eventually stops the current ﬂow. (a) Calculate the velocity of electrons and holes in this material. i Under reverse bias. pn junctions break down. The capacitance itself is a function of the voltage applied across the device. 2. Depending on the structure and doping levels of the device.1 V/m. “Zener” or “avalanche” breakdown may occur. (This is not a good assumption.1 for Si. calculate the total current ﬂowing through the device at T = 300 K.127) . Dp dp=dx. conducting a very high current. reverse bias. Upon formation of the pn junction. A n-type piece of silicon with a length of 0:1 m and a cross section area of 0:05 m0:05 m sustains a voltage difference of 1 V. (b) Determine the electron and hole concentrations if Ge is doped with P at a density of 5 1016 cm. and a “depletion resgion” is formed. 2007 at 13:42 55 (1) Sec. sharp gradients of carrier densities across the junction result in a high current of electrons and holes. The intrinsic carrier concentration of germanium (GE) is expressed as where Eg = 0:66 eV. As the carriers cross.kT cm. the junction carries a current that is an exponential function of the applie voltage: IS expVF =VT . A pn junction is a piece of semiconductor that receives n-type doping in one section and p-type doping in an adjacent section.3 . This condition is called equilibrium.) Eg ni = 1:66 1015 T 3=2 exp . Since the exponential model often makes the analysis of circuits difﬁcult. 2006] June 30. (a) If the doping level is 1017 cm.

10 but for x = 0 to x = 1.37 0 2 µm x and hole injection from the right. (a) To obtain a current of 1 mA with a voltage of 750 mV. Repeat Problem 7 if the electron and hole proﬁles are “sharp” exponentials.38 0 2 µm x 9.3 and NA = 4 1016 cm. (b) Calculate the built-in potential at T = 250 K. the p-side of a pn junction has not been doped. Assume n = 3900 cm2 =V s and p = 1900 cm2 =V s. 7. 2006] June 30. (a) Prove that the parallel combination operates as an exponential device. 6. 14. 2. If ND = 3 1016 cm. 2 Basic Physics of Semiconductors 4. calculate the built-in potential at T = 300 K. How do you explain the phenomenon of drift to a high school student? 10. Compare the results for linear and exponential proﬁles. A junction employs ND = 5 1017 cm. i. (a) Determine the majority and minority carrier concentrations on both sides.6 V.cls v. Determine the total current ﬂowing through the device if the cross section area is equal to 1 m 1 m. how should IS be chosen? (b) If the diode cross section area is now doubled. . From the data in Problem 1.3 and NA = 2 1015 cm. Consider a pn junction in forward bias.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.39.40 shows two diodes with reverse saturation currents of IS 1 and IS 2 placed in parallel. Explain the trend.. Due to a manufacturing error. (b) By what factor should NA be increased to double the junction capacitance? 13. Assume the cross section area of the bar is equal to a. 12.3 . 11. what voltage yields a current of 1 mA? 15.9. Repeat Problem 6 for Example 2. 8.e. 300 K. and 350 K. In Example 2.38). Figure 2. Determine the required ND if NA = 1017 /cm2 . compute the total number of electrons “stored” in the material from x = 0 to x = L.37 shows a p-type bar of silicon that is subjected to electron injection from the left 5 x 10 Electrons 16 2 x 10 16 Holes Figure 2. 5. Figure 2. 5 x 10 Electrons 16 2 x 10 16 Holes Figure 2. respectively (Fig. 2. they fall to negligible values at x = 2 m and x = 0. 2007 at 13:42 56 (1) 56 Chap. repeat Problem 3 for Ge.3 experiences a reverse bias voltage of 1.3 . A pn junction with ND = 3 1016 cm. (a) Determine the junction capacitance per unit area. An oscillator application requires a variable capacitance with the characteristic shown in Fig.

40 (b) If the total current is Itot . VX = 0:5 V. 16. (a) Prove that this combination can be viewed as a single two-terminal device having an exponential characteristic.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2. Compare the results with those obtained in Problem 19. Consider the circuit shown in Fig.42.4 Chapter Summary C j (fF/ µ m 2 ) 57 2.5 0 V R (V) Figure 2. Figure 2.5 −0. the cross section area of D1 is increased by a factor of 10.15 A. Note that VD1 changes little for VX 0:8 V.8 V. (b) For a tenfold change in the current.41 Calculate IB . D1 IB V D1 D1 V D2 VB Figure 2. Determine VD1 and IX for VX = 0:8 V and 1. 2. 2006] June 30. Calculate VD1 and IX for IX R1 2 kΩ VX D1 Figure 2.2 1. VD1 . we wish to increase IB by a factor of 10. 0.2 V. . What is the required change in VB ? 19. Two identical pn junctions are placed in series.cls v.41 shows two diodes with reverse saturation currents of IS 1 and IS 2 placed in series.3 −1. 2007 at 13:42 57 (1) Sec.2 V. In the circuit of Fig. and 1. 2.39 I tot VB D1 D2 Figure 2. IS 1 . and VD2 in terms of VB .42. and IS 2 . how much voltage change does such a device require? 17. 18. In the circuit of Problem 17. 1 V. where IS = 2 10. determine the current carried by each diode.42 20.

Suppose D1 in Fig. and 4 mA. If IS = 3 10. 2006] June 30. we wish D1 to carry a current of 0.42 must sustain a voltage of 850 mV for VX = 2 V.43 and wish to determine R1 and IS . Calculate R1 and IS . 23. D1 D2 IX R1 2 kΩ Figure 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In the circuit of Fig. does R1 carry a current equal to IX =2? Assume IS = 3 10. 2.cls v.47.44. Calculate R1 and IS . 2.44. 2. 2 Basic Physics of Semiconductors 21. . does R1 sustain a voltage equal to VX =2? Assume IS = 2 10. 2.43 that VX = 1 V ! IX = 0:2 mA and VX = 2 V ! IX = 0:5 mA. determine the value of R1 such that this resistor carries 0.44 25. 2. 28. Measure- IX VX R1 D1 Figure 2. For what value of IX in Fig. 24.44 depicts a parallel resistor-diode combination. We note IX R1 D1 VX Figure 2. 27. 29.45 ments indicate that IX = 1 mA ! VX = 1:2 V and IX = 2 mA ! VX = 1:8 V. Determine the required IS . 2 mA. Calculate the required IS . 2.16 A. 2.16 A.46 Calculate the voltage across R1 for IX = 2 mA.45 and wish to determine R1 and IS .42. 26. For what value of VX in Fig.46 employs two identical diodes with IS = 5 10. We have received the circuit shown in Fig.5 mA. calculate VD1 for IX = 1 mA. The circuit illustrated in Fig.5 mA for IX = 1:3 mA. 1 kΩ IX R1 D1 Figure 2.16 A. 2007 at 13:42 58 (1) 58 Chap. Figure 2.16 A. 2. 22. We have received the circuit shown in Fig. In the circuit of Fig.

51 . assume IS = 5 10.49 32. 34. Assume Iin varies from 0 to 2mA. 2007 at 13:42 59 (1) Sec. 2. 2. In the circuit of Fig. 31.48.51. Plot Vout as a function of Vin if Vin varies from . Using SPICE. IX VX R1 D1 Figure 2. Assume (a) a constantvoltage model.16 A.2 V to +2 V.50. Repeat Problem 31 for the circuit depicted in Fig. At what value of I in D1 R1 Vout Figure 2. 2.47 Assume IS = 5 10. 2.50 such that D1 carries 1 mA if Iin = 2 mA.4 Chapter Summary 59 D1 IX 1 mA R 1 D2 Figure 2. For the circuit shown in Fig.cls v. At what value of Vin are the voltage drops across R1 and D1 equal? R1 Vout V in D1 Figure 2.16 A for each diode. where R1 Iin are the currents ﬂowing through D1 and R1 equal? =1k . 2006] June 30. (b) an exponential model. 2. 2.48 SPICE Problems In the following problems.49.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. I in D1 Vout Figure 2.50 33. 30. plot Vout as a function of Iin . determine the value of R1 in Fig. R1 = 500 . Sketch VX as a function of IX for the circuit shown in Fig.

R1 such that Vout 0:7 V for References 1. 2 Basic Physics of Semiconductors 35. 1999. Streetman and S. Prentice-Hall. We say the circuit “limits” the output. Solid-State Electronic Device. 2. 2006] June 30. ﬁfth edition. use SPICE to select the value of Vin 2 V. In the circuit of Fig.cls v. Banerjee. B. 2007 at 13:42 60 (1) 60 Chap.51. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

3. ultimately arriving at interesting and real-life applications.1(b). the output of the transformer exhibits a zero dc content because the negative and positive half cycles enclose equal areas. We must 1 This value refers to the root-mean-square (rms) voltage.1 Initial Thoughts In order to appreciate the need for diodes. We proceed as follows: Diodes as Circuit Elements Ideal Diode Circuit Characteristics Actual Diode Applications Regulators Rectifiers Limiting and Clamping Circuits 3. 3. 2006] June 30. The result displays a positive average and some ac components.1(b) points to the need for a device that discriminates between positive and negative voltages. As shown in Fig.5 V. this is accomplished by ﬁrst stepping down the ac voltage by means of a transformer to about 4 V and subsequently converting the ac voltage to a dc quantity. 3.1. 110 2. implies that if the voltage across a resistor goes from positive to negative. V = IR. let us brieﬂy study the design of a cellphone charger. 2007 at 13:42 61 (1) 3 Diode Models and Circuits Having studied the physics of diodes in Chapter 2. The peak value is therefore equal to 2 The line ac voltage in most countries is at 220 V and 50 Hz.5.cls v. The charger converts the line ac voltage at 110 V1 and 60 Hz2 to a dc voltage of 3. so does the current through it. 3.1(a) perform this conversion? As depicted in Fig.1 Ideal Diode 3. we now rise to the next level of abstraction and deal with diodes as circuit elements. passing only one and blocking the other. Now suppose this waveform is applied to a mysterious device that passes the positive half cycles but blocks the negative ones. A simple resistor cannot serve in this role because it is linear. which can be removed by a low-pass ﬁlter (Section 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1(a). The waveform conversion in Fig. p 61 . leading to a zero average. This chapter also prepares us for understanding transistors as circuit elements in subsequent chapters.3 The same principle applies to adaptors that power other electronic devices. How does the black box in Fig. 3 The actual operation of adaptors is somewhat different. That is.1). Ohm’s law.

2007 at 13:42 62 (1) 62 V1 4 2 Chap.3(a). Figure 3. Note that the device is nonlinear because it does not satisfy y = x.2 summarizes the result of our thought process thus far. . Forward and Reverse Bias To serve as the mysterious device in the charger example of Fig.1. 2006] June 30.1 (a) Charger circuit. The corresponding terminals are called the “anode” and the “cathode.” Shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V V1 t Block Box Vout t (a) V1 4 2 ? t Equal Positive and Negative Areas (b) Positive Areas t Figure 3.2 Conceptual operation of a diode. therefore seek a device that behaves as a short for positive voltages and as an open for negative voltages. the diode must turn “on” if Vanode Vcathode and “off” if Vanode Vcathode [Fig. y (t ) t x (t ) t Figure 3. 3.3(a).cls v. 3 60 Hz Diode Models and Circuits t V line 110 2 60 Hz 3. 3. (b) elimination of negative half cycles. The mysterious device generates an output equal to the input for positive half cycles and equal to zero for negative half cycles. if x ! . the diode is a two-terminal device.x. y 6! .y . 3.2 Ideal Diode The mysterious device mentioned above is called an “ideal diode. with the triangular head denoting the allowable direction of current ﬂow and the vertical bar representing the blocking behavior for currents in the opposite direction.” respectively.

3. Consider the pipe shown in Fig.1 Ideal Diode 63 D1 Anode Cathode Forward Bias Reverse Bias IX (a) Hinge Forward Bias (b) Reverse Bias Pipe Valve Stopper (c) Figure 3. The diodes in Fig. 3. allowing a current. the valve rises. D1 A B (a) D2 C A D1 B (b) D2 C A D1 B (c) D2 C Figure 3. 3.4(a).3(b)]. If water pressure is applied from the left. Determine which one of the conﬁgurations in Fig. 2007 at 13:42 63 (1) Sec.3(c). we sometimes place more positive nodes higher to provide a visual picture of the circuit’s operation. allowing the ﬂow of current from A to B to C but not in the reverse direction. if water pressure is applied from the right.3 (a) Diode symbol.4 A water pipe analogy proves useful here.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Of course. 3. In Fig. diodes can be placed in series (or in parallel). (c) water pipe analogy. 4 In our drawings. and D2 . 3. the anodes of D1 and D2 point to the same direction.4(b).cls v. Example 3. the topology of Fig.4 can conduct current. On the other hand.1 As with other two-terminal devices. no current can ﬂow in either direction. Solution Exercise Determine all possible series combinations of three diodes and study their conduction properties. none of these circuits appears particularly useful at this point. from B to C . By the same token. 3. the stopper keeps the valve shut.3(b) are drawn according to this convention. Thus. where a valve (a plate) is hinged on the top and faces a stopper on the bottom. Vcathode = VD . . 2006] June 30. 3.4 Series combinations of diodes. we say the diode is “forward-biased” if VD tends to exceed zero and “reverse-biased” if VD 0. 3. (b) equivalent circuit.4(c) behaves as an open for any voltage. D1 stops current ﬂow from B to A. In Fig. Deﬁning Vanode . but they help us become comfortable with diodes.

2007 at 13:42 64 (1) 64 Chap. If VA 0. D1 is off. ID I R=0 V I R= Reverse Bias Forward Bias V VD (a) Figure 3.1) (3.5(b). 3.2 We said that an ideal diode turns on for positive anode-cathode voltages.3 Plot the I/V characteristic for the “antiparallel” diodes shown in Fig. Vcathode . this topology becomes much more interesting with actual diodes (Section 3.. The antiparallel combination therefore acts as a short for all voltages.6(a).resistor in series with the diode? Example 3. But the characteristic in Fig. a forward-biased ideal diode sustains a zero voltage—similar to a short circuit.2) The results are illustrated in Fig. it is often helpful to accompany equations with graphical visualizations. The result is illustrated in Fig. Since an ideal diode behaves as a short or an open. then the diode turns on and conducts inﬁnite current if the circuit surrounding the diode can provide such a current.3). Solution .5 I/V characteristics of (a) zero and inﬁnite resistors. the current that ﬂows through the device as a function of the voltage across it. How do we interpret this plot? This characteristic indicates that as VD exceeds zero by a very small amount.6(b). 3.5(a). 3. A common type of plot is that of the current/voltage (I/V) characteristic. (b) ideal diode. 3. yielding IA = 1. and ID is deﬁned as the current ﬂowing into the anode and out of the cathode. we combine the positive-voltage region of the ﬁrst with the negative-voltage region of the second. Thus. but D2 is on.5(b) does not appear to show any ID values for VD 0.cls v. 3 Diode Models and Circuits I/V Characteristics In studying electronic devices.e.5. Seemingly a useless circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. arriving at the ID =VD characteristic in Fig. 2006] June 30. i. Solution Exercise How is the characteristic modiﬁed if we place a 1. we ﬁrst construct the I/V characteristics for two special cases of Ohm’s law: R=0 I = V =1 R V = 0: R=1 I = R (3. again leading to IA = 1. Here. For an ideal diode. D1 is on and D2 is off. If VA 0. in circuits containing only ﬁnite currents. 3. (b) Example 3. VD = Vanode .

D1 remains off and IA = 0. the diode is on [Fig. But this implies that D1 carries a current from its cathode to its anode. and if VA is negative. 3. 2006] June 30. 2007 at 13:42 65 (1) Sec. Example 3. the circuit is reduced to that in Fig. IA IA D1 R1 (b) VA D1 R1 (a) IA R1 D1 R1 R1 (c) IA 1 R1 IA D1 R1 (e) VA VA (d) Figure 3. 3..7 (a) Diode-resistor series combination. postulating that the diode is off. D We surmise that. On the other hand. 3. If D1 is on. violating the deﬁnition of the diode. Let us study the circuit more rigorously. (b) resulting I/V characteristic. As VA rises above zero. for VA 0.1 Ideal Diode 65 IA VA D1 D2 IA VA (a) Figure 3. Suppose for some Solution . To conﬁrm the validity of this guess.7(a).7(b)] and IA = VA =R1 because VD1 = 0 for an ideal diode. let us assume D1 is on and see if we reach a conﬂicting result. We begin with VA 0. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if VA 0.7(c)] and ID = 0. Thus.6 (a) Antiparallel diodes.4 Plot the I/V characteristic for the diode-resistor combination of Fig. (b) equivalent circuit under forward bias. D1 is probably off [Fig. so is IA .7(d) plots the resulting I/V characteristic. 3. the actual current ﬂows from right to left. (d) I/V characteristic. if VA 0. (e) equivalent circuit if 1 is on. Figure 3. it tends to forward bias the diode. (c) equivalent circuit under reverse bias.cls v.e. Does D1 turn on for any VA 0 or does R1 shift the turn-on point? We again invoke proof by contradiction. The above observations are based on guesswork. i. (b) Exercise Repeat the above example if a 1-V battery is placed is series with the parallel combination of the diodes.7(e).

This assumption is therefore incorrect. In other words.cls v. If uncertain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution . we can assume an arbitrary state (on or off) for each diode and proceed with the computation of voltages and currents. Vout = VA = +3 V. Determine the response observed at the output. Example 3. if the assumptions are incorrect. the ﬁnal result contradicts the original assumptions. The above example leads to two important points. then we surmise that D1 is forward-biased and D2 . Exercise Repeat the above analysis if the terminals of the diode are swapped. If VA = +3 V. it is helpful to ﬁrst examine the circuit carefully and make an intuitive guess. D1 is still off. behaving as an open circuit and yielding IA = 0. we often prefer to consider the voltage to be the “cause” and the current.6 Figure 3. The voltage drop across R1 is therefore equal to zero. the series combination of D1 and R1 acts as an open for negative voltages and as a resistor of value R1 for positive voltages. immediately facing a conﬂict: D1 enforces a voltage of +3 V at the output whereas D2 shorts Vout to VB = 0.8 OR gate realized by diodes. Also. reverse-biased.5 Why are we interested in I/V characteristics rather than V/I characteristics? Solution In the analysis of circuits. In the circuit of Fig. each input can assume a value of either zero or +3 V. First. 3 Diode Models and Circuits VA 0. devices such as transistors fundamentally produce current in response to voltage. Of course. Exercise Plot the V/I characteristic of an ideal diode. Second. in the analysis of circuits.” This is because in typical circuits. 2007 at 13:42 66 (1) 66 Chap. 2006] June 30. the “effect. we can assume both D1 and D2 are forward-biased. Thus. D1 VA VB D2 RL Vout Example 3. 3.8. and VB = 0. D1 turns on for any VA 0. voltage polarities can be predicted more readily and intuitively than current polarities. suggesting that VD1 = VA and hence ID1 = 1 and contradicting the original assumption.

10(a). and if Vin 0.9(a). In practice. Since R1 has a tendency to maintain the cathode of D1 near zero. as Vin rises. 3. 3. Input/Output Characteristics Electronic circuits process an input and generate a corresponding output. we have Vout = Vin . we consider slightly positive or negative voltages to determine the response of a diode circuit. Exercise Construct a three-input OR gate. This state holds for the positive half cycle. After all.5 The circuit of Fig. D1 is on and Vout = Vin .9(b). we obtain the 5 Note that without R1 .9(d) illustrates the overall input/output characteristic. D1 is forward biased.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 Application Examples Recall from Fig. 3. D1 is reverse biased. Thus. If Vin 0. 3. We therefore modify the circuit as depicted in Fig. shorting the output and forcing Vout = 0 [Fig. 3. The circuit operates as a logical OR gate and was in fact used in early digital computers. a piece of wire experiencing a zero voltage behaves similarly. consider the circuit depicted in Fig. the state of an ideal diode with VD = 0 is somewhat arbitrary and ambiguous. We may naturally construct the circuit as shown in Fig. 3. An example. this does not mean it acts as an open circuit. 3. where the output is deﬁned as the voltage across D1 .7 Solution = 0? An ideal diode experiencing a zero voltage must carry a zero current (why?). 3.2 that we arrived at the concept of the ideal diode as a means of converting xt to y t. Let us now design a circuit that performs this function. then D1 is forward biased. Is an ideal diode on or off if VD Example 3. shorting the output to the input.” the output current is always equal to zero.cls v. D1 is off and Vout = 0.resistor is placed in series with the diode.10(c)]. If Vin 0. 2006] June 30. 2007 at 13:42 67 (1) Sec. 3.10(b) and analyze its response to a sinusoidal input [Fig. It is therefore instructive to construct the input/output characteristics of a circuit by varying the input across an allowable range and plotting the resulting output. D1 turns off and R1 ensures that Vout = 0 because ID R1 = 0. Unfortunately. Noting that if Vin 0. the cathode of the diode is “ﬂoating.1. 3. however. and the state of the diode is ambiguous.1 Ideal Diode 67 The symmetry of the circuit with respect to VA and VB suggests that Vout = VB = +3 V if VA = 0 and VB = +3 V. However. When Vin falls below zero.” It is instructive to plot the input/output characteristic of the circuit as well. Exercise Repeat the above example if a 1. . Figure 3. reducing the circuit to that in Fig. Since no current ﬂows through R1 . the output voltage is not deﬁned because a ﬂoating node can assume any potential.10(b) is called a “rectiﬁer.9(c)].

3.10(c) to arrive at another interesting application.7(a). (c) equivalent circuit for positive input.9 (a) Resistor-diode circuit. 2006] June 30. we have Vout = Vp sin !t for 0 t T 2 T tT = 0 for 2 1 Z T V tdt Vout. The rectiﬁer is a nonlinear circuit because if Vin Vout 6! .10(d) look similar? No.10(d). We now determine the time average (dc value) of the output waveform in Fig.Vout . 3. Solution Exercise Construct the characteristic if the terminals of D1 are swapped.8 Is it a coincidence that the characteristics in Figs.3) (3. we recognize that the output voltage in Fig.Vin then Example 3.4) To compute the average. Suppose Vin = Vp sin !t. the two plots differ by only a scaling factor equal to R1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3. we obtain the area under Vout and normalize the result to the period: 1 Z T=2 V sin !tdt =T p (3. (b) equivalent circuit for negative input. ! . Then.5) (3. (d) input/output characteristic. where ! = 2=T denotes the frequency in radians per second and T the period. 2007 at 13:42 68 (1) 68 V in < 0 R1 V in D1 Vout V in R1 Chap. in the ﬁrst cycle after t = 0. 3.6) . 3 Diode Models and Circuits V in > 0 R1 Vout V in Vout (a) (b) (c) Vout V in 1 (d) Figure 3. 3. Thus.7(d) and 3.10(b) is simply equal to IA R1 in Fig. behavior shown in Fig.cls v.avg = T out 0 0 (3.

That is. 1 = T Vp . (c) input and output waveforms. 2006] June 30. a rectiﬁer can operate as a “signal strength indicator.” For example. A cellphone receives a 1.8) Thus. (b) complete rectiﬁer.resistor is placed in series with the diode? .1 Ideal Diode D1 V in Vout V in D1 R1 Vout 69 (a) (b) V in t Vout 1 V in R1 V in R1 Rectified Half Cycles V in Vout 0 T 2 T (c) 3T 2 2T t (d) Figure 3. since cellphones receive varying levels of signal depending on the user’s location and environment.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.10 (a) A diode operating as a rectiﬁer.cls v. an expected result because a larger input amplitude yields a greater area under the rectiﬁed half cycles. V= = 0:637 V to 10 Exercise Do the above results change if a 1. 3. they require an indicator to determine how much the signal must be ampliﬁed. (d) input/output characteristic.9 Solution The rectiﬁed output exhibits an average value ranging from 2 mV/ = 3:18 mV. cos !t T=2 0 ! = Vp : (3.7) (3. the average is proportional to Vp . what is the corresponding range of the output average? Example 3. The above observation reveals that the average value of a rectiﬁed output can serve as a measure of the “strength” (amplitude) of the input.8-GHz signal with a peak amplitude ranging from 2 V to 10 mV. 2007 at 13:42 69 (1) Sec. If the signal is applied to a rectiﬁer.

For Vin 0. equal to 0. 2007 at 13:42 70 (1) 70 Chap. 3. 3. 3 Diode Models and Circuits In our effort toward understanding the role of diodes. where a 1-V battery is placed in series with an ideal diode. Shown in Fig.11(c). 2006] June 30. The circuit therefore does not allow the Example 3.3) lead to some important applications. Thus. VB . consider the topology in Fig. let us examine the circuit in Fig. the modiﬁcation indeed guarantees Vout +1 V for any input level.10 . “Limiters” prove useful in many applications and are described in Section 3. implying that a 1-V battery must be inserted in series with the diode. 3. the cathode voltage is higher than the anode voltage.11(b) be modiﬁed? In this case.11(c) for a sinusoidal input as the battery voltage. e. Sketch the time average of Vout in Fig.3. we examine another circuit that will eventually (in Section 3. the I/V characteristic of the diode-battery combination resembles that of a diode. 3. Even if V1 is slightly greater than zero. placing D1 in reverse behave? If V1 bias. (b) resistor-diode circuit.g. D1 must turn on only when Vout approaches +1 V. output to exceed zero. We say the circuit “clips” or “limits” at +1 V.11(a). the anode is not positive enough to forward bias D1 .cls v.9 V. (c) addition of series battery to (b).11 (a) Diode-battery circuit.5.11(a). D1 remains off. for Vin 0. How should the circuit of Fig. 3. First. But suppose we seek a circuit that must not allow the output to exceed +1 V (rather than zero)..11(b). and Vout = 0. D1 acts a short. Now. yielding Vout = Vin . Here. 3. but shifted to the right by 1 V. I1 I1 V1 D1 VB 1V +1 V (a) V1 Vout R1 V in D1 Vout V in t Vout 1 V in t (b) R1 D1 VB 1V V in + Vp V in Vout Vout t − Vp +1V Vout +1 V +1 V 1 V in t − Vp (c) Figure 3.5. How does this circuit 0. V1 must approach +1 V for D1 to turn on.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. as illustrated in the output waveform and the input/output characteristic. Depicted in Fig.

yielding an average greater than .1 to +1. D1 is always on because Vin . 3. Example 3. no limiting occurs and the average is equal to zero.11(b) a rectiﬁer? Solution Yes.Vp but less than VB . for VB Vp . If VB is very negative. 2007 at 13:42 71 (1) Sec.Vp .12(b) sketches this behavior. .12 . VB < − Vp V in t VB − Vp − Vp < VB Solution V in VB Vout − Vp t Vout = VB VB = 0 + Vp < VB + Vp VB V in VB Vout − Vp (a) t Vout t Vout − Vp + Vp − Vp − Vp 1 (b) π VB Figure 3. Exercise How should the circuit of Fig. 2006] June 30. 3. Figure 3. Exercise Repeat the above example if the terminals of the diode are swapped. producing a negative average. For . the output average is equal to VB [Fig. For VB = 0. indeed. 3.cls v. the average reaches .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In this case.12(a)].11 Is the circuit of Fig.1 Ideal Diode 71 varies from .11(b) be modiﬁed to pass only positive cycles to the output. D1 turns off at some point in the negative half cycle and remains off in the positive half cycle. 3.Vp = . The circuit passes only negative cycles to the output. Finally.Vp VB 0.

Figures 3. how do we choose one of the above models for the diodes? We may utilize the ideal model so as to develop a quick. 3 Diode Models and Circuits 3. we may discover that this idealization is inadequate and hence employ the constant-voltage model. Given a circuit topology. (a) We begin with Vin = . Example 3. The following examples illustrate these points.13(a) and (b) plot the I/V characteristics of the ideal diode and the pn junction.cls v. 3. operating as a short and reducing the circuit to a voltage Solution . 3. the forward and reverse bias conditions depicted in Fig.13 Diode characteristics: (a) ideal model. (c) constant-voltage model. for Vin 0.on V D.14(a) using (a) the ideal model and (b) the constant-voltage model.3(b) are quite similar to those studied for pn junctions in Chapter 2. ID Ij VD (a) (b) Vj ID V D. 3. rough understanding of the circuit’s operation.12 Plot the input/output characteristic of the circuit shown in Fig. recognizing that D1 is reverse biased. Upon performing this exercise. the diode remains off and no current ﬂows through the circuit.on (c) Figure 3.on VD V D.13 is the constant-voltage model developed in Chapter 2. providing a simple approximation of the exponential function and also resembling the characteristic plotted in Fig. 2007 at 13:42 72 (1) 72 Chap. This model sufﬁces in most cases. In fact. (b) exponential model.1. respectively. As Vin exceeds zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the voltage drop across R1 is zero and Vout = Vin . D1 turns on. 2006] June 30. Shown in Fig. The latter can serve as an approximation of the former by providing “unilateral” current conduction. Thus.2 PN Junction as a Diode The operation of the ideal diode is somewhat reminiscent of the current conduction in pn junctions. In fact. 3. but we may need to resort to the exponential model for some circuits.11(a).

on Vout = R1 (3.on Vout R2 R2 + R1 V D. divider.on V in Figure 3. displaying the same shape as that in Fig.on if Vin = VD.on . plot the current through R1 as a function of Vin . 3.14(b) but with a shift in the break point. In other words. 3. Reducing the circuit to that in Fig. Vout = Vout .14 (a) Diode circuit. Vout = VD. That is. Exercise In the above example.14(b) plots the overall characteristic. D1 is reverse biased for Vin VD. 3.11) : 1 + R2 R1 As expected. . yielding Vout = Vin .14(d) plots the resulting characteristic.on : R1 R2 It follows that (3.13(c)].on . As Vin exceeds VD.2 PN Junction as a Diode 73 V in R1 Vout R2 D1 Vout R2 R2 + R1 V in 1 (a) (b) V in R1 Vout R2 V D. operating as a constant voltage source with a value VD. 2007 at 13:42 73 (1) Sec. (b) input/output characteristic with ideal diode model.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. D1 turns on. we apply Kirchoff’s current law to the output node: Vout = R R2 R Vin for Vin 0: 1+ 2 (3. VD.cls v.14(c). revealing a slope equal to unity for Vin 0 and R2 =R2 + R1 for Vin 0. (c) input/output characteristic with constant-voltage diode model .9) Vin . Figure 3. the circuit operates as a voltage divider once the diode turns on and loads the output node with R2 .on . 2006] June 30. 3.on 1 (c) (d) V D.on [as illustrated in Fig.10) R2 V + V in D. (b) In this case. Figure 3.

I I S1 S2 that is. 2007 at 13:42 74 (1) 74 Chap.15. calculate VD is terms of Iin . D1 and D2 have different cross section areas but are otherwise identical.13 In the circuit of Fig. IS 1 . we must resort to the exponential equation because the ideal and constant-voltage models do not include the device area.3 Additional Examples Example 3.16) This section can be skipped in a ﬁrst reading . ID1 = Exercise For the circuit of Fig. 3.14) Iin I 1 + IS 2 S1 Iin : ID2 = I 1 + IS 1 S2 As expected.15) (3. We have Iin = ID1 + ID2 : We also equate the voltages across D1 and D2 : (3.12) VT ln ID1 = VT ln ID2 .13) ID1 = ID2 : IS1 IS2 Solving (3.14) together yields (3. 3 Diode Models and Circuits 3.cls v. Determine the current ﬂowing through each diode.15 Diode circuit. (3. Solution In this case.15. I in R 1 V1 D1 D2 Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (3. ID1 = ID2 = Iin =2 if IS 1 = IS 2 . 2006] June 30. 3.12) and (3. and IS 2 .

1.on 2 .cls v.16(b). Solution In this case.on and hence (3. vout = R R2 R Vin : 1+ 2 R2 V = V . Consequently. R1 + R2 in D.on R1 ) V D.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. requiring an input voltage given by: (3.18) R1 V : Vin = 1 + R D. We note that if Vin = .on . R1 Vout R2 D1 R1 Vout R2 V in V in (a) (b) Vout V D.on R2 V in R2 R2 + R1 (1 + (c) Figure 3.3 Additional Examples 75 Example 3. (c) input/output characteristic.17) At what point does D1 turn on? The diode voltage must reach VD.16(a).16 (a) Diode circuit. Note that a diode about to turn on carries zero current but sustains VD. 3. 2006] June 30. 3. the voltage across the diode happens to be equal to the output voltage.on . (b) equivalent circuit when D1 is off.14 Using the constant-voltage model plot the input/output characteristics of the circuit depicted in Fig. 2007 at 13:42 75 (1) Sec. D1 is reverse biased and the circuit reduces to that in Fig. 3.

The diode therefore still draws no current. it creates Vout 799 mV.19) The reader may question the validity of this result: if the diode is indeed on. e.g. (3. it draws current and the diode voltage is no longer equal to R2 =R1 + R2 Vin . So why did we express the diode voltage as such in Eq. we assume Vin gradually increases so that it places the diode at the edge of the turn-on..18)? To determine the break point. but the voltage across it and hence the input voltage are almost sufﬁcient to turn it on. . (3.

on : (3. 2007 at 13:42 76 (1) 76 Chap.on R2 R1 R1 + R2 V in 1 (c) (d) Figure 3. D1 remains forward-biased.on . Example 3.e. Note that in this regime. Thus.15 Plot the input/output characteristic for the circuit shown in Fig.17(a). 3 Diode Models and Circuits For Vin 1 + R1 =R2 VD. i.16(c) plots the overall characteristic.on X D1 R2 R1 Vout V in = − (a) (b) Vout V in R2 Vout R1 R ( 1 + 1 ) V D. establishing a voltage at node X equal to Vin + VD. Assume a constantvoltage model for the diode.17(b).on . (b) illustration for very negative inputs. 3.20) . (d) input/output characteristic.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1.cls v. yielding Vout 3.17 (a) Diode circuit. the anode is tied to ground and the cathode the output node. D1 is We begin with Vin = . This diagram suggests that the diode operates in forward bias. placing the more negative voltages on the bottom and the more positive voltages on the top. we have Solution Vout = Vin + VD. so long as D1 is on. Figure Exercise Repeat the above example but assume the terminals of D1 are swapped. = VD. plot the current through R1 as a function of Vin . and redraw the circuit as depicted in Fig. 2006] June 30. D1 V in R2 X R1 Vout V D.on .. Exercise For the above example. 3. (c) equivalent circuit when off. VX is independent of R2 because D1 acts as a battery.

Exercise Repeat the above example if the terminals of the diode are swapped. 2006] June 30. we may simply make a guess. predicting intuitively that D1 is on.22) R1 + = . in more complex circuits. we still apply intuition to minimize the guesswork.1 + R1 VD. proceed with the analysis. IR2 = IR1 proves useful here as this condition also implies that D1 carries no current (KCL at node X ). 3. IR2 remains constant but jIR1 j decreases.on : 2 As Vin exceeds this value. 3.on = . and eventually determine if the ﬁnal result agrees or conﬂicts with the original guess. From (3. At what point does D1 turn off? Interestingly.23) 1 Thus.on R2 R1 and hence (3. The following example illustrates this approach.21) and (3.18(a) using the constant-voltage diode model.17(d).17(c) and (3. The reader may ﬁnd it interesting to recognize that the circuits of Figs. the output is sensed across the diode whereas in the latter it is sensed across the series resistor.3 Additional Examples 77 We also compute the current ﬂowing through R2 and R1 : IR2 = VD. as Vin increases from .16(a) and 3.1.25) Vout = R R1 R Vin : 1+ 2 (3. the circuit reduces to that shown in Fig. We begin with Vin Solution = . 3.. Vin + VD. In other words. it may be difﬁcult to correctly predict the region of operation of each diode by inspection. at some point IR2 = IR1 .17(a) are identical: in the former.4. In such cases.16 Plot the input/output characteristic of the circuit shown in Fig. We also (blindly) assume that D2 . 2007 at 13:42 77 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The observation that at some point. i.23).on : (3. As mentioned in Example 3.e.Vin R VD. 3. 3. in this case it is simpler to seek the condition that results in a zero current through the diode rather than insufﬁcient voltage across it. VX (3. Example 3. Of course.1. D1 turns off if Vin is chosen to yield IR2 = IR1 . VD.26) The overall characteristic is shown in Fig.21) R2 IR1 = 0 .on (3.cls v.24) R Vin = .

(d) equivalent circuit.on . We must now analyze these results to determine whether they agree with our assumptions regarding the state of D1 and D2 .on V D.27) IR1 = . The path through VD. 2VD. 3 Diode Models and Circuits I R2 = D1 V in D2 Y V B= 2 V R1 X R1 Vout V D.on V in D 1 turns off.on D1 X R1 Vout Y VB R1 D2 Y V B= 2 V (e) R1 (d) Vout D1 − V D. (f) section of input/output characteristic.on : R 1 (3.on + VB .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.on ..on R2 Vout R1 X Y VB I R1 R1 X V in = − (a) (b) V in = − (c) D1 V in D2 X R1 Vout V in = − V D.on = .cls v.18(b). thus reducing the circuit to that in Fig.28) That is. 2007 at 13:42 78 (1) 78 Chap.on R2 Vout VB Y I1= V D. i. This voltage difference also appears across the branch consisting of R1 and VD. yielding R1 IR1 + VD.on Vout X R1 Vout D2 Y V B= 2 V R1 − V D. V in V in (f) (g) (h) Figure 3. (b) possible equivalent circuit for very negative inputs. (f) complete input/output characteristic.VB + VD. VR 2 (3.on and VB creates a difference of VD.18 (a) Diode circuit. Vout = Vin .on + VB between Vin and Vout . (g) equivalent circuit. V = . 2006] June 30. (c) simpliﬁed circuit. (e) equivalent circuit for in D. Consider the current ﬂowing through R2 : out IR2 = . VD. IR1 is independent of Vin .e.V is on. 3.on . and hence (3.29) .VB .

VX = Vin + VD.on . At what point does D2 turn on? The input voltage must exceed VY by VD. the voltage at node Y is equal to +VB whereas the cathode of D2 is at . Vout = Vin . revealing that Vout = 0 after the ﬁrst break point because the current ﬂowing through R1 and R2 is equal to zero.on .31) We now raise Vin and determine the ﬁrst break point. Vout = 0.30) Vout = Vin + VD. 2 (3.1.VD. .on . as the number of nonlinear devices in the circuit increases. Assuming that D1 is still slightly on. However. which is not possible.VD. i.18(c) and noting that VX = Vin + VD. Which one occurs ﬁrst? Let us assume D1 turns off ﬁrst and obtain the corresponding value of Vin . Since at this break point. assume D2 turns on before D1 turns off and show that the results conﬂict with the assumption.e. D2 must conduct current from its cathode to it anode.4 Large-Signal and Small-Signal Operation Our treatment of diodes thus far has allowed arbitrarily large voltage and current changes. We must now verify the assumption that D2 remains off. we have D.on R R2 R : 1+ 2 (3. summarizing the regions of operation. We call this regime “largesignal operation” and the exponential characteristic the “large-signal model” to emphasize that the model can accommodate arbitrary signal levels. “manual” analysis eventually becomes impractical. after which the circuit is conﬁgured as shown in Fig.18(f) plots the input-output characteristic to the extent computed thus far. Before D2 turns on. VX = Vout = 0. That is.18(g).18(h) plots the overall result. VD. 3.18(d).VD.cls v.. i.on . Consequently. we draw the circuit as shown in Fig. but the sharp nonlinearity at the turn-on point still proves problematic. (3. 2007 at 13:42 79 (1) Sec.e. as seen in previous examples. and hence D1 . 3. 3. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this model often complicates the analysis. The ideal and constant-voltage diode models resolve the issues to some extent. D2 operates in reverse bias for Vin = . Redrawing the circuit as in Fig. 2006] June 30. we recognize that at Vin . 3. 3. making it difﬁcult to develop an intuitive understanding of the circuit’s operation. The following example illustrates the general difﬁculty.32) Exercise In the above example. R2 . we have observed that the forward bias assumption for D2 translates to a current in a prohibited direction.1. In other words.on [Fig. VB : Figure 3. Since D2 is assumed off.18(e)].on . The diode therefore turns off at Vin = . In summary.on approaches zero. VR . The large value of IR2 and the constant value of IR1 indicate that the branch consisting of VB and D2 carries a large current with the direction shown. VB .on .4 Large-Signal and Small-Signal Operation 79 which approaches +1 for Vin = . Thus. 3. Fig. Vin .on = . the point at which D1 turns off or D2 turns on. thereby requiring a “general” model such as the exponential I/V characteristic. D2 is indeed off. Furthermore. and VY = VB . Vin must reach VB + VD. yielding a zero current through R1 ..

3. (a) With Vout = 2:4 V.109) that a tenfold change in a diode’s current translates to a 60-mV change in its voltage. 3 Diode Models and Circuits Example 3. this assumption may not be valid. Then. raising IX to 7 mA. ﬁrst suppose Vout remains constant and equal to 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34) IX = IS exp VD : V T It follows that (3. 7 Recall from Eq.38) 6 Made for the sake of simplicity here. IX = Vad R Vout 1 = 6 mA: We note that each diode carries IX and hence (3.17 Having lost his 2.35) mV 6 mA = IS exp 800mV 26 and (3.37) (b) If Vad increases to 3. Since the voltage across each diode has a logarithmic dependence upon the current. the additional 0. the current ﬂowing through R1 is equal to . 2006] June 30. where three identical diodes in forward bias produce a total voltage of Vout = 3VD 2:4 V and resistor R1 sustains the remaining 600 mV. saturation current.19 Adaptor feeding a cellphone.1 V must drop across R1 . (2.6 (a) Determine the reverse IX 600 mV R 1 = 100 Ω Vad = 3 V Adaptor Vout Cellphone Figure 3. an electrical engineering student tries several stores but does not ﬁnd adaptors with outputs less than 3 V. 2007 at 13:42 80 (1) 80 Chap. the change from 6 mA to 7 mA indeed yields a small change in Vout . IS 1 so that Vout 3.4 V. He then decides to put his knowledge of electronics to work and constructs the circuit shown in Fig.19.1 V.7 To examine the circuit quantitatively.4-V cellphone charger. (b) Compute Vout if the adaptor voltage is in fact Solution = 2:4 V.36) IS = 2:602 10. . Neglect the current drawn by the cellphone. we begin with IX = 7 mA and iterate: Vout = 3VD (3.1 V. we expect that Vout increases only slightly. To understand why.cls v.16 A: (3.33) (3.

These thoughts lead us to the extremely important concept of “small-signal operation.40) . To develop our understanding of small-signal operation. we conclude that Vout = 2:411 V with good accuracy. Exercise Repeat the above example if an output voltage of 2. ID ? We can begin with the nonlinear characteristic: Vad from 3 V to 3.39) (3. The change in If V + ID2 = IS exp VD1V V T VD1 exp V : = IS exp V VT T VT . The simplicity arises because such models are linear. 3. 2007 at 13:42 81 (1) Sec.20(c)].cls v. Of course. the reader may wonder if a simpler approach is really necessary. allowing standard circuit analysis and obviating the need for iteration.47) .43) (3.45) (3. 3. The constant-voltage diode model would not be useful in this case. since the above example does not present an overwhelmingly difﬁcult problem. which translates to a new Vout : (3.44). as seen in subsequent chapters. How do we predict the change in the diode current.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. circuits containing complex devices such as transistors may indeed become impossible to analyze if the nonlinear equations are retained. which sustains a voltage VD1 and carries a current ID1 [point A in Fig.20(a).4 Large-Signal and Small-Signal Operation 81 = 3VT ln IX I = 2:412 V: This value of Vout gives a new value for IX : S (3. The deﬁnition of “small” will become clear later.40) and (3.” whereby the circuit experiences only small changes in voltages and currents and can therefore be simpliﬁed through the use of “small-signal models” for nonlinear devices.44) Noting the very small difference between (3. let us consider diode D1 in Fig.46) (3. 2006] June 30. 3.35 is desired. 3. then expV=VT 1 + V=VT and ID2 = IS exp VD1 + V IS exp VD1 VT VT VT (3.42) Vout = 3VD = 2:411 V: (3.41) (3. motivating The situation described above is an example of small “perturbations” in circuits.20(b)].1 V results in a small change in the circuit’s voltages and currents. Now suppose a perturbation in the circuit changes the diode voltage by a small amount VD [point B in Fig. But. us to seek a simpler analysis method that can replace the nonlinear equations and the inevitable iterative procedure. IX = Vad R Vout 1 = 6:88 mA.

3.) The above result should not come as a surprise: if the change in VD is small. the section of the characteristic in Fig.52) I = VS exp VD1 VT T D = IV 1 . ID dID VD = dVD jV D=V D1 (3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.49) The key observation here is that ID is a linear function of V .50) (3. I D2 ID I D2 I D1 A V D1 V D2 VD B I D1 A ∆V D B ∆I D Figure 3. (c) change in ID as a result (3.21). The signiﬁcance of this trend becomes clear later. 3. ID = V ID1 : V T (3.20 (a) General circuit containing a diode. T which yields the same result as that in Eq. (b) operating point of of change in D .8 8 This is also to be expected.45) to obtain the change in equivalent to taking the derivative.48) = ID1 + V ID1 : V T That is. (3.20(c) between points A and B can be approximated by a straight line (Fig. Writing Eq. with a slope equal to the local slope of the characteristic.21 Approximation of characteristic by a straight line.49).51) (3.cls v. (3. 2007 at 13:42 82 (1) 82 Chap. 2006] June 30. 3 Diode Models and Circuits ID V D1 D1 I D1 I D1 A V D1 (a) (b) ID I D2 I D1 VD ? B A V D1 V D2 (c) ∆V D VD Figure 3. In other words. with a proportionality factor equal to ID1 =VT . ID for a small change in VD is in fact . V D1 . (Note that larger values of ID1 lead to a greater ID for a given VD .

dID =dVD calculated at VD = VD1 or ID = ID1 ). Example 3. Point A is called the “bias” point or the “operating” point.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (a) Determine the current change if VD changes by 1 mV.e.54) = 38:4 A: VD = VT ID I = 1 mA 0:1 mA = 2:6 mV: . If the voltage across a diode changes by a small amount (much less than VT ).cls v. then the change in the current is given by Eq. 3. it moves on a straight line to point B with a slope equal to the local slope of the characteristic (i.21 and.18 Solution (a) We have I ID = VD VD T (b) Using the same equation yields (3. 2007 at 13:42 83 (1) Sec.9 A diode is biased at a current of 1 mA. 3.53) (3. Equivalently..49).4 Large-Signal and Small-Signal Operation 83 Let us summarize our results thus far. (3. for small-signal analysis. we can assume the operation is at a point such as A in Fig. (b) Determine the voltage change if ID changes by 10%. 2006] June 30. due to a small perturbation.

In analogy with Ohm’s Law.58) This quantity is also called the “incremental” resistance to emphasize its validity for small changes. Note that v1 and vout in 9 Also called the “quiescent” point. a diode exhibits a voltage change of 3 mV.22(a) summarizes the results of our derivations for a forward-biased diode. For bias calculations.57) Exercise In response to a current change of 1 mA. Figure 3. 3. the device behaves as a linear resistor.22(b) is transformed to that in Fig. 3. with a resistance equal to rd . rd = 26 . Equation (3. In the above example.56) (3. .D mV 26 (3. the circuit of Fig. For example. the diode is replaced with an ideal voltage source of value VD.on .55) in the above example reveals an interesting aspect of small-signal operation: as far as (small) changes in the diode current and voltage are concerned. and for small changes.22(c) if only small changes in V1 and Vout are of interest.55) (3. Calculate the bias current of the diode. we deﬁne the “small-signal resistance” of the diode as: rd = VT : I D (3.

23 (a) Sinusoidal input along with a dc level. It follows that. 2006] June 30. In general.23(a). T and (3.cls v. as the bias point of the diode and Vp as a small perturbation. (c) smallsignal model. we rotate this diagram by 90 so that its vertical axis is aligned with the voltage axis of the diode characteristic. V I0 = IS exp V 0 .22(c) represent changes in voltage and are called small-signal quantities. A sinusoidal signal having a peak amplitude of Vp and a dc value of V0 can be expressed as V t = V0 + Vp cos !t.23(b). As shown in Fig.60) . 3. determine the resulting diode current. R1 VD.19 Solution The signal waveform is illustrated in Fig. (b) circuit example. we denote small-signal voltages and currents by lower-case letters.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. If this signal is applied across a diode and Vp VT .22 Summary of diode models for bias and signal calculations. 2007 at 13:42 84 (1) 84 Chap. 3. we can view V0 and the corresponding current. 3. With a signal swing much less than VT . ID ID Ip V (t ) V0 I0 Vp VD t t V0 t (a) (b) Figure 3. (b) response of a diode to the sinusoid. Example 3.on Bias Model (a) R1 D1 Vout v1 rd v out rd Small−Signal Model V1 (b) (c) Figure 3. 3 Diode Models and Circuits Fig.59) rd = VT : I 0 (3. I0 .

V T a task much more difﬁcult than the above linear calculations.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Beginning with VD = VT lnID =Is . we have Example 3. ID changes by a small amount and we wish to compute the change in VD .64) The diode in the above example produces a peak current of 0. we would need to solve the following equation ID t = IS exp V0 + Vp cos !t . T yielding (3. If Vp were large. 3. the peak current is simply equal to Ip = Vp =rd I = V0 Vp .cls v. 2007 at 13:42 85 (1) Sec. 2006] June 30. Exercise = 800 mV The above example demonstrates the utility of small-signal analysis.62) ID t = I0 + Ip cos !t V I = IS exp V 0 + V0 Vp cos !t: T T (3.61) (3. investigate the reverse case..10 (3.49).20 Solution VD1 + VD = VT ln ID1 + ID I = VT ln IID1 1 + ID I S S . (3. i.4 Large-Signal and Small-Signal Operation 85 Thus. Calculate IS . we assumed a small change in VD and obtained the resulting change in ID .e. Denoting the change in VD by VD .1 mA in response to V0 and Vp = 1:5 mV.63) (3.65) In the derivation leading to Eq.

67) (3. we assume ID . D1 (3.68) if = VT ln IID1 + VT ln 1 + ID : I S For small-signal operation.66) (3.

(3. 10 The function expa sin bt can be approximated by a Taylor expansion or Bessel functions. Figure 3. distinguishing between the cause and the effect. .24 illustrates the two cases.69) which is the same as Eq. (3. D1 ID1 and note that ln1 + VD = VT ID .49). Thus. ID1 1.

a 100-mV change in Vad yields an 11. Exercise Repeat the above example by taking the derivative of the diode voltage equation with respect to ID .17) and (3.71) That is. we can construct the small-signal model shown in Fig.25.21) if the value of R1 in Fig.5-mV change in Vout .17. we now revisit Example 3.) We can thus write: R1 Solution v ad rd rd rd v out Figure 3.17 with the aid of a small-signal model for the diodes. In Example 3.25 Small-signal model of adaptor.17.21 Repeat part (b) of Example 3. 3 Diode Models and Circuits ∆ID ∆V D D1 (a) ∆ID = = ∆V D rd ∆ID I D1 VT D1 ∆V D (b) ∆V D = ∆ I D r d = ∆V D ∆I D VT I D1 Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 3. . (As mentioned earlier.cls v. 3. The small-signal analysis therefore offers reasonable accuracy while requiring much less computational effort.19 is changed to 200 . 2006] June 30. Since each diode carries ID1 = 6 mA with an adaptor voltage of 3 V and VD1 = 800 mV.24 Change in diode current (voltage) due to a change in voltage (current). solution of nonlinear diode equations predicted an 11-mV change in Vout . r vout = R 3+d3r vad 1 d = 11:5 mV: (3. 3. With our understanding of small-signal operation. the voltages shown in this model denote small changes.70) (3. Exercise Repeat Examples (3. 2007 at 13:42 86 (1) 86 Chap. where vad = 100 mV and rd = 26 mV=6 mA = 4:33 .

17 and 3.5 mA and since this change is much less than the bias current (6 mA). . 2007 at 13:42 87 (1) Sec.22 In Examples 3. 2006] June 30.72) (3. A good circuit designer analyzes and understands the circuit before giving it to the computer for a more accurate analysis. A bad circuit designer.5 mA V ad Vout Cellphone Figure 3. but the intuition gained by hand analysis of a circuit proves invaluable in understanding fundamental limitations and various trade-offs that eventually lead to a compromise in the design.cls v. the reader may wonder if the smallsignal model is really necessary. as shown in Fig. (2) develop the small-signal model for each diode (i..26.5 mA11 and determine Vout . (3) replace each diode with its small-signal model and compute the effect of the input change.4 Large-Signal and Small-Signal Operation 87 Considering the power of today’s computer software tools. we write the change in the output voltage as: Vout = ID 3rd = 0:5 mA3 4:33 = 6:5 mV: (3.73) (3. the current drawn by the cellphone is neglected. Solution Since the current ﬂowing through the diodes decreases by 0. ~6 mA R 1 = 100 Ω 0.74) Exercise Repeat the above example if R1 is reduced to 80 . 3. Now suppose. Example 3. 11 A cellphone in reality draws a much higher current. on the other hand. the analysis of circuits containing diodes (and other nonlinear devices such as transistors) proceeds in three steps: (1) determine—perhaps with the aid of the constant-voltage model— the initial values of voltages and currents (before an input change is applied). Indeed.26 Adaptor feeding a cellphone.21. 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the load pulls a current of 0.e. In summary. calculate rd ). allows the computer to think for him/her. we utilize sophisticated simulation tools in the design of integrated circuits today.

29. As illustrated in Fig. In particular.28 Simple rectiﬁer.on V in V out Figure 3.on .29 Rectiﬁcation of positive cycles. Depicted in Fig. D1 remains on for negative values of Vin . 3.on . at which point D1 turns on and Vout = Vin . A brief outline is shown below. 2007 at 13:42 88 (1) 88 Chap. D1 V D. the resulting output reveals that this circuit is also a rectiﬁer. D1 V in R1 Vout V out (a) (b) V in t Figure 3. 3 Diode Models and Circuits 3.29(a) is also a rectiﬁer.28. 3. the circuit still operates as a rectiﬁer but produces a slightly lower dc level. For Vin VD. 3. speciﬁcally. . 3. D1 carries a small leakage current. we no longer assume D1 is ideal. Vout remains equal to zero until Vin exceeds VD. VD. for Vin . but the effect is negligible. but it blocks the positive cycles.27 Applications of diodes.on . 2006] June 30.5 Applications of Diodes The remainder of this chapter deals with circuit applications of diodes. Half−Wave and Full−Wave rectifiers Limiting Circuits Voltage Doublers Level Shifters and Switches Figure 3. but use a constant-voltage model.10(b) and study it more closely.23 Prove that the circuit shown in Fig. allowing R2 to maintain Vout = 0. 3. Example 3. Thus. D1 turns off.VD. As Vin exceeds .on .on . 12 If Vin 0.1 Half-Wave and Full-Wave Rectiﬁers Half-Wave Rectiﬁer Let us return to the rectiﬁer circuit of Fig.on V in R1 Vout t V D.cls v.VD.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In this case. Solution Exercise Plot the output if D1 is an ideal diode. D1 is off12 and Vout = 0.5.

For this reason. we note that at t = t3 . After t = t1 . VD1 . which is impossible. At t = t2 . 3. The operation of this circuit is quite different from that of the above rectiﬁer.on . Fortunately. VD. Vout .30(a). 3. Assuming a constant-voltage model for D1 in forward bias. At t t2 . We must therefore attempt to create a constant output. Assuming an ideal diode model. Vin = Vp . Here.on t1 t2 t3 t4 t5 t Continuing our analysis. As Vin rises from zero. Does Vout change after t = t1 ? Let us consider t = t4 as a potentially interesting point.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 3.on .” the circuit of Fig. (a) Repeat the above analysis. As Vin begins to fall.30(b)].Vp . Using the plots in Fig. Vout reaches a peak value of Vp .on . This is because if Vout were to fall.on = Vout . VD. Vin = . 2007 at 13:42 89 (1) Sec. VD.13 The diode therefore turns off after t1 .on indeﬁnitely. D1 is off until Vin VD. In other words.on across the diode. Interestingly. What happens as Vin passes its peak value? At t = t1 . Vin = 2Vp . 3.31(b).on. 3. at which point D1 begins to act as a battery and Vout = Vin . as a function of time.e.31(a). 2006] June 30. V out V D. but Vout exhibits no tendency to change because the situation is identical to that at t = t1 ..30 (a) Diode-capacitor circuit. the diode sustains a zero voltage difference. turning D1 off. applying a maximum reverse bias of Vout . Vout remains equal to Vp . VD. Vin just exceeds Vout but still cannot turn D1 on. we begin with a zero initial condition across C1 and study the behavior of the circuit [Fig. (b) Plot the voltage across D1 . (b) The voltage across the diode is VD1 = Vin . then C1 would need to be discharged by a current ﬂowing from its top plate through the cathode of D1 . D1 turns on as Vin exceeds zero and Vout = Vin . (b) input and output waveforms.on V in D1 V in C1 Vout Maximum Reverse Voltage (a) (b) Figure 3. we readily arrive at the waveform in Fig. Figure 3. Unlike a battery. Vp V p − V D.cls v. Vout must remain constant. a simple modiﬁcation solves the problem. and D1 is on. As depicted in Fig. 3. VD.3(c) proves useful here. 3.28 does not produce a useful output. we have Vin = Vp and Vout = Vp . (a) With a zero initial condition across C1 . the resistor is replaced with a capacitor.5 Applications of Diodes 89 Called a “half-wave rectiﬁer.24 Solution . Vin Vout and the diode experiences a negative voltage. Thus. i.31(a) shows the input and output waveforms. Vin = Vp = Vout + VD.on . the rectiﬁer generates an output that varies considerably with time and cannot supply power to electronic devices. VD. 3. Vin falls below Vout . VD1 is similar to Vin but with the 13 The water pipe analogy in Fig. At t = t5 . diodes used in rectiﬁers must withstand a reverse voltage of approximately 2Vp with no breakdown.

Determine the average current drawn from the batteries or the adapter. we consider a more realistic application where this circuit must provide a current to a load. we have I 7:58 A.31 (a) Input and output waveforms of the circuit in Fig.5. then RL = V=I = 0:436 . 2007 at 13:42 90 (1) 90 V out Chap.4). If the laptop is modeled by a resistor.30(a) achieves the properties required of an “ac-dc converter.3 V. 2006] June 30. Example 3. 3. 3 Diode Models and Circuits t1 V in (a) t t1 t V D1 −2 V p (b) Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3. Solution Exercise What power dissipation does a 1. (b) voltage across the diode. The circuit of Fig. RL .30 with an ideal diode. . average value shifted from zero to doublers (Section 3. Since P = V I .25 A laptop computer consumes an average power of 25 W with a supply voltage of 3.14 But how is the value of C1 chosen? To answer this question.” generating a constant output equal to the peak value of the input sinusoid.” . We will exploit this result in the design of voltage Exercise Repeat the above example if the terminals of the diode are swapped.cls v.load represent for such a supply voltage? 14 This circuit is also called a “peak detector.Vp .

Figure 3. Vin exceeds Vout by VD. C1 varies from very large values to very small C1 is very large. Example 3. 2007 at 13:42 91 (1) Sec.on . Vin and Vout become equal and slightly later.on = Vp . VD. From the waveforms in Fig. The output voltage continues to decrease while Vin goes through a negative excursion and returns to positive values.33 illustrates several cases. 3. If V in V out Very Small C 1 Large C1 Small C1 Solution t Figure 3. since changes in Vout are undesirable. However. We must therefore repeat our analysis with RL present. Hereafter. so does Vout because RL provides a discharge path for C1 . the circuit approaches that in Fig. Conversely. Exercise Repeat the above example for different values of RL with C1 constant. (b) input and output waveforms.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 3.cls v. t = t2 . With such a choice of C1 . 3. Vout falls slowly and D1 remains reverse biased. 2006] June 30. the current drawn by RL when D1 is off creates only a small change in Vout . if C1 is very small.on V in D1 V in t1 C1 RL Vout t3 t2 t V out VR (a) (b) Figure 3.32(b). the load can be represented by a simple resistor in some cases [Fig. we recognize that Vout behaves as before until t = t1 .on . C1 must be so large that the current drawn by RL does not reduce Vout signiﬁcantly. C1 is called the “smoothing” or “ﬁlter” capacitor. The resulting variation in Vout is called the “ripple. VD. thereby turning D1 on and forcing Vout = Vin . the circuit behaves as in the ﬁrst cycle. still exhibiting a value of Vin .5 Applications of Diodes 91 As suggested by the above example.on if the diode voltage is assumed relatively constant. at t = t3 .32 as values. exhibiting large variations in Vout .” Also. . 3. Of course. Vp V p − V D. 3.32(a)].26 Sketch the output waveform of Fig.28. as Vin begins to fall after t = t1 . VD. At some point.32 (a) Rectiﬁer driving a resistive load.33 Output waveform of rectiﬁer for different values of smoothing capacitor.

the discharge of C1 through RL can be expressed as: V p − V D.34). 2006] June 30. VD.on at t = t1 . VD. Since Vout = Vp .on .76) (3. Vp . thus. the value of C1 is chosen large enough to yield an acceptable ripple.on 1 . noting that exp. 3 Diode Models and Circuits Ripple Amplitude In typical applications. 3. (b) t Vout t = Vp . 3.C 0 t t3 . in Fig. VD. 1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.32(b) must remain below 5 to 10% of the input peak voltage.34 Ripple at output of a rectiﬁer. t1 . If the maximum current drawn by the load is known. To ensure a small ripple. for 1. greater than t3 .75) RL C1 must be much (3.on D1 V in C1 RL Vout Vp V in t1 t3 t4 t2 t V out VR (a) Figure 3. R tC L 1 t Vp .on exp R.on C : RL 1 . 2007 at 13:42 92 (1) 92 Chap. the (peak-to-peak) amplitude of the ripple. we must compute VR analytically (Fig. VD. VR .77) Vout t Vp . (3.cls v. VD. To this end. L 1 where we have chosen t1 = 0 for simplicity.

VD.on .on =RL discharges C1 .on Tin RL C1 p VR . L 1 fin 15 Recall that (3. a falling ramp—as if a constant current equal to Vp .15 This result should not come as a surprise because the nearly constant voltage across RL results in a relatively constant current equal to Vp . T .79) (3. t3 denotes the time during which D1 is on. . t1 = Tin . we write t3 . we can assume T Tin and hence VR Vp .CVD. where T = t4 . The peak-to-peak amplitude of the ripple is equal to the amount of discharge at t = t3 . Thus. VD. then the diode turns on for only a brief period. I = CdV=dt and hence dV = I=C dt. VD. VD. The ﬁrst term on the right hand side represents the initial condition across C1 and the second term.on =RL . t3 is equal to the input period. . Tin .80) This section can be skipped in a ﬁrst reading.on Tin C T : R L 1 (3.78) Recognizing that if C1 discharges by a small amount. Since t4 . VR = Vp .

A halfwave rectiﬁer follows the transformer to supply the power to the laptop computer of Example 3. the current drawn by the load is known. VD.on Tin VR RL = 1:417 F: This is a very large value.84) . Assume VD. We have Vp Solution = 4:5 V.on =RL . and cost of the adaptor may dictate a much greater ripple. weight. Exercise Repeat the above example for 220-V. 50-Hz line voltage. Assuming VD. For a given junction doping proﬁle and geometry. and (2) the current supplied to RL . 2007 at 13:42 93 (1) Sec. we note that the point at which D1 turns on is given by Vin t1 = Vp . thereby demanding that the circuit following the rectiﬁer tolerate such a large. RL = 0:436 .5 V. Vp sin !in t1 = Vp . In fact. periodic variation. and cost of the capacitor. We recognize from Fig. approximately equal to Vp . 0. = Tin1.1 V.on = 0:8 V. e. The peak diode current therefore occurs when the ﬁrst component reaches a maximum. VR . 3. Thus. assuming the transformer still produces a peak-to-peak swing of 9 V. Determine the minimum value of the ﬁlter capacitor that maintains the ripple below 0. VD. weight..on Vp for simplicity. and Tin = 16:7 ms.27 A transformer converts the 110-V.cls v.82) C1 = Vp . that the diode current in forward bias consists of two components: (1) the transient current drawn by C1 . Example 3. (3.e. Thus.25.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. i. limitations on size.g. (3..80) as the load current. 3. the power dissipated in the diode (= VD ID ) may raise the junction temperature so much as to damage the device. Repeating the above analysis with the load represented by a constant current source or simply viewing Vp .83) Diode Peak Current We noted in Fig. Which mains frequency gives a more desirable choice of C1 ? In many cases. Another important parameter of the diode is the maximum forward bias current that it must tolerate. VD. VR . 2006] June 30. 3. for Vin t = Vp sin !in t. we can write VR = CIL : f 1 in (3. The designer must trade the ripple amplitude with the size. C1 dVout =dt. if the current exceeds a certain limit. at the point D1 turns on because the slope of the output waveform is maximum. This section can be skipped in a ﬁrst reading. (3.81) (3.30(b) that the diode must exhibit a reverse breakdown voltage of at least 2 Vp . IL . 60-Hz line voltage to a peak-to-peak swing of 9 V.on =RL in Eq.35.5 Applications of Diodes 93 where fin .

cls v. VR + Rp Vp L s 2 V V = C1 !in Vp 2V R . obtaining the diode current as (3. 2006] June 30. 1 . and hence sin !in t1 = 1 . 2007 at 13:42 94 (1) 94 Chap.88) 2 V Ip = C1 !in Vp 1 . 3 Diode Models and Circuits D1 V in C1 RL V out Vp − VR V in Vout Vp t1 t Figure 3.86) (3.35 Rectiﬁer circuit for calculation of ID . VR : V p With VD. from (3.87) V Ip = C1 !in Vp cos !in t1 + Rp . reduces to (3. VR + Rp : Vp2 p L Since VR s .85) V ID1 t = C1 dVout + Rp dt This current reaches a peak at t = t1 : V = C1 !in Vp cos !in t + Rp : L L (3. L which. we also have Vout t Vin t.on neglected.85).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

Ip = 517 A: (3.91) V V Rp RLC1 !in 2V R + 1 : L p Determine the peak diode current in Example 3. we neglect the second term under the square root: V V Ip C1 !in Vp 2V R + Rp p L s (3.28 Solution 0 and C1 = 1:417 F. Thus. !in = 260 Hz.27 assuming VD. RL = 0:436 .92) Example 3. = 4:5 V.89) (3. and VR = 0:1 V. (3.on We have Vp s ! (3.93) .90) Vp .

2007 at 13:42 95 (1) Sec.5 Applications of Diodes 95 This value is extremely large. we also compose that in Fig. reducing the circuit to that shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if Vin 0. Depicted in Fig. The circuit therefore suffers from a large ripple in the presence of a heavy load (a high current). Note the polarity of Vout in the two diagrams. Full-Wave Rectiﬁer The half-wave rectiﬁer studied above blocks the negative half cycles of the input.e. Thus. yielding a zero current through RL and hence Vout = 0.36 (a) Input and output waveforms and (b) input/output characteristic of a full-wave rectiﬁer. but with the negative half cycles inverted (i. 3.36(a). if Vin 0. we can now combine the topologies of Figs. but.Vin . 3.37(f)]. where one blocks negative half cycles and the other.37(e) for simplicity. 3. both diodes are off. This conﬁguration is usually drawn as in Fig..38(c) and .38(b) and called a “bridge rectiﬁer.. 3. Shown in Fig. 3. 3. We begin with the assumption that the diodes are ideal to simplify the task of circuit synthesis.cls v. 3. Figure 3. positive half cycles. y (t ) t V in t (a) Vout Vout t x (t ) t (b) Figure 3. We ﬁrst implement a circuit that performs this function [called a “full-wave rectiﬁer” (FWR)] and next prove that it indeed exhibits a smaller ripple. 3. 3.37(c): we must ﬁrst design a half-wave rectiﬁer that inverts.. 3.37(f). If Vin 0. Here. i. unfortunately. Illustrated in Fig. 3.38(b). Vout = 0 for Vin 0 and Vout = Vin for Vin 0. i. It is possible to reduce the ripple voltage by a factor of two through a simple modiﬁcation. both D2 and D1 are on and Vout = .37(b). the problem is reduced to that illustrated in Fig.37(d) is such a topology. 2006] June 30. D2 and D1 are on and D3 and D4 are off. which can also be redrawn as in Fig.e. 3.e. Conversely.” Let us summarize our thoughts with the aid of the circuit shown in Fig. Exercise Repeat the above example if C1 = 1000 F. the idea is to pass both positive and negative half cycles to the output. In analogy with this circuit. Can we combine these circuits to realize a full-wave rectiﬁer? We may attempt the circuit in Fig. Note that the current drawn by C1 is much greater than that ﬂowing through RL . allowing the ﬁlter capacitor to be discharged by the load for almost the entire period. 3. With the foregoing developments.1).38(a). 3. the output contains both positive and negative half cycles.37(a). 3.37(d)] and the positive half cycles through D3 and D4 with no sign reversal [as in Fig. the resulting circuit passes the negative half cycles through D1 and D2 with a sign reversal [as in Fig. multiplied by .37(d) and (f) to form a full-wave rectiﬁer. Consider the two half-wave rectiﬁers shown in Fig. which simply blocks the negative input half cycles. no rectiﬁcation is performed because the negative half cycles are not inverted.36(b) depicts the desired input/output characteristic of the full-wave rectiﬁer.

the half-wave rectiﬁer in Fig. D2 Vin RL Vout Vin D4 (a) (b) Vout RL D3 D1 D2 Vin D4 (c) D3 Vin D1 D2 D3 D4 D1 (d) Figure 3.on . How do these results change if the diodes are not ideal? Figures 3. 3 Diode Models and Circuits RL (a) (b) D2 D2 ? D3 Vout Vin RL D4 Vout RL Vin D1 RL Vout Vin RL D1 (c) (d) (e) (f) Figure 3. The output remains equal to zero for jVin j Solution 2VD.Vin . (e) path for negative half cycles.28 produces Vout = Vin . yielding Vout = . and Vout = Vin . the bridge is simpliﬁed as shown in Fig. (d) realization of (c).38(c) and (d) reveal that the circuit introduces two forward-biased diodes in series with RL . On the other hand. yielding Vout = . (b) simpliﬁed diagram. The drop of 2VD. (c) rectiﬁcation and inversion. 3.on may pose difﬁculty if Vp is relatively small and the output voltage must be close to Vp . Example 3.on .38(d). By contrast.38 (a) Full-wave rectiﬁer.Vin .on and “tracks” the input for jVin j VD. if Vin 0. plot the input/output characteristic of a full-wave rectiﬁer. 2006] June 30.cls v. 2007 at 13:42 96 (1) 96 D1 RL D2 RL Chap. (b) no rectiﬁcation.on for Vin 0. 2VD.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.37 (a) Rectiﬁcation of each half cycle. 3. (c) current path for negative input. (d) current path for positive input. (f) path for positive half cycles. VD.29 Assuming a constant-voltage model for the diodes.

(b) equivalent circuit. 2007 at 13:42 97 (1) Sec.5 Applications of Diodes 97 with a slope of unity.40(a)].on +2V D.39 Input/output characteristic of full-wave rectiﬁer with nonideal diodes.on D1 RL C 1 Vout D3 (b) Figure 3. (3.on ? We now redraw the bridge once more and add the smoothing capacitor to arrive at the complete design [Fig.on due to the bridge.39 plots the result. R L 1 in where the numerator reﬂects the drop of 2VD. 3. Vout Vout V in t −2 V D.94) .CVf .on t Figure 3.cls v. 2006] June 30.80): V in t D4 D1 RL C 1 Vout V out t (a) D2 Vin D3 A D2 Vin B D4 V D. 3. the ripple is approximately equal to half of that in Eq. Exercise What is the slope of the characteristic for jVin j 2VD.40 (a) Ripple in full-wave rectiﬁer. Figure 3. Since the capacitor discharge occurs for about half of the input cycle.on VR 2 Vp . (3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1 2 D.

The results of our study are summarized in Fig.Vin + 2VD.41 Currents carried by diodes in a full-wave rectiﬁer. As illustrated in Fig. In Problem 38. the full-wave rectiﬁer offers another important advantage: the maximum reverse bias voltage across each diode is approximately equal to Vp rather than 2Vp . 3. 3. whereas the latter does not.on and Vout = Vin . A similar argument applies to the other diodes.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Another point of contrast between half-wave and full-wave rectiﬁers is that the former has a common terminal between the input and output ports (node G in Fig.40(b). we have Vout = . While using two more diodes. 2VD. Thus.28). . when Vin is near Vp and D3 is on. the voltage across D2 .on RL Figure 3. VD.on for Vin +2VD.on + Vout = Vp . From Figs.on for Vin .41. the diode currents appear as shown in Fig. Exercise Sketch the power consumed in each diode as a function of time. VAB .16 16 The four diodes are typically manufactured in a single package having four terminals. well justifying their use in adaptors and chargers. 3.on. 3 Diode Models and Circuits In addition to a lower ripple. full-wave rectiﬁers exhibit a lower ripple and require only half the diode breakdown voltage. In each half cycle. Assume no smoothing capacitor is connected to the output. Example 3.on .on I D1 = I D2 RL t I D3 = I D4 t − Vp − 2V D. is simply equal to VD.38(c) and (d).2VD. 2006] June 30. 2007 at 13:42 98 (1) 98 Chap. we study the effect of shorting the input and output grounds of a fullwave rectiﬁer and conclude that it disrupts the operation of the circuit.30 Plot the currents carried by each diode in a bridge rectiﬁer as a function of time for a sinusoidal input. 3.42. two of the diodes carry a current equal to Vout =RL and the other two remain off. Solution V in t Vp − 2V D.cls v. 3.

3.42 Summary of rectiﬁer circuits.83) for a full-wave rectiﬁer gives VR = 2CILf For VR W = 32:6 V 2C1f : 1 in 1 in (3. 2VD.96) Thus. 2007 at 13:42 99 (1) Sec.97) (3.on 5 :2 V : (3.95) (3. 2006] June 30.cls v.6 V and a ripple of 0.99) Exercise If cost and size limitations impose a maximum value of 1000 F on the smoothing capacitor.on .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the transformer preceding the rectiﬁer must step the line voltage (110 Vrms or 220 Vrms ) down to a peak value of 5. we have Vin. we determine the minimum value of the smoothing capacitor that ensures VR 0:2 V.98) = 0:2 V and fin = 60 Hz. what is the maximum allowable power drain in the above example? . C1 = 23. Solution We begin with the required input swing.on Vout V in t V in V out t Reverse Bias (a) 2 Vp Reverse Bias (b) Vp Figure 3. Next. 000 F: The diodes must withstand a reverse bias voltage of 5.31 Design a full-wave rectiﬁer to deliver an average power of 2 W to a cellphone with a voltage of 3. Example 3. (3. (3.p = 3:6 V + 2VD.2 V.2 V.5 Applications of Diodes 99 D1 V in C1 RL V p − V D. Rewriting Eq. Since the output voltage is approximately equal to Vp .on Vin D2 D3 D4 D1 RL C1 Vp − 2V D.2 V.

rD . 3 Diode Models and Circuits Example 3. This can be seen from the small-signal model of Fig.17 provides a voltage of 2. the output voltage varies with the load current.44(b): This section can be skipped in a ﬁrst reading. For such signal levels. For example. Operating in the reverse breakdown region. the ﬁnite output impedance of the transformer leads to changes in Vout if the current drawn by the load varies.5. resulting in a zero output. Furthermore.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.43 as a more versatile adaptor having a nominal output of 3VD.32 A radio frequency signal received and ampliﬁed by a cellphone exhibits a peak swing of 10 mV. We wish to generate a dc voltage representing the signal amplitude [Eq. . Exercise What if a constant voltage of 0. For these reasons. in the range of 1 to 10 . Diode Bridge R1 Vin C1 Load Figure 3.44(a) shows another regulator circuit employing a Zener diode. 3.43 Voltage regulator block diagram. 3. 2006] June 30. as studied in Example 3.g.4 V.. the circuit of Fig.cls v. Moreover. We may therefore arrive at the circuit shown in Fig. thus providing a relatively constant output despite input variations if rD R1 . a cellphone). it is not. Owing to its small amplitude. Unfortunately. Figure 3. 2007 at 13:42 100 (1) 100 Chap. a subject studied in Chapter 8. the 120-Hz ripple can be heard from the speakers. the peak amplitude produced by the transformer and hence the dc output vary considerably.8 V is added to the desired signal? 3.on 2:4 V. (3.2 Voltage Regulation The adaptor circuit studied above generally proves inadequate. We have already encountered a voltage regulator without calling it such: the circuit studied in Example 3.22. the signal cannot turn actual diodes on and off. “precision rectiﬁcation” is necessary. Is it possible to use the half-wave or full-wave rectiﬁers studied above? Solution No. D1 exhibits a small-signal resistance. possibly exceeding the maximum level that can be tolerated by the load (e.40(a) is often followed by a “voltage regulator” so as to provide a constant output. Due to the signiﬁcant variation of the line voltage. the ripple may become seriously objectionable in many applications. if the adaptor supplies power to a stereo. incurring only an 11-mV change in the output for a 100-mV variation in the input.8)]. 3.

In the circuit of Fig. (3. 2007 at 13:42 101 (1) Sec. Assuming VD. 2006] June 30.45(a). We ﬁrst determine the bias current of D1 and hence its small-signal resistance: Solution ID1 = Vin . Vin has a nominal value of 5 V.104) . (c) load regulation.on . 3. (b) small-signal equivalent.cls v.45 Circuit using two diodes. if rD = 5 and R1 = 1 k . then changes in Vin are attenuated by approximately a factor of 200 as they appear in Vout .102) rD1 = IVT D1 = 1:73 : (3.on 0:8 V for D1 .5 Applications of Diodes R1 Vout D1 R1 v out rd 101 V in v in (a) (b) Figure 3.7 V and a small-signal resistance of 5 . and D2 has a reverse breakdown of 2.on VDz v in R1 v out r d1 r d2 v in R1 r d1 r d2 v out iL Example 3. namely.33 Constant (a) (b) (c) Figure 3. and the latter by “load regulation. Our brief study of regulators thus far reveals two important aspects of their design: the stability of the output with respect to input variations. V in R1 Vout D1 D2 VD.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.100) For example. The former is quantiﬁed by “line regulation. R1 = 100 . VD2 R1 = 15 mA: Thus.” deﬁned as Vout =IL . D vout = r r+ R vin : D 1 (3.103) (3. VD. (b) small-signal equivalent of (a).43. poor stability if the load current varies signiﬁcantly. The Zener regulator nonetheless shares the same issue with the circuit of Fig.44 (a) Regulator using a Zener diode. 3. determine the line and load regulation of the circuit.” deﬁned as Vout =Vin . 3. and the stability of the output with respect to load current variations.101) (3.

Figure 3. we have vout rD1 + rD2 jjR1 = . 3. Exercise Repeat the above example for R1 = 50 and compare the results. 3.47). As the distance decreases from kilometers to hundreds of meters. 3. 3. 3. This behavior must hold for both positive and negative inputs. The nonlinear input-output characteristic suggests that one or more diodes must turn on or off as Vin approaches VL .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As illustrated in Fig.cls v.106) For load regulation. the circuit must simply pass the input to the output. we compute the line regulation as vout = rD1 + rD2 vin rD1 + rD2 + R1 = 0:063: (3.iL: That is. How should a limiting circuit behave? For small input levels. Vout = Vin . In .48(b).31-mV change in the output voltage.5. and as the input level exceeds a “threshold” or “limit. 3.. (3. It is therefore desirable to “limit” the signal amplitude at a suitable point in the receiver.46 Summary of regulators.105) (3.46 summarizes the results of our study in this section.44(b).” the output must remain constant. translating to the input/output characteristic shown in Fig. we assume the input is constant and study the effect of load current variations. the signal level may become large enough to “saturate” the circuits as it travels through the receiver chain.109) This value indicates that a 1-mA change in the load current results in a 6. a signal applied to the input emerges at the output with its peak values “clipped” at VL . 2007 at 13:42 102 (1) 102 Chap.3 Limiting Circuits Consider the signal received by a cellphone as the user comes closer to a base station (Fig. e. 3 Diode Models and Circuits From the small-signal model of Fig.108) (3.g. Using the small-signal circuit shown in Fig.48(a). We now implement a circuit that exhibits the above behavior. D1 Vin C1 Load Vin Load Vin Load Figure 3. 2006] June 30.45(c) (where vin = 0 to represent a constant input).107) vout = r + r jjR D1 D2 1 iL = 6:31 : (3.

Finally. fact. two “antiparallel” diodes can create a characteristic that limits at VD. A signal must be limited at 100 mV. First.on .52(a) illustrates how the voltage sources must shift the break points. 3. the negative values of Vin must also experience limiting. Assuming VD. We reexamine the former assuming a more realistic diode.48 (a) Input/output characteristic of a limiting circuit. the voltage source in series with D1 must be negative and equal to 700 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the above topology must satisfy two other conditions. the constant-voltage model. Example 3.49(a). must be an arbitrary voltage and not necessarily equal to VD. Vout is equal to Vin for Vin VD.on and equal to VD.on . 2007 at 13:42 103 (1) Sec. we have already seen simple examples in Figs. 3. then the circuit limits at Vin = .47 Signals received (a) far from or (b) near a base station. respectively.on [Fig. 2006] June 30. 3. accomplishing this objective. we recognize that if the anode and cathode of D1 are swapped.51).5 Applications of Diodes 103 Base Station Receiver Base Station Receiver (a) Figure 3. the source in series with D2 must be positive and equal to 700 mV. Inspired by the circuit of Fig. inserting constant voltage sources in series with the diodes shifts the limiting points to arbitrary levels (Fig. we postulate that a constant voltage source in series with D1 shifts the limiting point.VD. where the positive half cycles of the input are clipped at 0 V and +1 V. .on . Second.50(b). 3.. 3.49(b).cls v. As illustrated in Fig. the limiting level. To serve as a more general limiting circuit. 3. e. respectively. as shown in Fig. the resulting circuit limits at VL = VB 1 + VD. design the required limiting Solution Figure 3. Depicted in Fig.11(c). Similarly.50(a)]. Thus.52(b) shows the result. Figure 3. Since the positive limiting point must shift to the left. Note that VB 1 can be positive or negative to shift VL to higher or lower values.on thereafter.on circuit. 3. (b) Vout Vout + VL − VL + VL − VL Vout + VL − VL + VL V in V in − VL t t (a) (b) Figure 3.49(a).11(b) and (c). 3.34 = 800 mV. VL .g. 3. Beginning with the circuit of Fig. (b) response to a sinusoid.

“Voltage doublers” may serve this purpose.1:1 V. the voltage across C1 cannot change even if Vin changes because the right plate 17 Recall that VD = VT lnID =IS . but it is possible to realize a non-unity slope in the region. in the circuit of Fig.cls v.” . (b) limiter with level shift. e.49 (a) Simple limiter.on + V B1 V in Vout V D. 3 Diode Models and Circuits Vout R1 V in D1 Vout V D. we make two observations.Q.4 Voltage Doublers Electronic systems typically employ a “global” supply voltage. the design of some circuits in the system is greatly simpliﬁed if they run from a higher supply voltage. Thus. the circuits studied above actually display a nonzero slope in the limiting region (Fig. 3.. This section can be skipped in a ﬁrst reading. Second. This is because. However.109) implies that this effect is typically negligible.g. as Vin increases.VL Vin +VL. to charge one plate of a capacitor to +Q. we have thus far assumed Vout = Vin for .5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. e. (2. Exercise Before concluding this section. the 60-mV/decade rule expressed by Eq.on V in Vout V D.. First. 3.18 Before studying doublers.54(a).on t t (a) Vout R1 D1 VB1 V D.g. First. requiring that the discrete and integrated circuits operate with such a value. so does the current through the diode that is forward biased and hence the diode voltage. it is helpful to review some basic properties of capacitors.53). Vout = Vin .17 Nonetheless. Repeat the above example if the positive values of the signal must be limited at +200 mV and the negative values at . the other plate must be charged to . 3 V. 3. 6 V. 18 Voltage doublers are an example of “dc-dc converters.on + V B1 Vout V D.on V D.on + V B1 t V in t (b) Figure 3. 2006] June 30. 2007 at 13:42 104 (1) 104 Chap.

To determine the change in Vout .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.on + V B1 V D. 2006] June 30. 3. This is an important observation. Vout .on 105 Vout V in t V in D1 Vout t (a) R1 V in − V D.on Vout + V D. of C1 cannot receive or release charge (Q = CV ).on − V B2 V D.on − V B2 t Figure 3. Note that all four plates receive or release equal amounts of charge because C1 and C2 are in series.on + V D. the voltage change across C1 is equal to C2 Vout =C1 .54(b) operates as follows. 2007 at 13:42 105 (1) Sec.cls v.on − V D. the top plate of C2 equivalently holds more positive charge. resulting from Vin . we have Vin = C2 Vout + Vout : C 1 (3.on + V B1 V in Vout t V in D1 VB1 D2 VB2 Vout − V D. (b) limiter for both half cycles. Second. Since VC 1 remains constant. Adding these two voltage changes and equating the result to Vin . an input change Vin directly appears at the output. a capacitive voltage divider such as that in Fig.on − V D. 3. and hence the bottom plate absorbs negative charge from ground. If Vin becomes more positive. Having lost negative charge.on Vout V in t D1 D2 Vout t (b) Figure 3.51 General limiter and its characteristic.110) . thus requiring that the right plate absorb negative charge of the same magnitude from the top plate of C2 . Thus. we write the change in the charge on C2 as Q2 = C2 Vout .50 (a) Negative-cycle limiter. Vout R1 − V D.5 Applications of Diodes R1 Vout − V D. the left plate of C1 receives positive charge from Vin . which also holds for C1 : Q2 = Q1 .

Interestingly.53 Effect of nonideal diodes on limiting characteristic. While Vout in this circuit behaves exactly the same as VD1 in Fig. we note that as Vin exceeds zero. 3. 3. except that C1 (rather than C2 ) appears in the numerator. where the diode and the capacitors are exchanged and the voltage across D1 is labeled Vout . (b) voltage division.31: the voltage across the diode in the peak detector exhibits an average value of .52 (a) Example of a limiting circuit.2Vp (with respect to zero).54(a) is a special case of the capacitive divider with C2 = 0 and hence Vout = Vin . Assuming an ideal diode and a zero initial condition across C1 . As our ﬁrst step toward realizing a voltage doubler. Vout V in Figure 3. 3 Diode Models and Circuits Vout + V D. we redraw the circuit as shown in Fig. 2007 at 13:42 106 (1) 106 Chap.cls v. we derive the output waveform from a different perspective so as to gain more insight. 3. a peak value of . the input tends to place positive charge on the left plate of C1 and hence draw negative .55. recall the result illustrated in Fig.on −100 mV + V D. the circuit of Fig. For further investigation.on +100 mV (a) R1 D1 D2 V in V in Vout 700 mV (b) Figure 3.111) This result is similar to the voltage division expression for resistive dividers. more importantly. V C1 ∆V in V in C1 Vout ∆V in V in C1 C 2 Vout (a) (b) Figure 3.54 (a) Voltage change at one plate of a capacitor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. That is. (b) input/output characteristic. Vout = C C1 C Vin : 1+ 2 (3.30(a).Vp and. 3.

From this time.54(a). In particular. 3. The diode therefore turns off.19 As the input rises toward Vp .e. 3. as Vin varies from +Vp to . 2007 at 13:42 107 (1) Sec.56 Capacitor-diode circuit and (b) its waveforms. After t = t1 . . 3. 3. D1 turns on. forcing Vout = 0. Plot the output waveform of the circuit shown in Fig. the output goes from zero to .. charge from D1 . The output waveform is thus identical to that obtained in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. +2 V p Example 3. the output simply tracks the changes in the input while C1 sustains a constant voltage equal to Vp . 3. 19 If we assume D does not turn on. draw positive charge from the left plate and hence from D1 . Vin begins to fall and tends to discharge C1 .54(a). requiring that V out rise and D1 1 turn on. the voltage across C1 remains equal to Vin because its right plate is “pinned” at zero by D1 .31(b). reducing the circuit to that in Fig. then the circuit resembles that in Fig.55 (a) Capacitor-diode circuit and (b) its waveforms.cls v. Consequently. 2006] June 30. i.2Vp .Vp .5 Applications of Diodes t1 V out V in −Vp 107 0 t V in C1 D1 Vout V in V in t1 t −2 V p −Vp (b) (a) Figure 3.35 V out V in C1 t D1 Vout V in t2 V in V in V in (a) (b) t4 t Vp t1 Figure 3.56 if the initial condition across C1 is zero. and the cycle repeats indeﬁnitely.

As a result. In this case. C1 directly transfers the input change to the output for the entire positive half cycle. we must still analyze this circuit carefully and determine whether it indeed operates as a voltage doubler. Figure 3. at which point the direction of the current through C1 and D1 must change. and C1 = C2 . C1 is 1 V more positive than its left plate at We have thus far developed circuits that generate a periodic output with a peak value of . C1 carries a voltage equal to Vp and transfers the input change to the output. Fig.e. Thus. 3.30(a)].g. We surmise that if these circuits are followed by a peak detector [e.2Vp or +2Vp for an input sinusoid varying between . . attempting to place positive charge on the left plate of C1 and hence draw negative charge from D1 . turning D1 on and forcing Vout = 0. combining the circuit of Fig.30(a). zero initial conditions across C1 and C2 .2Vp or +2Vp may be produced. As Vin falls below zero. 2007 at 13:42 108 (1) 108 Chap. C1 V in X D1 D2 C 2 Vout V out Vp t V in Vp 2 t1 C1 V in C2 C1 V in C1 V in C2 t2 t3 t4 t5 t V in C2 C1 C 2 Vp V in C2 C1 Figure 3. D1 turns on. turning D1 off.. the diode turns off.57 Voltage doubler circuit and its waveforms. Of course. Solution Exercise Repeat the above example if the right plate of t = 0. We assume ideal diodes. reaching a peak value of +2Vp .cls v.Vp and +Vp . After t = t1 . the voltage across C1 remains equal to Vin until t = t2 . since the peak detector “loads” the ﬁrst stage when D2 turns on. 3.. the output tracks the input but with a level shift of +Vp . 3 Diode Models and Circuits As Vin rises from zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. then a constant output equal to .56 with the peak detector of Fig. i. the analysis is simpliﬁed if we begin with a negative cycle. Now. 3.57(a) exempliﬁes this concept. the input tends to push negative charge into C1 . 2006] June 30.

a change of 2Vp in Vin appears as a change equal to Vp in VX and Vout . in each input cycle. How does D2 behave in this regime? Since Vin is now rising. At t = t1 . VX tracks the change at the input. falling to zero at t = t3 . allowing C1 to charge to . As is evident from the foregoing analysis.. and each capacitor holds a constant voltage. But patience is a virtue and we must continue the transient analysis.20 Thus. reaching +Vp as Vin goes from .) As a result. As Vin begins to rise again. At this point. turning D2 on. D1 turns on again. Since the voltage across C1 is zero. the input begins to rise and tends to deposit positive charge on the left plate of C1 . raising VX and hence turning D2 on. For t t1 . both D1 and D2 are off. The reader may wonder if something is wrong here. D2 turns on at t = t5 .57. Thus. for t t1 . and vary sinusoidally but with an amplitude equal to Vp =2. (If D2 remains off. D1 turns off and D2 remains off because VX = 0 and Vout = +Vp . the voltage across C1 is zero because both Vin and Vout are equal to +Vp . 2007 at 13:42 109 (1) Sec. from t1 to t2 . Note at t = t2 . i. Vp =2. The output has now reached 3Vp =2. In other words.112) 1 Vout = Vp 1 + 1 + 4 + 2 = Vp 1 1. the output continues to rise by Vp . 3. the output change is equal to half of the input change. 3. the voltage across C1 reaches .5 Applications of Diodes 109 pinning node X to zero.. we postulate that VX also tends to increase (from zero). etc. Vout increases from +Vp to +Vp + Vp =2 as Vin goes from 0 to +Vp . D2 turns off. with the right plate of C1 ﬂoating. remain equal. VX and Vout begin from zero.Vp to 0. maintaining Vout at +Vp .Vp at t = t4 . forming a capacitive divider again. approaching a ﬁnal value of Vout = 1 Vin . then C1 simply transfers the change in Vin to node X . Thus.Vp .e. (3. D2 remains off and Vout = 0. VX = Vin . our objective was to generate an output equal to 2Vp rather than Vp . After this time.cls v. the circuit reduces to a simple capacitive divider that follows Eq. turning D1 off and yielding the circuit shown in Fig. 2 (3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2 = 2Vp : . Vp =4. 2006] June 30. What happens after t = t2 ? Since Vin begins to fall and tends to draw charge from C1 .111): because C1 = C2 . For t t2 . Now.

e. 3. From t = t1 to t = t3 . Using the diagram in Fig.58(b). I D . 1 remains off) and arrive at a conﬂicting result. D1 conducts and the peak current corresponds to the maximum slope of Vin .C1 dVin =dt. and writing the current as ID1 = .. 21 As usual. immediately after t = 0. D1 denotes the current ﬂowing from the anode to the cathode. Sketch the current through D1 in the doubler circuit as function of time.e.115) The reader is encouraged to continue the analysis for a few more cycles and verify this trend. repeating the same behavior in subsequent cycles.113) (3.. the reader is encouraged to assume otherwise (i.21 For 0 t t1 .36 Solution 20 As always. 3.114) (3.58(a). Example 3. (3. we construct the plot shown in Fig. i. the diode remains off. noting that D1 and C1 carry equal currents when D1 is forward biased.

Sustaining a relatively constant voltage in forward bias. VD. 22 The diode is drawn vertically to emphasize that Vout is lower than Vin .37 Solution To shift the level up.5 Diodes as Level Shifters and Switches In the design of electronic circuits.on across D1 . we apply the input to the cathode. we consider the circuit shown in Fig. 3. Design a circuit that shifts up the dc level of a signal by 2VD. establishing VD. Vout is simply lower than Vin by a constant amount.on . .on .g. 3 Diode Models and Circuits t4 t5 t2 t3 t V in C2 C1 C 2 Vp V in C2 C1 I D1 t1 t2 t3 t4 t Figure 3.cls v. 3. Figure 3. To alleviate this issue we modify the circuit as depicted in Fig.on .58 Diode current in a voltage doubler. we may need to shift the average level of a signal up or down because the subsequent stage (e.on . an ampliﬁer) may not operate properly with the present dc level. 2006] June 30. to obtain a shift of place two diodes in series. 2007 at 13:42 110 (1) 110 V in t1 C1 V in C2 C1 V in C1 V in C2 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Example 3.60 shows the result.59(a) as a candidate for shifting the level down by VD.22 If the current pulled by the next stage is negligible (or at least constant). However. In our ﬁrst attempt. where I1 draws a constant current. 2VD.5.59(b).. 3. a diode can be viewed as a battery and hence a device capable of shifting the signal level. Exercise Plot the current through D2 in the above example as a function of time. the diode current remains unknown and dependent on the next stage. Also. we This section can be skipped in a ﬁrst reading.

61(a) to “sample” Vin across C1 and “freeze” the value when S1 turns off. 3. the diode is forward-biased again.61(e). To resolve this issue. Vout .59 (a) Use of a diode for level shift. 3. and Vout = VX + VD2 = Vin if VD1 = VD2 . If I1 is on. That is. the diodes operate in forward bias. With both I1 and I2 on. VX = Vin . VD.e. VCC I1 Vout 2 V D. the circuit is modiﬁed as shown in Fig. Thus. where the back-to-back diodes fail to conduct for any value of Vin . .. where D2 is inserted between D1 and C1 . only if Vin . 3. so does D1 . D1 turns on for part of the cycle.on . In other words. Vout tracks Vin except for a level shift equal to VD.61(c).on (a) (b) t Figure 3. Exercise What happens if I1 is extremely small? The level shift circuit of Fig. i. 3. Now consider the case illustrated in Fig. 2007 at 13:42 111 (1) Sec. 3. For example. (b) practical implementation. and I2 provides a bias current for D2 . evidently disconnecting C1 from the input and freezing the voltage across C1 . 2006] June 30. the circuit reduces to that in Fig.on . even though I1 is off.on Vin Vin t Figure 3. VD1 . thereby isolating C1 from the input. As the input waveform completes a negative excursion and exceeds Vin1 at t = t2 .59(b) can be transformed to an electronic switch. allowing C1 to store a value equal to Vin1 . When I1 and I2 turn off. the two diodes and the two current sources form an electronic switch.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.60 Positive voltage shift by two diodes.61(d).on Vout I1 Vin Vout V D. where I1 turns off at t = t1 .on . When I1 turns off. Vout tracks Vin with no level shift. many applications employ the topology shown in Fig.61(b)].Vout remains less than VD.on Vout 2 V D. We used the term “evidently” in the last sentence because the circuit’s true behavior somewhat differs from the above description. 3. charging C1 with the input (in a manner similar to a peak detector).5 Applications of Diodes 111 Vin D1 Vin Vout D1 V D. The assumption that D1 turns off holds only if C1 draws no current from D1 . Let us replace S1 with the level shift circuit and allow I1 to be turned on and off [Fig.cls v. 3.

116) Exercise Calculate the change in the voltage at the left plate of Cj 1 (with respect to ground) in terms of . D 1 turns off.61 (a) Switched-capacitor circuit. Solution Figure 3.cls v. (c) problem of diode conduction. (a) (b) (c) t1 t2 t VCC CK Vin C1 CK I1 I1 Vout Vin C1 Vout (d) (e) Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we have Vin C j1 C j2 C1 Vout Figure 3. invoking the capacitive divider of Fig.38 Recall from Chapter 2 that diodes exhibit a junction capacitance in reverse bias. C Vout = C =2j =2C Vin : j + 1 To ensure this “feedthrough” is small. (d) more complete circuit.62 Feedthrough in the diode switch. 2006] June 30. 3 Diode Models and Circuits Vin Vin V in Vout C1 CK I1 D1 Vout C1 Vin D1 Vout I1 C1 CK Vout D 1 turns on. (e) equivalent circuit when 1 and 2 are off.54(b) and assuming Cj 1 = Cj 2 = Cj . 3. Speciﬁcally. (3. Study the effect of this capacitance on the operation of the above circuit. I I Example 3.62 shows the equivalent circuit for the case where the diodes are off. C1 must be sufﬁciently large. 2007 at 13:42 112 (1) 112 Chap. suggesting that the conduction of the input through the junction capacitances disturbs the output. (b) realization of (a) using a diode as a switch.

63. Under a high reverse bias voltage. 1 . Problems In the following problems. typically in the range of 700 to 800 mV. they leave ionized atoms behind. When an electron is freed from a covalent bond. in an n-type material. The pn junction can be considered in three modes: equilibrium. To increase the number of free carriers. The bandgap energy is the minimum energy required to dislodge an electron from its covalent bond. a constant-voltage model may be used in some cases to estimate the circuit’s response with less mathematical labor. As the carriers cross.6 Chapter Summary Silicon contains four atoms in its last orbital. and forward bias. Under forward bias. sharp gradients of carrier densities across the junction result in a high current of electrons and holes. 3. For example. i Under reverse bias. pn junctions break down. assume VD. Dp dp=dx. The electric ﬁeld in the depletion results in a built-in potential across the region equal to kT=q lnNA ND =n2 . Plot the I/V characteristic of the circuit shown in Fig. For doped or undoped semiconductors. Depending on the structure and doping levels of the device. A pn junction is a piece of semiconductor that receives n-type doping in one section and p-type doping in an adjacent section. reverse bias.on = 800 mV for the constant-voltage diode model. For example.6 Chapter Summary 113 Vin . n ND i and hence p n2 =ND . 3. “Zener” or “avalanche” breakdown may occur. and a “depletion region” is formed. a “hole” is left behind. the junction carries negligible current and operates as a capacitor. This condition is called equilibrium. semiconductors are “doped” with certain impurities. Upon formation of the pn junction.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1. the junction carries a current that is an exponential function of the applied voltage: IS expVF =VT .cls v. The capacitance itself is a function of the voltage applied across the device. np = n2 . It also contains a small number of free electrons at room temperature. 2007 at 13:42 113 (1) Sec. 2006] June 30. The drift current density is proportional to the electric ﬁeld and the mobility of the carriers and is given by Jtot = q n n + p pE . conducting a very high current. 3. Since the exponential model often makes the analysis of circuits difﬁcult. i Charge carriers move in semiconductors via two mechanisms: drift and diffusion. The electric ﬁeld created in the depletion region eventually stops the current ﬂow. The diffusion current density is proportional to the gradient of the carrier concentration and given by Jtot = q Dn dn=dx . addition of phosphorus to silicon increases the number of free electrons because phosphorus contains ﬁve electrons in its last orbital. .

1 V and VB = +1 V. . Plot IX as a function of VX for the circuit shown in Fig. Plot the input/output characteristics of the circuits depicted in Fig. 9.63 is expressed as VX = V0 cos !t. In the circuit of Fig.1 V and VB = +1 V.65 and VB = +1 V.66. plot IX and IR1 as a function of VX for two cases: VB = . plot IX as a function of time for two cases: VB = . 3. 8.cls v. If in Fig.1 V and IX R1 VX D1 Ideal VB Figure 3. 3 IX R1 D1 Ideal Diode Models and Circuits VX Figure 3. VX = V0 cos !t. Plot IX and ID1 as a function of VX for the circuit shown in Fig. 3.64. plot the current ﬂowing through the circuit as a function of time. For the circuit depicted in Fig.65.68. Assume VB = 2 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.64 4. Assume VB IX R1 VX VB D1 Ideal 0.66 7.1 V and VB = +1 V.1 V IX VX D1 Ideal VB = +1 V. R1 VB Figure 3.63 2. 2006] June 30. 5.64 for two cases: VB = . 3. 3. plot IX and IR1 as a function of VX for two cases: VB = . 3. 2007 at 13:42 114 (1) 114 Chap.67. If the input in Fig. 3. 3. 6. 3.69 using an ideal model for the diodes. I D1 Figure 3. For the circuit depicted in Fig. 3. plot IX as a function of VX for two cases: VB = .

cls v.68 R1 D1 VB (a) (b) D1 Vout V in VB V in VB R1 D1 (c) V in R1 Vout Vout D1 R1 VB (d) R1 Vout V in VB V in D1 Vout (e) Figure 3. plot the current ﬂowing through R1 as a function of Vin . 14. Repeat Problem 12 with a constant-voltage diode model.6 Chapter Summary IX R2 VX I R1 R1 D1 VB Ideal 115 Figure 3. Assume a constant-voltage diode model. Assume a constant-voltage model and a relatively large I0 . 3.71.67 IX R2 I R1 VX R1 D1 VB Ideal Figure 3. 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.69 10. plot the output of each circuit in Fig. 3. 3. 12. Assume an ideal diode model. For the circuits illustrated in Fig. 3. 9 as function of time. Plot the input/output characteristics of the circuits shown in Fig. If the input is given by Vin = V0 cos !t. plot Vout as a function of time if Iin = I0 cos !t. 18. Plot Vout as a function of Iin for the circuits shown in Fig. In the circuits of Fig. 16. Assuming the input is expressed as Vin = V0 cos !t. . Repeat Problem 9 with a constant-voltage diode model. 3. 3. Assume a constant-voltage diode model.71. Use an ideal diode model.71. plot the output of each circuit in Fig. 15. 13.70 using an ideal model for the diodes.72.70 as a function of time. plot Vout as a function of Iin for the circuits shown in Fig. 17. 3. 2007 at 13:42 115 (1) Sec. 2006] June 30. Assuming a constant-voltage diode model.

72. 3. 3.71 I in R1 D1 VB (a) Vout I in D1 R1 VB (b) Vout I in D1 VB Vout R1 (c) Figure 3.70 I in R1 D1 Vout I in R1 D1 VB (b) Vout (a) I in D1 R1 VB Vout I in D1 (d VB Vout R1 (c) Figure 3. 2007 at 13:42 116 (1) 116 R1 V in VB R1 D1 VB (a) (b) Chap. . 2006] June 30. plot Vout as a function of Iin assuming a constant-voltage model for the diodes.73. 3.cls v. Plot Vout as a function of time using a constant-voltage diode model.72 19.74 assuming a constantvoltage model. Assume a constant-voltage diode model.72 as a function of Iin . 20. 3 Diode Models and Circuits D1 VB D1 Vout V in Vout V in R1 Vout (c) VB R1 D1 (d) D1 R1 VB (e) V in Vout V in Vout Figure 3. For the circuits shown in Fig. Assume a constant-voltage diode model. 3. 22. where I0 is relatively large. assume Iin = I0 cos !t. In the circuits depicted in Fig. Plot the input/output characteristic of the circuits illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Plot the current ﬂowing through R1 in the circuits of Fig. 21. Plot the current ﬂowing through R1 as a function of Iin for the circuits of Fig. 23. 3.73.

cls v. 28. . Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig.77 assuming a constantvoltage model and VB = 2 V. Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume constant-voltage diode model. 3.73 D1 R1 R2 D1 R1 Vout V in R2 Vout V in (a) (b) Figure 3.76 assuming a constantvoltage model. 29.75. 27.6 Chapter Summary 117 D1 I in R1 D2 (a) Vout I in R1 D1 (b) D2 Vout I in R1 D1 (c) D2 Vout I in R1 D1 D2 Vout I in R1 D1 D2 D1 Vout I in D2 R1 (f) Vout (d) (e) D1 I in D2 R1 (g) D1 Vout I in D2 R1 (h) Vout Figure 3.74 24. Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig. 25. 3. 2006] June 30. 26.74. Plot the input/output characteristic of the circuits illustrated in Fig. 2007 at 13:42 117 (1) Sec. 3. Assume constant-voltage diode model.76.75 assuming a constantvoltage model. 3. Plot the input/output characteristic of the circuits illustrated in Fig. Assume constant-voltage diode model. Plot the input/output characteristic of the circuits illustrated in Fig. 3. 3. 3.

31. 3.1 mA in the circuits of Fig. For a 1000-F smoothing capacitor.76 30.on 800 mV for each diode.5 V.80 for an initial condition of +0:5 V across C1 . 3. 35. Repeat Problem 34 for the circuit shown in Fig.81.load with a peak voltage of 3.77.cls v. 2006] June 30. Suppose the rectiﬁer of Fig. 3. Assume constant-voltage diode model. 36. 3 D 1 VB Vout V in R1 Diode Models and Circuits Vout R2 (b) D1 V in R1 VB Vout R2 (c) R1 V in D1 VB Vout R2 (d) Figure 3. 32. 3. Assuming Vin = Vp sin !t. . plot the output waveform of the circuit depicted in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.32 drives a 100. calculate the ripple amplitude if the frequency is 60 Hz. 33. 3. In Problem 32. Beginning with VD.75 V in D1 R1 Vout D2 R2 V in D1 R1 Vout D2 R2 (a) (b) D1 V in R1 D2 R2 Vout V in D1 D2 R1 Vout R2 (d) D1 V in R1 D2 Vout R2 (e) (c) Figure 3. 3. determine the change in the current ﬂowing through the 1-k resistor in each circuit. calculate the change in Vout if Iin changes from 3 mA to 3. 2007 at 13:42 118 (1) 118 D1 V in R1 R2 VB (a) Chap. 34. determine the change in Vout if Vin changes from +2:4 V to +2:5 V for the circuits shown in Fig.on 800 mV for each diode.78. Plot the currents ﬂowing through R1 and D1 as a function of Vin for the circuits of Fig. Beginning with VD. Assume Vp = 5 V.79.

cls v. Assume the input and output grounds in a full-wave rectiﬁer are shorted together.6 Chapter Summary R1 V in D1 VB D2 R2 (a) (b) 119 D1 Vout V in D1 VB R2 R1 Vout R1 V in D1 R2 D2 VB (c) (d) Vout V in D1 R1 Vout D2 VB R2 Figure 3. compute the minimum required smoothing capacitor.38(b) as a function of time if Vin = V0 cos !t. 38. determine the ripple amplitude with a 1000-F smoothing capacitor and a load resistance of 30 .5 A with a maximum ripple of 300 mV. 41. 2007 at 13:42 119 (1) Sec.38(b) are shorted together. Explain what happens.on = 800 mV. A 3-V adaptor using a half-wave rectiﬁer must supply a current of 0. 3. Plot the input-output characteristic assuming an ideal diode model and explaining why the circuit does not operate as a full-wave rectiﬁer.78 37.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 40.82. For a frequency of 60 Hz. 42. 2006] June 30. 3. Assuming VD.on .77 V in D1 Vout R 1 = 1 kΩ V in D1 Vout R 1 = 1 kΩ D2 (a) (b) V in D1 R1 1 kΩ Vout D2 V in R1 1 kΩ R2 (d) Vout 2kΩ D2 (c) Figure 3. Plot the voltage across each diode in Fig. a student mistakenly has swapped the terminals of D3 as depicted in Fig. where V0 = 3 V and ! = 2 60 Hz. Assume a constant-voltage diode model and VD VD. Suppose the negative terminals of Vin and Vout in Fig. 3. 3. 39. . Draw the output waveform with and without the load capacitor and explain why the circuit does not operate as a rectiﬁer. While constructing a full-wave rectiﬁer. A full-wave rectiﬁer is driven by a sinusoidal input Vin = V0 cos !t.

R1 = 1000 . (a) Assuming R1 carries a relatively constant current and VD.79 V in D1 Vout C1 0.82 43. 3 Diode Models and Circuits D1 Vout I in R 1 = 1 kΩ D2 (a) (b) D1 I in R1 1 kΩ R1 Vout D2 I in 1 kΩ R2 (d) Vout 2kΩ D2 (c) Figure 3. what is the change in the total voltage across the three diodes? Assume R1 is much greater than 3rd . If the load current increases to 21 mA. . we estimate the ripple seen by the load in Fig. determine the ripple amplitude across the load. neglect the load. In this problem. 3. fin = 60 Hz. a current of 20 mA. and the peak voltage produced by the transformer is equal to 5 V. estimate the ripple amplitude across C1 . For simplicity. 3.5 V V in Figure 3.80 D1 Vout C1 0.5 V Figure 3. Suppose in Fig. 44.cls v. (b) Using the small-signal model of the diodes. Also. the diodes carry a current of 5 mA and the load.43. 2007 at 13:42 120 (1) 120 D1 Vout I in R 1 = 1 kΩ Chap. 2006] June 30.81 D2 Vin D4 Vout RL D3 D1 Figure 3. C1 = 100 F.on 800 mV.43 so as to appreciate the regulation provided by the diodes.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

Also. 3.51 for a negative threshold of . 52.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In the limiting circuit of Fig. 50. (a) Using hand calculations.) Suppose a triangular waveform is applied to the characteristic of Fig.84 49. 3. VB 2 . istic. Use SPICE to construct the input/output characteristic for .1:9 V and a positive threshold of +2:2 V. In the circuit of Fig. Plot the output waveform and note that it is a rough approximation of a sinusoid. Assume the input peak voltage is equal to 5 V.5 V in Figure 3. (b) Verify the result by SPICE. Using 1-k resistors. Design the limiting circuit of Fig. We wish to design a circuit that exhibits the input/output characteristic shown in Fig.V0 . and other components.85. Using the transient analysis in SPICE. 3. 3.on + VB 1 and . Vout +2V −2V +2V −2V 0. 2006] June 30.88 is driven by a 60-Hz sinusoid input with a peak amplitude of 5 V.VD.83 48.83. “Wave-shaping” applications require the input/output characteristic illustrated in Fig. The rectiﬁer shown in Fig. construct a circuit that provides such a characterVout +2V −4 V −2V +2V −2V 0. determine the required value of R1 .5 +4V 0. assume IS = 5 10. The half-wave rectiﬁer of Fig. 46. 3. 3.86 must deliver a current of 5 mA to R1 for a peak input level of 2 V. How should the input-output characteristic be modiﬁed so that the output becomes a better approximation of a sinusoid? SPICE Problems In the following problems. ideal diodes. plot the current ﬂowing through R1 as a function of Vin .84.2 V Vin +2 V.6 Chapter Summary 121 45. plot the currents ﬂowing through D1 and D2 as a function of time if the input is given by V0 cos !t and V0 VD.84 as shown in Fig. the maximum allowable current through each diode is 2 mA. 3.5 0. 51.87. construct the circuit. 3. and VD. 3.on .cls v. .16 A.5 V in Figure 3. (The value of resistors is not unique. 3.51. R1 = 500 and R2 = 1 k . Using ideal diodes and other components. 2007 at 13:42 121 (1) Sec. 47.on 800 mV.

87 D1 Vout V in 1 µF 100 Ω Figure 3. (b) Determine the peak current ﬂowing through D1 . 2006] June 30.5 V in V in t Figure 3.Vout j 5 mV. 53.88 (a) Determine the peak-to-peak ripple at the output.cls v. Using the dc analysis in SPICE to plot the input/output characteristic for 0 Vin 4 V. 2007 at 13:42 122 (1) 122 Chap.85 D1 Vout V in R1 Figure 3.89 is used in some analog circuits. 3 Diode Models and Circuits Vout +2V −4 V −2V +2V −2V 0. (c) Compute the heaviest load (smallest RL ) that the circuit can drive while maintaining a ripple less than 200 mVpp .2 V Vin +2 V and determine the maximum input range across which jVin .5 +4V 0. determine the values of VB 1 and VB 2 such that . The circuit shown in Fig.86 R1 D2 D1 R2 in Vout Figure 3.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.90 can provide an approximation of a sinusoid at the output in response to a triangular input waveform. The circuit of Fig. 54. 3. 3. Plot the input/output characteristic for .

90 . 3. 2 kΩ Vout D2 V B2 Vout 4V V in (a) (b) V in D1 V B1 Figure 3. 2007 at 13:42 123 (1) Sec.5 V 1 kΩ 123 D2 V in D4 D3 Vout D1 1 kΩ VEE = −2.89 the characteristic closely resembles a sinusoid.6 Chapter Summary VCC = +2.5 V Figure 3. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

cls v. Figure 4 illustrates the sequence of concepts introduced in this chapter.e. producing Vout . The ampliﬁcation factor or “voltage gain” of the circuit. Following the same thought process as in Chapter 2 for pn junctions. we aim to understand the physics of the transistor. an input voltage of 1 V yields an output current of 1 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1(b)].1 General Considerations In its simplest form. 4. Since V1 = Vin and Vout = . 4.KRL. Brattain.1(a). Note that K has a dimension of resistance. is deﬁned as AV = Vout Vin = . The negative sign indicates that the output is an “inverted” replica of the input circuit [Fig. preparing ourselves for the study of circuits employing such devices. Let us now construct the circuit shown in Fig. where I1 is proportional to V1 : I1 = KV1 . For example. derive equations that represent its I/V characteristics. we analyze the structure and operation of bipolar transistors. 124 (4. Our objective is to demonstrate that this circuit can operate as an ampliﬁer.1) Interestingly. 2007 at 13:42 124 (1) 4 Physics of Bipolar Transistors The bipolar transistor was invented in 1945 by Shockley. with K = 0:001 . then the circuit ampliﬁes the input.2) (4. We ﬁrst show how such a current source can form an ampliﬁer and hence why bipolar devices are useful and interesting. if KRL 1..1 .3) . subsequently replacing vacuum tubes in electronic systems and paving the way for integrated circuits.RL I1 . AV . i.KRLVin : (4. Vout is an ampliﬁed replica of Vin . and Bardeen at Bell Laboratories. the bipolar transistor can be viewed as a voltage-dependent current source. Voltage−Controlled Device as Amplifying Element Structure of Bipolar Transistor Operation of Bipolar Transistor Large−Signal Model Small−Signal Model 4. 2006] June 30. Consider the voltage-dependent current source depicted in Fig. In this chapter. and develop an equivalent model that can be used in circuit analysis and design.1 . 4. we have Vout = .1(b). where a voltage source Vin controls I1 and the output current ﬂows through a load resistor RL .

1 General Considerations V in Vp t 125 V1 I1 KV1 V in V1 I1 KV1 R L Vout V out K R L Vp t (a) (b) Figure 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and diodes in elementary circuit analysis and the previous chapters of this book. 4. the voltage gain remains unchanged.4. V in r in V1 I1 KV1 RL Vout Figure 4. 2007 at 13:42 125 (1) Sec. 4. We will see in Section 4. we discard some of these current and voltage combinations as irrelevant. we are accustomed to a oneto-one correspondence between the current through and the voltage across each device. bipolar transistors make the analysis of circuits more difﬁcult. 2006] June 30. Bipolar transistors are an example of such current sources and can ideally be modeled as shown in Fig. this model can be approximated by that in Fig. Note that K signiﬁes how strongly V1 controls I1 . as we develop our understanding of the transistor’s operation. Since V1 is equal to Vin regardless of the value of rin . Example 4. and depends on both the characteristics of the controlled current source and the load resistor. thus directly affecting the gain. (b) simple ampliﬁer. Having dealt with two-terminal components such as resistors. As three-terminal devices.1 (a) Voltage-dependent current source. This point proves useful in our analyses later.2 Voltage-dependent current source with an internal resistance rin . one may consider the current and voltage between every two terminals.1 Consider the circuit shown in Fig.3. .2.1(a).4 that under certain conditions. where the voltage-controlled current source exhibits an “internal” resistance of rin . arriving at a complex set of equations. Fortunately. capacitors. 4. Solution Exercise Repeat the above example if rin = 1. inductors. With three-terminal elements. Determine the voltage gain of the circuit. Note that the device contains three terminals and its output current is an exponential function of V1 .cls v. The foregoing study reveals that a voltage-controlled current source can indeed provide signal ampliﬁcation. on the other hand. thus obtaining a relatively simple model. 4.

While this simple diagram may suggest that the device is symmetric with respect to the emitter and the collector. VB . VBC . For example. For the device in Fig. 2007 at 13:42 126 (1) 126 Chap. the possible combinations of voltages and currents for a three-terminal device can prove overwhelming.4(b). the emitter “emits” charge carriers and the collector “collects” them while the base controls the number of carriers that make this journey. The three terminals are called the “base. the dimensions and doping levels of these two regions are quite different. As mentioned in the previous section. The circuit symbol for the npn transistor is shown in Fig.5(a) and recall from Chapter 2 that the depletion region sustains a strong electric ﬁeld. 4. Fortunately.” the “emitter. only one of these eight combinations ﬁnds practical value and comes into our focus here. Now suppose an electron is somehow “injected” from outside into the right side of the depletion region. Shown in Fig. VCB .3 Exponential voltage-dependent current source. 4. about 100 A in modern integrated bipolar transistors. 4. VBE . VBE 0. in reality. 4. it is instructive to study an interesting effect in pn junctions. Collector Collector (C) n Base VCB Base (B) p n Q 1 VCE VBE Emitter (E) (b) Emitter (a) Figure 4.” As explained later. In other words. E and C cannot be interchanged. The transistor is labeled Q1 here. and VCE .cls v. if the base is more positive than the emitter.. e. We readily note from Fig. Consider the reverse-biased junction depicted in Fig. Before continuing with the bipolar transistor. What happens to this electron? Serving as a minority carrier on the p side. We will also see that proper operation requires a thin base region. 2006] June 30. 4. leading to 23 possibilities for the terminal voltages of the transistor. the electron experiences the electric ﬁeld and is rapidly . and VC . 4. We denote the terminal voltages by VE . and VCE can assume positive or negative values.4(a) is an example comprising of a p layer sandwiched between two n regions and called an “npn” transistor.4(a) that the device contains two pn junction diodes: one between the base and the emitter and another between the base and the collector. then this junction is forward-biased.g.2 Structure of Bipolar Transistor The bipolar transistor consists of three doped regions forming a sandwich. 4 Physics of Bipolar Transistors 1 3 V1 I S exp V1 VT 2 Figure 4.4 (a) Structure and (b) circuit symbol of bipolar transistor. and the voltage differences by VBE .” and the “collector.4(a).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

with the emitter connected to ground.6 (a) Bipolar transistor with base and collector bias voltages. the transistor would not operate as a voltage-controlled current source and would prove of little value. Let us now consider the operation of the transistor in the active mode. This view implies that D1 carries a current and D2 does not. we analyze the operation of the transistor. we intend to show that (a) the current ﬂow from the emitter to the collector can be viewed as a current source tied between these two terminals. we say the device is biased in the “forward active region” or simply in the “active mode. After all. bearing in mind that the base region is very . We may be tempted to simplify the example of Fig. 4. To understand why the transistor cannot be modeled as merely two back-to-back diodes.8 V V BE = +0.6(b). (b) simplistic view of bipolar transistor.6(a) to the equivalent circuit shown in Fig. 2007 at 13:42 127 (1) Sec. 4. VBE .2 V... aiming to prove that. and (b) this current is controlled by the voltage difference between the base and the emitter. it appears that the bipolar transistor simply consists of two diodes sharing their anodes at the base terminal. under certain conditions.e. More speciﬁcally. Under these conditions.3 Operation of Bipolar Transistor in Active Mode In this section. The ability of a reverse-biased pn junction to efﬁciently “collect” externally-injected electrons proves essential to the operation of the bipolar transistor. the base voltage is set to about 0.cls v. 4. i. I2 V CE = +1 V V BE = +0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V (a) D2 V CE = +1 V I1 (b) D1 Figure 4.8 V and the collector voltage to a higher value. The base-collector junction therefore experiences a reverse bias of 0. We begin our study with the assumption that the base-emitter junction is forward-biased (VBE 0) and the base-collector junction is reverse-biased (VBC 0). we must examine the ﬂow of charge inside the device. Electron injected e n − − − − − − − − − − − − − − − − − − − − − − − − − − − − + + + + + − − − − − p + + + + + + + + + + + + + + + + + + + + + + + + + + + + E VR Figure 4. 2006] June 30.6(a)]. e.5 Injection of electrons into depletion region. we should anticipate current ﬂow from the base to the emitter but no current through the collector terminal. 4. Were this true. 1 V [Fig.” For example. it indeed acts as a voltage-controlled current source.g.3 Operation of Bipolar Transistor in Active Mode 127 swept away into the n side. 4.

7(a) summarizes our observations thus far.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. most of the electrons reach the edge of the collector-base depletion region. n V CE = +1 V p V BE = +0.7(b) and (c) illustrate this effect in “slow motion. (b) electrons approaching collector junction. the base region sustains but a small electric ﬁeld.29 for the emitterbase junction [Fig. two observations directly lead to the necessity of diffusion: (1) redrawing the diagram of Fig. we recognize that the density of electrons at x = x1 is very high. how do electrons travel through the base: by drift or diffusion? Second. to the collector while drawing a small current of holes through the base terminal.8 V n (c) Figure 4. through the base. i. In the active mode. requiring that the emitter doping level be much greater than that of the base (Chapter 2).8(a)]. Figures 4. how does the resulting current depend on the terminal voltages? Third.” We therefore observe that the reverse-biased collectorbase junction carries a current because minority carriers are “injected” into its depletion region. Consequently. it allows most of the ﬁeld to drop across the base-emitter depletion layer. 4. Figure 4. 4.5) and absorbed by the positive battery terminal. In fact. 2.8 V + h − e n + Depletion Region n V CE = +1 V p + h − e n + V BE = +0. 2007 at 13:42 128 (1) 128 Chap.8 V (a) (b) Depletion Region n − e p + h + V CE = +1 V V BE = +0. For proper transistor operation. the former current component must be much greater than the latter.cls v. We must now answer several questions. Thus. beginning to experience the built-in electric ﬁeld. (2) 1 This assumption simpliﬁes the analysis here but may not hold in the general case. What happens to electrons as they enter the base? Since the base region is thin. indicating that the emitter injects a large number of electrons into the base while receiving a small number of holes from it.e. 4. 4 Physics of Bipolar Transistors thin. Let us summarize our thoughts.1 leaving diffusion as the principal mechanism for the ﬂow of electrons injected by the emitter.5. First. as explained for pn junctions in Chapter 2. an npn bipolar transistor carries a large number of electrons from the emitter. the drift current in the base is negligible. Thus. the electrons are swept into the collector region (as in Fig. 2006] June 30. where the superscript emphasizes the high doping level. . Since the base-emitter junction is forward-biased. how large is the base current? Operating as a moderate conductor. electrons ﬂow from the emitter to the base and holes from the base to the emitter. (c) electrons passing through collector junction..7 (a) Flow of electrons and holes through base-emitter junction. we denote the emitter region with n+ . as illustrated in Fig.

4. 2006] June 30.2 As a forward-biased diode. providing a gradient for the diffusion of electrons. the base-emitter junction exhibits a high concentration of electrons at x = x1 in Fig. (c) electron proﬁle in base. As a result.8(c). 1 V0 T exp V BE = NB exp VV . 4.3.8(c) given by Eq. n x V CE Reverse Biased n p x x2 V CE e V BE p x1 e V BE n + h Forward Biased (a) n + (b) n x x2 x1 V CE e V BE p + n Electron Density (c) Figure 4.1 Collector Current We now address the second question raised above and compute the current ﬂowing from the collector to the emitter.8 (a) Hole and electron proﬁles at base-emitter junction. (b) zero electron density near collector. (2.8(b) is swept away. 4. the electron density in the base assumes the proﬁle depicted in Fig.96): BE nx1 = NE exp VV . 4. 4. 1 : n2 T i . the density of electrons falls to zero at this point.cls v. 2007 at 13:42 129 (1) Sec.3 Operation of Bipolar Transistor in Active Mode 129 since any electron arriving at x = x2 in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

(4.4) .

. NE and NB denote the doping levels in the emitter and the base. respectively. we determine the ﬂow of electrons into the collector as Jn = qDn dn dx (4.42)].5) Here. we assume VT = 26 mV. and we have utilized the relationship expV0 =VT = NE NB =n2 .6) = qDn 0 . electrons go from the emitter to the collector.T (4. the conventional direction of the current is from the collector to the emitter. B (4.7) 2 In an npn transistor. In this chapter. (2. Thus. i Applying the law of diffusion [Eq. Wnx1 .

2007 at 13:42 130 (1) 130 Chap. we obtain 2 E BE IC = ANqDn ni exp VV . substituting for nx1 from (4. 1 : B WB T In analogy with the diode current equation and assuming expVBE =VT .cls v.5). Multipling this quantity by the emitter cross section area. and changing the sign to obtain the conventional current. 4 Physics of Bipolar Transistors where WB is the width of the base region. AE . 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

9 (a) Two identical transistors drawing current from having twice the area.” Determine the current IX in Fig.9(a) if Q1 and Q2 are identical and operate in the active mode and V1 = V2 . IX I C1 Q1 V1 V2 (a) Example 4. VC . (4.9) implies that the bipolar transistor indeed operates as a voltage-controlled current source. (b) equivalence to a single transistor . T where E IS = ANqDn ni : W B B 2 (4.9) BE IC = IS exp VV .10) Equation (4. we write (4.2 I C2 Q2 V3 IX I C1 Q1 V1 C IX I C2 Q2 V3 V1 Q eq C 2A E V3 B B 2A E E AE E AE (b) Figure 4. proving a good candidate for ampliﬁcation.8) 1. 4. We may alternatively say the transistor performs “voltage-to-current conversion.

” operating as a single transistor with twice the emitter area of each. .. (2.12) . expected because the exponential dependence of IC upon VBE indicates a behavior similar to that of diodes. We therefore consider the baseemitter voltage of the transistor relatively constant and approximately equal to 0.3 Solution From Eq. Q1 has an emitter area of AE and Q2 an emitter area of In the circuit of Fig. 4.11) This result can also be viewed as the collector current of a single transistor having an emitter area of 2AE . we say the two transistors are “in parallel. of course. Exercise Repeat the above example if Q1 and Q2 have different emitter areas.3 Operation of Bipolar Transistor in Active Mode 131 Since IX Solution = IC 1 + IC 2 . V2 such that IC 1 = 10IC 2. (4.9). exp V1 V V2 = 10: T That is. 2007 at 13:42 131 (1) Sec. we have V1 IC 1 = IS exp VT .8 V for typical collector current levels. Determine V1 .e.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. i. we have 2 V E IX 2 ANqDn ni exp V 1 : WB B T (4.9(a).15) 60 mV at T = 300 K: Identical to Eq.14) (4. AE 1 = nAE2 . V2 = VT ln 10 (4. Exercise Repeat the above example if 8AE .9(b) and noting that Q1 and Q2 experience identical voltages at their respective terminals. 4. redrawing the circuit as shown in Fig. 4. Example 4. 2006] June 30. IC 2 IS exp V2 V T and hence (4. Q1 and Q2 are identical and operate in the active mode.109). this result is.13) V1 . (4. In fact.cls v.

A VBEint . VBEdis = 383 mV: (4. Using Eq. VBEdis = VT ln AE2 : E1 For this example. AE 2 =AE 1 (4. Since IS AE .16) where VBEint = VT lnIC 2 =IS 2 and VBEdis = VT lnIC 1 =IS 1 denote the base-emitter voltages of the integrated and discrete devices.10 Simple stage with biasing. 2006] June 30. respectively. whereas modern integrated devices may have an area as small as 0:5 m 0:2 m. 4 Physics of Bipolar Transistors Typical discrete bipolar transistors have a large area. Determine the output voltage in Fig. determine the difference between the base-emitter voltage of two such transistors for equal collector currents. we have VBE Example 4.16 A. VBEdis = VT ln IS1 . This current ﬂows through RL .g. we write IC Solution = 1:69 mA.4 Solution = VT lnIC =IS and hence I VBEint . (4.5 = 5 10.18) In practice. generating a voltage .cls v. Assuming other device parameters are identical. 1 kΩ 3V Q1 Vout Figure 4.9). VBEdis falls in the range of 100 to 150 mV because of differences in the base width and other parameters. Exercise Repeat the above comparison for a very small integrated device with an emitter area of 0:15 m 0:15 Since many applications deal with voltage quantities. 500 m 500 m.17) = 2:5 106. however. 2007 at 13:42 132 (1) 132 Chap. From Eq. (4. the collector current generated by a bipolar transistor typically ﬂows through a resistor to produce a voltage.10 if IS RL IC 750 mV Example 4..9). VBEint . The key point here is that VBE = 800 mV is a reasonable approximation for integrated transistors and should be lowered to about 700 mV for discrete devices. e.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. yielding VBEint . S2 (4.

4.11 (a) Bipolar transistor as a current source. Plotted in Fig. Recall from Eq.19) Exercise What happens if the load resistor is halved. In summary.3 Operation of Bipolar Transistor in Active Mode 133 drop of 1 k 1:69 mA = 1:69 V. in essence. (2. the base current must supply holes for both reverse injection into the emitter and recombination with the electrons traveling toward the collector. 4. 4. (b) I/V characteristic.cls v. 4. the base current.11(a)]. one recombines with a hole. 2007 at 13:42 133 (1) Sec. Since the bipolar transistor must satisfy Kirchoff’s current law. In practice. the base current contains an additional component of holes. IC RL. IB .2 Base and Emitter Currents Having determined the collector current.9) reveals an interesting property of the bipolar transistor: the collector current does not depend on the collector voltage (so long as the device remains in the active mode).11(b) is the current as a function of the collector-emitter voltage. As the electrons injected by the emitter travel through the base. Thus. we obtain Vout = 1:31 V: (4.12(b)]. the device draws a constant current. As an example. 2006] June 30. Since VCE = 3V . Equation (4. acting as a current source [Fig.5. one hole must be supplied by the base. results from the ﬂow of holes. the number of holes entering from the base to the emitter is a constant fraction of the number of electrons traveling from the emitter to the base.3. some may “recombine” with the holes [Fig. IC Q1 V1 I S exp V1 VT V1 (a) (b) Forward Active Region V CE Figure 4. some electrons and holes are “wasted” as a result of recombination. In the npn transistor of Fig. 4. exhibiting a constant value for VCE V1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we study the behavior of the transistor for VCE VBE . we now turn our attention to the base and emitter currents and their dependence on the terminal voltages. on the average. 4. For example. In Section 4.12(a). out of every 200 electrons injected by the emitter. . We can therefore view IB as a 3 Recall that VCE V1 is necessary to ensure the collector-base junction remains reverse biased. Thus.99) that the hole and electron currents in a forward-biased pn junction bear a constant ratio given by the doping levels and other parameters. for a ﬁxed base-emitter voltage. calculation of the base current readily yields the emitter current as well.3 Constant current sources ﬁnd application in many electronic circuits and we will see numerous examples of their usage in this book. for every 200 electrons injected by the emitter.

4 Physics of Bipolar Transistors n V CE V BE + h − e p − e n + V CE n IE (a) (b) Figure 4. 2007 at 13:42 134 (1) 134 IC n IB V BE + h − e p + Chap.12(a): IE = IC + IB = IC 1 + We can summarize our ﬁndings as follows: .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. It is common to write IC = IB . In order to determine the emitter current.20) where is called the “current gain” of the transistor because it shows how much the base current is “ampliﬁed.12 Base current resulting from holes (a) crossing to emitter and (b) recombining with electrons. we apply the KCL to the transistor with the current directions depicted in Fig. constant fraction of IE or a constant fraction of IC . 2006] June 30.cls v. 4. the of npn transistors typically ranges from 50 to 200.” Depending on the device structure. (4.

6 Solution BE IC = IS exp VV T (4. In this book.24) (4. we assume that the collector and emitter currents are approximately equal. 1 (4.22) BE IC = IS exp VV T 1 I exp VBE IB = S VT + 1 I exp VBE : IE = S V T (4. For a given VBE . If the current gain varies from 50 to 200 due to manufacturing variations.25) It is sometimes useful to write IC = = + 1 IE and denote = + 1 by .26) . For = 100. A bipolar transistor having IS = 5 10.21) : (4.23) (4. the collector current remains independent of : Example 4. suggesting that 1 and IC IE are reasonable approximations. = 0:99. calculate the minimum and maximum terminal currents of the device.16 A is biased in the forward active region with VBE = 750 mV.

We view the chain of dependencies as VBE ! IC ! IB ! IE . and the sum of the two ﬂows through the emitter. Consider the circuit shown in Fig.24) suggests that the base current is equal to that of a diode having a reverse saturation current of IS = .4 Bipolar Transistor Models and Characteristics 4. the reader may wonder about the cause and effect relationships. i. 2007 at 13:42 135 (1) Sec. Thus. we can place a diode between the base and emitter terminals.25).13. arriving at the model shown in Fig.29) (4.28) On the other hand. As illustrated in Fig.1 Large-Signal Model With our understanding of the transistor operation in the forward active region and the derivation of Eqs.13 Large-signal model of bipolar transistor in active region.23)-(4. we add a voltage-controlled current source between the collector and the emitter.14(a).4. 4.e.7 = 5 10.. 2006] June 30. the base-emitter voltage generates a collector current.11. (4. since the current drawn from the collector and ﬂowing into the emitter depends on only the base-emitter voltage. Since the base-emitter junction is forward-biased in the active mode. we can now construct a model that proves useful in the analysis and design of circuits—in a manner similar to the developments in Chapter 2 for the pn junction. 4. With the interdependencies of currents and voltages in a bipolar transistor. which requires a proportional base current. Moreover. But how do we ensure that the current ﬂowing through the diode is equal to 1= times the collector current? Equation (4. this current remains independent of the collector-emitter voltage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the base-emitter junction is modeled by a diode whose cross section area is 1= times that of the actual emitter area. . the emitter current experiences only a small variation because near unity for large : + 1= is 1:005IC IE 1:693 mA IE Exercise 1:02IC 1:719 mA: (4.cls v.4 Bipolar Transistor Models and Characteristics 135 = 1:685 mA: The base current varies from IC =200 to IC =50: (4.Q1 Example 4. B C VBE IS I S exp V BE VT β exp V BE VT E Figure 4.30) Repeat the above example if the area of the transistor is doubled.27) 8:43 A IB 33:7 A: (4. 4.17 A and VBE = 800 mV. where IS. 4. 4.

23)-(4. the voltage at node X drops. RC IC . Solution (a) Using Eq. The device approaches the “edge” of the forward active region if the base-collector voltage falls to zero. (b) variation of collector voltage as a function of collector resistance. We must now calculate the collector voltage..36) = +800 mV. (a) Determine the transistor terminal currents and voltages and verify that the device indeed operates in the active mode. this junction is reverse-biased and the transistor operates in the active mode. 4 Physics of Bipolar Transistors VX (V) RC IC V BE 500 Ω 2. as VX ! +800 mV. 2006] June 30.32) (4.e. (b) Determine the maximum value of RC that permits operation in the active mode.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.14(b) plots VX as a function of RC .25). Rewriting Eq. we have IC = 1:153 mA IB = 11:53 A IE = 1:165 mA: (4. (4.800 500 1041 R C (Ω ) (a) (b) Figure 4. we obtain VCC = RC IC + VX : That is.34) VX = 1:424 V: (4.424 0. i. Writing a KVL from the 2-V power supply and across RC and Q1 .0 X Q1 VCC 2V 1.14 (a) Simple stage with biasing.31) (4.cls v. (4. (4. 2007 at 13:42 136 (1) 136 Chap. for VX (4.37) . respectively. VX . Assume = 100.35) Since the collector voltage is more positive than the base voltage.33) The base and emitter voltages are equal to +800 mV and zero. C which. reduces to RC = 1041 : Figure 4.34) yields: RC = VCCI. (b)What happens to the circuit as RC increases? Since the voltage drop across the resistor. increases while VCC is constant. VX . (4.

studied in Section 4. IC is independent of VCE . This is in contrast to the small-signal model.11.2 I/V Characteristics The large-signal model naturally leads to the I/V characteristics of the transistor. the exponential relationship inherent in the device. With three terminal currents and voltages. if different values are chosen for VBE . this limits the voltage gain that the circuit can provide. 4.” After all. thus.15(a) plots IC versus VBE with the assumption that the collector voltage is constant and no lower than the base voltage. we may envision plotting different currents as a function of the potential difference between every two terminals—an elaborate task. 4 A 500-mV change in VBE leads to 500 mV=60 mV = 8:3 decades of change in IC . the above example apparently contains no signals! This terminology emphasizes that the model can be used for arbitrarily large voltage and current changes in the transistor (so long as the device operates in the active mode). if the base-emitter voltage varies from 800 mV to 300 mV. different values of VCE do not alter the characteristic. 2007 at 13:42 137 (1) Sec. Illustrated in Fig. The ﬁrst characteristic to study is. as explained below.4. IC Q1 V BE V CE V BE IC Q1 V CE IC I S exp I S exp V BE (a) IC V BE2 VT V BE1 VT V BE = V B2 V BE = V B1 V CE (b) Figure 4.cls v.4.14(a).4. For example. As we will see in Chapter 5. On the other hand. 4.13 is called the “large-signal model. Figure 4. 4.15(b). 2006] June 30. what is the minimum allowable value of VCC for transistor operation in the active mode? Assume RC = 500 . the characteristic is a horizontal line because IC is constant if the device remains in the active mode (VCE VBE ). only a few of such characteristics prove useful. and hence the collector current by many orders of magnitude. the characteristic moves up or down.15 Collector current as a function of (a) base-emitter voltage and (b) collector-emitter voltage. 4. Next. Exercise In the above example.4 Bipolar Transistor Models and Characteristics 137 RC . 4. However. As shown in Fig. The reader may wonder why the equivalent circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. This example implies that there exists a maximum allowable value of the collector resistance. we examine IC for a given VBE but with VCE varying. in the circuit of Fig. of course. 4.4 the model still applies. .

(b) collector current as a function of base current as a function of BE . (b) base current as a function of CE . e.25) suggest that the base and emitter currents follow the same behavior.24) and (4. 4 Physics of Bipolar Transistors The two plots of Fig.cls v. 4.40) IC 1. IC -VCE . IC jumps by increasingly greater steps: 24.5 µ A 0.153 mA.8 = 100.15 constitute the principal characteristics of interest in most analysis and design tasks. Solution VBE1 = 700 mV IC 1 = 24:6 A VBE2 = 750 mV IC 2 = 169 A VBE3 = 800 mV IC 3 = 1:153 mA: The characteristic is depicted in Fig.3. 2007 at 13:42 138 (1) 138 Chap.169 µ A 0. (c) Using the values obtained above. For IB characteristics.6 A to 169 A to 1.153 mA 169 µ A 24. 169 A if its base-emitter voltage is held at 750 mV.6 µ A V BE = 800 mV V BE = 750 mV V BE = 700 mV V CE (b) V BE (mV) (a) IB 11. we simply divide the IC values by 100 [Figs. and IB -VCE characteristics.153 mA 169 µ A 24. e. V V V VCE . we can also plot the IC -VCE characteristic as shown in Fig. We determine a few points along the IC -VBE characteristics.025 µ A 700 750 800 IB 11.5 µ A 0. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. concluding that the transistor operates as a constant current source of.169 µ A 0. Construct the IC -VBE .. IC 1.17 A and IB -VBE .38) (4.025 µ A V BE = 800 mV V BE = 750 mV V BE = 700 mV V CE (d) V BE (mV) (c) Figure 4. 4. Equations (4.. 2006] June 30.16 (a) Collector current as a function of BE . for equal increments in VBE .g.g.4.16(a). We return to this property in Section 4. IS = 5 10. For a bipolar transistor. Example 4.6 µ A 700 750 800 (4. . We also remark that.39) (4. 4.16(b).16(c) and (d)].

1 suggests that the device becomes “stronger” as K increases because a given input voltage yields a larger output current. we ask. The ratio IC =VBE approaches dIC =dVBE for very small changes and. compared to Eqs. if a base-emitter voltage change of 1 mV results in a IC of 0.17). Eq.1 mA in one transistor and 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.. 4. 4. the visualization of equations by means of such plots greatly enhances our understanding of the devices and the circuits employing them.” IC ∆V BE Figure 4.” gm : dI gm = dV C : (4. After all. We must therefore concentrate on the voltage-to-current conversion property of the transistor. if a signal changes the base-emitter voltage of a transistor by a small amount (Fig. in the limit. 2007 at 13:42 139 (1) Sec. More speciﬁcally.cls v. For a bipolar transistor. 4. what is the measure of the “goodness” of a voltage-dependent current source? The example depicted in Fig. is called the “transconductance.25). An important question that arises here is. as we will see throughout this book. 2006] June 30. the plots impart no additional information. particularly as it relates to ampliﬁcation of signals. another type of transistor described in Chapter 6). (4. For example.41) BE Note that this deﬁnition applies to any device that approximates a voltage-dependent current source (e.17 Test circuit for measurement of Q1 V CE gm .9) gives gm = dVd .g. how is the performance of such a device quantiﬁed? In other words.5 mA in another. we can view the latter as a better voltage-dependent current source or “voltage-to-current converter. how much change is produced in the collector current? Denoting the change in IC by IC .23)-(4.4 Bipolar Transistor Models and Characteristics 139 Exercise What change in VBE doubles the base current? The reader may wonder what exactly we learn from the I/V characteristics. we recognize that the “strength” of the device can be represented by IC =VBE .4. However. (4.3 Concept of Transconductance Our study thus far shows that the bipolar transistor acts as a voltage-dependent current source (when operating in the forward active region). 4.

43) (4.42) (4.44) I = VC : T The close resemblance between this result and the small-signal resistance of diodes [Eq. BE = V1 IS exp VV T T BE BE IS exp VV T (4. (3. .58)] is no coincidence and will become clearer in the next chapter.

” S. (b) 5 Unless otherwise stated. For example.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the value of IC 0 must be chosen according to the required gm and. 4. . if IC = 1 mA. meaning the device carries a bias (or “quiescent”) current of IC 0 in the absence of signals. and the corresponding base-emitter voltage.47) However. What happens to the transconductance of Q1 if the area of the device is increased by a factor of n? n I C0 I C0 Q1 V BE0 (a) Figure 4.44) reveals that. we use the term “bias current” to refer to the collector bias current.19 (a) One transistor and (b) Example 4. We say the transistor is “biased” at a collector current of IC 0 . e.. as we will see throughout this book. it is often helpful to view gm as the inverse of a resistance. 4 Physics of Bipolar Transistors Equation (4.46) (4. then with VT = 26 mV. Consider the circuit shown in Fig. the required gain.9 I C0 V CE V BE0 I C0 I C0 V CE n transistors providing transconductance. 4. VBE 0 . the transistor becomes a better amplifying device by producing larger collector current excursions in response to a given signal level applied between the base and the emitter. we have gm = 0:0385 . IC 0 .5 IC I C0 V BE0 V BE g m ∆V ∆V Figure 4. if VBE experiences a small perturbation V around VBE 0 . as IC increases.19(a). 2007 at 13:42 140 (1) 140 Chap. where gm = IC 0 =VT .18. then the collector current displays a change of gm V around IC 0 . Thus. 2006] June 30. As shown in Fig. The transconductance may be expressed in . gm = dIC =dVBE simply represents the slope of IC -VBE characteristic at a given collector current.18 Illustration of transconductance.45) (4.cls v.1 = 0:0385 S = 38:5 mS: (4. ultimately. In other words. for IC = 1 mA. we may write gm = 261 : (4.g.1 or “siemens.48) The concept of transconductance can be visualized with the aid of the transistor I/V characteristics.

Solution Exercise Repeat the above example if VBE 0 is reduced by VT ln n.20 for two different bias currents IC 1 and IC 2 . often undesirable effect. As a result.4. e. 2007 at 13:42 141 (1) Sec. the current produced by the transistor may ﬂow through a resistor to generate a proportional voltage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The derivation of gm in Eqs. and IE are examined. It is also possible to study the transconductance in the context of the IC -VCE characteristics of the transistor with VBE as a parameter. determine the changes in the currents ﬂowing through all terminals. From another perspective.21 depicts two conceptual examples where VBE or VCE is changed by V and the changes in IC . The derivation of the small-signal model from the large-signal counterpart is relatively straightforward. A similar beneﬁt accrues if a smallsignal model can be developed for transistors. For this reason. As shown in Fig. if n identical transistors. [Fig. Thus.19(b)]. 4. 4. Illustrated in Fig. Figure 4. We exploit this concept in Chapter 5 to design ampliﬁers. if the total collector current remains unchanged.44) suggests that the transconductance is fundamentally a function of the collector current rather than the base current. Recall from Chapter 3 that diodes can be reduced to linear devices through the use of the small-signal model. ampliﬁers. (4. We perturb the voltage difference between every two terminals (while the third terminal remains at a constant potential). On the other hand. the collector bias current plays a central role in the analysis and design. IC g m2 ∆V V BE = V B2 + ∆V V BE = V B2 V BE = V B1 + ∆V V BE = V B1 I C2 I C1 g m1 ∆V V CE Figure 4. IS is multiplied by the same factor.cls v.. may incorporate a large number of transistors.10. thus posing great difﬁculties in the analysis and design. and represent the results by proper circuit elements such as controlled current sources or resistors. then gm does not change but IB does. then so does the transconductance. if IC remains constant but varies. then the composite device exhibits a transconductance equal to n times that of each. the transconductance increases by a factor of n. IC = IS expVBE =VT also rises by a factor of n because VBE is constant. 2006] June 30.4 Bipolar Transistor Models and Characteristics 141 Since IS AE .g. with the base current viewed as secondary. 4.20 Transconductance for different collector bias currents. IB . 4. For example. 4. each carrying a collector current of IC 0 are placed in parallel.42)-(4. .4 Small-Signal Model Electronic circuits. the plots reveal that a change of V in VBE results in a greater change in IC for operation around IC 2 than around IC 1 because gm2 gm1 .

2006] June 30. 4. i. 2007 at 13:42 142 (1) 142 Chap. For simplicity. We know from the deﬁnition of transconductance that ∆ I C = g m ∆V BE ∆V BE Q1 V CE ∆I B VBE I S exp ∆I C V BE + ∆V BE VT V CE ∆V BE ∆I E B C B vπ g vπ m C B rπ vπ g vπ m C ∆V BE g ∆V BE m E E E Figure 4. 4 Physics of Bipolar Transistors ∆I C ∆I B ∆V ∆I B V BE (b) ∆I C ∆V Q1 Q1 V CE ∆I E (a) ∆I E Figure 4. The change in VBE creates another change as well: IB = IC (4. the current ﬂowing between these two terminals changes by gm = VBE .cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.22).49) concluding that a voltage-controlled current source must be connected between the collector and the emitter with a value equal to gm V . they can be related by Ohm’s Law.52) .50) (4. Since the voltage and current correspond to the same two terminals.21 Excitation of bipolar transistor with small changes in (a) base-emitter and (b) collectoremitter voltage. IC = gm VBE . (4. we denote VBE by v and the change in the collector current by gm v .. Let us begin with a change in VBE while the collector voltage is constant (Fig.51) = gm VBE : That is.22 Development of small-signal model. if the base-emitter voltage changes by VBE .e. by a resistor placed between the base and emitter having a value: r = VIBE B (4.

8 V v1 rπ vπ iC g vπ m (a) (b) Figure 4. We now turn our attention to the collector and apply a voltage change with respect to the emitter (Fig. The simple small-signal model developed in Fig. Since VCE leads to no change in any of the terminal currents.24 (a) Transistor with bias and small-signal excitation. 4.92 mA for VBE = I gm = VC T (4. IS = 3 10.22 serves as a powerful.10 iB V CC = 1.cls v. IC Q1 v1 800 mV Example 4. Thus. for a constant VBE . ∆I C ∆V CE Q1 V BE V BE VBE I S exp V BE VT ∆V CE Figure 4. This result is expected because the diode carries a bias current equal to IC = and.16 A.23).11. (b) small-signal equivalent circuit. this trade-off proves undesirable in some cases. (a) If v1 = 0. from Eq. 2007 at 13:42 143 (1) Sec. How about a change in the collector-base voltage? As studied in Problem 18. (b) If the microphone generates a 1-mV signal. the model developed in Fig. but the impedance between the base and emitter falls to lower values. 4.58). Studied in Chapter 5. and Q1 operates in the active mode. 4. determine the small-signal parameters of Q1 . the forward-biased diode between the base and the emitter is modeled by a small-signal resistance equal to =gm . With a high collector bias current.53) Thus. (3. depend on the bias current of the device. 4. We should remark that both parameters of the model.23 Response of bipolar transistor to small change in VCE . As illustrated in Fig. Solution = IS expVBE =VT .4 Bipolar Transistor Models and Characteristics 143 =g : m (4. gm and r . 4. 2006] June 30.22 need not be altered. where v1 represents the signal generated by a microphone. we obtain a collector bias current of 6. = 100. such a change also results in a zero change in the terminal currents. Consider the circuit shown in Fig. the collector voltage has no effect on IC or IB because IC = IS expVBE =VT and IB = IC = . versatile tool in the analysis and design of bipolar circuits. how much change is observed in the collector and base currents? (a) Writing IC 800 mV. 4.24(a). exhibits a small-signal resistance of VT =IC = = VT =IC = =gm .54) . a greater gm is obtained.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

4 Physics of Bipolar Transistors 1 = 3:75 .cls v. the device operates in the active mode.56) (4.63) which is. equal to IC = .58) (4. (a) The collector bias current of 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. and (4. which is equal to Vout . . of course. 2006] June 30.92 mA ﬂows through RC . a useful output is provided.55) r = g = 375 : m (4.57) (b) Drawing the small-signal equivalent of the circuit as shown in Fig. 4. but the result ﬂows through the 1.25. 2007 at 13:42 144 (1) 144 Chap. we obtain the change in the collector current as: IC = gm v1 1 mV = 3:75 = 0:267 mA: The equivalent circuit also predicts the change in the base current as (4. if the collector current ﬂows through a resistor. The microphone signal produces a change in IC .24(b) and recognizing that v = v1 . Exercise Repeat the above example if IS is halved.65) Since the collector voltage (with respect to ground) is more positive than the base voltage. RC IC = 1:108 V: (4.11 Solution Vout = VCC .61) (4. In other words. On the other hand. The above example is not a useful circuit. the circuit generates no output. The collector voltage. 4. (a) Verify that the transistor operates in the active mode.64) (4. leading to a potential drop of IC RC = 692 mV. (4.8-V battery. is thus given by: Example 4. The circuit of Fig.24(a) is modiﬁed as shown in Fig. (b) Determine the output signal level if the microphone produces a 1-mV signal.60) v IB = r 1 1 mV = 375 = 2:67 A.59) (4. where resistor RC converts the collector current to a voltage.62) (4.

12 Solution .8 V Q 1 Vout v1 800 mV Figure 4. Verify that the device operates in the active mode and compute the voltage gain. ignoring second-order effects in the device and their representation in the large-signal and smallsignal models. Note that Example 4.4. we must determine how the supply voltage. any other constant voltage in the circuit is replaced with a ground connection. Similarly. 1:384 V = 2:216 V and guaranteeing operation in the active mode. we simply “ground” the supply voltage in small-signal analysis.” 4. However.4 Bipolar Transistor Models and Characteristics 145 RC 100 Ω V CC = 1. 2006] June 30. The following example illustrates this point. 2007 at 13:42 145 (1) Sec. we observe that VCC must be replaced with a zero voltage to signify the zero change. To emphasize that such grounding holds for only signals. behaves with respect to small changes in the currents and voltages of the circuit.cls v.6 V. other components in the circuit must also be represented by a small-signal model. we sometimes say a node is an “ac ground. The circuit therefore ampliﬁes the input by a factor of 26. suppose we raise RC to 200 and VCC to 3. some circuits require attention to such effects if meaningful results are to be obtained. Exercise What value of RC places results in a zero collector-base voltage? The foregoing example demonstrates the ampliﬁcation capability of the transistor. Small-Signal Model of Supply Voltage We have seen that the use of the small-signal model of diodes and transistors can simplify the analysis considerably. a 1-mV microphone signal leads to a 0.7. Considering the circuit of Example 4. (b) As seen in the previous example. Since the supply does not change and since the small-signal model of the circuit entails only changes in the quantities. In such an analysis. In particular.5 Early Effect Our treatment of the bipolar transistor has thus far concentrated on the fundamental principles. We will study and quantify the behavior of this and other ampliﬁer topologies in the next chapter. Thus. 4. The key principle here is that the supply voltage (ideally) remains constant even though various voltages and currents within the circuit may change with time.11. Upon ﬂowing through RC .267-mA change in IC .25 Simple stage with bias and small-signal excitation. leading to a collector voltage of 3:6 V . this change yields a change of 0:267 mA 100 = 26:7 mV in Vout .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The voltage drop across RC now increases to 6:92 mA 200 = 1:384 V. VCC .

26 Small-signal equivalent circuit of the stage shown in Fig. thereby increasing the collector current.gm RC . we return to the internal operation of the transistor and reexamine the claim shown in Fig. the voltage gain must also double. E WB T A . Now suppose VCE is raised to VCE 2 [Fig. then the gain also grows indeﬁnitely? Does another mechanism in the circuit. the slope of the proﬁle increases. Does this mean that. Illustrated in Fig. reaching a value of 53.1 and RC = 200 .27(b)]. 4 Physics of Bipolar Transistors if VCC is not doubled. Recall from part (b) of the above example that the change in the output voltage is equal to the change in the collector current multiplied by RC . With gm = 3:75 . the equivalent circuit yields vout = . Equivalently. so does the voltage gain of the circuit. Discovered by Early. Exercise What happens if RC = 250 ? This example points to an important trend: if RC increases. To understand this effect.11 that “the collector current does not depend on the collector voltage.gm v RC = . 2 the effective base width.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thus increasing the reverse bias and widening the depletion region in the collector and base areas. 4. 4. 200 Ω RC rπ vπ v1 g vπ m v out Figure 4. perhaps in the transistor.27(a). Since RC is doubled. we have vout =v1 = .53:4. It can be proved that the rise in the collector current with VCE can be approximately expressed by a multiplicative factor: 2 E BE CE IC = ANqDn ni exp VV . then Vout = 1:8 V . 4.cls v. if RC ! 1. the “Early effect” translates to a nonideality in the device that can limit the gain of ampliﬁers.gm v1 RC and hence vout =v1 = . 1 1 + VV . limit the maximum gain that can be achieved? Indeed. 4. in Eq. where the collector voltage is somewhat higher than the base voltage and the reverse bias across the junction creates a certain depletion region width.9) to include this effect.26. WB . this phenomenon poses interesting problems in ampliﬁer design (Chapter 5).” Consider the device shown in Fig.25. x0 . This result is also obtained with the aid of the small-signal model.4. (4. 4. How is the Early effect represented in the transistor model? We must ﬁrst modify Eq.8) decreases. 2007 at 13:42 146 (1) 146 Chap. Since the base charge proﬁle must still fall to zero at the edge of depletion region. 1:384 V = 0:416 V and the transistor is not in the forward active region. 2006] June 30. (4.

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V BE CE IS exp VV 1+ V : T A .

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1+ VCE =VA .67) where WB is assumed constant and the second factor. models the Early effect.66) (4.” . (4. The quantity VA is called the “Early voltage.

4. 4. (b) effect of higher collector voltage. This is a reasonable approxIC V BE1 VT Without Early Effect With Early Effect .28(a)]. For a constant VCE .cls v. 4.67) with respect to VCE yields where it is assumed VCE imation in most cases. the dependence of IC upon VBE remains exponential but with a somewhat greater slope [Fig. On the other hand. It is instructive to examine the I/V characteristics of Fig.28(b)]. IC With Early Effect IC VBE 1 (4. 2007 at 13:42 147 (1) Sec.15 in the presence of Early effect.27 (a) Bipolar device with base and collector bias voltages. 4.68) VCE = IS exp VT VA I VC . for a constant VBE .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the IC .4 Bipolar Transistor Models and Characteristics V CE1 n x x2 x1 n + 147 V CE2 n x ’ x2 e V BE p e V BE n p + x1 (a) (b) Figure 4. differentiation of (4. (4. In fact.69) A VA and hence IC IS expVBE =VT .VCE characteristic displays a nonzero slope [Fig. 2006] June 30.

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Assume IS = 2 10.29).70) . 4. 4. we have from Eq. With VA Example 4. Determine the required base-emitter voltage if VA = 1 or VA = 20 V. Without Early Effect I S exp V BE (a) (b) V CE Figure 4. requiring modiﬁcation of the perspective shown in Fig.67) VBE = VT ln IC I S (4. 4. (4. The variation of IC with VCE in Fig.11(a). A bipolar transistor carries a collector current of 1 mA with VCE = 2 V.13 Solution = 1.16 A.28 Collector current as a function of (a) VBE and (b) VCE with and without Early effect. The transistor can still be viewed as a two-terminal device but with a current that varies to some extent with VCE (Fig.28(b) reveals that the transistor in fact does not operate as an ideal current source.

we have 1 + VCE =VA .72) = 757:8 mV: In fact. (4.73) where it is assumed ln1 . 4 X Physics of Bipolar Transistors Q1 V1 ( I S exp V1 VT ) ( 1+ VX VA ) Figure 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.cls v. we rewrite Eq.71) = 20 V. VA . for VCE (4.1 1 .67) as 0 B VBE = VT ln B IC @ 1 1 C C IS 1 + VCE A VA (4. = 760:3 mV If VA (4. VCE =VA . 2007 at 13:42 148 (1) 148 X Chap.29 Realistic model of bipolar transistor as a current source.

The large-signal model of Fig.4. where BE CE IC = IS exp VV 1 + VV T . IS A .13 must now be modiﬁed to that in Fig. for (4.75) 1. Exercise Repeat the above example if two such transistors are placed in parallel.4. 4.4. IC + V ln 1 .1 and 4. 4. VT VV . VCE VBE VT ln I T VA S CE VT ln IC .74) (4.30. Large-Signal and Small-Signal Models The presence of Early effect alters the transistor models developed in Sections 4.

A BE IB = 1 IS exp VV T IE = IC + IB : .

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76) (4. (4. For the small-signal model.78) Note that IB is independent of VCE and still given by the base-emitter voltage.77) (4.79) . we note that the controlled current source remains unchanged and gm is expressed as dI gm = dV C BE (4.

BE = V1 IS exp VV T T . 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.4 Bipolar Transistor Models and Characteristics 149 B IB VBE IE E IC ( I S exp C V1 VT ) ( 1+ V CE VA ) Figure 4.cls v. 2007 at 13:42 149 (1) Sec.30 Large-signal model of bipolar transistor including Early effect.

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81) r = g = VT : I C m (4.80) (4.31(a)]: BE IC + IC = IS exp VV T It follows that . I = VC : T Similarly.83) Considering that the collector current does vary with VCE . CE 1 + VV A (4.82) (4. 4. let us now apply a voltage change at the collector and measure the resulting current change [Fig.

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84) BE VCE . IC = IS exp VV VA T . 1 + VCE + VCE : V A (4.

(4. Called the “output resistance. to represent the Early effect. Note that both r and rO are inversely proportionally to the bias current. yielding an equivalent resistor: Depicted in Fig.86) (4. IC .88) Example 4. rO = VICE C VA = BE IS exp VV T VA : I C (4.14 A transistor is biased at a collector current of 1 mA. Determine the small-signal model if and VA = 15 V. (4. = 100 . 4.87) (4. rO . the small-signal model contains only one extra element.” rO plays a critical role in high-gain ampliﬁers (Chapter 5). Since the voltage and current change correspond to the same two terminals.69).31(b). they satisfy Ohm’s Law.85) which is consistent with Eq.

r = g Also.90) 1 = 26 . rO .94) = 15 k : Exercise What early voltage is required if the output resistance must reach 25 k ? In the next chapter. Figure 4. 2006] June 30.7). (2) establish a collector current that yields the required values for the small-signal parameters gm . These properties are studied in Chapter 11. e. Solution We have I gm = VC T and (4. Finally. the base-emitter and base-collector junctions exhibit a depletion-region capacitance that impacts the speed. rO . We must create proper dc voltages and currents at the device terminals to accomplish two goals: (1) guarantee operation in the active mode (VBE 0..92) rO = VA I C (4.31 (a) Small change in VCE and (b) small-signal model including Early effect. An important notion that has emerged from our study of the transistor is the concept of biasing. 4 Physics of Bipolar Transistors C ∆I C Q1 V BE ∆V B rπ vπ g vπ m rO E (a) (b) Figure 4.32 summarizes the concepts studied in this section. 4.91) (4. the load resistance tied to the collector faces an upper limit for a given supply voltage (Example 4. The analysis of ampliﬁers in the next chapter exercises these ideas extensively. we should remark that the small-signal model of Fig. we return to Example 4. = 2600 : m (4. We will conclude that the gain is eventually limited by the transistor output resistance.g. and r . 2007 at 13:42 150 (1) 150 Chap. . VCE 0). For example.31(b) does not reﬂect the highfrequency limitations of the transistor.89) (4.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.12 and determine the gain of the ampliﬁer in the presence of the Early effect.93) (4.

e. 4.33(a)]. it is desirable to operate bipolar devices in the forward active region. where they act as voltage-controlled current sources. As VCE approaches VBE .g. . 4. and we say the device is in “soft saturation. even in this case the transistor continues to operate as in the active mode.cls v.” If the collector voltage drops further. We know from Chapter 2 that a typical diode sustaining 200 mV of forward bias carries an extremely small current. but its depletion region still absorbs most of the electrons injected by the emitter into the base. 2006] June 30. 200 mV=60 mV=dec 9:2.” Suppose VCE = 550 mV and hence VBC = +200 mV. the junction sustains a zero voltage difference. VBC 0 and the B-C junction is forward biased? We say the transistor enters the “saturation region. But what happens if VCE VBE . i.32 Summary of concepts studied thus far. In this section.6 Thus. For VCE = VBE .. we study the behavior of the device outside this region and the resulting difﬁculties. 2007 at 13:42 151 (1) Sec. Let us set VBE to a typical value. the B-C junction experiences greater forward bias. 750 mV..5 Operation of Bipolar Transistor in Saturation Mode As mentioned in the previous section. car6 About nine orders of magnitude less than one sustaining 750 mV: 750 mV . and VBC goes from a negative value toward zero.e. the base-collector junction experiences less reverse bias. and vary the collector voltage from a high level to a low level [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 Operation of Bipolar Transistor in Saturation Mode V BE VT n V CE e 151 Operation in Active Mode I C = I S exp n − e p V BE + h + V CE V BE n n p + Large−Signal Model B C I/V Characteristrics IC B Small−Signal Model C VBE IS I S exp V BE VT I S exp IC V BE1 VT V CE V BE rπ vπ g vπ m β exp V BE VT E Early Effect E n V CE B Modified Small−Signal Model C rπ vπ g vπ m rO p V BE n + E Figure 4. 4.

34(b). then the degrades by 10. The above observations lead to the IC -VCE characteristics depicted in Fig. 2007 at 13:42 152 (1) 152 Chap. The term “saturation” is .35. Consequently. we have VBE . A bipolar transistor is biased with VBE = 750 mV and has a nominal of 100. 4. (b) ﬂow of holes to collector. Exercise Repeat the above example if VBE It is instructive to study the transistor large-signal model and I-V characteristics in the saturation region. 4. heavy saturation leads to a sharp rise in the base current and hence a rapid fall in .15 Solution If the base-collector junction is forward-biased so much that it carries a current equal to onetenth of the nominal base current. VT ln IC =1000 IS IS = VT ln 1000 180 mV: That is. 4.34(a).95) (4. including the base-collector diode. 4. a large number of holes must be supplied to the base terminal—as if is reduced.33 (a) Bipolar transistor with forward-biased base-collector junction. IB . We construct the model as shown in Fig. Example 4.97) = 570 mV: = 800 mV. 4 Physics of Bipolar Transistors ∆I C V CE Q1 V BE V BE + h n − e p + V CE n (a) (b) Figure 4.cls v. 2006] June 30. as illustrated in Fig. In other words. if the collector is left open. about a few hundred millivolts. what B-C voltage results in a current of IC =1000 if VBE = 750 mV gives a collector current of IC ? Assuming identical B-E and B-C junctions. VBC (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Since IB = IC =100. rying a signiﬁcant current [Fig.96) (4. where IC begins to fall for VCE less than V1 . VBC = VT ln IC . assume base-collector and base-emitter junctions have identical structures and doping levels. How much B-C forward bias can the device tolerate if must not degrade by more than 10? For simplicity. In fact. the B-C junction must carry no more than IC =1000. then DBC is forward-biased so much that its current becomes equal to the controlled current. We therefore ask. Note that the net collector current decreases as the device enters saturation because part of the controlled current IS 1 expVBE =VT is provided by the B-C diode and need not ﬂow from the collector terminal.33(b)].

e. used because increasing the base current in this region of operation leads to little change in the collector current.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) case of open collector terminal.36. RC IC VBE . 2007 at 13:42 153 (1) Sec. 4. It is important to recognize that the transistor simply draws a current from any component tied to its collector. Thus.5 Operation of Bipolar Transistor in Saturation Mode I S2 exp D BC B C 153 V BE VT D BC I S1 exp V BE VT V BE VBE D BE I S1 exp V BE VT VBE D BE E (a) (b) Figure 4. we permit soft saturation with VBC 400 mV because the current in the B-C junction is negligible. 4.16 For the circuit of Fig. determine the relationship between operation in soft saturation or active region. a resistor.cls v.. (4.35 Transistor I/V characteristics in different regions of operation. the collector current is still equal to IS expVBE =VT . Saturation Forward Active Region IC V1 V CE Figure 4. 2006] June 30. provided that various tolerances in the component values do not drive the device into deep saturation.g.34 (a) Model of bipolar transistor including saturation effects. Thus. 400 mV: (4. As a rule of thumb. Example 4. the speed of bipolar transistors also degrades in saturation (Chapter 11). Thus. electronic circuits rarely allow operation of bipolar devices in this mode. In addition to a drop in . it is the external component that deﬁnes the collector voltage and hence the region of operation. 400 mV.99) . The collector voltage must not fall below the base voltage by more than 400 mV: Solution VCC .98) VCC IC RC + VBE . RC and VCC that guarantees In soft saturation.

Figure 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. More importantly. operation in the active region requires forward-biasing the base-emitter junction and reverse-biasing the collector junction.36 (a) Simple stage. Under this condition. the collector-emitter voltage approaches a constant value called E Figure 4. forming a “pnp” device. Also. emphasizing that the emitter is heavily doped. a linear proﬁle of holes is formed in the base region to allow diffusion.38(a) shows the structure of a pnp transistor. (The battery tied between C and E indicates that VCE is relatively constant in deep saturation. 4 Physics of Bipolar Transistors Acceptable Region RC IC Q1 V BE (a) V CC V CC V BE − 400 mV RC (b) Figure 4.cls v. the transistor bears no resemblance to a controlled In the deep saturation region.) B 800 mV 200 mV C VCE. Thus. 4. . 2007 at 13:42 154 (1) 154 Chap. 4. All of the operation principles and equations described for npn transistors apply to pnp devices as well. IC RC still maintains a Exercise Determine the maximum tolerable value of RC . thus creating the base current.37.37 Transistor model in deep saturation. VBE 0 and VBC 0. we may wonder why such a device would be useful.1 Structure and Operation Figure 4.6 The PNP Transistor We have thus far studied the structure and properties of the npn transistor. VCC must be sufﬁciently large so that VCC reasonable collector voltage. We may naturally wonder if the dopant polarities can be inverted in the three regions. A small number of base majority carriers (electrons) are injected into the emitter or recombined with the holes in the base region.38(b) illustrates the ﬂow of the carriers. with the emitter and collector made of n-type materials and the base made of a p-type material. . As with the npn counterpart. 2006] June 30. 4. (b) acceptable range of VCC and RC .6. current source and can be modeled as shown in Fig. Under this condition.e. i. For a given value of RC .sat (about 200 mV). majority carriers in the emitter (holes) are injected into the base and swept away into the collector..

the collector must not be higher than the base.38(c) depicts the symbol of the pnp transistor along with constant voltage sources that bias the device in the active region. (3) The npn current equations (4. 4. Figure 4. 2007 at 13:42 155 (1) Sec. Since the base current must be included in the emitter current. The different cases are summarized in Fig. top of the page) toward a lower potential (i. We address this issue by making the following observations.102) .100) (4.39(b).38 (a) Structure of pnp transistor.39(a) shows two branches employing npn and pnp transistors. we note that IB1 and IC 1 add up to IE1 whereas IE2 “loses” IB2 before emerging as IC 2 .101) (4. We note that an npn transistor is in the active mode if the collector (voltage) is not lower than the base (voltage). bottom of the page). (1) The (conventional) current always ﬂows from a positive supply (i. 4.. T (4.6.cls v. here the base and collector voltages are lower than the emitter voltage. In contrast to the biasing of the npn transistor in Fig. 2006] June 30. Following our convention of placing more positive nodes on the top of the page. (2) The distinction between active and saturation regions is based on the B-C junction bias.6.2 Large-Signal Model The current and voltage polarities in npn and pnp transistors can be confusing.38(d) to emphasize VEB 0 and VBC 0 and to illustrate the actual direction of current ﬂow into each terminal. where the relative position of the base and collector nodes signiﬁes their potential difference.e.e. (b) current ﬂow in pnp transistor.. (c) proper biasing. on the other hand.6 The PNP Transistor 155 p x x2 x1 V CE V BE − e p − e n + h p + V CE h V BE n + p Hole Density (a) (b) V BE Q1 V BE (c) IE IB Q1 IC (d) V CE V CE Figure 4. (d) more intuitive view of (c). For the pnp device.25) must be modiﬁed as follows for the pnp device EB IC = IS exp VV T IS exp VEB IB = VT EB IE = + 1 IS exp VV . we redraw the circuit as in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4. 4. 4. illustrating that the (conventional) current ﬂows from collector to emitter in npn devices and from emitter to collector in pnp counterparts. Figure 4.23)-(4.

cls v. 4. 2006] June 30. Also. the Early effect can be included as EB IC = IS exp VV T E .39 (a) Voltage and current polarities in npn and pnp transistors. 4 Active Mode Physics of Bipolar Transistors Edge of Saturation 0 Saturation Mode I E2 I C1 I B1 Q1 I E1 0 (a) (b) Figure 4. I B2 Q2 I C2 V CC Active Mode Edge of Saturation Saturation Mode where the current directions are deﬁned in Fig. 2007 at 13:42 156 (1) 156 Chap. The only difference between the npn and pnp equations relates to the base-emitter voltage that appears in the exponent. (b) illustration of active and saturation regions.40. an expected result because VBE 0 for pnp devices and must be changed to VEB to create a large exponential term.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

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.41. Assume IS = 2 10.16 A and = 50.103) IS β exp V EB VT VEB IE I S exp IC V EB VT C B IB Figure 4. In the circuit shown in Fig. Example 4. EC 1 + VV : A (4.17 Q1 1. determine the terminal currents of Q1 and verify operation in the forward active region.2 V X RC V CC 2V 200 Ω Figure 4.40 Large-signal model of pnp transistor. 4.41 Simple stage using a pnp transistor. but VA = 1.

Vin represents a signal generated by a microphone.16 A.42. 2006] June 30. We nonetheless continue with our notation as it reﬂects the actual direction of currents and proves more efﬁcient in the analysis of circuits containing many npn and pnp transistors. 4. In the circuit of Fig. Exercise What is the maximum value of RC is the transistor must remain in soft saturation? (4.105) It follows that IB = 92:2 A IE = 4:70 mA: RC carries IC .106) (4.107) We must now compute the collector voltage and hence the bias across the B-C junction.cls v. Determine Vout for Vin = 0 and Vin = +5 mV if IS = 1:5 10.7 V Example 4. (4. Q1 operates in the active mode and the use of equations (4.18 IC RC 300 Ω Vout V CC 2.110) .100)-(4. 2007 at 13:42 157 (1) Sec. Invoking the illustration in Fig.109) which is lower than the base voltage.6 The PNP Transistor 157 We have VEB Solution = 2 V .42 PNP stage with bias and small-signal voltages. 4.100) and (4.104) (4.39(b). (4.102) is justiﬁed.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V Figure 4. 4. we conclude that We should mention that some books assume all of the transistor terminal currents ﬂow into the device.101) be multiplied by a negative sign. 1:2 V = 0:8 V and hence EB IC = IS exp VV T = 4:61 mA: (4. Q1 V in 1. thus requiring that the right-hand side of Eqs. For Vin Solution = 0.108) (4. VEB = +800 mV and we have EB IC jVin =0 = IS exp VV T (4. Since VX = RC IC = 0:922 V.

43(a). 4. 2006] June 30. a behavior similar to that of the npn counterparts in Figs. Depicted in Fig. Since a 5-mV change in V1 gives a 182-mV change in Vout . These results are more readily obtained through the use of the small-signal model.6. Following the convention in Fig. The small-signal model of pnp transistors may cause confusion.114) Note that as the base voltage rises.111) Vout = 1:038 V: If Vin increases to +5 mV. 4. In analogy with npn transistors.4.43 (a) Small-signal model of pnp transistor. The reader may notice that the terminal currents in the small-signal model bear an opposite direction with respect to those in the large-signal model of Fig. 4. We caution the reader about this confusion. E B ib rπ vπ ie E (a) ic g vπ m rO C ie rπ B vπ g vπ m rO C ib (b) ic Figure 4.3 Small-Signal Model Since the small-signal model represents changes in the voltages and currents. VBE 1 (4.31(b). the voltage gain is equal to 36. 4.5 mV. the collector voltage falls. one may automatically assume that the “top” terminal is the collector and hence the model in Fig.43(b). This is not an inconsistency and is studied in Problem 49. the small-signal model of the pnp transistor is indeed identical to that of the npn device. we expect npn and pnp transistors to have similar models. especially if drawn as in Fig.43(b) is not identical to that in Fig. .40. 4. Exercise Determine Vout is Vin = . 2007 at 13:42 158 (1) 158 Chap.43(b). we sometimes draw the model as shown in Fig. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4.113) Vout = 0:856 V: (4.25. and hence (4. 4 Physics of Bipolar Transistors = 3:46 mA. 4. yielding (4.112) = +795 mV and IC jVin =+5 mV = 2:85 mA. (b) more intuitive view of (a).38(d).cls v. 4. A few examples prove helpful here.

iX gm + r 1 (4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4.116) (4. Exercise What is the impedance of a diode-connected device operating at a current of 1 mA? Example 4.6 The PNP Transistor 159 Example 4. Noting that rpi carries a current equal to vX =r . Solution As illustrated in Figs. iX Q2 Q1 vX rπ vπ g vπ m (a) (b) Figure 4.45(d)-f. 2007 at 13:42 159 (1) Sec. Assume VA = 1.115) = 1. We call this structure a “diode-connected transistor. 4. It is seen that all three topologies reduce to the same equivalent circuit because VCC is grounded in the small-signal representation.118) g1 m VT : =I C Interestingly. . the device exhibits an impedance similar to that of a diode carrying the same bias current. 2006] June 30.” The same results apply to the pnp conﬁguration in Fig. 4.44(a).19 If the collector and base of a bipolar transistor are tied together.44(a). a two-terminal device results. Determine the small-signal impedance of the devices shown in Fig. we write a KCL at the input node: Solution vX + g v = i : r m X Since gm r (4.44(b)].44 We replace the bipolar transistor Q1 with its small-signal model and apply a small-signal voltage across the device [Fig. with a bias current of IC . 4. we replace each transistor with its small-signal model and ground the supply voltage. 4.cls v.117) (4.45(a)-(c) and compare the results.20 Draw the small-signal equivalent circuits for the topologies shown in Figs. 4. we have vX = 1 .

Exercise Repeat the above example if a resistor is placed between the collector and base of each transistor. Example 4. 2007 at 13:42 160 (1) 160 VCC RC v in Q 1 v out v in RC Chap. 4 VCC Q1 Physics of Bipolar Transistors VCC v in Q1 v out RC v out (a) (b) (c) RC rπ vπ g vπ m rπ vπ g vπ m v in rO v out v in r O RC v out (d) rπ v in vπ g vπ m rO RC v out v in rπ vπ g vπ m r O RC v out (e) v in rπ vπ g vπ m rO RC v out v in rπ vπ g vπ m r O RC v out (f) Figure 4. (b) simple stage using a pnp transistor. (f) small-signal equivalent of (f).45 (a) Simple stage using an npn transistor. (e) small-signal equivalent of (b). (c) another pnp stage. (d) small-signal equivalent of (a).cls v. 2006] June 30. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.46(a). 4.21 Draw the small-signal equivalent circuit for the ampliﬁer shown in Fig.

VCC RD R C1 Q2 v out Q1 v in Figure 4. Figure 4. 2007 at 13:42 161 (1) Sec. Note that rO1 . Such observations simplify the analysis (Chapter 5). (b) small-signal equivalent of (a). The carriers ﬂow from the emitter to the collector and are controlled by the base. 2006] June 30.cls v. 4. and r2 appear in parallel. Carriers injected by the emitter into the base approach the edge of collector depletion region and ae swept away by the high electric ﬁeld. the base-emitter junction is forward-biased and the base-collector junction reverse-biased (forward active region).47 has the same small-signal model as the above ampliﬁer. The bipolar transistor consists of two pn junctions and three terminals: base. and collector.7 Chapter Summary A voltage-dependent current source can form an ampliﬁer along with a load resistor. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Bipolar transistors are electronic devices that can operate as voltage-dependent current sources. Solution RC 1 . 4. Exercise Show that the circuit depicted in Fig.46(b) depicts the equivalent circuit. For proper operation. emitter.7 Chapter Summary 161 VCC R C1 RC Q1 v in R C2 v out Q2 v in rπ1 vπ 1 g m1 rπ2 vπ 1 r O1 vπ 2 g m2 v π2 r O2 v out R C2 (a) (b) Figure 4. 4.46 (a) Stage using npn and pnp devices.47 Stage using two npn devices.

The transconductance of a bipolar transistor is given by gm = IC =VT and remains independent of the device dimensions. Determine Vout =Vin . In the circuit of Fig.16 A. the base width of a bipolar transistor has increased by a factor of two.16 A.48 if VBE 1 . 3. 2006] June 30.49.48. Problems In the following problems. it is observed that the collector currents of Q1 and Q2 are equal I C1 Q1 V BE1 V BE2 I C2 Q2 Figure 4. Consider the circuit shown in Fig. 6. a resistance tied between the base and emitter. The small-signal model of bipolar transistors consists of a linear voltage-dependent current source. a bipolar transistor behaves as constant current source. 4 Physics of Bipolar Transistors The base terminal must provide a small ﬂow of carriers. 4. and a diode (accounting for the base current) tied between the base and emitter. If the base-collector junction is forward-biased. unless otherwise stated. How does the collector current change? 5.1(a) is constructed with K = 20 mA/V. Suppose the voltage-dependent current source of Fig. The ratio of collector current and the base current is denoted by . In the circuit of Fig. A resistance of RS is placed in series with the input voltage source in Fig. the bipolar transistor enters saturation and its performance degrades. The large-signal model of the bipolar transistor consists of an exponential voltage-dependent current source tied between the collector and emitter. IS 1 = IS 2 = 3 10. Plot the voltage gain as a function of x. assume the bipolar transistors operate in the active mode. 7. Repeat Problem 2 but assuming that rin and K are related: rin = a=x and K = bx. 4. 4. What value of load resistance in Fig. (a) If IS 1 = 2IS 2 = 5 10. VBE 2 = 20 mV. the bipolar transistor exhibits an exponential relationship between its collector current and base-emitter voltage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. (a) Calculate VB such that IX = 1 mA. 4.50. . 2007 at 13:42 162 (1) 162 Chap. 1.1(b) is necessary to achieve a voltage gain of 15? 2. some of which go to the emitter and some others recombine in the base region. In the forward active region. The small-signal models of npn and pnp transistors are identical. 4. (b) With the value of VB found in (a). determine VB such that IX = 1:2 mA. Due to a manufacturing error. 4. and an output resistance. 4. Determine the ratio of transistor cross section areas if the other device parameters are identical. choose IS 3 such that IY = 2:5 mA. In the forward active region.2.

Assuming that only integer multiples of a unit bipolar transistor having IS = 3 10.49 RC IX Q1 VB Q2 V CC = 2. RC R1 10 k Ω 1 kΩ V CC = 2 V Q1 Figure 4. determine the maximum value of VCC that places Q1 at the edge of saturation. and only a single voltage source. 4.16 A.50 (b) What value of RC places the transistors at the edge of the active mode? 8. 4.5 V Figure 4. construct .7 Chapter Summary 163 IX Q1 VB Q2 Q3 IY Figure 4. 10.51 of the active region.52. Assume IS = 5 10. 2006] June 30.16 A can be placed in parallel.53 if IS = 6 10. Consider the circuit shown in Fig. 4. Calculate the value of VB that places Q1 at the edge RC 500 Ω V CC = 2 V Q1 VB Figure 4.16 A. Repeat Problem 7 if VCC is lowered to 1.cls v. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.51. is available (Fig. 9. In the circuit of Fig.52 11.5 V. Assume IS = 3 10. 12.54). 4. VB .16 A. An integrated circuit requires two current sources: I1 = 1 mA and I2 = 1:5 mA. 2007 at 13:42 163 (1) Sec. Calculate VX in Fig.

IS 1 = 2IS 2 IX R1 = 10 k . IS 2 = 5 10. If 1 = 2 = 100 and IY Q1 Q2 VB Figure 4. 4 Physics of Bipolar Transistors Q1 1. If R1 = 10 k . 4.53 I1 I2 VB Unit Transistor Figure 4. Calculate the collector current.56 . IS 1 = 3 10.56. In the circuit of Fig.56. 2007 at 13:42 164 (1) 164 Chap. 18. 17. I2 = 0:3 mA.55 15. 4.cls v. Calculate IX and IY .16 A. assuming = 100 and IS = 7 10. 13. Repeat Problem 12 for three current sources I1 = 0:2 mA. compute VB such that IX = 1 mA.55. Suppose a voltage source is applied between the base and collector. 4. 14. 1 = 2 = 100.54 the required circuit with minimum number of unit transistors.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In the circuit depicted in Fig.5 V X 1 kΩ V CC = 2 V Figure 4. The base-emitter junction of a transistor is driven by a constant voltage. determine VB such that IC = 1 mA. Consider the circuit shown in Fig. 4.55.16 A. In the circuit of Fig.16 A. IC R1 Q1 VB Figure 4.16 A. If the device operates in the forward active R1 = 5 k . and I3 = 0:45 mA. = 4 10. 2006] June 30. VB = 800 mV and RB 16. R1 = 5 k . and VB = 800 mV.

since the signal changes the collector current. .119) where n is a constant coefﬁcient.58 23. e. A ﬁctitious bipolar transistor exhibits an IC -VBE characteristic given by IC = IS exp VBE .g. 10. Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig. = 100. = 100. prove that a change in base-collector voltage results in no change in the collector and base currents. A transistor with IS = 6 10.5 V Q1 Q1 0. What base-emitter voltage is required? 20. Construct the small-signal model of the device if IC is still equal to IB .5 V 10 µ A 1 kΩ RC V CC = 2. 4.57. Nonetheless. RC 50 Ω RC V CC = 2. If a bipolar device is biased at IC = 1 mA. Of course.) 19.58. what is the largest change in VBE that guarantees only 10 variation in gm ? 21.. 2007 at 13:42 165 (1) Sec. Most applications require that the transconductance of a transistor remain relatively constant as the signal level varies. (Neglect the Early effect.57 22.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. proper design ensures negligible variation. Assume IS = 8 10.5 V 1 kΩ V CC = 2.16 A must provide a transconductance of 1=13 . nV T (4.16 A.16 A. 2006] June 30. and VA = 1. Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig. 10 µA Q1 1 kΩ (a) V CC = 2 V Q1 1 kΩ (b) V CC = 2 V V CC = 2 V Q1 1 mA 1 mA V CC = 2 V Q1 (d) (c) Figure 4.cls v. Assume IS = 8 10. and VA = 1. 4. 4.7 Chapter Summary 165 region. gm = IC =VT does vary.8 V (a) Q1 (b) (c) Figure 4.

17 A.61.8 V V CC = 2. 2007 at 13:42 166 (1) 166 Chap.cls v.60.5 to 3 V. Construct the small-signal model of the device if IC is still equal to IS expVBE =VT . A ﬁctitious bipolar transistor exhibits the following relationship between its base and collector currents: 2 IC = aIB . we wish to decrease VB to compensate for the change in IC . Assuming IS RC 2 kΩ = 1 10. determine the change in the collector current of Q1 . (b) If VA = 5 V. VA = 5 V.8 V Figure 4.17 A and V CC Q1 0. 4 Physics of Bipolar Transistors 24.59 VA = 5 V.59. In the circuit of Fig.17 A. 4. Determine VX for (a) VA = 1.61 (a) Assuming VA = 1. In the circuit of Fig. where I1 is a 1-mA ideal current source and IS = 3 10. Determine the new value of VB . 2006] June 30. The collector voltage of a bipolar transistor varies from 1 V to 3 V while the base-emitter voltage remains constant. 27. 4. I1 Q1 VB V CC = 2 V Figure 4. (4. What Early voltage is necessary to ensure that the collector current changes by less than 5? 26. determine VB such that IC = 1 mA. .5 V Figure 4. 4.5 V. IS = 5 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In Problem 27.60 28.120) where a is a constant coefﬁcient. and (b) RC 1 kΩ X Q1 V B = 0. Consider the circuit shown in Fig. 25. 29. determine VB such that IC = 1 mA for a collector-emitter voltage of 1. VCC changes from 2.

32. and = 100 in Fig. 4.65 .17 A.62 and VA = 8 V for each device.64.7 Chapter Summary 167 30. 4. A bipolar current source is designed for an output current of 2 mA.. In the circuit of Fig. For the circuit depicted in Fig.63. What is the maximum value of RC if the collector-base must experience a forward bias of less than 200 mV? 100 k Ω RB RC V CC = 2. 2006] June 30.5 V Q1 VB Figure 4. n identical transistors are placed in parallel. 4. What value of VA guarantees an output resistance of greater than 10 k . 4.16 A and VA = 1.63 (a) Determine VB such that Q1 operates at the edge of the active region. where IS = 6 10. 31.16 A V B = 0. 2007 at 13:42 167 (1) Sec. construct the small-signal model of the equivalent transistor. (b) If we allow soft saturation. 2 kΩ RC V CC = 2. 34.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V Q1 Figure 4. Consider the circuit shown in Fig. Assume IS = 7 10.16 A and VA = 1.g.65. e. 4. VA = 1. by how much can VB increase? 33.cls v.62. Assume IS = 2 10.64 collector-base forward bias of 200 mV. calculate the maximum value of VCC that produces a RC 1 kΩ V CC Q1 Figure 4.8 V Figure 4. a collector-base forward bias of 200 mV. If IS = 5 10.

69 39.7 V Q2 V CC IX 2V Figure 4.17 A.cls v. 4.16 A. If VB is chosen to forward-bias the base-collector junction by 200 mV. If = 100. 2006] June 30.70. 4.17 A and = 100. . 4. 4. calculate IS .16 A. What is the value of that places Q1 at the edge of the active mode in Fig.71 such that Q1 operates at the edge of the active mode.5 V 1 kΩ Q1 Figure 4. In the circuit of Fig. RC Rp 9 kΩ V CC = 2.73 if IS = 3 10.68.66.82 V Q1 1.68 38. it is observed that IC = 3 mA. RB 1. Determine the collector current of Q1 in Fig.5 V Figure 4. 4.67. Consider the circuit shown in Fig.66 36. If IS 1 = 3IS2 = 6 10.69 if IS 50 k Ω = 2 10. what is the collector current? Q1 VB 1 kΩ V CC = 2. 4.67 37.16 A and VA = 1. In the circuit of Fig. 4.72? Assume IS = 8 10. 4 Physics of Bipolar Transistors 35. Calculate the value of IS such that the base-collector junction is forward-biased by 200 mV. Calculate the collector current of Q1 in Fig. calculate IX in Fig. 41. 40.7 V Q1 V CC IC 2V Figure 4. 4. Determine the value of IS in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 168 (1) 168 Chap. 0. = 100 and VA = 1. where IS = 5 10. 42.

5 V Figure 4. 2007 at 13:42 169 (1) Sec.2 V RC V CC 2V 2 kΩ Figure 4.5 V 1 kΩ (a) µA V CC 2 kΩ (c) 2. 2006] June 30. Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig. Assume IS = 3 10. 4.17 A. 45.5 V 20 Q1 V CC 2.5 V 500 (b) Ω Figure 4. . Calculate VX for (a) VA = 1. In the circuit of Fig. 4.5 V Figure 4. IS = 5 10. 4. Assume IS = 3 10.17 A.7 Chapter Summary 169 23 k Ω RB Q1 V CC IC 1.5 V 1V Figure 4.72 1 kΩ V CC Q1 2. 4. and VA = 1.70 Q1 V B = 1.76. = 100.74 44.75.73 43.71 100 k Ω RB Q1 V CC 1 kΩ 1.17 A.74.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 V Q1 V CC 2. and (b) VA = 6 V.cls v. Determine the operating point and the small-signal model of Q1 for each of the circuits shown in Fig. = 100. and VA = 1. Q1 1.

4. Consider the circuit depicted in Fig.43 do not seem to agree with those in the large-signal model of Fig.cls v. VA = 5 V.5 V 2 µA (a) (b) (c) Figure 4.78. 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 4 Physics of Bipolar Transistors V CC Q1 2. The terminal currents in the small-signal model of Fig. 4. Q1 1.7 V X V CC 500 2. and I1 = 2 mA.7 V X V CC 3 kΩ 2. Explain why this is not an inconsistency.77. .5 V Figure 4.40. In the circuit of Fig. = 100 and VA = 1. 51. 2007 at 13:42 170 (1) 170 2 kΩ 5 kΩ Chap.1 mV. 4. 48. Suppose VA = 5 V in the circuit of Fig. what is the change in VX ? (c) Construct the small-signal model of the transistor.5 V Figure 4. 2006] June 30.5 V Ω Figure 4.76 46. 4.79.16 A.75 Q1 1. Q1 VB X I1 V CC 2. 50.5 V V CC Q1 2.5 mA V CC Q1 2. Repeat Problem 46 for a current of 1 mA and compare the results. What is the required Early voltage? 47.78 (a) What value of VB yields VX = 1 V? (b) If VB changes from the value found in (a) by 0.77 (a) What value of IS places Q1 at the edge of the active mode? (b) How does the result in (a) change if VA = 1? 49. where IS = 6 10. A pnp current source must provide an output current of 2 mA with an output resistance of 60 k .5 V 0.

= 3IS2 = 5 10. 1 = 100.16 A. Q1 V in Q2 Vout RC V CC = 2.5 V (d) (e) Figure 4. . RE Q1 V CC RC 2.80.5 V RB Q1 RE Q1 V CC RC 2. where.16 A.5 V Q1 V CC RC 2.5 V Figure 4.5 mA V CC Q1 500 Ω 2. IS 1 2 = 50.7 Chapter Summary 360 k Ω 171 RB Q1 V CC 4 kΩ 2. 4. 2007 at 13:42 171 (1) Sec. Consider the circuit shown in Fig. Assume IS = 5 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VA = 1.5 V (a) (b) RE 0. (b) Calculate the transconductance of the transistor. 4.80 53.5 V Figure 4. 4. VA = 1.cls v.81 (a) We wish to forward-bias the collector-base junction of What is the maximum allowable value of Vin ? Q2 by no more than 200 mV. 52. = 100. 2006] June 30. and RC = 500 .5 V 300 Ω V CC 1 kΩ (c) 2. Determine the region of operation of Q1 in each of the circuits shown in Fig.81.79 (a) Determine IS such that Q1 experiences a collector-base forward bias of 200 mV.

VA.16 A.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.16 A. 4.86. IS 1 = 2IS2 = 6 10.84 (a) What value of Vin yields a collector current of 2 mA for Q2 ? (b) With the value found in (a). 4. .npn = 5 10. Repeat Problem 53 for the circuit depicted in Fig. Repeat Problem 57 for the stage depicted in Fig. V CC = 2. VA.5 V Figure 4. 4. In the circuit of Fig. IS.83. Q1 V in Q2 Vout RC V CC = 2. RC Q1 V in Q2 Vout V CC = 2. Plot the input/output characteristic of the circuit shown in Fig. Repeat Problem 53 for the circuit illustrated in Fig.npn = 5 V. SPICE Problems In the following problems. calculate the small-signal parameters of Q1 and Q2 and construct the equivalent circuit.83 56.82 55. RC Q1 Vout Q2 1 = 80 and 2 = 100. 4. 4. determine the minimum allowable value of Vin . 2007 at 13:42 172 (1) 172 Chap.5 V V in Figure 4. assume IS.87 for 0 Vin 1:8 V. 4 Physics of Bipolar Transistors (b) With the value found in (a). npn = 100. At what value of Vin does Q1 carry a collector current of 1 mA? 59.84. 2006] June 30.85 for 0 Vin 2:5 V. What value of Vin places the transistor at the edge of saturation? 58.pnp = 3:5 V.cls v. 57.82 but for part (a). 4.5 V Figure 4. Explain the dramatic difference between the two. Plot IC 1 and IC 2 as a function of Vin for the circuits shown in Fig. 54.17 A.pnp = 8 10. Verify that Q1 operates in the active mode. pnp = 50. calculate the small-signal parameters of Q1 and Q2 and construct the equivalent circuit.

5 V V in 1 kΩ Q1 Vout Figure 4. V CC = 2. Plot the input/output characteristic of the circuit illustrated in Fig.86 I C2 I C1 V in Q1 Q3 V CC = 2. 4.7 Chapter Summary 173 RC 1 kΩ Vout Q1 V B = 0.89 for 0 Vin 2:5 V.88 for 0 What value of Vin yields a transconductance of 50 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 4.9 V V in V CC = 2.5 V (a) (b) Figure 4.88 61.87 60. At what value of Vin do Q1 and Q2 carry equal collector currents? Can you explain this result intuitively? .85 V CC = 2. Plot the input/output characteristic of the stage shown in Fig. 4. 2007 at 13:42 173 (1) Sec.5 V V in Q2 V CC = 2.1 for Q1 ? RC 1 kΩ Vin 2 V.5 V Figure 4.5 V Vout Q1 V in Q2 Figure 4.cls v.

5 V V in Q1 Q2 Vout 1. 4 Physics of Bipolar Transistors 1 kΩ V CC = 2.cls v.5 V 1 kΩ Figure 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 2007 at 13:42 174 (1) 174 Chap.89 .

an ampliﬁer produces an output (voltage or current) that is a magniﬁed version of the input (voltage or current). While the ﬁeld of microelectronics involves much more than ampliﬁers. motivating us to master the analysis and design of such building blocks. What other aspects of an ampliﬁer’s performance are important? Three parameters that readily come to mind are (1) power dissipation (e. (3) noise (e... 5.1 General Considerations Recall from Chapter 4 that a voltage-controlled current source along with a load resistor can form an ampliﬁer. 175 . this chapter is quite long.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In general. the front-end ampliﬁer in a cellphone or a digital camera processes small signals and must introduce negligible noise of its own). This chapter proceeds as follows.g. 2007 at 13:42 175 (1) 5 Bipolar Ampliﬁers With the physics and operation of bipolar transistors described in Chapter 4. our study of cellphones and digital cameras in Chapter 1 indicates the extremely wide usage of ampliﬁcation. 2006] June 30. The reader is therefore encouraged to take frequent breaks and absorb the material in small doses. (2) speed (e.g.cls v. Since most electronic circuits both sense and produce voltage quantities.” vout =vin . some ampliﬁers in a cellphone or analog-to-digital converters in a digital camera must operate at high frequencies). Most of the concepts introduced here are invoked again in Chapter 7 (MOS ampliﬁers).. General Concepts Input and Output Impedances Biasing DC and Small−Signal Analysis Operating Point Analysis Simple Biasing Emitter Degeneration Self−Biasing Biasing of PNP Devices Amplifier Topologies Common−Emitter Stage Common−Base Stage Emtter Follower Building the foundation for the remainder of this book. 1 Exceptions are described in Chapter 12.1 our discussion primarily centers around “voltage ampliﬁers” and the concept of “voltage gain.g. we now deal with ampliﬁer circuits employing such devices. because it determines the battery lifetime in a cellphone or a digital camera).

the circuit must behave as a voltage source.1(a)]. Microphone Amplifier Speaker A v = 10 200 Ω 10 mV vm Rm 8Ω (a) 200 Ω vm Rm R amp v1 R in v amp RL 8 Ω v out (b) (c) Figure 5. Assume the microphone can be modeled with a voltage source having a 10-mV peak-to-peak signal and a series resistance of 200 .cls v.1(b) shows the interface between the microphone and the ampliﬁer. (a) Determine the signal level sensed by the ampliﬁer if the circuit has an input impedance of 2 k or 500 . In reality. At the output. Thus.e.1 (a) Simple audio system. i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. At the input.e. (b) Determine the signal level delivered to the speaker if the circuit has an output impedance of 10 or 2 . sense a voltage without disturbing (loading) the preceding stage. Solution (a) Figure 5. To understand this concept... deliver a constant signal level to any load impedance. The voltage .1 Input and Output Impedances In addition to the above parameters. the ideal output impedance is equal to zero. The ideal input impedance is therefore inﬁnite. Also assume the speaker can be represented by an 8. 2006] June 30. 5 Bipolar Ampliﬁers 5. Example 5.resistor. 2007 at 13:42 176 (1) 176 Chap. 5. the circuit must operate as a voltmeter. i. let us ﬁrst determine the I/O impedances of an ideal voltage ampliﬁer. The following example illustrates the issue. the I/O impedances of a voltage ampliﬁer may considerably depart from the ideal values. requiring attention to the interface with other stages. (b) signal loss due to ampliﬁer input impedance.1.1 An ampliﬁer with a voltage gain of 10 senses a signal generated by a microphone and applies the ampliﬁed output to a speaker [Fig. the input and output (I/O) impedances of an ampliﬁer play a critical role in its capability to interface with preceding and following stages. (c) signal loss due to ampliﬁer output impedance.

5. measuring the resulting current. on the other hand. 2 Recall that a zero voltage source is replaced by a short and a zero current source by an open. the method involves applying a voltage source to the two nodes (also called “port”) of interest. only 9 less than the microphone signal level.2(b) is shorted.3) v1 = 0:71vm.e. the output impedance of the ampliﬁer must be minimized. (b) Drawing the interface between the ampliﬁer and the speaker as in Fig.2(b) must be shorted to represent a zero voltage source. Since a voltage ampliﬁer is driven by a voltage source during normal operation. i. The importance of I/O impedances encourages us to carefully prescribe the method of measuring them. 2007 at 13:42 177 (1) Sec. For Ramp (5. 2006] June 30.2(a). On the other hand. (5. In Fig. vout = 0:44vamp. Also shown are arrows to denote “looking into” the input or output port and the corresponding impedance.1 General Considerations 177 sensed by the ampliﬁer is therefore given by v1 = R RinR vm : in + m For Rin (5.1(c). Exercise If the signal delivered to the speaker is equal to 0:2vm . (5.2 Illustrated in Fig. a substantial attenuation. 5. . 5.. As with the impedance of two-terminal devices such as resistors and capacitors. nearly 30 loss.1) =2k .5) =2 . v1 = 0:91vm. 5. we have R vout = R + L vamp : L Ramp For Ramp (5.2) = 500 . and since all independent sources must be set to zero. 5. The reader may wonder why the output port in Fig.2. the output remains open because it is not connected to any external sources.2(a) is left open whereas the input port in Fig. It is therefore desirable to maximize the input impedance in this case. 5. and deﬁning vX =iX as the impedance.cls v. for Rin (5. the input port in Fig. the procedure for calculating the output impedance is identical to that used for obtaining the Thevenin impedance of a circuit (Chapter 1).6) vout = 0:8vamp : Thus.4) = 10 . ﬁnd the ratio of Rm and RL . the input (output) impedance is measured between the input (output) nodes of the circuit while all independent sources in the circuit are set to zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. That is. 5.

5 Bipolar Ampliﬁers Output Port iX iX vx Short vX R out R in (a) (b) Figure 5. we note that the input impedance is simply given by vx = r : ix Since r = impedance..2 Measurement of (a) input and (b) output impedances.cls v. the input impedance is obtained by applying a small change in the input voltage and measuring the resulting change in the input current. the I/O impedances are usually regarded as small-signal quantities—with the tacit assumption that the signal levels are indeed small. The small-signal models of semiconductor devices therefore prove crucial here.e.2 Assuming that the transistor operates in the forward active region. As illustrated in Fig. (b) small-signal model.7) or lower IC yield a higher input =gm = VT =IC . 2006] June 30. at a port).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 178 (1) 178 Input Port Chap. Example 5. Solution Constructing the small-signal equivalent circuit depicted in Fig. we conclude that a higher Exercise What happens if RC is doubled? To simplify the notations and diagrams. the test voltage source is applied between the node of interest and ground.e. For example.3 (a) Simple ampliﬁer stage. Determining the transfer of signals from one stage to the next. . such a convention simply assumes that the other node is the ground.4. 5.3(a).. 5. determine the input impedance of the circuit shown in Fig. (5. we often refer to the impedance seen at a node rather than between two nodes (i. 5. i. VCC RC vX iX rπ vπ RC g vπ m v in Q1 rO (a) (b) Figure 5.3(b).

3 v in Q 1 R out R out (a) (b) Figure 5. and hence Rout = rO . 5. Neglect the Early effect for rπ vπ rπ vπ iX vX g vπ m R out (a) (b) Figure 5.5(b).6 (a) Impedance seen at emitter. gm v = 0. Solution Setting the input voltage to zero and using the small-signal model in Fig. we note that v = 0.5(a).6(a). Exercise What happens if a resistance of value R1 is placed in series with the base? Example 5. 5. (b) small-signal model. rπ vπ g vπ m rO Example 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we arrive at the small-signal Solution . 5. (b) small-signal model. 5. Setting the input voltage to zero and replacing VCC with ac ground.4 Concept of impedance seen at a node. Calculate the impedance seen looking into the collector of Q1 in Fig. VCC v in Q1 Q1 in Fig.1 General Considerations 179 Short R in R out (a) (b) Figure 5. 2006] June 30.4 Calculate the impedance seen at the emitter of simplicity. 2007 at 13:42 179 (1) Sec.cls v.5 (a) Impedance seen at collector.

Moreover. .cls v.2 Biasing Recall from Chapter 4 that a bipolar transistor operates as an amplifying device if it is biased in the active mode. we compute the operating (quiescent) conditions (terminal voltages and currents) of each transistor in the absence of signals.6(b). vX = 1 : iX gm + 1 r Since r (5. 5. It is imperative that the reader master these rules and be able to apply them in more complex circuits.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7): Looking into the base.7 Summary of impedances seen at terminals of a transistor. Exercise What happens if a resistance of value R1 is placed in series with the collector? The above three examples provide three important rules that will be used throughout this book (Fig.vX and (5.1. 2006] June 30.3 DC and Small-Signal Analysis The foregoing observations lead to a procedure for the analysis of ampliﬁers (and many other circuits).” this step determines both the region of operation (active or saturation) and the small-signal parameters of 3 While beyond the scope of this book.8) That is.4. 5. v gmv + v = .iX : r = .3 rO VA = rπ ac ac ac ac 1 gm Figure 5. 5. Looking into the collector. Interestingly.1.and reverse-biased. Looking into the emitter. in the absence of signals. we see 1=gm if the base is (ac) grounded and the Early effect is neglected. as explained in Section 4. r . ampliﬁcation properties of the transistor such as gm . Thus. the environment surrounding the device must ensure that the base-emitter and base-collector junctions are forward. the surrounding circuitry must also set (deﬁne) the device bias currents properly. and rO depend on the quiescent (bias) collector current. 2007 at 13:42 180 (1) 180 Chap. we see rO if the emitter is (ac) grounded. Called the “dc analysis” or “bias analysis. we have Rout 1=gm. we see r if the emitter is (ac) grounded. 5 Bipolar Ampliﬁers circuit shown in Fig.9) = =gm 1=gm. respectively. it can be shown that the impedance seen at the emitter is approximately equal to 1=gm only if the collector is tied to a relatively low impedance. that is. 5. First.

2006] June 30. Thus. must be set to zero for small-signal analysis. the supply voltage is constant and. V BE Bias (dc) Value t IC Bias (dc) Value t Figure 5. voltage and current sources that do not vary with time. study the response of the circuit to small signals and compute quantities such as the voltage gain and I/O impedances. the small. Fig. 5. we analyze the response to signal sources while constant sources are set to zero. It is important to bear in mind that small-signal analysis deals with only (small) changes in voltages and currents in a circuit around their quiescent values. we determine the effect of constant voltages and currents while signal sources are set to zero. all constant sources. the circuitry around the transistor is designed to establish proper bias conditions and hence the necessary small-signal parameters. DC Analysis Small−Signal Analysis VCC R C1 V CB V BE I C1 I C2 Short Open v in v out Figure 5. This criterion is justiﬁed because the amplifying properties of the transistor such as gm and r are 4 We say all constant voltage sources are replaced by an “ac ground. we perform “small-signal analysis. 2007 at 13:42 181 (1) Sec. Some iteration between the two steps may often be necessary so as to converge toward the desired behavior.4. for example. How do we differentiate between small-signal and large-signal operations? In other words.8. First. Second.cls v.. while establishing proper bias points. In Fig.signal behavior of the circuit is studied to verify the required performance. and second.9 summarizes these concepts. Second. Figure 5. As an example. 5.e..” i.1 General Considerations 181 each device. From another point of view.4. i.8 illustrates the bias and signal components of a voltage and a current.e. we say the circuit operates in the smallsignal regime. plays no role in the response to small signals. the two steps described above follow the superposition principle: ﬁrst. We should remark that the design of ampliﬁers follows a similar procedure .9 Steps in a general circuit analysis.8 Bias and signal levels for a bipolar transistor. We therefore ground all constant voltage sources4 and open all constant current sources while constructing the smallsignal equivalent circuit. the change in IC due to the signal must remain small. as mentioned in Section 4. under what conditions can we represent the devices with their small-signal models? If the signal perturbs the bias point of the device only negligibly.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. For example.” .

10 is an example where the battery serving as the supply voltage is replaced with a horizontal bar labeled VCC . the input voltage source is simpliﬁed to one node called Vin . Solution Unfortunately. That is. we consider 10 variation in the collector current as the upper bound for small-signal operation. If Vin (= VBE ) reaches 20 mV. 2006] June 30.10 Notation for supply voltage. . 5.5 A student familiar with bipolar devices constructs the circuit shown in Fig. developing skills to determine or create bias conditions. Example 5. 5. 2007 at 13:42 182 (1) 182 Chap. VCC RC Q1 Vout V in V in Q1 VCC RC Vout Figure 5.11 Ampliﬁer driven directly by a microphone. but as a rule of thumb. determine the peak value of the output signal. 5 Bipolar Ampliﬁers considered constant in small-signal analysis even though they in fact vary as the signal perturbs IC .10) 5 The subscript CC indicates supply voltage feeding the collector. The deﬁnition of “negligibly” somewhat depends on the circuit and the application. Illustrated in Fig. 5.5 Also. This phase of our study requires no knowledge of signals and hence the input and output ports of the circuit. we introduce various ampliﬁer topologies and examine their small-signal behavior.11 and attempts to amplify the signal produced by a microphone. a linear representation of the transistor holds only if the small-signal parameters themselves vary negligibly. VCC RC 1 kΩ Vout Q1 Vin Figure 5. (The microphone does not produce a dc output). then V IC = IS exp V BE T (5.2 Operating Point Analysis and Design It is instructive to begin our treatment of operating points with an example. the student has forgotten to bias the transistor. we will employ some simpliﬁed notations and symbols. we begin with the DC analysis and design of bipolar stages.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. with the understanding that the other node is ground. If IS = 6 10. In this chapter.16 A and the peak value of the microphone signal is 20 mV.cls v. In drawing circuit diagrams hereafter. Next.

the student in Example 5. leading to no ampliﬁcation.12) The circuit generates virtually no output because the bias current (in the absence of the microphone signal) is zero and so is the transconductance.1.6 Having realized the bias problem. so does Vout . Example 5. 2006] June 30.5 V RC 1 kΩ Vout Q1 Figure 5. Exercise Repeat the above example if a constant voltage of 0. Another important issue relates to the value of VBE : with VBE = VCC = 2:5 V.cls v. Acting as an ideal voltage source. As mentioned in Section 5.65 V is placed in series with the microphone. The fundamental issue here is that the signal generated by the microphone is shorted to VCC . 2007 at 13:42 183 (1) Sec.5 modiﬁes the circuit as shown in Fig. 5. VCC = 2. 5.12 V: (5. and set the collector current to the value required in the application. VCC maintains the base voltage at a constant value.2 Operating Point Analysis and Design 183 = 1:29 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.15 A: This change in the collector current yields a change in the output voltage equal to (5.12 Ampliﬁer with base tied to VCC . Solution Exercise Does the circuit operate better if a resistor is placed in series with the emitter of Q1 ? . Explain why the student needs to learn more about biasing.11) RC IC = 1:29 10.12. connecting the base to VCC to allow dc biasing for the base-emitter junction. prohibiting any change introduced by the microphone.2. enormous currents ﬂow into the transistor. Let us return to the above example for a moment. biasing seeks to fulﬁll two objectives: ensure operation in the forward active region. Since VBE remains constant.

where the base is tied to VCC through a relatively large resistor. . RB IB + VBE = VCC and hence (5.13) .14) .16) (5. we recall that the base-emitter voltage in most cases falls in the range of 700 to 800 mV and can be considered relatively constant.13. B note that the voltage drop across RC is equal to RC IC . 5.13 Use of base resistance for base current path.18) The circuit parameters can therefore be chosen so as to guarantee this condition.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For example. Instead. VCCR VBE RC VBE : B (5. and hence obtain VCE as VCE = VCC . 2007 at 13:42 184 (1) 184 Chap. we require the collector voltage to remain above the base voltage: . 2006] June 30. so as to forward-bias the base-emitter junction. VCC . 5 Bipolar Ampliﬁers 5. While not particularly interesting here. Our objective is to determine the terminal voltages and currents of Q1 and obtain the conditions that ensure biasing in the active mode.2. RC IC . we have computed the important terminal currents and voltages of Q1 .cls v.15) (5. Since the voltage drop across RB is equal to RB IB . using the sequence IB ! IC ! VCE . the emitter current is simply equal to IC + IB .1 Simple Biasing Now consider the topology shown in Fig. VCCR VBE RC : B (5. we write (5. to avoid saturation completely. = VCC . How do we analyze this circuit? One can replace Q1 with its large-signal model and apply KVL and KCL. but the resulting nonlinear equation(s) yield little intuition. IB = VCCR VBE : B With the base current known. The reader may wonder about the error in the above calculations due to the assumption of a constant VBE in the range of 700 to 800 mV. An example clariﬁes this issue. RB . In summary.17) Calculation of VCE is necessary as it reveals whether the device operates in the active mode or not. IC = VCCR VBE . we have VCC RB Y IC X IB Q1 RC Figure 5.

7 For the circuit shown in Fig.20) IC = 1:7 mA: With this result for IC . Writing (5.14.26) are quite close. (5. 5. (5. Verify that Q1 operates in the forward active region.28) . we use VBE = 800 mV as an initial guess and write Eq.cls v. we calculate a new value for VBE : (5.2 Operating Point Analysis and Design 185 Example 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. IB = VCCR VBE B = 16:5 A and hence (5.24) (5. Assume IS = 10. (5. Since IS is relatively small. VCC = 2.14 Simple biased stage.17 A. 2007 at 13:42 185 (1) Sec.27) (5.21) VBE = VT ln IC IS = 852 mV. determine the collector bias current. and iterate to obtain more accurate results. we surmise that the base-emitter voltage required to carry typical current level is relatively large. RC IC = 0:85 V.26) = 1:65 mA accurate VCE = VCC .5 V 100 k Ω 1 kΩ = 100 and RB RC Y IC X IB Q1 Figure 5. That is.23) . 5. IB = VCCR VBE B 17 A: It follows that (5. we have (5.22) (5.14) as Solution .25) IC = 1:65 mA: Since the values given by (5. 2006] June 30.19) (5.21) and (5.16). Thus. we consider IC enough and iterate no more.

1+ 2 if the base current is negligible. the topology of Fig.15 depicts an example. we return to the fundamental relationship IC = IS expVBE =VT and postulate that IC must be set by applying a well-deﬁned VBE .29) . a parameter that may change considerably. 2006] June 30. providing a baseemitter voltage equal to VX = R R2 R VCC .13 merits a few remarks.2. For these reasons. then IC rises to 1. 2007 at 13:42 186 (1) 186 Chap. (5. The transistor therefore operates near the edge of active and saturation modes. the effect of VBE “uncertainty” becomes more pronounced at low values of VCC because VCC . 5. Exercise What value of RB provides a reverse bias of 200 mV across the base-collector junction? The biasing scheme of Fig. driving the transistor toward heavy saturation. Figure 5.13 is rarely used in practice.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Thus.52. 5.2 Resistive Divider Biasing In order to suppress the dependence of IC upon . in low-voltage design—an increasingly common paradigm in modern electronic systems— the bias is more sensitive to VBE variations among transistors or with temperature .cls v. Second. In the above example.15) that IC heavily depends on . where R1 and R2 act as a voltage divider. First. Thus.98 mA and VCE falls to 0.VBE determines the base current. 5 Bipolar Ampliﬁers a value nearly equal to VBE . we recognize from Eq. (5. 5. if increases from 100 to 120.

Nonetheless. R VCC IC = IS exp R +2 R V . the design must ensure that the base current remains negligible.17 A and base current is negligible and the transistor operates in the active mode. 1 2 T VCC R1 Y X R2 RC IC Q1 (5. = 100.30) a quantity independent of . 5. Figure 5.15 Use of resistive divider to deﬁne VBE . Verify that the Determine the collector current of Q1 in Fig.16 if IS = 10.8 . Example 5.

37) Exercise What is the maximum value of RC if Q1 must remain in soft saturation? The analysis approach taken in the above example assumes a negligible base current. 2007 at 13:42 187 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. we have Solution VX = R R2 R VCC 1+ 2 = 800 mV: It follows that (5. requiring veriﬁcation at the end.31) (5.35) Is the base current negligible? With which quantity should this value be compared? Provided by the resistive divider. (5. IB must be negligible with respect to the current ﬂowing through R1 and R2 : VCC (5.2 Operating Point Analysis and Design VCC = 2.5 V 17 k Ω 187 R1 RC Y 5 kΩ IC X 8 kΩ Q1 R2 Figure 5. Neglecting the base current of Q1 .33) (5. 2006] June 30.32) BE IC = IS exp VV T = 231 A and (5.34) IB = 2:31 A: (5.36) R1 + R2 : This condition indeed holds in this example because VCC =R1 + R2 = 100 A 43IB . IB ? We also note that VCE = 1:345 V.cls v. and hence Q1 operates in the active region.16 Example of biased stage. But what if the end result indicates that IB is not negligible? We now analyze the circuit without this assumption. Let us replace the voltage divider with a Thevenin .

2006] June 30. The iteration then follows the sequence VBE ! IB ! IC ! VBE ! . (5. Assume . (5.17). noting that VThev is equal to the open-circuit output voltage (VX when the ampliﬁer is disconnected): VCC R1 VCC RC IC X R2 R1 VCC R2 VThev Q1 V Thev R1 R2 R Thev X IB VCC RC IC Q1 Figure 5. 5. IB RThev : V T (5. VT ln IC R 1 .39) VX = VThev .41) as This result along with IC = IB forms the system of equations leading to the values of IC and IB . VThev = R R2 R VCC : 1+ 2 Moreover. 5 Bipolar Ampliﬁers equivalent (Fig.17 Use of Thevenin equivalent to calculate bias.42) IS Thev and begin with a guess for VBE = VT lnIC =IS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 188 (1) 188 Chap. we rewrite (5. As in the previous examples. but the exponential dependence in IB = VThev . Calculate the collector current of Q1 in Fig.40) IC = IS exp VThev .18(a). 5.cls v. iterations prove useful here. IB RThev and (5. RThev is given by the output resistance of the network if VCC is set to zero: (5.41) Eq. For this reason.41) gives rise to wide ﬂuctuations in the intermediate solutions.38) RThev = R1 jjR2 : The simpliﬁed circuit yields: (5.

17 A. Example 5. Constructing the equivalent circuit shown in Fig.18(b).9 Solution = 100 and IS = 10.43) . we note that VThev = R R2 R VCC 1+ 2 (5. 5.

48) = IB = 91:9 A and VBE = VT ln IC IS = 776 mV: (5.15 makes the bias relatively insensitive to . IB = 0:79 A and IC = 79:0 A.cls v. After many iterations. (b) stage with Thevenin equivalent for the resistive divider and CC .44) RThev = R1 jjR2 = 54:4 k : (5. 2006] June 30. so is VX . 2007 at 13:42 189 (1) Sec.50) It follows that IB = 0:441 A and hence IC = 44:1 A. still a large ﬂuctuation with respect to the ﬁrst value from above. Continuing the iteration. 5. IC (5. 5. V = 800 mV and (5. In other words. Exercise How much can R2 be increased if Q1 must remain in soft saturation? While proper choice of R1 and R2 in the topology of Fig.47) (5. The circuit is therefore still of little practical value.45) (5.5 V 170 k Ω 189 VCC RC R Thev X V Thev IB IC Q1 R1 RC Y 5 kΩ X 80 k Ω IC IB Q1 R2 Figure 5.2 Operating Point Analysis and Design VCC = 2.18 (a) Stage with resistive divider bias. we obtain VBE = 757 mV. For example. thus multiplying the collector current by exp0:01VBE =VT 1:36 (for VBE = 800 mV). if R2 is 1 higher than its nominal value.46) We begin the iteration with an initial guess VBE = 750 mV (because we know that the voltage drop across RThev makes VBE less than VThev ).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.49) (5. a 1 error in one resistor value introduces a 36 error in the collector current. thereby arriving at the base current: IB = VThev . VBE RThev = 0:919 A: Thus. VBE 766 mV and IC = 63 A. the exponential dependence of IC upon the voltage generated by the resistive divider still leads to substantial bias variations. .

Also. Here. as described later in this chapter. let us determine the bias currents of the transistor.cls v. VBE . 2007 at 13:42 190 (1) 190 Chap.19 Addition of degeneration resistor to stabilize bias point.2. VP = VX .3 Biasing with Emitter Degeneration A biasing conﬁguration that alleviates the problem of sensitivity to and VBE is shown in Fig. thereby lowering the sensitivity to VBE . Thus.19. Called “emitter degeneration. resistor RE appears in series with the emitter.” the VCC R1 Y X R2 P RC IC Q1 IE RE Figure 5. R2 . 5. E . 2006] June 30. 5 Bipolar Ampliﬁers 5. we have VX = VCC R2 =R1 + R2 . introducing a smaller error in VBE and hence IC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. From an intuitive viewpoint. yielding V IE = RP 1 =R VCC R R2 R . VBE E 1+ 2 IC . Neglecting the base current. To understand the above property. addition of RE in series with the emitter alters many attributes of the circuit. an error in VX due to inaccuracies in R1 . or VCC is partly “absorbed” by RE . this occurs because RE exhibits a linear (rather than exponential) IV relationship.

(5.10 Solution We neglect the base current and write VX = VCC R R2 R 1+ 2 = 900 mV: Using VBE (5.55) = 800 mV as an initial guess. How much does the collector current change if R2 is 1 higher than its nominal value? Example 5.17 A.52) (5. (5.53) if 1. then IE and IC remain relatively constant. i. An example illustrates this point.51) (5..57) . Assume = 100 and IS = 5 10. 5.54) (5. VBE = 100 mV. the difference between VCC R2 =R1 + R2 and VBE is large enough to absorb and swamp such variations.e. Calculate the bias currents in the circuit of Fig. How can this result be made less sensitive to VX or VBE variations? If the voltage drop across RE .20 and verify that Q1 operates in the forward active region. we have VP = VX .56) (5.

then (5. we must reexamine the assumption of VBE (5. the device is indeed in the active region.2 Operating Point Analysis and Design VCC = 2. which is reasonable because the emitter and collector currents have changed by only 9. Illustrated in Fig. 2006] June 30. The collector voltage is given by VY = VCC . Is the assumption of negligible base current valid? With IC 1 mA. Let us now determine if Q1 operates in the active mode. (5. we note that this assumption is equivalent to considering VBE constant. 2007 at 13:42 191 (1) Sec. IB 10 A whereas the current ﬂowing through R1 and R2 is equal to 100 A. IC RC = 1 :5 V : (5. For greater accuracy. and (2) VRE must be large enough (100 mV to several hundred millivolts) to suppress the effect of uncertainties in VX and VBE .61) (5.62) With the base voltage at 0.9 V. (5. We may assume that the 9-mV change directly appears across RE .56).20 Example of biased stage. 5. From Eq. we conclude that the initial guess is reasonable. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V 16 k Ω 191 R1 RC Y X 1 kΩ Q1 P RE 100 9 kΩ R2 Ω Figure 5. raising the emitter current by 9 mV=100 = 90 A.9 can be followed.19 is used extensively in discrete circuits and occasionally in integrated circuits.54) indicates that VX rises to approximately 909 mV. two rules are typically followed: (1) I1 IB to lower sensitivity to .cls v.59) (5.57) suggests that a 4-mV error in VBE leads to a 4 error in VP and hence IE . an iterative procedure similar to that in Example 5. and hence IE IC 1 mA: With this result. Furthermore. Since (5. . indicating a good approximation.60) VBE = VT ln IC IS = 796 mV.21. 5. The assumption is therefore reasonable. Exercise What value of R2 places Q1 at the edge of saturation? The bias topology of Fig. Eq.58) = 800 mV. If R2 is 1 higher than its nominal value.

65) (5.63) (5. (2) based on the expected variations of R1 . we pose the (5.67) VCC . e. 5. we obtain RE = 400 .cls v. where the base current is neglected.5 mA and a VBE of 778 mV. For the base current IB = 5 A to be negligible. R2 . which in conjunction with (5.g. (4) choose R1 and R2 so as to provide the necessary value of VX and establish I1 IB . and IS = 5 10. the value of RC is bounded by a maximum that places Q1 at the edge of saturation.. that is.1 translates to a collector current of 0.21 Summary of robust bias conditions.66) . = 100.21 so as to provide a transconductance of 1=52 for Q1 .. To establish VX = VBE + RE IC = 978 mV. R1 + R2 = 50 k .64) (5. choose a value for VRE IC RE . RC IC 1:522 V: (5. 2006] June 30.11 must have . Assume VCC = 2:5 V. we A gm of 52 Solution R2 R1 + R2 VCC = VBE + RE IC . Assuming RE IC = 200 mV. 2007 at 13:42 192 (1) 192 VCC R1 I1 I 1 >> I B R2 RE X IB Y Chap. RC IC VX . VCC R1 + R2 IB .63) yields R1 = 30:45 k R2 = 19:55 k : How large can RC be? Since the collector voltage is equal to VCC following constraint to ensure active mode operation: (5.g. Thus.68) . RC IC . What is the maximum tolerable value of RC ? Example 5. Design Procedure It is possible to prescribe a design procedure for the bias topology of Fig. (3) calculate VX = VBE + IC RE with VBE = VT lnIC =IS .21 that serves most applications: (1) decide on a collector bias current that yields proper small-signal parameters such as gm and r . 5. Design the circuit of Fig. by a factor of 10. The following example illustrates these concepts.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Determined by small-signal gain requirements. e. and VBE . 200 mV.17 A. 5 Bipolar Ampliﬁers R C Small Enough to Avoid Saturation IC Q1 VRE >> Variations in VX and VBE Figure 5.

73) (5. VX IC 1:044 k : (5. We rewrite (5. the much smaller values of R1 and R2 here than in Example 5. the collector voltage falls below the base voltage. the reduction in RC translates to a lower voltage gain. Also. the transistor can tolerate soft saturation.cls v. Let us return to the above example and study these issues. leading to a low input impedance. RC 3:044 k : (5.1. thereby limiting the minimum value of the collector voltage to avoid saturation. 2006] June 30. VX = VBE + RE IC = 1:278 V and (5. up to about 400 mV of base-collector forward bias. then R1 + R2 and hence R1 and R2 are quite small. It follows that R1 = 1:45 k R2 = 3:55 k : (5.. Specifically.11 introduce a low input impedance.21 to lower sensitivities do impose some trade-offs. The value of RE is now given by 500 mV=0:5 mA = 1 k .1.72) Since the base voltage has risen to 1. 5. As mentioned in Chapter 4.64) as VCC R1 + R2 100IB .278 V.3. Thus.11 but assuming VRE Example 5. 400 mV and hence a greater value for RC .69) If RC exceeds this value. an overly conservative design faces the following issues: (1) if we wish I1 to be much much greater than IB .2 Operating Point Analysis and Design 193 Consequently. then VX (= VBE + VRE ) must be high. Repeat Example 5. leading to RC VCC . the collector voltage must exceed this value to avoid saturation. . Exercise The two rules depicted in Fig.74) As seen in Section 5. 2007 at 13:42 193 (1) Sec. Repeat the above example if the power budget is only 1 mW and the transconductance of Q1 is not given. in low-voltage applications. Also.63) still holds. obtaining R1 + R2 (5.3.12 Solution = 500 mV and I1 100IB . We compute the exact input impedance of this circuit in Section 5. we may allow VY VX .70) =5k . The collector current and base-emitter voltage remain unchanged. i.e. 5.71) (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (2) if we choose a very large VRE . loading the preceding stage.

A result of self-biasing.. IS = 5 10. and = 100.cls v.75) and (5. For example. (5.76) (5. 2007 at 13:42 194 (1) 194 Chap.75) VY = RB IB + VBE = RB IC + VBE : Equating the right hand sides of (5. 2006] June 30. RB = 10 VCC = 2:5 V. i. if RC increases indeﬁnitely.4 Self-Biased Stage Another biasing scheme commonly used in discrete and integrated circuits is shown in Fig. Q1 remains in the active region. 5. this stage exhibits many interesting and useful attributes.77) V IC = VCC . Called “self-biased” because the base current and voltage are provided from the collector. VCC RB IB X RC Y IC Q1 Figure 5.e. RC carries a current We now determine the collector bias current by assuming IB equal to IC .21.22.22 Self-biased stage. IB RB . 5.22 if RC = 1 k .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this important property guarantees that Q1 operates in the active mode regardless of device and circuit parameters. 5. thereby yielding VY = VCC . 5. we begin with an initial guess for VBE .2. RBE : RC + B As usual. compute IC .13 . 5 Bipolar Ampliﬁers Exercise Repeat the above example if VRE is limited to 100 mV. Repeat the calculations for RC = 2 k .77) gives (5. RC IC : Also. .17 A.78) = VT lnIC =IS k Determine the collector current and voltage of Q1 in Fig. (5. Example 5. Let us begin the analysis of the circuit with the observation that the base voltage is always lower than the collector voltage: VX = VY . IC . and utilize VBE to improve the accuracy of our calculations. a critical advantage over the circuit of Fig.

78) gives IC = 0:810 mA: (5. Since RB IB = 81 mV.78).16 A and = 100. Eq.22 for gm IS = 5 10.80) is acceptable. but it must remain substantially lower than RC .84) The choice of RB also depends on small-signal requirements and may deviate from this value. concluding that the initial guess for VBE and the value of IC given by it are reasonably accurate.79) and hence VBE = VT lnIC =IS = 807:6 mV. we have from (5. then and VY = VCC conditions. If RC = 2 k . This result serves as a quick estimate of the transistor bias .14 = 1=13 and VCC = 1:8 V. VBE in the numerator of (5. (5. IC RC VBE . . 2006] June 30. we choose RC = 10RB = and rewrite (5.82) = VT lnIC =IS . C (5. 5. IC VCCR VBE .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Design the self-biased stage of Fig. Compared with VCC . 1 C where VBE (5. the 9-mV error is negligible and the value of IC in (5.81) Design Procedure Equation (5.78): IC = 1:545 mA.78) as . 2007 at 13:42 195 (1) Sec. We also note that RB IB = 154:5 mV and VY = RB IB + VBE 0:955 V.80) To check the validity of the initial guess. In fact. Exercise What happens if the base resistance is doubled? Equation (5.78) together with the condition RC RB = provides the basic expressions for the design of the circuit. Assume . IC = VCC:1RVBE . VBE must be much greater than the uncertainties in the value of VBE . we write VBE = VT lnIC =IS = 791 mV.2 Operating Point Analysis and Design 195 Assuming VBE Solution = 0:8 V. RC = VCC:1I VBE 1 C R = RC : B (5. then with VBE = 0:8 V. 5. VY 0:881 V. if RC RB = . With the required value of IC known from smallsignal considerations. (5. . (2) RC must be much greater than RB = to lower sensitivity to .78) and the above example suggest two important guidelines for the design of the self-biased stage: (1) VCC .83) (5. That is.cls v. 10 Example 5.

and .15 Solution The topology is the same as that in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.88) Note that RB IB = 95 mV. Example 5.89) . IB RB + VEB = VCC : (5.23 Summary of biasing techniques. Figure 5.24 and determine the maximum allowable value of RC for operation in the active mode. VBE = 754 mV. R1 I1 RB RC R1 RC Q1 Q1 R2 Sensitive to Resistor Errors RC Q1 RE VRE R2 RB RC Q1 Always in Active Mode Sensitive to β Figure 5. We illustrate these points with the aid of some examples.cls v.85) (5.23 summarizes the biasing principles studied in this section.5 V.87) (5. RC VCC:1I VBE 1 C 475 : R RB = 10C = 4:75 k : (5. 2007 at 13:42 196 (1) 196 Chap. Circuits using pnp devices follow the same analysis and design procedures while requiring attention to voltage and current polarities. yielding a collector voltage of 754 mV + 95 mV = 849 mV.5 Biasing of PNP Transistors The dc bias topologies studied thus far incorporate npn transistors. 5 Bipolar Ampliﬁers Since gm Solution = IC =VT = 1=13 . 5. we have IC = 2 mA.13 and we have. 2006] June 30. Exercise Repeat the above design with a supply voltage of 2. (5. 5.86) Also. 5. Calculate the collector and voltage of Q1 in the circuit of Fig.2.

16 Solution VThev = R R1 R VCC 1+ 2 RThev = R1 jjR2 : (5. The transistor enters saturation at VY = VX . 2006] June 30. VEB ) and bringing Q1 closer to saturation. 5. 5. i. we have IB RB as the condition for edge of saturation. 5.93) (5.92) RC.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . IC RC.95) (5.25(a).cls v.2 Operating Point Analysis and Design VCC Q1 Y IC RC 197 IB RB VEB X Figure 5.max = VCC I.e. we assume IB is signiﬁcant and construct the Thevenin equivalent of the voltage divider as depicted in Fig. (5. VY rises.max Exercise For a given RC .max . 2007 at 13:42 197 (1) Sec. IC = VCCR VEB : B (5. As a general case. IB = VCCR VEB B and (5. thus approaching VX (= VCC .25(b): Example 5.90) .. obtaining RB = RC. VEB C = RB : From another perspective.91) The circuit suffers from sensitivity to .max = VCC .24 Simple biasing of pnp stage. That is. what value of RB places the device at the edge of saturation? Determine the collector current and voltage of Q1 in the circuit of Fig.94) = IC RC. since VX = IB RB and VY = IC RC . VEB and hence (5. If RC is increased.96) .

98) (5.97) V IB = VCC . some iteration between IC and VEB may be necessary. VEB Thev R2 V . then the transistor bias heavily depends on . Adding the voltage drop across RThev and VEB to VThev yields VThev + IB RThev + VEB = VCC . we equate the voltage drop across R2 to VEB . (b) Thevenin equivalent of divider and VCC .cls v.25 (a) PNP stage with resistive divider biasing.100) RThev As in Example 5. V CC EB 2 = R1 + RR : Thev It follows that (5. if IB I1 . RThev . VEB : IC = (5.9. Equation (5. thereby R2 V = V R1 + R2 CC EB . (5. On the other hand. 5 Bipolar Ampliﬁers VCC R2 I1 R1 I B VEB X Y IC RC (a) (b) VCC R Thev IB VEB X V Thev Y IC RC Q1 Q1 Figure 5. 2006] June 30.99) obtaining the collector current: R2 R1 + R2 VCC .100) indicates that if IB is signiﬁcant. 2007 at 13:42 198 (1) 198 Chap. that is.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

30).101) (5. R2 VCC IC = IS exp R + R V : 1 2 (5.17 Assuming a negligible base current. (5. calculate the collector current and voltage of Q1 in the . Exercise What is the maximum value of RC is Q1 must remain in soft saturation? Example 5.102) T Note that this result is identical to Eq.

With IB I1 . 2006] June 30.26. What is the maximum allowable value of forward active region? VCC R2 I1 RE I B VEB X R1 Y IC RC Q1 VRE RC for Q1 to operate in the Figure 5. 5.26 PNP stage with degeneration resistor.2 Operating Point Analysis and Design 199 circuit of Fig. Adding to VX the emitter-base voltage and the drop across RE . we have VX = VCC R1 =R1 + R2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.103) IE = R1 . 2007 at 13:42 199 (1) Sec. 5. we obtain Solution VX + VEB + RE IE = VCC and hence (5.

104) Using IC IE . VEB : E R1 + R2 (5. Eq. R2 VCC . (5. But a more straightforward approach is to recognize that the voltage drop across R2 is equal to VEB + IE RE . we have written a KVL from VCC to ground.103). Also. we can verify the assumption IB I1 . i. with IB = IC = .. In arriving at (5.104).e. 1+ 2 VCC R R1 R = RC. we can compute a new value for VEB and iterate if necessary. VCC R R2 R = VEB + IE RE .maxIC 1+ 2 .

V R R1 + R2 CC EB : E It follows that (5.106) (5.105) which yields the same result as in (5. V : R1 + R2 CC EB 1 (5.max 2 V .107) RC. R RC.max = RE VCC R R1 R 1+ 2 R2 V . The maximum allowable value of RC is obtained by equating the base and collector voltages: (5.104).108) .

We must write a KVL from VCC through the emitter-base junction of Q1 . 5 Bipolar Ampliﬁers Exercise Repeat the above example if R2 = 1.18 X VEB Figure 5. 5.27 Self-biased pnp stage. RB .cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Moreover. Since 1 and hence IC IB . RC carries a current approximately equal to IC .27. VCC Q1 IB RB Y IC RC Example 5. yielding Solution VCC = VEB + VX = VEB + RB IB + IC RC . 2006] June 30. and RC to ground. Determine the collector current and voltage of Q1 in the self-biased circuit of Fig. VX = RB IB + VY = RB IB + RC IC . creating VY = RC IC . 2007 at 13:42 200 (1) 200 Chap.

+ RC (5.78). (5. Exercise How far is Q1 from saturation? .109) (5. Q1 always remains in the active mode. etc. since the base is higher than the collector voltage. (5. = VEB + RB + RC IC : Thus. and determine a new value for VEB . we begin with a guess for VEB . VEB .111) CC IC = VRB . Note that.112) a result similar to Eq.110) (5. compute IC . As usual.

Nevertheless.3 Bipolar Ampliﬁer Topologies Following our detailed study of biasing. the output signal can be sensed from any of the terminals (with respect to ground) [Figs. v in v in v in (a) (b) (c) v out v out v out (d) (e) Figure 5. the circuit is called a “common-emitter” (CE) stage (Fig. 5.cls v.7 before proceeding further. 2007 at 13:42 201 (1) Sec. we can now delve into different ampliﬁer topologies and examine their small-signal properties. The reader is encouraged to review Examples (5. The term “common-emitter” is used because the emitter terminal is grounded and hence appears in common to the input and output ports.29).28(a)] and the output signal is sensed at the collector [Fig. the large-signal behavior of ampliﬁers also becomes important in many applications. In all cases. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. bipolar transistors operating in the active mode respond to base-emitter voltage variations by varying their collector current.28(d)-(f)]. 5.28(d)]. This property rules out the input connection shown in Fig. Similarly.2)-(5.28(c) because here Vin does not affect the base or emitter voltages. we identify the stage based on the input and output connections (to the base and from the collector. 5.1 pointed to the circuit of Fig.28 Possible input and output connections to a bipolar transistor. 5. 2006] June 30. as seen in Chapter 4. 6 While beyond the scope of this book.25 as an ampliﬁer. 5.28(a)(c). 5. 5. If the input signal is applied to the base [Fig. 4. as conceptually illustrated in Figs. we may surmise that three possibilities exist for applying the input signal to the device. We study each carefully. We have encountered and analyzed this circuit in different contexts without giving it a name.3. the topology in Fig. .28(b) and (e) remain incompatible because Vout would be sensed at the input node (the emitter) and the circuit would provide no function.6 Since the bipolar transistor contains three terminals. leading to nine possible combinations of input and output networks and hence nine ampliﬁer topologies. 5. 5. 5. The above observations reveal three possible ampliﬁer topologies. But we note that the input and output connections in Figs. 4. the bipolar transistors operate in the active mode.28(f) proves of no value as Vout is not a function of the collector current.3 Bipolar Ampliﬁer Topologies 201 5.1(b) and hence the topology of Fig. (f) However. Also. The number of possibilities therefore falls to four. seeking to compute its gain and input and output impedances.4) and the three resulting rules illustrated in Fig.1 Common-Emitter Topology Our initial thoughts in Section 4. respectively) so as to avoid confusion in more complex topologies.

gmRC : (5. Av is proportional to gm (i. Interestingly.30. denoting the dc drop across RC with VRC and writing gm = IC =VT . 2007 at 13:42 202 (1) 202 VCC RC Vout Chap. As explained in Chapter 4. 5. RC . shown in Fig.29 lowers Vout . we express (5. we have = vout =vin . and (b) analysis of the CE stage including the bias circuitry as a more realistic case.115) . 5 Bipolar Ampliﬁers V in Q 1 Output Sensed at Collector Input Applied to Base Figure 5. Second. the small-signal gain is negative because raising the base voltage and hence the collector current in Fig.113) . R C and v = vin . vout = gm v .3 that a small increment of V applied to the base of Q1 in Fig. We neglect the Early effect for now. Beginning from the output (5.114) as jAv j = IC RC V T (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In fact. the collector bias current) and the collector resistor. we construct the small-signal equivalent of the circuit. acts as an ac ground because its value remains constant with time.cls v.114) Equation (5.29 increases the collector current by gm V and hence the voltage drop across RC by gm V RC . Let us ﬁrst compute the small-signal voltage gain Av port and writing a KCL at the collector node. the voltage gain of the stage is limited by the supply voltage. A higher collector bias current or a larger RC demands a greater voltage drop across RC . 5. 2006] June 30. the supply voltage node..114) embodies two interesting and important properties of the CE stage. 5. VCC .4. First.29 Common-emitter stage. We deal with the CE ampliﬁer in two phases: (a) analysis of the CE core to understand its fundamental properties.e. Analysis of CE Core Recall from the deﬁnition of transconductance in Section 4. but this drop cannot exceed VCC . In order to examine the amplifying properties of the CE stage.30 Small-signal model of CE stage. v in rπ vπ g vπ m v out − RC RC v out Figure 5. It follows that Av = .

122) (5. 2006] June 30.124) (5. . 5. 2007 at 13:42 203 (1) Sec. the transistor itself requires a minimum collector-emitter voltage of about VBE to remain in the active region. we have IC edge of saturation is given by Solution VCC . so long as Q1 remains in soft saturation (VBC 400 mV).. VBE C 1:8 k : (5. an input signal drives the transistor into saturation. forward-biasing the base-collector junction for half of each cycle. VCE 400 mV and hence RC VCC . The value of RC that places Q1 at the (5.I400 mV C 2:52 k : In this case.117) Furthermore.125) Av = . along with VBE 800 mV.53:9: (5. RC IC = VBE . A more aggressive design may allow Q1 to operate in soft saturation. the circuit ampliﬁes properly. which.120) (5. the maximum voltage gain is given by (5.gmRC = .126) Of course.g. jAv j VCC V VBE : T Design a CE core with VCC voltage gain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.38:5: (5.121) The voltage gain is therefore equal to Av = .3 Bipolar Ampliﬁer Topologies 203 RC = VV : T Since VRC (5. For example.cls v.8-mVpp output.119) Since P = IC VCC = 1 mW.116) VCC .19 = 1:8 V and a power budget. Nevertheless. 5. (5. e.118) Example 5. a 2-mVpp input signal gives rise to a 107. driving Q1 into heavy saturation [Fig. a 2-mVpp input results in a 77-mVpp output. As illustrated in Fig.31(a). of 1 mW while achieving maximum = 0:556 mA. lowering the limit to . the circuit can now tolerate only very small voltage swings at the output. P . CC jAv j VV : T (5.123) Under this condition. yields RC VCC I.

” Exercise Repeat the above example if VCC = 2:5 V and compare the results.128) =gm = VT =IC and decreases as the collector iX vX (a) (b) Figure 5.32(a). leaving . the dependent current source also vanishes. 2006] June 30. We say the circuit suffers from a trade-off between voltage gain and voltage “headroom.8 mVpp Q1 t t (b) Figure 5. where the input voltage source is set to zero (replaced with a short). the input impedance is simply equal to bias increases. 5 Bipolar Ampliﬁers 77 mV pp 800 mV Q1 t t (a) VCC RC 2 mVpp 800 mV 400 mV 107. The output impedance is obtained from Fig. iX vX rπ vπ g vπ m RC rπ vπ g vπ m RC (5. Let us now calculate the I/O impedances of the CE stage. we write Rin = vX iX = r : Thus.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 204 (1) 204 VCC RC 2 mVpp 800 mV Chap. 5. Since v = 0.32(b). 5.32 (a) Input and (b) output impedance calculation of CE stage. (b) in saturation.127) (5. 5.31(b)].31 CE stage (a) with some signal levels. Using the equivalent circuit depicted in Fig.

. For example. for a given value of output impedance.3 Bipolar Ampliﬁer Topologies 205 RC as the only component seen by vX . 2007 at 13:42 205 (1) Sec.132) Interestingly.4.114) suggests that the voltage gain of the CE stage can be increased indeﬁnitely if RC ! 1 while gm remains constant. this trend appears valid if VCC is also raised to ensure the transistor remains in the active mode. Exercise What happens to this result if the supply voltage is halved? Inclusion of Early Effect Equation (5.131) (5. we have Av = .cls v. then the voltage gain is automatically set. Rout : Rin (5.33 summarizes the trade-offs in the performance of the CE topology along with the parameters that create such trade-offs. What is the voltage gain of the circuit? Since Rin Example 5.33 CE stage trade-offs. From an intuitive point of view.gmRC = . Mentioned in Section 4. We will develop other circuits in this book that avoid this “coupling” of design speciﬁcations.5. a given change in the input voltage and hence the collector current gives rise to an increasingly larger output swing as RC increases. . 2006] June 30.129) (5. RC is ﬁxed and the voltage gain can be increased by increasing IC . Figure 5.gm RC . Rout = vX iX = RC : (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. thereby lowering both the voltage headroom and the input impedance. if the I/O impedances are speciﬁed. Voltage Headroom (Swings) g m Voltage Gain RC Output Impedance RC Input Impedance β gm Figure 5.20 Solution = r = =gm and Rout = RC . 5.130) The output impedance therefore trades with the voltage gain. In other words. A CE stage must achieve an input impedance of Rin and an output impedance of Rout .

142) (5.34 depicts the small-signal equivalent circuit of the CE stage including the transistor output resistance. the Early effect limits the voltage gain even if RC approaches inﬁnity.137) (5. 2006] June 30.21 = 100 Solution We have I gm = VC T and (5. Figure 5. 5.140) = 1.139) (5.gmRC jjrO 35: (As a comparison. Note that rO appears in parallel with RC .136) = 26 . if VA (5. Example 5.29 is biased with a collector current of 1 mA and RC = 1 k .143) . 2007 at 13:42 206 (1) 206 Chap.1 rO = VA I C Thus. 5 Bipolar Ampliﬁers In reality. determine the small-signal voltage gain and the I/O impedances. however. we write Rin = r =g m = 2:6 k (5. we must reexamine the above derivations in the presence of the Early effect. (5. If and VA = 10 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.gm RC jjrO : (5.135) (5.34 CE stage including Early effect.) For the I/O impedances. allowing us to rewrite (5.133) We also recognize that the input impedance remains equal to r whereas the output impedance falls to Rout = RC jjrO : v in rπ vπ g vπ m rO RC v out (5.141) (5. then Av 38.cls v.138) = 10 k : Av = . The circuit of Fig.114) as Av = .134) Figure 5. Since achieving a high gain proves critical in circuits such as operational ampliﬁers.

35(a). But with RE 6= 0. In modern integrated bipolar transistors. We rarely deal with this parameter for voltage ampliﬁers. we assume gm rO 1 (and hence rO 1=gm) for all transistors.35(b)].3 Bipolar Ampliﬁer Topologies 207 and Rout = RC jjrO = 0:91 k : (5. some fraction of V appears across RE .144) (5. in (5.147) Called the “intrinsic gain” of the transistor to emphasize that no external device loads the circuit. CE Stage With Emitter Degeneration In many applications. where a resistor RE appears in series with the emitter. 5. We now substitute gm = IC =VT and rO gm rO represents the maximum voltage gain provided by a single transistor. but note that AI = for the stage shown in Fig. it is instructive to make some qualitative observations. the collector current change is also less than gm V . producing a collector current change of gm V . 2007 at 13:42 207 (1) Sec.29 because the entire collector current is delivered to RC . Another parameter of the CE stage that may prove relevant in some applications is the “current gain. Suppose the input signal raises the base voltage by V [Fig.cls v. the intrinsic gain of a bipolar transistor is independent of the bias current. thereby arriving at T (5.29 is modiﬁed as shown in Fig. We therefore expect that the voltage gain of 7 But other second-order effects limit the actual gain to about 50. Let us determine the gain of a CE stage as RC ! 1. (5.7 In this book. 5.133) gives (5. If RE were zero. assuming Q1 is biased properly.” this technique improves the “linearity” of the circuit and provides many other interesting properties that are studied in more advanced courses.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As with the CE core. Equation (5. then the base-emitter voltage would also increase by V . 5.gmrO : role in high-gain ampliﬁers. .148) where iout denotes the current delivered to the load and iin the current ﬂowing to the input. thus leaving a voltage change across the BE junction that is less than V . we intend to determine the voltage gain and I/O impedances of the circuit. Consequently. playing a fundamental = VA =IC in Eq. 2006] June 30.145) Exercise Calculate the gain if VA = 5 V. 5. the CE core of Fig. VA falls in the vicinity of 5 V.” deﬁned as AI = iiout . Before delving into a detailed analysis. Called “emitter degeneration. 5. yielding a gain of nearly 200. jAv j = VA : V Interestingly.146) Av = .133).

but as explained below. To determine vout =vin .35 (a) CE stage with degeneration. yielding an input impedance greater than =gm = r . Thus. gvout : R m C (5. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we have vin = v + vRE . the voltage drop across RE is given by vRE = r + gm v RE : Since the voltage drop across r and RE must add up to vin . the degenerated stage is lower than that of the CE core with no degeneration. vout .cls v. 5 VCC RC Vout Bipolar Ampliﬁers ∆V RE Q1 (a) (b) Figure 5.36 is the small-signal equivalent circuit. (b) effect of input voltage change. Thus.36 Small-signal model of CE stage with emitter degeneration. While undesirable. gm v = .149) v = . where VCC is replaced with an ac ground and the Early effect is neglected. a desirable property. v out v in rπ vπ RE g vπ m RC Figure 5. A common mistake is to conclude that Rin = r + RE . We now quantify the foregoing observations by analyzing the small-signal behavior of the circuit.150) We also recognize that two currents ﬂow through RE : one originating from r equal to v =r and another equal to gm v . 5. Rin = r + + 1RE . the base current also changes by less than gm V= . R C obtaining (5. Depicted in Fig. emitter degeneration increases the input impedance of the CE stage. the reduction in gain is incurred to improve other aspects of the performance. Note that v appears across r and not from the base to ground. 2007 at 13:42 208 (1) 208 VCC RC Vout V in RE Q1 Chap. How about the input impedance? Since the collector current change is less than gm V . we ﬁrst write a KCL at the output node.

= v + v + gm v RE r .

151) (5. v (5.152) (5.153) .

150) and rearranging the terms.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we arrive at . 2007 at 13:42 209 (1) Sec. 5.cls v. 2006] June 30.3 Bipolar Ampliﬁer Topologies 209 = v 1 + r1 + gm RE : Substituting for v from (5.

. (5.154) vout = .

VCC RC v out v in RE rπ2 (a) (b) VCC RC VCC v in Q2 RE rπ2 Q1 v out Q1 Figure 5. 5. To arrive at an interesting interpretation of Eq. gm RC : vin 1 + r1 + gm RE As predicted earlier. Av = . 1 RC : gm + RE (5. the gain falls by a factor of 1 + gm RE . (5.22 Determine the voltage gain of the stage shown in Fig. we divide the numerator and denominator by gm .7). we can assume gm 1=r and hence (5.37(a). with the understanding that it must be included. This transistor is degenerated by two devices: RE and the base-emitter junction of Q2 .37 (a) CE stage example.) This and similar interpretations throughout this book greatly simplify the analysis of ampliﬁers—often obviating the need for drawing smallsignal circuits. 5. 1 +m RC : g R m E Thus.37(b). The latter exhibits an impedance of r2 (as illustrated in Fig.156).157) It is helpful to memorize this result as “the gain of the degenerated CE stage is equal to the total load resistance seen at the collector (to ground) divided by 1=gm plus the total resistance placed in series with the emitter. we often ignore the negative sign in the gain.155) 6= 0.156) g Av = . With (5. The total resistance placed in series with the emitter is Solution .” (In verbal descriptions. (b) simpliﬁed circuit. Example 5. 5. the magnitude of the voltage gain is lower than gm RC for RE 1. leading to the simpliﬁed model depicted in Fig. We identify the circuit as a CE stage because the input is applied to the base of Q1 and the output is sensed at its collector.

we have .158) Without the above observations. Since v = r iX . we reduce the circuit to that shown in Fig. yielding Av = . where the total load resistance seen at the collector of Q1 is equal to RC jjr2 . To compute the input impedance of the degenerated CE stage.38(b).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Summing v and vRE and equating the result to vX . the current ﬂowing through RE is equal to iX + gm r iX = 1 + iX . 5.cls v. The voltage gain is thus given by Solution Av = . 5 Bipolar Ampliﬁers therefore equal to RE jjr2 . (b) The topology is a CE stage degenerated by RE . (b) simpliﬁed circuit. 2006] June 30. we redraw the small-signal model as in Fig. 5.38(a). we would need to draw the small-signal model of both Q1 and Q2 and solve a system of several equations.159) Exercise Repeat the above example if a resistor is placed in series with the emitter of Q2 . Modeling the latter by r2 .38 (a) CE stage example. Example 5. Exercise Repeat the above example if a resistor is placed in series with the emitter of Q2 .39(a) and calculate vX =iX . but the load resistance between the collector of Q1 and ac ground consists of RC and the base-emitter junction of Q2 . 2007 at 13:42 210 (1) 210 Chap. RC jjr2 : 1 gm1 + RE (5. VCC RC v out v in RE Q1 Q2 RE VCC v in Q1 rπ2 VCC RC v out (a) Figure 5. 1 RC : + RE jjr2 gm1 (5. creating a voltage drop of RE 1 + iX .23 Calculate the voltage gain of the circuit in Fig. 5.

but in the circuit of Fig. emitter degeneration increases the input impedance [Fig. Does the factor + 1 bear any intuitive meaning? We observe that the ﬂow of both base and collector currents through RE results in a large voltage drop.40 Output impedance of degenerated stage. + 1iX RE .153) applies to this circuit as well: iX rπ vπ v RE P RE g vπ m RC vX (a) Figure 5. The above observation is articulated as follows: any impedance tied between the emitter and ground is multiplied by + 1 when “seen from the base.161) (5.39 (a) Input impedance of degenerated CE stage. 5. Why is Rin not simply equal to r + RE ? This would hold only if r and RE were exactly in series.3 Bipolar Ampliﬁer Topologies iX vX rπ vπ v RE P RE g vπ m RC iX vX R in ( β +1) R E 211 v out rπ (a) (b) Figure 5. 5. where the input voltage is set to zero. vX = r iX + RE 1 + iX . yielding v = 0 and hence gm v = 0. Equation (5..40.e. and hence (5. vX .39(b)]. and Rout = vX iX = RC . 5. vin = 0 = v + r + gmv RE . the test voltage source. (b) equivalent circuit.160) Rin = vX iX = r + + 1RE : (5. supplies a current of only iX while producing a voltage drop of + 1iX RE across RE —as if iX ﬂows through a resistor equal to + 1RE . . 5. 2006] June 30. gm v . if the two carried equal currents. all of iX ﬂows through RC . Thus. In other words.162) As predicted by our qualitative reasoning. We also calculate the output impedance of the stage with the aid of the equivalent shown in Fig. the collector current.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. also ﬂows into node P .” The expression “seen from the base” means the impedance measured between the base and ground.39(a). even though the current drawn from vX is merely iX . i.cls v. 2007 at 13:42 211 (1) Sec.

164) (5. v (5.163) (5.165) .

24 A CE stage is biased at a collector current of 1 mA.168) RE = g1 The input impedance is given by = 26 : m (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Finally. For Av Solution = 20 in the absence of degeneration. RE .166) = IC =VT = 26 . 2006] June 30. 5 Bipolar Ampliﬁers revealing that emitter degeneration does not alter the output impedance if the Early effect is neglected.173) . determine RC . 5. Assume = 100. and the I/O impedances. If the circuit provides a voltage gain of 20 with no emitter degeneration and 10 with degeneration.cls v.41. together with gm (5. (5. which. Rin = 5200 Rout = RC = 520 : Exercise What bias current would result in a gain of 5 with such emitter and collector resistor values? Example 5. yields RC = 520 : Since degeneration lowers the gain by a factor of two.175) 1 and RE = 1=gm in this example.174) (5. Assume a very large value for C1 . (5.170) Rin = r + + 1RE = g + + 1RE m 2r because (5.1 . . Example 5. Thus. i. (5.172) (5.167) 1 + gm RE = 2. we require gm RC = 20.171) (5.e.169) (5. 2007 at 13:42 212 (1) 212 Chap..25 Compute the voltage gain and I/O impedances of the circuit depicted in Fig.

iout = gmv = gm and hence . Let us place the transistor and the emitter resistor in a black box having still three terminals [Fig. 5.154) still holds. Thus.42(b). (5. 2007 at 13:42 213 (1) Sec. 2006] June 30. we can view the box as a new transistor (or “active” device) and model its behavior by new values of transconductance and impedances.157). Also. 5. Since Eq. (5.165) apply. it acts as a short circuit for the signal frequencies of interest. If C1 is very large. the constant current source is replaced with an open circuit in the small-signal equivalent circuit. Denoted by Gm to avoid confusion with gm of Q1 . 5.cls v. (5. 1 + r 1 + gm RE vin (5.178) . (b) small-signal equivalent.176) .42(a)]. (5. The degenerated CE stage can be analyzed from a different perspective to provide more insight. 5. the equivalent transconductance is obtained from Fig. we have i out rπ vπ RE g vπ m i out v in Q1 RE v in (a) (b) Figure 5.41 CE stage example.177) Gm = ivout in (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.35(a) and Eqs. the stage reduces to that in Fig.162).3 Bipolar Ampliﬁer Topologies 213 VCC RC Vout V in RE Constant Q1 C1 Figure 5. (5. For small-signal operation. Solution Exercise Repeat the above example if we tie another capacitor from the base to ground.42 (a) Degenerated bipolar transistor viewed as a black box.

The resulting voltage divider yields r + + 1RE vA vin = r + + 1RE + RB : Combining (5. we arrive at the overall gain as (5.43(b). 2006] June 30.39(b). VCC RC v in RB A RE v out Q1 v in RB rπ ( β +1) R E A (a) (b) Figure 5.43 (a) CE stage with base resistance. An interesting property of the degenerated CE stage is that its voltage gain becomes relatively independent of the transistor transconductance and hence bias current if gm RE 1. or (b) recognize that the signal at node A is simply an attenuated version of vin and write vout = vA vout : vin vin vA (5. (5.162) and the model depicted in Fig.155) and (5.157). as illustrated in Fig. As a more general case. (b) equivalent circuit. Let us ﬁrst compute vA =vin with the aid of Eq.180) Here.Gm RD . As seen below. RB may represent the output resistance of a microphone connected to the input of the ampliﬁer. From Eq.cls v. To analyze the small-signal behavior of this stage.43(a)].155) and (5. (5. As studied in Problem 40. 5. RB only degrades the performance of the circuit. 2007 at 13:42 214 (1) 214 Chap. 5 Bipolar Ampliﬁers 1 + gm R : g m E (5.157).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we can adopt one of two approaches: (a) draw the small-signal model of the entire circuit and solve the resulting equations. (5.RC =RE under this condition. For example. and vout =vA represents the voltage gain from the base of Q1 to the output. we now consider a degenerated CE stage containing a resistance in series with the base [Fig.181) vout = r + + 1RE . this trend in fact represents the “linearizing” effect of emitter degeneration. the voltage gain of the stage with a load resistance of RD is given by .179) For example. but often proves inevitable.157). vA =vin denotes the effect of voltage division between RB and the impedance seen at the base of Q1 . We leave the former approach for Problem 44 and continue with the latter here. as already obtained in Eqs. 5. 5. we note that Av ! .

gmRC vin r + + 1RE + RB 1 + 1 + g R r m E r + 1 m = r ++ + 1R RER r .184) . 1R + R : + E B (5. .182) (5.183) (5.g1 r RCR E+ B + + E RC = r + .

2006] June 30. we can deﬁne two different input impedances.cls v. We also note that the output impedance of the circuit remains equal to Rout = RC even with RB (5. but RB is scaled down by + 1. 5.186) Rin2 = RB + r + + 1RE : (5. The following quantities are obtained: RB 104 . (5. 5. we divide the numerator and the denominator by : Av 1 . From Eq.185) Compared to (5. The above results reveal that resistances in series with the emitter and the base have similar effects on the voltage gain.RC RB : gm + RE + + 1 (5. jAv j = 20. (5. one seen at the base of Q1 and another at the left terminal of RB (Fig.1 . 2007 at 13:42 215 (1) Sec.185). Assume RE = 4=gm and = 100. Rin1 proves more relevant and useful.44 Input impedances seen at different nodes. Rin1 = r + + 1RE and the latter.44). Design a CE stage with a bias current of 1 mA that ampliﬁes this signal to 40 mV. this result contains only one additional term in the denominator equal to the base resistance divided by + 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.43(a).187) In practice. and RE = RC = jAv j g1 + RE + RB1 + m 2:8 k : .3 Bipolar Ampliﬁer Topologies 215 To obtain a more intuitive expression. 5. The signiﬁcance of this observation becomes clear later. gm = 26 .157). This is studied in Problem 45.26 A microphone having an output resistance of 1 k generates a peak signal level of 2 mV. For the stage of Fig. The former is equal to VCC RC RB Q1 R in2 R in1 RE v out Figure 5. Example 5.188) 6= 0. Solution = 1 k .

(5.190) .189) (5.

Somewhat beyond the scope of this book. 5 Bipolar Ampliﬁers Exercise Repeat the above example if the microphone output resistance is doubled. (b) simpliﬁed circuit. I1 with an open circuit. as it provides the foundation for many other topologies studied later. and VCC with ac ground. 5. the output resistance.185)-(5. where R1 and RC appear in parallel and R2 acts as an emitter degeneration resistor. 5. VCC RC v in RB Q1 v out R1 R2 I1 (a) (b) RC v in RB Q1 R2 v out R1 C1 Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.27 Determine the voltage gain and I/O impedances of the circuit shown in Fig.193) Exercise What happens if a very large capacitor is tied from the emitter of Q1 to ground? Effect of Transistor Output Resistance The analysis of the degenerated CE stage has thus far neglected the Early effect. Replacing C1 with a short circuit.45(b).RC jjR1RB gm + R2 + + 1 Rin = RB + r + + 1R2 Rout = RC jjR1 : (5.45 (a) CE stage example.45(a).192) (5. Equations (5. the derivation of the circuit properties in the presence of this effect is outlined in Problem 48 for the interested reader. namely.cls v. Example 5.191) (5. we arrive at the simpliﬁed model in Fig. We nonetheless explore one aspect of the circuit. Assume a very large value for C1 and neglect the Early effect. 2007 at 13:42 216 (1) 216 Chap.188) are therefore written respectively as Solution Av = 1 . 2006] June 30. .

195) (5. R out V in RE Q1 rπ vπ P RE iX g vπ m iX rO vX (a) (b) Figure 5.200) for two special cases RE r and RE r .202) . We readily note that RE and r appear in parallel.46(a)]. Since gm v ﬂows from the output node into P . 5. (5. and the current ﬂowing through RE jjr is equal to iX .194) where the negative sign arises because the positive side of v is at ground.v ) and equating the result to vX . emitter degeneration raises the output impedance from rO to the above value. v = iX + gm iX RE jjr rO + iX RE jjr : It follows that (5. gm v rO . v = ..198) 1. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The “boosting” of output resistance as a result of degeneration proves extremely useful in circuit design.cls v.46(b). These concepts are studied in Chapter 9. resistors rO and RE are not in series. Adding this voltage to that across RE (= . we draw the small-signal equivalent circuit as in Fig. by a factor of 1 + gm RE jjr .201) (5. 2006] June 30. 5. (5. 2007 at 13:42 217 (1) Sec. 5. A common mistake here is to write Rout = rO + RE . i. gm v and hence sustains a voltage of iX . To include the Early effect.197) (5. Also. (b) equivalent circuit. We also recognize that rO carries a current of iX .199) (5.7 that Rout = rO if RE = 0. The reader may wonder if the increase in the output resistance is desirable or undesirable. Recall from Fig. conferring ampliﬁers with a higher gain as well as creating more ideal current sources. Rout = 1 if VA = 1 (why?). gm v rO . grounding the input terminal.e. gm rO (5.3 Bipolar Ampliﬁer Topologies 217 Our objective is to determine the output impedance seen looking into the collector of a degenerated transistor [Fig.200) Rout rO + gm rO RE jjr rO 1 + gm RE jjr : Interestingly.46 (a) Output impedance of degenerated stage.146) that the intrinsic gain of the transistor.196) Rout = 1 + gm RE jjr rO + RE jjr = rO + gm rO + 1RE jjr : Recall from (5. It is instructive to examine (5. we have RE jjr ! r and Rout rO 1 + gm r rO .iX RE jjr . we obtain vX = iX . 5. For RE r . and hence (5.

we arrive at the simpliﬁed Example 5.cls v. Replacing Vb and C1 with an ac ground and I1 with an open circuit.204) RE = g1 Note that indeed r = 26 : m (5.47). the maximum resistance seen at the collector of a bipolar transistor is equal to rO —if the degeneration impedance becomes much larger than r . degeneration must raise the output resistance by a factor of two.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.206) = =gm RE . In the analysis of circuits. 2007 at 13:42 218 (1) 218 Chap.47 Stage with explicit depiction of rO . 5 Bipolar Ampliﬁers because 1. of course. (5. Thus. 5. the output resistance is boosted by a factor of 1 + gm RE . we have RE jjr ! RE and Rout 1 + gmRE rO : (5. This representation.203) Thus. The available bipolar transistor exhibits = 100 and VA = 10 V. we sometimes draw the transistor output resistance explicitly to emphasize its signiﬁcance (Fig. R out Q1 V in RE rO Figure 5. assumes Q1 itself does not contain another rO . Since rO = VA =IC = 10 k .48(a) if C1 is very large. Example 5.29 Solution . We postulate that the condition RE r holds and write Solution 1 + gm RE = 2: That is. 2006] June 30. Exercise What is the output impedance if RE is doubled? Calculate the output resistance of the circuit shown in Fig.28 We wish to design a current source having a value of 1 mA and an output resistance of 20 k . Determine the minimum required value of emitter degeneration resistance. For RE r .205) (5. 5.

49(a).cls v. Recall from Fig.209) Exercise What is the output resistance if a very large capacitor is tied between the emitter of ground? Q1 and The procedure of progressively simplifying a circuit until it resembles a known topology proves extremely critical in our work. yielding a zero gm2 v2 . In analogy with Fig.30 Determine the output resistance of the stage shown in Fig. we rewrite Eq.7 that the impedance seen at the collector is equal to rO if the base and emitter are (ac) grounded. 5. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Called “analysis by inspection.40.48(b). Now. 5. (c) resistance seen at the collector. 5. 2006] June 30.48 (a) CE stage example.40(a).210) . 5. In analogy with Fig.48(b). we ignore R1 for the moment.200) as Rout1 = 1 + gm R2 jjr rO : Returning to Fig. Q2 is reduced to rO2 because its base-emitter voltage is ﬁxed by Vb1 . 5. model in Fig. we rewrite Eq.” this method obviates the need for complex small-signal models and lengthy calculations. reducing the circuit to that in Fig. 2007 at 13:42 219 (1) Sec. rO2 plays the role of emitter degeneration resistance for Q1 . From another perspective. 5. The reader is encouraged to attempt the above example using the small-signal model of the overall circuit to appreciate the efﬁciency and insight provided by our intuitive approach. 5.48(c). 5. (5. (b) simpliﬁed circuit.200) as Solution Rout = 1 + gm1rO2 jjr1 rO1 : (5.49(b)].207) Rout = Rout1 jjR1 = f 1 + gm R2 jjr rO g jjR1 : (5. Example 5. (5. we have (5. Q2 can be replaced with rO2 [Fig. 5.3 Bipolar Ampliﬁer Topologies R out R out R out1 219 Q1 Vb R1 R2 C1 Q1 R2 R1 Q1 R2 I1 (a) (b) (c) Figure 5. Since R1 appears in parallel with the resistance seen looking into the collector of Q1 .208) (5.

We begin with simple biasing schemes described in Section 5. this topology is studied and utilized extensively in Chapter 9.5 V 100 k Ω RB X RC 1 kΩ Vout Q1 Figure 5. 2007 at 13:42 220 (1) 220 R out Chap. we now study a more general case wherein the circuit contains a bias network as well. If used in this circuit. 5 Bipolar Ampliﬁers R out Q1 V b2 Q1 r O2 Q2 V b1 (a) (b) Figure 5. failing to amplify. Many microphones exhibit a small low-frequency resistance (e. 100 ). Let us begin with an example. Called a “cascode” circuit. the microphone low-frequency resistance disrupts the bias of the ampliﬁer. CE Stage with Biasing Having learned the small-signal properties of the common-emitter ampliﬁer and its variants.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. VCC = 2.50 Microphone ampliﬁer. Exercise Repeat the above example for a “stack” of three transistors. Example 5. forming a voltage divider with RB and providing a very low base voltage.. 2006] June 30.212) . (b) simpliﬁed circuit.2 and progressively add complexity (and more robust performance) to the circuit. a microphone resistance of 100 yields Solution VX = 100 k100 100 2:5 V + 2:5 mV: Thus. For example.g. Q1 carries no current. 5. Unfortunately. such a microphone creates a low resistance from the base of Q1 to ground.211) (5. (5.31 A student familiar with the CE stage and basic biasing constructs the circuit shown in Fig.50 to amplify the signal produced by a microphone.49 (a) CE stage example. Explain the cause of this problem.

5.213) . For bias calculations. we have VCC RB X C1 (a) VCC RB RC X Y Q1 v in X Q1 RB RC v out RC Y Q1 Vout (b) (c) Q1 RB R in2 R in1 (d) RC RB Q1 RC R out (e) Figure 5.52(a). .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5.cls v. 5.50 be ﬁxed? Since only the signal generated by the microphone is of interest. the bias point of Q1 remains independent of the resistance of the microphone because C1 carries no bias current. The value of C1 is chosen so that it provides a relatively low impedance (almost a short circuit) for the frequencies of interest. That is. B (5. From Section 5.5 V 100 k Ω RB X RC 1 kΩ Vout Q1 C1 Figure 5.51 Capacitive coupling at the input of microphone ampliﬁer. 5.1. The foregoing observation suggests that the methodology illustrated in Fig. (b) simpliﬁed stage for bias calculation. leading to Fig. (c) simpliﬁed stage for small-signal calculation. 5. Let us begin with the stage depicted in Fig. IC = VCCR VBE . 2007 at 13:42 221 (1) Sec.” Many circuits employ capacitors to isolate the bias conditions from “undesirable” effects. 5.51 so as to isolate the dc biasing of the ampliﬁer from the microphone.9 must include an additional rule: replace all capacitors with an open circuit for dc analysis and a short circuit for small-signal analysis.52 (a) Capacitive coupling at the input of a CE stage. a series capacitor can be inserted as depicted in Fig.52(b). the signal source is set to zero and C1 is opened. 2006] June 30.3 Bipolar Ampliﬁer Topologies 221 Exercise Does the circuit operate better if RB is halved? How should the circuit of Fig. (e) simpliﬁed circuit for output impedance calculation. VCC = 2.2. (d) simpliﬁed circuit for input impedance calculation. We say C1 is a “coupling” capacitor and the input of this stage is “ac-coupled” or “capacitively-coupled. More examples clarify this point later.

7 that the impedance seen looking into the base. 2007 at 13:42 222 (1) 222 Chap. we have vout = .29. C1 is replaced with a short and VCC with ac ground.5 V 100 k Ω RB X RC 1 kΩ C1 Q1 Figure 5. vX = vin regardless of the value of RB . 5. Here. Example 5. the student in Example 5. negligibly impacts the performance of the stage shown in Fig. then Thus.52(e)]. We now turn our attention to small-signal analysis.. We attempt to solve the circuit by inspection: if unsuccessful.52(c) resembles the CE core illustrated in Fig. Interestingly. Explain why. 5. Comparing this circuit with that in Fig. .53 and attempts to drive a speaker. this effect is usually negligible. RC VCCR VBE : B (5. Nevertheless.cls v.52(a). VCC = 2. VY = VCC .216) m C O vin However.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the input impedance is affected by RB [Fig. 5. RB .gm RC . Recall from Fig. Rin1 .214) To avoid saturation. the bias resistor. and rO can be calculated. 5.g R jjr : (5. but Q1 is maintained as a symbol. Unfortunately. Here. 5. is equal to r if the emitter is grounded. Since the voltage gain from the base to the collector is given by vout =vX = . the bias resistor lowers the input impedance. the small-signal parameters gm . yielding Rin2 = r jjRB : (5. r . The circuit of Fig. RB has no effect on the voltage at node X so long as vin remains an ideal voltage source. RB simply appears in parallel with Rin1 .e. as shown in Problem 51.215) vout = .32(b). 2006] June 30. 5.52(d)].217) 1.53 Ampliﬁer with direct connection of speaker. we recognize that Rout remains unchanged: Rout = RC jjrO : (5.31 modiﬁes the design to that shown in Fig. 5. In summary. 5. With the bias current known.52(c).218) because both terminals of RB are shorted to ground. we will resort to using a small-signal model for Q1 and writing KVLs and KCLs.32 Having learned about ac coupling. i. the circuit still fails. 5. 5 Bipolar Ampliﬁers . To determine the output impedance. we set the input source to zero [Fig. considering the simpliﬁed circuit of Fig.g R : m C vin If VA (5. VY VBE . except for RB .

5 V translates to a voltage drop of 1 V across collector current of 1 mA. The solenoid exhibits a very low dc resistance. e. the speaker in Fig. 2007 at 13:42 223 (1) Sec. (a) If IS = 5 10.219) (5. Thus. Thus.33 The student applies ac coupling to the output as well [Fig.g. compute the of the transistor. (b) Speakers typically exhibit a low impedance in the audio frequency range.222) and = IC =IB = 58:8.54 (a) Ampliﬁer with capacitive coupling at the input and output.g. the student still observes no gain in the circuit.221) (5. (5.53 shorts the collector to ground.5 V. IB = VCCR VBE B = 17 A.cls v.54(b). 5. Solution (a) A collector voltage of 1. 5. 5. Exercise Does the circuit operate better if the speaker is tied between the output node and VCC ? Example 5. driving Q1 into deep saturation.220) .. less than 1 .223) . RC and hence a VBE = VT ln IC IS = 796 mV: It follows that (5. indicating that Q1 operates in the active region.54(a)] and measures the quiescent points to ensure proper biasing.5 V 100 k Ω 1 kΩ RB X RC v out 100 k Ω C1 (a) Q1 C2 Q1 RB RC 1 k Ω R sp 8Ω v in (b) Figure 5.3 Bipolar Ampliﬁer Topologies 223 Solution Typical speakers incorporate a solenoid (inductor) to actuate a membrane. 2006] June 30. 5. yielding a gain of jAv j = gmRC jjRS = 0:31 (5.17 VCC = 2. we note that the total resistance seen at the collector node is equal to 1 k jj8 . (b) simpliﬁed small-signal model. The collector bias voltage is 1. e. A and VA = 1. 8 . (b) Explain why the circuit provides no gain. However. Drawing the ac equivalent as in Fig..BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

3.225). For small-signal analysis. 5. 5.224) The output resistance is equal to RC jjrO .RC . degeneration also lowers .56(a) along with an input coupling capacitor.15 and repeated in Fig. we can interpose a “buffer” stage between the CE ampliﬁer and the speaker (Section 5.gm RC jjrO and the input impedance is given by VCC R1 RC Q1 R2 v in Q1 R1 R2 RC v out v in C1 (a) (b) Figure 5. This is studied in Problem 53. the input impedance is lowered to: Rin = r + + 1RE jjR1 jjR2 . except that both R1 and R2 appear in parallel with the input. How can we remedy the problem of loading here? Since the voltage gain is proportional to gm .cls v. Equations (5.55 (a) Biased stage with capacitive coupling.3). The design in Fig.52) and (5. Alternatively.53).38)-(5. gm + RE (5.52(b). the simpliﬁed circuit in Fig. On the other hand.2. repeated in Fig.56(b). 5 Bipolar Ampliﬁers Exercise Repeat the above example for RC = 500 . To determine the bias conditions. (5. We also construct the simpliﬁed ac circuit shown in Fig. Thus. 5. However. 5.3. we can bias Q1 at a much higher current to raise the gain. the voltage gain is still equal to . (5. Let us now consider the biasing scheme shown in Fig.55(a). 5. 2007 at 13:42 224 (1) 224 Chap. we set the signal source to zero and open the capacitor(s).226) As explained in Section 5. 5. the small-signal parameters of Q1 can be computed.54(a) exempliﬁes an improper interface between an ampliﬁer and a load: the output impedance is so much higher than the load impedance that the connection of the load to the ampliﬁer drops the gain drastically. 5. the use of emitter degeneration can effectively stabilize the bias point despite variations in and IS . noting that the voltage gain is not affected by R1 and R2 and remains equal to Av = 1. The bias point is determined by opening C1 and following Eqs.225) where Early effect is neglected.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.55(b) reveals a resemblance to that in Fig. 5.41) can then be used. 2006] June 30. We next study the more robust biasing scheme of Fig. Rin = r jjR1 jjR2 : (5. as evident from (5. (b) simpliﬁed circuit. With the collector current known. whereas the output impedance remains equal to RC if VA = 1.19.

3 Bipolar Ampliﬁer Topologies VCC R1 RC Q1 R2 (a) 225 v out Q1 v in R1 R2 RE RC v in C1 RE (b) Figure 5.57 to satisfy the following conditions: IC = 1 mA. the maximum impedance of C1 must be much smaller than 1=gm = 26 . With IC = 1 mA IE .gm RC and (5. the maximum impedance must remain below roughly 0:1 1=gm = 2:6 : Solution 1 1 1 C2 ! 10 gm for ! = 2 20 Hz: 8 A common mistake here is to make the impedance of (5. Assume = 100. 2006] June 30. the gain.56 (a) Degenerated stage with capacitive coupling. 5. . voltage drop across RE = 400 mV.228) (5. IS = 5 10.229) Design the stage of Fig.227) Rin = r jjR1 jjR2 Rout = RC : Example 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For the voltage gain to remain unaffected by degeneration.8 Occurring at 20 Hz. and VCC = 2:5 V. 5.57 is such a topology. Is it possible to apply degeneration to biasing but not to the signal? Illustrated in Fig. Av = . We can therefore write VCC R1 RC Q1 R2 RE C2 v in C1 Figure 5.34 (5. 5.57 Use of capacitor to eliminate degeneration. voltage gain = 20 in the audio frequency range (20 Hz to 20 kHz).230) C1 much less than RE .cls v. (b) simpliﬁed circuit. where C2 is large enough to act as a short circuit for signal frequencies of interest. 2007 at 13:42 225 (1) Sec.16. the value of RE is equal to 400 . input impedance 2 k .

For example. (5. VCC R1 + R2 and 5IB (5. at the cost of creating more sensitivity to .237) (5. (5.236) R2 = 11:4 k R1 = 13:6 k : We must now check to verify that this choice of R1 and R2 satisﬁes the condition Rin That is.240) Unfortunately. obtaining (5. requiring modiﬁcation of the design. 2007 at 13:42 226 (1) 226 Chap. C2 6120 F: (This value is unrealistically large.233) Since the voltage across RE is equal to 400 mV and VBE = VT lnIC =IS = 736 mV.239) (5. R1 and R2 lower the input impedance excessively.234) R1 + R2 25 k : Under this condition.) We also have (5.231) jAv j = gm RC = 20. with a base current of 10 A. we have VX = 1:14 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5 Bipolar Ampliﬁers Thus.235) VX R R2 R VCC = 1:14 V.241) R1 + R2 50 k : (5. To remedy the problem.232) RC = 512 : (5. 1+ 2 yielding (5.242) .238) 2k . Also. if this current is set to 5IB = 50 A and we still neglect IB in the calculation of VX . Rin = r jjR1 jjR2 = 1:85 k : (5. 2006] June 30. the current ﬂowing through R1 and R2 must exceed 100 A to lower sensitivity to : VCC R1 + R2 and hence 10IB (5. we can allow a smaller current through R1 and R2 than 10IB .cls v.

2007 at 13:42 227 (1) Sec.243) (5.58(a). VCC R1 RS v in C1 Q1 R2 (a) RC C2 RL v out v in RS R1 R2 v out X Q1 RE RC RL RE (b) RS v in R1 R2 v out X Q1 RE RC RL (b) Figure 5. R jjRjjjj 2 jj + + + 1R R+ R RC jjRL : 1 2 r E S 1 + RE gm (5. where the input signal source exhibits a ﬁnite resistance and the output is tied to a load RL . 5. (c) Thevenin model of input network.cls v.58(b) reveals Vin is attenuated by the voltage division between RS and the impedance seen at node X .. 5. giving (5.244) Rin = 2:14 k : (5.e.247) (5. The simpliﬁed ac circuit of Fig.58 (a) General CE stage. R1 jjR2 jj r + + 1RE .248) . 5. i.3 Bipolar Ampliﬁer Topologies 227 Consequently.56(a). 2006] June 30. 5.246) vout = vX vout vin vin vX R1 R r + 1 E = . R2 = 22:4 k R1 = 27:2 k . but RS and RL lower the voltage gain vout =vin .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The biasing remains identical to that of Fig. We conclude our study of the CE stage with a brief look at the more general case depicted in Fig. vX = R1 jjR2 jj r + + 1RE : vin R1 jjR2 jj r + + 1RE + RS The voltage gain from vin to the output is given by (5.245) Exercise Redesign the above stage for a gain of 10 and compare the results. (b) simpliﬁed circuit.

The above computation views the input network as a voltage divider.3. the idea is to replace vin . The two approaches described above exemplify analysis techniques used to solve circuits and gain insight. As we will see. but at a slightly faster pace. 5.4.249) (5. Headroom RC Gain RC rO R out A v = − g m (RC r O ) A v . R in A v = − g mR C R out R in R1 C1 R2 RC Q1 R1 R2 RC RE RE C2 Figure 5. lower values of R1 and R2 reduce the gain.251) are identical. we now turn our attention to the “common-base“ (CB) topology. RS and R1 jjR2 with vThev and RThev : R1 vThev = R jjRjjR2R vin 1 2+ S RThev = RS jjR1 jjR2 : The resulting circuit resembles that in Fig. 5 Bipolar Ampliﬁers As expected. the reader may wonder why we study other ampliﬁer topologies. R1 .249). (5. Alternatively. 5. Figure 5.58(c). The reader is encouraged to review Examples 5.cls v.2-5.250) R1 Av = . 5. 1 RC jjRLRThev R jjRjjR2R .59 Summary of concepts studied thus far. . and R2 on the voltage gain. Nearly all of the concepts described for the CE conﬁguration apply here as well.248) and (5. we can utilize a Thevenin equivalent to include the effect of RS . (5.185): (5. 5.43(a) and follows Eq. 2007 at 13:42 228 (1) 228 Chap.28 before proceeding further. The reader is encouraged to prove that (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We therefore follow the same train of thought.59 summarizes the concepts studied in this section. Illustrated in Fig. Neither requires drawing the small-signal model of the transistor because the reduced circuits can be “mapped” into known topologies. their resulting rules illustrated in Fig.7.2 Common-Base Topology Following our extensive study of the CE stage. other conﬁgurations provide different circuit properties that are preferable to those of the CE stage in some applications. 1 2+ S gm + RE + + 1 (5. 2006] June 30. Given the ampliﬁcation capabilities of the CE stage. 5.251) where the second fraction on the right accounts for the voltage attenuation given by Eq. and the possible topologies in Fig.

The input is applied to the emitter and the output is sensed at the collector. 2007 at 13:42 229 (1) Sec.61(a) respond to an input signal?9 If Vin goes up by a small amount V .cls v. Beginning with the output node. Consequently. we equate the current ﬂowing through RC to gm v : . Av = gm RC : (5. however.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this expression is identical to the gain of the CE topology. Analysis of CB Core How does the CB stage of Fig.61(b). As with the CE stage.252) Interestingly. this circuit exhibits a positive gain because an increase in Vin leads to an increase in Vout . .61 (a) Response of CB stage to small input change. the base acts as ac ground and hence as a node “common” to the input and output ports. VCC RC Vout Q1 Vb v in Input Applied to Emitter Output Sensed at Collector Figure 5.60-5. We therefore surmise that the small-signal voltage gain is equal to VCC RC Vout Q1 Vb v in V in (a) g ∆V R C m v out rπ vπ g vπ m RC ∆V (b) Figure 5. Biased at a proper voltage.60 shows the CB stage. (b) small-signal model. we ﬁrst study the core and subsequently add the biasing elements. 5. the collector current falls by gm V .253) 9 Note that the topologies of Figs. Let us conﬁrm the above results with the aid of the small-signal equivalent depicted in Fig. the base-emitter voltage of Q1 decreases by the same amount because the base voltage is ﬁxed.3 Bipolar Ampliﬁer Topologies 229 Figure 5. where the Early effect is neglected. Unlike the CE stage.61(a) are identical even though Q1 is drawn differently. 5. allowing Vout to rise by gm V RC .60 Common-base stage. 2006] June 30. 5. vout = gm v . R C (5. 5.

thereby allowing a maximum voltage drop across RC equal to 1:8 V . Vb must remain higher than the input by about 800 mV. We can then write Av = gmRC = IC RC VT = 17:2: (5. in Fig. VBE . IC = 0:2 mA.259) . For example. the voltage drop across RC cannot exceed VCC . To avoid saturation. Similar to the CE stage limitation. and = 100. the voltage headroom. Design a CB stage to sense the thermometer voltage and amplify the change with maximum gain. Thus.258) (5. IS = 5 10. Solution Illustrated in Fig. 2007 at 13:42 230 (1) 230 Chap.cls v. We ﬁrst examine the circuit’s headroom limitations. then the output must not fall below approximately 800 mV. this condition translates to VCC RC VCC − V BE ~0V ~800 mV 800 mV 0 Vb t V in Figure 5. 5. Vb .62). 5. 1:354 V = 0:446 V..254) vout = g R : vin m C As with the CE stage. and the output must remain higher than or equal to Vb . the CB topology suffers from trade-offs between the gain.vout =gm RC . Thus. VBE : = VT Example 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we recognize that v It follows that = . the collector voltage must not fall below the base voltage. 5 Bipolar Ampliﬁers obtaining v = .35 (5. and the I/O impedances. Considering the input node next. Assume VCC = 1:8 V. 2006] June 30.257) (5.17 A. if the dc level of the input is zero (Fig.vin . 5.256) The voltage produced by an electronic thermometer is equal to 600 mV at room temperature. the circuit must operate properly with an input level of 600 mV. (5.63(a).62 Voltage headroom in CB stage. I Av = VC RC T VCC . i.255) (5. Vb = VBE + 600 mV = VT lnIC =IS + 600 mV = 1:354 V. How should the base voltage.e.61(a) be chosen? Recall that the operation in the active region requires VBE 0 and VBC 0 (for npn devices).

262) Exercise Repeat the above example if the thermometer voltage is 300 mV.3 Bipolar Ampliﬁer Topologies VCC RC Vout Q1 Vb Q1 RC Vout IB VCC R1 I1 R2 231 V in 600 mV V in 600 mV Thermometer (a) (b) Figure 5. e.g. Also.cls v. 2006] June 30. Thus. we choose I1 10IB 20 A VCC =R1 + R2 .63(b).7. 5. 26 IC = 1 mA (in sharp contrast to the corresponding value for a CE stage. 2007 at 13:42 231 (1) Sec. (b) bias network for base. we have Rin = g1 m (5. 10 This example serves only as an illustration of the CB stage. The reader is encouraged to repeat the problem with IC = 0:4 mA to verify that the maximum gain remains relatively independent of the bias current.. Let us now compute the I/O impedances of the CB topology so as to understand its capabilities in interfacing with preceding and following stages. The rules illustrated in Fig. obviating the need for small-signal equivalent circuits. =gm). .64(a). R1 + R2 = 90 k . 5.63 (a) CB stage sensing an input.261) (5. From the rules in Fig. A CE stage may prove more suited to sensing a thermometer voltage.10 We must now generate Vb . the simpliﬁed ac circuit reveals that Rin is simply the impedance seen looking into the emitter with the base at ac ground. Vb R R2 R VCC 1+ 2 and hence (5. The input impedance of the CB stage is therefore relatively low. 5. To lower sensitivity to .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 prove extremely useful here. Shown in Fig. 5. A simple approach is to employ a resistive divider as depicted in Fig. 5.260) R2 = 67:7 k R1 = 22:3 k : (5.263) for if VA = 1.

64 (a) Input impedance of CB stage. we have Rout1 = rO and hence Q1 rO ac RC R out1 R out Figure 5. Rin = VX =IX = 1=gm. The input impedance of the CB stage can also be determined intuitively [Fig. Consequently. the current supplied by VX also changes by gm V . where Rout1 is the impedance seen at the collector with the emitter grounded. Rout = rO jjRC (5. 5 VCC RC Bipolar Ampliﬁers Q1 ac IX VX Q1 Vb R in (a) ∆V (b) Figure 5. Suppose a voltage source VX tied to the emitter of Q1 changes by a small amount V . 5. 2007 at 13:42 232 (1) 232 VCC RC Chap.65).66. many stand-alone high-frequency ampliﬁers are designed with an input resistance of 50 to provide “impedance matching” between modules in a cascade and the transmission lines (traces on a printed-circuit board) connecting the modules (Fig.7.11 50− Ω Transmission Line 50− Ω Transmission Line 50 Ω 50 Ω Figure 5. 5. The baseemitter voltage therefore changes by the same amount. The output impedance of the CB stage is computed with the aid of Fig. . We note that Rout = Rout1 jjRC .64(b)]. 5. where the input voltage source is set to zero. For example. indeed.264) 11 If the input impedance of each stage is not matched to the characteristic impedance of the preceding transmission line. From the rules of Fig. Since the collector current ﬂows through the input source.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.65 System using transmission lines. Does an ampliﬁer with a low input impedance ﬁnd any practical use? Yes.66 Output impedance of CB stage. leading to a change in the collector current equal to gm V . corrupting the signal or at least creating dependence on the length of the lines. (b) response to a small change in input.cls v. 5. then “reﬂections” occur. 2006] June 30.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Shown in Fig.256) and (5.265) A common-base ampliﬁer is designed for an input impedance of Rin and an output impedance of Rout . It is instructive to study the behavior of the CB topology in the presence of a ﬁnite source resistance. 5.269) .67. More speciﬁcally. (5.266) Exercise Compare this value with that obtained for the CE stage.254) that the gain from the emitter to the output is given by RS + g1 gm 1 vin (5.267) m (5. Neglecting the Early effect. we have Av = Rout : R in (5. 2006] June 30. 5. we conclude that the CB stage exhibits a set of trade-offs similar to those depicted in Fig. such a circuit suffers from signal attenuation from the input to node X . since the impedance seen looking into the emitter of Q1 (with the base grounded) is equal to 1=gm (for VA = 1). determine the voltage gain of the circuit. 5.266). (5. 2007 at 13:42 233 (1) Sec.36 (5. Since Rin Solution = 1=gm and Rout = RC .33 for the CE ampliﬁer. From Eqs.67 CB stage with source resistance.268) vout = g R : m C vX (5. thereby providing a smaller voltage gain. we have VCC RC v out RS v in Q1 X v in RS X 1 gm 1 gm Figure 5. vX = 1 = 1 + g R vin : m S We also recall from Eq.3 Bipolar Ampliﬁer Topologies 233 or Rout = RC if VA = 1: Example 5.cls v.

load. as described later in this section. Figure 5.274) (5.271) reveals that (5. gm + RS (5.load directly.271) a result identical to that of the CE stage (except for a negative sign) if RS is viewed as an emitter degeneration resistor.273) Av = 1 RC gm + RS = 1: 2 The circuit is therefore not suited to driving a 50. Example 5. 5 Bipolar Ampliﬁers It follows that vout = gm RC vin 1 + gm RS = 1 RC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.load? Assume VA = 1. (5. vin . 1=gm . (5. Determine the required bias current if the input impedance of the ampliﬁer must “match” the impedance of the antenna. it is necessary that the input impedance of the CB core. be equal to RS . RS = 50 . voltage source.275) 12 The dots denote the need for biasing circuitry. .antenna. For impedance matching. (b) equivalent circuit. 2006] June 30.272) (5. then Eq.68 (a) CB stage sensing a signal received by an antenna.68 depicts the ampliﬁer12 and the equivalent circuit with the antenna modeled by a VCC RC v out Antenna Antenna Solution VCC RC v out RS v in Q1 VB Q1 VB Figure 5.37 A common-base stage is designed to amplify an RF signal received by a 50. and hence IC = gm VT = 0:52 mA: If RC itself is replaced by a 50.cls v. 2007 at 13:42 234 (1) 234 Chap. and a resistance. What is the voltage gain if the CB stage also drives a 50.270) (5.

2006] June 30. Rout is equal to RC in parallel with the impedance seen looking into the collector.1. in the above example. IC displays much less dependence on the collector voltage.resistor is also tied from the emitter of Q1 to ground? Another interesting point of contrast between the CE and CB stages relates to their current gains. As with the CE stage. when calculating Rout . 5. it is inVCC RC v out RE v in (a) (b) rO Q1 RB VB RE rO Q1 R out1 RC R out2 Figure 5. . As illustrated in Fig.g..276) Rout = RC jj f 1 + gmRE jjr rO + RE jjr g : (5. Fig. AI = for the CE stage.71(a)]. we may desire to analyze the CB topology in the general case: with emitter degeneration.71. 5. VA 1. iin = vin =RS + 1=gm.5 if RC RS . 5. Is this true in general? Recall that the output impedance is determined by setting the input source to zero. i. and hence given by Eq.197): Rout1 = 1 + gmRE jjr rO + RE jjr : It follows that (5. and a resistance in series with the base [Fig. and we wish to compute the output impedance.e. (b) output impedance seen at different nodes. The CB stage displays a current gain of unity because the current ﬂowing into the emitter simply emerges from the collector (if the base current is neglected). Rout1 ..3 Bipolar Ampliﬁer Topologies 235 Exercise What is the voltage gain if a 50. as illustrated in Fig. 2007 at 13:42 235 (1) Sec. identical values of VA and emitter degeneration). Explain why these tests do not represent practical situations.3. 5. Nevertheless. In fact.69(a)]. which upon ﬂowing through RC . It is therefore no coincidence that the output impedances are identical if the same assumptions are made for both circuits (e. But Rout1 is identical to the output resistance of an emitter-degenerated common emitter stage. Example 5.277) The reader may have recognized that the output impedance of the CB stage is equal to that of the CE stage.cls v. On the other hand. as mentioned in Section 5. this analysis is somewhat beyond the scope of this book. we have no knowledge of the input terminal of the circuit. 5.” This claim is justiﬁed by the tests illustrated in Fig. 5.69(b). injected into the base while the collector voltage is varied. if a constant current is drawn from the emitter.46.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. If a constant current is . (5. In other words. IC exhibits a slope equal to rO 1 [Fig. structive to consider a special case where RB = 0 but VA 1. It is thus not surprising that the voltage gain does not exceed 0.69 (a) General CB stage. Outlined in Problem 64. On the other hand.38 Old wisdom says “the output impedance of the CB stage is substantially higher than that of the CE stage. yields vout = RC vin =RS + 1=gm.70 for CE and CB stages. 5.

IC VCC IB Q1 V1 V1 (a) Open (b) IC IC VB Q1 IE V1 IC V1 rπ vπ g vπ m rO R out rπ vπ g vπ m rO R out Open (c) (d) Figure 5.cls v. each stage may be driven by a voltage source having a ﬁnite impedance. 2006] June 30. From a small-signal point of view. Exercise Repeat the above example if a resistor of value R1 is inserted in series with the emitter. 5.71 (a) Resistance seens at collector with emitter grounded.46) with an inﬁnite emitter resistance. (b) resistance seen at collector with an ideal current source in emitter.278) (5. 5 VCC RC Vb Q1 RE v out Bipolar Ampliﬁers VCC RC Q1 R out RE (b) Figure 5. the current through r is zero. (d) small-signal model of (b). 2007 at 13:42 236 (1) 236 VCC RC Q1 v in RE v out VCC RC Q1 RE R out v in (a) Chap. Fig. much greater than rO .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. exhibiting an output resistance of Rout = 1 + gmRE jjr rO + RE jjr = 1 + gmr rO + r rO + r . Solution The principal issue in these tests relates to the use of current sources to drive each stage. of course. the two circuits reduce to those depicted in Figs. In practice. yielding gm v = 0 and hence Rout = rO . however. 5.71(c) and (d). making the above comparison irrelevant. .280) which is. On the other hand. (c) small-signal model of (a). (5.71(c). 5. In Fig. with current sources IB and IE replaced with open circuits because they are constant.70 (a) CE stage and (b) CB stage simpliﬁed for output impedance calculation.71(d) resembles an emitter-degenerated stage (Fig.279) (5. 5.

As usual.vout =gm RC .vout = RC . 2006] June 30. we write gm v = .69(a) occurs if VA = 1 but RB 0. The current ﬂowing through r (and RB ) is then equal to v =r = .72 to study its behavior. 2007 at 13:42 237 (1) Sec. Multiplying this current by RB + r .cls v. 5. . 5. .282) v + g v = vP . 5.3 Bipolar Ampliﬁer Topologies 237 Another special case of the topology shown in Fig.vout =gmr RC = . we employ the smallsignal model shown in Fig.vout RB + r RC vout R + r : = R B C We also write a KCL at P : (5.vout =RC and hence v = . vin . vP = . r m RE (5. we obtain the voltage at node P : RB rπ vπ P v in RE g vπ m RC v out Figure 5. Since this case does not reduce to any of the conﬁgurations studied earlier.283) that is.281) (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.72 CB stage with base resistance.

still assuming VA = 1. From the small-signal equivalent circuit shown in .v vout R + r .185) for the CE stage.286) vout RC RB + 1 : vin RE + + 1 gm As expected. revealing that. Let us now determine the input impedance of the CB stage in the presence of a resistance in series with the base. the two stages exhibit equal gains. except for a negative sign. Furthermore. this expression is identical to that in (5. we have (5. the gain is positive.284) RC vout = vin + 1RE + RB + r : Dividing the numerator and denominator by (5. Figure 5. RB may arise from the biasing network.1 It follows that out r + gm gm RC = . Note that RB degrades the gain and is not added to the circuit deliberately. v RC B in : RE (5. As explained later in this section.73 illustrates the results.285) + 1.

Fig. r v = . 5. KCL at the input node gives (5. we recognize that r and RB form a voltage divider. thereby producing13 RB rπ vπ g vπ m RC v out vX iX Figure 5.i : X r m Thus. 2007 at 13:42 238 (1) 238 Chap.73 Comparison of CE and CB stages with base resistance. 2006] June 30. 5 Bipolar Ampliﬁers VCC RC RB Q1 v in RE v in v out RB VCC RC v out Q1 RE Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.74.74 Input impedance of CB stage with base resistance.cls v. (5.287) v + g v = .288) . r +R vX : B Moreover.

the base resistance is divided by + 1 when “seen” from the emitter. .291) Note that Rin = 1=gm if RB = 0.1 . where the emitter resistance is multiplied by + 1 13 Alternatively. This is in contrast to the case of emitter degeneration.iX vX = r + RB iX +1 g1 + RB1 : + m (5.7. Interestingly. an expected result from the rules illustrated in Fig.r r + gm r + RB vX = . yielding a voltage of B X B across r .290) (5.289) and (5.r vX =r + RB . 5. the current through r + R is equal to v =r + R .

cls v.291) is simply equal to Solution Req = g 1 + RB1 : + m1 Reducing the circuit to that shown in Fig.76 (a) Example of CB stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.76(b). Figure 5. RB VA = Q1 RB 1 + g m β +1 r π + (β +1) R E VA = Q1 RE Figure 5.292) RX = g 1 + Req1 + m2 1 = g1 + + 1 g1 + m2 m1 .39 Determine the impedance seen at the emitter of identical and VA = 1. (b) simpliﬁed circuit. 5. 5. VCC RB Q1 Q2 R eq RX RC Q2 in Fig. Thus. but with its base tied to a ﬁnite series resistance equal to that seen at the emitter of Q1 . Interestingly. we have (5.76(a) if the two transistors are VCC RB 1 + g m1 β +1 RC v out Q2 RX (b) v out (a) Figure 5. which from Eq.75 Impedance seen at the emitter or base of a transistor. 5. 2007 at 13:42 239 (1) Sec.75 summarizes the two cases. (5. 2006] June 30. The circuit employs Q2 as a common-base device.3 Bipolar Ampliﬁer Topologies 239 when seen from the base. these results remain independent of RC if VA = 1. we must ﬁrst obtain the equivalent resistance Req . Example 5.

. we now extend our analysis to the circuit including biasing.293) (5. An example proves instructive at this point. RB : +1 (5.294) Exercise What happens if a resistor of value R1 is placed in series with the collector of Q1 ? CB Stage with Biasing Having learned the small-signal properties of the CB core.

” VCC RC v out Q1 Vb v in C1 Example 5.31 decides to incorporate ac coupling at the input of a CB stage to ensure the bias is not affected by the signal source.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the student has shorted the signal to ac ground. drawing the design as shown in Fig.5. 2006] June 30.cls v.40 The student in Example 5.41 Figure 5. forcing a zero bias current and hence a zero transconductance. . That is. the design provides no dc path for the emitter current of Q1 . the emitter voltage is equal to zero regardless of the value of vin .78 CB stage with emitter shorted to ground. 5.6. Explain why “haste makes waste. yielding vout = 0. Unfortunately. where no base current can be supported. 2007 at 13:42 240 (1) 240 Chap.78). the student quickly connects the emitter to ground so that VBE = Vb and a reasonable collector current can be established (Fig.77 CB stage lacking bias current. Explain why this circuit does not work. 5. VCC RC Vout Q1 Vb V in C1 Figure 5. Solution As with Example 5. Solution Exercise In what region does Q1 operate if Vb = VCC ? Somewhat embarrassed. 5 Bipolar Ampliﬁers Example 5.77. The situation is similar to the CE counterpart in Example 5.

79(a) is an example.297) 1 = 1 + 1 + g R R : m E S Since vout =vX (5. To resolve this apparent contradiction. (b) inclusion of source resistance.3 Bipolar Ampliﬁer Topologies 241 Exercise Does the circuit operate better if Vb is raised? The above examples imply that the emitter can remain neither open nor shorted to ground. 2006] June 30. Following the analysis illustrated in Fig.295) As with the input biasing network in the CE stage (Fig. 5. the reduction in Rin manifests itself if the source voltage exhibits a ﬁnite output resistance. 5. vout = 1 vin 1 + 1 + gm RE RS gmRC : (5. VCC RC v out 1 gm VCC RC v out Q1 Vb X v in R S C1 R in RE Vb Q1 v in C1 RE RE (a) (b) Figure 5.79(b).67.” Thus. 5. Rin = g1 jjRE : m (5. noting that the latter shunts the input . We recognize that Rin now consists of two parallel components: (1) 1=gm.79 (a) CB stage with biasing. Shown in Fig. thereby requiring some bias element. we must distinguish between the two components 1=gm and RE . such a circuit attenuates the signal.296) = 1 m g jjRE + RS (5. where RE provides a path for the bias current at the cost of lowering the input impedance. seen looking “down. 5. 5. Depicted in Fig. lowering the overall voltage gain. we can write vX Rin vin = Rin + RS 1 g jjRE m (5. The reader may see a contradiction in our thoughts: on the one hand. we view the low input impedance of the CB stage a useful property. on the other hand. 2007 at 13:42 241 (1) Sec.298) = gm RC .58). we consider the reduction of the input impedance due to RE undesirable.299) As usual.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. we have preferred solution by inspection over drawing the small-signal equivalent. seen looking “up” into the emitter (with the base at ac ground) and (2) RE .

we must have RE and hence gm VT : 1 (5. recall from Eq.302) However. then i2 also falls. As shown in Fig.81 (a) CB stage with base bias network.301) That is. 14 In the extreme case. RE = 0 (Example 5. 5 Bipolar Ampliﬁers VCC RC v out i in R S C1 Q1 i2 i1 RE Vb v in Figure 5. (b) use of Thevenin equivalent. then i2 rises. Vb R R2 R VCC : 1+ 2 (5. Vb . with only i2 reaching RC and contributing to the output signal. 2007 at 13:42 242 (1) 242 Chap. 5. (5.14 Thus. (c) effect of bypass capacitor. iin splits two ways.80. For RE to affect the input impedance negligibly.81(b). 2006] June 30. Shown in Fig. thus “wasting” the signal.81(a). if 1=gm decreases while RE remains constant.286) that a resistance in series with the base reduces the voltage gain of the CB stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. .80 Small-signal input current components in a CB stage. such a topology must ensure I1 IB to minimize sensitivity to . generated? We can employ a resistive divider similar to that used in the CE stage. source current to ground. yielding VCC RC Q1 C1 R E (a) VCC RC R Thev Q1 V Thev RE (b) VCC RC Q1 R2 RE (c) R1 IB R2 I1 Vb R1 CB Figure 5. Substituting a Thevenin equivalent for R1 and R2 as depicted in Fig. reduction of Rin due to RE is undesirable. By contrast. 5.300) IC RE (5. How is the base voltage. If RE decreases while 1=gm remains constant.cls v. the dc voltage drop across RE muts be much greater than VT .41) and i2 = 0. 5.

RE 1=gm. Assume IS = 5 10.307) (5. we write (5. Since the voltage drop across RE is equal to 500 0:52 mA = 260 mV and VBE = VT lnIC =IS = 899 mV.. = 100.81(c)]. 5. For this reason. and VCC = 2:5 V. 5.82 Example of CB stage with biasing.16 A.310) Vb R R2 R VCC : 1+ 2 VCC R + R = 52 A: 1 2 .g. Thus.304) Av = gm RC .42 Design a CB stage (Fig.309) (5. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution We begin by selecting RE .3 Bipolar Ampliﬁer Topologies 243 we recognize that a resistance of RThev = R1 jjR2 now appears in series with the base. we have Vb = IE RE + VBE = 1:16 V: Selecting the current through R1 and R2 to be 10IB (5. VCC RC V out V in C1 Q1 R2 RE I C RE R1 Vb CB Figure 5.cls v. yielding (5. VA = 1.306) We now determine the base bias resistors. 2007 at 13:42 243 (1) Sec. Example 5. 2006] June 30. acting as a short circuit at frequencies of interest [Fig.308) = 52 A. a “bypass capacitor” is often tied from the base to ground.305) RC = 500 : (5. RE = 500 . e.303) IC = 0:52 mA: If the base is bypassed to ground (5. to minimize the undesirable effect of Rin g1 = 50 m and hence (5.82) for a voltage gain of 10 and an input impedance of 50 .

3.) (5. 2007 at 13:42 244 (1) 244 Chap.271). C1 plays a role similar to RS in Fig.313) (5.314) = 71 pF: Since the impedance of CB appears in series with the base and plays a role similar to the term RB = + 1 in Eq. we may also use the term “follower” to refer to emitter followers in this chapter.286). if we assume. for ! = 2 900 MHz: g C1 = 20! m (5. (5.1 = 1=gm =20 to ensure negligible gain degradation.3. must remain much less than 1=gm = 50 . We ﬁrst study the core and subsequently add the biasing elements. for example.7.315) CB = 0:7 pF: (A common mistake is to make the impedance of CB negligible with respect to than with respect to 1=gm . rules illustrated in Fig. the emitter follower senses the input at the base of the transistor and produces the output at the emitter. Consequently. Vout is constant. 5. In high-performance applications such as cellphones. its impedance. (5. For the sake of brevity. Shown in Fig.5.67 and Eq. The collector is tied to VCC and hence ac ground. 2006] June 30. The reader is encouraged to review Examples 5.316) R1 jjR2 rather Exercise Design the above circuit for an input impedance of 100 . Since Vout changes in the same . and the possible topologies in Fig. the base-emitter voltage of Q1 tends to increase. From another perspective.3 Emitter Follower Another important circuit topology is the emitter follower (also called the “common-collector” stage). Emitter Follower Core How does the follower in Fig. we may choose jC1 ! j. jC1 ! j. Thus.28 before proceeding further. 5 Bipolar Ampliﬁers It follows that R1 = 25:8 k R2 = 22:3 k : (5. then VBE must rise and so must IE .cls v. raising the collector and emitter currents. 5. For example. 5. The higher emitter current translates to a greater drop across RE and hence a higher Vout .84(a) respond to a change in Vin ? If Vin rises by a small amount Vin .2 .311) (5. Appearing in series with the emitter of Q1 . 5. the impedances of C1 and CB must be sufﬁciently small at this frequency.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if the ampliﬁer is used at the receiver front end of a 900-MHz cellphone.312) The last step in the design is to compute the required values of C1 and CB according to the signal frequency. 5.1 .83. requiring that Vout go up. 5. we require that 1 1 1 1 + 1 CB ! = 20 gm and hence (5.

5. Vout Vin .317) v = r+ 1 vout : RE 15 In an extreme case described in Example 5. implying that the follower exhibits a voltage gain less than unity. 2006] June 30. the gain becomes equal to unity. Suppose Vin increases from Vin1 to Vin1 + Vin and Vout from Vout1 to Vout1 +Vout [Fig. the equivalent circuit yields v in rπ vπ g vπ m v out RE Figure 5. 5. 2007 at 13:42 245 (1) Sec.85 Small-signal model of emitter follower. Thus. we expect the voltage gain to be positive. (b) response of the circuit. 5. v + g v = vout r m RE and hence (5.” VCC V in Q1 Vout RE V in1 V BE1 V out1 (b) V in1 + ∆V in V BE2 V out1 + ∆V out (a) Figure 5.43. Note that Vout is always lower than Vin by an amount equal to VBE . As explained later. then VBE2 must be less than VBE1 .84 (a) Emitter follower sensing an input change. contradicting the assumption that Vout has increased. the input and output impedances of the emitter follower make it a particularly useful circuit for some applications. (5. ﬁrst assuming VA = 1.83 Emitter follower.15 The reader may wonder if an ampliﬁer with a subunity gain has any practical value. and the circuit is said to provide “level shift. Vout Vin . Another interesting and important observation here is that the change in Vout cannot be larger than the change in Vin . direction as Vin . But this means the emitter current also decreases and so does IE RE = Vout .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.84(b)]. Shown in Fig. If the output changes by a greater amount than the input.85.cls v. Let us now derive the small-signal properties of the follower.3 Bipolar Ampliﬁer Topologies VCC V in Input Applied to Base 245 Q1 RE Output Sensed at Emitter Vout Figure 5.318) .

The circuit of Fig.321) must tend to inﬁnity. Since the emitter resistor is replaced with an ideal current source. (5. A constant current source ﬂowing through Q1 requires that VBE = VT lnIC =IS remain constant.321) suggests that the emitter follower acts as a voltage divider.322) This result can also be derived intuitively.319) vout = 1 vin 1 + r 1 + 1 RE RE 1 : RE + g m The voltage gain is therefore positive and less than unity.43 In integrated circuits. 5. Suppose. Writing Vout = Vin .86.87(a).cls v.318). VBE . 5 Bipolar Ampliﬁers We also have vin = v + vout : Substituting for v from (5. . VCC V in Q1 Vout I1 Figure 5. conﬁrming operation as a voltage divider. as if Q1 operates with RE = 1 (Example 5. 5. 5. The Thevenin resistance is obtained by setting the input to zero [Fig. 2007 at 13:42 246 (1) 246 Chap. Thus. Equation (5. we wish to model vin and Q1 by a Thevenin equivalent. we obtain (5. Determine the voltage gain if the current source is ideal and VA = 1. The Thevenin voltage is given by the open-circuit output voltage produced by Q1 [Fig. 5. vThev = vin .321) Example 5. 5. a perspective that can be reinforced by an alternative analysis. Exercise Repeat the above example if a resistor of value R1 is placed in series with the collector.87(d).320) (5.87(c)] and is equal to 1=gm .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the follower is typically realized as shown in Fig. 2006] June 30.86 Follower with current source. the value of RE in Eq. 5. (5.87(a) therefore reduces to that shown in Fig. as shown in Fig. yielding Solution Av = 1: (5.87(b)].43). we recognize that Vout exactly follows Vin if VBE is constant.

. 2007 at 13:42 247 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) Thevenin resistance seen at emitter.cls v.88(c) depicts the equivalent circuit.44 VCC RS v out VCC Q1 Q1 RS 1 + gm β+ 1 v Thev = v in RE v out (c) Figure 5.88(a)] if VA = 1. and Q1 by a Thevenin equivalent. (d) simpliﬁed circuit. revealing that Solution vout = RE vin RE + RS + 1 : + 1 gm (5.323) This result can also be obtained by solving the small-signal equivalent circuit of the follower. We model vin . 5.3 Bipolar Ampliﬁer Topologies VCC Q1 v in RE (a) (b) 247 VCC Q1 v out v in v out = v in VCC Q1 v Thev = v in R Thev (c) R Thev = 1 gm v out RE (d) Figure 5. Figure 5. Determine the voltage gain of a follower driven by a ﬁnite source impedance of RS [Fig. RS . RS v in RE R Thev (a) (b) Example 5. The reader can show that the open-circuit voltage is equal to vin .88(b)] is given by (5. (c) Thevenin resistance. 5. 5.88 (a) Follower with source impedance.291) as RS = + 1 + 1=gm . Furthermore. the Thevenin resistance [Fig.87 (a) Emitter follower stage. (c) simpliﬁed circuit. (b) Thevenin voltage . 2006] June 30.

vX = v + iX + gm v RE = iX r + iX + gm iX r RE . . its value remains unchanged if RC = 0. we have iX r = v .326) This expression is identical to that in Eq. Assume = 100. to a much larger value. (5.” This concept can be illustrated by an example. thereby serving as an efﬁcient “buffer. and the follower is biased with an ideal current source. 5. Solution (a) As depicted in Fig. Rsp . (b) An emitter follower biased at a current of 5 mA is interposed between the CE stage and the speaker. RE . which is the case for an emitter follower [Fig. In the equivalent circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. This is. 5.325) vX = r + 1 + R : E iX (5. 2006] June 30. the current iX and gm v ﬂow through RE . the equivalent resistance seen at the collector is now given by the parallel combination of RC and the speaker impedance. let us compute their input and output impedances.162) derived for a degenerated CE stage. no coincidence.89 (a) Input impedance of emitter follower.cls v. of course. (b) equivalence of CE and follower stages. VA = 1. 5 Bipolar Ampliﬁers Exercise What happens if RE = 1? In order to appreciate the usefulness of emitter followers.89(a). and hence (5. Determine the voltage gain of the CE ampliﬁer if (a) The stage drives an 8.324) (5.45 A CE stage exhibits a voltage gain of 20 and an output resistance of 1 k . Adding the voltages across r and RE and equating the result to vX .90(a). The key observation here is that the follower “transforms” the load resistor. producing a voltage drop equal to iX + gm v RE . we have iX vX rπ vπ RE g vπ m R in VCC RC Q1 RE R in 0 VCC Q1 RE (a) (b) Figure 5. Example 5. Also. Since the input impedance of the CE topology is independent of the collector resistor (for VA = 1).speaker directly. The voltage gain therefore degrades drastically. reducing the gain from 20 to 20 RC jj8 =RC = 0:159. 5.89(b)]. 2007 at 13:42 248 (1) 248 Chap.

(5.88.327) (5. As illustrated in Fig. From Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we need not resort to a small-signal model here as Rout can be obtained by inspection. 2006] June 30.91(b). 5. (b) From the arrangement in Fig.3 Bipolar Ampliﬁer Topologies 249 1 kΩ VCC RC R sp Q1 C1 v in 1 kΩ VCC RC Q2 Q1 R in1 I1 C1 R sp v in (a) (b) Figure 5. and hence RS VCC Q1 RE R out RE RS VCC Q1 RS 1 + gm β+ 1 RE (a) (b) Figure 5. a Exercise Repeat the above example if the emitter follower is biased at a current of 10 mA. 5. we note that Rin1 = r2 + + 1Rsp = 1058 : Thus.cls v. We now calculate the output impedance of the follower. the former is equal to RS = + 1 + 1=gm. the output resistance can be viewed as the parallel combination of two components: one seen looking “up” into the emitter and another looking “down” into RE . Interestingly.91 (a) Output impedance of a follower. 5. (b) components of output resistance. 5. . assuming the circuit is driven by a source impedance RS [Fig.91(a)].90 (a) CE stage and (b) two-stage circuit driving a speaker. 2007 at 13:42 249 (1) Sec.90(b). 5.328) 20 RC jjRin1 =RC = 10:28. the voltage gain of the CE stage drops from 20 to substantial improvement over case (a).

.329) This result can also be derived from the Thevenin equivalent shown in Fig. 5.88(c) by setting vin to zero.R S Rout = + g1 jjRE : +1 m (5.

329) reveals another important attribute of the follower: the circuit transforms the source impedance. We can therefore rewrite Eqs. (5.92 illustrates a key point that facilitates the analysis: in small-signal operation. thereby providing higher “driving” capability. the results obtained above can be readily modiﬁed to reﬂect this nonideality. 2006] June 30. Fortunately. We say the follower operates as a good “voltage buffer” because it displays a high input impedance (like a voltmeter) and a low output impedance (like a voltage source). 2007 at 13:42 250 (1) 250 Chap. (5. Figure 5.cls v. RE jjrO RE jjrO + RS 1 + g1 + m Rin = r + + 1RE jjrO . Effect of Transistor Output Resistance Our analysis of the follower has thus far neglected the Early effect. RS . rO appears in parallel with RE .323). 5 Bipolar Ampliﬁers Equation (5. to a much lower value.329) as VCC RS v in Q1 RE rO v in RS Q1 RE rO Figure 5.326) and (5.92 Follower including transistor output resistance.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

332) Determine the small-signal properties of an emitter follower using an ideal current source (as in Example 5. we have rO RS + 1 rO + + 1 g m Rin = r + + 1rO .331) (5. Since RE Solution = 1.46 (5.43) but with a ﬁnite source impedance RS .330) (5. Rout = RS 1 + g1 jjRE jjrO : + m Av = Example 5.

and hence (5. gm rO 1.336) (5. Rout = RS 1 + g1 jjrO : + m Av = rO + RS 1 + Rin + 1rO : Av rO (5.335) Also.333) (5.337) .334) (5.

we follow the iterative procedure described in Section 5. It is interesting to note that. 5. As usual. For this reason.47 Solution To determine the bias current. a condition typically valid.” Since a base current iB results in an emitter current of + 1iB . allowing the same voltage for the base without driving Q1 into saturation.3 Bipolar Ampliﬁer Topologies 251 We note that Av approaches unity if RS + 1rO . Calculate the bias current and voltages if IS = 5 10. the follower draws only iL = + 1 from the source voltage (Fig. VCC R1 C1 X R2 RE Q1 Vout v in RB C1 IB X Y RE Q1 Vout VCC v in (a) (b) Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. followers are often biased as shown in Fig. Writ- .cls v.3.93 Current ampliﬁcation in a follower.16 A. we can say that for a current iL delivered to the load. This is because the collector is tied to VCC . 2006] June 30. 5. The following example illustrates this point.94(a) depicts an example similar to the scheme illustrated in Fig. Thus. where RB IB is chosen much less than the voltage drop across RE . 5. = 100. vX sees the load impedance multiplied by + 1.94(b) employs RB = 10 k and RE = 1 k . 5.94(b). The follower of Fig. thus lowering the sensitivity to . Figure 5.93). and VCC = 2:5 V. unlike the CE topology. Exercise How are the results modiﬁed if RE 1? The buffering capability of followers is sometimes attributed to their “current gain. the current ﬂowing through R1 and R2 is chosen to be much greater than the base current. iL β+ 1 vX VCC Q1 iL Load Figure 5. (b) single base resistor. What happens if drops to 50? Example 5. 5. Emitter Follower with Biasing The biasing of emitter followers entails deﬁning both the base voltage and the collector (emitter) current.19 for the CE stage. 2007 at 13:42 251 (1) Sec. the emitter follower can operate with a base voltage near VCC .2.94 Biasing a follower by means of (a) resistive divider.

VCC RB C1 Q1 C2 RL v in Figure 5. IE = 1:593 V . CE and CB stages can provide a voltage gain greater than unity and their input and output impedances are independent of the load and source impedances. Thus. In integrated circuits. (5.95 Capacitive coupling at input and output of a follower. but the bias current remains constant. we have IC = 1:593 mA. IB RB = 159 mV whereas RE IC = 1:593 V. the base-emitter junction. Since IB RB RE IC . emphasizing that a proper bias point must be established to deﬁne the small-signal properties of each circuit. since IEE is constant. Exercise If RB is doubled. so do VX and VY . the three ampliﬁer topologies studied here exhibit different gains and I/O impedances. leads to IC = 1:545 mA: (5. 0:159 V=1 k = 1:434 mA. the topologies of Fig. this issue is resolved by replacing the emitter resistor with a constant current source (Fig. we expect that variation of and hence IB RB negligibly affects the voltage drop across RE and hence the emitter and collector currents.96. 5 Bipolar Ampliﬁers ing a KVL through RB . respectively (if . As a rough estimate.94 suffer from supply-dependent biasing.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.95). is the circuit more or less sensitive to the variation in ? As manifested by Eq. (5.4 Summary and Additional Examples This chapter has created a foundation for ampliﬁer design. if VCC rises. implying that a twofold change in leads to a 10 change in the collector current. reducing the drop across RE by 159 mV. for = 50. BE E C CC which. The reader is encouraged to repeat the above iterations with = 50 and determine the exact current. so are VBE and RB IB .339) and hence relatively accurate. 5. 2006] June 30. IB RB is doubled ( 318 mV). (5. Using this value in Eq.338).338) 800 mV. and RE gives RB IC + V + R I = V .340) a value close to that in (5.cls v. That is. with VBE (5.338). Depicted in Fig. each serving a speciﬁc application. Under this condition.339) It follows that VBE = VT lnIC =IS = 748 mV. 5. 2007 at 13:42 252 (1) 252 Chap. 5. Now. 5.

97 (a) Example of CE stage. revealing that R1 appears between base and ground.48 = 1. 5. The simpliﬁed ac model is depicted in Fig. our emphasis is on solution by inspection and hence intuitive understanding of the circuits.96 Summary of bipolar ampliﬁer topologies. Assuming VA Example 5.4 Summary and Additional Examples CE Stage CB Stage Follower 253 VCC RC Vout V in Q1 V in Q1 RC VCC V in Vout Vb VCC Q1 Vout RE Figure 5. Replacing vin . RS .97(a). RThev + 1 + RE : + 1 gm (5. 2006] June 30. (5. we have Solution vThev = R R1R vin 1+ S RThev = R1 jjRS : The resulting circuit resembles that in Fig. 2007 at 13:42 253 (1) Sec. On the other hand. (b) equivalent circuit with C1 shorted.342) vout R2 jjRC vThev = . 5.97(b). We assume various capacitors used in each circuit have a negligible impedance at the signal frequencies of interest. 5. and R1 with a Thevenin equivalent [Fig.43(a) and satisﬁes Eq. VA = 1). determine the voltage gain of the circuit shown in Fig.185): (5. As usual. seeking to improve our circuit analysis techniques.343) .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.341) (5.97(c)]. In this section. 5. we consider a number of challenging examples. 5.cls v. followers display a voltage gain of at most unity but their terminal impedances depend on the load and source impedances. (c) simpliﬁed circuit . VCC RC v out Q1 RE v in R1 RS Q1 RE R2 RC v out v Thev R Thev Q1 RE RC v out R2 R1 RS C1 R2 v in (a) (b) (c) Figure 5. and R2 between collector and ground.

(5.185): Solution vout = .345) vout = . 5.49 = 1.346) Exercise What happens if C2 is tied from the emitter of Q1 to ground? .98(b). R2 appears as an emitter degeneration resistor.98(a). (b) simpliﬁed circuit. RS . we replace vin . As shown in the simpliﬁed diagram of Fig.98 (a) Example of CE stage. 5. RC RThev + 1 + R vin 2 + 1 gm and hence (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and R1 with a Thevenin equivalent and utilize Eq. 5 Bipolar Ampliﬁers Substituting for vThev and RThev gives R2 jjRC R1 vout = . 2007 at 13:42 254 (1) 254 Chap. RC R1 RS jjR1 + 1 + R R1 + RS : vin 2 + 1 gm (5. compute the voltage gain of the circuit shown in Fig. R1 jjRS + 1 + R R1 + RS : vin E + 1 gm (5. VCC RC C1 v out Q1 R1 C2 (a) v out RS Q1 R1 R2 RC v in RS R2 v in I1 (b) Figure 5. As in the above example. 2006] June 30.344) Exercise What happens if a very large capacitor is added from the emitter of Q1 to ground? Assuming VA Example 5.cls v.

5.99 (a) Example of CE stage. 5.4 Summary and Additional Examples 255 5. Recall from Fig. 5.RC gm1 + Req .351) Exercise Repeat the above example if R1 is placed in series with the emitter of Q2 .RC = 1 : + R1 1 + g 1 gm1 + m2 The input impedance is also obtained from Fig. Example 5.350) (5. VCC RC v out Q1 v in I1 R eq (a) (b) RC VCC Q2 VB R1 v in v out Q1 R eq Figure 5.347) Av = 1 .75 that Req = R1 1 + g 1 : + m2 The simpliﬁed model in Fig. compute the voltage gain and input impedance of the circuit shown in Fig.75: (5.51 = 1.348) (5.349) Rin = r1 + + 1Req = r1 + R1 + r2 : (5. 2007 at 13:42 255 (1) Sec. . 5. Req . 5.100(a) if VA Example 5. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution The circuit resembles a CE stage (why?) degenerated by the impedance seen at the emitter of Q2 .99(a).99(b) thus yields (5. (b) simpliﬁed circuit.50 Assuming VA = 1. Calculate the voltage gain of the circuit in Fig.cls v.

In this circuit. Q1 operates as a common-base device (why?) but with a resistance Req in series with its base [Fig. R1 appears in parallel with RC and R2 is shorted to ground on both ends [Fig.329): Solution Req = . e. as given by Eq. 2006] June 30. 5. (b) simpliﬁed circuit.100(b)]. 5. Since the base is at ac ground. we recognize that Q2 resembles an emitter follower. To obtain Req .52 = 1. (5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5.cls v.. concluding that Req can be viewed as the output resistance of such a stage. but with RC replaced by RC jjR1 : 1 Av = RC jjR1 : RS + g Solution (5.101(b)]. 2007 at 13:42 256 (1) 256 VCC RC v out C1 v in RS Q1 R2 CB v in R1 Chap.352) m Exercise What happens if RC is replaced by an ideal currents source? Determine the input impedance of the circuit shown in Fig. RC Q2 RB RE R in (b) Q1 R eq Figure 5.91(a). (b) simpliﬁed circuit.271).101(a) if VA VCC RC v out Q1 R eq R in (a) Example 5. 5 Bipolar Ampliﬁers v out Q1 RS RC R1 (a) (b) Figure 5.101 (a) Example of CB stage. 5.g. the topology in Fig. The voltage gain is given by (5.100 (a) Example of CB stage.

RB 1 +1 + g m2 jjRE : (5.353) .

divided by + 1.cls v.101(b). from Fig. we observe that Rin contains two components: one equal to the resistance in series with the base. and another equal to 1=gm1 : eq Rin = R+ 1 + g 1 . Req . 2007 at 13:42 257 (1) Sec. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 5.4 Summary and Additional Examples 257 Now.

354) (5. R2 . (b) circuit with C1 shorted. RS .355) The reader is encouraged to obtain Rin through a complete small-signal analysis and compare the required “manual labor” to the above algebra. Exercise What happens if the current gain of Q2 goes to inﬁnity? Example 5. 5. (c) simpliﬁed circuit. where the output resistance of Q1 is explicitly drawn. and R1 with their Thevenin equivalent and recognizing that RE .102(b). 5. we employ Eq.102(c)].102(a) with VA 1. and rO appear in parallel [Fig.330) and write Solution vout RE jjR2 jjrO vThev = RE jjR2 jjrO + 1 + RThev g +1 m (5. Replacing vin .102 (a) Example of emitter follower. Noting that X is at ac ground. (5. 5.53 Compute the voltage gain and the output impedance of the circuit depicted in Fig. VCC RS Q1 v in R1 X C2 R2 RE v out v in RS R1 Q1 RE (b) rO v out R2 (a) R Thev Q1 v Thev RE (c) v out R2 r O Figure 5. we construct the simpliﬁed circuit shown in Fig.356) . m1B 1 1 1 R + = +1 + 1 gm2 jjRE + gm1 : (5.

we refer to Eq.357) Rout = RThev + g1 jjRE jjR2 jjrO +1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 258 (1) 258 Chap.cls v.332): (5. (5. 5 Bipolar Ampliﬁers and hence vout = RE jjR2 jjrO R R1R : vin R jjR jjr + 1 + RS jjR1 1 + S E 2 O g +1 m For the output resistance. 2006] June 30.

RS jjR1 m = + g1 jjRE jjR2 jjrO : +1 m .

As the ﬁrst step.358) (5. we represent the role of Q2 and Q3 by the impedances that they create at their emitter.359) Exercise What happens if RS = 0? Example 5. 5.75 B Req1 = R+11 + g 1 : m2 (5.54 Determine the voltage gain and I/O impedances of the topology shown in Fig. we have from Fig.103(a). (b) simpliﬁed circuit. 5. (5.360) . VCC R B2 R eq2 v in R eq1 R B1 Q2 Q1 RC v out Q3 RE v in Q3 RE R eq1 R eq2 RC v out (a) (b) Figure 5. Assume VA = 1 and equal ’s for npn and pnp transistors.103 (a) Example of CE stage. Solution We identify the stage as a CE ampliﬁer with emitter degeneration and a composite collector load. Since Req1 denotes the impedance seen looking into the emitter of Q2 with a base resistance of RB 1 .

Rin = r3 + + 1RE + Req1 . 5. 5.cls v.103(b).5 Chapter Summary 259 Similarly.363) Also. B Req2 = R+21 + g 1 .362) (5.361) Av = . It follows that (5. 2007 at 13:42 259 (1) Sec. R B1 + 1 + 1 + R E + 1 gm2 gm3 RC + Req2 (5. Req1 + g 1 + RE m3 B RC + R+21 + g 1 m1 : =.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. m1 leading to the simpliﬁed circuit shown in Fig.

RB1 + 1 . r . Signals simply perturb these conditions. and rO .364) (5. the input and output impedances of ampliﬁers determine the ease with which various stages can be cascaded. The impedances seen looking into the base. collector. Biasing techniques establish the required base-emitter and base-collector voltages while providing the base current. In order to obtain the required small-signal bipolar device parameters such as gm .366) (5. carry a certain collector current and operate in the active region. the transistor must be “biased.367) Exercise What happens if RB 2 ! 1? 5.5 Chapter Summary In addition to gain. rO (with emitter grounded).365) Rout = RC + Req2 B = RC + R+21 + g 1 : m1 (5. and 1=gm (with base grounded). and emitter of a bipolar transistor are equal to r (with emitter grounded).” i. = r3 + + 1 RE + + 1 g m2 and (5. respectively.e. Voltage ampliﬁers must ideally provide a high input impedance (so that they can sense a voltage without disturbing the node) and a low output impedance (so that they can drive a load without reduction in gain). ..

5. The voltage gain expressions for CE and CB stages are similar but for a sign.108. Determine the input impedance of the circuits depicted in Fig.cls v. Compute the bias point of the circuits depicted in Fig. Assume VA VCC R1 Q1 R2 R in R in (a) (b) (c) = 1. Determine the small-signal input resistance of the circuits shown in Fig. 2006] June 30. only three ampliﬁer topologies are possible: common-emitter and common-base stages and emitter followers.105. 5 Bipolar Ampliﬁers With a single bipolar transistor. 5. Emitter degeneration improves the linearity but lowers the voltage gain. Problems 1. 7. 5. Assume VA = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Compute the input resistance of the circuits depicted in Fig.) 3. 5. The CE stage provides a moderate voltage gain.107. a moderate input impedance. Compute the output resistance of the circuits depicted in Fig. 5. Emitter degeneration raises the output impedance of CE stages considerably.104. Determine the average power delivered to a load resistance RL and plot the result as a function of RL . serving as a good voltage buffer. The emitter follower provides a voltage gain less than unity. VCC Q1 VCC Q1 R1 R in VCC Q1 R in Q2 (d) Q2 Figure 5. (Recall from Chapter 3 that each diode behaves as a linear D1 R1 D1 R1 D2 R1 D1 (a) (b) (c) R in R in R in D2 Figure 5.104 resistance if the voltage and current changes are small. and a low output impedance. and a moderate output impedance. IS = . Assume = 100. a high input impedance. 6. The CB stage provides a moderate voltage gain. a low input impedance. 2. An antenna can be modeled as a Thevenin equivalent having a sinusoidal voltage source V0 cos !t and an output resistance Rout . Compute the output impedance of the circuits shown in Fig. 5. 2007 at 13:42 260 (1) 260 Chap.106. Assume all diodes are forward-biased.105 4.109. 5. and a moderate output impedance.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Consider the circuit shown in Fig. Construct the small-signal equivalent of each of the circuits in Problem 9.16 A.cls v.110. 5. IS = 510. Construct the small-signal equivalent of each of the circuits in Problem 7. and VA = 1. 8.5 Chapter Summary R out RB Q1 R1 R out VB Q1 Q2 (b) (c) (d) 261 R out Q1 Q1 Q2 R out VCC VB (a) Figure 5.106 VCC VCC Q1 R in R1 Q1 R in R1 (a) (b) Ideal VCC Q1 R in Q2 VB R1 (c) VB VCC Q2 Q1 R in (d) (e) VCC Q2 R in Q1 Figure 5. .108 6 10. 5.16 A.107 VCC Q1 RC R out Q1 Q2 VB (b) R out (a) Figure 5. 2007 at 13:42 261 (1) Sec. Assume = 100. Calculate the bias point of the circuits shown in Fig. 11. 10. IS = 6 10. 5. 9. and VA = 1. 2006] June 30. where = 100. and VA = 1.16 A.111.

110 (b) (c) V CC = 2. In the circuit of Fig.5 V 1 kΩ Q1 Q1 Q2 0.5 V 100 k Ω 500 Ω 100 k Ω Chap.112. 5.5 V 1 kΩ 100 k Ω Bipolar Ampliﬁers V CC = 2.5 V Q1 (a) (b) (c) Figure 5.5 mA. 2007 at 13:42 262 (1) 262 V CC = 2.5 V 500 V CC = 2.111 (a) What is the minimum value of RB that guarantees operation in the active mode? (b) With the value found in RB .5 V RB 2 kΩ 3 kΩ Q1 Figure 5.5 V 12 k Ω 1 kΩ Ω 16 k Ω Q1 16 k Ω Q1 Q2 13 k Ω 0.5 V Q1 (a) Figure 5. V CC = 2. calculate the value of IS .cls v.5 V 50 k Ω 3 kΩ rises 30 k Ω Q1 Figure 5.112 (a) If the collector current of Q1 is equal to 0. 2006] June 30. 5 V CC = 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . how much base-collector forward bias is sustained if to 200? 12.109 V CC = 2.5 V 34 k Ω 3 kΩ 9 kΩ V CC = 2. = 100 and VA = 1.

5 V R1 RC 3 kΩ 10 k Ω Q1 R2 R E = 200 Ω Figure 5.5 V R1 5 kΩ Q1 R2 Figure 5.17 A. IS = 10. and VA = 1. Explain why no solution exists. The circuit of Fig. Consider the circuit shown in Fig. 5.114 for a gain (= gm RC ) of A0 with an V CC R1 RC Q1 R2 Figure 5.114 output impedance of R0 . calculate the value of IS . 1 = 2 = 100. 5. 13. and VA = 1. 5.113 a gm of at least 1=260 . 15. .115 (a) Determine the required value of R1 . 16.16 A.17 A. and VA = 1.115 is designed for a collector current of 0. = 100. determine the maximum value of R2 that guarantees operation of Q1 in the active mode. determine the minimum allowable values of R1 and R2 . The circuit of Fig. (b) What is the error in IC if RE deviates from its nominal value by 5? 17. 5.113 must be designed for an input impedance of greater than 10 k and V CC = 2. 5.16 A. 2006] June 30. Assume IS = V CC = 2.117. 6 10.5 Chapter Summary 263 (b) If Q1 is biased at the edge of saturation.cls v. (a) Determine the collector currents of Q1 and Q2 . Assume = 100.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and VA = 1. What is the maximum achievable input impedance here? Assume VA = 1. If = 100. where IS 1 = 2IS 2 = 5 10. 18. In the circuit of Fig. 2007 at 13:42 263 (1) Sec. We wish to design the CE stage depicted in Fig. Repeat Problem 13 for a gm of at least 1=26 . IS = 2 10.116.25 mA. 14. 5. (b) Construct the small-signal equivalent circuit.

The circuit of Fig.5 V 100 Ω 1 = 2 = 100. and 16 k Ω Q1 Q2 Figure 5. 5. 2007 at 13:42 264 (1) 264 V CC = 2.118 (a) Determine the operating point of the transistor.5 V RB Rp 1 kΩ 100 Ω Q1 Figure 5.117 19.118.5 V 13 k Ω R1 RC Q1 1 kΩ Q2 12 k Ω R2 RE 400 Ω Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9 kΩ = IS2 = 4 10.16 A.119 must be biased with a collector current of 1 mA. 2006] June 30. 5 Bipolar Ampliﬁers RC 2 kΩ Q1 R2 R E = 100 Ω Figure 5.5 V 30 k Ω Chap. Compute the VCC = 2. IS 1 VA = 1. 20. In the circuit depicted in Fig.119 .cls v.116 VCC = 2. 5. V CC = 2. (b) Draw the small-signal equivalent circuit.

16 A.5 V 10 k Ω 1 kΩ = 1.123 (a) Determine the operating point of Q1 . where IS Calculate the operating point of Q1 . VX = 1:1 V.123. 5. a parasitic resistor. In the circuit of Fig.5 V RB Rp 1 kΩ 500 Ω Q1 Figure 5. and VA = 1. 40 k Ω Q1 Figure 5.cls v. 20 k Ω 500 Ω = 6 10. 5.16 A. what is the value of IS ? V CC = 2. V CC = 2. If = 100. 2007 at 13:42 265 (1) Sec. 5. and VA = 1.16 A. . RP . = 100. 2006] June 30.5 V 300 Ω X 10 k Ω Q1 Figure 5. and VA = 1.16 A. and VA 24.122 forward bias must not exceed 200 mV? Assume IS = 3 10.121 23. V CC = 2.120 22.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.120. = 100. Due to a manufacturing error. What is the minimum allowable value of RB if the base-collector VCC = 2.122. In the circuit of Fig.5 Chapter Summary 265 required value of RB if IS = 3 10.5 V Q1 400 Ω Figure 5. 21. = 100 and VA = 1. 5. has appeared in series with the collector of Q1 in Fig. IS = 8 10.121. = 100. 5. Consider the circuit shown in Fig.

5 V Q1 Q2 300 Ω 80 k Ω (b) (a) Figure 5. 30. and VA = 1. We have chosen RB in Fig. Determine the bias point of each circuit shown in Fig. Construct the small-signal model of the circuits in Problem 26. 27.or reverse-bias across the basecollector junction at these two extremes.125.16 A. Determine the forward. and VA = 1. Assume = 50. VCC = 2.127 to place Q1 at the edge of saturation. Assume npn VCC = 2.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VCC = 2.16 A. 26.16 A. and VA = 1. 5.128 such that Q1 sustains a reverse bias of 300 mV .5 V 32 k Ω 18 k Ω 100 Ω 18 k Ω Figure 5. 2006] June 30. In the circuit of Fig.5 V Q1 VB 500 Ω Q2 Figure 5. 28. 31. Assume npn 32 k Ω = 2 pnp = 100. But the actual value of this resistor can vary by 5.126 IS = 9 10. 5. 5. Calculate the value of RE in Fig.5 V Q1 Q1 Q2 1 kΩ (a) (b) VCC = 2. 200 Ω = 100. Draw the small-signal model of the circuits in Problem 28. IS = 8 10.124 (a) Calculate VB such that Q1 carries a collector current of 1 mA. and VA = 1. 5 Bipolar Ampliﬁers (b) Draw the small-signal equivalent circuit. 29. 5.125 IS = 9 10.5 V Q1 60 k Ω 200 Ω = 2 pnp = 100.124. IS 1 = IS 2 = 3 10.cls v. (b) Construct the small-signal equivalent circuit.16 A. Calculate the bias point of the circuits shown in Fig. 2007 at 13:42 266 (1) 266 Chap. 25. 5.126. V CC = 2.

What happens if the value of RE is halved? 32.128 across its base-collector junction.5 Chapter Summary VCC = 2.cls v. what value of IS yields a collector current of 1 mA in Fig.16 A. IS = 8 10.5 V 10 k Ω RE Q1 10 k Ω 5 kΩ Figure 5.) Constructing the circuit shown in Fig.127 VCC = 2. determine the collectorVCC R1 Q1 R2 R1 Q1 R2 R3 (a) (b) Figure 5. 5.5 V Q1 RB 1 kΩ 267 5 kΩ Figure 5.”(The npn counterpart has a similar topology. and VA = 1.6 k Ω Figure 5. 5. 5. 5. 2006] June 30. 2007 at 13:42 267 (1) Sec. Assume = 50.129 33.130 .130(a) is called a “VBE multiplier.130(b).5 V Q1 20 k Ω 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.129? VCC = 2. The topology depicted in Fig. If = 80 and VA = 1.

cls v. 2V T and no Early effect.5 V Vout V in Q1 Figure 5. (5.368) .132 must be designed for maximum voltage gain while maintaining Q1 RC V in 1 kΩ VCC Vout Q1 Figure 5. The circuit of Fig. Compute the voltage gain for a bias current of 1 mA. 5. 36. 2006] June 30. 35. If VA = 10 V and VBE = 0:8 V. (The npn counterpart can also be used.133 is equal to 50 and the output impedance equal to 10 k . 5. 37. determine the bias current of the transistor. 5 Bipolar Ampliﬁers emitter voltage of Q1 if the base current is negligible. We wish to design the CE stage of Fig. What is the minimum 50 k Ω VCC = 2. Suppose the bipolar transistor in Fig.131 allowable supply voltage if Q1 must remain in the active mode? Assume VA = 1 and VBE = 0:8 V.) 34. 2007 at 13:42 268 (1) 268 Chap. calculate the required bias current.133 employs an ideal current source as the load.134 tic: IC = IS exp VBE . 5. If the voltage gain VCC Ideal Vout V in Q1 Figure 5. The CE stage of Fig.131 for a voltage gain of 20. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.132 in the active mode.134 exhibits the following hypothetical characterisRC V in 1 kΩ VCC Vout Q1 Figure 5.

135. Calculate the input impedance of the circuit. (5. Calculate the bias current and the value of RC if = 100.157) for the gain of a degenerated CE stage.136 current.135 39. We wish to design the degenerated stage of Fig. Repeat Problem 42 for a voltage gain of 100. 2007 at 13:42 269 (1) Sec. 5. For the following two cases. determine the relative change in the gain if IC varies by 10%: (a) gm RE is nominally equal to 3. Transistor Q2 in Figs.137 for a voltage gain of 10 with Q1 operating at the edge of saturation. respectively? 42. 5. Repeat Problem 38 with VA 1. IS = 5 10. The more constant gain in the second case translates to greater circuit linearity. Writing gm = IC =VT .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 43. What is the maximum gain that can be achieved in this stage? .16A. (b) gm RE is nominally equal to 7. IC .136 in terms of the collector bias VCC RC Vout V in Q1 RE Figure 5. Assume VA = 1. 2006] June 30. 5. Express the voltage gain of the stage depicted in Fig.5 Chapter Summary 269 38.cls v. 41.135(d) and (e) operates in soft saturation. If VA = 1. 40. Determine the voltage gain and I/O impedances of the circuits shown in Fig. Consider Eq. what is the gain if the dc voltage drops across RC and RE are equal to 20VT and 5VT . Explain why no solution exists. and VT . we note that gm and hence the voltage gain vary if IC changes with the signal level. VCC VCC Q2 Vout V in Q1 V in Q1 Q2 R1 Vout V in Q1 VCC Q2 RC Vout (a) (b) (c) VCC Q2 RC Vout V in Q1 V in VCC Q2 Vout RC Q1 (d) (e) Figure 5. 5. and VA = 1. 5.

. 5 Bipolar Ampliﬁers VCC = 2.cls v. 2007 at 13:42 270 (1) 270 Chap. Compare the output impedances of the circuits illustrated in Fig.137 44. compute the output impedance of a degenerated CE stage with VA 1. 5.5 V RC Vout V in Q1 200 Ω Figure 5. 5.138. Assume 1. 5.140. 49. Using a small-signal equivalent circuit.138 47. Assume VA = 1. 45. Construct the small-signal model of the CE stage shown in Fig. 5. Compute the voltage gain the I/O impedances of the circuits depicted in Fig. 5. 46. Construct the small-signal model of the CE stage shown in Fig. 50. Assume 1. Assume 1. 2006] June 30.43(a) and prove that the output impedance is equal to RC if the Early effect is neglected. 48. Calculate the output impedance of the circuits shown in Fig.43(a) and calculate the voltage gain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 5. VCC Q2 R1 Vout V in Q1 RE (a) (b) (c) VCC RC Vout V in Q1 Q2 V in Q2 VCC RC Vout Q1 VCC RC V in RB Q1 Q2 Vout V in RB Q1 RC Vout Q2 VCC VB (d) (e) Figure 5. Assume VA = 1. Determine the voltage gain and I/O impedances of the circuits shown in Fig.141. Assume VA = 1.139.

142. 5.5 VCC RE V in Q1 Chapter Summary VCC RE V in Vout Q1 RC Vout Q2 V in VCC Q3 VCC RE Q1 Vout RC Q2 Q2 V in VCC Q1 Vout RC 271 RC Q2 (a) (b) (c) (d) Figure 5. Repeat Example 5.143 is biased with a collector current of 2 mA.217) and prove that the result remains close to r if IB RB VT (which is valid because VCC and VBE typically differ by about 0. Calculate vout =vin for each of the circuits depicted in Fig.5 V or higher. . 2006] June 30.140 VCC Q1 Q2 R out (a) VCC Q1 Q2 R out (b) Figure 5. The common-base stage of Fig.) 52. and VA = 1.33 with RB = 25k and RC = 250 .16 A. Writing r = VT =IC . Is the gain greater than unity? 54. 5.141 51. 5. Assume VA = 1. (a) Calculate the voltage gain and I/O impedances of the circuit. (5. Assume IS = 8 10. = 100.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.139 R out R out Q1 Q2 Q1 R out Q2 VCC Q1 RB R1 Q2 VCC I1 (a) (b) (c) Figure 5. 2007 at 13:42 271 (1) Sec. assume the capacitors are very large. expand Eq. 53.cls v. Also.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 5 V CC = 2.5 V RC 10 k Ω Vout V in C1 Q1 100 Ω Vout V in 1 kΩ C1 V in 1 kΩ Vout Q1 500 Ω C1 C2 Q1 2 kΩ 11 k Ω C2 (a) (b) (c) 2 kΩ Figure 5.142 VCC RC 500 Ω Vout Q1 V in Vb Figure 5.144. Determine the voltage gain of the circuits shown in Fig.143 (b) How should VB and RC be chosen to maximize the voltage gain with a bias current of 2 mA? 55. 5. 2007 at 13:42 272 (1) 272 V CC = 2.cls v.144 (b) (c) (d) VCC Q3 RC Vout Vout Q1 V in RS RE Vb V in Vb VCC Q2 Q1 Vout V in RC Q1 RE Vb Vb . VCC Q3 VCC Q2 RC Vout Q1 V in (a) Figure 5. Assume VA = 1.5 V 100 k Ω 1 kΩ 50 k Ω Chap.5 V 1 kΩ 14 k Ω Bipolar Ampliﬁers V CC = 2.

Repeat Problem 58 for CB = 0.145. 63.cls v. 2007 at 13:42 273 (1) Sec. (a) Determine the operating point of Q1 . 5.5 Chapter Summary 273 56.5 V 13 k Ω V out Q1 V in 400 Ω CB 12 k Ω Figure 5.146 58. 5. 62. VCC ideal Vout Q1 V in Vb Figure 5. 5. 5. 2006] June 30. 60. . Assume VA = 1. 5.148 if VA = 1 and CB is very large. Assume VA 1.151 provides two outputs. Calculate the voltage gain and the I/O impedances of the stage depicted in Fig.146.147 59.16 A. Calculate the voltage gain and I/O impedances of the CB stage shown in Fig.149 if VA = 1 and CB is very large. determine the relationship between vout1 =vin and vout2 =vin . Assume VA VCC VCC VCC R1 Q1 Q2 R1 Q1 Q2 R in (a) = 1. where and CB is very large. The circuit of Fig.150 if VA 1. Compute the voltage gain and I/O impedances of the stage shown in Fig. IS = 8 10.147. (b) Calculate the voltage gain and I/O impedances of the circuit. VCC = 2. 5. VA = 1. 5.145 57.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 61. Calculate the voltage gain of the circuit shown in Fig. 5. 1 kΩ = 100. VCC R2 R2 R1 Q1 Vb R in Q2 R2 R1 Q1 Q2 R in (b) R in (c) (d) Figure 5. Compute the input impedance of the stages depicted in Fig. Consider the CB stage depicted in Fig. If IS 1 = 2IS 2 .

152.148 VCC ideal V out Q1 V in R1 CB R2 Figure 5.9.151 64. 2007 at 13:42 274 (1) 274 Chap. Calculate the required bias current and RE . Assume VA = 1.cls v. Assume = 100 and VA = 1.152 must provide an input impedance of greater than 10 k with a minimum gain of 0. 5 Bipolar Ampliﬁers VCC Q2 V out Q1 V in R2 R1 CB Figure 5.149 VCC ideal V out Q1 V in RS Vb Figure 5.150 VCC RC R C V out1 Q1 V in Vb Q2 Vout2 Figure 5. 5.8. a base resistance. 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 66. A microphone having an output impedance RS = 200 drives an emitter follower as shown . Assume 1. 67. determine the bias current of Q1 such that the gain is equal to 0. 2006] June 30. Using a small-signal model. 65. The circuit of Fig. determine the voltage gain of a CB stage with emitter degeneration. For RE = 100 in Fig. and VA 1.

68. 5.5 V V in Q1 Vout RE 275 Figure 5. 2007 at 13:42 275 (1) Sec. Assume VA = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume VA = 1 and the collectors of Q1 and Q2 are tied to VCC . (c) Compute the current gain of the pair. (a) If the emitter of Q2 is grounded.152 in Fig. calculate the impedance seen at the emitter of Q2 .5 Chapter Summary VCC = 2.” where Q1 plays a role somewhat similar to an emitter follower driving Q2 .cls v. determine the impedance seen at the base of Q1 . (b) If the base of Q1 is grounded.153 .154. 5. VCC V in Q1 Vout Vb Q2 (a) VCC V in Q1 Vout Q2 (b) (c) VCC V in RS Q2 Q1 Vout VCC V in RE Q2 Q1 Vout RE V in VCC Q1 Vout Q2 (d) (e) Figure 5. Determine the bias current such that the output impedance does not exceed 5 VCC = 2. 2006] June 30. Figure 5. Assume = 100 and VA = 1.155 depicts a “Darlington pair. Compute the voltage gain and I/O impedances of the circuits shown in Fig.154 69. Note that IE1 IC 1 = IB2 = IC 2 = .153. 5. . deﬁned as IC 1 + IC 2 =IB 1 .5 V V in RS Q1 I1 R out Figure 5.

Assume IS = 7 10.157.158 sume VA 1.156 (a) Calculate the output impedance of the current source.158 illustrates a cascade of an emitter follower and a common-emitter stage. 71.155 70. (But for bias calculations.5 V 10 k Ω Q1 .16 VCC = 2. Q2 serves as a current source for the input device VCC V in Q1 R CS Vb Q2 RE Figure 5. 5 Bipolar Ampliﬁers Q1 Q2 Figure 5.157 A. V in C1 Q1 C2 100 Ω 1 kΩ Vout Figure 5. (b) Replace Q2 and RE with the impedance obtained in (a) and compute the voltage gain and I/O impedances of the circuit. 72. 2006] June 30. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. = 100. RCS .) Also. AsVCC V in RC Q1 X RE Q2 Vout Figure 5. Determine the voltage gain of the follower depicted in Fig. 2007 at 13:42 276 (1) 276 Chap. 5. assume the capacitors are very large. Figure 5. 5.cls v. assume VA = 1. and VA = 5 V. In the emitter follower shown in Fig.156.

161 for maximum voltage gain but with an output VCC = 2.5 V RB V in RC Vout Q1 Figure 5. 2007 at 13:42 277 (1) Sec. The stage depicted in Fig. 5. and VA = 1. 5. and an output impedance of 1 k .cls v. assume = 100.5 V RB V in CB RC Vout Q1 Figure 5.160 greater than 5 k . 76. 5. (a) Calculate the I/O impedances of the circuit. Design the CE stage shown in Fig. vout =vin = vX =vin vout =vX . Assume VCC V in RC Q1 X RE Q2 Vout Vb Figure 5. 2006] June 30.5 Chapter Summary 277 (a) Calculate the input and output impedances of the circuit. Design the stage. 75. If the transistor is allowed to sustain a basecollector forward bias of 400 mV.161 impedance no greater than 500 . Allowing the transistor to experience at most 400 mV of base-collector forward bias. and input impedance of VCC = 2.159 shows a cascade of an emitter follower and a common-base stage. unless otherwise stated. IS = 6 10. If the lowest signal frequency of interest is 200 Hz. 74.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.161 must be designed for minimum supply voltage but with a voltage gain of 15 and an output impedance of 2 k . 5. We wish to design the CE stage of Fig. . (b) Determine the voltage gain. 73.159 VA = 1. 5.160 for a voltage gain of 10. Design Problems In the following problems. The CE stage of Fig. estimate the minimum allowable value of CB . design the stage. 77. (b) Calculate the voltage gain. Figure 5.161 must achieve maximum input impedance but with a voltage gain of at least 20 and an output impedance of 1 k .16 A. vout =vin = vX =vin vout =vX . design the stage and calculate the required supply voltage.

and Q1 experiences a maximum base-collector forward bias of 400 mV. Assume a voltage drop of 10VT = 260 mV across RE so that this resistor does not affect the input impedance signiﬁcantly. Design the stage of Fig. 5. 86. The stage of Fig. 2007 at 13:42 278 (1) 278 Chap. Design the degenerated CE stage of Fig. 5. We wish to design the CE stage of Fig. assume the current ﬂowing through R1 is approximately 10 times the base current. The CB ampliﬁer of Fig.161 for minimum power dissipation.163 must achieve a voltage gain of 8 with an output impedance of 500 . assuming that RE sustains 200 mV. . Design the CE stage of Fig.162 impedance of 500 . Design the circuit with the same assumptions as those in Problem 83. 5. 85. and a voltage drop of 200 mV across RE .5 V R1 V in R2 RE RC Vout Q1 Figure 5. 5.163 for a power budget of 5 mW and a voltage gain of 10. Assume RE sustains a voltage drop of 300 mV and the current ﬂowing through R1 is approximately 10 times the base current. 2006] June 30. 5. 5. If the voltage gain must be equal to A0 . 83. What is the minimum required power dissipation? Make the the same assumptions as those in Problem 83.162 for a voltage gain of 5 and an output V CC = 2. Design the circuit. 5. 82. and the lowest frequency of interest is 200 Hz.161 for a power budget of 1 mW and a voltage gain of 20. 80. 84.162 must be designed for maximum voltage gain but an output impedance of no greater than 1 k .5 V R1 CB Q1 R2 RE Vin RC Vout Figure 5. 79. a voltage gain of 5. We wish to design the CB stage of Fig. 5. 5 Bipolar Ampliﬁers 78. Assume the current ﬂowing through R1 is approximately 10 times the base current. determine the trade-off between the power dissipation and the output impedance of the circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.162 for a power budget of 5 mW. Design the CB ampliﬁer of Fig. and the current ﬂowing through R1 is approximately 10 times the base current.163 for a voltage gain of 20 and an input V CC = 2.163 impedance of 50 .163 for an output impedance of 200 and a voltage gain of 20. Also. 5. 81. Make the same assumptions as those in Problem 83. Design the common-base stage shown in Fig.cls v.

91. with a voltage VCC = 2. that it can drive? 90. The follower shown in Fig. Make the same assumptions as those in Problem 83. The follower of Fig. RL . 89.pnp = 8 10. Design the CB stage of Fig. 5.85 and an input VCC = 2. npn = 100.16 A.npn = 5 V.8. 2007 at 13:42 279 (1) Sec.npn = 5 10. 5.165 gain of 0. VA. 5. assume IS. (Hint: select the voltage drop across RE to be much greater than VT so that this resistor does not affect the voltage gain signiﬁcantly.5 Chapter Summary 279 87.165 must drive a load resistance. V CC = 2. 5.) SPICE Problems In the following problems.5 V R1 V in Q1 Vout RL Figure 5. Assume RL = 200 .16 A. RL = 50 . IS.pnp = 3:5 V. What is the minimum load resistance.9.164 for a voltage gain of 0.5 V R1 V in C1 Q1 RE C2 Vout RL Figure 5.166 must amplify signals in the range of 1 MHz to 100 MHz. 5. pnp = 50. VA.cls v.163 for the minimum supply voltage if an input impedance of 50 and a voltage gain of 20 are required.166 . 2006] June 30. The common-emitter shown in Fig. 88. Design the circuit assuming that the lowest frequency of interest is 100 MHz. Design the emitter follower shown in Fig. 5.164 must consume 5 mW of power while achieving a voltage gain of 0.164 impedance of greater than 10 k .5 V 100 k Ω 1 kΩ V in C1 C2 P Vout Q1 500 Ω Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

Repeat Problem 93 for the stage illustrated in Fig.5 V 10 k Ω 1 kΩ Vout Q1 V in C1 P Figure 5.cls v. VN =VX is far from 0. 1 F. Explain why. (c) Compute the voltage gain of the circuit at 10 MHz. 5 Bipolar Ampliﬁers (a) Using the . Which one of the two circuits is less sensitive to supply variations? .g. 5. V CC = 2.. 1 nF. (d) With the proper value of C2 found in (c).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Unfortunately.op command. and 1 pF. (c) Plot jVout =Vin j as a function of frequency for several values of C2 .g.167. Predicting an output impedance of about 1 k for the stage shown in Fig. (b) Select the value of C1 such that it operates as nearly a short circuit (e. 5.5.168 (a) Determine the bias conditions of Q1 . 2007 at 13:42 280 (1) 280 Chap. How much can VCC fall while the gain of the circuit degrades by only 5? 94.167 93. 5. 5. choose the value of C1 such that jVP =Vin j 0:99 at 1 MHz.5 V 100 k Ω 1 kΩ N C1 C2 IX VX Q 1 1 kΩ 500 Ω Figure 5. jVP =Vin j 0:99) at 10 MHz. V CC = 2.e. Consider the self biased stage shown in Fig.) 92.168. determine the bias conditions of Q1 and verify that it operates in the active region.. where VX represents an ac source with zero dc value. for C2 = 1 F). (b) Running an ac analysis. e. 2006] June 30. Determine the value of C2 such that the gain of the circuit at 10 MHz is only 2 below its maximum (i. a student constructs the circuit depicted in Fig.166. (e) Suppose the supply voltage is provided by an aging battery. This ensures that C1 acts as a short circuit at all frequencies of interest. determine the input impedance of the circuit at 10 MHz. (One approach is to insert a resistor in series with Vin and adjust its value until VP =Vin or Vout =Vin drops by a factor of two.169.. (d) Determine the input impedance of the circuit at 10 MHz.

(c) What is the signal attenuation of the emitter follower? Does the overall gain increase if RG2 is reduced to 100 ? Why? .170 (a) Determine the value of RE 1 such that Q2 carries a bias current of 2 mA.169 95. C2 . 2007 at 13:42 281 (1) Sec.5 Chapter Summary V CC = 2. 2006] June 30.5 V 2 kΩ 600 Ω load at a V in C1 2 kΩ X Q1 R E1 C2 Q2 200 Ω C3 50Ω Vout Figure 5.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) Determine the minimum acceptable value of C1 . V CC = 2. The ampliﬁer shown in Fig. 5. 5.cls v.5 V 10 k Ω 1 kΩ 281 V in C1 1 kΩ Vout Q1 Figure 5.170 employs an emitter follower to drive a 50frequency of 100 MHz. and C3 if each one is to degrade the gain by less than 1.

and a doped piece of silicon. Figure 6 illustrates the sequence of concepts covered in this chapter. we analyze the structure and operation of MOSFETs. where C denotes the capacitance between the two plates. memory chips containing billions of transistors.1(b)? As positive charge is placed on the top plate. “mirroring” any charge deposited on the top plate. What happens if a potential difference is applied as shown in Fig.1 Structure of MOSFET Recall from Chapter 5 that any voltage-controlled current source can provide signal ampliﬁcation. and sophisticated communication circuits providing tremendous signal processing capability. MOSFETs also behave as such controlled sources but their characteristics are different from those of bipolar transistors. 2006] June 30.g. MOSFETs (also called MOS devices) offer unique properties that have led to the revolution of the semiconductor industry.) We therefore observe that a “channel” of free electrons may be created at the interface between the insulator and the piece of silicon. the p-type silicon does contain a small number of electrons.. This revolution has culminated in microprocessors having 100 million transistors. (Even though doped with acceptors. 6. e. 6. 2007 at 13:42 282 (1) 6 Physics of MOS Transistors Today’s ﬁeld of microelectronics is dominated by a type of device called the metal-oxidesemiconductor ﬁeld-effect transistor (MOSFET).g. we begin with a simple geometry consisting of a conductive (e. 282 . as evident from Q = CV .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. from the piece of silicon. seeking models that prove useful in circuit design. we utilize the models to study MOS ampliﬁer topologies. potentially serving as a good conductive path if the electron density is sufﬁciently high. an insulator (“dielectric”). Operation of MOSFETs MOS Structure Operation in Triode Region Operation in Saturation I/V Characteristics MOS Device Models Large−Signal Model Small−Signal Model PMOS Devices Structure Models 6. Our treatment of MOS devices and circuits follows the same procedure as that taken in Chapters 2 and 3 for pn junctions. Illustrated in Fig.. Conceived in the 1930s but ﬁrst realized in the 1960s. such a structure operates as a capacitor because the p-type silicon is somewhat conductive. In order to arrive at the structure of the MOSFET. The key point here is that the density of electrons in the channel varies with V1 . In Chapter 7.1(a). electrons. it attracts negative charge. In this chapter. metal) plate.

Before delving into the operation of the MOSFET. The dielectric layer sandwiched between the gate and the substrate plays a critical role in the performance of transistors and is created by growing silicon dioxide (or simply “oxide”) on top 1 The capacitance between two plates is given by A=t. .cls v. and t is the dielectric thickness.4. The dependence of the electron density upon V1 leads to an interesting property: if. two contacts are attached to the substrate through two heavily-doped n-type regions because direct connection of metal to the substrate would not produce a good “ohmic” contact. for example. (Note that the current prefers to take the path of least resistance. 6. (c) current ﬂow as a result of potential difference.” To allow current ﬂow through the silicon material. The gate plate must serve as a good conductor and was in fact realized by metal (aluminum) in the early generations of MOS technology. Called the “gate” (G).2 These two terminals are called “source” (S) and “drain” (D) to indicate that the former can provide charge carriers and the latter can absorb them. (The p-type counterpart is studied in Section 6.2(a) reveals that the device is symmetric with respect to S and D.1 The ability of silicon fabrication technology to produce extremely thin but uniform dielectric layers (with thicknesses below 20 A today) has proven essential to the rapid advancement of microelectronic devices.) We draw the device as shown in Fig. let us consider the types of materials used in the device. as depicted in Fig. to achieve a strong control of Q by V . 2 Used to distinguish it from other types of contacts such as diodes. where is the “dielectric constant” (also called the “permitivity”). thus ﬂowing primarily through the channel rather than through the entire body of silicon. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Equation Q = CV suggests that.2. V1 can control the current by adjusting the resistivity of the channel.1 (a) Hypothetical semiconductor device. Figure 6. the value of C must be maximized. 6. it was discovered that noncrystaline silicon (“polysilicon” or simply “poly”) with heavy doping (for low resistivity) exhibits better fabrication and physical properties. The foregoing thoughts lead to the MOSFET structure shown in Fig. 2006] June 30. A is the area of each plate. depending on the voltages applied to the device. either of these two terminals can drain the charge carriers from the other.) This will serve our objective of building a voltage-controlled current source. the top conductive plate resides on a thin dielectric (insulator) layer. today’s MOSFETs employ polysilicon gates. 6.. with n-type source/drain and p-type substrate. i.2(b) for simplicity. 2007 at 13:42 283 (1) Sec. we allow a current to ﬂow from left to right through the silicon material. this transistor operates with electrons rather than holes and is therefore called an n-type MOS (NMOS) device.2(a) as a candidate for an amplifying device. Thus.e. which itself is deposited on the underlying p-type silicon “substrate.1 Conductive Plate Structure of MOSFET 283 Insulator V1 p−Type Silicon Channel of Electrons V1 V2 (a) (b) (c) Figure 6.2(c) depicts the circuit symbol for an NMOS transistor. wherein the arrow signiﬁes the source terminal. As explained in Section 6.1(c). by reducing the thickness of the dielectric layer separating the two plates. However. the term “ohmic” contact emphasizes bidirectional current ﬂow—as in a resistor. (b) operation as a capacitor. Figure 6.

. 6. only the depletion region capacitance associated with the two diodes must be taken into account.4. (b) side view.3). The outline is shown in Fig. Polysilicon S/D Diffusion Oxide n+ t ox = 18 A Length 90 nm n+ p −substrate Oxide−Silicon Interface Figure 6. Figure 6. 6.” referring to a fabrication method used in early days of microelectronics. 2007 at 13:42 284 (1) 284 Chap.3 shows some of the device dimensions in today’s state-of-the-art MOS technologies. We should also remark that these regions in fact form diodes with the p-type substrate (Fig. 6 Physics of MOS Transistors Source Gate Conductive Plate Drain n+ p −substrate Insulator (a) G S D n+ G n + n + S D (c) p −substrate (b) Figure 6. As explained later.2 (a) Structure of MOSFET. The n+ regions are sometimes called source/drain “diffusion. proper operation of the transistor requires that these junctions remain reverse-biased. The oxide thickness is denoted by tox . Thus.3 Typical dimensions of today’s MOSFETs. of the silicon area. 6. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Operation of MOSFET This section deals with a multitude of concepts related to MOSFETs. (c) circuit symbol.cls v.

5(a). more negative ions are exposed and the depletion region under the oxide becomes deeper. Resting on top of the oxide. 4 Note that this depletion region contains only one immobile charge polarity. as VG rises. 6. no current can ﬂow from the source to the drain.2. These concepts become clearer below. 2007 at 13:42 285 (1) Sec. Note that the electrons are readily provided by the n+ source and drain regions. Fortunately. Does this mean the transistor never turns on?! Fortunately.2 Operation of MOSFET 285 Qualitative Analysis Formation of Channel MOSFET as Resistor Channel Pinch−off I/V Characteristics I/V Characteristics Channel Charge Density Dain Current Triode and Saturation Regions Analog Properties Transconductance Channel−Length Modulation Other Properties Body Effect Subthreshold Conduction Velocity Saturation Figure 6. if VG becomes sufﬁciently positive. but we ignore that for now.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we do not show this connection in the diagrams.1 and 6. As VG increases from zero. 6. the positive charge on the gate must be mirrored by negative charge in the substrate. For simplicity.2 suggests that the MOSFET may conduct current between the source and drain if a channel of electrons is created by making the gate voltage sufﬁciently positive. Moreover.4 Note that the device still acts as a capacitor—positive charge on the gate is mirrored by negative charge in the substrate—but no channel of mobile charge is created yet.1(b) that.” VTH . the only current of interest is that ﬂowing between the source and the drain. whereas the depletion region in a pn junction consists of two areas of negative and positive ions on the two sides of the junction. thereby exposing negative ions and creating a depletion region [Fig. We say the MOSFET is on. ensuring that these diodes are not forwardbiased. Thus.1 Qualitative Analysis Our study of the simple structures shown in Figs. MOSFET as a Variable Resistor The conductive channel between S and D can be viewed as a resistor. 6. What happens as VG increases? To mirror the charge on the gate. and need not be supplied by the substrate. Furthermore. 6. This circuit does not appear particularly useful but it gives us a great deal of insight.g. . the substrate itself is also tied to zero. Note that the gate terminal draws no (low-frequency) current as it is insulated from the channel by the oxide. Can the source-substrate and drain-substrate junctions carry current in this mode? To avoid this effect. forming a conductive channel [Fig. where the source and drain are grounded and the gate voltage is varied.. 6. the gate remains insulated from other terminals and simply operates as a plate of a capacitor. another phenomenon precedes the formation of the channel. 6.3 we may face many combinations of terminal voltages and currents. We must study the dependence of this current upon the gate voltage (e..g. 2006] June 30. Our analysis will indeed conﬁrm these conjectures while revealing other subtle effects in the device. for a constant gate voltage). While we stated in Section 6. for a constant drain voltage) and upon the drain voltage (e. with the (low-frequency) gate current being zero.4 Outline of concepts to be studied.5(c)].5(b)]. the positive charge on the gate repels the holes in the substrate. Since the MOSFET contains three terminals. Let us ﬁrst consider the arrangement shown in Fig. in reality. and falls in the range of 300 mV to 500 mV. Recall from Fig. since the density of electrons in the channel must increase as VG 3 The substrate acts as a fourth terminal. The gate potential at which the channel begins to appear is called the “threshold voltage. It is interesting to recognize that the gate terminal of the MOSFET draws no (low-frequency) current.cls v. we expect that the magnitude of the current can be controlled by the gate voltage. We say the MOSFET is off. 6.1 that electrons are attracted to the interface. free electrons are attracted to the oxide-silicon interface.

Conceptually illustrated in Fig.7.cls v.7 Use of MOSFET to adjust signal levels. Since V cont v in RM R1 v out Figure 6.1 In the vicinity of a wireless base station. . possibly “saturating” the circuits and prohibiting proper operation.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. G S D Figure 6.6. Devise a variable-gain circuit that lowers the signal level as the cellphone approaches the base station. 2007 at 13:42 286 (1) 286 Chap. 6.5 (a) MOSFET with gate voltage. 6 Physics of MOS Transistors VG n+ p −substrate (a) VG n+ VG n+ p −substrate Depletion Region (b) VG n+ n+ p −substrate n+ Free Electrons Negative Ions (c) Figure 6. 2006] June 30. 6. the value of this resistor changes with the gate voltage.6 MOSFET viewed as a voltage-dependent resistor. (c) formation of channel. such a voltage-dependent resistor proves extremely useful in analog and digital circuits. the signal received by a cellphone may become very strong. Solution A MOSFET can form a voltage-controlled attenuator along with a resistor as shown in Fig. (b) formation of depletion region. becomes more positive (why?). Example 6.

In fact. 6. the device is off. (c) ID -VD characteristic. (b) ID -VG characteristic. (d) ID -VD characteristics for various gate voltages . If VG VTH . The slope of the characteristic is equal to 1=Ron . Our brief treatment of the MOS I/V characteristics thus far points to two different views of the operation: in Fig. .cls v. yielding the ID -VD characteristic shown in Fig. 2006] June 30.8(b)]. 6. no current ﬂows between S and D because the two terminals are at the same potential. 2007 at 13:42 287 (1) Sec. if VG VTH .8(c). Each view provides valuable insight into the operation of the transistor.1) the output signal becomes smaller as Vcont falls because the density of electrons in the channel decreases and RM rises. the source-drain path may act as a simple resistor. where Ron denotes the “on-resistance” of the transistor. no channel exists. MOSFETs are commonly utilized as voltage-dependent resistors in “variable-gain ampliﬁers. 5 The term “on-resistance” always refers to that between the source and drain as no resistance exists between the gate and other terminals.5(c). 6. 6. VG is varied while VD remains constant whereas in Fig. On the other hand. then ID 0 [Fig. and ID = 0 regardless of the value of VD .” Exercise What happens to RM if the channel length is doubled? In the arrangement of Fig.8 (a) MOSFET with gate and drain voltages. VD is varied while VG remains constant. vin RM + R1 (6. 6. 6.8(a) and examine the drain current (= source current).5 ID VG VD VD VTH (a) (b) VG n+ p −substrate n+ ID ID VD VG ID VG ID ID VD VG R on −1 ID VG3 VG2 VG1 VD VD (c) (d) Figure 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Operation of MOSFET 287 vout = R1 .8(b). We now raise the drain voltage as shown in Fig. 6.8(c).

The following example reinforces the concepts studied thus far. The ID -VG and ID -VD characteristics shown in Figs. 6. (d) ID -VD characteristics for different oxide thicknesses. the semiconductor industry has continued to reduce the gate oxide thickness. yielding a greater slope. 6. play a central role in our understanding of MOS devices. (b) ID -VD characteristics for different channel lengths. the resulting characteristics strengthen the notion of voltage-dependent resistance.2 Sketch the ID -VG and ID -VD characteristics for (a) different channel lengths.9(c)] or drain voltage [Fig. For this reason. 6. As the channel length increases. producing less drain current for a given gate voltage [Fig. the capacitance between the gate and the silicon substrate decreases. Consequently.cls v. 6. and (b) different oxide thicknesses. the current results from the drift of charge.9(a)]. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.8(b) and (c). we note that a given voltage results in less charge on the gate and hence a lower electron density in the channel. 2007 at 13:42 288 (1) 288 Chap. 6. the device suffers from a higher on-resistance. ID exhibits a smaller slope as a function of VD [Fig.8(d). Thus. (c) ID -VG characteristics for different oxide thicknesses.9 (a) ID -VG characteristics for different channel lengths. affect the I-V characteristics? As tox increases.6 Thus. If the mobility falls at high 6 Recall that the resistance of a conductor is proportional to the length. the drain current begins with lesser values as the channel length increases [Fig. from Q = CV . Similarly.9(d)]. How about the transport mechanism in a MOSFET? Since the voltage source tied to the drain creates an electric ﬁeld along the channel. It is therefore desirable to minimize the channel length so as to achieve large drain currents—an important trend in the MOS technology development. respectively. Depicted in Fig. ID ID Solution VTH (a) VG (b) VD ID ID VTH (c) VG (d) VD Figure 6. tox . so does the on-resistance.8(b) change if VG increases? The higher density of electrons in the channel lowers the on-resistance. Exercise The current conduction in the channel is in the form of drift. for VG VTH . . Example 6. 2006] June 30. 6 Physics of MOS Transistors How does the characteristic of Fig.9(b)]. Recall from Chapter 2 that charge ﬂow in semiconductors occurs by diffusion or drift. How does the oxide thickness.

2007 at 13:42 289 (1) Sec. (c) equivalence to devices in parallel. the dimension perpendicular to the length [Fig. We therefore observe that “lateral” dimensions such as L and W can be chosen by circuit designers whereas “vertical” dimensions such as tox cannot. the potential difference between 7 Recall that the resistance of a conductor is inversely proportional to the cross section area. what can we say about the on-resistance as the temperature goes up? While both the length and the oxide thickness affect the performance of MOSFETs. . 6. only the former is under the circuit designer’s control. (2) if the drain voltage remains higher than the source voltage. thus lowering the resistance between the source and the drain7 and yielding the trends depicted in Fig. it can be speciﬁed in the “layout” of the transistor. Channel Pinch-Off Our qualitative study of the MOSFET thus far implies that the device acts as a voltage-dependent resistor if the gate voltage exceeds VTH . producing a high drain current [Fig.10(c)].BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. To understand this effect. In reality. so does the width of the channel. Thus. 6. the transistor operates as a current source if the drain voltage is sufﬁciently positive. on the other hand. then the voltage at each point along the channel with respect to ground increases as we go from the source towards the drain. i. possibly limiting the speed of the circuit. The latter. 6.11(a)..).cls v. which itself is equal to the product of the width and thickness of the conductor. Another MOS parameter controlled by circuit designers is the width of the transistor.10 (a) Dimensions of a MOSFET (W and L are under circuit designer’s control. this effect arises from the gradual voltage drop along the channel resistance.10(a)].10(b). is deﬁned during fabrication and remains constant for all transistors in a given generation of the technology. a wider device can be viewed as two narrower transistors in parallel.2 Operation of MOSFET 289 temperatures. we make two observations: (1) to form a channel. the width of each device in the circuit must be chosen carefully. t ox W n+ L (a) n+ ID W ID W S G D VTH VG VD (b) (c) Figure 6. (b) ID characteristics for different values of W . and since the potential at the oxide-silicon interface rises from the source to the drain. Illustrated in Fig. We may then surmise that W must be maximized. 6. 6. 2006] June 30. however.e. From another perspective. but we must also note that the total gate capacitance increases with W . Since the gate voltage is constant (because the gate is conductive but carries no current in any direction). the potential difference between the gate and the oxide-silicon interface must exceed VTH . How does the gate width impact the I-V characteristics? As W increases.

) It follows that Q = WCox VGS . (Hereafter. VTH : (6. we have V = VGS . 2007 at 13:42 290 (1) 290 Chap.e. VTH ? Since V x now goes from 0 at x = 0 to VD VG .2. falling to a minimum at x = L. Nonetheless. we write C = WCox to account for the width of the transistor [Fig. and the MOSFET acts as a constant current source—similar to a bipolar transistor in the forward active region. if the drain voltage is high enough to produce [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6. Does this mean the transistor cannot conduct current? No.” From Q = CV . Moreover. Channel Charge Density Our derivations require an expression for the channel charge (i. we conclude that.. 6. 6. then the channel ceases to exist near the drain.12(a)]. we can now formulate the behavior of MOSFETs in terms of their terminal voltages. VD VTH . The device therefore contains no channel between L1 and L. 6 Physics of MOS Transistors the gate and the oxide-silicon interface decreases along the x-axis [Fig.2) . The density of electrons in the channel follows the same trend. VTH because no mobile charge exists for VGS VTH . then Q is the desired charge density. free electrons) per unit length. Note that the source-substrate and drain-substrate junctions carry no current.11(b)]. VG VD n+ ID Potential = V G Difference < VG n+ x = VG − VD Gate−Substrate Potential Difference V (x ) VG VD − VG L L x x (a) (b) Figure 6. once the electrons reach the end of the channel. we denote both the gate and drain voltages with respect to the source. We say the gate-substrate potential difference is not sufﬁcient at x = L to attract electrons and the channel is “pinched off” From these observations. 2006] June 30.cls v. 6. Denoting the gate capacitance per unit area by Cox (expressed in F/m2 or fF/m2 ). the device still conducts: as illustrated in Fig.2 Derivation of I/V Characteristics With the foregoing qualitative study.13(a)]. (b) gate-substrate voltage difference along the channel. What happens if VD rises even higher than VG . the voltage difference between the gate and the substrate falls to VTH at some point L1 L [Fig. VG . they experience the high electric ﬁeld in the depletion region surrounding the drain junction and are rapidly swept to the drain terminal. as shown in the next section. VTH at x = L. the drain voltage no longer affects the current signiﬁcantly.12(c). we note that if C is the gate capacitance per unit length and V the voltage difference between the gate and the channel.12(b)]. 6. 6.11 (a) Channel potential variation. also called the “charge density.

Eq. 6. Note that Q is expressed in coulomb/meter. noting that V x goes from zero to VD if the channel is not pinched off.15).12 (a) Pinchoff.2) is valid only near the source terminal. As shown in Fig. where the channel potential remains close to zero. W n+ n+ Figure 6. we denote the channel potential at x by V x and write Qx = WCox VGS . 2006] June 30. Now recall from Fig.14. (c) detailed operation near the drain. and the charge density falls as we go from the source to the drain. V x . Note from Chapter 2 that (1) I is given by the total charge that passes through the cross section of the bar in one second. 2007 at 13:42 291 (1) Sec.13 Illustration of capacitance per unit length. (6. VTH .cls v. and (2) if the carriers move with a velocity of v m/s. (b) variation of length with drain voltage. (6.2 Operation of MOSFET VG n+ Electrons 291 ID > V TH n+ VD VG VD VG n+ n+ ID VD V TH VG VD (a) VG n+ n+ ID VD E n+ 0 (b) L1 L x (c) Figure 6. Thus. then the charge enclosed in v meters along the bar passes through the cross .3) Drain Current What is the relationship between the mobile charge density and the current? Consider a bar of semiconductor having a uniform charge density (per unit length) equal to Q and carrying a current I (Fig. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.11(a) that the channel voltage varies along the length of the transistor. 6. 6.

6). we have v meters W t = t1 t = t1 + 1 s L h x1 V1 x x1 V1 x Figure 6. As explained in Chapter 2. VTH dV: (6. (6.9) . we write ID = WCox VGS .14 Device illustration for calculation of drain current.7) Z x=L x=0 ID dx = Z V x=VDS V x=0 n Cox W VGS .cls v. 6 Physics of MOS Transistors VG n+ n+ ID VD V (x ) L dx Figure 6. our immediate need is to ﬁnd an expression for ID in terms of the terminal voltages. V x and dV=dx must vary such that the product of VGS . Since the charge enclosed in v meters is equal to Q v . VTH n dV x : dx (6. and (6. 0 x section in one second. = +n dV . Combining (6. VTH and dV=dx is independent of x.5) (6. (6. V x . To this end. VDS : 2 L (6.4).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. dx (6. 2007 at 13:42 292 (1) 292 Chap. 2 ID = 1 n Cox W 2VGS . since ID must remain constant along the channel (why?). V x . I = Q v.3).15 Relationship between charge velocity and current. we obtain v = . V x .n E. While it is possible to solve the above differential equation to obtain V x in terms of ID (and the reader is encouraged to do that). VTH VDS .8) That is.6) Interestingly.4) where dV=dx denotes the derivative of the voltage at a given point. 2006] June 30.

a higher gate oxide capacitance leads to a larger electron density in the channel for a given gate-source voltage.g. VTH .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 293 (1) Sec. Illustrated in Fig.3 Solution VGS3 I D. Second.16). for a constant VGS . It is common to write W=L as the ratio of two values e. VTH 2 .max and VGS .. For example. Cox . the ratio remains unchanged but the gate capacitance increases.max2 VGS1 − V TH VGS1 VGS2 − V TH VGS3 − V TH VDS Figure 6. ID varies parabolically with VDS (Fig. First.max3 VGS2 I D.max VGS .max = 1 n Cox W VGS . 6. VTH . and W=L is to be expected: a higher mobility yields a greater current for a given drain-source voltage. 2006] June 30. As VGS increases.10) Example 6.8) to emphasize the choice of W and L. ID I D. 6.2 Operation of MOSFET 293 We now examine this important equation from different perspectives to gain more insight.max4 Parabola ID. the characteristics exhibit maxima that follow a parabolic shape themselves because ID. VGS − V TH VDS at VDS = VGS . Exercise What happens to the above plots if tox is halved? . 6.10(c)].16 Parabolic ID -VDS characteristic. Plot the ID -VDS characteristics for different values of VGS . reaching a maximum of ID 1 2 µ n C ox W (VGS − V TH ( L 2 Figure 6. and a larger W=L (called the device “aspect ratio”) is equivalent to placing more transistors in parallel [Fig. the individual values of W and L also become critical in most cases. 5 m=0:18 m (rather than 27. the linear dependence of ID upon n .cls v. VTH 2 2 L (6. if both W and L are doubled.17 MOS characteristics for different gate-source voltages.17. so do ID. 6. While only the ratio appears in many MOS equations.

11) Ron = From another perspective. Eq.g. An electronic antenna switch is therefore necessary here. Solution The system is designed such that the phone receives for half of the time and transmits for the other half.12) Figure 6. VTH VDS .19 Role of antenna switch in a cordless phone.19). (6. In fact. e.8 Receiver Receiver Transmitter Transmitter Figure 6. the device can operate as an electronic switch. ID VGS2 VGS1 VDS VDS VGS3 ID VGS3 VGS2 VGS1 W V . As predicted in Section 6.18).9) reduces to: exhibiting a linear ID -VDS behavior for a given VGS .. 6. VTH . every 20 ms (Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6 Physics of MOS Transistors The nonlinear relationship between ID and VDS reveals that the transistor cannot generally be modeled as a simple linear resistor. Ron = 1. L 1 (6. Example 6. 6. the equivalent on-resistance is given by VDS =ID : ID n Cox W VGS . (6. if VDS 2VGS . the antenna is alternately connected to the receiver and the transmitter in regular intervals. V : n Cox L GS TH (6. 2006] June 30. In particular.4 A cordless telephone incorporates a single antenna for reception and transmission. at small VDS (near the origin).e.1. Explain how the system must be conﬁgured. the parabolas in Fig. . for VGS = VTH .18 Detailed characteristics for small VDS .12) suggests that the on-resistance can be controlled by the gate-source voltage. 2007 at 13:42 294 (1) 294 Chap.17 can be approximated by straight lines having different slopes (Fig.. 8 Some cellphones operate in the same manner.2. i. 6. Thus.cls v. However.

12). 6. n Cox = 100 A=V2 . Assume the antenna can be modeled as a 50. If VDD = 1:8 V. we wish to ensure R on V out 50 Ω R on R ant Transmitter V in Figure 6.20 Signal degradation due to on-resistance of antenna switch.. and VTH = 0:4 V. this choice of W=L may still attenuate high-frequency signals. The circuit designer must therefore maximize W=L and VGS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. by no more than 10.) .15) (Since wide transistors introduce substantial capacitance in the signal path.4.cls v. the switch connecting the transmitter to the antenna must negligibly attenuate the signal.g. VDD . determine the minimum required aspect ratio of the switch.14) W 1276: L (6.5 In the cordless phone of Example 6.13) Ron 5:6 : Setting VGS to the maximum value. 6. 2006] June 30.20. How many switches are needed? In most applications. The following example illustrates this point. we obtain from Eq. Solution As depicted in Fig.2 Operation of MOSFET 295 Exercise Some systems employ two antennas.resistor. Example 6. it is desirable to achieve a low on-resistance for MOS switches. Vout 0:9 Vin and hence (6. e. each of which receives and transmits signals. 2007 at 13:42 295 (1) Sec. (6. (6.

W ID = 1 n Cox L VGS . Also.” the quantity VGS . 6 Physics of MOS Transistors Exercise What W=L is necessary if VDD drops to 1. 6.2 V? Triode and Saturation Regions Equation (6. In reality. the drain current reaches “saturation. VTH rather than VDS . (6. For the sake of brevity. MOSFETs are sometimes called “square-law” devices to emphasize the relationship between ID and the overdrive.VTH V x=0 n Cox W VGS . with the triode and saturation regions in MOSFETs appearing similar to saturation and forward active regions in bipolar transistors. We also use the term “deep triode region” for VDS transistor operates as a resistor. It follows that the integration in (6. respectively. becomes constant for VDS VGS . We say the device operates in the “triode region”9 if VDS VGS .12(b). The I-V characteristic of Fig.9) expresses the drain current in terms of the device terminal voltages.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 296 (1) 296 Chap. the integral on the right hand side is evaluated up to VGS . VTH .21 resembles that of bipolar devices.21). 2006] June 30.” . further increase in VDS simply shifts the pinch-off point slightly toward the drain. we hereafter denote L1 with L. VTH (Fig. In particular.e.12 that the channel experiences pinch-off if VDS = VGS . Called the “overdrive voltage. and be modiﬁed to ID 1 2 µ n C ox W (VGS − V TH ( L 2 Triode Region Saturation Region VGS − V TH VDS Figure 6.17) a result independent of VDS and identical to ID. It is unfortunate that the term “saturation” refers to completely different regions in MOS and bipolar I-V characteristics.” that is. VTH .21 Overall MOS characteristic. Z x=L x=0 1 ID dx = Z V x=VGS . VTH 2 .max in (6. implying that the current begins to fall for VDS VGS . 6. VTH plays a key role in MOS circuits.7) and (6.16) Note that the upper limits correspond to the channel pinch-off point. recall that Eqs. where the parabola). recall from Fig. 9 Also called the “linear region. i. VTH . from x = 0 to x = L1 in Fig.8) are valid only where channel charge exists. VTH (the rising section of the 2VGS . 6.8) must encompass only the channel. Thus.10) if we assume L1 L.. 2 1 (6.cls v. Consequently. V x . To understand why. VTH dV: (6. 6.

18) (6. VTH > VTH ID 1 2 µ n C ox W (VGS − V TH ( L 2 Saturated Triode Region Saturation Region M1 VGS − V TH VDS (a) (b) Figure 6. Let us assume M1 is saturated and proceed.cls v.6 = 0:4 V. 2006] June 30. Furthermore.17). 1V Figure 6. the square-law dependence of ID upon VGS .23. It is unclear a priori in which region M1 operates.2 Operation of MOSFET 297 We employ the conceptual illustration in Fig. 6.20) (6. what is the change in the drain voltage? VDD = 1.23 Simple MOS circuit. Note that the gate-drain potential difference suits this purpose and we need not compute the gatesource and gate-drain voltages separately. 2007 at 13:42 297 (1) Sec.22 Illustration of triode and saturation regions based on the gate and drain voltages. VTH suggests that the device can act as a voltage-controlled current source. Exhibiting a “ﬂat” current in the saturation region.19) VX = VDD . RD ID = 0:8 V: (6.18 5 kΩ Example 6.8 V RD ID X M1 W = 2 L 0. Assume n Cox = 100 A=V2 and VTH If the gate voltage increases by 10 mV. Calculate the bias current of M1 in Fig.22 to determine the region of operation. a MOSFET can operate as a current source having a value given by (6. Since VGS = 1 V. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution 1 ID = 2 n Cox W VGS . 6. VTH 2 L = 200 A: We must check our assumption by calculating the drain potential: (6.21) .

. With VGS = +1 V. the drain voltage must fall to VGS . Example 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. ID = VDDR VDS D = 240 A: Since ID scales linearly with W=L.22 therefore indicates that M1 indeed operates in saturation.cls v. (2) Bipolar devices exhibit an exponential IC -VBE characteristic while MOSFETs display a squarelaw dependence. If VGS increases by 1 mV. the aspect ratio of each device may be chosen differently to satisfy the design requirements. lowering VX to (6. If the gate voltage increases to 1. The illustration in Fig. W j = 240 A 2 L max 200 A 0:18 4 = 02::18 : ID = 248:04 A. the former provide a greater transconductance than the latter (for a given bias current). M1 is still saturated. Assume VTH = 0:4 V. Exercise What choice of RD places the transistor at the edge of the triode region? It is instructive to identify several points of contrast between bipolar and MOS devices.24) (6. (4) The gate of MOSFETs draws no bias current.7 Solution = 0:6 V for M1 to enter the triode (6. (6. (1) A bipolar transistor with VBE = VCE resides at the edge of the active region whereas a MOSFET approaches the edge of saturation if its drain voltage falls below its gate voltage by VTH . 2007 at 13:42 298 (1) 298 Chap.01 V. but we neglect this effect here. The 34-mV change in VX reveals that the circuit can amplify the input.28) 10 New generations of MOSFETs suffer from gate “leakage” current.27) (6.10 Determine the value of W=L in Fig. 6 Physics of MOS Transistors The drain voltage is lower than the gate voltage.22) VX = 0:766 V: (6.23 that places M1 at the edge of saturation and calculate the drain voltage change for a 1-mV change at the gate. (3) In bipolar circuits. That is. 6.25) . most transistors have the same dimensions and hence the same IS . then ID = 206:7 A. 2006] June 30. VTH region.23) Fortunately. whereas in MOS circuits. That is. but by less than VTH . 6.26) (6.

6.8 V RD ID V GS X M1 W = 2 L 0. VTH gives Solution = VDS = VDD . RD ID : Substituting for ID from (6. VTH 2 . VTH = VDD .1 + 1 + 2RD VDD n Cox W L RD n Cox W L q + VTH : (6. 2007 at 13:42 299 (1) Sec. R2D n Cox W VGS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 Operation of MOSFET 299 changing VX by VX = ID RD = 4:02 mV: The voltage gain is thus equal to 4. . (6. Calculate the maximum allowable gate voltage in Fig.32) VGS = .24 Simple MOS circuit.31) VGS .8 Figure 6. L and hence VGS . VDD = 1.29) (6.18 5 kΩ Example 6. 2006] June 30.17) (6. 6.33) Exercise Calculate the value of VGS if mun Cox = 100 A=V2 and VTH = 0:4 . At the edge of saturation.cls v.1 + 1 + 2RD VDD n Cox W L RD n Cox W L q : (6. VTH = Thus.30) Exercise Repeat the above example if RD is doubled. VGS .02 in this case.24 if M1 must remain saturated.

3 Channel-Length Modulation In our study of the pinch-off effect.17) by a corrective term: L is constant. 2007 at 13:42 300 (1) 300 Chap. the relative change in L (and hence in ID ) for a given change in VDS is smaller (Fig.25 Variation of ID in saturation region. In other words. we assume hand side of (6. L where is called the “channel-length modulation coefﬁcient. we observed that the point at which the channel vanishes in fact moves toward the source as the drain voltage increases. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. channel-length modulation results in a ﬁnite output impedance given by the inverse of the ID -VDS slope in Fig. 6.17).9 11 Since different MOSFETs in a circuit may be sized for different ’s. . This is because is inversely proportional to L: for a longer channel.12(b) varies with VDS to some extent.) L1 ID ID L2 VDS VDS Figure 6.11 (By contrast.34) 1 ID = 2 n Cox W VGS . 6 Physics of MOS Transistors 6.” While only an approximation.26 Channel-length modulation. 6. What is the device output impedance? Example 6. this linear dependence of ID upon VDS still provides a great deal of insight into the circuit design implications of channel-length modulation. Unlike the Early effect in bipolar devices (Chapter 4).26).25. ID 1 2 µ n C ox W (VGS − V TH ( L 2 VGS − V TH Figure 6. the amount of channel-length modulation is under the circuit designer’s control.25. but multiply the right (6. 6. the base width of bipolar devices cannot be adjusted by the circuit designer. (6. A MOSFET carries a drain current of 1 mA with VDS = 0:5 V in saturation. Determine the change in ID if VDS rises to 1 V and = 0:1 V. 2006] June 30. Called “channel-length modulation” and illustrated in Fig. this phenomenon yields a larger drain current as VDS increases because ID 1=L1 in Eq. Similar to the Early effect in bipolar devices.1 . yielding a constant Early voltage for all transistors in a given technology.cls v. VDS To account for channel-length modulation.2. we do not deﬁne a quantity similar to the Early voltage here. VTH 2 1 + VDS . the value of L1 in Fig.

V 2 1 + V ID2 = 2 n ox L GS TH DS 2 and hence (6. VDS2 = 1 V.35) (6.41) (6. 6. The same effect was observed for bipolar current sources in Chapters 4 and 5.cls v.1 .2 Operation of MOSFET 301 Solution We write ID1 = 1 n Cox W VGS .36).36) V ID2 = ID1 1 + VDS2 : 1+ DS 1 With ID1 (6. ID2 = 1:048 mA: The change in ID is therefore equal to 48 A.39) (6. Thus. W=L remains unchanged but drops to 0. 2006] June 30. 1 + V ID2 = ID1 1 + VDS2 DS 1 = 1:024 mA: That is. yielding an output impedance of (6.40) Exercise Does W affect the above results? The above example reveals that channel-length modulation limits the output impedance of MOS current sources.37) = 1 mA. Assuming Example 6. (6.10 Solution 1=L. VDS1 = 0:5 V.9 if both W and L are doubled.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 .42) = 24 A and rO = 20:84 k : (6. calculate ID and rO in Example 6.35) and (6.05 V.38) rO = VIDS D = 10:42 k : (6. 2007 at 13:42 301 (1) Sec. and = 0:1 V.43) . ID (6. VTH 2 1 + VDS1 2 L 1 C W V . In Eqs.

6 Physics of MOS Transistors Exercise What output impedance is achieved if W and L are quadrupled and ID is halved. Among these three expressions for gm . (1) gm is proportional to W=L for a given ID .47) GS TH revealing that (1) gm is linearly proportional to ID for a given VGS . For a MOSFET operating in saturation. a MOS transistor can be characterized by its transconductance: @I gm = @V D : GS (6.17) gives p gm = 2n Cox W ID : L r (6. VTH . VTH from (6. (6. VTH change if both W=L and Equation (6. VTH . Eq. if VGS remains constant and the width of the device is doubled. these dependencies prove critical in understanding performance trends of MOS devices and have no counterpart in bipolar transistors. and (2) gm is proportional to a given W=L. 6. then both IC and gm increase linearly. VTH . and (2) gm is inversely proportional to VGS . we have concluding that (1) gm is linearly proportional to W=L for a given VGS .12 . (6. VTH for a given W=L. These results can be understood intuitively if we view the doubling of W=L and ID as shown in Fig. . If the bipolar transistor width is increased while VBE remains constant.17) suggests that the overdrive remains constant. The reader can show that this trend applies to any type of transistor.17). dividing (6. 2007 at 13:42 302 (1) 302 Chap.cls v. Indeed. Solution 12 There is some resemblance between the second column and the behavior of gm = IC =VT . how do gm and VGS ID are doubled? Example 6. (6. Moreover.4 MOS Transconductance As a voltage-controlled current source. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.46) indicates that gm is also doubled. L (6.45) by (6. Moreover.46) pI D for I gm = V 2.46) is more frequently used because ID may be predetermined by power dissipation requirements.17) for the saturation region. Also. substituting for VGS .2.27.DV . and (2) gm is linearly proportional to VGS . Using Eq. VTH for a given ID . we obtain gm = n Cox W VGS .1. Summarized in Table 6. thereby doubling the transconductance. it is as if two transistors carrying equal currents are placed in parallel. 2006] June 30.44) This quantity serves as a measure of the “strength” of the device: a higher value corresponds to a greater change in the drain current for a given change in VGS .11 . (6.45) That is.

Exercise How do gm and VGS .49) . 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 m). 13 Of course. then the device experiences less velocity .49) is not accurate. 2007 at 13:42 303 (1) Sec. carrier mobility degrades.2 under velocity saturation conditions. 2006] June 30.48) (6.13 saturation and (6.1 Various dependencies of gm . if L is increased substantially.. the I/V characteristics no longer follow the square-law behavior.2. ID now exhibits a linear dependence on VGS This section can be skipped in a ﬁrst reading.27 Equivalence of a wide MOSFET to two in parallel.5 Velocity Saturation Recall from Section 2.1. VTH : Interestingly. Let us examine the derivations in Section 6. As a result. 6. VTH change if only W and ID are doubled? 6. V GS V GS V DS V DS Figure 6. eventually leading to a constant velocity. while VDS remains constant.cls v. VTH and no dependence on L.3 that at high electric ﬁelds. Owing to their very short channels (e.2. we have ID = vsat Q = vsat WCox VGS . (6. modern MOS devices experience velocity saturation even with drain-source voltages as low as 1 V. Denoting the saturated velocity by vsat .g.2 Operation of MOSFET 303 W Constant L VGS − V TH Variable g g m m W Variable L VGS − V TH Constant g g m m W Variable L VGS − V TH Constant g g m m ID VGS − V TH ID W L W L 1 VGS − V TH Table 6.

n Cox W=L = 50. An interesting phenomenon occurs as the source-substrate potential difference departs from zero: the threshold voltage of the device changes.52) and the typical values for VTH = 0:698 V: 14 The p+ island is necessary to achieve an “ohmic” contact with low resistance. respectively. In particular. Substrate Contact VS p+ p −substrate n+ VG VD n+ VG VS VD Figure 6. VG = VD = 1:4 V.” this phenomenon is formulated as VTH = VTH 0 + j2 F + VSB j . then the source-substrate junction remains reverse-biased and the device still operates properly. Since the source-body voltage. this condition need not hold in all circuits. and F yield (6. and VTH 0 = 0:6 V. we have assumed that both the source and the substrate (also called the “bulk” or the “body”) are tied to ground.50) (6.14 The dashed line added to the transistor symbol indicates the substrate terminal.28 illustrates this case. Eq.6 Other Second-Order Effects (6. and and F are p technology-dependent parameters having typical values of 0. Figure 6.4 V and 0.4 V.53) Solution = 0:5 V. Called “body effect. VSB Example 6.52) where VTH 0 denotes the threshold voltage with VSB = 0 (as studied earlier). VTH increases.cls v. a quantity independent of L and ID . 2006] June 30.51) Body Effect In our study of MOSFETs. Determine the drain current if = 0.28. We denote the voltage difference between the source and the substrate (the bulk) by VSB . j2 F j. 2007 at 13:42 304 (1) 304 Chap.2. as the source becomes more positive with respect to the substrate. The source terminal is tied to a potential VS with respect to ground while the substrate is grounded through a p+ contact.28 Body effect. For example. However. .12 = 100 A=V2 . if the source terminal rises to a positive voltage while the substrate is at zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. p p (6. In the circuit of Fig. 6 Physics of MOS Transistors We also recognize that @I gm = @V D GS = vsat WCox. 6. 6. (6. assume VS = 0:5 V.

6.58) .29(c)]. For VDS VGS . Called “subthreshold conduction.13 Solution Noting that the device operates in saturation (why?). 2006] June 30. and the device conducts a small current even for VGS VTH .34) to express the device behavior: 2 ID = 1 n Cox W 2VGS . the transistor acts as a voltage-controlled current source.56) (6. Note that ID does depend on VDS and is therefore not an ideal current source.3 MOS Device Models With our study of MOS I/V characteristics in the previous section. VTH 2 1 + VDS Saturation Region 2 L (6. 2007 at 13:42 305 (1) Sec. with VG = VD . Finally. We neglect body effect in this book.3. lending itself to the model shown in Fig. (6.” this effect has become a critical issue in modern MOS devices and is studied in more advanced texts. the transistor can be viewed as a voltage-controlled resistor [Fig. we now develop models that can be used in circuit analysis and design.1 Large-Signal Model For arbitrary voltage and current levels.30(a) versus V1 as V1 varies from zero to VDD . VS . VTH . 6. but it can still incorporate a voltage-controlled current source as depicted in Fig. VTH .57) In the saturation region. Subthreshold Conduction The derivation of the MOS I/V characteristic has assumed that the transistor abruptly turns on as VGS reaches VTH . Body effect manifests itself in some analog and digital circuits and is studied in more advanced texts.55) Exercise Sktech the drain current as a function of VS as VS goes from zero to 1 V. VTH 2 2 L = 102 A: (6.29(a). if VDS 2VGS . 6. Sketch the drain current of M1 in Fig. 6. the gate remains an open circuit to represent the zero gate current.29(b). In reality. the model must reﬂect the triode region. we write 1 ID = 2 n Cox W VGS .3 MOS Device Models 305 Also. Example 6. 6. 6. VDS Triode Region 2 L ID = 1 n Cox W VGS . VTH VDS . formation of the channel is a gradual effect.cls v. In all three cases.54) (6.9) and (6. Assume = 0. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the device operates in saturation (why?) and hence ID = 1 n Cox W VG . we must resort to Eqs. VTH 2 L (6.

(b) triode region. VTH . V1 . If V1 reaches VDD .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3. 6 Physics of MOS Transistors ID S µ n C ox W (VGS − V TH ( (1+ λVDS ) L 2 (a) VGS < V TH VDS > VGS − V TH G D G 1 2 2 µ n C ox W [ 2 (VGS − V TH ( VDS + VDS ] L VGS < V TH VDS >> 2 (VGS − V TH ( D 1 W (V µ n C ox GS − V TH ( L ID S R on = S (b) (c) Figure 6.30 (a) Simple MOS circuit. As V1 rises.5 V and VDD = 2 6. VDD M1 V1 VDD − V TH V1 (a) (b) ID Figure 6. The development . VTH varies with V1 if the substrate is tied to ground. large-signal models can be reduced to linear. VGS drops to VTH . VTH 2 : 2 L (6. Exercise Repeat the above example if the gate of V. (b) variation of ID with V1 .59) At V1 = 0. VGS falls and so does ID .30(b).2 Small-Signal Model If the bias currents and voltages of a MOSFET are only slightly disturbed by signals. 2006] June 30. owing to body effect. 2007 at 13:42 306 (1) 306 VGS < V TH VDS < VGS − V TH G D 1 2 Chap. small-signal representations.cls v. (c) deep triode region. Note that.29 MOS models for (a) saturation region. turning the transistor off. the nonlinear. The drain current thus varies as illustrated in Fig. = 1 n Cox W VDD . M1 is tied to a voltage equal to 1. 6. VGS = VDD and the device carries maximum current.

(b) inclusion of channel-length modulation.. 6. 6. variation of iD with vDS . 2007 at 13:42 307 (1) Sec. . where iD = gm vGS and the gate remains open. we draw the basic model as in Fig. Viewing the transistor as a voltage-controlled current source.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Of particular interest to us in this book is the small-signal model for the saturation region.cls v. i.31(a). To represent channel-length modulation. we add a resistor as in Fig.31 (a) Small-signal model of MOSFET. 2006] June 30. 6.e.31(b): G D G D v GS g v GS m v GS g v GS m rO S (a) S (b) Figure 6.3 MOS Device Models 307 of the model proceeds in a manner similar to that in Chapter 4 for bipolar devices.

60) (6.64) 1 rO = I = 20 k : D (6.1 . r (6. .65) (6.5 mA. If n Cox = 0:1 V. @I . Example 6. Exercise Repeat the above example if W=L is doubled.62) A MOSFET is biased at a drain current of 0.63) (6. gm rO . W=L = 10. yielding (6.66) This means that the intrinsic gain.14 = 100 A=V2 . and Solution We have gm = 2nCox W ID L = 11 : k Also. V 2 : 2 n Cox L GS TH 1 rO I : D Since channel-length modulation is relatively small.61) can be approximated as ID . calculate its small-signal parameters. the denominator of (6.1 rO = @V D DS (6.61) 1 =1 W V . (Chapter 4) is equal to 20 for this choice of device dimensions and bias current.

as illustrated in Fig.32 (a) Structure of PMOS device. approaching saturation as VD falls to VG . 2006] June 30. VTH = VG + jVTH j.33. Assume VDD = 2:5 V and jVTH j = 0:5 V. to turn the device on. changing the doping polarities of the substrate and the S/D areas results in a “PMOS” device. 6. The transistor operates in the triode region if the drain voltage is near the source potential. In the circuit of Fig. the gate-source . That is. (b) PMOS circuit symbol. determine the region of operation of M1 as V1 goes from VDD to zero.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6 Physics of MOS Transistors 6. Following the conventions used for bipolar devices.32(c) conceptually illustrates the gate-drain voltages G required for each region of operation. As V1 falls and approaches VDD .cls v.4 PMOS Transistor Having seen both npn and pnp bipolar transistors.32(b). 6. For V1 Solution = VDD . Figure 6. 2007 at 13:42 308 (1) 308 Chap. VGS VTH . where VTH itself is negative.32(a). with the source terminal identiﬁed by the arrow and placed on top to emphasize its higher potential.15 Figure 6. VDD M1 V1 1V Example 6. we draw the PMOS device as in Fig. S D S G D (a) Triode Region Edge of Saturation (b) Saturation Region p+ n −substrate p+ ID > VTHP VTHP < VTHP (c) Figure 6. VGS = 0 and M1 is off. Indeed.33 Simple PMOS circuit. (c) illustration of triode and saturation regions based on gate and drain voltages. The channel now consists of holes and is formed if the gate voltage is below the source potential by one threshold voltage.jVTH j. 6. the reader may wonder if a p-type counterpart exists for MOSFETs.

VDS : L Alternatively. yielding RX = vX i X (6. L where is multiplied by a negative sign. Example 6. 6. (c) smallsignal model of (b). 6.34(b).32(b). At this point. . the transistor enters the triode region further.72) 15 To make this equation more consistent with that of NMOS devices [Eq. i.5 V.32(c)]. The following example illustrates this point. we can deﬁne itself to be negative and express ID as 1=2p Cox W=LVGS VTH 2 1 + VDS . turning the device on.cls v.e.tri j = 1 p Cox W 2jVGS j .4 PMOS Transistor 309 potential is negative enough to form a channel of holes. jVTH j = 0:5 V. (6.sat = .34 (a) Diode-connected NMOS and PMOS devices.jVTH j = +2 V while VD = +1 V. the small-signal equivalent appears as depicted in Fig.71) vX = gm1 vX + rO1 i1 X (6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution For the NMOS version. M1 is saturated [Fig.tri = .sat j = 2 p Cox W jVGS j . 6. VG = VDD . jVTH j2 1 + jVDS j L (6. 6. The voltage and current polarities in PMOS devices can prove confusing. a negative carries little physical meaning.15 In the triode region. As V1 falls further. VTH VDS . (6. 2007 at 13:42 309 (1) Sec.. 2 p Cox W VGS . Assume 6= 0.67) 1 2 ID.70) 2 jID. (b) small-signal model of (a). VGS becomes more negative and the transistor current rises. As V1 goes below 0. M1 is at the edge of the triode region. determine the small-signal resistances RY . VTH 2 1 .34)]. Using the current direction shown in Fig. RX VDD M2 M1 RY vx iX v1 gm1v 1 r O1 vY iY v1 RX and M2 gm2v 1 r O2 (a) (b) (c) Figure 6. jVTH jjVDS j . we express ID in the saturation region as 1 ID.31). 6.16 For the conﬁgurations shown in Fig.68) 1 jID. 2006] June 30. For V1 = +1 V . 2 p Cox W 2VGS . 6.69) (6. But. both equations can be expressed in terms of absolute values: (6. VDS : 2 L The small-signal model of PMOS transistor is identical to that of NMOS devices (Fig. VDS .34(a). .

Fortunately. thereby accommodating PMOS transistors.16 and the higher cost of CMOS processes seemed prohibitive. the structures shown in Fig.32(a) reveal that the two require different types of substrate.35 CMOS technology. an “n-well” encloses a PMOS device while the NMOS transistor resides in the p-substrate. the above structure requires more complex processing than simple NMOS or PMOS devices. 2006] June 30. Owing to the lower mobility of holes (Chapter 2). 16 The ﬁrst Intel microprocessor. we draw the equivalent as shown in Fig.cls v.35. PMOS devices exhibit a poorer performance than NMOS transistors. the small-signal resistance is equal to 1=gm if ! 0. was realized in NMOS technology. Called “complementary MOS” (CMOS) technology.2(a) and 6.46) indicates that the transconductance of a PMOS device is lower for a given drain current. Eq. However.34(c) and write (6. We therefore prefer to use NMOS transistors wherever possible. In fact. 6. As illustrated in Fig. many signiﬁcant advantages of complementary devices eventually made CMOS technology dominant and NMOS technology obsolete.5 CMOS Technology Is it possible to build both NMOS and PMOS devices on the same wafer? Figures 6. In analogy with their bipolar counterparts [Fig.73) RY = vY iY vY = gm2 vY + rO1 i1 Y 1 jjr : =g O2 m2 (6. (6. 6.34(a) are called “diode-connected” devices and act as two-terminal components: we will encounter many applications of diode-connected devices in Chapters 9 and 10. . the 4004. 6 Physics of MOS Transistors = g 1 jjrO1 : m1 For the PMOS version.44(a)]. 6. 2007 at 13:42 310 (1) 310 Chap. a local n-type substrate can be created in a p-type substrate. For example.76) In both cases. the ﬁrst few generations of MOS technology contained only NMOS transistors.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. NMOS Device B S PMOS Device D S G G D B p+ n+ n+ p+ n −well p+ n+ p −substrate Figure 6.75) (6.74) (6. 6. 4.

VTH 2 .e.cls v.6 Comparison of Bipolar and MOS Devices 311 6. The current is also proportional to the device aspect ratio. A MOSFET consists of a conductive plate (the “gate”) atop a semiconductor substrate and two junctions (“source” and “drain”) in the substrate. That is. the device operates a voltage-dependent resistor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. A measure of the small-signal performance of voltage-dependent current sources is the “transconductance. MOSFETs operating in the saturation region behave as current sources and ﬁnd wide application in microelectronic circuits. the charge density near the drain falls.6 Comparison of Bipolar and MOS Devices Having studied the physics and operation of bipolar and MOS transistors. Note that the exponential IC -VBE dependence of bipolar devices accords them a higher transconductance for a given bias current. In this region. VTH and pinch-off occurs.2 shows some of the important aspects of each device. As the drain voltage rises. MOSFETs are electronic devices that can operate as voltage-dependent current sources. the drain current is proportional to VGS .. a depletion region is formed in the substrate under the gate area. 2006] June 30. If the drain voltage reaches one threshold below the gate voltage. the device is not an ideal current source. Table 6. mobile carriers are attracted to the oxide-silicon interface and a channel is formed.” deﬁned as the change in the output current divided by the change in . As the gate voltage rises. the channel ceases to exist near the drain. Called “channel-length modulation. 6. As the drain voltage exceeds VGS . W=L. the drain voltage is less than one threshold below the gate volatge. If the drain-source voltage is small.7 Chapter Summary A voltage-dependent current source can form an ampliﬁer along with a load resistor. In this region. tem MOSFETs enter the “saturation region” if channel pinch-off occurs.2 Comparison of bipolar and MOS transistors.” MOSFETs operate in the “triode” region if the drain voltage is more than one threshold below the gate voltage. the drain current is a function of VGS and VDS . we can now compare their properties. Bipolar Transistor Exponential Characteristic Active: VCB > 0 Saturation: VCB < 0 Finite Base Current Early Effect Diffusion Current − MOSFET Quadratic Characteristic Saturation: VDS < VGS − V TH Triode: VDS > VGS − V TH Zero Gate Current Channel−Length Modulation Drift Current Voltage−Dependent Resistor Table 6.” this effect leads to variation of drain current in the saturation region. Beyond a certain gate-source voltage (the “threshold voltage”). The gate draws nearly zero current because an insulating layer separates it from the substrate. The gate controls the current ﬂow from the source to the drain. leading to “pinch-off. the drain end of the channel begins to move toward the source. 6. i. reducing the effective length of the device. 2007 at 13:42 311 (1) Sec.

An NMOS device carries 1 mA with VGS . VTH and VDS and measuring ID ? 7. where the charge density approaches zero? Calculate the total charge stored in the channel of an NMOS device if Cox = 10 fF=m2 . Is it possible to determine these quantities by applying different values of VGS . NMOS and PMOS transistors are fabricated on the same substrate to create CMOS technology. and VTH = 0:4 V for NMOS devices and devices. calculate VDS and W=L.0:4 V for PMOS 1.VTH = 0:8 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. In the following problems.6 mA with VGS . The transconductance of MOSFETs can be expressed by one of three equations in terms of the bias voltages and currents. Plot both V x and dV=dx as a function of x for different values of W or VTH . Assuming ID is constant. solve Eq.cls v. Referring to Fig. If both devices operate M1 W L W L M2 M eq Figure 6. unless otherwise stated. The drain current of a MOSFET in the triode region is expressed as 2 ID = n Cox W VGS . VTH VDS .4) indicates that the charge density and carrier velocity must change in opposite directions if the current remains constant. Operation across different regions and/or with large swings exempliﬁes “large-signal behavior.36. Meq . 4. the MOSFET can be represented by a small-signal model consisting of a linear voltage-dependent current source and an output resistance.VTH = 0:6 V and 1. Problems = 200 A=V2 . 1 VDS : L 2 (6. . explain intuitively why this combination is equivalent to a single transistor. . 6.” If the signal swings are sufﬁciently small. 2007 at 13:42 312 (1) 312 Chap. L = 0:1 m. 3. Assume VDS = 0. VTH = 1 V. (6. 6. 6 Physics of MOS Transistors the input voltage. Two identical MOSFETs are placed in series as shown in Fig. Equation (6. What are the width and length of Meq ? Consider a MOSFET experiencing pinch-off near the drain.11 and assuming that VD 0.77) Suppose the values of n Cox and W=L are unknown. (a) Sketch the electron density in the channel as a function of x.36 2. 6. 2006] June 30. as resistors. The small-signal model is derived by making a small change in the voltage difference between two terminals while the the other voltages remain constant. and VGS . assume n Cox p Cox = 100 A=V2 . If the device operates in the triode region. W = 5 m.7) to obtain an expression for V x. (b) Sketch the local resistance of the channel (per unit length) as a function of x. The small-signal models of NMOS and PMOS devices are identical. How can this relationship be interpreted at the pinch-off point. 5.

11. Deﬁne gm = @ID =@VGS for a constant VDS . 9. Compute the transconductance of a MOSFET operating in the triode region. If the supply voltage is 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Explain why gm = 0 for VDS = 0. we can deﬁne an incremental drain-source resistance as rDS. 2007 at 13:42 313 (1) Sec. An NMOS device operating with a small drain-source voltage serves as a resistor.8 V.7 Chapter Summary 313 8. For a MOS transistor biased in the triode region. Explain why this is not possible.cls v. what is the minimum on-resistance that can be achieved with W=L = 20? 10. We wish to use an NMOS transistor as a variable resistor with Ron = 500 at VGS = 1 V and Ron = 400 at VGS = 1:5 V.tri = @V DS . 6. 2006] June 30.

VTH . Compare the results.1 : (6. 6. In the circuit of Fig. Determine the transconductance of such a device. It is possible to deﬁne an “intrinsic time constant” for a MOSFET operating as a resistor: = Ron CGS . (b) Repeat part (a) for V1 = 0:5 V. (a) For V1 = 0. 6. plot ID as a function of VGS for different values of VDS . 17. Obtain an expression for and explain what the circuit designer must do to minimize the time constant. If Vin 0.78) Derive an expression for this quantity.17). . 16. Advanced MOS devices do not follow the square-law behavior expressed by Eq. VTH vsat . and we may instead write: ID = WCox VGS .37 14. (6. Determine the transconductance of such a device. 2 L (6.80) where is less than 2. explain why the peaks of the parabolas lie on a parabola themselves. (6. 13.81) where vsat is a relatively constant velocity. the square-law behavior is not valid.37. such that the circuit attenuates the signal by only 5. determine W=L VG M1 RL V in Vout Figure 6. 15. For an NMOS device. For MOS devices with very short channel lengths. @ID . Assume VG = 1:8 V and RL = 100 .79) where CGS = WLCox . 12. where V0 is on the order of a few millivolts.37.17. In the circuit of Fig. In Fig. 6. the input is a small sinusoid superimposed on a dc level: Vin = V0 cos !t + V1 . 18. M1 serves as an electronic switch. obtain W=L in terms of RL and other parameters so that Vout = 0:95Vin . A somewhat better approximation is: ID = 1 n Cox W VGS . (6.

compute W=L of M1 in Fig. explain what happens if the gate oxide thickness is doubled due to a manufacturing error.38.5 V M1 0. Determine the region of operation of M1 in each of the circuits shown in Fig.5 V 2V 1. what is the minimum allowable value of VDD if M1 must not enter the .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 6.5 V (g) (h) (i) Figure 6.5 V M1 0. Assume = 0.5 V 0.5 V 0.5 V 1. 2006] June 30.2 V 1V 0. 6. Determine the region of operation of M1 in each of the circuits shown in Fig. 24. 6.2 V (b) M1 M1 0.38 19.5 V M1 1V M1 0.5 V 2V 1.41 such that the device operates at the edge of saturation. 20.e.5 V 0. M1 1V 1V M1 (a) 1V 0. 6.5 V M1 0.39. If VDS1 = 0:5 V and VDS2 = 1 V. Using the value of W=L found in Problem 22.5 V 0.40) match to within 1. i. 2007 at 13:42 314 (1) 314 Chap. In the Fig.. 6 Physics of MOS Transistors M1 0.5 V (d) (e) (f) M1 0. what is the maximum tolerable value of ? 22.5 V (a) (b) (c) M1 1. 0:99ID2 ID1 1:01ID2.2 V 0.42. 6.39 21. Two current sources realized by identical MOSFETs (Fig. 23.cls v.5 V 0.5 V M1 0.7 V (c) (d) Figure 6.

41 VDD = 1. Assuming W=L = 10=0:18 = 0:1 V. = 0. In Fig. Calculate the bias current of M1 in Fig. 6. 2006] June 30.1 .42 triode region? Assume = 0.43. Assume = 0.7 Chapter Summary 315 I D1 M1 VB I D2 M2 Figure 6. . 6. Also. 28. 25. 2007 at 13:42 315 (1) Sec. 6. 6. Assume = 0.47. Assume VX goes from 0 to VDD = 1:8 V.44 for a bias current of I1 . calculate the drain current of M1 in Fig.43 26.8 V RD 500 Ω 1V M 1 W = 10 L 0. 27.18 Figure 6. 29. 6. 6. Compute the value of W=L for M1 in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.46.cls v. derive a relationship among the circuit parameters that guarantees M1 operates VDD RD M1 W L Figure 6. and VDD = 1:8 V. Sketch IX as a function of VX for the circuits shown in Fig.8 V RD 1 kΩ 1V M1 Figure 6.40 VDD = 1. Determine at what value of VX the device changes its region of operation.45 if = 0. at the edge of saturation.

1 .8 V M1 RS Figure 6.46 1 kΩ VDD RD M1 Figure 6. 6. VTH = 0:5 V.8 V M1 M1 VX (a) 1V 1V IX IX M1 VX IX M1 VX IX VX (b) (c) (d) Figure 6. (a) Determine W=L if ID = 0:5 mA.45 VDD = 1.cls v. What value of VB places the VDD = 1. W=L = 20=0:18 and = transistor at the edge of saturation? RD 5 kΩ 0:1 V.44 VDD RD M1 W L Figure 6. In the circuit of Fig. (c) Determine ID if VGS .8 V M1 VB Figure 6. 2006] June 30. VTH = 0:5 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.48. 2007 at 13:42 316 (1) 316 Chap.48 31. An NMOS device operating in saturation with 1=50 . = 0 must provide a transconductance of .47 30. (b) Determine W=L if VGS . 6 Physics of MOS Transistors VDD = 1.

35. VTH is doubled but ID remains constant. With the value of W=L obtained in Problem 41. of a MOSFET (a) as a function of VGS .8 V RD 100 VDD = 1. Determine the region of operation of M1 in each circuit shown in Fig. 6. Repeat Problem 36 for = 0:2 V.1 and W=L = 20=0:18. VDD = 1. VTH is constant. gm rO . Construct the small-signal model of the circuits depicted in Fig. 6.8 V M1 0. 38. Determine how the transconductance of a MOSFET (operating in saturation) changes if (a) W=L is doubled but ID remains constant. The “intrinsic gain” of a MOSFET operating in saturation is deﬁned as gm rO .56 if all of the transistors operate in saturation and 6= 0. Also.49.55. VTH if ID is constant. An NMOS device with = 0:1 V. 2006] June 30. what value of W=L places M1 at the edge of saturation in Fig. determine the operating point of M1 in each circuit depicted in Fig. Assume VDS is constant.54. = 0. If W=L = 10=0:18 and = 0. Assume all transistors operate in saturation and 6= 0. 41.8 V M1 2 kΩ VDD = 1. 6. If = 0.8 V RD 5 kΩ VDD = 1.8 V 1 mA Ω M1 1V M1 M1 (a) (b) (c) VDD = 1. Construct the small-signal model of each circuit shown in Fig.53? 42. Assuming a constant VDS . 45. 6. (b) VGS .cls v. Sketch IX as a function of VX for the circuits shown in Fig.5 mA (d) (e) Figure 6. 6. VTH remains constant. Determine the region of operation of M1 in each circuit shown in Fig. 6. 33. 39.50. . 40. (c) ID is doubled but W=L remains constant. Determine at what value of VX the device changes its region of operation. plot the intrinsic gain.51. Derive an expression for gm rO and plot the result as a function of ID .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. If = 0:1 V. 37.1 .49 34. what happens if VB changes to +0:8 V? 43. 6. (d) ID is doubled but VGS . 6. (b) as a function of ID if VGS . 44. Determine the required value of W=L if ID = 0:5 mA. 2007 at 13:42 317 (1) Sec. 36.7 Chapter Summary 317 32. construct the small-signal model of each of the circuits shown in Fig.1 must provide a gm rO of 20 with VDS = 1:5 V. Assume VX goes from 0 to VDD = 1:8 V. 6.52.

where M1 and M2 operate in saturation and exhibit channel-length modulation coefﬁcients n and p . 2007 at 13:42 318 (1) 318 VDD RD Vout M2 VB V in M1 (a) Chap.60. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD .58. SPICE Problems In the following problems.57. 48. use the MOS models and source/drain dimensions given in Appendix A. For the circuit shown in Fig. (a) Construct the small-signal equivalent circuit and explain why M1 and M2 appear in “parallel. respectively. 6.59 for 0 Vin 1:8 V. At what value of Vin does the slope (gain) reach a maximum? 49. 47.6 V M1 (a) Figure 6. plot VX as a function of IX for 0 IX 3 mA.” (b) Determine the small-signal voltage gain of the circuit.3 V 0.cls v. For the arrangements shown in Fig.3 V 1V 0. 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.51 (b) (c) (d) 46. 6. 2006] June 30. respectively. plot ID as a function of VX as VX varies from 0 to 1.3 V M1 0. Explain the sharp change in VX as IX exceeds a certain value.50 M1 2V 2V M1 0. Plot the input/output characteristic of the stage shown in Fig. Consider the circuit depicted in Fig. Can we say these two arrangements are equivalent? . 6. 6 VDD RD Vout V in M2 (b) Physics of MOS Transistors VDD RD Vout V in M1 M2 (c) M1 VDD VDD V in M1 Vout M2 VB V in M2 (e) RD Vout M1 (d) Figure 6.8 V.

4 V Figure 6.8 V 1 kΩ M1 (a) (b) (c) Figure 6.8 V M1 IX VX (a) (b) VDD = 1.4 V 1V M1 0.8 V M1 500 Ω VDD = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.52 (c) (d) VDD = 1.9 V 0. 2007 at 13:42 319 (1) Sec.cls v.55 .8 V M1 VX IX 1V VDD = 1.5 V 0. 6.8 V M1 1 kΩ VDD = 1.9 (a) (b) M1 0.9 V 319 M1 0. 2006] June 30.5 V 0.53 VDD = 1.8 V M1 IX M1 VX IX VX (c) (d) Figure 6.7 Chapter Summary M1 1.9 V 0.8 V M1 1V 2 kΩ Figure 6.54 VDD = 1.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.56 VDD M2 V in M1 Vout Figure 6.8 V 500 Ω M1 V in 10 0.18 Vout Figure 6. 2007 at 13:42 320 (1) 320 Chap.57 M1 0.58 VDD = 1.59 .18 VX IX Figure 6.9 V 2 0. 2006] June 30.cls v. 6 Physics of MOS Transistors V in VDD RS V in M1 Vout RD V in VDD M1 Vout RD M2 Vb M1 Vout R1 M2 RD (c) (a) (b) VDD V in M1 Vout R1 RD M2 V in VDD R2 Vout M1 M2 R1 (d) (e) Figure 6.

9 V 5 0.36 5 0.60 .36 VX M2 (a) (b) Figure 6.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.9 V 5 0. 6.7 Chapter Summary IX M1 0. 2006] June 30. 2007 at 13:42 321 (1) Sec.36 321 IX M1 VX 0.

2007 at 13:42 322 (1) 322 Chap. Plot IX as a function of VX for the arrangement depicted in Fig. 2006] June 30. 6 Physics of MOS Transistors 50. 6.18 M1 5 0.18 VX Figure 6.9 V 5 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.18 VX Figure 6. VDD = 1. Can you explain the behavior of the circuit? IX M1 0. Repeat Problem 50 for the circuit illustrated in Fig.8 V.62 .8 V M1 5 0. 6.cls v.61 as VX varies from 0 to 1.62.18 IX M1 5 0.61 51.

e. General Concepts Biasing of MOS Stages Realization of Current Sources MOS Amplifiers Common−Source Stage Common−Gate Stage Source Follower 7. Section 5. 2007 at 13:42 323 (1) 7 CMOS Ampliﬁers Most CMOS ampliﬁers have identical bipolar counterparts and can therefore be analyzed in the same fashion. Consider the circuit shown in Fig. 2006] June 30.cls v. in most bias calculations. We assume the reader is familiar with concepts such as I/O impedances.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. MOS circuits may incorporate biasing techniques that are quite different from those described in Chapter 5 for bipolar stages. we have VX = R R2 R VDD : 1+ 2 (7. we can neglect channel-length modulation. We assume M1 operates in saturation. and dc and small-signal analysis. In other words. Also.1. The outline of the chapter is shown below. a voltage-controlled current source) suggests that the same must hold for MOS ampliﬁers.1. biasing.1) 323 .. Noting that the gate current is zero.2 Biasing Depending on the application.” 7.1. we expect three basic CMOS ampliﬁers: the “common-source” (CS) stage.3 that the nine possible circuit topologies using a bipolar transistor in fact reduce to three useful conﬁgurations. Nonetheless. It is recommended that the reader review Chapter 5. it is still instructive to apply some of the biasing concepts of Chapter 5 to MOS stages. and the “source follower. Most of these techniques are beyond the scope of this book and some methods are studied in Chapter 5. 7. speciﬁcally. Our study in this chapter parallels the developments in Chapter 5.1. The similarity of bipolar and MOS small-signal models (i.1 General Considerations 7.1 MOS Ampliﬁer Topologies Recall from Section 5. where the gate voltage is deﬁned by R1 and R2 . the “common-gate” (CG) stage. identifying both similarities and differences between CMOS and bipolar circuit topologies.

cls v.1 MOS stage with biasing. either by iteration or by ﬁnding ID from (7.2) Also. 2006] June 30.3) can be solved to obtain ID and VGS .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V 4 kΩ CMOS Ampliﬁers R1 Y RD ID X 10 k Ω M1 R2 RS 1 kΩ Figure 7. 2007 at 13:42 324 (1) 324 Chap. Since VX = VGS + ID RS . (7. VTH 2 : 2 L (7. 7 VDD = 1.2) and (7.3) Equations (7.2) and replacing for it in (7. R2 V = V + I R : R1 + R2 DD GS D S ID = 1 n Cox W VGS .3): .

R 1 1 W 2 2 R1 + R2 VDD . VGS RS = 2 n Cox L VGS . VTH : r s .

4) That is R 2 VGS = .9) .1 Solution We have VX = R R2 R VDD 1+ 2 = 1:286 V: (7. W=L = 5=0:18.2) to obtain ID . VTH + V1 . VTH + V12 + 2V1 R 2 +DD . and = 0. Of course. n Cox = 100 A=V2 . VTH + R 2+2R V1 VDD .1 assuming VTH = 0:5 V. VTH to ensure operation in the saturation region. 1 2 RV = . VTH .7) Example 7.V1 . 1 R2 where (7.5) (7.6) V1 = This value of VGS can then be substituted in (7. VTH 2 . (7.8) (7. What is the maximum allowable value of RD for M1 to remain in saturation? : n Cox W RS L 1 (7. VY must exceed VX . 7.V1 . Determine the bias current of M1 in Fig.

1 General Considerations 325 With an initial guess VGS = 1 V.15) . 2007 at 13:42 325 (1) Sec. That is. (7.1.14) This gives ID = 297 A. This is due to the quadratic (rather than exponential) ID -VGS dependence.6) to avoid lengthy calculations.12) (7.2 . Example 7. ID = VX R VGS S = 332 A. assume M1 is in saturation and RD = 2:5 k and compute (a) the maximum allowable value of W=L and (b) the minimum allowable value of RS (with W=L = 5=0:18). VY D = 3:25 k : = VX .13) VGS = 0:989 V: (7. yielding a drain current of 286 A. We may therefore utilize the exact result in (7. (7.11) Consequently.10) (7.18) (7. As seen from the iterations. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. Since V1 = 0:36 V. VGS = 0:974 V and (7.17) RD = VDDI . and hence (7. the solutions converge more slowly than those encountered in Chapter 5 for bipolar circuits. ID = VX R VGS S = 312 A: The maximum allowable value of RD is obtained if VY (7.cls v. VTH = 0:786 V.16) (7.19) Exercise What is the value of R2 that places M1 at the edge of saturation? In the circuit of Example 7. the voltage drop across RS can be expressed as VX .3) gives the new value of VGS as v u VGS = VTH + u t = 0:954 V: n Cox W L 2ID (7. VGS = 286 mV. Assume = 0. . Substituting for ID in Eq.

n Cox W L 2ID (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.25) (7. VTH 2 .23) A. 2006] June 30.21) ID = VDD .22) (7. M1 can carry a larger current for a given VGS .24) v u VGS = VTH + u t = 1:041 V.22 can also be applied to MOS ampliﬁers.3). VY RD = 406 A: The voltage drop across RS is then equal to 406 mV. the maximum allowable value of ID is given by Solution = 2:5 k (7. RS + RD ID .2.30) .27) (7. M1 must carry a current of 406 A with VGS = 0:88 V: 1 ID = 2 n Cox W VGS . 0:406 V = 0:88 V. we have (7. Since (b) With W=L = 5=0:18. 5. VGS = 245 mV. L (7. Thus. the circuit can be analyzed by noting that M1 is in saturation (why?) and the voltage drop across RG is zero. the minimum allowable value of RS gives a drain current of 406 W = 56:2: L (7. 7 CMOS Ampliﬁers (a) As W=L becomes larger.28) Exercise Repeat the above example if VTH = 0:35 V. yielding VGS = 1:286 V . With RD and VX = 1:286 V. ID RD + VGS + RS ID = VDD : Finding VGS from this equation and substituting it in (7.26) the voltage drop across RS is equal to VX . The self-biasing technique of Fig. 7. (7. L thus. VGS I = 604 : D (7. It follows that RS = VX . Depicted in Fig. In other words.29) 1 ID = 2 n Cox W VDD .20) (7. VTH 2 L 406 A = 50 A=V2 W 0:38 V2 . 2007 at 13:42 326 (1) 326 Chap.

VTH RS + RD + 4 1 n Cox L 3 7 2 W 5 ID + VDD .32) RD = 2:867 k : (7.2 V. W 5 M 1 L = 0.18 200 Ω Figure 7. 7. 7.31) Calculate the drain current of M1 in Fig. we solve (7.2 Self-biased MOS stage.3 Example of self-biased MOS stage.cls v.33) Exercise Repeat the above example if VDD drops to 1. 2 6VDD . Solution Equation (7. and = 0.3 if n Cox = 100 A=V2 . 2006] June 30. VTH What value of RD is necessary to reduce ID by a factor of two? VDD = 1.31) for RD : (7.8 V RD 20 k Ω 1 kΩ Example 7.1 General Considerations VDD RD RG ID M1 RS 327 Figure 7. .31) gives ID = 556 A: To reduce ID to 278 A. It follows that 2 2 RS + RD 2 ID .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. where channel-length modulation is neglected.3 = 0:5 V. 2007 at 13:42 327 (1) Sec. VTH = 0: (7.

gm v1 RD .34) .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. NMOS or PMOS devices conﬁgured as shown in Figs.4 (a) NMOS device operating as a current source. M1 converts the input voltage variations to proportional drain current changes.2.2 Common-Source Stage 7. (7. and RD transforms the drain currents to the output voltage.1.4(c) and (d) do not operate as current sources because variation of VX or VY directly changes the gate-source voltage of each transistor. 2006] June 30. For small signals. it draws current from node X to ground.. with the input applied to the gate and the output sensed at the drain. If = 0. VDD X Vb M1 Y Y X Vb M2 VDD Vb Y Vb M1 X VDD M1 (a) (b) (c) (d) Figure 7.g R . As illustrated in Fig. 6. the basic CS stage is similar to the common-emitter topology. an NMOS device serves as a current source with one terminal tied to ground. m D vin a result similar to that obtained for the common emitter stage in Chapter 5.34. the small-signal model in Fig. (d) NMOS topology not operating as a current source. Speciﬁcally. i. (c) PMOS topology not operating as a current source. (b) PMOS device operating as a current source. It is important to understand that only the drain terminal of a MOSFET can draw a dc current and still present a high impedance. 2007 at 13:42 328 (1) 328 Chap. the small-signal model of these two structures is identical to that of the diode-connected devices in Fig. From another perspective. 7. On the other hand.5(b) yields vin = v1 and vout = . That is. vout = . 7 CMOS Ampliﬁers 7. If channel-length modulation is neglected. thus changing the drain current considerably.5(a). (b) small-signal mode.e.4(a). a PMOS transistor [Fig. these currents remain independent of VX or VY (so long as the transistors are in saturation).3 Realization of Current Sources MOS transistors operating in saturation can act as current sources.4(b)] draws current from VDD to node Y . 7. revealing a small-signal impedance of only 1=gm (if = 0) rather than inﬁnity. 7. VDD RD ID V in Input Applied to Gate (a) (b) v in Vout M1 Output Sensed at Drain v out v1 g v1 m RD Figure 7. 7. 7.1 CS Core Shown in Fig.5 (a) Common-source stage. 7.cls v.

r (7.cls v. (7.6 if ID = 1 mA. VTH . 2007 at 13:42 329 (1) Sec. we the CS stage is also limited by the supply voltage. RD ID VGS .42) (7.6 Example of CS stage.37) Calculate the small-signal voltage gain of the CS stage shown in Fig.35) concluding that if ID or RD is increased.4 (7. VTH : Example 7. This concept is beyond the scope of this book.38) (7. 2n Cox W ID RD .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.gmRD = 3:33: To check the operation region.36) RD ID VDD .8 V RD 1 kΩ = v out v in 10 M1 W = L 0.40) (7. VGS . we ﬁrst determine the gate-source voltage: (7. . Solution We have gm = 2nCox W ID L 1 = 300 : Thus. 2006] June 30.18 Figure 7. VDD = 1.41) v u VGS = VTH + u t = 1:1 V: n Cox W L 2ID (7. that is.2 Common-Source Stage 329 of p2TheCvoltage gain.39) Av = . 7. and = 0. Verify that M1 operates in saturation. but “subthreshold conduction” eventually limits the transconductance. n Cox 100 A=V2 .43) 1 It is possible to raise the gain to some extent by increasing W . VDD . L (7. VTH = 0:5 V. so is the voltage drop across RD (= ID RD ). 7. Since gm n ox W=LID have r = Av = .1 For M1 to remain in saturation.

46) (7. The small-signal model of CS topology is therefore modiﬁed as shown in Fig. 2006] June 30. v1 g v1 m (7. For example. . then M1 enters the triode region and its transconductance drops. if RD is doubled with the intention of doubling Av . In practice. Since VGS .8.44) a point of contrast to the CE stage (whose Rin is equal to r ).7. The similarity between the small-signal equivalents of CE and CS stages indicates that the output impedance of the CS ampliﬁer is simply equal to Rout = RD : This is also seen from Fig. Av = .45) iX RD vX Figure 7. 2007 at 13:42 330 (1) 330 Chap. 7 CMOS Ampliﬁers The drain voltage is equal to VDD . in a similar manner.gmRD jjrO Rin = 1 Rout = RD jjrO : (7.7 Output impedance of CS stage. (7. channel-length modulation may not be negligible. RD ID = 0:8 V. especially if RD is large. we say the CS ampliﬁer provides a current gain of inﬁnity. The high input impedance of the CS topology plays a critical role in many analog circuits. revealing that iX v1 g v1 m rO RD vX Figure 7. 7. Since the gate current is zero (at low frequencies).8 Effect of channel-length modulation on CS stage. Let us now compute the I/O impedances of the CS ampliﬁer. VTH = 0:6 V. By contrast.48) In other words. Exercise What value of VTH places M1 at the edge of saturation? Since the gate terminal of MOSFETs draws a zero current (at very low frequencies). 7. the current gain of a commonemitter stage is equal to . Rin = 1.cls v. channel-length modulation and the Early effect impact the CS and CE stages. the device indeed operates in saturation and has a margin of 0.2 V with respect to the triode region.47) (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. respectively.

50) This result may imply that jAv j falls as L increases. Let us determine the small-signal gain and output impedance of the circuit. 7. VDD Av Example 7.10(a)].5 v out v in M1 L (a) (b) Figure 7. Exercise Repeat the above example if a resistor of value M1 . 7. 2006] June 30. but recall from Chapter 6 that r 2 C WL n ox jAv j ID : L. jAv j increases with L [Fig. 2007 at 13:42 331 (1) Sec. (b) gain as a function of device channel length.1 r 2n Cox W can provide. 7.51) Consequently. we single transistor have n Cox D O ID .2 CS stage With Current-Source Load As seen in the above example. allowing the use of (7. Having a constant gate-source voltage. 7.1 : (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.9(b)]. 7. M2 simply behaves as a resistor equal to its output impedance [Fig. Writing (7.9 (a) CS stage with ideal current source as a load.10(b)] .4(b) therefore suggest the use of a PMOS device as the load of an NMOS CS ampliﬁer [Fig.2. the trade-off between the voltage gain and the voltage headroom can be relaxed by replacing the load resistor with a current source. 7. The observations made in relation to Fig. Solution The ideal current source presents an inﬁnite small-signal resistance.9(a) and plot the result as a function of the transistor channel length while other parameters remain constant.2 Common-Source Stage 331 Assuming M1 operates in saturation. R1 is tied between the gate and drain of 7. determine the voltage gain of the circuit depicted in Fig.46) with RD = 1: Av = .cls v.gmrO : This highest voltage a p2 is theW=LI and r = gain that.49) gm = jAv j = pI L : D (7.

producing vout = . 7. M2 acts as a small-signal resistance equal to 1=gm2 .gm1rO1 jjrO2 Rout = rO1 jjrO2 : Example 7.3 CS stage With Diode-Connected Load In some applications.10 (a) CS stage using a PMOS device as a current source. because v1 = 0 and hence gm2 v1 = 0. Thus.cls v. (b) small-signal model.1.3). Transistor M2 generates a small-signal current equal to gm2 vin .2.54) Exercise Calculate the gain if the circuit drives a loads resistance equal to RL .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. such a topology exhibits only a moderate gain due to the relatively low impedance of the diode-connected device (Section 7. Equations (7.52) (7. 7. which then ﬂows through rO1 jjrO2 .48) give Av = . we may use a diode-connected MOSFET as the drain load. 7 CMOS Ampliﬁers v1 gm2v 1 r O2 v out v in M1 (b) r O1 (a) Figure 7.6 (7. 2007 at 13:42 332 (1) 332 VDD Vb M2 v out v in M1 VDD Chap. the drain node of M1 sees both rO1 and rO2 to ac ground. Compute the voltage gain of the circuit.gm2 rO1 jjrO2 : (7. Thus.46) and (7. Illustrated in Fig. VDD v in M2 v out Vb M1 Figure 7. Solution Av = .12(a). With = 0.gm2 vin rO1 jjrO2 . 2006] June 30. and (7.11 shows a PMOS CS stage using an NMOS current source load.11 CS stage using an NMOS device as current source.53) Figure 7.34) yields .

Av = .57) Interestingly.2 Common-Source Stage VDD M2 Vout V in M1 V in Q1 (b) 333 VCC Q2 Vout v in M1 (c) 1 g m2 r O2 v out r O1 (a) Figure 7. the gain is given by the dimensions of M1 and M2 and remains independent of process parameters n and Cox and the drain current. As depicted in Fig.58) (7. 2007 at 13:42 333 (1) Sec. 7.12(b).12(c).gm1 . 7. Shown in Fig.gm1 g 1 m p2 C 2 W=L I 1 D = . ID .59) (7.gm1 g 1 m2 IC 1 1 = .60) arises from a fundamental difference between MOS and bipolar devices: transconductance of the former depends on device dimensions whereas that of the latter does not.12 (a) MOS stage using a diode-connected load. and hence Av = . the resistance seen at the drain is now equal to 1=gm2 jjrO2 jjrO1 .1: (7. A more accurate expression for the gain of the stage in Fig. V I =V T C2 T .55) (7. The reader may wonder why we did not consider a common-emitter stage with a diodeconnected load in Chapter 5.60) The contrast between (7.cls v.56) = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. W=L1 : W=L2 s (7. 7.57) and (7. 7. p n ox 2n Cox W=L2 ID (7. (c) simpliﬁed circuit of (a). such a circuit is not used because it provides a voltage gain of only unity: Av = .12(a) must take channel-length modulation into account. (b) bipolar counterpart. 2006] June 30.

13(a) if 6= 0.62) Example 7. 7. 1 g jjrO2 jjrO1 : m2 (7.7 . the output resistance of the stage is given by Rout = g 1 jjrO2 jjrO1 : m2 Determine the voltage gain of the circuit shown in Fig. (7.61) Similarly.

Thus.12(a). 2006] June 30.13 CS stage with diode-connected PMOS device.gm2 .cls v. Av = . 7 CMOS Ampliﬁers Figure 7. but with NMOS devices changed to PMOS transistors: M1 serves as a common-source device and M2 as a diode-connected load.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7. 2007 at 13:42 334 (1) 334 VDD V in M2 Vout M1 Chap. Solution This stage is similar to that in Fig.

the degeneration resistor sustains a fraction of the input voltage change. and linearity.14 (a) CS stage with degeneration.2.14 depicts the stage along with its small-signal equivalent (if = 0). vin = v1 + gmv1 RS and hence (7. (b) small-signal model.63) Exercise Repeat the above example if the gate of M1 is tied to a constant voltage equal to 0.14(b). I/O impedances. we have VDD RD Vout V in M1 RS RS v in v1 g v1 m v out RD (a) (b) Figure 7.5 V.65) . Figure 7. 7.4 CS Stage With Degeneration Recall from Chapter 5 that a resistor placed in series with the emitter of a bipolar transistor alters characteristics such as gain. 1 jjr jjr : O1 O2 g m1 (7. From Fig.64) v1 = 1 +vgin R : m S (7. As with the bipolar counterpart. 7. We expect similar results for a degenerated CS ampliﬁer.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.15 (a) Example of CS stage with degeneration.2 Common-Source Stage 335 Since gm v1 ﬂows through RD . 2007 at 13:42 335 (1) Sec.cls v. VDD RD Vout V in M1 M2 v in 1 g m2 (b) (7. we may study the effect of a resistor appearing in series with the gate (Fig. gmRD vin 1 + gm RS = . Adding the voltage drops across rO and RS and equating the result to vX .67) Example 7. presenting an impedance of 7. Figure 7. RG sustains no voltage drop and does not affect the voltage gain or the I/O impedances.15(a) if = 0. The gain is therefore given by (7.iX RS = iX + gm iX RS .8 RD v out M1 (a) Figure 7. Av = . Also. Transistor M2 serves as a diode-connected device.66) (7.67) if RS is replaced with 1=gm2 : Solution 1=gm2 [Fig.iX RS .17 shows the small-signal equivalent of the circuit. 1 RD . Effect of Transistor Output Impedance As with the bipolar counterparts. (b) simpliﬁed circuit.gmv1 RD and vout = .157) for the bipolar counterpart. Since RS carries a current equal to iX (why?).16). 7. the current through rO is equal to iX . 2006] June 30. 7.15(b)]. we have . gm . we have v1 = . 7. However. since the gate current is zero (at low frequencies). the inclusion of the transistor output impedance complicates the analysis and is studied in Problem 31. 1 RD 1 : gm1 + gm2 (7. vout = . Compute the voltage gain of the circuit shown in Fig. gm + RS a result identical to that expressed by (5. Nonetheless. gm v1 = iX . the output impedance of the degenerated CS stage plays a critical role in analog design and is worth studying here.68) Exercise What happens if 6= 0 for M2 ? In parallel with the developments in Chapter 5.

197) yields the same results as above. iX v1 RS g v1 m rO vX Figure 7. 7. 7 CMOS Ampliﬁers VDD RD RG M1 RS Vout V in Figure 7.72) Alternatively. and hence (7. 2007 at 13:42 336 (1) 336 Chap.69) vX = r 1 + g R + R m S S iX O = 1 + gm rO RS + rO gm rO RS + rO : (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. 7. 5.17 is similar to its bipolar counterpart in Fig. As expected from our study of the bipolar degenerated stage.9 Vb M1 M2 (a) M1 r O1 1 r g m2 O2 (b) Figure 7.70) (7.17 Output impedance of CS stage with degeneration. Solution The diode-connected device M2 can be represented by a small-signal resistance of . the MOS version also exhibits a “boosted” output impedance.cls v. Compute the output resistance of the circuit in Fig. (b) simpliﬁed circuit.18(a) if M1 and M2 are identical. Letting r ! 1 in Eqs.46(a) but with r = 1.71) (7.196) and (5. (5. rO iX + gm iX RS + iX RS = vX .18 (a) Example of CS stage with degeneration. we observe that the model in Fig. R out R out Example 7.16 CS stage with gate resistance.

7. Transistor M1 is degenerated by this resistance.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and from (7. 2006] June 30.cls v.70): Rout = rO1 1 + gm1 g which. since gm1 . 2007 at 13:42 337 (1) Sec.2 Common-Source Stage 337 1=gm2jjrO2 1=gm2.

73) = gm2 = gm. m2 1 + g1 m2 (7.19(a) and compare the result with that in the above example. R out R out V b2 V b1 M1 M2 (a) M1 r O1 r O2 (b) Figure 7. introducing a resistance of rO2 from the source of M1 to ground [Fig.76) (7.78) .75). 7.71) can therefore be written as Solution Rout = 1 + gm1 rO1 rO2 + rO1 gm1rO1 rO2 + rO1 : Assuming gm1 rO2 (7. 7. transistor M2 operates as a current source. reduces to Rout = 2rO1 + g1 m 2rO1 : (7. we have Rout gm1 rO1 rO2 : We observe that this value is quite higher than that in (7. Equation (7. (b) simpliﬁed circuit.10 Determine the output resistance of the circuit in Fig. With its gate-source voltage ﬁxed.77) 1 (which is valid in practice).19 (a) Example of CS stage with degeneration.19(b)].75) Exercise Do the results remain unchanged if vice? M2 is replaced with a diode-connected PMOS de- Example 7. Assume M1 and M2 are in saturation. (7.74) (7.

and VDD = 1:8 V. an input impedance of 50 k . 2006] June 30.11 (7.20(b)].1 is similar to that analyzed for the bipolar stage in Chapter 5.20(c)]. Depicted in Fig. VTH = 0:5 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (c) use of bypass capacitor. and a power budget of 5 mW. 7 CMOS Ampliﬁers Exercise Repeat the above example for the PMOS counterpart of the circuit. 7. 7.80) where is assumed to be zero.RD . 7.82) Design the CS stage of Fig.cls v.20(a) along with an input coupling capacitor (assumed a short circuit). Rin = R1 jjR2 : Av = R R1 jjR2 R 1. 7. it is possible to utilize degeneration for bias point stability but eliminate its effect on the small-signal performance by means of a bypass capacitor [Fig. = 0. 7. but raises the voltage gain: (7.81) Av = . Assume n Cox = 100 A=V2 .20 (a) CS stage with input coupling capacitor.20(c) for a voltage gain of 5. such a circuit no longer exhibits an inﬁnite input impedance: VDD R1 C1 V in R2 M1 RS RD Vout V in R1 RG C1 M1 R2 RS VDD RD Vout V in R1 RG C1 M1 R in R2 RS C2 VDD RD Vout (a) (b) (c) Figure 7. Also. if the circuit is driven by a ﬁnite source impedance [Fig. 7. . Unlike the case of bipolar realization. G + R1 jj 2 gm + RS (7. (b) inclusion of gate resistance.79) Thus. As mentioned in Chapter 5. assume a voltage drop of 400 mV across RS . the voltage gain falls to (7.5 CS Core With Biasing The effect of the simple biasing network shown in Fig. this does not alter the input impedance of the CS stage: Rin = R1 jjR2 .2. R R1 jjR2 R gmRD : G + R1 jj 2 Example 7. 2007 at 13:42 338 (1) 338 Chap.

which. As an initial guess. This choice yields (7.DV GS TH = 92:1 . yields. we allocate 2. even though VGS is reasonable. we have chosen an excessively large RD .85) RD = 463 : Writing (7. requiring that R2 (7. ID RD = 1:8 V . 2006] June 30.cls v. 6 and hence (7. driving M1 into the triode region! How did our design procedure lead to this result? For the given ID .92) (7. an excessively small gm (because gm RD = 5). The drain voltage is given by VDD . 2007 at 13:42 339 (1) Sec. the choice of gm and RD is somewhat ﬂexible so long as gm RD = 5.2 Common-Source Stage 339 The power budget along with VDD = 1:8 V implies a maximum supply current of 2.88) L With VGS = 1 V and a 400-mV drop across RS . VGS = 1 I gm = V 2.84) (7.89) R1 + R2 VDD = 1:4 V.7 mA to M1 and the remaining 80 A to R1 and R2 . We must therefore increase gm so as to allow a lower value for RD . e.78 mA. i. the gate voltage reaches 1..g. 1:25 V = 0:55 V. we must ensure a reasonable value for VGS .e. However.93) . For example. VTH 2 2 L gives (7.91) We must now check to verify that M1 indeed operates in saturation. with ID known. 7.4 V.4 V. suppose we halve RD and double gm by increasing W=L by a factor of four: W = 864 L gm = 46:1 : 3 (7. along with Rin = R1 jjR2 = 50 k .83) As with typical design problems.86) ID = 1 n Cox W VGS . Since the gate voltage is equal to 1..87) W = 216: (7. It follows that Solution RS = 148 : V. R1 = 64:3 k R2 = 225 k : (7.90) (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the gate-drain voltage difference exceeds VTH .

VDD . a value higher Exercise Repeat the above example for a power budget of 3 mW and VDD = 1:2 V. then the gate-source voltage of M1 decreases by the same amount. and VDD = 1:8 V. Is M1 in saturation? The drain voltage is equal to VDD . Neglect channel-length modulation.21 Common-gate stage. 2006] June 30. the CG topology resembles the common-base stage studied in Chapter 5. 7. the voltage gain is positive and equal to VDD RD Vout V in Input Applied to Source M1 Vb Output Sensed at Drain Figure 7. determine the maximum allowable value of RD and hence the maximum voltage gain. VTH to ensure M1 is saturated. (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.94) = 1:17 V. a high ID or RD is necessary. With W=L known. must remain above Vb .cls v. M1 operates in saturation. yielding a gate voltage of 650 mV. 7. V . but the drain voltage. the gate-source voltage can be determined from Example 7.84): VGS = 250 mV.96) .3 Common-Gate Stage Shown in Fig. Av = gmRD : (7. RD ID than the gate voltage minus VTH . to achieve a high gain. In particular. ID RD . A microphone having a dc level of zero drives a CG stage biased at ID = 0:5 mA. If W=L = 50.95) The CG stage suffers from voltage headroom-gain trade-offs similar to those of the CB topology. 2007 at 13:42 340 (1) 340 Chap. n Cox = 100 A=V2 . 7 CMOS Ampliﬁers The corresponding gate-source voltage is obtained from (7.12 Solution 1 ID = 2 n Cox W VGS . That is.21. Here. Thus. thereby lowering the drain current by gm V and raising Vout by gm V RD . VTH = 0:5 V. if the input rises by a small value. VTH 2 L (7.

22 Signal levels in CG stage. VDD RD Vb − V TH = 0.1 and (7. (7. ID RD Vb .947 V V in Figure 7.vX and iX v1 iX g v1 m RD v1 g v1 m RD vX vX (a) (b) Figure 7.cls v.98) RD 2:71 k : Also.20(a).3 Common-Gate Stage 341 as VGS = 0:947 V: For M1 to remain in saturation. 2006] June 30. The gate voltage can be generated using a resistive divider similar to that in Fig. 2007 at 13:42 341 (1) Sec. the above value of W=L and ID yield gm (7.97) VDD . 7.447 V M1 0 Vout Vb = 0.22 summarizes the allowable signal levels in this design.23 (a) Input and (b) output impedances of CG stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.102) .100) Av 6:06: Figure 7. we have from Fig.gmv1 = gmvX : (7.101) (7. 7. Neglecting channel-length modulation for now.99) = 447 . expecting to obtain results similar to those of the CB topology. what value should be chosen for W=L? We now compute the I/O impedances of the CG stage. iX = . Exercise If a gain of 10 is required.23(a) v1 = . VTH and hence (7. 7.

In contrast to the common-source stage.107) (7. The analysis of the common-gate stage in the general case.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.24) but still with = 0. 7.. 2006] June 30. vX = 1 gm vin gm + RS 1 = 1 + g R vin : m S Thus.23(b). including both channel-length modulation and a ﬁnite source impedance is beyond the scope of this book (Problem 41). 1 (7.104) Rout = RD .cls v.25(a)] does not alter the gain or I/O impedances (at low frequencies) because it sustains . m a relatively low value. Let us study the behavior of the CG stage in the presence of a ﬁnite source impedance (Fig.106) vout = vout vX vin vX vin g = 1 +mgRD m RS = 1 RD : gm + RS (7.108) (7. 7 CMOS Ampliﬁers That is.109) The gain is therefore equal to that of the degenerated CS stage except for a negative sign.103) = 0 and hence (7. an expected result because the circuits of Figs.7 are identical.105) (7.23(b) and 7. In a manner similar to that depicted in Chapter 5 for the CB topology. a resistance appearing in series with the gate terminal [Fig. Rin = g1 . 7. v1 (7.e. 7. from Fig. 2007 at 13:42 342 (1) 342 Chap. we can make two observations. we write VDD RD Vout RS v in M1 X 1 gm Vb v in RS vX 1 gm Figure 7.24 Simpliﬁcation of CG stage with signal source resistance. 7. However. the CG ampliﬁer exhibits a current gain of unity: the current provided by the input voltage source simply ﬂows through the channel and emerges from the drain node. Also. First. i.

We ﬁrst compute vX =vin with the aid of the equivalent circuit depicted in Fig. 7. 2006] June 30.13 (7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.110) For the circuit shown in Fig.26 (a) Example of CG stage.111) = 1 + g 1 g R : m1 + m2 S (7.25 (a) CG stage with gate resistance. we have vout = gm1 RD vin 1 + gm1 + gm2 RS : (7.cls v. 7.3 Common-Gate Stage VDD RD Vout M1 v in RG Vb RS rO M1 R out 343 (a) (b) Figure 7.25(b)] is identical to that of the degenerated CS topology: Rout = 1 + gm rO RS + rO : Example 7. VDD RD Vout RS M 1 V in X M2 Vb v in RS 1 g m1 R out1 RS r O1 M1 1 r g m2 O2 (c) vX 1 g m2 (b) (a) Figure 7.113) . calculate the voltage gain if = 0 and the output impedance if 0. (c) calculation of output resistance.112) = gm1 RD . 2007 at 13:42 343 (1) Sec. (b) output resistance of CG stage. the output resistance of the CG stage in the general case [Fig. Second.26(a). 7. (b) equivalent input network. 7.26(b): Solution vX = gm2 jj gm1 1 1 vin gm2 jj gm1 + RS Noting that vout =vX 1 1 (7. a zero potential drop—as if its value were zero.

116) (7.119) where channel-length modulation is neglected.1 CG Stage With Biasing Following our study of the CB biasing in Chapter 5. Providing a path for the bias current to ground. 7. VDD RD Vout RS C1 M1 X R3 R1 V in R2 Figure 7.117) Exercise Calculate the output impedance if the gate of M2 is tied to a constant voltage.14 = 5. we have vout = vX vout vin vin vX R3 = R jj1jj1=gm R gm RD .27 CG stage with biasing. . As mentioned earlier. which from (7. resistor R3 lowers the input impedance—and hence the voltage gain—if the signal source exhibits a ﬁnite output impedance. as shown in Fig. 2006] June 30. Since the impedance seen to the right of node X is equal to R3 jj1=gm .26(c). =gm + S 3 (7.114) (7.27 for the following parameters: vout =vin Example 7. we ﬁrst consider Rout1 .115) The overall output impedance is then given by Rout = Rout1 jjRD gm1 rO1 g 1 jjRS + rO1 jjRD : m2 (7. Design the common-gate stage of Fig.118) (7. we surmise the CG ampliﬁer can be biased as shown in Fig. RS .cls v. 7.3.27. 2007 at 13:42 344 (1) 344 Chap. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the voltage divider consisting of R1 and R2 does not affect the small-signal behavior of the circuit (at low frequencies). 7 CMOS Ampliﬁers To compute the output impedance.110) is equal to Rout1 = 1 + gm1rO1 g 1 jjrO2 jjRS + rO1 gm1 rO1 g 1 jjRS + rO1 : m2 m2 (7. 7.

ID RD = 1:05 V. Since the drain voltage exceeds VG . the drain voltage is given by VDD . VDD = 1:8 V. we must ﬁrst compute the maximum allowable VGS . we obtain a total supply current of 1. what voltage gain can be achieved? Suppose in Example 7. VTH VGS . What is the minimum acceptable value of W=L? For a given ID .11 mA. as W=L decreases. allowing a lower value of RD .1 . VTH = 136:4 .121) = 45 k and R2 = 135 k .11. Exercise If W=L cannot exceed 100. VTH . R3 = 500 . then W=L = 244. The resistive divider consisting of R1 and R2 must establish a gate voltage equal to 1. Thus.122) VGS .1 mA for the drain current of M1 . and = 0. VTH increases. VGS .3 Common-Gate Stage 345 RS = 0.124) . From the power budget. power budget = 2 mW. Allocating 10 A to the voltage divider.120) (7.14. 1=gm = 50 .cls v. For example. where VR3 denotes the voltage drop across R3 . The gate voltage is equal to VGS plus the drop across R3 .123) gives: 2ID (7. VTH + VR3 2 (7. Av VGS . amounting to 1. dictating RD = 682 for vout =vin = 5. and set gm RD to the required gain: (7. Thus.15 Solution VDD . We must now compute two interrelated parameters: W=L and RD . and gm = 2ID =VGS . 2006] June 30. 2007 at 13:42 345 (1) Sec.35 V while drawing 10 A: Solution VDD = 10 A R1 + R2 R2 V = 1:35 V: R1 + R2 DD It follows that R1 (7. We impose the condition for saturation as Example 7. On the other hand. M1 is indeed in saturation. ID RD VGS + VR3 . we choose an initial value for VGS to arrive at a reasonable guess for W=L. the voltage drop across R3 is equal to 550 mV. VTH . VTH = 0:5 V.35 V. A larger value of W=L yields a greater gm . R1 and R2 . As in Example 7. we wish to minimize W=L (and hence transistor capacitances).123) VDD . Assume n Cox = 100 A=V2 . if VGS = 0:8 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we leave 1. 7. VTH RD = Av : Eliminating RD from (7.122) and (7. Let us determine whether M1 operates in saturation.

2007 at 13:42 346 (1) 346 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VTH In other words. VR3 : Av + 1 2 (7.125) W=L It follows that 2 .cls v. 2006] June 30. 7 CMOS Ampliﬁers and hence VGS . VDD .

128) .28 is raised by a small amount.28.29(a) depicts the small-signal equivalent of the source follower. From our analysis of emitter followers in Chapter 5. Since the dc level of Vout is lower than that of Vin by VGS . thereby raising the source current and hence the output voltage. 7. including channellength modulation.126) Av + 2 W=L 172:5: (7. V 2 : n Cox 2 DD R3 (7. we expect this topology to exhibit a subunity gain. we have gmv1 rO jjRL = vout : (7. Vout “follows” Vin . we say the follower can serve as a “level shift” circuit.4. Thus. The ampliﬁer senses the input at the gate and produces the output at the source. too.1 Source Follower Core If the gate voltage of M1 in Fig.4 Source Follower The MOS counterpart of the emitter follower is called the “source follower” (or the “commondrain” stage) and shown in Fig. with the drain tied to VDD . VDD V in Input Applied to Gate M1 Vout RL Output Sensed at Source Figure 7. the gate-source voltage tends to increase.127) Exercise Repeat the above example for Av = 10.28 Source follower. The circuit’s behavior is similar to that of the bipolar counterpart. VID . Vin . Figure 7. 7. 7. Recognizing that rO appears in parallel with RL . 7.

we can view the above result as voltage division between a resistance equal to 1=gm and another equal to rO jjRL [Fig.4 Source Follower 1 gm 347 v in v1 g v1 m rO v in v out RL r O v out RL (a) (b) Figure 7. 7. 2006] June 30. VDD V in M1 Vout Vb M2 (a) (b) M2 serves as a current source. It is desirable to maximize RL (and Example 7.30(a). however. V in M1 r O1 Vout r O2 Figure 7.132) . rO ).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The voltage gain is therefore positive and less than unity. Since M2 simply presents an impedance of rO2 from the output node to ac ground [Fig. 2007 at 13:42 347 (1) Sec.131) (at low frequencies) because it sustains a zero drop.cls v. 7.30 (a) Follower with ideal current source. that a resistance placed in series with the gate does not affect (7. (b) simpliﬁed circuit.129) vout = gm rO jjRL vin 1 + gmrO jjRL = 1 rO jjRL : g + rO jjRL m (7. Also.29(b)]. we substitute RL = rO2 in Eq.131) As with emitter followers. 7. vin = v1 + vout : It follows that (7. where Calculate the voltage gain of the circuit. (7.130) (7. Note.29 (a) Small-signal equivalent of source follower.16 A source follower is realized as shown in Fig. 7.30(b)]. (b) simpliﬁed circuit.131): Solution Av = 1 rO1 jjrO2 : gm1 + rO1 jjrO2 (7.

137) In summary. the source follower exhibits a very high input impedance and a relatively low output impedance.56 mA. 2 The input impedance is inﬁnite at low frequencies.136) (7. 7.135) Exercise What voltage gain can be achieved if the power budget is raised to 15 mW? It is instructive to compute the output impedance of the source follower. VTH = 0:5 V. the former is equal to 1=gm jjrO . then Av 1. Assume n Cox = 100 A=V2 . Using this value for ID in gm = 2n Cox W=LID gives p W=L = 360: (7. = 0. 2007 at 13:42 348 (1) 348 Chap.5 and a power budget of 10 mW. thereby providing buffering capability.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.load with a voltage gain of 0. we have Av = 1 RL gm + RL and hence (7. 7.28. RS is placed in series with the source of Example 7. 7 CMOS Ampliﬁers If rO1 jjrO2 1=gm1.2 As illustrated in Fig. Rout consists of the resistance seen looking up into the source in parallel with that seen looking down into RL . yielding Rout = g1 jjrO jjRL g1 jjRL : m m (7.17 Design a source follower to drive a 50.31. With 6= 0. With RL Solution = 50 and rO = 1 in Fig.134) The power budget and supply voltage yield a maximum supply current of 5.cls v.133) gm = 501 : (7. . and VDD = 1:8 V. Exercise Repeat the above example if a resistance of value M2 . 2006] June 30.

31 Output resistance of source follower. formed: Solution W=L. 2006] June 30. The following three equations can be (7. 7.138) 1 ID = 2 n Cox W VGS .141) (7. Assume n Cox = 100 A=V2 . VDD = 1:8 V.32 for a drain current of 1 mA and a voltage gain of 0. VTH 2 2 L ID RS + VGS = VDD . 7. Let us compute the bias current of the circuit. I R . we have VGS + ID RS = VDD : Neglecting channel-length modulation.2 Source Follower With Biasing The biasing of source followers is similar to that of emitter followers (Chapter 5). VTH = 0:5 V.142) ID = 1 n Cox W VGS . VDD C1 V in RG M1 RS C2 Vout Figure 7.139) (7.cls v.8. = 0. Note that M1 operates in saturation because the gate and drain voltages are equal. With a zero voltage drop across RG .32 Source follower with input and output coupling capacitors.4. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we write (7. V 2 : = 2 n ox L DD D S TH The resulting quadratic equation can be solved to obtain ID . The unknowns in this problem are VGS .18 (7. and RS .4 Source Follower 349 M1 RL rO M1 rO 1 gm rO R out RL Figure 7. VTH 2 L 1 C W V .140) Design the source follower of Fig. Also.32 depicts an example where RG establishes a dc voltage equal to VDD at the gate of M1 (why?) and RS sets the drain bias current. 2007 at 13:42 349 (1) Sec. and RG = 50 k . the input impedance of the circuit has dropped from inﬁnity to RG . Example 7. Figure 7.

142).147) (7. 7. the common-source stage. the small-signal behavior of these circuits is quite similar to that of their bipolar counterparts. VID RS 2I R GS TH + D S 2ID RS = V . and the source follower.149) (7. we have studied three basic CMOS building blocks.146) A RS = VDD I. VTH .V +I R : DD TH D S Thus. VTH 2 . We have noted that the biasing .33).140) reveals that the bias current of the source follower varies with the supply voltage. With the aid of (7. then (7. ID RS A = VDD . 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (7. namely. As observed throughout the chapter. To avoid this effect.143) do not contain W=L and can be solved to determine VGS and RS . VDD .143) If gm is written as 2ID =VGS . with the exception of the high impedance seen at the gate terminal. 7 CMOS Ampliﬁers Av = 1 RS : gm + RS RS Av = VGS .141) that (7.144) (7. VTH 2ID + RS 2 = V . integrated circuits bias the follower by means of a current source (Fig. 2006] June 30.148) VGS = VDD .152) Exercise What voltage gain can be achieved if W=L cannot exceed 50? Equation (7. VTH 2 . we write (7.142) and (7.150) (7.151) W = 107: L (7. vA D v = 867 : and (7. the common-gate stage.143) as (7.145) (7.5 Summary and Additional Examples In this chapter.cls v. v Av = 0:933 V: It follows from (7. 2007 at 13:42 350 (1) 350 Chap.

Thus.34(a). We identify M1 as a common-source device because it senses the input at its gate and generates the output at its drain. schemes are also similar. 2007 at 13:42 351 (1) Sec. yielding Solution Av = . 7. .154) Exercise Repeat the above example if M2 is converted to a diode-connected device. and M3 with another equal to 1=gm3 jjrO3 . In this section. M2 can be replaced with a small-signal resistance equal to rO2 .cls v. VDD V in M1 Vout Vb M2 M3 v in M1 r O2 r O1 v out 1 r g m3 O3 (b) (a) Figure 7.34(b). 2006] June 30.33 Source follower with biasing. with the quadratic ID -VGS relationship supplanting the exponential IC -VBE characteristic.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Transistors M2 and M3 therefore act as the load. (7.19 Calculate the voltage gain and output impedance of the circuit shown in Fig.gm1 g 1 jjrO1 jjrO2 jjrO3 m3 and (7. 7. 7. The circuit now reduces to that depicted in Fig.153) Rout = g 1 jjrO1 jjrO2 jjrO3 : m3 Note that 1=gm3 is dominant in both expressions.5 Summary and Additional Examples VDD C1 RG M1 C2 Vout Vb M2 V in C1 RG M1 C2 Vout VDD 351 V in Figure 7. we consider a number of additional examples to solidify the concepts introduced in this chapter. Example 7. (b) simpliﬁed circuit.34 (a) Example of CS stage. emphasizing analysis by inspection. with the former serving as a current source and the latter as a diode-connected device.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. transistor M1 drives the current-source load. M2 .155) Exercise Repeat the above example if the gate of M3 is tied to a constant voltage.35(a).20 Compute the voltage gain of the circuit shown in Fig. For simplicity. Thus the total impedance seen at the drain is equal to 1+ gm1 rO1 RS + Solution .21 Determine the voltage gain of the ampliﬁers illustrated in Fig.36(a) presents an impedance of 1 + gm1 rO1 RS + rO1 to the drain of M2 . assume rO1 = 1 in Fig. V DD M3 V in Vb M1 Vout M2 (a) (b) 1 r g m3 O3 V in M1 Vout r O2 Figure 7. 7. 7.36.cls v. Operating as a CS stage and degenerated by the diode-connected device M3 . Neglect channel-length modulation in M1 .35(b). we have 2 Av = . 7 CMOS Ampliﬁers Example 7. 7. Example 7. 2006] June 30. VDD V in M2 Vout Vb M1 RS V b1 M1 RS (b) VDD V b2 M2 Vout V in (a) Figure 7. transistor M1 in Fig. 1 rO1 : + g jjrO3 gm1 m3 Solution (7.35 (a) Example of CS stage. 2007 at 13:42 352 (1) 352 Chap. Simplifying the ampliﬁer to that in Fig.36 Examples of (a) CS and (b) CG stages .36(b). Degenerated by RS . 7. (b) simpliﬁed circuit. 7.

Calculate the voltage gain of the circuit shown in Fig.158) Exercise What happens if a resistance of value R1 is placed in series with the drain of M1 ? . we derive the model depicted in Fig. (b) simpliﬁed circuit. From Fig. VDD RD Vout V in M1 M2 I1 Vb v in 1 g m1 M 2 Example 7. A simple method of analyzing the circuit is to replace vin and M1 with a Thevenin equivalent.37(a) if = 0. giving a voltage gain of Av = .157) Exercise Replace RS wit a diode-connected device and repeat the analysis. Thus. 7.5 Summary and Additional Examples 353 rO1 jjrO2 . M1 operates as a source follower and M2 as a CG stage (why?).gm2 f 1 + gm1 rO1 RS + rO1 jjrO1 g : Av2 = 1 rO2 : gm1 + RS (7.29(b).36(b).cls v. obtaining (7. 7.22 RD v out (a) Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7. (b) In this circuit.37 (a) Example of a composite stage. 2007 at 13:42 353 (1) Sec. Solution Av = 1 RD 1 : gm1 + gm2 (7. 2006] June 30.37(b). M1 operates as a common-gate stage and M2 as the load. 7.156) In Fig.109): (7. 7.

7. M1 operates as a degenerated CS stage with a drain load consisting of the diode-connected device M3 and the current source M4 .131) Solution 1 vout1 = gm2 jjrO2 : 1 1 vin gm2 jjrO2 + gm1 (7. Calculate the voltage gain from the input to and to X .38 Example of composite stage. VDD Vb M4 V in X M2 M3 Y M1 Vout1 Vout2 Y Figure 7. Exhibiting a small-signal impedance of 1=gm2jjrO2 .” i. 7 CMOS Ampliﬁers Example 7. rO (with source grounded). resulting in 1 vout2 = . Assume = 0 for M1 . yielding from (7.6 Chapter Summary The impedances seen looking into the gate. 7. The reader can show that if rO1 = 1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . 2006] June 30. Signals simply perturb these conditions. 2007 at 13:42 354 (1) 354 Chap.cls v. the transistor must be “biased. respectively . This load impedance is equal to 1=gm3jjrO3 jjrO4 ..23 The circuit of Fig. and source of a MOSFET are equal to inﬁnity. and 1=gm (with gate grounded). gm3 jjrO3 jjrO4 : 1 + 1 jjr vin gm1 gm2 O2 (7. For Vout1 . transistor M2 acts as a load for the follower. the circuit serves as a source follower.160) Exercise Which one of the two gains is higher? Explain intuitively why.e. drain. In order to obtain the required small-signal MOS parameters such as gm and rO .159) For Vout2 . then M3 and M4 do not affect the source follower operation.38 produces two outputs. carry a certain drain current and sustain certain gate-source and drain-source voltages.

Consider the circuit shown in Fig. = 0.) 4. . The CS stage provides a moderate voltage gain. Calculate the maximum transconductance that M1 can provide (without going into the triode region. unless otherwise stated.6 Chapter Summary 355 Biasing techniques establish the required gate voltage by means of a resistive path to the supply rails or the output node (self-biasing). p Cox = 100 A=V2 . determine the maximum allowable value of VDD = 1. 1. We wish to design the circuit of Fig. (b) What are the required values of R1 and R2 if the input impedance must be at least 30 k .40 3. 7. Problems In the following problems.42 must be designed for a voltage drop of 200 mV across RS . and VTH = 0:4 V for NMOS devices and .0:4 V for PMOS devices. The circuit of Fig. and a low output impedance.39. assume n Cox = 200 A=V2 . a low input impedance. 7. 2. serving as a good voltage buffer. 2006] June 30.8 V 50 k Ω 1 kΩ W=L if M1 must M1 Figure 7. The voltage gain expressions for CS and CG stages are similar but for a sign. a high input impedance. The source follower provides a voltage gain less than unity. The CG stage provides a moderate voltage gain.40 for a drain current of 1 mA. With a single transistor. In the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Source degeneration improves the linearity but lowers the voltage gain. 2007 at 13:42 355 (1) Sec. Assume = 0.8 V R1 500 Ω = 20=0:18. and a moderate output impedance. only three ampliﬁer topologies are possible: common-source and common-gate stages and source followers. and a moderate output impedance. (a) Calculate the minimum allowable value of W=L if M1 must remain in saturation. 7. Source degeneration raises the output impedance of CS stages considerably. M1 R2 Figure 7. If W=L compute R1 and R2 such that the input impedance is at least 20 k .39 remain in saturation. 7. VDD = 1.cls v. a high input impedance.41. 7.

If W=L = 50=0:18. 2007 at 13:42 356 (1) 356 Chap. 7. We wish to design the stage in Fig.8 V 10 k Ω 1 kΩ M1 100 Ω Figure 7. 7. Assuming the current ﬂowing through R2 is one-tenth of ID1 .8 V R1 500 Ω M1 R2 RS 100 Ω Figure 7. a parasitic resistor.5 mA.8 V R1 500 Ω M1 R2 RS 200 Ω Figure 7. 7. RP has appeared in the circuit of Fig. 7.44 must be designed for a drain current of 1 mA. 7.cls v.45 for a drain current of 0. calculate the values of R1 and R2 such that these resistors carry a current equal to one-tenth of ID1 . 7 CMOS Ampliﬁers VDD = 1. calculate the required value of RD . The self-biased stage of Fig.43 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We know that circuit samples free from this error exhibit VGS = VDS whereas defective .8 V RG RD M1 Figure 7. Due to a manufacturing error. 2006] June 30. 6.42 5.44 provide a transconductance of 1=100 . 8.46. Consider the circuit depicted in Fig. where W=L = 20=0:18. calculate the values of R1 and R2 so that ID1 = 0:5 VDD = 1.43.41 VDD = 1. If M1 is to VDD = 1.

45 VDD = 1. We know that circuit samples free from this error exhibit VGS = VDS + 100 mV whereas VDD = 1.47. = 0:1 V. VB 2 = 1:2 V.48. 7. a parasitic resistor. calculate W1 and W2 . RP has appeared in the circuit of Fig. Due to a manufacturing error.8 V 10 k Ω 20 k Ω 1 kΩ M1 RS RP 200 Ω Figure 7.5 mA.1 .cls v. IX M1 VB IY M2 Figure 7. Determine the values of W=L and RP .6 Chapter Summary VDD = 1. Compare the output resistances of the two current sources. 9. The two current sources in Fig. An NMOS current source must be designed for an output resistance of 20 k and an output current of 0. 10. What is the maximum tolerable value of ? 12. .25 m and = 0:1 V. 2007 at 13:42 357 (1) Sec. 7.8 V R1 2 kΩ 357 M1 R2 Figure 7. M1 and M2 have lengths equal to 0.48 Determine W1 and W2 such that IX = 2IY = 1 mA. 7.46 samples exhibit VGS = VDS + VTH .47 defective samples exhibit VGS = VDS + 50 mV. If VB 1 = 1 V.49 must be designed for IX = IY = 0:5 mA. In the circuit of Fig. Assume VDS 1 = VDS 2 = VB = 0:8 V.1 . Determine the values of W=L and RP . and L1 = L2 = 0:25 m. 7.8 V 30 k Ω RP 2 kΩ M1 Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. What is the output resistance of each current source? 11.

cls v.52.50 14. 7. and 2 = 0:15 V.1 .1 . 7 CMOS Ampliﬁers IX M1 V B1 V B2 IY M2 Figure 7. (b) Now sketch IX as a function of VX as VX goes from 0 to VDD . 17. = 0:1 V. where W=L1 = 10=0:18 and W=L2 = 30=0:18. Calculate IX VDD W L IX M1 VB M2 2W L and IY if IY Figure 7. VDD = 1. 2007 at 13:42 358 (1) 358 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. W=L2 = 10=0:18.51 15.1 . 7. In the common-source stage of Fig. (a) What gate voltage yields a drain current of 0.5 mA? (Verify that M1 operates in saturation. (a) Determine VB such that ID1 = jID2 j = 0:5 mA for VX = 0:9 V. and VX has a dc level of 1.53. In the circuit of Fig. if = 0:1 V. VX M1 V B1 Figure 7. If W=L = 10=0:25. In the circuit of Fig. VB = 1 V and W=L = 20=0:25.51. VB1 = 0:2 V. W=L1 = 5=0:18. 7. W=L = 30=0:18 and = 0.49 13.1 .50 as a current source. 7.2 V.8 V M2 VB X M1 Figure 7. How are the output resistances of M1 and M2 related? Consider the circuit shown in Fig.52 16. 7.) . A student mistakenly uses the circuit of Fig. 2006] June 30. M1 and M2 serve as current sources.54. 1 = 0:1 V. calculate the impedance seen at the source of M1 . calculate VB such that VX = 0:9 V.

We wish to design the stage of Fig.55 Determine the required value of RD if the power dissipation must not exceed 1 mW.cls v.1 .8 V RD 2 kΩ Vout V in M1 Figure 7.8 V Vb M2 Vout V in M1 Figure 7. 7. (a) Compute the required gate bias voltage.8 V RD Vout V in M1 Figure 7. 7. (b) With such a gate voltage.8 V M2 VB IX VX 359 M1 Figure 7. . 7. 18. (b) if W=L2 = 20=0:18. 7.56 must provide a voltage gain of 10 with a bias current of 0. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume 1 = 0:1 V. how much can W=L be increased while M1 remains in saturation? What is the maximum voltage gain that can be achieved as W=L increases? 19.53 VDD = 1.6 Chapter Summary VDD = 1.54 is designed with W=L = 20=0:18. = 0. The CS stage of Fig. calculate the voltage gain of the stage. and 2 = 0:15 V. and ID = 0:25 mA.55 for a voltage gain of 5 with W=L 20=0:18. 20. calculate the required value of VB . VDD = 1.54 (b) With such a drain bias current. The circuit of Fig.5 mA. 2007 at 13:42 359 (1) Sec. VDD = 1.1 .56 (a) Compute the required value of W=L1 .

(b) Now calculate the voltage gain. 27. Assume = 0. If the width and the length of both transistors are doubled.56.1 .8 V M2 Vout V in M1 = Figure 7.1 . In the stage of Fig.56 is designed for a bias current of I1 with certain dimensions for M1 and M2 . Explain which one of the topologies shown in Fig. The CS stage of Fig. determine W=L2 . If 1 = 0:15 V. W=L1 = 20=0:18.59. Calculate the voltage gain if 1 = 0:1 V.59 26. how does the voltage gain change? Consider two cases: (a) the bias current remains constant.1 and 2 = 0:05 V. determine the required value of W=L2 .58 mA. 7. The CS stage depicted in Fig. In the circuit of Fig.57 24. VDD Vb M2 Vout V in M1 (a) VDD V in M2 Vout Vb M1 (b) Figure 7. 7. The circuit of Fig. . 7 CMOS Ampliﬁers 21.58 must achieve a voltage gain of 15 at a bias current of 0.59 for a voltage gain of 3. 22. 23.57 is preferred.cls v. (c) Explain why this choice of W=L2 yields the maximum gain.59 must achieve a voltage gain of 5. W=L1 = 10=0:18 and ID1 = 0:5 mA.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7. (a) If W=L2 = 2=0:18. determine W=L2 such that M1 operates at the edge of saturation. 7. We wish to design the circuit shown in Fig. 7. (a) If = 0. 2007 at 13:42 360 (1) 360 Chap. If W=L1 VDD = 1. 2006] June 30.5 VDD = 1. 7. (b) What is the maximum allowable bias current if M1 must operate in saturation? 20=0:18. 7. 25. compute the required value of W=L1 . or (b) the bias current is doubled. M2 has a long length so that 2 1 . and ID = 1 mA.8 V V in M2 Vout Vb M1 Figure 7.

cls v. 33. 7. (a) If RD = 1 k .61 30. Assuming gm rO 1. Assume = 0. 2006] June 30. VDD = 1. The CS stage of Fig. 7. 7.60 28. Assume = 0. calculate the voltage gain of the circuit. Does the transistor operate in saturation for this choice of RD ? 31. 7. The degenerated CS stage of Fig. Assume 6= 0. compute the required value of W=L for a gate voltage of 1 V. 7. Does the transistor operate in saturation for this choice of W=L? (b) If W=L = 50=0:18. Determine the output impedance of each circuit shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Calculate the voltage gain of the circuits depicted in Fig. determine the required value of W=L. What is the voltage gain of the circuit? .64 carries a bias current of 1 mA.8 V RD Vout V in M1 RS Figure 7. In the circuit of Fig. If 6= 0. 7. 32.60. Consider a degenerated CS stage with 0.63. 34. determine the voltage gain of the stages shown in Fig. If RD = 1 k and = 0:1 V.61. 29.62. determine the required value of RD . determine the gate voltage such that M1 operates at the edge of saturation. Assume a drop of 200 mV across RS and = 0.1 . 2007 at 13:42 361 (1) Sec. 7.6 Chapter Summary VDD M2 Vout Vb M2 VDD M3 Vout V in M1 V in M1 M3 Vb VDD M2 Vout 361 V in M1 (a) (b) (c) VDD V in M2 Vout Vb M1 M3 Vb V in VDD M2 Vout M1 M3 V in (e) (f) VDD M2 RD Vout M1 (d) Figure 7.61 must provide a voltage gain of 4 with a bias current of 1 mA.

The common-gate stage shown in Fig. whether M1 comes closer to the triode region) and the voltage gain. 7.66. and Vb = 1 V.g. 38. In the common-source stage depicted in Fig. = 0. 7.68. (c) With the values found in (b). what happens if W=L is twice that found in (a)? Consider both the bias conditions (e.68 must provide a voltage gain of 4 and an input impedance of 50 . If ID = 0:5 mA. where I1 deﬁnes the bias current of M1 and C1 is very large.cls v. determine W=L to obtain a voltage gain of 5. determine the values of RD and W=L. An adventurous student decides to try a new circuit topology wherein the input is applied to the drain and the output is sensed at the source (Fig. what is the maximum allowable value of RD ? (b) With the value found in (a). (a) Compute the value of W=L to obtain a voltage gain of 5. calculate the voltage gain of the circuit.67. 41. Consider the CS stage shown in Fig. Suppose in Fig. 7 VDD M2 RD Vout V in M1 CMOS Ampliﬁers VDD RD Vout M2 I1 Vb (c) VDD RD Vout V in M2 M1 Vb Vb V in VDD M2 M1 Vout M3 (d) (e) Figure 7.. 37. (a) If = 0 and I1 = 1 mA. and C1 is very large. A CG stage with a source resistance of RS employs a MOSFET with 0. (b) Choose the values of R1 and R2 to place the transistor 200 mV away from the triode region while R1 + R2 draws no more than 0. 2007 at 13:42 362 (1) 362 VDD M2 Vout V in M1 M3 V in M1 M3 (a) (b) Chap. 7.65).1 mA from the supply. determine the voltage gain of the circuit and discuss the result. Assuming gm rO . and = 0. RD = 500 . 7. the drain current of M1 is deﬁned by the ideal current source I1 and remains independent of R1 and R2 (why?). 40.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Repeat Problem 34 with = 0 and compare the results. . 7. 39. Determine the values of W=L and RD for an input impedance of 50 and maximum voltage gain (while M1 remains in saturation).62 35. ID = 0:5 mA. Suppose I1 = 1 mA. 36. 2006] June 30. = 0. Assume 6= 0.

cls v. (c) Compute the voltage gain.65 42.64 V in VB M1 Vout RS Figure 7.63 VDD = 1. calculate the required value of W=L.70 is biased by means of I1 = 1 mA. 7.69 must provide an input impedance of 50 and an output impedance of 500 . 2007 at 13:42 363 (1) Sec. Assume = 0 and C1 is very large. The CG stage depicted in Fig. 7. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 V RD Vout V in M1 Figure 7. 43.6 Chapter Summary VDD R out V in M2 M1 Vb V in R out M1 M2 I1 (b) 363 Vb (a) R out Vb M2 VDD V in M2 Vb V in M1 (c) M1 M3 M3 R out (d) Figure 7. Assume = 0. (a) What is the maximum allowable value of ID ? (b) With the value obtained in (a). (a) What value of RD places the transistor M1 100 mV away from the triode region? (b) What is the required W=L if the circuit must provide a voltage gain of 5 with the value of RD obtained in (a)? . The CG ampliﬁer shown in Fig. 2006] June 30.

71. 7.74. Repeat Problem 45 for the circuit shown in Fig. 2006] June 30.72.8 V RD Vout V in M1 Vb Figure 7. 2007 at 13:42 364 (1) 364 Chap. 45. 7 VDD = 1. Determine the voltage gain of each stage depicted in Fig.67 VDD = 1.68 VDD = 1. .8 V R1 C1 M1 V in I1 C1 RD Vout Figure 7. 7. Explain why this stage is not a common-gate ampliﬁer. 46. calculate the voltage gain of the circuit shown in Fig.66 VDD = 1. 7. (a) Writing vout =vin = vX =vin vout =vX and assuming = 0.cls v.69 44.8 V R1 C1 M1 V in R2 I1 C1 RD Vout CMOS Ampliﬁers Figure 7. 47.8 V RD Vout V in M1 Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. compute the overall voltage gain. where a common-source stage (M1 and RD1 ) is followed by a common-gate stage (M2 and RD2 ). Assume = 0. (b) Simplify the result obtained in (a) if RD1 ! 1. Consider the circuit of Fig. Assuming = 0. 7. Explain why this result is to be expected.73.

We wish to design the source follower shown in Fig. 49. Calculate the voltage gain if W=L = 20=0:18 and = 0:1 V.6 Chapter Summary 365 VDD = 1.8. Assume = 0 and the capacitors are very large. The circuit of Fig. 7. 7.8 if = 0. 7. The source follower depicted in Fig. Determine the required value of W=L.77 for a voltage gain of 0.78 must exhibit an output impedance of less than 50 with a power budget of 2 mW. The source follower of Fig.8 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 7. .cls v.8 V RD Vout C1 V in M1 I1 Figure 7. determine the required gate bias voltage. If W=L = 30=0:18 and = 0. 50.78 employs a current source. Determine the values of I1 and W=L if the circuit must provide an output impedance less than 100 with VGS = 0:9 V. Compute the required value of W=L for a voltage gain of 0. 7.77 is to be designed with a maximum bias gate voltage of 1. Assume = 0.1 . 52. 2006] June 30. 7. The source follower shown in Fig. 2007 at 13:42 365 (1) Sec. 51.76 is biased through RG . 7. Assume = 0.75. 53.71 48.70 VDD M2 Vout V in M1 RS Vb V in (a) VDD M2 RD Vout M1 Vb V in M1 RS VDD M2 Vout Vb R1 (c) (b) VDD Vb M3 M2 RD Vout V in M1 (d) V in Vb RD I1 (e) VDD M1 M2 Vout Vb Figure 7. Calculate the voltage gain of the stage depicted in Fig.

The CS ampliﬁer of Fig. 57. where a source follower (M1 and I1 ) precedes a common-gate stage (M2 and RD ). Design Problems In the following problems. compute the overall voltage gain. Assume C1 is very large and = 0.82 for a voltage gain of 5 and an output impedance of 1 k . Compute the required value of W=L. 2007 at 13:42 366 (1) 366 VDD R D1 M2 M1 R D2 Vout Vb X V in Chap. (a) Writing vout =vin = vX =vin vout =vX . Consider the circuit shown in Fig. 58.72 VDD R D2 V in M1 M2 R D1 X Vout Vb Figure 7.81. Bias the transistor so that it operates 100 mV away from the triode region.79 for a voltage gain of 0. 7.82 must be designed for a voltage gain of 5 with a power budget of 2 mW. 7. 7. Assume 6= 0.74 54. 2006] June 30. (b) Simplify the result obtained in (a) if gm1 = gm2 . unless otherwise stated.73 VDD I1 Vout RG V in M1 Figure 7. 7. 7 CMOS Ampliﬁers Figure 7. If RD ID = 1 V. 7. determine the required value of W=L. 55. Design the CS stage shown in Fig.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 56. assume = 0. We wish to design the source follower of Fig.80. Make the same assumptions . Determine the voltage gain of the stages shown in Fig.8 with a power budget of 3 mW. Assume the capacitors are very large and RD = 10 k .

82 for maximum voltage gain but with W=L 50=0:18 and a maximum output impedance of 500 . 7. Make the same assumptions as those in Problem 57.78 as those in Problem 57.83 must provide a voltage gain of 4 with a power budget of 2 mW while the voltage drop across RS is equal to 200 mV. The degenerated stage depicted in Fig.6 Chapter Summary VDD RD Vout C1 R3 R4 M1 R1 CB R2 367 V in Figure 7.76 VDD = 1. Assume . 2006] June 30. 7. We wish to design the CS stage of Fig. Design the circuit of Fig. design the circuit. Determine the required current.8 V M1 Vout 1 kΩ RS Figure 7. 61.cls v.8 V V in M1 Vout I1 Figure 7. 7.8 V V in 500 Ω M1 Vout RS Figure 7.77 VDD = 1. 2007 at 13:42 367 (1) Sec.83 for a voltage gain of 5 and a power budget of 6 mW.75 RG V in 50 k Ω VDD = 1. If the overdrive voltage of the transistor must not exceed 300 mV and R1 + R2 must consume less than than 5 of the allocated power. Make the same assumptions as those in Problem 57. 59. 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 60.

8 V V in M1 C1 Vout I1 50 Ω Chap. 62. 7 CMOS Ampliﬁers RL Figure 7.79 VDD V in M1 Vout RS Vb M2 (a) (b) VDD V in M1 Vout Vb M2 RS (c) VDD V in M1 Vout M2 VDD V in R1 M2 R2 (d) (e) VDD VDD V b2 V b1 Vb M3 M2 Vout V in M1 (f) M1 Vout M3 M1 Vout V in M2 Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. M2 serves as a current source. In the circuit of Fig. 2007 at 13:42 368 (1) 368 VDD = 1.cls v.80 VDD RD Vout V in M1 X M2 I1 Vb Figure 7. 63. Design the stage for a voltage 200 . The circuit shown in Fig.81 the voltage drop across RS is equal to the overdrive voltage of the transistor and RD = .85. 2006] June 30. Assuming a power budget of 2 mW and an input impedance of 20 k . 7. Select the values of C1 and CS so that their impedance is negligible at 1 MHz. 7. with CS serving as a low impedance at the frequencies of interest. design the circuit such that M1 operates 200 mV away from the triode region.84 must provide a voltage gain of 6.

1 .5 V (i.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. M2 must remain in saturation if Vout 1:5 V).87 incorporates a degenerated PMOS current source.1 for both ..84 VDD = 1. The CS stage of Fig.1 for both transistors and the maximum allowable level at the output is 1. 7.83 VDD = 1.8 V R1 C1 M1 V in RS CS RD Vout Figure 7.e. Consider the circuit shown in Fig.86. 7. The degeneration must raise the output impedance of the current source to about 10rO1 such that the voltage gain remains nearly equal to the intrinsic gain of M1 . (b) Design the circuit for a voltage gain of 15 and a power budget of 3 mW.8 V RG C1 V in M1 RD C2 Vout 369 Figure 7. Assume = 0:1 V. 7.8 V R1 C1 M1 V in R2 RS RD Vout Figure 7.6 Chapter Summary VDD = 1. 2007 at 13:42 369 (1) Sec. 64.8 V Vb M2 Vout V in M1 Figure 7. Assume = 0:1 V. 65.cls v. (a) Calculate the voltage gain. 2006] June 30. where CB is very large and n = 0:5p = 0:1 V.85 gain of 20 and a power budget of 2 mW. Assume RG 10rO1 jjrO2 and the dc level of the output must be equal to VDD =2.82 VDD = 1.

7.cls v.8 V M2 RG Vout V in M1 CMOS Ampliﬁers CB Figure 7. VDD = 1. VDD = 1. (a) If VB = 1 V.87 transistors and a power budget of 2 mW.89 . 2007 at 13:42 370 (1) 370 Chap.8 V RS Vb M2 Vout V in M1 Figure 7. (b) Determine W=L1 to achieve a voltage gain of 30. Assume a power budget of 3 mW. determine the values of W=L2 and RS so that the impedance seen looking into the drain of M2 is equal to 10rO1 .88 for a voltage gain of 4.8 V RD Vout V in M1 I1 and a Figure 7. 2006] June 30. Assuming a power budget of 1 mW and an overdrive of 200 mV for M1 .89 for an input impedance of 50 voltage gain of 5.86 VDD = 1.88 67. design the circuit shown in Fig.8 V M2 Vout V in M1 Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 66. 7. 7 VDD = 1. Design the common-gate stage depicted in Fig.

93 for a voltage gain of 0. Design the circuit of Fig. Consider the source follower shown in Fig.8 V RD V out V in M1 RS RG CG 10RD and CG serves as a Figure 7. Assume the output dc level is equal to VDD =2 and the input impedance exceeds 10 k ..BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.91 shows a self-biased common-gate stage.6 Chapter Summary 371 68. Design the circuit for a power budget of 5 mW and a voltage gain of 5. 7. Select RS 10=gm and R1 + R2 = 20 k . 7. 2007 at 13:42 371 (1) Sec. VTH + 250 mV = VDD . (Hint: since M1 is biased 250 mV away from the triode region.e. we have RS ID + VGS . 7. 7.92 such that it can accommodate an output swing of 500 VDD = 1. where RG VDD = 1.8 V RD V out V in M1 R1 RS R2 Figure 7. Vout can fall below its bias value by 250 mV without driving M1 into the triode region.cls v.90 such that M1 operates 100 mV away from the triode region while providing a voltage gain of 4. 70.) 71. ID RD . Assume a voltage gain of 4 and an input impedance of 50 . Assume RS 10=gm so that the input impedance remains approximately equal to 1=gm . VDD = 1.92 mVpp .8 and a power budget of 2 mW. 7. Figure 7.8 V RD Vout V in M1 RS Figure 7. i. Design the source follower depicted in Fig. The circuit must provide a voltage gain of .91 low impedance so that the voltage gain is still given by gm RD .90 69. Design the CG stage shown in Fig.94. 2006] June 30. Assume a power budget of 2 mW. 72.

a voltage gain of 0. .8 V RG V in X RS M1 C1 Vout 50 Ω RL Figure 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 372 (1) 372 Chap. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD . and a minimum allowable output of 0. SPICE Problems In the following problems.94 0. Assuming = 0:1 V. 74.9. 2006] June 30. The circuit must operate VDD = 1.8 V 10 k Ω I1 Vout W ( (1 L V in C1 1 kΩ M1 Figure 7. In the circuit of Fig. VDD = 1. use the MOS models and source/drain dimensions given in Appendix A.. In the source follower of Fig.1 for both transistors. Assume the input impedance exceeds 20 k .95.1 .96.96 (a) Using hand calculations.95 with a power budget of 3 mW. M2 serves as a current source. Design the circuit such that the dc voltage at node X is equal to VDD =2. determine W=L1 such that gm1 = 100 .8 at 100 MHz while consuming 3 mW.cls v. 73.e. design the circuit. 7.8 V RG V in M1 Vout RS Figure 7. M2 must remain in saturation if VDS 2 0:3 V). I1 is an ideal current source equal to 1 mA. 7 CMOS Ampliﬁers VDD = 1.93 VDD = 1. 7.8 V V in M1 Vout Vb M2 Figure 7.3 V (i. respectively.

cls v.5 V.2 V.8 V 10 0. 7.97 (a) What value of Vin places M2 at the edge of saturation? (b) What value of Vin places M1 at the edge of saturation? (c) Determine the voltage gain if Vin has a dc value of 1.97 employs a bias current source. What is the voltage gain under these conditions? (b) What is the change in the gain if the mobility of the NMOS device varies by 10? Can you explain this result using the expressions derived in Chapter 6 for the transconductance? . The source follower of Fig.99. M2 VDD = 1. (c) What dc value at the input reduces the gain by 10 with respect to that obtained in (a)? 77.18 Vout V in M1 10 0. 2007 at 13:42 373 (1) Sec. 7. M2 .18 Figure 7.98 (a) Determine the voltage gain if Vin has a dc value of 1. M1 V in VDD = 1. (b) Verify that the gain drops if the dc value of Vin is higher or lower than 1.18 Figure 7.8 V W2 0.. 7. (d) What is the change in the gain if Vb changes by 50 mV? 76.98 depicts a cascade of a source follower and a common-gate stage.8 V 20 0.18 Vout M2 0. Consider the CS stage shown in Fig. Figure 7.6 Chapter Summary 373 (b) Select C1 for an impedance of 100 ( 1 k ) at 50 MHz. (d) What is the change in the gain if I1 varies by 20? 75.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume Vb 1:2 V and W=L1 = W=L2 = 10 m=0:18 m. where M2 operates as a resistor.2 V. VDD 1 kΩ = Vout V in M1 M2 1 mA Vb Figure 7. 2006] June 30. (c) Simulate the circuit and obtain the voltage gain and output impedance at 50 MHz.8 V yields an output dc level of 1 V.99 (a) Determine W2 such that an input dc level of 0.

VDD = 1. 7 CMOS Ampliﬁers 78.100 .100 and compare the sensitivities to the mobility.18 Vout 10 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Repeat Problem 77 for the circuit illustrated in Fig.18 M2 V in M1 Figure 7. 7. 2006] June 30. 2007 at 13:42 374 (1) 374 Chap.cls v.8 V W2 0.

Since each op amp implemented a mathematical operation (e.1 General Considerations The operational ampliﬁer can be abstracted as a black box having two inputs and one output.2 Shown in Fig. In this chapter.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. developing op-amp-based circuits that perform interesting and useful functions.1) 1 Vacuum tubes were amplifying devices consisting of a ﬁlament that released electrons. the op amp symbol distinguishes between the two inputs by the plus and minus sign. Op amps realized by vacuum tubes1 served as the core of electronic “integrators. 375 . integrated op amps serve as building blocks in (active) ﬁlters. thus forming systems whose behavior followed a given differential equation.g.” such circuits were used to study the stability of differential equations that arose in ﬁelds such as control or power systems. we study the operational ampliﬁer as a black box. 2 In modern integrated circuits.1(a). The outline is shown below. We view the op amp as a circuit that ampliﬁes the difference between the two inputs..cls v. The voltage gain is denoted by A0 : Vout = A0 Vin1 . Vin1 and Vin2 are called the “noninverting” and “inverting” inputs.” “differentiators. Similarly. respectively. integration). Called “analog computers. arriving at the equivalent circuit depicted in Fig. General Concepts Op Amp Properties Linear Op Amp Circuits Noninverting Amplfier Inverting Amplifier Integrator and Differentiator Voltage Adder Nonlinear Op Amp Circuits Precision Rectifier Logarithmic Amplifier Square Root Circuit Op Amp Nonidealities DC Offsets Input Bias Currents Speed Limitations Finite Input and Output Impedances 8. for example.1(b). the term “operational ampliﬁer” was born. 2006] June 30. and another that controlled the ﬂow—somewhat similar to MOSFETs. 2007 at 13:42 375 (1) 8 Operational Ampliﬁer As A Black Box The term “operational ampliﬁer” (op amp) was coined in the 1940s. 8. Op amps ﬁnd wide application in today’s discrete and integrated electronics. well before the invention of the transistor and the integrated circuit. the analo-to-digital converter(s) used in digital cameras often employ op amps.. Vin2 : (8. a plate that collected them.” etc. In the cellphone studied in Chapter 1. 8. op amps typically have two outputs that vary by equal and opposite amounts.

8 Operational Ampliﬁer As A Black Box Vout V in1 V in2 (a) (b) A 0 (V in1 − V in2 ) Figure 8. forms the foundation for many circuit topologies that would be difﬁcult to realize using an ampliﬁer having Vout = AVin .2(b)]. we may say Vin1 = Vin2 if A0 = 1. The positive slope (gain) is consistent with the label “noninverting” given to Vin1 . Vout = A0 Vin1 . the ampliﬁer stages studied in Chapters 5 and 7 have only one input node (i.1 The circuit shown in Fig. 8.cls v. 8. e. Example 8. As seen throughout this chapter. Vout = .A0 Vin2 [Fig. We can then consider the effect of the op amp “nonidealities” on the performance. (b) equivalent circuit. On the other hand. 8. 2 V.e. obtaining the behavior shown in Fig.. brings Vin1 and Vin2 close to each other. Note that the output is tied to the inverting input. an inﬁnite input impedance. The very high gain of the op amp leads to an important observation. 8. quickly revealing the basic function of the circuit. Vin2 . the op amp. Since realistic circuits produce ﬁnite output swings. . A common mistake is to interpret Vin1 = Vin2 as if the two terminals Vin1 and Vin2 are shorted together. It must be borne in mind that Vin1 . the principal property of the op amp. if Vin1 = 0. Ampliﬁer circuits having two inputs are studied in Chapter 10. and inﬁnite speed.1(a) is always small: out Vin1 . a zero output impedance. the difference between Vin1 and Vin2 in Fig. we have Vout = A0 Vin1 . Vin2 = VA : 0 (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. After all. Vin2 becomes only inﬁnitesimally small as A0 ! 1 but cannot be assumed exactly equal to zero. Vout V in1 Vout A0 V in1 V in2 Vout −A 0 Vout V in2 (a) (b) Figure 8. Determine the output voltage if Vin1 = +1 V and A0 = 1000. they sense the input voltage with respect to ground). along with the circuitry around it. With Vin2 = 0. 2007 at 13:42 376 (1) 376 V in1 V in2 Vout Chap. 2006] June 30.3 is called a “unity-gain” buffer.2 Op amp characteristics from (a) noninverting and (b) inverting inputs to output.1 (a) Op amp symbol. Following the above idealization. revealing a negative slope and hence an “inverting” behavior.. The reader may wonder why the op amp has two inputs. In fact. It is instructive to plot Vout as a function of one input while the other remains at zero.2) In other words. the ﬁrst-order analysis of an op-amp-based circuit typically begins with this idealization.g. How does the “ideal” op amp behave? Such an op amp would provide an inﬁnite voltage gain.2(a).

an op amp may operate between ground and a positive supply. 8.5) 1000.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.4 to explicitly indicate the supply voltages. A0 = Vin = 1 V.3) (8.3 Unity-gain buffer. (8. the difference between the two inputs would be zero and Vout = Vin . Indeed. 8. hence the term “unity-gain buffer. Solution If the voltage gain of the op amp were inﬁnite. In each case. VCC V in1 V in2 VEE Vout Figure 8. and Vout = 0:999 V. For example. (8.cls v. we study a number of circuits that utilize op amps to process analog signals.4 Op amp with supply rails.2 Op-Amp-Based Circuits In this section.4) Vout = A0 : Vin 1 + A0 As expected.” For a ﬁnite gain.9999? Op amps are sometimes represented as shown in Fig. 8. Vin1 . Vout : That is. 2007 at 13:42 377 (1) Sec. In this example. we write Vout = A0 Vin1 . Vin2 is small compared to Vin and Vout . we ﬁrst assume an ideal op amp to understand the underlying principles and subsequently examine the effect of the ﬁnite gain on the performance. . VEE and VCC . in which case VEE = 0. the gain approaches unity as A0 becomes large.2 Op-Amp-Based Circuits A 0 = 1000 +1V 377 V in Vout Figure 8. Exercise What value of A0 is necessary so that the output voltage is equal to 0. Vin2 = A0 Vin .

g.5 Noninverting ampliﬁer. the circuit is called a “noninverting ampliﬁer. However.g.8) Vout 1 + R1 : Vin R2 (8.6) Vin1 Vin2 R R2 R Vout .. If R1 =R2 ! 0.9) Due to the positive gain. If R1 =R2 ! 1.6(b).1 Noninverting Ampliﬁer Recall from Chapters 5 and 7 that the voltage gain of ampliﬁers typically depends on the load resistor and other parameters that may vary considerably with temperature or process. as depicted in Fig. if R2 approaches inﬁnity. we have (8. 8. we note that Vout =Vin ! 1. 2006] June 30. 2007 at 13:42 378 (1) 378 Chap. 20.g. Op-ampbased circuits can provide such precision. the voltage gain itself may suffer from a variation of.3 because the ideal op amp draws no current at its inputs. R1 =R2 remains constant. Illustrated in Fig. Shown in Fig. this case in fact reduces to the unity-gain buffer of Fig. 8 Operational Ampliﬁer As A Black Box 8. 3 Variation with process means the circuits fabricated in different “batches” exhibit somewhat different characteristics..BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. if R2 approaches zero.2 Solution = 1 and R1 =R2 = 0.3 As a result. A/D converters)..5.6(a).g. the noninverting ampliﬁer consists of an op amp and a voltage divider that returns a fraction of the output voltage to the inverting input: V in1 A0 V in V in2 R1 R2 Vout Figure 8. Vin2 = R R2 R Vout : 1+ 2 Since a high op amp gain translates to a small difference between Vin1 and Vin2 . Of course. with no effect on the gain if the op amp is ideal. the voltage gain depends on only the ratio of the resistors. we have Vout =Vin ! 1. with no fraction of the output fed back to the input.” Interestingly.2. . The idea of creating dependence on only the ratio of quantities that have the same dimension plays a central role in circuit design. 8.cls v. e. in some applications (e. say. 1+ 2 and hence (8. Resistor R1 simply loads the output node. a much more precise gain (e. e. 8.7) (8.000) is required. if R1 and R2 increase by 20. this occurs because the circuit reduces to the op amp itself. 8. yielding a zero drop across R1 and hence Vin2 = Vout . Study the noninverting ampliﬁer for two extreme cases: R1 =R2 Example 8.. 2.

and the gain of the overall ampliﬁer.6): (8.11) Vin 1 + R2 A0 : R1 + R2 As expected.10) the “open-loop” gain and the latter the “closed-loop” gain.1 1 . 2007 at 13:42 379 (1) Sec. Exercise Suppose the circuit is designed for a nominal gain of 2. and substitute for Vin2 from (8..00 but the R1 and mismatch of 5% (i. Based on the model shown in Fig.11) indicates that the ﬁnite gain of the op amp creates a small error in the value of Vout =Vin . 8.12) Vin R2 R2 A0 Called the “gain error. we write Vin1 .1(b). What is the actual voltage gain? R2 suffer from a Let us now take into account the ﬁnite gain of the op amp. If much greater than unity.2 Op-Amp-Based Circuits 379 Vout V in R1 R2 = 0 (a) (b) Vout V in R1 R2 = Figure 8. we call the former Vout 1 + R1 1 . 1 + R1 1 : (8. Vout =Vin . Vin2 A0 = Vout . 2006] June 30. To avoid confusion between the gain of the op amp. R1 = 1 0:05R2 ). Equation (8.e. for 1: Vout = A0 (8. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. this result reduces to (8.9) if A0 R2 =R1 + R2 1.6 Noninverting ampliﬁer with (a) zero and (b) inﬁnite value for R2 . A0 .” the term 1 + R1 =R2 =A0 must be minimized according to each application’s requirements. 8. the term A0 R2 =R1 + R2 can be factored from the denominator to permit the approximation 1 + .cls v.

.

Example 8. or (b) 50. we have 1 + R1 =R2 Solution . For a nominal gain of 5.3 A noninverting ampliﬁer incorporates an op amp having a gain of 1000. Determine the gain error if the circuit is to provide a nominal gain of (a) 5.

obtaining a gain error of: (8. 1 1 + R1 A = 0:5: R2 0 = 5.13) .

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. if 1 + R1 =R2 = 50.cls v. 2007 at 13:42 380 (1) 380 Chap. then . 8 Operational Ampliﬁer As A Black Box On the other hand.

7(b)]. Recall from Section 8.1 that if the op amp gain is inﬁnite. then a ﬁnite output swing translates to Vin1 .R1 : Vin R2 (8. (c) analogy with a seesaw.7(a). the entire input voltage appears across R2 . For this reason. R 1 1 + R1 A = 5: 2 0 (8. 8. 8.2 Inverting Ampliﬁer Depicted in Fig.. node X bears a zero potential even though it is not shorted to ground. the I/O impedances are derived in Problem 7. producing a current of Vin =R2 .2. (b) currents ﬂowing in resistors. Vin2 ! 0. which must then ﬂow through R1 if the op amp input draws no current [Fig. Vout = Vin R1 R2 yielding (8. node X is called a “virtual ground. the “inverting ampliﬁer” incorporates an op amp along with resistors R1 and R2 while the noninverting input is grounded. 0 . i. For a nonideal op amp. a higher closed-loop gain inevitably suffers from less accuracy. With an ideal op amp. Exercise Repeat the above example if the op amp has a gain of 500. the noninverting ampliﬁer exhibits an inﬁnite input impedance and a zero output impedance. Since the left terminal of R1 remains at zero and the right terminal at Vout .14) In other words.15) Vout = .” Under this condition. R1 R2 X Vout V in V in Virtual Ground (a) (b) V in R2 R2 X R1 Vout A R2 R1 (c) B Figure 8.7 (a) Inverting ampliﬁer. 8.16) .e.

This behavior is similar to a seesaw [Fig.18) 1 1 1 + R2 : 2 R1 + A0 R1 Factoring R2 =R1 from the denominator and assuming 1 + R1 =R2 =A0 =. Let us now compute the closed-loop gain of the inverting ampliﬁer with a ﬁnite op amp gain. Vout = A0 Vin1 . This trade-off sometimes makes this ampliﬁer less attractive than its noninverting counterpart. 8. the topology of Fig. Vout R2 V in R1 Figure 8.g. 8.8 Inverting ampliﬁer. displaying a similarity with the noninverting circuit but with the input applied at a different point. We note from Fig.19) (8. a lower R2 results in a greater gain but a smaller input impedance.” As with its noninverting counterpart.7(b). respectively. allowing displacement of point A to be “ampliﬁed” (and “inverted”) at point B .7(c)].R Vout = .A0 VX : Equating the currents through R2 and R1 and substituting . Such a short in Fig.Vout =A0 for VX . It is important to understand the role of the virtual ground in this circuit.8. in Fig. yielding Vout = 0. we obtain (8.7(a) that the currents ﬂowing through R2 and R1 are given by Vin .17) (8.cls v. It is interesting to note that the inverting ampliﬁer can also be drawn as shown in Fig. thereby experiencing only small variations with temperature and process. Vout =R1 . Vin =R2 . If the inverting input of the op amp were not near zero potential. 8. 2007 at 13:42 381 (1) Sec. 8. the gain of this circuit is given by the ratio of the two resistors. then neither Vin =R2 nor Vout =R1 would accurately represent the currents ﬂowing through R2 and R1 .. Vin2 = .2 Op-Amp-Based Circuits 381 Due to the negative gain. 8. does not move). Moreover. the circuit is called the “inverting ampliﬁer. That is. In contrast to the noninverting ampliﬁer. 8.VX =R2 and VX .7(a) exhibits an input impedance equal to R2 —as can be seen from the input current. respectively. 8.20) .7(b) would force to ground all of the current ﬂowing through R2 . The above development also reveals why the virtual ground cannot be shorted to the actual ground. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 1 1 + R2 1 + 1 Vin A0 R1 A0 (8. where the point between the two arms is “pinned” (e.

21) As expected. a higher closed-loop gain ( .R1 =R2 ) is accompanied with a greater gain error. we have (8. . Note that the gain error expression is the same for noninverting and inverting ampliﬁers. R1 1 . Vout . 1 1 + R1 : Vin R2 A0 R2 1.

7(a) for a nominal gain of 4. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and an input impedance of at least 10 k . 8 Operational Ampliﬁer As A Black Box Design the inverting ampliﬁer of Fig.cls v.4 Solution Since both the nominal gain and the gain error are given. 8. We have R1 = 4 2 . 2007 at 13:42 382 (1) 382 Chap. we must ﬁrst determine the minimum op amp gain. Example 8. a gain error of 0:1.

we choose: (8. Z1 . 8. In the above example. we assumed the input impedance is approximately equal to R2 .24) R2 = 10 k R1 = 40 k : (8. we can write Z1 Z2 Vout V in Figure 8. Vin Z2 (8. How accurate is this assumption? With A0 = 5000.Vout =5000 .22) (8. yielding an input current of Vin + 4Vin =5000=R1.3 Integrator and Differentiator Our study of the inverting topology in previous sections has assumed a resistive network around the op amp.2. (8.9 Circuit with general impedances around the op amp.9). our assumption leads to an error of about 0:08—an acceptable value in most applications. 8.27) . That is.25) (8. In analogy with (8. Vout . the virtual ground experiences a voltage of . In general.23) A0 = 5000: Since the input impedance is approximately equal to R2 .4Vin =5000. RR 1 1 + 1 = 0:1: A0 R2 Thus. it is possible to employ complex impedances instead (Fig.26) Exercise Repeat the above example for a gain error of 1% and compare the results.16).

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. Z1 C1 s. Equating the currents ﬂowing through R1 and C1 gives Vout Vin f Figure 8. This can also be seen in the time domain. Z1 is a capacitor and Z2 a resistor (Fig.2 Op-Amp-Based Circuits 383 where the gain of the op amp is assumed large. Figure 8. 8.4 the circuit operates as an integrator (and a low-pass ﬁlter).11 Frequency response of integrator.31) Equation (8. integrators originally appeared in analog computers to simulate differential equations. If Z1 or Z2 is a capacitor.12(a). As mentioned at the beginning of the chapter. 8. electronic integrators ﬁnd usage in analog ﬁlters. two interesting functions result.5 Plot the output waveform of the circuit shown in Fig.9. Vin = .28) (8.10 Integrator. Assume a zero initial condition across C1 and an ideal op amp. 8. That is. control systems.R 1 s: C 1 1 Providing a pole at the origin. 8. we have C1 R1 X Vout V in = Figure 8.1 and Z2 = R1 .29) = . and many other applications.29) indicates that Vout =Vin approaches inﬁnity as the input frequency goes to zero. Integrator Suppose in Fig. 4 Pole frequencies are obtained by setting the denominator of the transfer function to zero. C1 s Vin R1 1 (8. approaching an open circuit and reducing the circuit to the open-loop op amp. . R 1C Z 1 1 Vin dt: (8. This is to be expected: the capacitor impedance becomes very large at low frequencies. 2007 at 13:42 383 (1) Sec. Vout = . Example 8.10).30) Vout = .C dVout 1 R1 dt and hence (8. With an ideal op amp. Today.11 plots the magnitude of Vout =Vin as a function of frequency.cls v.

2007 at 13:42 384 (1) 384 Chap. To gain more insight. Thus.10 with VX . We may therefore consider the RC ﬁlter as a “passive” approximation of the integrator. so do the currents through R1 and C1 .34) .12(b)]: Solution Vout = . 8.13(b) becomes slow enough to be approximated as a ramp. The above example demonstrates the role of the virtual ground in the integrator. RVC t 0 t Tb : 1 1 Z (8. Exercise Repeat the above example if V1 is negative.33) (Note that the output waveform becomes “sharper” as R1 C1 decreases.V1 Tb =R1 C1 (proportional to the area under the input pulse) thereafter. The ideal integration expressed by (8. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. which decreases as Vout rises. 8 Operational Ampliﬁer As A Black Box V1 0 V in Tb C1 V1 0 I C1 V1 R1 0 0 V in Tb R1 X Vout V1 R1 Vout − 0 V1 R 1C1 (b) − V1 T b R 1C1 t (a) Figure 8. leading to an increasingly slower voltage variation across C1 . In fact. the voltage across the capacitor and hence Vout remain equal to .32) (8. for a large R1 C1 product. (b) input and output waveforms. On the other hand.cls v. the integrator forces a constant current (equal to V1 =R1 ) through the capacitor. VX = VX . the exponential response of Fig. R 1C Vin dt 1 1 1 = . the RC ﬁlter creates a current equal to Vin .13. 2006] June 30. Denoting the potential of the virtual ground node in Fig.) When Vin returns to zero. forcing the right plate voltage of C1 to fall linearly with time while its left plate is pinned at zero [Fig. Vout 1 R1 C1 s (8.32) occurs because the left plate of C1 is pinned at zero. 8. When the input jumps from 0 to V1 . Vout =R1 . 8.12 (a) Integrator with pulse input. As illustrated in Fig. a constant current equal to V1 =R1 begins to ﬂow through the resistor and hence the capacitor. let us compare the integrator with a ﬁrst-order RC ﬁlter in terms of their step response. We now examine the performance of the integrator for A0 1. we have Vin .

8. 8.1R C : 0 1 1 1 (8.1=RX CX .14 Simple low-pass ﬁlter.38). Determine RX and CX such that this circuit exhibits the same pole as that of the above integrator. Vout = .2 Op-Amp-Based Circuits C1 385 V1 0 V in R1 X Vout V1 R1 0 V1 V in R1 Vout V 1 − V out R1 C1 Figure 8.36) 1 + 1 + 1 R C s . RX CX = A0 + 1R1 C1 : The choice of choice is (8. and V VX = .40) It is as if the op amp “boosts” the value of C1 by a factor of A0 + 1.35) Thus.out : A 0 (8.13 Comparison of integrator with and RC circuit.1 (8. Vin 1 1 A0 A0 revealing that the gain at s = 0 is limited to A0 (rather than inﬁnity) and the pole frequency has moved from zero to sp = A +.37) Such a circuit is sometimes called a “lossy” integrator to emphasize the nonideal gain and pole position.6 Recall from basic circuit theory that the RC ﬁlter shown in Fig. . 2007 at 13:42 385 (1) Sec. Solution From (8.39) (8. An interesting RX = R1 CX = A0 + 1C1 : (8.cls v. 2006] June 30. Example 8.38) RX and CX is arbitrary so long as their product satisﬁes (8.14 contains a pole at . RX Vout CX V in Figure 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.37).

43) Vout = . Vout = .17(a) assuming an ideal op amp. 8.44) At t = 0.15). (8. Figure 8. 2007 at 13:42 386 (1) 386 Chap. 2006] June 30.R1 C1 dVin : dt Example 8. 8 Operational Ampliﬁer As A Black Box Exercise What value of RX is necessary if CX = C1 ? Differentiator If in the general topology of Fig. the circuit acts as a differentiator (and a high-pass ﬁlter).15 Differentiator.16 plots the magnitude of Vout =Vin as a function of frequency. we have R1 C1 V in X Vout Figure 8.9. dt 1 arriving at (8. an impulse of current ﬂows through C1 because the op amp maintains VX constant: Solution Iin = C1 dVin dt (8. 8.cls v. Z1 is a resistor and Z2 a capacitor (Fig.41) (8. From a time-domain perspective. out C1 dVin = . . Vin = 0 and Vout = 0 (why?). 8.45) .R1 C1 s: (8. we can equate the currents ﬂowing through C1 and R1 : Vout Vin R 1 C1 f Figure 8.42) Exhibiting a zero at the origin.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VR .7 Plot the output waveform of the circuit shown in Fig. R1 1 Vin C1 s = .16 Frequency response of differentiator. When Vin jumps to V1 .

Vin returns to zero. generating an output given by (8. the output exhibits neither an inﬁnite height (limited by the supply voltage) nor a zero width (limited by the op amp nonidealities). At current in C1 : (8.46) Vout = . In reality.49) (8.2 Op-Amp-Based Circuits V1 0 387 V in I C1 R1 V1 0 0 Tb C1 V in Tb I in X Vout Vout 0 0 (a) (b) t Figure 8. (b) input and output waveforms. the virtual ground node permits the input to change the voltage across C1 instantaneously. 8.47) (8.18). In the RC ﬁlter. 2006] June 30.50) It follows that Vout = .Iin R1 = .52) We can therefore say that the circuit generates an impulse of current C1 V1 t and “ampliﬁes” it by R1 to produce Vout . . node X is not “pinned.51) (8. = C1 V1 t: The current ﬂows through R1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. of course. on the other hand.R1 C1 V1 t: Figure 8. Exercise Plot the output if V1 is negative. It is instructive to compare the operation of the differentiator with that of its “passive” counterpart (Fig.Iin R1 = R1 C1 V1 t: (8.cls v.” thereby following the input change at t = 0 and limiting the initial current in the circuit to V1 =R1 .17 (a) Differentiator with pulse input.48) t = Tb. In the ideal differentiator. 8. again creating an impulse of Iin = C1 dVin dt = C1 V1 t: (8.17(b) depicts the result. 2007 at 13:42 387 (1) Sec.

VX = VX .55). Solution The capacitor and resistor operate as a voltage divider: Vout = RX Vin RX + 1 CX s X Xs = R RC Cs + 1 : X X (8. CX V in RX Vout RX and Figure 8. 8. R1 V1 0 C1 V in I in X Vout 0 V1 V in C1 X R1 V1 Vout (a) (b) Figure 8.R1C1 s Vin 1 + 1 + R1 C1 s : A0 A0 In contrast to the ideal differentiator. 8 Operational Ampliﬁer As A Black Box If the decay time constant. Equating the capacitor and resistor currents in Fig.56) (8. 2006] June 30. Let us now study the differentiator with a ﬁnite op amp gain.15 gives Vin . 8.54) sp = . A0 + 1 : RC 1 1 (8. is sufﬁciently small.53) Vout = . R1 C1 . the passive circuit can be viewed as an approximation of the ideal differentiator. 2007 at 13:42 388 (1) 388 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vout : 1 R1 C1 s Substituting . the circuit contains a pole at (8.8 Determine the transfer function of the high-pass ﬁlter shown in Fig. we have (8.19 and choose CX such that the pole of this circuit coincides with (8.cls v.57) .19 Simple high-pass ﬁlter.18 Comparison of differentiator and RC circuit.55) Example 8.Vout =A0 for VX .

8. the environmen- 5 The term “mixing” bears a completely different meaning in the RF and wireless industry. in“noise cancelling” headphones.20 Op amp with general network. 2006] June 30. a number of microphones may convert the sounds of various musical instruments to voltages.2 Op-Amp-Based Circuits 389 The circuit therefore exhibits a zero at the origin (s pole to be equal to (8.5 For example. (8. This operation is called “mixing” in the audio industry. For example.60) Exercise What is the necessary value of CX if RX = R1 ? An important drawback of differentiators stems from the ampliﬁcation of high-frequency noise. Unfortunately. such a circuit provides the following transfer function Vout V in Z2 Z1 Figure 8.5 to avoid the sign reversal. Vout = 1 + Z1 . In audio recording.42) and Fig. 8.20.61) if the op amp is ideal. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.59) (8. 2007 at 13:42 389 (1) Sec. and these voltages must then be added to create the overall musical piece.2. . Vin Z2 (8.cls v. 8. this function does not translate to ideal integration or differentiation. The reader may wonder if it is possible to employ a conﬁguration similar to the noninverting ampliﬁer of Fig.1=RX CX . for example.58) A0 + 1 1 RX CX = R1 C1 : One choice of RX and CX is 1 RX = A R+ 1 0 CX = C1 . Shown in Fig. we require = 0) and a pole at .55).4 Voltage Adder The need for adding voltages arises in many applications.9 and its integrator and differentiator descendants operate as inverting circuits. 8.16. As suggested by (8. the increasingly larger gain of the circuit at high frequencies tends to boost noise in the circuit. For this (8. The general topology of Fig. 8. Z1 = R1 and Z2 = 1=C2 s yield a nonideal differentiator (why?).

(8.21 depicts a voltage adder (“summer”) incorporating an op amp.21 Voltage adder.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.RF R1 + R2 : 1 2 For example. 2007 at 13:42 390 (1) 390 Chap. 8 Operational Ampliﬁer As A Black Box tal noise is applied to an inverting ampliﬁer and subsequently added to the signal so as to cancel itself. Figure 8. VX = 0. if R1 .62) V V Vout = . The two currents add at the virtual ground node and ﬂow through RF : RF V1 V2 R1 X R2 Vout Figure 8.Vout : R1 R2 RF That is. With an ideal op amp.cls v. V1 + V2 = . respectively. and R1 and R2 carry currents proportional to V1 and V2 . 2006] June 30.

(8..3. respectively.g.. For example.63) = R2 = R.22(a)]. the diodes remain off and the output voltage remains at zero. This property also proves useful in many applications. 8. Equation (8. “break” the connection between the output of the op amp and its inverting input.3 Nonlinear Functions It is possible to implement useful nonlinear functions through the use of op amps and nonlinear devices such as transistors. It is possible to place a diode around an op amp to form a “precision rectiﬁer. in audio recording it may be necessary to lower the “volume” of one musical instrument for part of the piece. This can be . i.e. e. 8. Now suppose we wish to hold X at zero during negative cycles.. We note that the high gain of the op amp ensures that node X tracks Vin (for both positive and negative cycles).R F V1 + V2 : (8. if the input signal amplitude is less than approximately 0. Let us begin with a unity-gain buffer tied to a resistive load [Fig. This drawback prohibits the use of the circuit in high-precision applications. a circuit that rectiﬁes even very small signals.64) This circuit can therefore add and amplify voltages.e. 8. The behavior of the circuit in the presence of a ﬁnite op amp gain is studied in Problem 31.” i. Extension to more than two voltages is straightforward. The virtual ground property plays an essential role here as well.63) indicates that V1 and V2 can be added with different weightings: RF =R1 and RF =R2 .7 V. if a small signal received by a cellphone must be rectiﬁed to determine its amplitude.1 Precision Rectiﬁer The rectiﬁer circuits described in Chapter 3 suffer from a “dead zone” due to the ﬁnite voltage required to turn on the diodes. a task possible by varying R1 and R2 . That is. then R Vout = .

on so that D1 is barely on. Example 8.9 Plot the waveforms in the circuit of Fig. Note that Vout is sensed at X rather than at the output of the op amp. let us ﬁrst assume that Vin = 0.23 (a) Inverting precision rectiﬁer. R1 carries little current.23(b) shows the resulting waveforms. turning D1 barely on but with little current so that VX 0. (b) circuit waveforms. where D1 is inserted in the feedback loop.cls v. To analyze the operation of this circuit. 2007 at 13:42 391 (1) Sec. VX 0 and VY .on (a) Figure 8. What happens if Vin becomes slightly negative? For Vout to assume a negative value.on . Figure 8. V in D1 R1 X Y V in VY −V D. VY rises further so that the current ﬂowing through D1 and R1 yields Vout Vin . D1 turns off (why?). D1 turns off and the op amp produces a very large negative output (near the negative supply rail) because its noninverting input falls below its inverting input. thus raising the current through R1 .on for positive input cycles.3 Nonlinear Functions 391 accomplished as depicted in Fig. In its attempt to minimize the voltage difference between the noninverting and the inverting inputs.on t V out t (a) (b) (c) Figure 8. 8. (b) t VX t t For Vin = 0. For Vin 0. 2006] June 30. Solution . Now if Vin becomes slightly positive. (b) precision rectiﬁer.22(c) plots the circuit’s waveforms in response to an input sinusoid.VD. 8. the op amp creates VY . V in V in X Vout V in X V out R1 R1 D1 t Y VY V D. which is not possible. Figure 8. and X is a virtual ground. the op amp raises VY to approximately VD1.23(a) in response to an input sinusoid. As Vin becomes positive. That is. VY only slightly decreases to allow D1 to carry the higher current. D1 must carry a current from X to Y . (c) circuit waveforms. even small positive levels at the input appear at the output.VD.22 (a) Simple op amp circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.22(b). Thus. That is. leading to VX = Vin and driving VY to a very positive value. 8.

In the actual circuit. and Vout approaches the negative supply rail. Thus.2 Logarithmic Ampliﬁer Consider the circuit of Fig.3. the emitter voltage must fall below zero to provide a greater collector current.VBE and hence VBE = VT ln Vin =R1 : I S (8. R1 carries a current equal to Vin =R1 and so does Q1 . 8 Operational Ampliﬁer As A Black Box Exercise Repeat the above example for a triangular input that goes from .66) .66) predicts that Vout is not deﬁned. Equation (8. As with previous linear and nonlinear circuits. It may be desirable in such cases to amplify weak signals and attenuate (“compress”) strong signals. Logarithmic ampliﬁers (“logamps”) prove useful in applications where the input signal level may vary by a large factor. Vout = .24 in fact implements the inverse function of the exponential characteristic. The large swings at the output of the op amp in Figs. Additional techniques can resolve this issue (Problem 39).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3. 2007 at 13:42 392 (1) 392 Chap. 2006] June 30. hence a logarithmic dependence. With an ideal op amp.cls v.VT ln R in : I 1 S (8. V in R1 R1 X V in Q1 Vout Figure 8. The effect of ﬁnite op amp gain is studied in Problem 41. 8. Q1 cannot carry a “negative” current. where a bipolar transistor is placed around the op amp. Note that Q1 operates in the active region because both the base and the collector remain at zero.22(b) and 8.24. we surmise that replacing the bipolar transistor with a MOSFET V Vout = . Also. 8. The reader may wonder what happens if Vin becomes negative. the virtual ground plays an essential role here as it guarantees the current ﬂowing through Q1 is xactly proportional to Vin . the loop around the op amp is broken. requiring an increase in VBE . so do the currents ﬂowing through R1 and Q1.2 V to +2 V. 8.24 Logarithmic ampliﬁer.3 Square-Root Ampliﬁer Recognizing that the logarithmic ampliﬁer of Fig.23(a) lower the speed of the circuit as the op amp must “recover” from a saturated value before it can turn D1 on again.66) is to be expected: if Vin rises. It is therefore necessary to ensure Vin remains positive. Since the base is at zero.65) The output is therefore proportional to the natural logarithm of Vin . 8. 8. The negative sign in (8.

4 Op Amp Nonidealities 393 leads to a “square-root” ampliﬁer. In practice. 8. (8. called the input “offset voltage. however. as conceptually shown in Fig.68) 8. As Vin becomes more positive. op amps suffer from other imperfections that may affect the performance signiﬁcantly. 2007 at 13:42 393 (1) Sec.u t If Vin is near zero. Vos .1 DC Offsets The op amp characteristics shown in Fig.4 Op Amp Nonidealities Our study in previous sections has dealt with a relatively idealized op amp model—except for the ﬁnite gain—so as to establish insight. . then Vout remains at . a zero input difference may not give a zero output difference! Illustrated in Fig. VTH : n Cox W R1 L 2Vin (8.25. placing M1 at the edge of conduction. .” Vout Vos V in1 − V in1 Vos (a) (b) (c) Vout Figure 8. In this section. M1 operates in saturation. (b) mismatch between input devices.cls v. 8. With its gate and drain at zero.e. for Vout = 0. 2006] June 30.25 Square-root circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.26 (a) Offset in an op amp.67) v u Vout = .Vout . such a circuit requires that M1 carry a current equal to Vin =R1 : M1 Vout V in R1 X Figure 8. (c) representation of offset. we deal with such nonidealities.4. 8. Vout falls to allow M1 to carry a greater current. V 2 : R1 2 n ox L GS TH (Channel-length modulation is neglected here. i. What causes offset? The internal circuit of the op amp experiences random asymmetries (“mismatches”) during fabrication and packaging.) Since VGS = . Vin = 1 C W V . For example.. the characteristic is “offset” to the right or to the left. 8.2 imply that Vout = 0 if Vin1 = Vin2 . In reality. the input difference must be raised to a certain value. Illustrated in Fig.26(a).VTH . 8.

2 in the presence of op amp offsets. Depicted in Fig. 8. 2007 at 13:42 394 (1) 394 Chap.26(c)].BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Vout = 1 + R1 Vin + Vos : R2 . The same effect occurs for MOSFETs.27. We model the offset by a single voltage source placed in series with one of the inputs [Fig. Why are DC offsets important? Let us reexamine some of the circuit topologies studied in Section 8.26(b). the bipolar transistors sensing the two inputs may display slightly different base-emitter voltages.cls v. 2006] June 30. the noninverting ampliﬁer now sees a total input of Vin + Vos .27 Offset in noninverting ampliﬁer. 8. Since offsets are random and hence can be positive or negative. 8 Operational Ampliﬁer As A Black Box 8. Vos can appear at either input with arbitrary polarity. thereby generating Vos V in R1 R2 Vout Figure 8.

thus incurring accuracy limitations.10 A truck weighing station employs an electronic pressure meter whose output is ampliﬁed by the circuit of Fig.6 Example 8. we recognize that the ﬁrst stage ampliﬁes the offset by a factor of 100. Solution From Fig. If the pressure meter generates 20 mV for every 100 kg of load and if the op amp offset is 2 mV.28 to amplify the signal produced by a microphone. The following example illustrates this point. The second stage 6 The reader can show that placing Vos in series with the inverting input of the op amp yields the same result. generating a dc level of 200 mV at node X (if the microphone produces a zero dc output)..69) In other words. Exercise What offset voltage is required for an accuracy of 1 kg? DC offsets may also cause “saturation” in ampliﬁers. what is the accuracy of the weighing station? Solution An offset of 2 mV corresponds to a load of 10 kg. The targeted gain is 104 so that very low level sounds (i. Example 8. the circuit ampliﬁes the offset as well as the signal. microvolt signals) can be detected. 8.27. We therefore say the station has an error of 10 kg in its measurements.11 An electrical engineering student constructs the circuit shown in Fig. (8. Explain what happens if op amp A1 exhibits an offset of 2 mV.e. 8. 8. .27.

7(a) in a similar manner. now ampliﬁes VX by another factor of 100.20 and Eq. and its gain falls to a small value.9) because the circuits of Figs. the output cannot exceed this value.29(a)].) Exercise Repeat the above example if the second stage has a voltage gain of 10. . 8. where resistor R2 is placed in parallel with C1 . 3 V.61) that the response to this “input” consists of the input itself [the unity term in (8. We can therefore express Vout in the time domain as Vos dt Vout = Vos + R 1C 1 1 0 V = Vos + R os t. The problem of offsets proves quite serious in integrators. DC offsets impact the inverting ampliﬁer of Fig. the circuit integrates the op amp offset. 8. 8. 8.70) (8.5 and 8. 2007 at 13:42 395 (1) Sec. Figure 8. (The problem of offset ampliﬁcation in cascaded stages can be resolved through ac coupling. say.61)]. Even in the presence of an input signal. 1 C1 Zt (8. the second op amp drives its transistors into saturation (for bipolar devices) or triode region (for MOSFETs). Suppose the input is set to zero and Vos is referred to the noninverting input [Fig. Of course. as Vout approaches the positive or negative supply voltages. We now examine the effect of offset on the integrator of Fig.4 Op Amp Nonidealities A1 X 10 k Ω 100 Ω 10 k Ω 100 Ω 395 A2 Vout Figure 8. 8. thereby attempting to generate Vout = 20 V.29(b)]. the circuit of Fig. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.71) where the initial condition across C1 is assumed zero. (8.29(c) are similar at low frequencies: Vout = Vos 1 + R2 : R1 For example. if Vos = 2 mV and R2 =R1 least remains away from saturation. What happens at the output? Recall from Fig.29(c) depicts a modiﬁcation..cls v.10. the transistors in the op amp fail to provide gain and the output saturates [Fig. 8.1 depending on the sign of Vos .29(a) integrates the offset and reaches saturation. 8. 8. We say the second stage is saturated. generating an output that tends to +1 or . This is studied in Problem 49. In other words.28 Two-stage ampliﬁer. Now the effect of Vos at the output is given by (8.61)] and the integral of the input [the second term in (8. If A2 operates with a supply voltage of.

(8. but at .72) = 100. then Vout contains a dc error of 202 mV.

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396 (1)

396

C1

Chap. 8

**Operational Ampliﬁer As A Black Box
**

Vout

R1

VCC Vout

VCC

V os

VEE

t

(a)

(b)

R2 C1 R1 Vout V in V os R1

R2 C1

Vout

(c)

(d)

Figure 8.29 (a) Offset in integrator, (b) output waveform, (c) addition of R2 to reduce effect of offset, (d) determination of transfer function.

How does R2 affect the integration function? Disregarding Vos , viewing the circuit as shown in Fig. 8.29(d), and using (8.27), we have

1 Vout = , R2 (8.73) Vin R1 R2 C1 s + 1 : Thus, the circuit now contains a pole at ,1=R2 C1 rather than at the origin. If the input signal frequencies of interest lie well above this value, then R2 C1 s 1 and Vout = , 1 : (8.74) Vin R1 C1 s That is, the integration function holds for input frequencies much higher than 1=R2 C1 . Thus, R2 =R1 must be sufﬁciently small so as to minimize the ampliﬁed offset given by (8.72) whereas R2 C1 must be sufﬁciently large so as to negligibly impact the signal frequencies of interest.

8.4.2 Input Bias Current Op amps implemented in bipolar technology draw a base current from each input. While relatively small ( 0:1-1 A), the input bias currents may create inaccuracies in some circuits. As shown in Fig. 8.30, each bias current is modeled by a current source tied between the corresponding input and ground. Nominally, IB 1 = IB 2 . Let us study the effect of the input currents on the noninverting ampliﬁer. As depicted in Fig. 8.31(a), IB 1 has no effect on the circuit because it ﬂows through a voltage source. The current IB2 , on the other hand, ﬂows through R1 and R2 , introducing an error. Using superposition and setting Vin to zero, we arrive at the circuit in Fig. 8.31(b), which can be transformed to that in Fig. 8.31(c) if IB 2 and R2 are replaced with their Thevenin equivalent. Interestingly, the circuit now resembles the inverting ampliﬁer of Fig. 8.7(a), thereby yielding

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397 (1)

Sec. 8.4

Op Amp Nonidealities

397

V in1 V in2 Vout I B1 I B2

Figure 8.30 Input bias currents.

Vout V in I B1 I B2

(a)

Vout I B1 X I B2

(b)

R1 R2

R1 R2

Vout R2

− I B2 R 2 (c) Figure 8.31 (a) Effect of input bias currents on noninverting ampliﬁer, (b) simpliﬁed circuit, (c) Thevenin equivalent.

R1

R
Vout = ,R2 IB2 , 1

= R1 IB2

R2

(8.75) (8.76)

if the op amp gain is inﬁnite. This expression suggests that IB 2 ﬂows only through R1 , an expected result because the virtual ground at X in Fig. 8.31(b) forces a zero voltage across R2 and hence a zero current through it. The error due to the input bias current appears similar to the DC offset effects illustrated in Fig. 8.27, corrupting the output. However, unlike DC offsets, this phenomenon is not random; for a given bias current in the bipolar transistors used in the op amp, the base currents drawn from the inverting and noninverting inputs remain approximately equal. We may therefore seek a method of canceling this error. For example, we can insert a corrective voltage in series with the noninverting input so as to drive Vout to zero (Fig. 8.32). Since Vcorr “sees” a noninverting ampliﬁer, we have

**R Vout = Vcorr 1 + R1 + IB2 R1 : 2
**

For Vout

(8.77)

= 0,

Vcorr = ,IB2 R1 jjR2 :

(8.78)

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Vcorr

Chap. 8

Operational Ampliﬁer As A Black Box

Vout = 0 X I B2 R1 R2

Figure 8.32 Addition of voltage source to correct for input bias currents.

A bipolar op amp employs a collector current of 1 mA in each of the input devices. If = 100 and the circuit of Fig. 8.32 incorporates R2 = 1 k , R1 = 10 k , determine the output error and the required value of Vcorr . We have IB

Example 8.12

Solution

= 10 A and hence

Vout = 0:1 mV:

Thus, Vcorr is chosen as

(8.79)

Vcorr = ,9:1 V:

(8.80)

Exercise

Determine the correction voltage if

= 200.

Equation (8.78) implies that Vcorr depends on IB 2 and hence the current gain of transistors. Since varies with process and temperature, Vcorr cannot remain at a ﬁxed value and must “track” . Fortunately, (8.78) also reveals that Vcorr can be obtained by passing a base current through a resistor equal to R1 jjR2 , leading to the topology shown in Fig. 8.33. Here, if IB 1 = IB2 , then Vout = 0 for Vin = 0. The reader is encouraged to take the ﬁnite gain of the op amp into account and prove that Vout is still near zero.

R1 V in R2 I B1 Vout I B2 R1 R2

Figure 8.33 Correction for variation of beta.

From the drawing in Fig. 8.31(b), we observe that the input bias currents have an identical effect on the inverting ampliﬁer. Thus, the correction technique shown in Fig. 8.33 applies to this circuit as well.

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399 (1)

Sec. 8.4

Op Amp Nonidealities

399

In reality, asymmetries in the op amp’s internal circuitry introduce a slight (random) mismatch between IB 1 and IB 2 . Problem 53 studies the effect of this mismatch on the output in Fig. 8.33. We now consider the effect of the input bias currents on the performance of integrators. Illustrated in Fig. 8.34(a) with Vin = 0 and IB 1 omitted (why?), the circuit forces IB 2 to ﬂow through C1 because R1 sustains a zero voltage drop. In fact, the Thevenin equivalent of R1 and IB2 [Fig. 8.34(b)] yields

C1 C1 R1 Vout

− I B2 R 1

R1 Vout

I B2

(a) (b)

Figure 8.34 (a) Effect of input bias currents on integrator, (b) Thevenin equivalent.

Vout = , R 1C

Z

= + R 1C IB2 R1 dt

B = IC 2 dt:

1 1 1

1 1

Vin dt

(8.81) (8.82) (8.83)

(Of course, the ﬂow of IB 2 through C1 leads to the same result.) In other words, the circuit integrates the input bias current, thereby forcing Vout to eventually saturate near the positive or negative supply rails. Can we apply the correction technique of Fig. 8.33 to the integrator? The model in Fig. 8.34(b) suggests that a resistor equal to R1 placed in series with the noninverting input can cancel the effect. The result is depicted in Fig. 8.35.

C1 V in R1 Vout R1

Figure 8.35 Correction for input currents in an integrator.

Example 8.13

An electrical engineering student attempts the topology of Fig. 8.35 in the laboratory but observes that the output still saturates. Give three possible reasons for this effect.

Solution

First, the DC offset voltage of the op amp itself is still integrated (Section 8.4.1). Second, the two input bias currents always suffer from a slight mismatch, thus causing incomplete cancellation. Third, the two resistors in Fig. 8.35 also exhibit mismatches, creating an additional error.

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400 (1)

400

Chap. 8

Operational Ampliﬁer As A Black Box

Exercise

Is resistor R1 necessary if the internal circuitry of the op amp uses MOS devices?

The problem of input bias current mismatch requires a modiﬁcation similar to that in Fig. 8.29(c). The mismatch current then ﬂows through R2 rather than through C1 (why?). 8.4.3 Speed Limitations Finite Bandwidth Our study of op amps has thus far assumed no speed limitations. In reality, the internal capacitances of the op amp degrade the performance at high frequencies. For example, as illustrated in Fig. 8.36, the gain begins to fall as the frequency of operation exceeds f1 . In this chapter, we provide a simple analysis of such effects, deferring a more detailed study to Chapter 11.

Av A0

1

f1

fu

f

Figure 8.36 Frequency response of an op amp.

To represent the gain roll-off shown in Fig. 8.36, we must modify the op amp model offered in Fig. 8.1. As a simple approximation, the internal circuitry of the op amp can be modeled by a ﬁrst-order (one-pole) system having the following transfer function:

Vout A0 Vin1 , Vin2 s = 1 + s ; !1

(8.84)

where !1 = 2f1 . Note that at frequencies well below !1 , s=!1 1 and the gain is equal to A0 . At very high frequencies, s=!1 1, and the gain of the op amp falls to unity at !u = A0 !1 .

This frequency is called the “unity-gain bandwidth” of the op amp. Using this model, we can reexamine the performance of the circuits studied in the previous sections. Consider the noninverting ampliﬁer of Fig. 8.5. We utilize Eq. (8.11) but replace A0 with the above transfer function:

Vout s = Vin 1+

A0 : R1 + R2 + 1 + s !1 R2

1

s 1+ !

A0

(8.85)

Multiplying the numerator and the denominator by 1 + s=!1 gives

Vout s = A0 s + R2 A + 1 : Vin !1 R1 + R2 0

(8.86)

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401 (1)

Sec. 8.4

Op Amp Nonidealities

401

The system is still of ﬁrst order and the pole of the closed-loop transfer function is given by

j!p;closed j = 1 + R R2 R A0 !1 : 1+ 2

(8.87)

As depicted in Fig. 8.37, the bandwidth of the closed-loop circuit is substantially higher than that of the op amp itself. This improvement, of course, accrues at the cost of a proportional reduction in gain—from A0 to 1 + R2 A0 =R1 + R2 .

Av A0 A0

(1+ Op Amp Frequency Response Noninverting Amplifier Frequency Response

R2 A ) R 1+ R 2 0 1

f1

(1+

fu R2 A )f R 1+ R 2 0 1

f

Figure 8.37 Frequency response of (a) open-loop op amp and (b) closed-loop circuit.

Example 8.14

A noninverting ampliﬁer incorporates an op amp having an open-loop gain of 100 and bandwidth of 1 MHz. If the circuit is designed for a closed-loop gain of 16, determine the resulting bandwidth and time constant. For a closed-loop gain of 16, we require that 1 + R1 =R2

Solution

j!p;closed j = 1 + R R2 R A0 !1 1+ 2

= 16 and hence

1 0 C B = B1 + R 1 A0 C !1 A @ 1 +1

= 2 635 MHz:

(8.88)

(8.89)

R2

(8.90)

Given by j!p;closed j,1 , the time constant of the circuit is equal to 2.51 ns.

Exercise

Repeat the above example if the op amp gain is 500.

The above analysis can be repeated for the inverting ampliﬁer as well. The reader can prove that the result is similar to (8.87). The ﬁnite bandwidth of the op amp may considerably degrade the performance of integrators. The analysis is beyond the scope of this book, but it is outlined in Problem 57 for the interested reader.

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402

Chap. 8

Operational Ampliﬁer As A Black Box

Another critical issue in the use of op amps is stability; if placed in the topologies seen above, some op amps may oscillate. Arising from the internal circuitry of the op amp, this phenomenon often requires internal or external stabilization, also called “frequency compensation.” These concepts are studied in Chapter 12. Slew Rate In addition to bandwidth and stability problems, another interesting effect is observed in op amps that relates to their response to large signals. Consider the noninverting conﬁguration shown in Fig. 8.38(a), where the closed-loop transfer function is given by (8.86). A small step of V at the input thus results in an ampliﬁed output waveform having a time constant equal to j!p;closed j,1 [Fig. 8.38(b)]. If the input step is raised to 2V , each point on the output waveform also rises by a factor of two.7 In other words, doubling the input amplitude doubles both the output amplitude and the output slope.

V in t V in Vout V in R2 R1 V out

∆V

2 ∆V

t

V out

Ramp

Linear Settling

t t (a) (b) (c) Figure 8.38 (a) Noninverting ampliﬁer, (b) input and output waveforms in linear regime, (c) input and output waveforms in slewing regime.

In reality, op amps do not exhibit the above behavior if the signal amplitudes are large. As illustrated in Fig. 8.38(c), the output ﬁrst rises with a constant slope (i.e., as a ramp) and eventually settles as in the linear case of Fig. 8.38(b). The ramp section of the waveform arises because, with a large input step, the internal circuitry of the op amp reduces to a constant current source charging a capacitor. We say the op amp “slews” during this time. The slope of the ramp is called the “slew rate” (SR). Slewing further limits the speed of op amps. While for small-signal steps, the output response is determined by the closed-loop time constant, large-signal steps must face slewing prior to linear settling. Figure 8.39 compares the response of a non-slewing circuit with that of a slewing op amp, revealing the longer settling time in the latter case. It is important to understand that slewing is a nonlinear phenomenon. As suggested by the waveforms in Fig. 8.38(c), the points on the ramp section do not follow linear scaling (if x ! y , then 2x 6! 2y ). The nonlinearity can also be observed by applying a large-signal sine wave to the circuit of Fig. 8.38(a) and gradually increasing the frequency (Fig. 8.40). At low frequencies, the op amp output “tracks” the sine wave because the maximum slope of the sine wave remains less than the op amp slew rate [Fig. 8.40(a)]. Writing Vin t = V0 sin !t and Vout t = V0 1 + R1 =R2 sin !t, we observe that

7 Recall that in a linear system, if xt ! yt, then 2xt ! 2yt.

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403 (1)

Sec. 8.4

Op Amp Nonidealities

403

V in

t

Without Slewing

V out

With Slewing

t

Figure 8.39 Output settling speed with and without slewing.

Vout V in R2 R1

V in

Vout

t

(a)

(b)

V in t1

Vout

t2

(c)

t

Figure 8.40 (a) Simple noninverting ampliﬁer, (b) input and output waveforms without slewing, (c) input and output waveforms with slewing.

dVout = V 1 + R1 ! cos !t: 0 dt R2

(8.91)

The output therefore exhibits a maximum slope of V0 ! 1 + R1 =R2 (at its zero crossing points), and the op amp slew rate must exceed this value to avoid slewing. What happens if the op amp slew rate is insufﬁcient? The output then fails to follow the sinusoidal shape while passing through zero, exhibiting the distorted behavior shown in Fig. 8.40(b). Note that the output tracks the input so long as the slope of the waveform does not exceed the op amp slew rate, e.g., between t1 and t2 .

Example 8.15

The internal circuitry of an op amp can be simpliﬁed to a 1-mA current source charging a 5-pF capacitor during large-signal operation. If an ampliﬁer using this op amp produces a sinusoid with a peak amplitude of 0.5 V, determine the maximum frequency of operation that avoids slewing.

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404 (1)

404

Chap. 8

Operational Ampliﬁer As A Black Box

The slew rate is given by I=C = 0:2 V/ns. For an output given by Vout Vp = 0:5 V, the maximum slope is equal to

Solution

= Vp sin !t, where

(8.92)

dVout j = V !: dt max p

Equating this to the slew rate, we have

! = 263:7 MHz:

(8.93)

That is, for frequencies above 63.7 MHz, the zero crossings of the output experience slewing.

Exercise

Plot the output waveform if the input frequency is 200 MHz.

R1 =R2 . To deﬁne the maximum sinusoidal frequency that remains free from slewing, it is common to assume the worst case, namely, when the op amp produces its maximum allowable voltage swing without saturation. As exempliﬁed by Fig. 8.41, the largest sinusoid permitted at the output is given by

VDD V in1 V in2 Vout V min

0

Equation (8.91) indicates that the onset of slewing depends on the closed-loop gain,

1+

VDD V max

Figure 8.41 Maximum op amp output swings.

Vout = Vmax , Vmin sin !t + Vmax + Vmin ; 2 2

(8.94)

where Vmax and Vmin denote the bounds on the output level without saturation. If the op amp provides a slew rate of SR, then the maximum frequency of the above sinusoid can be obtained by writing

dVout j = SR dt max

and hence

(8.95)

!FP = VmaxSRVmin : ,

2

(8.96)

Called the “full-power bandwidth,” !FP serves as a measure of the useful large-signal speed of the op amp.

BR

Wiley/Razavi/Fundamentals of Microelectronics

[Razavi.cls v. 2006]

June 30, 2007 at 13:42

405 (1)

Sec. 8.4

Op Amp Nonidealities

405

8.4.4 Finite Input and Output Impedances Actual op amps do not provide an inﬁnite input impedance8 or a zero output impedance—the latter often creating limitations in the design. We analyze the effect of this nonideality on one circuit here. Consider the inverting ampliﬁer shown in Fig. 8.42(a), assuming the op amp suffers from an output resistance, Rout . How should the circuit be analyzed? We return to the model in Fig. 8.1 and place Rout in series with the output voltage source [Fig. 8.42(b)]. We must solve the circuit in the presence of Rout . Recognizing that the current ﬂowing through Rout is equal to ,A0 vX , vout =Rout , we write a KVL from vin to vout through R2 and R1 :

R1 R2 X Vout V in v in

− A 0v X

R1 R2 X R out v out

(a)

(b)

Figure 8.42 (a) Inverting ampliﬁer, (b) effect of ﬁnite output resistance of op amp.

**vin + R1 + R2 ,A0 vX , vout = vout : R
**

out

To construct another equation for vX , we view R1 and R2 as a voltage divider:

(8.97)

**vX = R R2 R vout , vin + vin : 1+ 2
**

Substituting for vX in (8.97) thus yields

(8.98)

**A0 , Rout vout = , R1 R1 vin R2 1 + Rout + A0 + R1 : R R
**

2 2

(8.99)

The additional terms ,Rout =R1 in the numerator and Rout =R2 in the denominator increase the gain error of the circuit. An electrical engineering student purchases an op amp with A0 = 10; 000 and Rout = 1 and constructs the ampliﬁer of Fig. 8.42(a) using R1 = 50 and R2 = 10 . Unfortunately, the circuit fails to provide large voltage swings at the output even though Rout =R1 and Rout =R2 remain much less than A0 in (8.99). Explain why. For an output swing of, say, 2 V, the op amp may need to deliver a current as high as 40 mA to R1 (why?). Many op amps can provide only a small output current even though their small-signal output impedance is very low.

Example 8.16

Solution

8 Op amps employing MOS transistors at their input exhibit a very high input impedance at low frequencies.

BR

Wiley/Razavi/Fundamentals of Microelectronics

[Razavi.cls v. 2006]

June 30, 2007 at 13:42

406 (1)

406

Chap. 8

Operational Ampliﬁer As A Black Box

Exercise

If the op amp can deliver a current of 5 mA, what value of R1 is acceptable for output voltages as high as 1 V?

8.5 Design Examples

Following our study of op amp applications in the previous sections, we now consider several examples of the design procedure for op amp circuits. We begin with simple examples and gradually proceed to more challenging problems. Design an inverting ampliﬁer with a nominal gain of 4, a gain error of 0:1, and an input impedance of at least 10 k . Determine the minimum op amp gain required here. For an input impedance of 10 k , we choose the same value of R2 in Fig. 8.7(a), arriving at R1 = 40 k for a nominal gain of 4. Under these conditions, Eq. (8.21) demands that

Example 8.17

Solution

1 R1 A0 1 + R2

and hence

For a gain error of 1%. Determine the required open-loop gain and bandwidth of the op amp. 8. we may select R1 = 4 k and R2 = 1 k and check the gain error from (8.9).100) A0 5000: (8.2 A.102) 1 R1 A0 1 + R2 . R1 = 4: R2 (8. Example 8.99) at the end.18 Solution From Fig. closed-loop bandwidth = 50 MHz. we have The choice of R1 and R2 themselves depends on the “driving capability” (output resistance) of the op amp.101) Exercise Repeat the above example for a nominal gain of 8 and compare the results. Assume the op amp has an input bias current of 0. gain error = 1. Design a noninverting ampliﬁer for the following speciﬁcations: closed-loop gain = 5. 0:1 (8.5 and Eq. For example. (8.

103) . 1 (8.

105) (8.19 Design an integrator for a unity-gain frequency of 10 MHz and an input impedance of 20 k . such a small capacitor value may prove impractical.108) = 20 k . If the op amp provides a slew rate of 0.112) . Exercise Repeat the above example for a gain error of 2 and compare the results.1 V/ns.110) dVout j = 1 V : dt max R1 C1 p Equating this result to 0.106) (8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 Design Examples 407 and hence A0 500: Also.1 A0 2 250 MHz : 100 (8.1 V/ns gives (8. 2006] June 30. C1 = 0:796 pF: (In discrete design.29). Example 8.104) !1 !1 !p. the op amp must provide an open-loop bandwidth of at least 500 kHz. we have R1 C1 2 10 MHz = 1 and.109) 1 Vout = R. 2007 at 13:42 407 (1) Sec. 8.C Vp sin !t.111) Vp = 1:59 V: (8.closed R 1 + 1 + R1 .) For an input given by Vin = Vp cos !t. (8.107) Thus. the open-loop bandwidth is given by (8. 1 1 ! with a maximum slope of (8. with R1 1 (8.cls v.closed 1 + R R2 R A0 1+ 2 !p. from (8.87). what is the largest peak-to-peak sinusoidal swing at the input at 1 MHz that produces an output free from slewing? Solution From (8.

8 Operational Ampliﬁer As A Black Box In other words. an op amp producing a moderate output swing requires only a very small input difference. Exercise How do the above results change if the op amp provides a slew rate of 0. i. Actual op amps exhibit “nonlinear” characteristics. These effects impact the performance of various circuits. Due to its high voltage gain. 500 for 1 V jVout j 2 V. for large signals. the voltage gain may be equal to 1000 for . the input peak-to-peak swing at 1 MHz must remain below 3. and close to zero for jVout j 2 V. Placing a bipolar device around an op amp provides a logarithmic function. differentiators are less common than integrators. the circuit operates as an integrator.. An inverting conﬁguration using multiple input resistors tied to the virtual ground node can serve as a voltage adder. 2007 at 13:42 408 (1) 408 Chap. Op amps suffer from various imperfections.e. The noninverting ampliﬁer topology exhibits a nominal gain equal to one plus the ratio of two resistors.. The inverting ampliﬁer conﬁguration provides a nominal gain equal to the ratio of two resistors. (a) Plot the input/output characteristic of this op amp.e.5 V/ns? 8. distorting the output waveform.” If the feedback resistor in an inverting conﬁguration is replaced with a capacitor.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.18 V for the output to be free from slewing.cls v. The speed of op amp circuits is limited by the bandwidth of the op amps. the op amp suffers from a ﬁnite slew rate. Also. nonlinearity)? . 2006] June 30. (b) What is the largest input swing that the op amp can sense without producing “distortion” (i. most notably. Placing a diode around an op amp leads to a precision rectiﬁer. Due to their higher noise. For example. If the input resistor in an inverting conﬁguration is replaced with a capacitor. including dc offsets and input bias currents. With the noninverting input of the op amp tied to ground. The circuit also suffers from a gain error that is inversely proportional to the gain of the op amp. a circuit that can rectify very small input swings. the circuit acts as a differentiator. Problems 1. Its gain error is the same as that of the noninverting conﬁguration. Integrator ﬁnd wide application in analog ﬁlters and analog-todigital converters.1 V Vout +1 V. integrators. the inverting input also remains close to the ground potential ans is thus called a “virtual ground.6 Chapter Summary An op amp is a circuit that provides a high voltage gain and an output proportional to the difference between two inputs.

A noninverting ampliﬁer must provide a nominal gain of 4 with a gain error of 0:1.11). determine the gain error if A0 drops to 0:6A0 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8.45. Compute the minimum required op amp gain.43 What happens if A0 ! 1? 7. an adventurous student decides that it is possible to achieve a zero gain error with a ﬁnite A0 if R2 =R1 + R2 is slightly adjusted from its nominal value. (a) Suppose a nominal closed-loop gain of 1 is required.43. resistor R2 deviates from its nominal value V in1 A0 V in V in2 R1 R2 Vout Figure 8.45 . Vin2 : (8. 8. 2007 at 13:42 409 (1) Sec.44. determine the closed-loop gain and input impedance. What happens if A0 ! 1? 8. compute the closed-loop gain and output R out Vout V in1 V in2 A 0 (V in1 − V in2 ) Figure 8. Determine the gain error. In the noninverting ampliﬁer shown in Fig. An op amp exhibits the following nonlinear characteristic: Vout = tanh Vin1 . 5. Representing the op amp as depicted in Fig.cls v.6 Chapter Summary 409 2. Vin2 0. 2006] June 30.44 impedance. A noninverting ampliﬁer employs an op amp having a nominal gain of 2000 to achieve a nominal closed-loop gain of 8. How should R2 =R1 + R2 be chosen? (b) With the value obtained in (a). Modeling the op amp as shown in Fig. Looking at Equation (8. A noninverting ampliﬁer employs an op amp with a ﬁnite output impedance. 8. Sketch this characteristic and determine the small-signal gain of the op amp in the vicinity of Vin1 . 8. 4. 6. Vout V in1 V in2 R in A 0 (V in1 − V in2 ) Figure 8. A noninverting ampliﬁer incorporates an op amp having an input impedance of Rin . Rout .113) 3.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The op amp used in an inverting ampliﬁer exhibits a ﬁnite input impedance.47 divided by the change in W . Suppose this op amp is used in a noninverting ampliﬁer with a nominal gain of 5. Figure 8. The input/output characteristic of an op amp can be approximated by the piecewise-linear behavior illustrated in Fig.. Plot the closed-loop input/output characteristic of the circuit.8A 0 −4 mV −2 mV A0 +2 mV +4 mV V in1 − V in2 Figure 8.48 12. An inverting ampliﬁer must provide a nominal gain of 8 with a gain error of 0:2.43. Also. (Note that the closed-loop gain experiences much less variation. Determine the gain of the system. 8. 8. Calculate the closed-loop gain of the noninverting ampliﬁer shown in Fig. 13. Suppose RS plays the role of R2 in the noninverting ampliﬁer (Fig.48 if A0 Verify that the result reduces to expected values if R1 ! 0 or R3 ! 0. Calculate the gain error of the circuit if R=R2 1. where the gain drops from A0 to 0:8A0 and eventually to Vout 0. 2006] June 30. Vin = 1 V. Rin . 11. 9.46. 2007 at 13:42 410 (1) 410 Chap. Vin2 j increases.cls v. and W the weight of each truck. A0 V in R1 R2 R3 R4 Vout = 1. a proportionality factor. the closed-loop circuit is much more linear. determine the closed-loop gain and input impedance.47). . Determine the minimum required op amp gain. A truck weighing station incorporates a sensor whose resistance varies linearly with the weight: RS = R0 + W .46 zero as jVin1 . i.e. Modeling the op amp as shown in Fig. deﬁned as the change in Vout Vin =1 V A0 R1 Vout RS Figure 8. 8.) 10. 8 Operational Ampliﬁer As A Black Box by R. Here R0 is a constant value. 8.

6 Chapter Summary 411 14. An inverting ampliﬁer is designed for a nominal gain of 8 and a gain error of 0:1 using an op amp that exhibits an output impedance of 2 k . 2007 at 13:42 411 (1) Sec. The integrator of Fig. Figure 8. 21. determine the required gain of the op amp. 2006] June 30.51 senses an input signal given by Vin C1 R1 V in A0 Vout = V0 sin !t. 8. 8. 15.49.44. An inverting ampliﬁer must provide an input impedance of approximately 10 k and a nominal gain of 4. calculate the required open-loop gain of the op amp. respectively. If the input impedance of the circuit must be equal to approximately 1 k .50 if A0 R1 R2 X A0 V in Vout R4 R3 = 1. Determine the Figure 8. If the values of R1 and C1 are limited to 10 k and 1 nF. Modeling the op amp as depicted in Fig.50 19. Verify that the result reduces to expected values if R1 ! 0 or R3 ! 0. R3 R1 R4 R2 Vout V in Figure 8.49 18. compute the frequency of the sinusoid. An inverting ampliﬁer employs an op amp having an output impedance of Rout . Assuming A0 = 1. The integrator of Fig.51 is used to amplify a sinusoidal input by a factor of 10. 8. 8. 20.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.51 must provide a pole at no higher than 1 Hz. If the op amp exhibits an open-loop gain of 1000 and an output impedance of 1 k . . The integrator of Fig. compute the closed-loop gain and output impedance. 16. determine the gain error. Determine the closed-loop gain of the circuit depicted in Fig. 17.cls v. 8. 8. If A0 = 1 and R1 C1 = 10 ns. 8.51 output signal amplitude if A0 = 1. compute the closed-loop gain of the inverting ampliﬁer shown in Fig.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Plot Vout as a function of time if V1 = RF V1 V2 R2 X R1 A0 Vout Figure 8.54.52 is used to amplify a sinusoidal input at a frequency of 1 MHz R1 C1 V in A0 Vout Figure 8. If the values of R1 and C1 cannot be lower than 1 k and 1 nF. 8.51 exhibits a ﬁnite output impedance and is modeled as depicted in Fig.cls v.52 25. 8. Compute the transfer function Vout =Vin and compare the location of the pole with that given by Eq. (8. 27. compute the required gain of the op amp. Consider the voltage adder shown in Fig. Calculate the transfer function of the circuit shown in Fig. Repeat Problem 28 if A0 1. 28.44. Consider the integrator shown in Fig. Determine the transfer function Vout =Vin and compare the result with Eq. 8. 8.52 exhibits a ﬁnite input impedance and is modeled as shown in Fig.37).53 if A0 = 1. What choice of component values reduces jVout =Vin j to unity at all frequencies? R2 C1 C2 V in R1 A0 Vout Figure 8.43.43. 8. (8. determine the value of R1 C1 .52 for a pole frequency of 100 MHz. 8. 26. Compute the transfer function and compare the result with Eq.42). 2007 at 13:42 412 (1) 412 Chap. by a factor of 5. 8 Operational Ampliﬁer As A Black Box 22. 23. We wish to design the differentiator of Fig. (8. Can the resistors and capacitors be chosen so as to reduce jVout =Vin j to approximately unity? 30.57).42). If A0 = 1. Assume R1 = R2 and A0 = 1.54 V0 sin !t and V2 = V0 sin3!t. Determine the transfer function Vout =Vin and compare the location of the pole with that given by Eq. The differentiator of Fig.52 suffers from a ﬁnite output impedance and is modeled as depicted in Fig. 8. . 24. The op amp used in the differentiator of Fig. Suppose the op amp in Fig. 8.44. The op amp used in the integrator of Fig. 8. 8.51 and suppose the op amp is modeled as shown in Fig. (8. respectively. 8. 2006] June 30. 8.53 29.

6 Chapter Summary 413 31.55. 8. With the aid of the op amp model shown in Fig. 2007 at 13:42 413 (1) Sec. 8. 8.55 also represent the input impedance of the op amp.22(b) by connecting a diode from node Y to ground. 40. Explain how this can be accomplished. Rout . 35. Due to a manufacturing error. Plot VX and VY as a function of time in response to a sinusoidal input.54 suffers from a ﬁnite gain. 37. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 8. Vout . compute Vout in terms of V1 and V2 . 2006] June 30.24 varies from . Plot the current ﬂowing through D1 in the precision rectiﬁer of Fig. Suppose Vin in Fig. Plot VY . (Note that RP can RF V1 V2 R2 X R1 A0 RP Vout Figure 8.1 V to +1 V. . Calculate Vout in terms of V1 and V2 . Consider the voltage adder illustrated in Fig. 8. Figure 8. 8.57 current ﬂowing through D1 as a function of time for a sinusoidal input.) 33. 8.56 op amp exhibits a ﬁnite input impedance.56.cls v. 34. 32. Consider the precision rectiﬁer depicted in Fig. determine Vout in terms of V1 and V2 .58. where RP is a parasitic resistance and the R F V1 V2 R2 X R1 A0 RP Vout Figure 8. Calculate Vout in terms of V1 and V2 for A0 = 1 and A0 1. 38. Use a constant-voltage model for the diode. 8. Sketch Vout and VX as a function of Vin if the op amp is ideal.54 employs an op amp having a ﬁnite output impedance. 8.57 shows a precision rectiﬁer producing negative cycles. Plot the current ﬂowing through D1 in the precision rectiﬁer of Fig. a parasitic resistance RP has appeared in the adder of Fig. where a parasitic resistor RP has appeared in parallel with D1 .23(a) as a function of time for a sinusoidal input.22(b) as a function of time for a sinusoidal input.43. Using the op amp model depicted in Fig. 8. We wish to improve the speed of the rectiﬁer shown in Fig.44. The voltage adder of Fig. 36. 8. 39. The op amp in Fig. and the V in X V out R1 D1 Y Figure 8.

A student attempts to construct a noninverting logarithmic ampliﬁer as illustrated in Fig.59 43. (a) Determine the required values of IS and R1 . Calculate Vout . 8.61. 2006] June 30.cls v.1 V to .60 can be considered a “true” square-root ampliﬁer. 8 Operational Ampliﬁer As A Black Box Y D1 R1 RP Figure 8. 8. 44. 8. Suppose the gain of the op amp in Fig. Plot the magnitude of the gain as a function of Vin and explain why the circuit is said to provide a “compressive” characteristic. Determine the input/output characteristic of the circuit. Determine the small-signal voltage gain of the logarithmic ampliﬁer depicted in Fig. 46. 8. . Describe the operation of this circuit. 2007 at 13:42 414 (1) 414 V in X V out Chap. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.58 41.24 by differentiating both sides of (8. 42. 47. In the noninverting ampliﬁer of Fig.28 suffers from an input offset of 3 mV. Calculate Vout in terms of Vin for the circuit shown in Fig.24 is ﬁnite. The logarithmic ampliﬁer of Fig. 8. Deter- R1 X V in V TH M1 Vout Figure 8. (b) Calculate the small-signal voltage gain at the two ends of the range. 45.66) with respect to Vin .59. Q1 Vout V in R1 X Figure 8.62.24 must “map” an input range of 1 V to 10 V to an output range of . Suppose each op amp in Fig. the op amp offset is represented by a voltage source in series with the inverting input. 8. 8.60 mine Vout in terms of Vin and compute the small-signal gain by differentiating the result with respect to Vin . Determine the maximum offset error in Vout if each ampliﬁer is designed for a gain of 10. 48. The circuit illustrated in Fig.1:5 V.

An inverting ampliﬁer incorporates an op amp whose frequency response is given by Eq.31 incur a small offset. 8. input offset of Vos . (a) A0 = 500. 56.63. Figure 8. 2007 at 13:42 415 (1) Sec.64 shows an integrator employing an op amp whose frequency response is given by As = A0 s : 1+ ! 0 (8.6 Chapter Summary 415 R1 X V in M1 Vout Figure 8. f1 = 50 Hz.. Determine the required values of R1 and R2 if C1 100 pF. Suppose the input bias currents in Fig. calculate Vout if the op amp exhibits an R1 R2 A0 V in Vout Figure 8.84). (8. Explain the effect of op amp offset on the output of a logarithmic ampliﬁer. 8. Assume A0 = 1. 57. The integrator of Fig. 53.e. 55. 52. V ? A noninverting ampliﬁer must provide a bandwidth of 100 MHz with a nominal gain of 4. Determine which one of the following op amp speciﬁcations are adequate: (a) A0 = 1000. What is the maximum allowable value of R1 jjR2 if the output error due to this mismatch must remain below a certain value.63 50. 8. Explain why dc offsets are not considered a serious issue in differentiators.29(c) must operate with frequencies as low as 1 kHz while providing an output offset of less than 20 mV with an op amp offset of 3 mV. 8. 54. f1 = 1 MHz. 2006] June 30.62 49. Calculate Vout . For the inverting ampliﬁer illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Repeat Problem 53 for the circuit shown in Fig.cls v. i.114) . IB 1 = IB 2 + I . 8.33. 51. Determine the transfer function of the closed-loop circuit and compute the bandwidth.61 A0 V in R1 V OS R2 Vout Figure 8.

65 V.2 at Vin = 2 V? Assume the gain of the op amp is sufﬁciently high. Assume the largest available capacitor is 50 pF. Design Problems 60. Design an integrator whose step response approximates V t = t with an error less than 0:1 for the range 0 V t V0 (Fig. 8. 8. where 1 = .0:5 V . and a total resistance of 20 k . the step response of an integrator is a slow exponential rather than an ideal ramp.65).5 V. 8 Operational Ampliﬁer As A Black Box Determine the transfer function of the overall integrator. 66. Simplify the result if 1=R1 C1 . 1 V . Assume = 10 V=s. C1 R1 Vout V in A (s ( !0 Figure 8. 2007 at 13:42 416 (1) 416 Chap. V0 = 1 V0 lR am p ∆V ∆V = 0. a gain error of 0:2. With a ﬁnite op amp gain. A noninverting ampliﬁer with a nominal gain of 4 senses a sinusoid having a peak amplitude of 0. SPICE Problems . The unity-gain buffer of Fig. 2006] June 30. Design an integrator that attenuates input frequencies above 100 kHz and exhibits a pole at 100 Hz.7(a) for a nominal gain of 8 and a gain error of 0:1.64 58. 8.3 must be designed to drive a 100 load with a gain error of 0:5. Design a noninverting ampliﬁer with a nominal gain of 4. Design a logarithmic ampliﬁer that “compresses” an input range of 0:1 V 2 V to an output range of . Can a logarithmic ampliﬁer be designed to have a small-signal gain (dVout =dVin ) of 2 at Vin = 1 V and 0. 62. Assume the op amp has a ﬁnite gain but is otherwise ideal. 65.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 61. and the capacitor must remain below 20 pF.1:5. Determine the required op amp gain if the op amp has an output resistance of 1 k . 63. 64. If the op amp provides a slew rate of 1 V/ns. Assume Rout = 100 .0:5 and 2 = .1% V0 Id ea Vout t Figure 8. A voltage adder must realize the following function: Vout = 1 V1 + 2 V2 . Design the circuit if the worst-case error in 1 or 2 must remain below 0:5 and the input impedance seen by V1 or V2 must exceed 10 k . Design the inverting ampliﬁer of Fig. what is the highest input frequency for which no slewing occurs? 59.

Assume IS. (Hint: VX Vin .cls v. Assuming an op amp gain of 1000 and IS = 10.) . In the circuit of Fig. 69.67 70.66. Apply a 10-MHz sinusoid at the input and plot the output as a function of time.66 68. Using ac analysis in SPICE.67. Repeat Problem 67 but assuming that the op amp suffers from an output resistance of 1 k . each op amp provides a gain of 500.17 A for D1 . 8. 2006] June 30.Q1 = 5 10.16 A. 8.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.68 71. 10 k Ω 10 pF 1 kΩ 1 kΩ 10 pF V in Vout Figure 8. plot the input/output characteristic of the precision rectiﬁer shown in Fig. 8. What is the error in the output amplitude with respect to the input amplitude? 10 pF 1 kΩ 1 kΩ 10 pF V in Vout Figure 8. V CC = 2. The arrangement shown in Fig.69 incorporates an op amp to “linearize” a common-emitter stage. plot the frequency response of the circuit depicted in Fig.5 V 500 Ω Vout Q1 V in X 100 Ω Figure 8. V in V out 1 kΩ Y D1 Figure 8. 2007 at 13:42 417 (1) Sec. 8.6 Chapter Summary 417 67.68.69 (a) Explain why the small-signal gain of the circuit approaches RC =RE if the gain of the op amp is very high. 8. and = 100.

(c) Subtract Vout = 5Vin (e. 8 Operational Ampliﬁer As A Black Box (b) Plot the input/output characteristic of the circuit for 0:1 V Vin 0:2 V and an op amp gain of 100. 2007 at 13:42 418 (1) 418 Chap.g. ..BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. using a voltage-dependent voltage source) from the above characteristic and determine the maximum error. 2006] June 30.cls v.

2006] June 30. 1 Coined in the vacuum-tube era. we have R out1 Vb Q1 RE Vb R out2 M1 RS Figure 9.1.1 Cascode as a Current Source Recall from Chapters 5 and 7 that the use of current-source loads can markedly increase the voltage gain of ampliﬁers. How can we increase the output impedance of a transistor that acts as a current source? An important observation made in Chapters 5 and 7 forms the foundation for our study here: emitter or source degeneration “boosts” the impedance seen looking into the collector or drain. For the circuits shown in Fig. The “cascode”1 stage is a modiﬁed version of common-emitter or common-source topologies and proves useful in high-performance circuit design.cls v. Our study includes both bipolar and MOS implementations of each building block. We also know that a single transistor can operate as a current source but its output impedance is limited due to the Early effect (in bipolar devices) or channel-length modulation (in MOSFETs).1 Output impedance of degenerated bipolar and MOS devices.” 419 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we deal with two other important building blocks in this chapter. and the “current mirror” is an interesting and versatile technique employed extensively in integrated circuits. Cascode Stages Cacode as Current Source Cacode as Amplifier Current Mirrors Bipolar Mirrors MOS Mirrors 9.1. respectively.1 Cascode Stage 9. 2007 at 13:42 419 (1) 9 Cascode Stages and Current Mirrors Following our study of basic bipolar and MOS ampliﬁers in previous chapters. the term “cascode” is believed to be an abbreviation of “cascaded triodes. 9. Shown below is the outline of the chapter.

2 (a) Cascode bipolar current source. Let us compute the output impedance of the bipolar cascode of Fig. 9.3) (9.2(a) are biased at a collector current of 1 mA. determine the output resistance. Since the baseemitter voltage of Q2 is constant.1. 9. Example 9. then the degenerated current source “‘consumes” a headroom of 800 mV.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2(a) for the bipolar version. we call Q1 the cascode transistor and Q2 the degeneration transistor. this transistor simply operates as a small-signal resistance equal to rO2 [Fig. Unfortunately. In analogy with the resistively-degenerated counterpart in Fig.5) 1.1 2 Or simply the “cascode. Bipolar Cascode In order to relax the trade-off between the output impedance and the voltage headroom.4) observing that RE or RS can be increased to raise the output resistance.6) (9.2(a).4 V to remain soft saturation.7) If Q1 and Q2 in Fig. Q2 requires a headroom of approximately 0. 9. if RE sustains 300 mV and Q1 requires a minimum collectoremitter voltage of 500 mV. This conﬁguration is called the “cascode” stage. the voltage drop across the degeneration resistor also increases proportionally. Assume = 100 and VA = 5 V for both transistors. we can replace the degeneration resistor with a transistor. In this case. however. For example.cls v. consuming voltage headroom and ultimately limiting the voltage swings provided by the circuit using such a current source. 9.1) (9. Rout 1 + gm1 rO1 rO2 jjr1 gm1rO1 rO2 jjr1 : Note. 2007 at 13:42 420 (1) 420 Chap. emitter of Q1 while consuming a headroom independent of the current. the idea is to introduce a high small-signal resistance (= rO2 ) in the R out R out V b1 V b2 Q1 Q2 (a) Vb Q1 r O2 (b) Figure 9. 9. however. Note thatIC 1 IC 2 if 1 1. (9. (b) equivalent circuit.2 To emphasize that Q1 and Q2 play distinctly different roles here. 9 Cascode Stages and Current Mirrors Rout1 = 1 + gm RE jjr rO + RE jjr = 1 + gmrO RE jjr + rO Rout2 = 1 + gmRS rO + RS = 1 + gmrO RS + rO .2) (9. we have Rout = 1 + gm1 rO2 jjr1 rO1 + rO2 jjr1 : Since typically gm1 rO2 jjr1 (9.2(b)]. Depicted in Fig. 2006] June 30.” . (9. that rO cannot generally be assumed much greater than r .

12). After all.7) can be simpliﬁed by noting that gm = IC =VT . V + V C1 T A T where IC (9.8) (9. (9. “cascoding” has boosted Rout by a factor of 66 here. Eq. then Rout1 approaches Rout.max gm1 rO1 r1 1 rO1 : (9.12) rO2 = 1 (Fig.1. the Early voltage of Q2 is equal to 50 V. thereby limiting Rout to 1 rO1 .3 Compare the resulting output impedance of the cascode with the upper bound given by Eq. Example 9. 2007 at 13:42 421 (1) Sec. rO = VA =IC . and r = VT =IC : Solution VA2 VT IC 1 VA1 IC 2 IC 1 Rout V I T C 1 VA2 + VT IC 2 IC 1 I 1 VA V VA VT .1 Cascode Stage 421 Since Q1 and Q2 are identical and biased at the same current level. r1 still appears from the emitter of Q1 to ac ground.10) By comparison. .1)].BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. i. Exercise What Early voltage is required for an output resistance of 500 k ? It is interesting to note that if rO2 becomes much greater than r1 . 2006] June 30. 9.3 Cascode topology using an ideal current source. the output resistance of Q1 with no degeneration would be equal to rO1 = 5 k . all bipolar transistors fabricated on the same wafer exhibit the same Early voltage. (9. even with Figure 9. At room temperature. VT 26 mV and hence Rout 328:9 k : (9. 9. This example applies to discrete implementations.2 3 In integrated circuits. R out Q1 r π1 Ideal This is the maximum output impedance provided by a bipolar cascode.9) = IC 1 = IC 2 and VA = VA1 = VA2 .11) (9.3) [or RE = 1 in (9.cls v.. Note that rO2 and r1 are comparable in this example.e. Suppose in Example 9.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (9. it is impossible to double the output impedance of the cascode by emitter degeneration.13) (9.18) In practice. RoutA = 1 + gm2 RE jjr2 rO2 + RE jjr2 : It follows from (9.16) RoutA jjr1 = 2rO2 jjr1 : That is. 9 Cascode Stages and Current Mirrors Since gm1 Solution = 26 .4. r1 is typically less than rO2 . 9.17) RoutA = r2rO2 rr1 : . 9. Determine the required value of the degeneration resistor if Q1 and Q2 are identical.1 . As illustrated in Fig. . Example 9.cls v. we have (9. Exercise Repeat the above example if the Early voltage of Q1 is 10 V. and rO2 = 50 k .14) Rout gm1 rO1 rO1 jjr1 475 k : The upper bound is equal to 500 k . 1 O2 (9. 2007 at 13:42 422 (1) 422 Chap.1): R out R out V b1 Q1 R outA Vb Q1 R outA Solution V b2 Q2 RE Figure 9. 2006] June 30.2(a) by a factor of two through the use of resistive degeneration in the emitter of Q2 .15) Rout gm1 rO1 RoutA jjr1 : We wish this value to be twice that given by (9. about 5 higher. rO1 = 5 k . and no positive value of RoutA exists! In other words. r1 = 2:6 k . we replace Q2 and RE with their equivalent resistance from (9.4 .3 We wish to increase the output resistance of the bipolar cascode of Fig.7) that (9.7): (9.

the ratio of (9.5 shows a pnp cascode.5 if rO2 r1 . That is. The output impedance is given by (9. since Q2 provides only an output impedance of rO2 .5? What does the above result mean? Comparing the output resistances obtained in Examples 9. 9. 2006] June 30. 9.6 Evolution of cascode topology viewed as stacking Q1 atop Q2 . More speciﬁcally.6. 9. Example 9. 9.cls v.5). we recognize that even identical transistors yield an Rout (= 328:9 k ) that is not far from the upper bound (= 500 k ).5 PNP cascode current source. R out V b1 X V b2 Q2 (a) R out V b1 V b1 Q1 1 r g m2 O2 VCC Q2 X V b2 Q1 R out (b) VCC 1 r g m2 O2 Q1 V b2 Q1 R out Figure 9. Fig. where Q1 serves as the cascode device and Q2 as the degeneration device.7 . we “stack” Q1 on top of it to raise Rout . While we have arrived at the cascode as an extreme case of emitter degeneration.7) and (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 and 9. 2007 at 13:42 423 (1) Sec. R out R out = r O2 V b2 Q2 V b1 V b2 Q1 Q2 g m1 r O1 ( r O2 r π 1 ) Figure 9.2.7 are not cascodes. it is also possible to view the evolution as illustrated in Fig.4 Explain why the topologies depicted in Fig.12) is equal to rO2 =rO2 + r1 . VCC V b2 V b1 Q2 Q1 R out Figure 9.1 Cascode Stage 423 Exercise Is there a solution if the output impedance must increase by a factor of 1. a value greater than 0. For completeness.

2006] June 30. 9 Cascode Stages and Current Mirrors Unlike the cascode of Fig. 9.1).cls v. the circuits of Fig. Transistor Q2 now operates as a diode-connected device (rather than a current source). r1 and since gm1 gm2 (why?).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.7 connect the emitter of Q1 to the emitter of Q2 . 2007 at 13:42 424 (1) 424 Chap. the output impedance. . 9. is therefore considerably lower: Solution Rout = 1 + gm1 g 1 jjrO2 jjr1 rO1 + g 1 jjrO2 jjr1 : m2 m2 In fact. Rout . Given by (9.2(a). thereby presenting an impedance of 1=gm2 jjrO2 (rather than rO2 ) at node X . since 1=gm2 rO2 .

7(b). . 9. g Rout 1 + gm1 rO1 + g 1 m2 m2 2rO1 : The same observations apply to the topology of Fig.

MOS Cascodes The similarity of Eqs.22) (9. 9.8 MOS cascode current source and its equivalent. .5 mA.23) where it is assumed gm1 rO1 rO2 rO 1 . implying that the output impedance is proportional to the intrinsic gain of the cascode device.3) for degenerated stages suggests that cascoding can also be realized with MOSFETs so as to increase the output impedance of a current source.20) (9.1 . Equation (9.5 Design an NMOS cascode for an output impedance of 500 k and a current of 0. Example 9. (9. Equation (9.23) is an extremely important result. (9.1) and (9. assume M1 and M2 in Fig.8. (9. For simplicity. source. Illustrated in Fig. the idea is to replace the degeneration resistor with a MOS current R out V b1 X V b2 M2 M1 Vb R out M1 r O2 Figure 9. 9.19) (9.21) Exercise Estimate the output impedance for a collector bias current of 1 mA and VA = 8 V.3) can now be written as Rout = 1 + gm1 rO2 rO1 + rO2 gm1rO1 rO2 . Assume n Cox = 100 A=V2 and = 0:1 V.8 are identical (they need not be). r O 2 . thus presenting a small-signal resistance of rO2 from X to ground.

27) .cls v. (9. This observation reveals an interesting point of contrast between bipolar and MOS cascodes: in the former.1 Cascode Stage 425 We must determine W=L for both transistors such that Solution gm1 rO1 rO2 = 500 k : Since rO1 (9. 9.9 MOS cascode viewed as stack of M1 atop of M2 . other second-order effects limit the output impedance of MOS cascodes. 9. 9. has appeared in a cascode as shown in Fig. We observe that Rp is in parallel with rO1 .bip = rO1 . whereas in the latter. 2007 at 13:42 425 (1) Sec. and r are inﬁnite (at low frequencies). raising rO2 eventually leads to Rout. The output resistance is given by (9. Rp .9). It is therefore possible to rewrite (9.23) as Example 9.4 This is because in MOS devices.10 illustrates a PMOS cascode. Determine the output resistance.25) 1 2nCox W ID = 800 : L It follows that We should also note that gm1 rO1 W = 15:6: L = 25 1. Figure 9.1 and hence (9. (9.24) = rO2 = ID .6 Solution Rout = gm1 rO1 jjRp rO2 : 4 In reality.22).11. recognize that stacking a MOSFET on top of a current source “boosts” the impedance by a factor of gm2 rO2 (the intrinsic gain of the cascode transistor).26) Exercise What is the output resistance if W=L = 32? Invoking the alternative view depicted in Fig. 2006] June 30. During manufacturing. a large parasitic resistor. 9.1 = 20 k r . Rout.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we R out R out = r O2 V b2 M2 V b1 X V b2 M2 M1 g m1 r O1 r O2 Figure 9.6 for the MOS counterpart (Fig. we require that gm1 = 800 .MOS = gm1 rO1 rO2 increases with no bound.

we need to understand the concept of the transconductance for circuits. substituting rO1 jjRp for rO1 : Rout = 1 + gm1 rO2 rO1 jjRp + rO2 : (9.10 PMOS cascode current source. we deﬁned the transconductance of a transistor as the change in the collector or drain current divided by the change in the base-emitter or gate-source voltage.12. the cascode topology can also serve as a high-gain ampliﬁer. R out M1 V b1 V b2 M2 RP Figure 9. (9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30. As illustrated in Fig. be shorting the output node to ground. In Chapters 4 and 6. and the “short-circuit transconductance” of the circuit is . For our study below.cls v. 9 VDD V b2 X V b1 M1 R out M2 Cascode Stages and Current Mirrors Figure 9. the output voltage is set to zero Circuit i out ac GND v in Figure 9.11 If gm1 rO1 jjRp is not much greater than unity.2 Cascode as an Ampliﬁer In addition to providing a high output impedance as a current source. 2007 at 13:42 426 (1) 426 Chap.12 Computation of transconductance for a circuit. 9. we return to the original equation. This concept can be generalized to circuits as well. In fact.1. the output impedance and the gain of ampliﬁers are closely related.22).28) Exercise What value of Rp degrades the output impedance by a factor of two? 9.

32) Exercise How does Gm change if the width and bias current of the transistor are doubles? Lemma The voltage gain of a linear circuit can be expressed as Av = . (9. noting that RD carries no current (why?). 2007 at 13:42 427 (1) Sec.12.Gm Rout .31) (9.29) The transconductance signiﬁes the “strength” of a circuit in converting the input voltage to a current.13(a). That is.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. in this case. write Solution Gm = ivout in iD1 =v GS 1 = gm1 : Thus. 9. Proof We know that a linear circuit can be replaced with its Norton equivalent [Fig. the collector or drain must by shorted to ac ground. 9. 9.13(b). 9. Norton’s theorem states that iout is obtained by shorting the output to ground vout = 0 and 5 While omitted for simplicity in Chapters 4 and 6. 9. Example 9.7 Calculate the transconductance of the CS stage shown in Fig. the transconductance of the circuit is equal to that of the transistor.14(a)]. (9.30) (9.13 As depicted in Fig.5 Note the direction of iout in Fig. = 0 is also required for the transconductance .33) where Rout denotes the output resistance of the circuit (with the input voltage set to zero). we short the output node to ac ground and.1 Cascode Stage 427 deﬁned as Gm = ivout jvout=0 : in (9. the condition vout of transistors.cls v. 2006] June 30. VDD RD v out v in M1 (a) VDD RD i out M1 (b) ac GND v in Figure 9.

i. iout is simply equal to the collector current of Q1 .Gm vin Rout and hence (9. 9.14 (a) Norton equivalent of a circuit. 9.14(b)].38) .35) vout = . We also relate iout to vin by the transconductance of the circuit.34) (9.14(a).8 Determine the voltage gain of the common-emitter stage shown in Fig. In this case.G R : m out vin Example 9. 9 Cascode Stages and Current Mirrors Vout v in i out R out Vout (a) i out v in (b) Figure 9.36) iX Q1 vX (a) (b) (c) Figure 9.cls v. Gm = ivout in = gm1 : (9. 9. vout = . Thus. gm1 vin . (b) computation of short-circuit output current . Gm = iout =vin .15 Solution To calculate the short-circuit transconductance of the circuit. VCC I1 v out v in Q1 v in Q1 i out ac GND (9.37) (9.15(b)]..15(a). in Fig. we place an ac short from the output to ground and ﬁnd the current through it [Fig.ioutRout = .e. 9. 2007 at 13:42 428 (1) 428 Chap. computing the short-circuit current [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.

9. the small-signal current. suppose we stack a transistor on top of Q1 as shown in Fig. 2006] June 30. 9.44) In this case. Does the voltage gain increase or decrease? The above lemma serves as an alternative method of gain calculation. from the above lemma. In the limit. 2007 at 13:42 429 (1) Sec.Gm Rout = .15(c): Rout = vX iX = rO1 : It follows that (9. .16 (a) Flow of output current generated by a CE stage through rO1 .gm1 vin rO1 .1 that the circuit achieves a high output impedance and. Av = . produced by Q1 ﬂows through rO1 . we obtain the output resistance as depicted in Fig. VA : V T (9. 9. a voltage gain higher than that of a CE stage.41) (9.39) (9. the collector load impedance must be maximized. as in cascodes. 9.gm1rO1 : (9.gm1rO1 = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) use of cascode to increase the output impedance. It also indicates that the voltage gain of a circuit can be increased by raising the output impedance. Bipolar Cascode Ampliﬁer Recall from Chapter 4 that to maximize the voltage gain of a common-emitter stage.1. Now.43) (9.1 Cascode Stage 429 Note that rO does not carry a current in this test (why?).16(b). gm1 vin . an ideal current source serving as the load [Fig.42) Exercise Suppose the transistor is degenerated by an emitter resistor equal to RE . We know from Section 9. Next.16(a)] yields a voltage gain of VCC I1 VCC I1 v in Q1 g v m1 in r O1 V b1 v out v in Q1 Q2 v out (a) (b) Figure 9. The transconductance falls but the ouput resistance rises. thus generating an output voltage equal to .40) Av = .cls v.

(b) detailed view of (a). Q1 still produces a collector current of gm1 vin . 1=gm2 rO1 jjr2 + g 1 jjrO2 m2 rO1 jjr2 : (9. As a commoni out Q2 ac GND i out Q2 r O2 X Q1 v in ac GND Q1 v in (a) g v m1 in g v m1 in r O1 (b) Figure 9.gm1 rO1 gm1rO1 jjr2 : . which subsequently ﬂows through Q2 and hence through the output short: iout = gm1vin : That is. 2007 at 13:42 430 (1) 430 Chap.17(b). Dividing gm1 vin between this impedance and rO1 .50) (9. this transistor can be viewed as a diode-connected device having an impedance of 1=gm2 jjrO2 . Av = .gm1 gm2 rO1 jjr2 rO2 + rO1 jjr2 : Also. and hence iout gm1vin : (9. the collector current of Q1 must split between rO1 and the impedance seen looking into the emitter of Q2 . 9.gm1 rO1 gm1 rO1 jjr2 + 1 . emitter stage. Since the base and collector voltages of Q2 are equal.53) Av = .45) Gm = gm1 : (9. we write from (9. (9. After all.17(a). since Q1 and Q2 carry approximately equal bias currents.52) (9.46) dubiously.17 (a) Short-circuit output current of a cascode.Gm Rout = . rO1 . the short-circuit transconductance is equal to iout =vin .49) (9. As shown in Fig. 9.33) and (9. as shown in Fig.cls v. 9 Cascode Stages and Current Mirrors Let us determine the voltage gain of the bipolar cascode with the aid of the above lemma. To obtain the overall voltage gain.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.47) rO2 . the approximation Gm = gm1 is reasonable.gm1 f 1 + gm2rO1 jjr2 rO2 + rO1 jjr2 g .5). We must therefore verify that only a negligible fraction of gm1 vin is “lost” in rO1 . 2006] June 30. we have iout = gm1 vin For typical transistors.48) That is.51) gm2 and rO1 rO2 : (9.46) The reader may view (9. gm1 (9.

654: Cascoding thus raises the voltage gain by a factor of 65. But.53). the idea is to consider the cascode device. 9. An actual current source lowers the impedance seen at the output node and hence the voltage gain.18 Cascode ampliﬁer as a cascade of a CE stage and a CB stage.000? It is possible to view the cascode ampliﬁer as a common-emitter stage followed by a commonbase stage. 9. jAv j = 12. 9.cls v.9 Solution = 26 . V CC I1 v out Q2 CB Vb Stage v in Q1 CE Stage Figure 9. the load is assumed to be an ideal current source.54) gm1 rO1 jjr2 = 65:8 and from (9.16(b) is biased at a current of 1 mA. as a commonbase transistor that senses the small-signal current produced by Q1 .1 .1 Cascode Stage 431 Compared to the simple CE stage of Fig. (9.18.56) (9.16(a). This perspective may prove useful in some cases. the cascode ampliﬁer exhibits a gain that is higher by a factor of gm1 rO1 jjr2 —a relatively large value because rO1 and r2 are much greater than 1=gm1 .16(b). For example. Q2 .8. Assume the load is an ideal current source. dropping the output impedance to Rout = rO3 jj f 1 + gm2 rO1 jjr2 rO2 + rO1 jjr2 g rO3 jj gm2 rO2 rO1 jjr2 + rO1 jjr2 : (9. determine the voltage gain. 2007 at 13:42 431 (1) Sec. 9.57) . in the circuit of Fig. rO 1 rO2 = 5 k . We have gm1 Example 9. Thus. (9. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.55) Exercise What Early voltage gives a gain of 5. Illustrated in Fig. the circuit illustrated in Fig. 9.19(a) suffers from a low gain because the pnp current source introduces an impedance of only rO3 from the output node to ac ground. 9. The bipolar cascode of Fig. If VA = 5 V and = 100 for both transistors. r1 r2 2600 . The high voltage gain of the cascode topology makes it attractive for many applications.

19 (a) Cascode with a simple current-source load.62) (9.19(b).9 incorporates a cascode load using VA = 4 V and = 50.53).1.64) . this gain is about half of that expressed by (9.10 Suppose the circuit of Example 9. Example 9. we express the voltage gain as Av = . Recognizing that the short-circuit transconductance.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The output impedance is now given by the parallel combination of those of the npn and pnp cascodes. postulating that the circuit of Fig.cls v. 9. Thus. 2006] June 30. Gm . Rop = gm3 rO3 rO4 jjr3 = 151 k and (9.63) Ron = 329 k : (9. 2007 at 13:42 432 (1) 432 Chap.gm1Ron jjRop .5 is a good candidate and arriving at the stage depicted in Fig. Using (9.1 that cascoding also raises the output impedance of current sources. Ron and Rop . 9 Cascode Stages and Current Mirrors VCC V b3 VCC V b2 Q3 v out V b1 v in Q2 Q1 V b1 v in Q2 Q1 R out VCC r O3 V b2 v out V b1 v in Q2 Q1 Q4 Q3 R op R on (a) (b) Figure 9. since npn and pnp devices may display different Early voltages. How should we realize the load current source to maintain a high gain? We know from Section 9. respectively.59) Note that.61) This result represents the highest voltage gain that can be obtained in a cascode stage. we have Ron gm2 rO2 rO1 jjr2 Rop gm3 rO3 rO4 jjr3 : (9. (b) use of cascode in the load to raise the voltage gain.60) (9.7). 9. For comparable values of Ron and Rop .gm1 f gm2rO2 rO1 jjr2 jj gm3 rO3 rO4 jjr3 g : (9. of the stage is still approximately equal to gm1 (why?).58) (9. rO1 (= rO2 ) may not be equal to rO3 (= rO4 ) . What is the voltage gain? pnp transistors with Solution The load transistors carry a collector current of approximately 1 mA.

compared to a simple common-source stage. Our gradual approach to constructing this stage reveals the role of each device.14 utilizes our knowledge of the output impedance to quickly provide the voltage gain of the stage. yielding a voltage gain of gm1 if 1=gm2 rO1 . Since and r are inﬁnite for MOS devices (at low frequencies).53) to arrive at (9. the voltage gain has risen by a factor of gm2 rO2 (the intrinsic gain of the cascode device). CMOS Cascode Ampliﬁer The foregoing analysis of the bipolar cascode ampliﬁer can readily be extended to the CMOS counterpart. the gain has fallen by approximately a factor of 3 because the pnp devices suffer from a lower Early voltage and . this stage also provides a short-circuit transconductance Gm output resistance is given by (9.67) (9.68) (9.5 mA.22).69).65) (9.20 (a) MOS cascode ampliﬁer. The (9. 2007 at 13:42 433 (1) Sec.19(b) proves quite formidable if we attempt to replace each transistor with its small-signal model and solve the resulting circuit. that M1 and . however. 9. It is important to take a step back and appreciate our analysis techniques. Moreover.69) Av = . 9. Exercise Repeat the above example for a collector bias current of 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.20(a) with an ideal current-source VDD V b2 V b2 VDD I1 v out V b1 X v in M1 (a) M4 M3 v out M2 X M1 (b) R op R on V b1 v in M2 Figure 9.gm1rO1 gm2 rO2 : In other words. (b) realization of load by a PMOS cascode.Gm Rout . 2006] June 30. Depicted in Fig.gm1 1 + gm2 rO2 rO1 + rO2 . load. 9. Note.66) Compared to the ideal current source case. allowing straightforward calculation of the output impedance.1 Cascode Stage 433 It follows that jAv j = gm1 Ron jjRop = 3. 9. 981: (9.cls v. the lemma illustrated in Fig. The cascode of Fig. we can also utilize (9.

If n Cox = 100 A=V2 .70) (9. As with the bipolar counterpart.20(b). 9 Cascode Stages and Current Mirrors M2 need not exhibit equal transconductances or output resistances (their widths and lengths need not be the same) even though they carry equal currents (why?). 2007 at 13:42 434 (1) 434 Chap. gm3 = gm4 . W=L3.gm1 gm2 rO2 rO1 jjgm3 rO3 rO4 : Example 9.74) ID1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2 = 577 . rO1 = rO2 .1 .2 = 30. Illustrated in Fig.1 and p = 0:15 V.73) (9.cls v.72) The cascode ampliﬁer of Fig. p Cox = 50 A=V2 .4 = 40. 9.71) Av .11 (9. n = 0:1 V. We have Solution = gm2 . gm1 rO3 = rO4 .1 and s . the circuit exhibits the following output impedance components: Ron gm2 rO2 rO1 Rop gm3 rO3 rO4 : The voltage gain is therefore equal to (9.2 = 2nCox L 1. 2006] June 30. the MOS cascode ampliﬁer must incorporate a cascode PMOS current source so as to maintain a high voltage gain. 9. determine the voltage gain.2 gm1. With the particular choice of device parameters here. and (9.20(b) incorporates the following device parameters: W=L1. ID1 = = ID4 = 0:5 mA.

318: (9.75) rO1.W gm3.77) rO3.2 = I1 n D1. (9.82) .79) (9.81) (9.1 : Also.76) (9.71) thus respectively give (9.2 = 20 k and (9.80) Av = .78) Ron 693 k Rop 250 k and (9.4 = 707 .gm1Ron jjRop .70) and (9.4 = 13:3 k : Equations (9.

9. we have R2 I1 (9. where VCC R1 I1 Q1 R2 VBE (a) VDD R1 I1 M1 R2 VGS (b) Figure 9.cls v. 2006] June 30.2 Current Mirrors 9. 2007 at 13:42 435 (1) Sec. this voltage experiences some variation. R1 and R2 divide VCC down to the required VBE .2.20 C in Finland and +50 C in Saudi Arabia.1 Initial Thoughts The biasing techniques studied for bipolar and MOS ampliﬁers in Chapters 4 and 6 prove inadequate for high-performance microelectronic circuits. 9. Illustrated in Fig. consider the bipolar current source shown in Fig. VTH 2 L 1+ 2 . however.2 Current Mirrors 435 Exercise Explain why a lower bias current results in a higher output impedance in the above example. where the base current is neglected.21(b). 9. But. A similar situation arises in CMOS circuits. Thus.83) R1 + R2 VCC = VT ln IS . 9. Calculate the output impedance for a drain current of 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. a MOS current source biased by means of a resistive divider suffers from dependence on VDD and temperature. contains two temperature-dependent parameters: VT = kT=q and IS . for a desired current I1 . gradually loses voltage as it is discharged. thereby mandating that the circuits operate properly across a range of supply voltages. Another critical issue in biasing relates to ambient temperature variations. even if the base-emitter voltage remains constant with temperature. we can write I1 = 1 n Cox W VGS . The right-hand side. the bias current of CE and CS stages is a function of the supply voltage—a serious issue because in practice. For example. I1 does not. That is. Here.21 Impractical biasing of (a) bipolar and (b) MOS current sources.25 mA.21(a). what happens if the temperature varies? The left-hand side remains constant if the resistors are made of the same material and hence vary by the same percentage. To understand how temperature affects the biasing. VTH 2 2 L = 1 n Cox W R R2 R VDD . The rechargeable battery in a cellphone or laptop computer. for example. A cellphone must maintain its performance at .

84) : (9. 2 (9.85) .

22 Concept of current mirror. (b) voltage proportional to natural logarithm of current. an elegant method of creating supply.) VCC I REF X VBE (a) (b) (c) VCC I copy I REF Q REF V1 I REF Q REF VCC I copy ? Q1 X Q 1 Current Mirror Figure 9.23(a).22 must be implemented as a bipolar or MOS transistor. Called the “bandgap reference circuit” and employing several tens of devices. Unfortunately. 9 Cascode Stages and Current Mirrors Since both the mobility and the threshold voltage vary with temperature. In summary. the complexity of the bandgap prohibits its use for each current source in a large integrated circuit. We must therefore seek a method of “copying” the golden current without duplicating the entire bandgap circuitry. In order to avoid supply and temperature dependence.and temperature-independent voltages and currents exists and appears in almost all microelectronic systems..22 conceptually illustrates our goal here.86) . 9. Figure 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.g. this scheme is studied in more advanced books [1]. such that Q1 carries a current equal to IREF : IS1 exp VX = IREF . we surmise that the current mirror resembles the topology shown in Fig. 9. For example. 9.cls v.2 Bipolar Current Mirror Since the current source generating Icopy in Fig. Fortunately. 2006] June 30. a bandgap reference can provide a “golden current” while requiring a few tens of devices. e. (The MOS counterpart is similar. 9. the typical biasing schemes introduced in Chapters 4 and 6 fail to establish a constant collector or drain current if the supply voltage or the ambient temperature are subject to change. The golden current generated by a bandgap reference is “read” by the current mirror and a copy having the same characteristics as those of IREF is produced. VCC I REF I copy Current Mirror Figure 9. VX = VBE . (c) bipolar current mirror. where Q1 operates in the forward active region and the black box guarantees Icopy = IREF regardless of temperature or transistor characteristics. Icopy = IREF or 2IREF . The bandgap circuit by itself does not solve all of our problems! An integrated circuit may incorporate hundreds of current sources. as the load impedance of CE or CS stages to achieve a high gain. I1 is not constant even if VGS is. Let us summarize our thoughts thus far.23(a) be realized? The black box generates an output voltage. How should the black box of Fig.2. 2007 at 13:42 436 (1) 436 Chap. V T (9. Current mirrors serve this purpose.23 (a) Conceptual illustration of current copying.

Figure 9. the base-emitter voltage of the devices is not deﬁned.2 Current Mirrors 437 where Early effect is neglected. thereby yielding Icopy = IREF . since QREF and Q1 have equal base-emitter voltages..87) We must therefore seek a circuit whose output voltage is proportional to the natural logarithm of its input.REF denotes the reverse saturation current of QREF .12 An electrical engineering student who is excited by the concept of the current mirror constructs the circuit but forgets to tie the base of QREF to its collector (Fig. Fortunately.REF (9. 2007 at 13:42 437 (1) Sec. S. From one perspective. We say Q1 “mirrors” or copies the current ﬂowing through QREF . . the inverse function of bipolar transistor characteristics.89) (9.REF exp VX VT Icopy = IS1 exp VX VT and hence (9.24).e. 9. S. we neglect the base currents.cls v. 9. V1 = VX if IS.REF = IS1 . if QREF is identical to Q1 . a single diode-connected device satisﬁes (9. Neglecting the base-current in Fig. we can write IREF = IS. From another perspective. VCC I REF Q REF I copy ? Q1 Figure 9. In other words. The lack of the base currents translates to Icopy = 0. This holds even though VT and IS vary with temperature. Example 9.90) Icopy = I IS1 IREF . For now. the black box satisﬁes the following relationship: VX = VT ln IREF : I S1 (9. i. we have V1 = VT ln IIREF . 9. i..24 Solution The circuit provides no path for the base currents of the transistors.91) which reduces to Icopy = IREF if QREF and Q1 are identical.88) where IS. More fundamentally. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. QREF takes the natural logarithm of IREF and Q1 takes the exponential of VX . Thus. Note that VX does vary with temperature but such that Icopy does not.REF (9.e. displaying the current mirror circuitry.87).23(b).23(c) consolidates our thoughts. Explain what happens.

The circuit is often drawn as in Fig.REF . Here. 9.25. hoping that the battery VX provides the base currents and deﬁnes the base-emitter voltage of QREF and Q1 .j IREF : S. along with (9. 2007 at 13:42 438 (1) 438 Chap. 2IREF . e. Explain what happens.j exp VX . yields (9. Q1 now carries a ﬁnite current.13 Realizing the mistake in the above circuit. how do we obtain different values for these copies. we recognize that VX can serve as the base-emitter voltage of multiple transistors. 5IREF . etc.25 Solution While i.. 9.j .26(b) for simplicity. Exercise Suppose VX is slightly greater than the necessary value.REF (9. The student has forgotten that a diodeconnected device is necessary here to ensure that VX remains proportional to lnIREF =IS. 9.REF . the student makes the modiﬁcation shown in Fig.87).cls v. In what region does QREF operate? We must now address two important questions. 2006] June 30.21. the biasing of Q1 is no different from that in Fig.. VT lnIREF =IS. transistor Qj carries a current Icopy. V T (9.j = IS. 9 Cascode Stages and Current Mirrors Exercise What is the region of operation of QREF ? Example 9. how do we make additional copies of IREF to feed different parts of an integrated circuit? Second. V T which. Icopy = IS1 exp VX .94) . given by Icopy. thus arriving at the circuit shown in Fig.93) Icopy. VCC I REF Q REF VX I copy ? I REF Q REF VX VX VCC I copy ? Q1 Q1 Figure 9. 9.? Considering the topology in Fig.22(c).92) which is a function of temperature if VX is constant.g.j = I IS.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9.e.26(a). First.

Recall from Chapter 4 that this is equivalent to placing n unit transistors in parallel.2 Current Mirrors VCC I REF Q REF I copy1 I copy2 I copy3 439 Q1 Q2 Q3 (a) VCC I REF Q1 Q REF (b) VCC I copy1 Q2 I copy2 Q3 Q REF (c) I copy3 I REF Q1 Q2 I copy = 3 I REF Q3 Figure 9.5 mA Q4 Q5 Figure 9.cls v. 2006] June 30. design the required current sources.14 A multistage ampliﬁer incorporates two current sources of values 0.5 mA. Using a bandgap reference current of 0.27 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. We say the copies are “scaled” with respect to IREF .REF ( the emitter area of QREF ).26 (a) Multiple copies of a reference current. Example 9. Neglect the effect of the base current for now.75 mA and 0. Solution Figure 9.25 mA 0.94) readily answers the second question as well: If IS. 2007 at 13:42 439 (1) Sec. all transistors are identical to ensure proper scaling of IREF . then Icopy. VCC I REF Q REF 0. Here. providing Icopy = 3IREF .25 mA. 9.26(c) depicts an example where Q1 -Q3 are identical to QREF . Equation (9.j ( the emitter area of Qj ) is chosen to be n times IS. The key point here is that multiple copies of IREF can be generated with minimal additional complexity because IREF and QREF themselves need not be duplicated.27 illustrates the circuit. (c) combining output currents to generate larger copies. Figure 9.j = nIREF . (b) simpliﬁed drawing of (a).75 mA Q1 Q2 Q3 0.

The current of 500 A requires 10 unit transistors.97) It is desired to generate two currents equal to 50 A and 500 A from a reference of 200 A. 2006] June 30.cls v. denoted by 10AE for simplicity.25 mA I copy Q1 X Q REF1 Q REF2 Q REF3 Figure 9. 9 Cascode Stages and Current Mirrors Exercise Repeat the above example if the bandgap reference current is 0.95) (9.15 (9.29). 9.1 mA. A unit transistor thus generates 50 A (Fig. VCC I REF 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.28. Q1 . 2007 at 13:42 440 (1) 440 Chap. To produce the smaller current.REF (= 3IS here) so that a unit transistor. Design the current mirror circuit. The use of multiple transistors in parallel provides an accurate means of scaling the reference in current mirrors. Repeating the expressions in (9. the idea is VCC I REF 0. 9.90). we have IREF = 3IS exp VX VT VX Icopy = IS exp V T and hence (9. we must employ four unit transistors for QREF such that each carries 50 A.89) and (9.96) Icopy = 1 IREF : 3 Example 9. Exempliﬁed by the circuit in Fig.2 mA Solution I copy1 X Q1 AE 4A E I copy2 Q2 10 A E Figure 9. how do we create fractions of IREF ? This is accomplished by realizing QREF itself as multiple parallel transistors. But. to begin with a larger IS. can generate a smaller current.29 .28 Copying a fraction of a reference current .

since IC.26(a) by all transistors.101) To suppress the above error.F IE. the total copied current) increases. recognizing that QREF and Q1 still have equal base-emitter voltages and hence carry currents with a ratio of n.31.cls v.REF + Icopy n + Icopy . Here.2 Current Mirrors 441 Exercise Repeat the above example for a reference current of 150 A. 1 IC. the base currents of Q1 and QREF can be expressed as IB1 = Icopy 1 IB. More speciﬁcally.102) . 9. (9. the second term in the denominator is much less than unity and Icopy nIREF . the bipolar current mirror can be modiﬁed as illustrated in Fig.REF (9.98) (9. Effect of Base Current We have thus far neglected the base current drawn from node X in Fig.. thereby reducing the effect of the base currents by a factor of . We analyze the error with the aid of the diagram shown in Fig. However. Thus. 2007 at 13:42 441 (1) Sec. 2006] June 30. 9.30. Our objective is to calculate Icopy . an effect leading to a signiﬁcant error as the number of copies (i.F . so does the error in Icopy . emitter follower QF is interposed between the collector of QREF and node X . 9.e. The error arises because a fraction of IREF ﬂows through the bases rather than through the collector of QREF .100) = Icopy =n. respectively.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. assuming IC. VCC I REF Q REF AE I copy nβ I copy Q1 I copy nA E β Figure 9. as the copied current ( n) increases. which. where AE and nAE denote one unit transistor and n unit transistors. we can repeat the above analysis by writing a KCL at X : For a large and moderate n. 9.30 Error due to base currents.REF = Icopy n : Writing a KCL at X therefore yields (9. leads to Icopy = nIREF : 1 + 1 n + 1 (9.F = Icopy + Icopy n .99) 1 IREF = IC.

31 Addition of emitter follower to reduce error due to base currents. 2006] June 30. obtaining the base current of QF as 1 IB.F = Icopy 1 + n : 2 Another KCL at node P gives .F QF X I copy Q1 Cascode Stages and Current Mirrors I copy nA E β Figure 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.F I C. 2007 at 13:42 442 (1) 442 Chap.cls v. 9 VCC I REF P Q REF AE I copy nβ I B.

(9.103) IREF = IB.REF .F + IC.

we write a KCL at X : Example 9. Noting that Icopy1 .32).110) .108) Icopy1 = IREF 4 + 15 Icopy2 = 10IREF : 15 4+ With the addition of emitter follower (Fig.REF : copy1 Thus.107) (9. (9.106) That is.104) (9.109) (9. Icopy 1 + 1 + Icopy = 2 n n and hence (9. Icopy2 .105) Icopy = nIREF : 1 + 12 n + 1 (9. the error is lowered by a factor of .REF + Icopy1 + Icopy2 + IC. and IC.REF = 4I + Icopy1 + 10Icopy1 + IC.16 Solution IREF = IC. 9. we have at X : (9.REF (the total current ﬂowing through four unit transistors) still retain their nominal ratios (why?). 9. Compute the error in Icopy1 and Icopy2 in Fig.29 before and after adding a follower.

2007 at 13:42 443 (1) Sec. the reference transistor has an area of 3AE .23(c).. i. We must therefore deﬁne the bias current of Q2 properly.115) copy1 and hence Icopy1 = IREF 15 4+ 2 (9. 2 (9. 2006] June 30.32 IC.114) (9.116) Icopy2 = 10IREF : 15 4+ 2 (9.33(a). we form the pnp current mirror depicted in Fig.F = IC.111) (9.REF + Icopy1 + Icopy2 = 4Icopy1 + Icopy1 + 10Icopy1 = 15Icopy1 : A KCL at P therefore yields (9. .REF 2 = 15Icopy1 + 4I . For example.33(b)]. PNP Mirrors Consider the common-emitter stage shown in Fig. where a current source serves as a load to achieve a high voltage gain. 9. 9. if QREF and Q2 are identical and the base currents negligible. then Q2 Q1 carries a current equal to IREF . 9.33(c).2 mA 443 QF Q 1 X 4A E I copy1 AE I copy2 Q2 10 A E Figure 9. 9. In analogy with the npn counterpart of Fig.e.cls v. 9.112) (9.113) IREF = 15Icopy1 + IC.2 Current Mirrors VCC I REF P 0.117) Exercise Calculate Icopy1 if one of the four unit transistors is omitted. The current source can be realized as a pnp transistor operating in the active region [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

. In the mirror of Fig.23(c).33(c) it ﬂows from X to ground.npn = 5 V. We can also create various scaling scenarios between QREF 1 and QM and between QREF 2 and Q2 .gm1rO1 jjrO2 = . Assume VA. 2007 at 13:42 444 (1) 444 Chap.34.pnp T A. (c) proper biasing of Q2 .M onto IC 2 .pnp = 4 V. and VCC = 2:5 V. 9. V1 VVA. Q1 and Q2 are biased at a current of 700 A. IREF = 100 A. VA. How do we generate the latter from the former? It is possible to combine the npn and pnp mirrors for this purpose. From the power budget and VCC = 2:5 V. Exercise What Early voltage is necessary for a voltage gain of 100? We must now address an interesting problem. as illustrated in Fig.M . Note that the base currents introduce a cumulative error as IREF is copied onto IC. 9. 9. whereas in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.34 at a collector current of 1 mA while IREF Example 9.17 Design the circuit of Fig.5! This is because the gain of the stage is simply given by the Early voltages and VT . 9. QREF incorporates one unit device and Q1 seven unit devices.118) (9. Example 9. Thus. a fundamental constant of the technology and independent of the bias current. 2006] June 30. it is assumed that the golden current ﬂows from VCC to node X .pnp = . Assuming for simplicity that QREF 1 .33 (a) CE stage with current-source load. Thus. QM .33(c) for a voltage gain of 100 and a power budget of 2 mW. of which 100 A is dedicated to IREF and QREF .119) (9. thereby forcing the same current through Q2 and Q1 . and Q2 are identical and neglecting the base currents. (b) realization of current source by a pnp device.npn VA. we obtain a total supply current of 800 A.18 = 25 A. we observe that QM draws a current of IREF from QREF 2 . 9 VCC Vb v out v in Q1 v in Q1 Q2 v out Cascode Stages and Current Mirrors VCC Q REF X v in Q2 v out I REF Q1 VCC I1 (a) (b) (c) Figure 9.npn + VA. the circuit’s gain cannot reach 100. and IC. We wish to bias Q1 and Q2 in Fig.85:5: (9. QREF 2 . requiring that the (emitter) area of Q2 be 7 times that of QREF .cls v.) The voltage gain can be written as Solution Av = . 9. (For example.120) What happened here?! We sought a gain of 100 but inevitably obtained a value of 85. with the above choice of Early voltages.

Choose the scaling factors in the circuit so as to minimize the number of unit transistors. the two transistors suffer from signiﬁcant IS mismatch. Example 9.REF 1 and IC 2 = IC.M = 8IREF jIC 2 j = 5IC. Exercise How much IS mismatch results in a 30% collector current mismatch? . 16 units. Solution It is possible that the two transistors were fabricated in different batches and hence underwent slightly different processing. the npn and pnp scaling factors can be swapped.121) (9. Random variations during manufacturing may lead to changes in the device parameters and even the emitter area. Explain why. and in the latter case. 2007 at 13:42 445 (1) Sec. 2006] June 30.122) IC.19 An electrical engineering student purchases two nominally identical discrete bipolar transistors and constructs the current mirror shown in Fig. This is why current mirrors are rarely used in discrete design.M = 40IC.23(c). Icopy is 30 higher than IREF . 9. As a result.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we can choose either Solution IC.REF 2 as it would necessitate 43 units.M or (9. Note that we have implicitly dismissed the case IC. For an overall scaling factor of 1 mA=25 A = 40. Unfortunately.2 Current Mirrors VCC I REF I C.123) (9. the four transistors in the current mirror circuitry require 15 units.M Q REF1 X1 QM Q REF2 X2 v in Q2 v out Q1 445 Figure 9. Exercise Calculate the exact value of IC 2 if = 50 for all transistors.M : (9.34 Generation of current for pnp devices.124) (In each case.M = 10IREF jIC 2 j = 4IC. 9.cls v.) In the former case.

drawing the MOS counterpart of Fig. 9.35 (a) Conceptual illustration of copying a current by an NMOS device.2.2 can be applied to MOS current mirrors as well.35(a). 9. (b) generation of a voltage proportional to square root of current. we recognize that the black box must generate VX such that VDD I REF X M1 VGS (a) (b) (c) VDD I copy1 I REF M REF VX I REF M REF VDD I copy ? X M 1 Current Mirror Figure 9. 2006] June 30. In particular. (c) MOS current mirror.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.2.23(a) as in Fig. 9 Cascode Stages and Current Mirrors 9. 2007 at 13:42 446 (1) 446 Chap.cls v.3 MOS Current Mirror The developments in Section 9. 1 C W 2 n ox L .

the black box must satisfy the following input (current)/output (voltage) characteristic: v u VX = u 2IREF u t n Cox .125) where channel-length modulation is neglected. 1 VX . VTH 1 2 = IREF . Thus. (9.

From Chapter 6. we can view the circuit’s operation from two perspectives: (1) MREF takes the square root of IREF and M1 squares the result. or (2) the drain currents of the two transistors can be expressed as 2 ID. 9. it must operate as a “square-root” circuit. As with the bipolar version. we recall that a diodeconnected MOSFET provides such a characteristic [Fig.REF = 1 n Cox W 2 L REF VX . 9.35(b)].35(c).126) That is. VTH . W L + VTH 1 : 1 (9. thus arriving at the NMOS current mirror depicted in Fig.

1 Icopy = 2 n Cox W VX . L 1 . VTH 2 .

127) (9.128) where the threshold voltages are assumed equal. (9. It follows that which reduces to Icopy = IREF Icopy = .

L REF if the two transistors are identical. . WL 1 IREF .

thinking that the gate current is zero and hence leaving the gates ﬂoating (Fig.13 decides to try the MOS counterpart. . 9.20 The student working on the circuits in Examples 9. Explain what happens.W (9.12 and 9.129) Example 9.36).

2 Current Mirrors VDD I REF X M REF Floating Node 447 I copy ? M1 Figure 9.129) and hence a copy current independent of device parameters and temperature.21 An integrated circuit employs the source follower and the common-source stage shown in Fig. 9. In other words.2 mA VDD V in2 M2 Vout2 0. e. an initial condition created at node X when the power supply is turned on. VDD V in1 M1 Vout1 0.36 Solution This circuit is not a current mirror because only a diode-connected device can establish (9. Example 9.5 mA I1 (a) I2 VDD V in1 VDD I REF W 3( ( L 0. Icopy is very poorly deﬁned.37 .cls v.g.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3-mA reference. 9. The following example illustrates these concepts.. 2006] June 30. 2007 at 13:42 447 (1) Sec. Exercise Is MREF always off in this circuit? Generation of additional copies of IREF with different scaling factors also follows the principles shown in Fig. 9. Since the gates of MREF and M1 are ﬂoating.3 mA VDD V in2 M2 Vout2 I2 M I2 5( M1 Vout1 I1 M I1 M REF 2( W ( L (b) W ( L Figure 9. Design a current mirror that produces I1 and I2 from a 0.37(a). they can assume any voltage.26.

6 MOS mirrors need not resort to the technique shown in Fig. The circuit of Fig. 9.29. . the gate oxide thickness is reduced to less than 30 A.34. we select an aspect ratio of 3W=L for the diode-connected device.cls v. Figure 9. 9.37(b) shows the overall circuit. 2007 at 13:42 448 (1) 448 Chap. 9. leading to “tunneling” and hence noticeable gate current. Since MOS devices draw a negligible gate current. 9 Cascode Stages and Current Mirrors Following the methods depicted in Figs. and 5W=L for MI 2 .38 exempliﬁes these ideas. On the other hand.38 NMOS and PMOS current mirrors in a typical circuit. this effect mandates circuit modiﬁcations that are described in more advanced texts [1]. Investigated in Problem 53.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. channel-length modulation in the current-source transistors does lead to additional errors.3 Chapter Summary Stacking a transistor atop another forms a cascode structure. Solution Exercise Repeat the above example if IREF = 0:8 mA.28 and 9. The cascode topology can also be considered an extreme case of source or emitter degeneration. 9. resulting in a high output impedance. This effect is beyond the scope of this book. CS Stage VDD Follower Vout1 VDD I REF V in1 V in2 Vout2 M REF V in3 Follower CS Stage VDD V in4 Vout3 Vout4 Figure 9.31. 2006] June 30. 2W=L for MI 1 . 9. The idea of combining NMOS and PMOS current mirrors follows the bipolar counterpart depicted in Fig. 6 In deep-submicron CMOS technologies.

2.42.1 for the circuit shown in Fig.and temperaturedependent currents.5 mA. where VCC = 2:5 V. Repeat Example 9. 9. If VBE or VGS are well-deﬁned. Determine the output resistance in each case.39 3. Problems 1. then IC or ID are not. Consider the cascode stage depicted in Fig.3 Chapter Summary 449 The voltage gain of an ampliﬁer can be expressed as .e. (a) Repeat Problem 1 for this circuit. Current mirrors are rarely used in disrcete design as their accuracy depends on matching between transistors.39. (a) Compute Vb2 for a bias current of 1 mA.17 A and = 100 for both transistors. a parasitic resistor RP has appeared in the cascode circuits of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.41.39. In the circuit of Fig. Setting the bias currents of analog circuits to well-deﬁned values is difﬁcult.40. Current mirrors can “copy” a well-deﬁned reference current numerous times for various blocks in an analog system. assuming I1 is ideal and equal to 0. For example.2(a). 5. In the bipolar cascode stage of Fig.5 mA. IS = 6 10. 9. 6.Gm Rout . assuming a bias current of 0. VBE 1 . 9.cls v. This relationship indicates that the gain of ampliﬁers can be maximized by maximing their output impedance. 9. 4. we have chosen RC = 1 k and VCC = 2:5 V. VCC RC V1 V b1 V b2 Q1 Q2 Figure 9. Suppose the circuit of Fig. determine the value of Vb1 such that Q2 experiences a base-collector forward bias of only 300 mV. where Q3 plays the role of . i. 2007 at 13:42 449 (1) Sec. compute the maximum allowable value of RC such that Q1 experiences a base-collector forward bias of no more than 300 mV.41 is realized as shown in Fig. 9. (b) Noting that VCE 2 = Vb1 . 9. Neglect the Early effect. 9.. 2006] June 30. The load of a cascode stage is also realized as a cascode circuit so as to approach an ideal current source. (b) With the minimum allowable value of Vb1 . Current mirrors can scale a reference current by integer or non-integer factors. where Gm denotes the short-circuit transconductance of the ampliﬁer. IC 1 = 0:5 mA while IC 2 = 1 mA. resistive dividers tied to the base or gate of transistors result in supply. Estimate the maximum allowable bias current if each transistor sustains a base-collector forward bias of 200 mV. 9. a cascode stage can operate as a high-gain ampliﬁer. Due to a manufacturing error. With its high output impedance.

9. a student adventurously swaps the collector and base terminals of the degeneration transistor.43 student can achieve? Assume the transistors are identical. 8. What is the maximum output impedance that the R out V b1 V b2 Q1 Q2 I1 .40 R out VCC V b1 V b2 Q1 Q2 I1 Figure 9. determine the output impedance of the V bn Qn Figure 9. While constructing a cascode stage.n and VA3 = VA. a student decides to extend the idea as illustrated in Fig.42 circuit. 9.43.41 R out VCC V b1 V b2 Q1 Q2 Q3 V b3 Figure 9. arriving at the circuit shown in Fig. 9 Cascode Stages and Current Mirrors R out R out V b1 RP RP V b2 Q2 Q1 V b1 Q2 V b2 Q1 (a) (b) (c) (d) Figure 9. . 7.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.44. 2007 at 13:42 450 (1) 450 R out V b1 RP V b2 Q2 V b2 Q2 Q1 V b1 Q1 RP R out Chap.p . Excited by the output impedance “boosting” capability of cascodes. 2006] June 30. Assuming VA1 = VA2 = VA.cls v.

(b) Noting that VX = Vb1 + jVBE 1 j. Determine the output impedance of each circuit shown in Fig. Using this approximation. The pnp cascode depicted in Fig.49. the Early voltage reaches tens of volts. (a) Calculate the required value of Vb2 . compute the maximum tolerable value of .9) and explain why the result resembles that in Eq.47 must provide a bias current of 0. IS = 10.12). The MOS cascode of Fig. Assume n Cox = 100 A/V2 and VTH = 0:4 V. 10. 9. (a) Neglecting channel-length modulation. (b) Compare this expression with that in Eq. (a) Writing gm = 2n Cox W=LID . calculate the output impedance of the circuit. where VDD = 1:8 V. If VCC = 2.1 .48 must be designed for a bias current of 0.44 (a) Assuming both transistors operate in the active region.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. compute the required value of Vb2 .5 mA with an output impedance of at least 50 k . and W=L2 = 40=0:18.16 and = 100.45 must provide a bias current of 0. Assume 1. (9. What is the minimum tolerable value of Vb1 if M2 must remain in saturation? (b) Assuming = 0:1 V. (9. Assume n Cox = 100 A/V2 and VTH = 0:4 V. determine the maximum allowable value of Vb1 such that Q2 experiences a base-collector forward bias of only 200 mV. 9.5 mA to a circuit. 2007 at 13:42 451 (1) Sec. 9. p . 9. If n Cox = 100 A/V2 and W=L = 20=0:18 for both transistors. simplify Eq. determine the output impedance of the circuit. 9. 9. (9. Consider the circuit shown in Fig. 14. (b) Compare the result with that of a cascode stage for a given bias current (IC 1 ) and explain why this is generally not a good idea. 15.cls v. 9. 13.45 11.46.23) in terms of ID and plot the result as a function of ID . Explain which ones are considered cascode stages.5 V V b2 V b1 Q2 X Q1 Circuit 0. Which one is a stronger function of the bias current? The cascode current source shown in Fig.9) for the bipolar counterpart. 2006] June 30. W=L1 = 20=0:18. 12.5 mA Figure 9. express Eq. (9.5 mA. allowing the approximation VA VT if 100. For discrete bipolar transistors.3 Chapter Summary R out V b1 V b2 Q2 Q1 451 Figure 9.

cls v. 9 Cascode Stages and Current Mirrors R out Q1 V b1 RP R out R out V b1 V b2 RB Q1 Q2 (a) R out V b1 V b1 V b2 RB (b) Q1 RB Q2 (c) Q1 Q2 Q2 (d) VCC RE V b2 V b1 Q2 Q1 V b2 VCC Q2 Q1 R out Vb V b2 I1 Q1 V b2 VCC I1 Q2 R out (g) R out (e) (f) Figure 9.48 (a) If we require a bias current of 1 mA and RD = 500 .46 R out V b1 V b2 M1 M2 Figure 9.47 V b1 V b2 M 1 W = 30 L 0. 17. Assume all of the transistors operate in saturation and gm rO 1. what is the highest allowable value of Vb1 ? (b) With such a value chosen for Vb1 .18 M 2 W = 20 L 0. The PMOS cascode of Fig.50. 2006] June 30. 2007 at 13:42 452 (1) 452 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 9.51 must provide a bias current of 0. what is the value of VX ? 16.5 mA with an output impedance of 40 k . If p Cox = 50 A/V2 and = 0:2 V. determine the required value of W=L1 = W=L2 .18 Figure 9.1 . . Compute the output resistance of the circuits depicted in Fig. 9.

Assume L. 9. explain what happens if the widths of both transistors are increased by a factor of N while the transistor lengths and bias currents remain unchanged. 20.49 R out R out V b1 RG M2 (a) R out V b1 V b2 V b3 R out M1 V b1 M1 M2 (b) M1 M3 M2 (c) V b1 M2 M1 (d) Figure 9. 9. 9.53) reduces to 2 Av V V VA V . determine the minimum required value of VA1 = VA2 . Assume all of the transistors operate in saturation and gm rO 1. where the input is applied to the base of Q2 .16(b) must be designed for a voltage gain of 500.3 Chapter Summary VDD RD V1 V b1 X V b2 M2 M1 453 Figure 9. Compute the short-circuit transconductance and the voltage gain of each of the stages in Fig. Having learned about the high voltage gain of the cascode stage.51 is designed for a given output impedance.130) a quantity independent of the bias current.cls v. 23.54. 2007 at 13:42 453 (1) Sec. a student adventurously constructs the circuit depicted in Fig. If 1 = 2 = 100. The cascode stage of Fig. 9. 22. 9.53. Rout . Prove that Eq. Using Eq.23). T A+ T (9. (9. Determine the output impedance of the stages shown in Fig. 21. The PMOS cascode of Fig. 2006] June 30. 9.51 18. Assume 0 and VA 1. 19.52. (9.1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Assume I1 = 1 mA.50 VDD V b2 V b1 M2 M1 R out Figure 9.

explain intuitively why the voltage gain of this stage cannot be as high as that of the cascode. 2006] June 30. (a) Replacing Q1 with rO1 . 9. 9 Cascode Stages and Current Mirrors R out VDD V b1 V b2 M1 M2 M3 V b3 RG (a) (b) VDD V b2 V b1 M2 M1 R out (c) R out V b1 V b2 V b3 (d) M1 M2 M3 V b3 M3 Figure 9.56.52 VCC VDD Vb M2 Vout V in M1 Vb M1 V in VDD M2 Vout V in Q1 RE (c) (d) VCC V in Q2 Vout Vb Q1 RE Vb Q2 Vout (a) (b) VDD RE V b2 M2 Vout M1 V in RS (e) VDD RE V in M2 Vout M1 RS (f) (g) VCC RE V in V b1 Q2 Vout RC V b1 Figure 9. compute the short-circuit transconductance and the voltage gain. 9.cls v. 24.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) Assuming gm rO 1. Calculate the voltage gain of each stage illustrated in Fig. .55. 25. 2007 at 13:42 454 (1) 454 R out V b1 M1 M2 Chap.53 rather than to the base of Q1 . Determine the short-circuit transconductance and the voltage gain of the circuit shown in Fig.

Determine the voltage gain of the circuit. Express Eq. 9.61) in terms of these quantities. Due to a manufacturing error.20(a) is designed for a given voltage gain.1 for both transistors.cls v.N . 9. Writing gm = 2n Cox W=LID and rO = 1=ID .P . 2006] June 30. 3 = 4 = P . The MOS cascode of Fig. Does the result depend on the bias current? 27. a bipolar cascode ampliﬁer has been conﬁgured as shown in Fig. Av . If n Cox = 100 A=V2 and = 0:1 V. The MOS cascode of Fig.79) and the result obtained in Problem 28. 30. express Eq. VA1 = VA2 = VA. 9.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3 Chapter Summary VCC I1 Vout V in V b1 Q2 Q1 455 Figure 9. Using Eq.54 VCC I1 Vout V b2 V b1 V in Q2 Q1 Figure 9. V31 = VA4 = VA. 9.20(a) must provide a voltage gain of 200.19 and assume 1 = 2 = N . 28.57. 9. explain what happens if the widths of the transistors are increased by a factor of N while the transistor lengths and bias currents remain p .56 26. 29. determine the required value of W=L1 = W=L2 . (9. (9. 2007 at 13:42 455 (1) Sec.55 VCC I1 Vout V b1 RP V in Q2 V in Q2 Q1 V b1 Q1 RP I1 Vout V b1 V in Q1 Q2 RE V in Q2 VCC I1 Vout V b1 Q1 VCC I1 Vout Q3 VCC V b3 VCC (a) (b) (c) (d) Figure 9. (9. Consider the cascode ampliﬁer of Fig.72) in terms of the device parameters and plot the result as a function of ID .

9. and p = 0:15 V. 34. W=L1 = = W=L4 = 20=0:18. 32.59.cls v. VDD V b4 V b3 V b2 V in M4 M3 Vout M2 M1 V b1 Figure 9. In the cascode stage of Fig. Repeat Problem 30 if the lengths of both transistors are increased by a factor of N while the transistor widths and bias currents remain unchanged. VDD V b4 V b3 M2 V b2 V in M1 RP M4 M3 Vout V b2 V in M2 M1 RP V b4 V b3 VDD M4 M3 Vout V b2 V b1 M2 M1 V in M5 V in M5 V b4 V b3 VDD M4 M3 Vout V b2 V b1 M2 M1 V b4 V b3 VDD M4 M3 Vout (a) (b) (c) (d) Figure 9. and p Cox = 50 A=V2 . If n Cox = 100 A=V2 . n = 0:1 V. 9. a CMOS cascode ampliﬁer has been conﬁgured as shown in Fig. 9 VCC Q4 V b2 Q3 Cascode Stages and Current Mirrors v out V b1 v in Q2 Q1 Figure 9. Calculate the voltage gain of the circuit. 2007 at 13:42 456 (1) 456 Chap.20(b).1 .1 . 2006] June 30. Assume gm rO 1. 31. Determine the voltage gain of each circuit in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Due to a manufacturing error. calculate the bias current such that the circuit achieves a voltage gain of 500.58.57 unchanged.59 . 9.58 33.

9. Repeat Example 9. If I1 is 10% greater than its nominal value.23(b). 2007 at 13:42 457 (1) Sec. 9. . deﬁned as @I1 =@VCC .64. 43. resistor RP has appeared in series with the emitter of Q1 in Fig. Having learned about the logarithmic function of the circuit in Fig. (9. Explain intuitively why this sensitivity is proportional to the transconductance of Q1 . 9. (9. 2006] June 30. express the value of RP in terms of other circuit parameters. a student remembers the logarithmic ampliﬁer studied in Chapter 8 and constructs the circuit depicted in Fig. express the value of RP in terms of other circuit VCC I REF Q REF I1 Q1 RP Figure 9.61.) Determine the sensitivity of I1 to VTH and explain why this issue becomes more serious at low supply voltages. The parameters n Cox and VTH in Eq. Repeat Problem 40 for the circuit shown in Fig. Repeat Problem 38 for the topology shown in Fig. (9. parameters.85) (in terms of VDD ). Explain what happens. determine the sensitivity of I1 to VCC .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.60. 9. From Eq. 38.62. 36.85) also vary with the fabrication process. If I1 is half of its nominal value. IX R1 Q1 V1 Q2 V REF Figure 9.61 40.63. Design an npn current mirror for this purpose. We wish to generate two currents equal to 50 A and 230 A from a reference of 130 A. 9. Neglect the base curents. (Integrated circuits fabricated in different batches exhibit slightly different parameters. 42. Due to a manufacturing error.15 if the reference current is equal to 180 A. 37. 9. Repeat Problem 35 for Eq.62 41. 44. Assume QREF and Q1 are identical.cls v. resistor RP has appeared in series with the base of QREF in Fig.83). Assume QREF and Q1 are identical and 1.60 39. Due to a manufacturing error. 9. Q1 V1 V REF R1 IX Q2 Figure 9.3 Chapter Summary 457 35. but assuming that I1 is twice its nominal value.

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458 (1)

458

Chap. 9

VCC I REF Q REF RP

Cascode Stages and Current Mirrors

I1 Q1

Figure 9.63

VCC I REF Q REF I1 RP Q1

Figure 9.64

VCC I REF Q REF I1 RP Q1

Figure 9.65

45. Repeat Problem 44 for the circuit shown in Fig. 9.65, but assuming I1 is 10% less than its nominal value. 46. Taking base currents into account, determine the value of Icopy in each circuit depicted in Fig. 9.66. Normalize the error to the nominal value of Icopy .

VCC I REF Q1 AE Q REF

(a)

VCC I copy

5A E

**VCC I copy AE I REF Q1
**

2A E

I REF Q1

5A E

I copy

3A E

Q2

I2

5A E

Q REF

(b)

Q REF

(c)

Figure 9.66

47. Calculate the error in Icopy for the circuits shown in Fig. 9.67. 48. Taking base currents into account, compute the error in Icopy for each of the circuits illustrated in Fig. 9.68. 49. Determine the value of RP in the circuit of Fig. 9.69 such that I1 = IREF =2. With this choice of RP , does I1 change if the threshold voltage of both transistors increases by V ? 50. Determine the value of RP in the circuit of Fig. 9.70 such that I1 = 2IREF . With this choice of RP , does I1 change if the threshold voltage of both transistors increases by V ?

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459 (1)

Sec. 9.3

Chapter Summary

VCC I REF Q1 nA E Q REF Q2 I2 kAE I copy1 mA E

459

Figure 9.67

VCC I REF AE AE AE I copy AE

3A E 2A E

VCC I REF

5A E 9A E

I copy

(a)

(b)

Figure 9.68

VDD I REF M1 W L M REF I1 W L RP

Figure 9.69

VDD I REF M1 W L RP M REF I1 W L

Figure 9.70

51. Repeat Example 9.21 if the reference current is 0.35 mA. 52. Calculate Icopy in each of the circuits shown in Fig. 9.71. Assume all of the transistors operate in saturation. 53. Consider the MOS current mirror shown in Fig. 9.35(c) and assume M1 and M2 are identical but 6= 0. (a) How should VDS 1 be chosen so that Icopy1 is exactly equal to IREF ?

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460 (1)

460

VDD I REF

3 (W( L n 5 (W( L p 2 (W( L n

Chap. 9

VDD W 3( ( L p I copy I REF

Cascode Stages and Current Mirrors

( W (p

L

5 (W( L n

2 (W( L p

( W (n L

M REF

I copy W 3( ( L n

M REF

(a)

(b)

Figure 9.71

(b) Determine the error in Icopy1 with respect to IREF if VDS 1 is equal to VGS , VTH (so that M1 resides at the edge of saturation). Design Problems In the following problems, unless otherwise stated, assume IS;n = IS;p = 6 10,16 A, VA;n = VA;p = 5 V, n = 100; p = 50; nCox = 100 A/V2 , p Cox = 50 A/V2 , VTH;n = 0:4 V, and VTH;p = ,0:5 V, where the subscripts n and p refer to n-type (npn or NMOS) and p-type (pnp or PMOS) devices, respectively. 54. Assuming a bias current of 1 mA, design the degenerated current source of Fig. 9.72(a) such that RE sustains a voltage approximately equal to the minimum required collector-emitter

R out Vb Q1 RE V b1 V b2 Q1 Q2

(b)

R out

(a)

Figure 9.72

voltage of Q2 in Fig. 9.72(b) ( 0:5 V). Compare the output impedances of the two circuits. 55. Design the cascode current source of Fig. 9.72(b) for an output impedance of 50 k . Select Vb1 such that Q2 experiences a base-collector forward bias of only 100 mV. Assume a bias current of 1 mA. 56. We wish to design the MOS cascode of Fig. 9.73 for an output impedance of 200 k and a

R out V b1 V b2 M1 M2

Figure 9.73

bias current of 0.5 mA. (a) Determine W=L1 = W=L2 if = 0:1 V,1 . (b) Calculate the required value of Vb2 .

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461 (1)

Sec. 9.3

Chapter Summary

461

**57. The bipolar cascode ampliﬁer of Fig. 9.74 must be designed for a voltage gain of 500. Use
**

VCC I1 Vout V b1 V in Q2 Q1

Figure 9.74

Eq. (9.53) and assume = 100. (a) What is the minimum required value of VA ? (b) For a bias current of 0.5 mA, calculate the required bias component in Vin . (c) Compute the value of Vb1 such that Q1 sustains a collector-emitter voltage of 500 mV. 58. Design the cascode ampliﬁer shown in Fig. 9.75 for a power budget of 2 mW. Select Vb1 and

VCC = 2.5 V V b3 V b2 Q4 Q3 Vout V b1 V in Q2 Q1

Figure 9.75

is achieved? 59. Design the CMOS cascode ampliﬁer of Fig. 9.76 for a voltage gain of 200 and a power

VDD V b3 V b2 V b1 V in M4 M3 Vout M2 M1

Vb2 such that Q1 and Q4 sustain a base-collector forward bias of 200 mV. What voltage gain

Figure 9.76

budget of 2 mW with VDD = 1:8 V. Assume W=L1 = = W=L4 = 20=0:18 and p = 2n = 0:2 V,1 . Determine the required dc levels of Vin and Vb3 . For simplicity, assume Vb1 = Vb2 = 0:9 V. 60. The current mirror shown in Fig. 9.77 must deliver I1 = 0:5 mA to a circuit with a total power budget of 2 mW. Assuming VA = 1 and 1, determine the required value of IREF and the relative sizes of QREF and Q1 .

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462

Chap. 9

**Cascode Stages and Current Mirrors
**

VCC = 2.5 V

Circuit

I REF I1 Q REF Q1

Figure 9.77

**61. In the circuit of Fig. 9.78, Q2 operates as an emitter follower. Design the circuit for a power
**

VCC = 2.5 V V in I REF Q REF Q1 Q2 Vout

Figure 9.78

budget of 3 mW and an output impedance of 50 . Assume VA = 1 and 1. 62. In the circuit of Fig. 9.79, Q2 operates as a common-base stage. Design the circuit for an

VCC = 2.5 V RC Vout I REF V in Q REF Q1 Q2 Vb

Figure 9.79

63.

64. 65. 66.

67.

output impedance of 500 , a voltage gain of 20, and a power budget of 3 mW. Assume VA = 1 and 1. Design the circuit of Fig. 9.30 for Icopy = 0:5 mA and an error of less than 1 with respect to the nominal value. Explain the trade-off between accuracy and power dissipation in this circuit. Assume VCC = 2:5 V. Design the circuit of Fig. 9.34 such that the bias current of Q2 is 1 mA and the error in IC 1 with respect to its nominal value is less than 2. Is the solution unique? Figure 9.80 shows an arrangement where M1 and M2 serve as current sources for circuits 1 and 2. Design the circuit for a power budget of 3 mW. The common-source stage depicted in Fig. 9.81 must be designed for a voltage gain of 20 and a power budget of 2 mW. Assuming W=L1 = 20=0:18, n = 0:1 V,1 , and p = 0:2 V,1 , design the circuit. The source follower of Fig. 9.82 must achieve a voltage gain of 0.85 and an output impedance of 100 . Assuming W=L2 = 10=0:18, n = 0:1 V,1 , and p = 0:2 V,1 , design the circuit.

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463 (1)

Sec. 9.3

Chapter Summary

463

VDD = 1.8 V

Circuit 1 Circuit 2 1 mA

I REF

0.5 mA

M REF

M1

M2

Figure 9.80

VDD = 1.8 V M REF M2

I REF

V in

M1

Figure 9.81

VDD = 1.8 V I REF M REF V in M1 Vout M2

Figure 9.82

**68. The common-gate stage of Fig. 9.83 employs the current source M3 as the load to achieve
**

VDD = 1.8 V M4 M3 Vout M1 I REF M REF M5 V in M2 Vb

Figure 9.83

a high voltage gain. For simplicity, neglect channel-length modulation in M1 . Assuming W=L3 = 40=0:18, n = 0:1 V,1 , and p = 0:2 V,1 , design the circuit for a voltage gain of 20, an input impedance of 50 , and a power budget of 13 mW. (You may not need all of the power budget.) SPICE Problems

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464

Chap. 9

Cascode Stages and Current Mirrors

In the following problems, use the MOS device models given in Appendix A. For bipolar transistors, assume IS;npn = 5 10,16 A, npn = 100, VA;npn = 5 V, IS;pnp = 8 10,16 A, pnp = 50, VA;pnp = 3:5 V. 69. In the circuit of Fig. 9.84, we wish to suppress the error due to the base currents by means of resistor RP .

VCC = 2.5 V I REF Q REF

1 mA

I1 Q1

RP

Figure 9.84

(a) Tying the collector of Q2 to VCC , select the value of RP so as to minimize the error between I1 and IREF . (b) What is the change in the error if the of both transistors varies by 3? (c) What is the change in the error if RP changes by 10? 70. Repeat Problem 69 for the circuit shown in Fig. 9.85. Which circuit exhibits less sensitivity to variations in and RP ?

VCC = 2.5 V I REF Q REF RP

1 mA

I1 Q1

Figure 9.85

71. Figure 9.86 depicts a cascode current source whose value is deﬁned by the mirror arrangement, M1 -M2 . Assume W=L = 5 m=0:18 m for M1 -M3 .

VDD = 1.8 V I out

0.5 mA

Vb

M3 M2

M1

Figure 9.86

(a) Select the value of Vb so that Iout is precisely equal to 0.5 mA. (b) Determine the change in Iout if Vb varies by 100 mV. Explain the cause of this change. (c) Using both hand analysis and SPICE simulations, determine the output impedance of the cascode and compare the results. 72. We wish to study the problem of biasing in a high-gain cascode stage, Fig. 9.87. Assume W=L1;2 = 10 m=0:18 mum, Vb = 0:9 V, and I1 = 1 mA is an ideal current source. (a) Plot the input/output characteristic and determine the value of Vin at which the slope (small-signal gain) reaches a maximum.

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465 (1)

References

VDD = 1.8 V I1 Vout Vb V in M2 M1

465

Figure 9.87

(b) Now, suppose the biasing circuitry that must produce the above dc value for Vin incurs an error of 20 mV. From (a), explain what happens to the small-signal gain. 73. Repeat Problem 72 for the cascode shown in Fig. 9.88, assuming W=L = 10 m=0:18 m for all of the transistors.

VDD = 1.8 V M5

1 mA

M4 M3 Vb M2 Vout

V in

M1

Figure 9.88

References

1. B. Razavi, Design of Analog CMOS Integrated Circuits McGraw-Hill, 2001.

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10

Differential Ampliﬁers

The elegant concept of “differential” signals and ampliﬁers was invented in the 1940s and ﬁrst utilized in vacuum-tube circuits. Since then, differential circuits have found increasingly wider usage in microelectronics and serve as a robust, high-performance design paradigm in many of today’s systems. This chapter describes bipolar and MOS differential ampliﬁers and formulates their large-signal and small-signal properties. The concepts are outlined below.

General Considerations Differential Signals Differential Pair Bipolar Differential pair Qualitative Analysis Large−Signal Analysis Small−Signal Analysis MOS Differential pair Qualitative Analysis Large−Signal Analysis Small−Signal Analysis Other Concepts Cascode Pair Common−Mode Rejection Pair with Active Load

**10.1 General Considerations
**

10.1.1 Initial Thoughts In order to understand the need for differential circuits, let us ﬁrst consider an example.

Example 10.1

Having learned the design of rectiﬁers and basic ampliﬁer stages, an electrical engineering student constructs the circuit shown in Fig. 10.1(a) to amplify the signal produced by a microphone. Unfortunately, upon applying the result to a speaker, the student observes that the ampliﬁer output contains a strong “humming” noise, i.e., a steady low-frequency component. Explain what happens.

Solution

Recall from Chapter 3 that the current drawn from the rectiﬁed output creates a ripple waveform at twice the ac line frequency (50 or 60 Hz) [Fig. 10.1(b)]. Examining the output of the commonemitter stage, we can identify two components: (1) the ampliﬁed version of the microphone signal and (2) the ripple waveform present on VCC . For the latter, we can write

Vout = VCC , RC IC ;

(10.1)

noting that Vout simply “tracks” VCC and hence contains the ripple in its entirety. The “hum” originates from the ripple. Figure 10.1(c) depicts the overall output in the presence of both the signal and the ripple. Illustrated in Fig. 10.1(d), this phenomenon is summarized as the “supply

466

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467 (1)

Sec. 10.1

General Considerations

VCC

110 V 60 Hz To Bias

467

RC Vout Q1

C1

(a)

VCC

Voice Signal Ripple

VCC

Vout

Signal

t

(b) (c)

t

(d)

Figure 10.1 (a) CE stage powered by a rectiﬁer, (b) ripple on supply voltage, (c) effect at output, (d) ripple and signal paths to output.

noise goes to the output with a gain of unity.” (A MOS implementation would suffer from the same problem.)

Exercise

What is the hum frequency for a full-wave rectiﬁer or a half-wave rectiﬁer?

How should we suppress the hum in the above example? We can increase C1 , thus lowering the ripple amplitude, but the required capacitor value may become prohibitively large if many circuits draw current from the rectiﬁer. Alternatively, we can modify the ampliﬁer topology such that the output is insensitive to VCC . How is that possible? Equation (10.1) implies that a change in VCC directly appears in Vout , fundamentally because both Vout and VCC are measured with respect to ground and differ by RC IC . But what if Vout is not “referenced” to ground?! More speciﬁcally, what if Vout is measured with respect to another point that itself experiences the supply ripple to the same extent? It is thus possible to eliminate the ripple from the “net” output. While rather abstract, the above conjecture can be readily implemented. Figure 10.2(a) illustrates the core concept. The CE stage is duplicated on the right, and the output is now measured between nodes X and Y rather than from X to ground. What happens if VCC contains ripple? Both VX and VY rise and fall by the same amount and hence the difference between VX and VY remains free from the ripple. In fact, denoting the ripple by vr , we express the small-signal voltages at these nodes as

vX = Av vin + vr vY = vr :

That is,

(10.2) (10.3)

vX , vY = Av vin :

Note that Q2 carries no signal, simply serving as a constant current source.

(10.4)

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468 (1)

468

Chap. 10

Differential Ampliﬁers

VCC

Ripple Ripple

VCC R C1 X Q1 Y Q2 R C2 A1

R C1

To Bias

R C2 X Q1 Vout

To Bias

Y Q2

v in

(a) (b)

Figure 10.2 Use of two CE stages to remove effect of ripple.

The above development serves as the foundation for differential ampliﬁers: the symmetric CE stages provide two output nodes whose voltage difference remains free from the supply ripple. 10.1.2 Differential Signals Let us return to the circuit of Fig. 10.2(a) and recall that the duplicate stage consisting of Q2 and RC 2 remains “idle,” thereby “wasting” current. We may therefore wonder if this stage can provide signal ampliﬁcation in addition to establishing a reference point for Vout . In our ﬁrst attempt, we directly apply the input signal to the base of Q2 [Fig. 10.3(a)]. Unfortunately, the signal components at X and Y are in phase, canceling each other as they appear in vX , vY :

**vX = Av vin + vr vY = Av vin + vr vX , vY = 0:
**

Vr VCC R C1

To Bias

(10.5) (10.6) (10.7)

VCC R C1 X Y Q2

− v in

R C2

To Bias

R C2

X Q1 V in

(a)

Y Q2

+ v in

Q1

(b)

(c)

Figure 10.3 (a) Application of one input signal to two CE stages, (b) use of differential input signals, (c) generation of differential phases from one signal.

For the signal components to enhance each other at the output, we can invert one of the input

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469 (1)

Sec. 10.1

General Considerations

469

phases as shown in Fig. 10.3(b), obtaining

**vX = Av vin + vr vY = ,Av vin + vr
**

and hence

(10.8) (10.9)

vX , vY = 2Av vin :

(10.10)

Compared to the circuit of Fig. 10.2(a), this topology provides twice the output swing by exploiting the ampliﬁcation capability of the duplicate stage. The reader may wonder how ,vin can be generated. Illustrated in Fig. 10.3(c), a simple approach is to utilize a transformer to convert the microphone signal to two components bearing a phase difference of 180 . Our thought process has led us to the speciﬁc waveforms in Fig. 10.3(b): the circuit senses two inputs that vary by equal and opposite amounts and generates two outputs that behave in a similar fashion. These waveforms are examples of “differential” signals and stand in contrast to “single-ended” signals—the type to which we are accustomed from basic circuits and previous chapters of this book. More speciﬁcally, a single-ended signal is one measured with respect to the common ground [Fig. 10.4(a)] and “carried by one line,” whereas a differential signal is measured between two nodes that have equal and opposite swings [Fig. 10.4(b)] and is thus “carried by two lines.”

VCC

Vin

Vout

Q1

(a)

VCC

Q1

Q2

Output Differential Signal

V1 VCM V2 t

(c) 2V0

Input Differential Signal

(b) Figure 10.4 (a) Single-ended signals, (b) differential signals, (c) illustration of common-mode level.

Figure 10.4(c) summarizes the foregoing development. Here, V1 and V2 vary by equal and opposite amounts and have the same average (dc) level, VCM , with respect to ground:

V1 = V0 sin !t + VCM V2 = ,V0 sin !t + VCM

(10.11) (10.12)

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470

Chap. 10

Differential Ampliﬁers

Since each of V1 and V2 has a peak-to-peak swing of 2V0 , we say the “differential swing” is 4V0 . We may also say V1 and V2 are differential signals to emphasize that they vary by equal and opposite amounts around a ﬁxed level, VCM . The dc voltage that is common to both V1 and V2 [VCM in Fig. 10.4(c)] is called the “commonmode (CM) level.” That is, in the absence of differential signals, the two nodes remain at a potential equal to VCM with respect to the global ground. For example, in the transformer of Fig. 10.3(c), +vin and ,vin display a CM level of zero because the center tap of the transformer is grounded. How can the transformer of Fig. 10.3(c) produce an output CM level equal to +2 V. The center tap can simply be tied to a voltage equal to +2 V (Fig. 10.5).

v in1 v in1

2V +2 V

Example 10.2 Solution

v in2

v in2 t

Figure 10.5

Exercise

Does the CM level change if the inputs of the ampliﬁer draw a bias current?

Example 10.3

Determine the common-mode level at the output of the circuit shown in Fig. 10.3(b). In the absence of signals, VX = VY = VCC , RC IC (with respect to ground), where RC = RC 1 = RC 2 and IC denotes the bias current of Q1 and Q2 . Thus, VCM = VCC , RC IC . Interestingly, the ripple affects VCM but not the differential output.

Solution

If a resistor of value R1 is inserted between VCC and the top terminals of RC 1 and RC 2 , what is the output CM level?

Exercise

Our observations regarding supply ripple and the use of the “duplicate stage” provide sufﬁcient justiﬁcation for studying differential signals. But, how about the common-mode level? What is the signiﬁcance of VCM = VCC , RC IC in the above example? Why is it interesting that the ripple appears in VCM but not in the differential output? We will answer these important questions in the following sections.

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471 (1)

Sec. 10.2

Bipolar Differential Pair

471

10.1.3 Differential Pair Before formally introducing the differential pair, we must recognize that the circuit of Fig. 10.4(b) senses two inputs and can therefore serve as A1 in Fig. 10.2(b). This observation leads to the differential pair. While sensing and producing differential signals, the circuit of Fig. 10.4(b) suffers from some drawbacks. Fortunately, a simple modiﬁcation yields an elegant, versatile topology. Illustrated in Fig. 10.6(a), the (bipolar) “differential pair”1 is similar to the circuit of Fig. 10.4(b), except that the emitters of Q1 and Q2 are tied to a constant current source rather than to ground. We call IEE the “tail current source.” The MOS counterpart is shown in Fig. 10.6(b). In both cases, the sum of the transistor currents is equal to the tail current. Our objective is to analyze the large-signal and small-signal behavior of these circuits and demonstrate their advantages over the “single-ended” stages studied in previous chapters.

VCC RC X V in1 Q1 Q2 RC Y Vin2 V in1 RD X M1 M2 I SS VDD RD Y Vin2

I EE

(a) (b)

Figure 10.6 (a) Bipolar and (b) MOS differential pairs.

For each differential pair, we begin with a qualitative, intuitive analysis and subsequently formulate the large-signal and small-signal behavior. We also assume each circuit is perfectly symmetric, i.e., the transistors are identical and so are the resistors.

**10.2 Bipolar Differential Pair
**

10.2.1 Qualitative Analysis It is instructive to ﬁrst examine the bias conditions of the circuit. Recall from Section 10.1.2 that in the absence of signals, differential nodes reside at the common-mode level. We therefore draw the pair as shown in Fig. 10.7, with the two inputs tied to VCM to indicate no signal exists at the input. By virtue of symmetry,

**VBE1 = VBE2 IC 1 = IC 2 = IEE ; 2 VX = VY = VCC , RC IEE : 2
**

1 Also called the “emitter-coupled pair” or the “long-tailed pair.”

(10.13) (10.14)

where the collector and emitter currents are assumed equal. We say the circuit is in “equilibrium.” Thus, the voltage drop across each load resistor is equal to RC IEE =2 and hence (10.15)

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472 (1)

472

Chap. 10

VCC R C1 X Q1 V CM I EE R C1 = R C2 = R C Q2 R C2 Y

Differential Ampliﬁers

Figure 10.7 Response of differential pair to input CM change.

In other words, if the two input voltages are equal, so are the two outputs. We say a zero differential input produces a zero differential output. The circuit also “rejects” the effect of supply ripple: if VCC experiences a change, the differential output, VX , VY , does not. Are Q1 and Q2 in the active region? To avoid saturation, the collector voltages must not fall below the base voltages:

revealing that VCM cannot be arbitrarily high.

VCC , RC IEE VCM ; 2

(10.16)

Example 10.4

A bipolar differential pair employs a load resistance of 1 k close to VCC can VCM be chosen? and a tail current of 1 mA. How

Solution

Equation 10.16 gives

**VCC , VCM RC IEE 2 0:5 V:
**

That is, VCM must remain below VCC by at least 0.5 V.

(10.17) (10.18)

What value of RC allows the input CM level to approach VCC is the transistors can tolerate a base-collector forward bias of 400 mV?

Exercise

Now, let us vary VCM in Fig. 10.7 by a small amount and determine the circuit’s response. Interestingly, Eqs. (10.13)-(10.15) remain unchanged, thereby suggesting that neither the collector current nor the collector voltage of the transistors is affected. We say the circuit does not respond to changes in the input common-mode level; or the circuit “rejects” input CM variations. Figure 10.8 summarizes these results. The “common-mode rejection” capability of the differential pair distinctly sets it apart from our original circuit in Fig. 10.4(b). In the latter, if the base voltage of Q1 and Q2 changes, so do their collector currents and voltages (why?). The reader may recognize that it is the tail current source in the differential pair that guarantees constant collector currents and hence rejection of the input CM level.

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473 (1)

Sec. 10.2

**Bipolar Differential Pair
**

VCC R C I EE

Upper Limit of VCM to Avoid Saturation 2

473

VX , VY

VCM1 VCM2

Figure 10.8 Effect of VCM 1 and VCM 2 at output.

With our treatment of the common-mode response, we now turn to the more interesting case of differential response. We hold one input constant, vary the other, and examine the currents ﬂowing in the two transistors. While not exactly differential, such input signals provide a simple, intuitive starting point. Recall that IC 1 + IC 2 = IEE . Consider the circuit shown in Fig. 10.9(a), where the two transistors are drawn with a vertical offset to emphasize that Q1 senses a more positive base voltage. Since the difference between the base voltages of Q1 and Q2 is so large, we postulate that Q1 “hogs” all of the tail current, thereby turning Q2 off. That is,

VCC = 2.5 V RC X V in1 = +2 V Q1 Q2 P I EE

(a) (b)

VCC = 2.5 V RC Vout RC Y Q2 Q1 P I EE Vin2 = +2 V

RC Vout Y Vin2 = +1 V V in1 = +1 V

X

Figure 10.9 Response of bipolar differential pair to (a) large positive input difference and (b) large negative input difference.

IC 1 = IEE IC 2 = 0;

and hence

(10.19) (10.20)

VX = VCC , RC IEE VY = VCC :

(10.21) (10.22)

But, how can we prove that Q1 indeed absorbs all of IEE ? Let us assume that it is not so; i.e., IC 1 IEE and IC 2 6= 0. If Q2 carries an appreciable current, then its base-emitter voltage must reach a typical value of, say, 0.8 V. With its base held at +1 V, the device therefore requires an emitter voltage of VP 0:2 V. However, this means that Q1 sustains a base-emitter voltage of Vin1 , VP = +2 V , 0:2 V = 1:8 V!! Since with VBE = 1:8 V, a typical transistor carries an enormous current, and since IC 1 cannot exceed IEE , we conclude that the conditions VBE1 = 1:8 V and VP 0:2 V cannot occur. In fact, with a typical base-emitter voltage of 0.8 V, Q1 holds node P at approximately +1:2 V, ensuring that Q2 remains off.

we can sketch the collector currents of Q1 and Q2 as a function of the input difference [Fig. Since VX and VY are differential. Vin2 . the transistor carrying the current lowers its collector voltage to VCC .15). That is. a nonzero differential input yields a nonzero differential output— a behavior in sharp contrast to the CM response.25) (10. Solution . What is the maximum allowable base voltage if the differential input is large enough to completely steer the tail current? Assume VCC = 2:5 V. (10. 10.23).25).cls v.24) IC 2 = IEE IC 1 = 0. Vin2 j becomes sufﬁciently large. Thus. 10 Differential Ampliﬁers Symmetry of the circuit implies that swapping the base voltages of situation [Fig.26) The above experiments reveal that.19). 2006] June 30.9(b)]. Given by VCC . From Eqs.” Example 10.10 Variation of (a) collector currents and (b) output voltages as a function of input.10(a)].14). based on Eqs. In fact. RC IEE = 2 V. (10.5 A bipolar differential pair employs a tail current of 0. and (10. It is also important to note that VX and VY vary differentially in response to Vin1 . If IEE is completely steered.21). (10.10(b). RC IEE VX = VCC : (10. we can sketch the input/output characteristics of the circuit as shown in Fig. giving Q1 and Q2 reverses the (10. and hence VY = VCC . Q2 Q1 Q1 Q2 Q1 Q2 I EE VCC I EE VCC − R C 2 VCC − R C I EE 0 (b) I C2 I C1 0 (a) I EE 2 VX VY V in1 − V in2 V in1 − V in2 Figure 10. 10. we can deﬁne a common-mode level for them. (10. 10. the base voltage must remain below this value so as to avoid saturation. the differential pair “steers” the tail current from one transistor to the other. this quantity is called the “output CM level. RC IEE =2. as the difference between the two inputs departs from zero. We have not yet formulated these characteristics but we do observe that the collector current of each transistor goes from 0 to IEE if jVin1 . and (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.23) (10.5 mA and a collector resistance of 1 k . 2007 at 13:42 474 (1) 474 Chap.

10. the net decrease in VBE 2 is equal to V (10.28) that IC 1 must be equal to .28) How is I related to V ? If the emitters of Q1 and Q2 were directly tied to ground. I: I = C2 (10. since IC 1 + IC 2 = IEE . 2007 at 13:42 475 (1) Sec.11 (a) Differential pair sensing small.30) IC 2 = . yielding (10.27) (10. IC 2 decreases by the same amount: VCC RC + ∆V RC Y Q1 P I EE (a) (b) + ∆V X Q2 X Q1 P Q2 Y VCM − ∆V VCM VCM − ∆V VCM ∆VP I EE Figure 10.29) + VP . 10. 2006] June 30.27) and (10. VP : Similarly. VP and hence 2 IC 1 = gm V . As a result. As illustrated in Fig. 10. the base voltage of Q1 is raised from VCM by V while that of Q2 is lowered from VCM by the same amount.32) Interestingly. we “zoom in” around Vin1 .2 Bipolar Differential Pair 475 Exercise Repeat the above example if the tail current is raised to 1 mA. then I would simply be equal to gm V . We surmise that IC 1 increases slightly and.11(b). We must therefore compute the change in VP . Suppose. differential input changes. In the last step of our qualitative analysis. dictating that gm V .IC 2 . as shown in Fig. Vin2 = 0 (the equilibrium condition) and study the circuit’s behavior for a small input difference. (b) hypothetical change at P .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VP = gm V + VP and hence (10. IC 1 = IEE + I 2 IEE . VP rises by VP .11(a). the tail voltage remains constant if the two inputs vary differentially and by a small amount—an observation critical to the small-signal analysis of the circuit.gmV + VP : But recall from (10. . node P is free to rise or fall.31) VP = 0: (10. the net increase in VBE 1 is equal to V . In the differential pair.cls v. however.

providing a transconductance of 0:25 mA=26 mV = 104 .gmV RC VY = gmV RC : The differential output therefore goes from 0 to (10. 10. Q1 and Q2 carry signiﬁcantly different currents.31).42) = 1040 : Exercise Redesign the circuit for a power budget of 0.6 Design a bipolar differential pair for a gain of 10 and a power budget of 1 mW with a supply voltage of 2 V.11(a).36) VX . With VP = 0 in Fig. 2007 at 13:42 476 (1) 476 Chap. Which one of the above equations is violated? For a large differential input.41) (10. VY = . It follows that Solution RC = jAV j g m (10.25 mA near equilibrium. 2006] June 30.29) and (10.5 mW and compare the results. the power budget translates to a tail current of 0.34) VX = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. With VCC = 2 V. .40) (Note that the change in the differential input is equal to 2V .38) (10.33) (10.) This expression is similar to that of the common-emitter stage.gmRC : (10.2gmV RC : We deﬁne the small-signal differential gain of the circuit as (10.37) Av = Change in Di erential Output Change in Di erential Input .2gmV RC = 2V = . Each transistor thus carries a current of 0.35) (10.30) respectively as IC 1 = gm V IC 2 = .gmV and (10.39) (10. thus exhibiting unequal transconductances and prohibiting the omission of gm ’s from the two sides of (10. 10 Differential Ampliﬁers The reader may wonder why (10. Example 10.32) does not hold if V is large. we can rewrite (10.cls v.5 mA.1 .

Not having seen any large-signal analysis in the previous chapters. where gm1. compare their voltage gains.2 RC .46) where IEE =2 is the bias current of each transistor in the differential pair. and supply voltages. In order to derive the relationship between the differential input and output of the circuit.2 Bipolar Differential Pair 477 Example 10. 10. In other words.45) IEE = IC .48) (10. 2007 at 13:42 477 (1) Sec.10).cls v.7 Compare the power dissipation of a bipolar differential pair with that of a CE stage if both circuits are designed for equal voltage gains. 10.49) . Our interest arises from (a) the need to understand the circuit’s limitations in serving as a linear ampliﬁer. we ﬁrst note from Fig.2 RC = gm RC and hence (10.2 denotes the transconductance of each of the two transistors.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.43) jAV. 2VT VT (10.47) indicating that the differential pair consumes twice as much power.2. For a CE stage (10.44) gm1. IEE = 2IC . and IC represents the bias current of the CE stage.CE j = gmRC : Thus. and (b) the application of the differential pair as a (nonlinear) current-steering circuit.2 Large-Signal Analysis Having obtained insight into the operation of the bipolar differential pair. Solution The gain of the differential pair is written from (10.40) as jAV.12 that Vout1 = VCC . Exercise If both circuits are designed for the same power budget. RC IC 1 Vout2 = VCC . RC IC 2 (10. (10. collector resistances. This is one of the drawbacks of differential circuits. we now quantify its large-signal behavior. (10. and equal supply voltages. the reader may naturally wonder why we are suddenly interested in this aspect of the differential pair. 2006] June 30. aiming to formulate the input/output characteristic of the circuit (the sketches in Fig.di j = gm1. 10. equal collector resistances.

and recalling from Chapter 4 that VBE = VT lnIC =IS .51) We must therefore compute IC 1 and IC 2 in terms of the input difference. 10 Differential Ampliﬁers VCC RC V out1 V in1 Q1 P I EE Vout Q2 RC Vout2 Vin2 Figure 10. VT ln IC 2 IS1 IS2 IC 1 : = VT ln I C2 Also. VBE2 . IC 2 exp Vin1 V Vin2 + IC 2 = IEE T and.56) contain two unknowns. VBE2 = VT ln IC 1 . Substituting for IC 1 from (10. Assuming = 1 and VA = 1. Vin1 . 2006] June 30.52) Vin1 . : 1 + exp Vin1 V Vin2 T The symmetry of the circuit with respect to Vin1 and Vin2 and with respect to IC 1 and IC 2 suggests that IC 1 exhibits the same behavior as (10. VBE1 = VP = Vin2 . we write a KVL around the input network.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.55) in (10.58) .RC IC 1 .57) IEE (10. IC 2 : (10.58) but with the roles of Vin1 and Vin2 IC 2 = . Vout2 = .56) Equations (10. obtaining (10.53) (10.55) IC 1 + IC 2 = IEE : (10. a KCL at node P gives (10.56) yields . 2007 at 13:42 478 (1) 478 Chap. (10.50) (10.54) (10.55) and (10. and hence Vout = Vout1 .12 Bipolar differential pair for large-signal analysis. Vin2 = VBE1 . therefore.cls v.

67) (10. Vin2 = . Similarly. .5: In other words.cls v. Vin2 IEE exp V T = Vin1 . Example 10. In particular. and IEE can be considered steered completely to Q2 .62) . 10. IC 1 IEE :4:54 105 1 + 4 54 10.5 (10. 1 + exp Vin2 V Vin1 T Vin1 . Vin2 =VT ! 0 and IEE .10 4:54 10.64) IC 1 ! IEE IC 2 ! 0: IEE if Vin1 . 4:54 10. Vin2 : 1 + exp VT Alternatively. Vin2 is very positive. IC 1 = (10.61) (10. Q1 carries only 0:0045 of the tail current.58) in (10. Vin2 =VT ! 1 and as predicted by our qualitative analysis [Fig. if Vin1 . IEE exp Vin1 V Vin2 T (10. expVin1 .60) play a crucial role in our quantitative understanding of the differential pair’s operation. can we say IC 1 0 and IC 2 (10.5 .10VT ? Since exp.5 What is meant by “very” negative or positive? For example. if Vin1 (10.69) (10.70) .8 Solution We require that IC 1 = 0:02IEE . then expVin1 . 10.56) to obtain IC 1 .63) (10. the reader can substitute for IC 2 from (10. 2007 at 13:42 479 (1) Sec. Vin2 is very negative.9(b)].66) 4:54 10. Determine the differential input voltage that steers 98 of the tail current to one transistor.60) IC 1 ! 0 IC 2 ! IEE .59) (10.68) IEE 1 .58) and (10. (10.2 Bipolar Differential Pair 479 exchanged: Equations (10.65) (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2006] June 30.5IEE and IEE IC 2 1 + 4:54 10.

Solution For the sinusoids depicted in Fig. Vin2 : = . 2006] June 30. 10. IC 2 . and reaches a saturated level of . indicating that the differential output voltage begins from a “saturated” value of +RC IEE for a very negative differential input. we recognize that even a differential input of 4VT 104 mV “switches” the differential pair. Vin2 for relatively small values of jVin1 .13 summarizes the results. Vin2 1 + exp VT and (10.74) (10. Vin2 1 + exp VT Vin1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3:91VT : (10. RC IC 2 = VCC . thereby concluding that jVin1 .12. Vin2 j must remain well below this value for linear operation. gradually becomes a linear function of Vin1 .71) We often say a differential input of 4VT is sufﬁcient to turn one side of the bipolar pair nearly off. Vin2 becomes very positive.9 Sketch the output waveforms of the bipolar differential pair in Fig. From Example 10. we have Vout1 = VCC . : 1 + exp Vin1 V Vin2 T (10. RC IEE . 10. the circuit operates linearly because the maximum .14(a) in response to the sinusoidal inputs shown in Figs.RC IC 1 . Example 10. Vout2 = . Vin2 . RC Vin1 . 1 . Assume Q1 and Q2 remain in the forward active region.73) Vout2 = VCC .8. IEE exp Vin1 V Vin2 T = VCC .78) Figure 10. exp Vin1 V Vin2 T = RC IEE Vin1 . 10 Differential Ampliﬁers and hence Vin1 . Exercise What differential input is necessary to steer 90% of the tail current? For the output voltages in Fig.14(b) and (c). Vin2 j.cls v. 10.76) (10.77) (10.RC IEE tanh 2V T (10.72) (10. RC IC 1 . Note that this value remains independent of IEE and IS .RC IEE as Vin1 . 2007 at 13:42 480 (1) 480 Chap.75) Of particular importance is the output differential voltage: Vout1 .14(b). 10.

14 differential input is equal to 2 mV. as Vin1 approaches 50 mV above VCM and Vin2 reaches 50 mV below VCM (at t = t1 ). On the other hand. 2006] June 30. thus producing Vout1 VCC . 10. turning Q1 or Q2 off.14(c) force a maximum input difference of 200 mV. the sinusoids in Fig. The outputs are therefore sinusoids having a peak amplitude of 1 mV gm RC [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. RC IEE Vout2 VCC : (10.cls v.13 Variation of currents and voltages as a function of input. 2007 at 13:42 481 (1) Sec.80) . Q1 absorbs most of the tail current.2 Bipolar Differential Pair 481 I EE I C2 I C1 0 I EE 2 V in1 − V in2 VCC I EE VCC − R C 2 VCC − R C I EE V out1 V out2 0 V in1 − V in2 + R C I EE V out1 − V out2 0 V in1 − V in2 − R C I EE Figure 10. For example.14(d)]. Vin1 VCC RC V out1 V in1 Q1 P I EE Vout2 (a) Vin1 VCM Vin2 Vin2 t (b) 1 mV 100 mV RC Vout2 Q2 Vin2 VCM t1 (c) t Vout2 1 mV x g m R C VCC VCC − R C I EE 2 VCM Vout1 Vout1 t (d) VCC − R C I EE t t1 (e) Figure 10. 10.79) (10.

10. vin1 and vin2 represent small changes in each input and must satisfy vin1 = . v2 v1 + g v + v2 + g v = 0: r1 m1 1 r2 m2 2 With r1 = r2 and gm1 = gm2 . but the requirement is that the input signals not inﬂuence the bias currents of Q1 and Q2 appreciably.87) . In Problem 28.81) (10. 10. (10.vin2 for differential operation. The result is sketched in Fig. v1 = vP = vin2 . In other words.84) That is. we prove that this property holds in the presence of Early effect as well.14(e). With each half resembling a commonemitter stage.cls v. Since vP = 0.82) (10. In practice. Assuming perfect symmetry.86) Thus. We say the circuit operates as a “limiter” in this case. the tail node maintains a constant voltage (and hence is called a “virtual ground”). 10. Exercise What happens to the above results if the tail current is halved? 10. the outputs remain saturated until jVin1 . reducing the differential pair of Fig. Note that the tail current source is replaced with an open circuit. we construct the small-signal model of the circuit as shown in Fig.15(a) to two “half circuits” [Fig.83) = . v1 = 0: (10.vin2 .v2 and since vin1 (10.15(b)]. (10.32). 2007 at 13:42 482 (1) 482 Chap. Here. We also obtained a voltage gain equal to gm RC .gmRC vin1 (10.2.85) (10. playing a role similar to the diode limiters studied in Chapter 3.3 Small-Signal Analysis Our brief investigation of the differential pair in Fig. The virtual-ground nature of node P for differential small-signal inputs simpliﬁes the analysis considerably. We now study the small-signal behavior of the circuit in greater detail. the two transistors must exhibit approximately equal transconductances—the same condition required for node P to appear as virtual ground. 10.82) yields v1 = . and VA = 1. for small differential inputs. this node can be shorted to ac ground. 2006] June 30. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the deﬁnition of “small signals” is somewhat arbitrary. let us write a KVL around the input network and a KCL at node P : vin1 . an input difference of less than 10 mV is considered “small” for most applications. As explained in previous chapters. 10 Differential Ampliﬁers Thereafter.81) translates to 2vin1 = 2v1 : (10. an ideal tail current source. we can write vout1 = .11 revealed that. Vin2 j falls to less than 100 mV. vP = vin1 . As with the foregoing large-signal analysis.15(a). the small-signal model conﬁrms the prediction made by (10.

10.16(a). we may draw only one half.gmrO vin2 (10.g R .15(c). with the understanding that the incremental inputs are small and differential. Example 10. Thus. 10. the Early effect in Q1 and Q2 cannot be neglected.90) (10. we may draw the two half circuits as in Fig.cls v. where ideal current sources are used as loads to maximize the gain.40). 10. Solution vout1 = . and the half circuits must be visualized as depicted in Fig.2 Bipolar Differential Pair 483 RC v in1 r π1 vπ 1 g m1 RC vπ 1 P (a) g m2 vπ 2 vπ 2 r π2 v in2 RC v in1 r π1 vπ 1 g m1 RC vπ 1 g m2 vπ 2 vπ 2 r π2 v in2 (b) VCC RC RC V in1 Q1 (c) Q2 Vin2 Figure 10.15 (a) Small-signal model of bipolar pair. m C vin1 . For simplicity. vout2 = .88) vout1 .91) . vin2 (10.gmRC vin2 : It follows that the differential voltage gain of the differential pair is equal to (10.10 Compute the differential gain of the circuit shown in Fig. (b) simpliﬁed small-signal model. vout2 = . (c) simplied diagram. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 483 (1) Sec. With ideal current sources. 2006] June 30. since the two halves are identical.16(b).gmrO vin1 vout2 = .89) the same as that expressed by (10. Also.

VCC Vb Q3 V in1 Q1 P I EE (a) Q4 Vout Q2 Vin2 v in1 Q1 (b) Q3 v out Figure 10.cls v. vin2 where rON denotes the output impedance of the npn transistors.17(a) illustrates an implementation of the topology shown in Fig.g r : m O vin1 . Calculate the differential voltage gain. 2007 at 13:42 484 (1) 484 VCC Chap.g r jjr .17(b). 10 Differential Ampliﬁers v out Vout V in1 Q1 P I EE (a) (b) Q2 Vin2 v in1 Q1 r O1 r O2 Q2 v in2 Figure 10.16(a).11 Figure 10.93) . (10. 2006] June 30.17 Noting that each pnp device introduces a resistance of rOP at the output nodes and drawing the half circuit as in Fig. m ON OP vin1 . 10. Example 10. 10.92) Exercise Calculate the gain for VA = 5 V. vout2 = .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. vin2 (10. vout2 = . we have Solution vout1 .16 and hence vout1 .

12 VCC 1. This property holds for any other node that appears on the axis of symmetry. the signals need not be small in this case. 2007 at 13:42 485 (1) Sec. 10. We must emphasize that the differential voltage gain is deﬁned as the difference between the outputs divided by the difference between the inputs. R2 Q2 Vin2 V in1 Q3 Vout R1 Q1 (b) Figure 10. ∆V A Figure 10.cls v.19(b).18 R1 X R2 B ∆V Determine the differential gain of the circuit in Fig. we express the total resistance seen at the collector of Q1 as Rout = rO1 jjrO3 jjR1 : Thus.95) . As such. 10. 10. the voltage gain is equal to (10. this gain is equal to the singleended gain of each half circuit. 2006] June 30.18 create a virtual ground at X if (1) R1 = R2 and (2) nodes A and B vary by equal and opposite amounts. the two resistors shown in Fig.19 Solution Drawing one of the half circuits as shown in Fig. (10. We assume perfect symmetry in each case.2 Bipolar Differential Pair 485 Exercise Calculate the gain if Q3 and Q4 are conﬁgured as diode-connected devices.19(a) if VA Vb Q3 Q4 Vout R1 V in1 Q1 P I EE (a) Example 10.2 Additional examples make this concept clearer.94) Av = . 10. the symmetry of the circuit (gm1 = gm2 ) establishes a virtual ground at node P in Fig.gm1rO1 jjrO3 jjR1 : 2 Since the resistors are linear. We now make an observation that proves useful in the analysis of differential circuits. As noted above.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.12 if the incremental inputs are small and differential. 10. For example.

10.gm1rO1 jjrO3 jjR1 : (10.21(a). This is because Q3 and Q4 experience a constant base-emitter voltage in both cases. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.21(a) and (b). 10 Differential Ampliﬁers Exercise Repeat the above example if R1 6= R2 . thereby serving as current sources and exhibiting only an output resistance. Calculate the differential gain of the circuit illustrated in Fig.20(b)—the same as that in the above example. It follows that Solution Av = . 10.20(a) if VA VCC X Q3 R1 Vout V in1 Q1 P I EE (a) (b) Example 10. node P is a virtual ground. VX remains constant. 10. yielding the half circuit depicted in Solution . Example 10. X Q4 R2 Q2 Vin2 v in1 Q3 R1 v out1 Q1 Figure 10. R1 = R2 = 10 k . In the topology of Fig.13 1. Assume VA = 1. leading to the conceptual half circuit shown in Fig. 2007 at 13:42 486 (1) 486 Chap. and IEE = 1 mA.cls v.20 For small differential inputs and outputs.96) Exercise Calculate the gain if VA = 4 V for all transistors.14 Determine the gain of the degenerated differential pairs shown in Figs. 2006] June 30.

RERC 1 : 2 + gm (10. It follows that Av = .97) m In the circuit of Fig. RE + g1 RC : (10. 10.21 Fig. From Chapter 5.2 Bipolar Differential Pair VCC RC X Vout Q1 RE P Q2 RE I EE (a) 487 VCC RC X Vin2 V in1 Q1 RE Vout Q2 RC Y Vin2 RC Y V in1 I EE I EE (b) RC v out v in1 Q1 RE (c) RC v out v in1 Q1 RE 2 (d) Figure 10. the line of symmetry passes through the “midpoint” of RE . we have Av = . 10. we have v 1 v 2 rpi1 = iX = . 10.22(b). 10. Exercise Design each circuit for a gain of 5 and power consumption of 2 mW. From the equivalent circuit in Fig.22(a). In other words.21(d)]. r2 : (10.21(b). if RE is regarded as two RE =2 units in series. then the node between the units acts as a virtual ground [Fig. = 2:5 V. 2006] June 30.98) The two circuits provide equal gains if the pair in Fig.21(b) incorporates a total degeneration resistance of 2RE . I/O Impedances For a differential pair.99) . 10. Assume VCC VA = 1.21(c). we can deﬁne the input impedance as illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. 2007 at 13:42 487 (1) Sec. 10. and RE = 2=gm.cls v.

v2 = 2r1 iX : It follows that (10.102) but proves useful in some calculations. Also. 10. 10 Differential Ampliﬁers VCC RC iX Q1 Q2 r π1 vπ 1 g m1 RC iX RC vπ 1 P g m2 RC vπ 2 vπ 2 iX r π2 vX I EE vX (a) (b) Figure 10.23 Calculation of single-ended input impedance. .23). The above quantity is called the “differential input impedance” of the circuit. 2007 at 13:42 488 (1) 488 Chap.22 (a) Method for calculation of differential input impedance. For this reason. the reader can show that the differential and single-ended output impedances are equal to 2RC and RC .3 MOS Differential Pair Most of the principles studied in the previous section for the bipolar differential pair apply directly to the MOS counterpart as well. In a manner similar to the foregoing development.102) as if the two base-emitter junctions appear in series. 2006] June 30. respectively.101) vX = 2r . We continue to assume perfect symmetry. vX = v1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. pi1 iX (10. our treatment of the MOS circuit in this section is more concise.103) This result provides no new information with respect to that in (10.100) (10. It is also possible to deﬁne a “single-ended input impedance” with the aid of a half circuit (Fig.cls v. obtaining VCC RC iX Q1 vX Figure 10. vX = r : iX 1 (10. (b) equivalent circuit of (a).

it is useful to compute the “equilibrium overdrive voltage” of M1 and M2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.107). We assume = 0 and hence ID = 1=2nCox W=LVGS . The circuit thus rejects input CM variations. and VDD = 1:8 V. RD ISS 2 VCM . VTH = 0:5 A MOS differential pair is driven with an input CM level of 1.cls v.104) VX = VY = VDD .109) . VTH 2 .6 V.3. VTH equil: = u ISS W : t n Cox L (10. = ID2 = ISS =2. what is the maximum allowable load resistance? Example 10.105) That is.24 Response of MOS differential pair to input CM variation. RD ISS =2. 2007 at 13:42 489 (1) Sec. VTH : VDD . we require that their drain voltages not fall below VCM . VGS . a greater tail current or a smaller W=L translates to a larger equilibrium overdrive. For our subsequent derivations.1 Qualitative Analysis Figure 10. VCM + VTH ISS 2:8 k : (10.106) As expected.3 MOS Differential Pair 489 10. a zero differential input gives a zero differential output. leaving VX and = 0:5 mA.107) It can also be observed that a change in VCM cannot alter ID1 VY undisturbed. Carrying a current of ISS =2. 2006] June 30. VTH equil: . 10. each device exhibits an overdrive of v u VGS .108) (10. VTH : (10. If ISS V.15 Solution From (10. we have RD 2 VDD . RD ISS : 2 (10. yielding VDD RD X M1 V CM I SS M2 RD Y Figure 10. Note that the output CM level is equal to VDD .24(a) depicts the MOS pair with the two inputs tied to VCM . To guarantee that M1 and M2 operate in saturation. ID1 = ID2 = ISS 2 and (10.

(c) qualitative plots of currents and voltages. Figure 10. It follows that . (10.113) The circuit therefore steers the tail current from one side to the other. Exercise What is the maximum tail current if the load resistance is 5 k . 10. as explained later. Let us now examine the circuit’s behavior for a small input difference. VX = VDD .25(b)].25(a)]. 2006] June 30. generating VDD RD Vout X V in1 M1 M2 I SS (a) (b) VDD RD Vout Y RD RD Y Vin2 V in1 X M1 M2 Vin2 I SS I SS I D2 I D1 0 I SS 2 VX VY VDD I SS VDD − R D 2 VDD − R D I SS 0 V in1 − V in2 (c) V in1 − V in2 Figure 10.25(c) sketches the characteristics of the circuit.25 illustrates the response of the MOS pair to large differential inputs.111) VX = VDD VY = VDD . then (10. RD ISS : (10. then M1 carries the entire tail current. Figure 10.27)-(10. If Vin1 is well above Vin2 [Fig.26(a).110) (10. 10 Differential Ampliﬁers We may suspect that this limitation in turn constrains the voltage gain of the circuit. such a scenario maintains VP constant because Eqs. RD ISS VY = VDD : Similarly. 10. if Vin2 is well above Vin1 [Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.112) (10. Depicted in Fig. (b) response of MOS differential pair to very negative input. producing a differential output in response to a differential input.25 (a) Response of MOS differential pair to very positive input. 2007 at 13:42 490 (1) 490 Chap.32) apply to this case equally well. 10.

we have ISS = 1:11 mA: The output CM level (in the absence of signals) is equal to (10. 2007 at 13:42 491 (1) Sec. and VDD = 1:8 V.122) . (10. we must choose the transistor dimensions such that gm each transistor carries a drain current of ISS =2.120) Setting gm RD = 5.cls v.118) For VCM. each resistor must sustain a voltage drop of no more than 200 mV. Since (10.119) (10. similar to that of a common-source stage. = 0. the differential voltage gain is given by (10.117) Example 10.2gmRD V: As expected.121) gm = 2n Cox W ISS . 10.gmV and (10.16 Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2 mW subject to the condition that the stage following the differential pair requires an input CM level of at least 1.116) Av = .gmRD .6 V. Assume n Cox = 100 A=V2 .115) VX .out = 1:6 V. = 5=360 . Solution From the power budget and the supply voltage.3 MOS Differential Pair VDD RD + ∆V 491 RD Y M1 P I SS M2 VCM − ∆V X VCM Figure 10. thereby assuming a maximum value of VCM. RD ISS : 2 RD = 360 : (10.out = VDD .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.114) (10. L 2 and hence r W = 1738: L (10. VY = .26 Response of MOS pair to small differential inputs. 2006] June 30. ID1 = gm V ID2 = .

the input CM level can comfortably remain at VDD .out Figure 10. the constraint on the load resistor in this case arises from the output CM level requirement. 10. (a) For the two circuits to consume the same amount of power ID1 Solution = ISS = 2ID2 = 2ID3 . what voltage gain can be achieved? What is the maximum allowable input CM level in the above example if VTH Example 10.in I SS M2 VDD RD Y V CM. .e. Exercise Does the above result hold if VTH = 0:2 V.107) as VCM. (b) power dissipation for given transistor dimensions.27..in VDD . 2007 at 13:42 492 (1) 492 Chap. Example 10. discuss the choice of (a) transistor dimensions for a given power budget. If the two circuits are designed for the same voltage gain and the same supply voltage. 10.124) V CM.125) Interestingly.17 Solution = 0:4 V? We rewrite (10. 2006] June 30. In contrast to Example 10.out + VTH : This is conceptually illustrated in Fig. RD ISS + VTH 2 VCM.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. RD X M1 V CM.27 VCM. Thus.28 incorporate equal load resistors. 10 Differential Ampliﬁers The large aspect ratio arises from the small drop allowed across the load resistors.cls v.18 The common-source stage and the differential pair shown in Fig.5. i.123) (10.in V TH (10. Exercise If the aspect ratio must remain below 200.in 2 V: (10.

ID2 : (10. Vout = Vout1 . From Fig.126) (10.3.29 MOS differential pair for large-signal analysis. (b) If the transistors in both circuits have the same dimensions.129) . doubling the power consumption. ID2 . 2006] June 30. we neglect channel-length modulation and write a KVL around the input network and a KCL at the tail node: Vin1 . Exercise Discuss the above results if the CS stage and the differential pair incorporate equal source degeneration resistors.128) (10.cls v.3 MOS Differential Pair VDD R V in1 v in M1 M1 M2 I SS R Vin2 493 VDD R Figure 10. VGS1 = Vin2 . VGS2 ID1 + ID2 = ISS : (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.28 each transistor in the differential pair carries a current equal to half of the drain current of the CS transistor. 10.121) therefore requires that the differential pair transistors be twice as wide as the CS device to obtain the same voltage gain. VDD RD V out1 V in1 M1 Vout M2 I SS RD Vout2 Vin2 Figure 10.RD ID1 . Equation (10. 10. then the tail current of the differential pair must be twice the bias current of the CS stage for M1 -M3 to have the same transconductance. Vout2 = .29.2 Large-Signal Analysis As with the large-signal analysis of the bipolar pair. 10.127) To obtain ID1 . 2007 at 13:42 493 (1) Sec. our objective here is to derive the input/output characteristics of the MOS pair as the differential input varies from very negative to very positive values.

10 Differential Ampliﬁers Since ID = 1=2nCox W=LVGS . 2ISS : 2 4 L ID1 = ISS + Vin1 .131) (10.130) Substituting for VGS 1 and VGS 2 in (10. ID2 : p p (10.128).140) . p (10. 2 ID1 ID2 n Cox W L 2 I . n Cox W Vin1 . n Cox W Vin1 .136) 2 16ID1 ISS . Vin2 n Cox W 4ISS .135) (10. VGS2 n Cox L 2 W ID1 . Vin2 2 .cls v. 2007 at 13:42 494 (1) 494 Chap. we have Vin1 . Vin2 2 = We now ﬁnd pI I . Vin2 2 : L (10. D1 D2 ID1 + ID2 .132) Squaring both sides yields Vin1 .134) 4 ID1 ID2 = 2ISS . L square the result again.138) and hence 2 2 ID1 = ISS 1 4ISS . 2006] June 30.133) (10. L and substitute ISS . we show that only the solution with the sum of the two terms is acceptable: s (10. VTH 2 . u VGS = VTH + u 2ID W : t n Cox L v u =u t 2 v (10. Vin2 2 : 2 4 L L s (10. Vin2 2 . ID1 = 2ISS . 16ISS ID1 + 2ISS . Vin2 2 = 0 D1 L (10. Vin2 2 . n Cox W Vin1 . ID1 for ID2 . n Cox W Vin1 . n Cox W Vin1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.139) In Problem 44. 2 16ID1 ID2 = 2ISS . Vin2 = VGS1 . 2pI I : = SS D1 D2 n Cox W L p (10. n Cox W Vin1 .137) It follows that 16I 2 2 .

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495 (1)

Sec. 10.3

MOS Differential Pair

495

The symmetry of the circuit also implies that

**ID2 = ISS + Vin2 , Vin1 n Cox W 4ISS , n Cox W Vin2 , Vin1 2 : 2 4 L L
**

That is,

s

(10.141)

**u ID1 , ID2 = 1 n Cox W Vin1 , Vin2 u 4ISSW , Vin1 , Vin2 2 : t 2 L C
**

n ox

v

(10.142)

L

Equations (10.140)-(10.142) form the foundation of our understanding of the MOS differential pair. Let us now examine (10.142) closely. As expected from the characteristics in Fig. 10.25(c), the right-hand side is an odd (symmetric) function of Vin1 , Vin2 , dropping to zero for a zero input difference. But, can the difference under the square root vanish, too? That would suggest that ID1 , ID2 falls to zero as Vin1 , Vin2 2 reaches 4ISS =n Cox W=L , an effect not predicted by our qualitative sketches in Fig. 10.25(c). Furthermore, it appears that the argument of the square root becomes negative as Vin1 , Vin2 2 exceeds this value! How should these results be interpreted? Implicit in our foregoing derivations is the assumption that both transistors are on. However, as jVin1 , Vin2 j rises, at some point that M1 or M2 turns off, violating the above equations. We must therefore determine the input difference that places one of the transistors at the edge of conduction. This can be accomplished by equating (10.140), (10.141), or (10.142) to ISS , but leading to lengthy algebra. Instead, we recognize from Fig. 10.30 that if, for example, M1

Edge of Conduction + ~0

I SS M2

− I SS + VGS2

M1 VTH

−

Figure 10.30 MOS differential pair with one device off.

approaches the edge of conduction, then its gate-source voltage falls to a value equal to VTH . Also, the gate-source voltage of M2 must be sufﬁciently large to accommodate a drain current of ISS :

VGS1 = VTH

**v u VGS2 = VTH + u 2ISSW : t n Cox
**

L

It follows from (10.128) that

(10.143) (10.144)

**v u jVin1 , Vin2 jmax = u 2ISSW ; t n Cox
**

L

(10.145)

where jVin1 , Vin2 jmax denotes the input difference that places one transistor at the edge of conduction. Equation (10.145) is invalid for input differences greater than this value. Indeed,

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496 (1)

496

Chap. 10

Differential Ampliﬁers

substituting from (10.145) in (10.142) also yields jID1 , ID2 j = ISS . We also note that jVin1 , Vin2 jmax can be related to the equilibrium overdrive [Eq. (10.106)] as follows:

p jVin1 , Vin2 jmax = 2VGS , VTH equil: :

(10.146)

The above ﬁndings are very important and stand in contrast to the behavior of the bipolar differential pair and Eq. (10.78): the MOS pair steers all of the tail current3 for jVin1 , Vin2 jmax whereas the bipolar counterpart only approaches this condition for a ﬁnite input difference. Equation (10.146) provides a great deal of intuition into the operation of the MOS pair. Speciﬁcally, we plot ID1 and ID2 as in Fig. 10.31(a), where Vin = Vin1 , Vin2 , arriving at the differential characteristics in Figs. 10.31(b) and (c). The circuit thus behaves linearly for small values of Vin and becomes completely nonlinear for Vin Vin;max . In other words, Vin;max serves as an absolute bound on the input signal levels that have any effect on the output.

I SS I D2 I D1

− ∆V in,max 0 (a)

I SS

2 + ∆V in,max + I SS

V in1 − V in2

I D1 − I

D2

+ ∆V in,max 0 − I SS (b)

− ∆V in,max

V in1 − V in2

V out1 − V out2

+ R D I SS − ∆V in,max 0 (c) + ∆V in,max − R D I SS

V in1 − V in2

Figure 10.31 Variation of (a) drain currents, (b) the difference between drain currents, and (c) differential output voltage as a function of input.

Example 10.19

Examine the input/output characteristic of a MOS differential pair if (a) the tail current is doubled, or (b) the transistor aspect ratio is doubled. (a) Equation (10.145) suggests that doubling ISS increases Vin;max by a factor of 2. Thus, the characteristic of Fig. 10.31(c) expands horizontally. Furthermore, since ISS RD doubles, the characteristic expands vertically as well. Figure 10.32(a) illustrates the result, displaying a greater slope.

Solution

p

3 In reality, MOS devices carry a small current for illustration.

VGS = VTH , making these observations only an approximate

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497 (1)

Sec. 10.3

**MOS Differential Pair
**

V out1 − V out2

+2R D I SS + R D I SS + ∆V in,max − 2 ∆V in,max − ∆V in,max − R D I SS −2 R D I SS (a) + 2 ∆V in,max

497

V in1 − V in2

V out1 − V out2

+ R D I SS − ∆V in,max − ∆V in,max 2 − R D I SS (b) + ∆V in,max 2

V in1 − V in2

+ ∆V in,max

Figure 10.32

(b) Doubling W=L lowers Vin;max by a factor of 2 while maintaining ISS RD constant. The characteristic therefore contracts horizontally [Fig. 10.32(b)], exhibiting a larger slope in the vicinity of Vin = 0.

p

Exercise

Repeat the above example if (a) the tail current is halved, or (b) the transistor aspect ratio is halved.

Example 10.20

Design an NMOS differential pair for a power budget of 3 mW and Assume n Cox = 100 A=V2 and VDD = 1:8 V.

Vin;max = 500 mV.

The tail current must not exceed 3 mW=1:8 V = 1:67 mA. From Eq. (10.145), we write

Solution

**2ISS W= 2 L n Cox Vin;max = 133:6:
**

The value of the load resistors is determined by the required voltage gain.

(10.147) (10.148)

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498 (1)

498

Chap. 10

Differential Ampliﬁers

Exercise

How does the above design change if the power budget is raised to 5 mW?

10.3.3 Small-Signal Analysis The small-signal analysis of the MOS differential pair proceeds in a manner similar to that in Section 10.2.3 for the bipolar counterpart. The deﬁnition of “small” signals in this case can be seen from Eq. (10.142); if

jVin1 , Vin2 j

then

n Cox L

4ISS ; W

(10.149)

u 1 ID1 , ID2 2 n Cox W Vin1 , Vin2 u 4ISSW t L n Cox L r = n Cox W ISS Vin1 , Vin2 : L

v

(10.150)

(10.151)

Now, the differential inputs and outputs are linearly proportional, and the circuit operates linearly. We now use the small-signal model to prove that the tail node remains constant in the presence of small differential inputs. If = 0, the circuit reduces to that shown in Fig. 10.33(a), yielding

RD v in1 v1 g v m1 1 P (a) RC v in1 v1 g v m1 1 g v m2 2 RC v2 v in2 g v m2 2 RD v2 v in2

(b)

Figure 10.33 (a) Small-signal model of MOS differential pair, (b) simpliﬁed circuit.

**vin1 , v1 = vin2 , v2 gm1 v1 + gm2 v2 = 0:
**

Assuming perfect symmetry, we have from (10.153)

(10.152) (10.153)

v1 = ,v2

(10.154)

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499 (1)

Sec. 10.3

MOS Differential Pair

499

and for differential inputs, we require vin1

= ,vin2 . Thus, (10.152) translates to

vin1 = v1

and hence

(10.155)

vP = vin1 , v1

=0

(10.156) (10.157)

Alternatively, we can simply utilize Eqs. (10.81)-(10.86) with the observation that v =r = 0 for a MOSFET, arriving at the same result. With node P acting as a virtual ground, the concept of half circuit applies, leading to the simpliﬁed topology in Fig. 10.33(b). Here,

**vout1 = ,gmRD vin1 vout2 = ,gmRD vin2 ;
**

and, therefore,

(10.158) (10.159)

**vout1 , vout2 = ,g R : m D vin1 , vin2
**

Example 10.21

Prove that (10.151) can also yield the differential voltage gain. Since Vout1 , Vout2 from (10.151)

(10.160)

Solution

= ,RD ID1 , ID2 and since gm = n Cox W=LISS (why?), we have

p

Vout1 , Vout2 = ,RD n Cox W ISS Vin1 , Vin2 L = ,gm RD Vin1 , Vin2 :

r

(10.161) (10.162)

This is, of course, to be expected. After all, small-signal operation simply means approximating the input/output characteristic [Eq. (10.142)] with a straight line [Eq. (10.151)] around an operating point (equilibrium).

Using the equation gm overdive voltage.

Exercise

= 2ID =VGS , VTH , express the above result in terms of the equilibrium

As with the bipolar circuits studied in Examples 10.10 and 10.14, the analysis of MOS differential topologies is greatly simpliﬁed if virtual grounds can be identiﬁed. The following examples reinforce this concept. Determine the voltage gain of the circuit shown in Fig. 10.34(a). Assume 6= 0.

Example 10.22

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500 (1)

500

VDD M3 Vout V in1 M1 M2 I SS

(a)

Chap. 10

Differential Ampliﬁers

M4 M3 Vin2 v in1 v out1 M1

(b)

Figure 10.34

Solution

Drawing the half circuit as in Fig. 10.34(b), we note that the total resistance seen at the drain of M1 is equal to 1=gm3jjrO3 jjrO1 . The voltage gain is therefore equal to

Av = ,gm1 g 1 jjrO3 jjrO1 : m3

(10.163)

Exercise

Repeat the above example if a resistance of value R1 is inserted in series with the sources of M3 and M4 .

**Assuming = 0, compute the voltage gain of the circuit illustrated in Fig. 10.35(a).
**

VDD

Example 10.23

**Vout V in1 P I SS1
**

(a)

M3 Q

M4

Vin2 v out1

I SS2

v in1

M1 M3

(b)

Figure 10.35

Identifying both nodes P and Q as virtual grounds, we construct the half circuit shown in Fig.

Solution

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501 (1)

Sec. 10.4

Cascode Differential Ampliﬁers

501

10.35(b), and write

g Av = , gm1 :

m3

(10.164)

Exercise

Repeat the above example if 6= 0.

**Assuming = 0, calculate the voltage gain of the topology shown in Fig. 10.36(a).
**

VDD

Example 10.24

Vout R DD R SS

R DD

2

**v out1 M2 Vin2 v in1 M1 R SS
**

2

V in1

M1

(a)

(b)

Figure 10.36 .

Grounding the midpoint of RSS and RDD , we obtain the half circuit in Fig. 10.36(b), where

Solution

Av = , RSS 2 1 : 2 + gm

Exercise

RDD

(10.165)

Repeat the above example if the load current sources are replaced with diode-connected PMOS devices.

**10.4 Cascode Differential Ampliﬁers
**

Recall from Chapter 9 that cascode stages provide a substantially higher voltage gain than simple CE and CS stages do. Noting that the differential gain of differential pairs is equal to the single-

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502 (1)

502

Chap. 10

Differential Ampliﬁers

ended gain of their corresponding half circuits, we surmise that cascoding boosts the gain of differential pairs as well. We begin our study with the structure depicted in Fig. 10.37(a), where Q3 and Q4 serve as cascode devices and I1 and I2 are ideal. Recognizing that the bases of Q3 and Q4 are at ac ground, we construct the half circuit shown in Fig. 10.37(b). Equation (9.51) readily gives the gain as

VCC I1 Vout Q3 Vb V in1 Q1 Q2 Vin2 v in1 I EE

(a) (b)

I2

Q4 Q3

v out1

Q1

Figure 10.37 (a) Bipolar cascode differential pair, (b) half circuit of (a).

Av = ,gm1 gm3 rO1 jjr3 rO3 + rO1 jjr3 ;

(10.166)

conﬁrming that a differential cascode achieves a much higher gain. The developments in Chapter 9 also suggest the use of pnp cascodes for current sources I1 and I2 in Fig. 10.37(a). Illustrated in Fig. 10.38(a), the resulting conﬁguration can be analyzed with the aid of its half circuit, Fig. 10.38(b). Utilizing Eq. (9.61), we express the voltage gain as V

CC

**V b3 Q7 V b2 Q5 Q3 V b1 V in1 Q1 Q2 Vin2 v in1 I EE
**

(a) (b)

Q8 Q6 Vout Q4 Q7 Q5 Q3 v out1

Q1

Figure 10.38 (a) Bipolar cascode differential pair with cascode loads, (b) half circuit of (a).

Av ,gm1 gm3 rO3 rO1 jjr3 jj gm5 rO5 rO7 jjr5 :

(10.167)

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503 (1)

Sec. 10.4

Cascode Differential Ampliﬁers

503

Called a “telescopic cascode,” the topology of Fig. 10.38(b) exempliﬁes the internal circuit of some operational ampliﬁers. Due to a manufacturing defect, a parasitic resistance has appeared between nodes A and the circuit of Fig. 10.39(a). Determine the voltage gain of the circuit.

VCC V b3 Q7 A V b2 Q5 Q3 V b1 V in1 Q1 Q2 Vin2 v in1 I EE

(a) (b)

Example 10.25

B in

Q8 B R1 Q6 Vout Q4 Q7 Q5 Q3 R1

2

v out1

Q1

Figure 10.39

The symmetry of the circuit implies that the midpoint of R1 is a virtual ground, leading to the half circuit shown in Fig. 10.39(b). Thus, R1 =2 appears in parallel with rO7 , lowering the output impedance of the pnp cascode. Since the value of R1 is not given, we cannot make approximations and must return to the original expression for the cascode output impedance, Eq. (9.1):

Solution

R1 r + r jjr jj R1 : Rop = 1 + gm5 rO7 jjr5 jj 2 O5 O7 5 2 Av = ,gm1 gm3 rO3 rO1 jjr2 jjRop :

(10.168)

The resistance seen looking down into the npn cascode remains unchanged and approximately equal to gm3 rO3 rO1 jjr2 . The voltage gain is therefore equal to (10.169)

If = 50 and VA = 4 V for all transistors and IEE gain by a factor of two?

Exercise

= 1 mA, what value of R1 degrades the

We now turn our attention to differential MOS cascodes. Following the above developments for bipolar counterparts, we consider the simpliﬁed topology of Fig. 10.40(a) and draw the half

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504 (1)

504

Chap. 10

Differential Ampliﬁers

**circuit as depicted in Fig. 10.40(b). From Eq. (9.69),
**

VDD

M3 V b1 V in1

Vout M4 M1 M2 I SS

(a)

M3 Vin2 v in1

v out1

M1

(b)

Figure 10.40 (a) MOS cascode differential pair, (b) half circuit of (a).

Av ,gm3rO3 gm1 rO1 :

(10.170)

Illustrated in Fig. 10.41(a), the complete CMOS telescopic cascode ampliﬁer incorporates PMOS cascades as load current sources, yielding the half circuit shown in Fig. 10.41(b). It follows from Eq. (9.72) that the voltage gain is given by

V b3 V b2 M5 M3 V b1 V in1 M1 M2 I SS

(a) (b)

M7

M8

VDD M7

M6 Vout M4 Vin2 v in1

M5 M3 v out1

M1

Figure 10.41 (a) MOS telescopic cascode ampliﬁer, (b) half circuit of (a).

**Av ,gm1 gm3 rO3 rO1 jjgm5 rO5 rO7 :
**

Example 10.26

Due to a manufacturing defect, two equal parasitic resistances, shown in Fig. 10.42(a). Compute the voltage gain of the circuit.

(10.171)

R1 and R2 , have appeared as

Noting that R1 and R2 appear in parallel with rO5 and rO6 , respectively, we draw the half circuit as depicted in Fig. 10.42(b). Without the value of R1 given, we must resort to the original expression for the output impedance, Eq. (9.3):

Solution

Rp = 1 + gm5 rO5 jjR1 rO7 + rO5 jjR1 :

(10.172)

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505 (1)

Sec. 10.5

**Common-Mode Rejection
**

M7 M8 VDD M7 Vb2 M6 M5 M4 M1 M2 I SS

(a) (b)

505

V b3 V b2

M5 M3 V b1 V in1

R1

R2

R1 v out1

Vout

M3 Vin2 v in1

M1

Figure 10.42

The resistance seen looking into the drain of the NMOS cascode can still be approximated as

**Rn gm3 rO3 rO1 :
**

The voltage gain is then simply equal to

(10.173)

Av = ,gm1 Rp jjRn :

(10.174)

Exercise

Repeat the above example if in addition to the sources of M3 and M4 .

R1 and R2 , a resistor of value R3 appears between

**10.5 Common-Mode Rejection
**

In our study of bipolar and MOS differential pairs, we have observed that these circuits produce no change in the output if the input CM level changes. The common-mode rejection property of differential circuits plays a critical role in today’s electronic systems. As the reader may have guessed, in practice the CM rejection is not inﬁnitely high. In this section, we examine the CM rejection in the presence of nonidealities. The ﬁrst nonideality relates to the output impedance of the tail current source. Consider the topology shown in Fig. 10.43(a), where REE denotes the output impedance of IEE . What happens if the input CM level changes by a small amount? The symmetry requires that Q1 and Q2 still carry equal currents and Vout1 = Vout2 . But, since the base voltages of both Q1 and Q2 rise, so does VP . In fact, noting that Vout1 = Vout2 , we can place a short circuit between the output nodes, reducing the topology to that shown in Fig. 10.43(b). That is, as far as node P is concerned, Q1 and Q2 operate as an emitter follower. As VP increases, so does the current through REE and hence the collector currents of Q1 and Q2. Consequently, the output common-mode level falls. The change in the output CM level can be computed by noting that the stage in Fig. 10.43(b) resembles a degenerated CE stage. That is, from Chapter 5,

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506 (1)

506

VCC RC V out1 Q1 V CM I EE P Q2 RC Vout2

Chap. 10

Differential Ampliﬁers

VCC Vout Q2 Q1 P I EE R EE

RC 2

V CM R EE

(a)

(b)

Figure 10.43 (a) CM response of differential pair in the presence of ﬁnite tail impedance, (b) simpliﬁed circuit of (a).

**Vout;CM = , 2 1 Vin;CM REE + 2g m =,
**

, 2REE + gm1

RC

(10.175)

RC

;

(10.176)

where the term 2gm represents the transconductance of the parallel combination of Q1 and Q2 . This quantity is called the “common-mode gain.” These observations apply to the MOS counterpart equally well. An alternative approach to arriving at (10.175) is outlined in Problem 65. In summary, if the tail current exhibits a ﬁnite output impedance, the differential pair produces an output CM change in response to an input CM change. The reader may naturally wonder whether this is a serious issue. After all, so long as the quantity of interest is the difference between the outputs, a change in the output CM level introduces no corruption. Figure 10.44(a) illustrates such a situation. Here, two differential inputs, Vin1 and Vin2 , experience some common-mode noise, Vin;CM . As a result, the base voltages of Q1 and Q2 with respect to ground appear as shown in Fig. 10.44(b). With an ideal tail current source, the input CM variation would have no effect at the output, leading to the output waveforms shown in Fig. 10.44(b). On the other hand, with REE 1, the single-ended outputs are corrupted, but not the differential output [Fig. 10.44(c)]. In summary, the above study indicates that, in the presence of input CM noise, a ﬁnite CM gain does not corrupt the differential output and hence proves benign.4 However, if the circuit suffers from asymmetries and a ﬁnite tail current source impedance, then the differential output is corrupted. During manufacturing, random “mismatches” appear between the two sides of the differential pair; for example, the transistors or the load resistors may display slightly different dimensions. Consequently, the change in the tail current due to an input CM variation may affect the differential output. As an example of the effect of asymmetries, we consider the simple case of load resistor mismatch. Depicted in Fig. 10.45(a) for a MOS pair,5 this imperfection leads to a difference between Vout1 and Vout2 . We must compute the change in ID1 and ID2 and multiply the result by RD and RD + RD .

4 Interestingly, older literature has considered this effect troublesome. 5 We have chosen a MOS pair here to show that the treatment is the same for both technologies.

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507 (1)

Sec. 10.5

Common-Mode Rejection

507

VCC RC Vout1 A V in1 Q1 P Q2 RC Vout2 B V in2

VA VB

VA VB

Vout1

Vout1

V CM

I EE

R EE

Vout2

Vout2

Vout1 −Vout2

Vout1 −Vout2

t

(a) (b) (c)

t

**1, (c) effect of CM noise at the output with REE 6= 1.
**

RD V out1

Figure 10.44 (a) Differential pair sensing input CM noise, (b) effect of CM noise at output with REE =

VDD R D + ∆R D Vout2 M1 P M2

∆V

V CM

I SS

R SS

Figure 10.45 MOS pair with asymmetric loads.

How do we determine the change in ID1 and ID2 ? Neglecting channel-length modulation, we ﬁrst observe that

1 ID1 = 2 n Cox W VGS1 , VTH 2 (10.177) L 1 ID2 = 2 n Cox W VGS2 , VTH 2 ; (10.178) L concluding that ID1 must be equal to ID2 because VGS 1 = VGS 2 and hence VGS 1 = VGS2 . In other words, the load resistor mismatch does not impact the symmetry of currents carried by M1 and M2 .6 Writing ID1 = ID2 = ID and VGS 1 = VGS 2 = VGS , we recognize that both ID1 and ID2 ﬂow through RSS , creating a voltage change of 2ID RSS

6 But with

6= 0, it would.

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508 (1)

508

Chap. 10

Differential Ampliﬁers

across it. Thus,

**VCM = VGS + 2ID RSS
**

and, since VGS

(10.179)

= ID =gm,

VCM = ID g1 + 2RSS : m

That is,

188) RC ACM .187) Determine ACM .DM . we strive to minimize this corruption by maximizing the output impedance of the tail current source.186) (This result can also be obtained through small-signal analysis.183) (10.185) RD Vout VCM = 1 + 2RSS : g m (10. thereby generating a differential output change of ID = 1 VCM : g + 2RSS m (10. (10. It is therefore reasonable to assume RSS 1=gm and R ACM . this current change ﬂows through both RD and RD +RD . Vout2 = ID RD .181) Vout = Vout1 . ID RD + RD = .189) .180) Produced by each transistor.46.) We say the circuit exhibits “common mode to differential mode (DM) conversion” and denote the above gain by ACM .186) yields (10.182) (10.DM for the circuit shown in Fig.ID RD = .27 Solution = 1 for Q1 and Q2 . 1 VCM RD : g + 2RSS m It follows that (10. 10. a bipolar current source may employ emitter degeneration and a MOS current source may incorporate a relatively long transistor.DM = 1 : + 2f 1 + gm3 R1 jjr3 rO3 + R1 jjr3 g gm1 (10. Assume VA Example 10. For example.184) (10. Recall from Chapter 5 that emitter degeneration raises the output impedance to Rout3 = 1 + gm3 R1 jjr3 rO3 + R1 jjr3 : Replacing this value for RSS in (10.DM 2R D : SS (10. In practice.

.cls v. .” CMRR serves as a measure of how much wanted signal and how much unwanted corruption appear at the output if the input consists of a differential component and common-mode noise. 1). Thus.46. 2006] June 30.28 Calculate the CMRR of the circuit in Fig.DM (10. Example 10.DM . While undesirable. This effect is beyond the scope of this book [1]. The mismatches between the transistors in a differential pair also lead to CM-DM conversion.190) Representing the ratio of “good” to “bad.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Solution For small mismatches (e. then the relative corruption at the output is small. CM-DM conversion cannot be simply quantiﬁed by ACM . If the circuit provides a large differential gain. and the differential gain is equal to gm1 RC .46 Exercise Calculate the above result if R1 ! 1. ADM .5 Common-Mode Rejection VCC RC V out1 Q1 V CM P R out3 Vb Q3 R1 Q2 R C + ∆R C Vout2 509 Figure 10.g.191) m CMRR = g1 RC g 1 + 2 1 + gm3 R1 jjr3 rO3 + 2R1 jjr3 : RC m1 Exercise Determine the CMRR if R1 ! 1. 2007 at 13:42 509 (1) Sec. RC RC . 10. We therefore deﬁne the “common-mode rejection ratio” (CMRR) as CMRR = A ADM : CM . 10. (10.

the output is sensed at node Y with respect to ground rather than with respect to node X . Q1 -Q2 . Shown in Fig. VCC RC V in1 V in2 Vout X V in1 V in2 RC Y Vout (a) (b) Figure 10.) The output is sensed with respect to ground. the circuit employs a symmetric differential pair. the internal circuits of such op amps must incorporate a stage that “converts” a differential input to a single-ended output.47(a)]. Here. 10.48. (b) possible implementation of (a). 7 In practice. Thus.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 510 (1) 510 Chap. To arrive at the circuit. We may naturally consider the topology shown in Fig.cls v. we study an interesting combination of differential pairs and current mirrors that proves useful in many applications. 10. (Transistors Q3 and Q4 are also identical.47(b) as a candidate for this task. Recall that the op amps used in Chapter 8 have a differential input but a single-ended output [Fig. the voltage gain is now halved because the signal swing at node X is not used. 10.48 Differential pair with active load. VCC Q3 N V in1 Q1 Q2 Vin2 Vout Q4 I EE Figure 10.47 (a) Circuit with differential input and single-ended output. We now introduce a topology that serves the task of “differential to single-ended” conversion while resolving the above issues. additional stages precede this stage so as to provide a high gain. Q3 -Q4 . .6 Differential Pair with Active Load In this section. along with a current-mirror load.7 Unfortunately. 10 Differential Ampliﬁers 10. 2006] June 30. let us ﬁrst address a problem encountered in some cases.

we recognize that the change in IC 3 is also equal to I . RL . 10. we observe that the fall in IC 2 translates to a rise in Vout because Q2 draws less current from RL . In other words.1 Qualitative Analysis It is instructive to ﬁrst decompose the circuit of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The load resistor.49(a) (along with a ﬁctitious load RL ). Q1 and Q2 produce equal and opposite changes in their collector currents in response to a differential ∆I R L V I EE 2 + ∆V + ∆I I EE 2 CC − ∆I RL Vb Q3 N − ∆V Q4 VCM Q1 P Q2 VCM I EE 2 + ∆I ∆I R L RL I EE (a) (b) Figure 10. is added to augment our intuition but it is not necessary for the actual operation. (b) response of active load to current change.6. jIC 3 j. 10. the voltage across RL changes by IRL . 10. With the input voltage changes shown here. in response to the differential input shown in Fig. Second. 2007 at 13:42 511 (1) Sec. Now consider the circuit in Fig.48 into two sections: the input differential pair and the current-mirror load. differential changes at the input and follow the signals to the output (Fig. VN changes by I=gm3 (for small I ). 2006] June 30. Neglecting the base currents of these two transistors.50. Ignoring the role of Q3 and Q4 for the moment. 10.49 (a) Response of input pair to input change. In order to understand the detailed operation of the circuit.49(b) and suppose the current drawn from Q3 increases from IEE =2 to IEE =2 + I . Vout rises. we note that IC 1 increases by some amount I and IC 2 decreases by the same amount. we apply small. change at the input.6 Differential Pair with Active Load 511 10. 10. and jIC 4 j increase by I . the collector current of Q4 also increases by I . since the small-signal impedance seen at node N is approximately equal to 1=gm3 . What happens? First. Since Q4 “injects” a greater current into the output node. Let us now determine how the change in IC 1 travels through Q3 and Q4 .cls v. The output change can therefore be an ampliﬁed version of V . IC 1 . 10. by virtue of current mirror action. VCC Q3 N I EE 2 + ∆V + ∆I Q4 I C4 I EE 2 − ∆I RL Vout VCM Q1 P Q2 VCM − ∆V I EE Figure 10. As a result. As depicted in Fig. . creating a voltage change of IRL across RL .50). This change is copied into IC 4 by virtue of the current mirror action.50 Detailed operation of pair with active load.

51 Signal paths in pair with active load. The foregoing analysis directly applies to the CMOS counterpart. 10. ID1 rises to ISS =2 + I and ID2 falls to ISS =2 . 10.) 10. differential input.52. each path forces Vout to increase. (In this circuit.53. 10. VCC Vb Q3 V in1 Q1 P I EE (a) Q4 Vout Q2 Vin2 Figure 10. the combination of Q3 and Q4 plays a critical role in the operation of the circuit. vout . . the circuit of Fig. we wish to determine the small-signal single-ended output. 10.2 Quantitative Analysis The existence of the signal paths in the differential to single-ended converter circuit suggests that the voltage gain of the circuit must be greater than that of a differential topology in which only one output node is sensed with respect to ground [e. VCC Q3 N V in1 Q1 Path 1 Path 2 Q4 Q2 Vin2 Vout I EE Figure 10. one through Q1 and Q2 and another through Q1 . which translates to a voltage change at the output node. the current mirror transistors are identical. Our initial examination of Q3 and Q4 in Fig. 10. 2007 at 13:42 512 (1) 512 Chap. 10. vin1 .51(a)]. The change in ID2 tends to raise Vout .52 Differential pair with current-source loads. divided by the smallsignal differential input. Specifically.47(b)].50 contains two signal paths. increasing jID4 j and raising Vout . For a differential input change. To conﬁrm this conjecture. 10. in response to a small.g. in the above example. too.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. I . The key point here is that the two paths enhance each other at the output. each path experiences a current change.50 indicates an interesting difference with respect to current mirrors studied in Chapter 9: here Q3 and Q4 carry signals in addition to bias currents. vin2 .cls v.52. shown in Fig. where the baseemitter voltage of the load transistors remains constant and independent of signals. Q3 and Q4 [Fig.54) to demonstrate that both CMOS and bipolar versions are treated identically. Fig.6. Also. 10. Called an “active load” to distinguish it from the load transistors in Fig. We deal with a CMOS implementation here (Fig.. This also stands in contrast to the current-source loads in Fig. the change in ID1 and ID3 is copied into ID4 . 10 Differential Ampliﬁers In summary. 2006] June 30.

we note that iX and iY must add up to zero at node P and hence iX = . Approach I Without a half circuit available. the analysis can be performed through the use of a complete small-signal model of the ampliﬁer. . M3 A V in1 M1 P I SS M2 VDD M4 Vout Vin2 Figure 10.54 MOS pair for small-signal analysis. we expect a relatively small voltage swing—on the order of the input swing—at this node.) The asymmetry resulting from the very different voltage swings at the drains of M1 and M2 disallows grounding node P for small-signal analysis.6 Differential Pair with Active Load VDD M3 + ∆V 513 M4 RL M1 M2 I SS − ∆V Vout Figure 10. the circuit is asymmetric.iY . we perform the analysis in two steps.55. On the other hand. The circuit of Fig. (After all. 2007 at 13:42 513 (1) Sec. 2006] June 30. 10. the circuit serves as an ampliﬁer. M3 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. In M3 1 g mP M4 g v mP A iY r ON r ON P g v mN 2 v2 M2 v in2 r OP vA iX g v mN 1 r OP v out A v in1 v1 M1 Figure 10. creating a low impedance at node A. Also. We present two approaches to solving this circuit. Referring to the equivalent circuit shown in Fig.53 MOS differential pair with active load.55 (a) Small-signal equivalent circuit of differential pair with active load. With the diodeconnected device.cls v. 10. the ﬁrst step. where the dashed boxes indicate each transistor. transistors M2 and M4 provide a high impedance and hence a large voltage swing at the output node.54 presents a quandary. While the transistors themselves are symmetric and the input signals are small and differential.

we have (10. then vout (10. vin2 + vout = 0: Substituting for vA and iX from above. gmN v2 . vin2 = gmN rON 2rON + 2rOP This is the exact expression for the gain. we ﬁrst seek a Thevenin equivalent for the section consisting of vin1 . Recall that vThev is the voltage between A and B in the “open-circuit condition” This section can be skipped in a ﬁrst reading.199) vin1 .iX gmP jjrOP and v . M1 and M2 .200) vin1 .1 vA = . v2 (10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. gmN v1 and that through rON of M2 equal to iY . If gmP rOP 1. iY .cls v. . gmN v2 rON + vout = 0: Since v1 . we write a KVL around the loop consisting of all four transistors.vA + iX . .195) In the second step. It follows that . vin2 . g i 1 jjr =r mP X g OP OP = iX : mP (10. Approach II In this approach. gmN v1 rON .194) Thus.196) = vin1 .vA + 2iX rON .193) (10.56(a). As illustrated in Fig.197) 1 vout 1 jjr gmP jjrOP + 2rON r 1 + g 1 jjr rOP 1 + gmP g OP mP g OP OP mP mP + vout = gmN rON vin1 . gmN rON vin1 . 2006] June 30. The current through rON of M1 is equal to iX .iY = r out + gmP vA OP vout . assuming vin1 and vin2 are differential. iX = rOP 1 + gmP g 1 jjrOP mP vout : (10. 10. we decompose the circuit into sections that more easily lend themselves to analysis by inspection. vin2 : (10.192) (10. vin2 = gmN rON jjrOP : The gain is indepedent of gmP and equal to that of the fully-differential circuit. 2007 at 13:42 514 (1) 514 Chap. vin2 and iX = . 10 Differential Ampliﬁers .198) Solving for vout yields vout rOP 1 + gmP g 1 jjrOP vout mP : (10.iY . the use of the active load has restored the gain. In other words.

the circuit is symmetric.gmN rON vin1 .201) v Thev R Thev (a) vX iX iX M2 r O1 r O2 P I SS v2 v Thev A v in1 M1 P I SS M2 B v in2 M1 v1 (b) (c) Figure 10. Under this condition. To determine the Thevenin resistance. 2006] June 30. 10. Having reduced the input sources and transistors to a Thevenin equivalent. 10.57 depicts the simpliﬁed circuit. where the subscript N refers to NMOS devices. we have iX . vin2 . (b) Thevenin voltage. 10. we now compute the gain of the overall ampliﬁer.cls v. The objective is to calculate vout in terms of vThev . and (c) Thevenin resistance of input pair. 10. 2007 at 13:42 515 (1) Sec. where the diodeconnected transistor M3 is replaced with 1=gm3 jjrO3 and the output impedance of M4 is drawn explicitly.56(c)]. resembling the topology of Fig. we can view vA as a divided version of vE : 1 gm3 jjrO3 vout + vThev : vA = 1 gm3 jjrO3 + RThev (10. Noting that M1 and M2 have equal gate-source voltages (v1 = v2 ) and writing a KVL around the “output” loop.6 Differential Pair with Active Load 515 [Fig.204) . we set the inputs to zero and apply a voltage between the output terminals [Fig.16(a).203) The reader is encouraged to obtain this result using half circuits as well.56 (a) Thevenin equivalent. Figure 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.56(b)]. M3 A v in1 M1 P I SS M2 VDD M4 B v out v in2 (10. gm1 v1 rO1 + iX + gm2 v2 rO2 = vX and hence (10.202) RThev = 2rON : (10.92) thus yields vThev = . Equation (10. Since the voltage at node E with respect to ground is equal to vout + vThev .

vin2 ON OP ON and hence .205) that 0 Bg B m4 @ 1 + 1 1 jjr + R gm3 O3 Thev gm3 jjrO3 + RThev 1 gm3 jjrO3 1 C v + v + vout = 0: C out Thev A rO4 (10. Given by gm4 vA .57 Simpliﬁed circuit for calculation of voltage gain.205) where the last term on the left hand side represents the current ﬂowing through RThev . the small-signal drain current of M4 must satisfy KCL at the output node: gm4vA + vout + 1 vout + vThev = 0.206) Recognizing that 1=gm3 rO3 .201) and (10. and 1=gm3 rO3 = rO4 = rOP . 10 VDD M4 R Thev v Thev E B v out r O4 Differential Ampliﬁers A Figure 10.cls v.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we reduce (10.204) and (10.207) therefore give vout r 1 + r 1 = gmN rONr vin1 .207) 2 v + v + vout = 0: out Thev R r Thev Equations (10. rO4 gm3 jjrO3 + RThev (10. 2007 at 13:42 516 (1) 516 r O3 1 g m3 Chap. 2006] June 30.206) to RThev and assuming gm3 = gm4 = gmp and OP (10. It follows from (10.

51(b). the path through the active load restores the gain even though the output is single-ended.56 is much less than that at the output. vin2 = gmN rON jjrOP : (10. This current ﬂows through M1 and hence through M3 . gm4 vA . we surmised that the voltage swing at node A in Fig. the gain of this circuit is the same as the differential gain of the topology in Fig. Interestingly. 10.58. 10. In other words.vout rO4 + gm4 vA g 1 jjrO3 : m3 .208) vout vin1 . (10. As depicted in Fig. In our earlier observations. generating Example 10. KCL at the output node indicates that the total current drawn by M2 must be equal to .vout =rO4 .209) The gain is independent of gmp . Prove this point.29 Solution vA = . 10.

210) . (10.

e. and two identical loads. the input differential swing of a bipolar differential pair must remain below roughly VT . with the two components beginning from the same dc (common-mode) level and changing by equal and opposite amounts. Compared with single-ended signals. vA .. 10. differential changes at the input. r mP OP revealing that vA is indeed much less that vout . p . which is 2 larger than the equilibrium overdrive of each transistor. The transistor currents in a differential pair remain constant as the input CM level changes. The tail current can be mostly steered to one side with a differential input of about 4VT .e. A differential pair consists of two identical transistors..cls v. 1 g m3 (10. 2006] June 30. For small. A differential signal consists of two single-ended signals carried over two wires. differential signals are more immune to common-mode noise. For small-signal operation. i. the tail node voltage of a differential pair remains constant and is thus considered a virtual ground node. i. each of which is simply a common-emitter stage.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. a tail current. The transistor currents change in opposite directions if a differential input is applied. 2g vout . the circuit responds to differential inputs. 2007 at 13:42 517 (1) Sec. 10. the circuit “rejects” input CM changes. MOS differential pairs can steer the tail current with a differential input equal to p 2ISS =n Cox W=L. Bipolar differential pairs exhibit a hyperbolic tangent input/output characteristic.58 Exercise Calculate the voltage gain from the differential input to node A.211) VDD M4 r O4 v out M1 P I SS M2 +v in r O3 A −v in Figure 10.7 Chapter Summary Single-ended signals are voltages measured with respect to ground.7 Chapter Summary 517 That is. The pair can then be decomposed into two half circuits.

2007 at 13:42 518 (1) 518 Chap.1. 10. the loads can be cascoded to maximize the voltage gain. In the circuit of Fig.59. To calculate the effect of ripple at the output of the circuit in Fig. a fraction of the input CM change appears as a differential component at the output. Plot the waveforms VCC I1 X RC Y RC I2 Figure 10.59 4. Problems 1. The differential output of a perfectly symmetric differential pair remains free from input CM changes. assuming VA 1. Also. we can assume VCC is a small-signal “input” and determine the (small-signal) gain from VCC to Vout . 10. The input transistors of a differential pair can be cascoded so as to achieve a higher voltage gain. assuming RC 1 = RC 2 . Repeat Problem 1 for the circuit of Fig.61.60 at X and Y and determine their peak-to-peak swings and common-mode level. It is possible to replace the loads of a differential pair with a current mirror so as to provide a single-ended output while maintaining the original gain. Assume VA 1 and 0. 5. Repeat Problem 4 for the circuit depicted in Fig. VCC RC Vout Q1 V in I EE Vb V in M1 RS RD Vout VDD V in VCC Q1 Vout I EE RS V in VDD M1 Vout (a) (b) (c) (d) Figure 10. 3. 10 Differential Ampliﬁers Unlike their bipolar counterparts. corrupting the desired signal.2(a). 10. Repeat Problem 1 for the stages shown in Fig. MOS differential pairs can provide more or less linear characteristics depending on the choice of the device dimensions. 2. Similarly. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . Compute this gain.I0 cos !t + I0 . plot the voltage at node P as a function of time. The circuit is called a differential pair with active load. 2006] June 30. 10. I1 = I0 cos !t + I0 and I2 = .cls v. In the presence of asymmetries and a ﬁnite tail current source impedance.60. The gain seen by the CM change normalized to the gain seen by the desired signal is called the common-mode rejection ration.

cls v. 10. VCC RC X I1 Y I2 IT RC RC X I1 IT VCC RC Y I2 RC RP X I1 Y I2 VCC RC RC X I1 Y I2 RP VCC RC (a) (b) (c) (d) Figure 10. . Assuming I1 = I0 cos !t + I0 and I2 = .V0 cos !t + V0 .I0 cos !t + 0:8I0 . Repeat Problem 4 for the topology shown in Fig.64 10.7 Chapter Summary VCC R1 RC X I1 P RC Y I2 519 Figure 10. 10. 10.62 6. Assuming V1 = V0 cos !t + V0 and V2 = . 2006] June 30. 7. but assume I2 = .61 VCC RC X I1 RC Y I2 Figure 10. Assume I1 is constant.63 8. 10. Can X and Y be considered true differential signals? 9.65. plot VX and VY as a function of time for the circuits illustrated in Fig.62.63. VCC I1 X RC Vb Y RC I2 Figure 10. Repeat Problem 4. Assume IT is constant.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10. 2007 at 13:42 519 (1) Sec. Repeat Problem 4 for the topology shown in Fig.I0 cos !t + I0 . plot VP as a function of time for the circuits shown in Fig.64.

compute Gm and plot the result as a function of Vin1 . 2006] June 30. (b) VCC rises by V .12. IC 1 =IC 2 = 5. RC = 500 . (10. how does IC 1 =IC 2 change if the temperature rises from 27 C to 100 C? 19.cls v. 10.13 if the ambient temperature goes from 27 C to 100 C. determine the input difference at which the transconductance of Q2 drops by a factor of 2. 10. 2007 at 13:42 520 (1) 520 RC V1 V2 (a) Chap. (10.60).9(a) and assume IEE = 1 mA. 10. or (c) RC is halved? 18. Vout2 : in1 in2 (10.9(b). In Fig. determine the change in VX .58) and (10. What is the corresponding input differential voltage? With this voltage applied.7. Neglecting the Early effect.10 if (a) IEE is halved. 12. 21. Vin2 . What is the maximum allowable value of RC if Q1 must remain in the active region? 15. Explain why we say the circuit “rejects” supply noise.213) Determine the gain and compute its value if Vin1 . Suppose in Fig.212) From Eqs. VY change? 13. Vin2 does Gm drop by a factor of two with respect to its maximum value? 22. and VX . we can compute the small-signal voltage gain of the bipolar differential pair: out . Vin2 rises because IC 2 decreases.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. determine the maximum allowable input. VY . 10. 10. 23. 20. Repeat Problem 12. 10.I Gm = @@IC 1 .7. Consider the circuit of Fig. and VX . the small-signal transconductance of Q2 falls as Vin1 . In the circuit of Fig.12: . From Eq. How do VX . . What is the maximum allowable value of IEE if Q2 must remain in the active region? 16. 10. Suppose the input differential signal applied to a bipolar differential pair must not change the transconductance (and hence the bias current) of each transistor by more than 10.58).78). With the aid of Eq. 17. What is the maximum value of Gm ? At what value of Vin1 . Explain what happens to the characteristics shown in Fig. VY .65 11. Determine the region of operation of Q1 .9(a).12. but assuming that RC 1 = RC 2 + R. 10 RC RC P V1 V2 (b) Differential Ampliﬁers RC RC P V1 V2 (c) RC P I1 R1 Figure 10. IEE experiences a change of I .58). (10. In the circuit of Fig. 14. 10. What happens to the characteristics depicted in Fig. It is possible to deﬁne a differential transconductance for the bipolar differential pair of Fig. 10. V Av = @@ VV 1 . VCC rises by V . Neglect the Early effect. VY . Vin2 contains a dc component of 30 mV. In the differential pair of Fig. 10. (10. VC 2 : V in1 in2 (10. Suppose IEE = 1 mA and RC = 800 in Fig. Using Eq.

p = 4 V. . 10. 10.) VCC RC Vout V in1 Q1 P I EE Q2 Vin2 RC R EE Figure 10. 26. Repeat the small-signal analysis of Fig. Calculate the voltage gain of the circuit. In Problem 25. plot the output waveforms (as a function of time). estimate the slope of the output square waves for V0 = 80 mV or 160 mV if ! = 2 100 MHz. 2007 at 13:42 521 (1) Sec.215) Vin1 = V0 sin !t + VCM Vin2 = . In Example 10. If VA.7 Chapter Summary 521 24. 10.p = 4 V.67 30. Explain why the output square wave becomes “sharper” as the input amplitude increases. IEE = 1 mA. prove that P is still a virtual ground. 10. where IEE = 2 mA.V0 sin !t + VCM . Assume (10. (First. IEE = 1 mA and VA = 5 V. VA. (b) If V0 = 50 mV. Consider the circuit shown in Fig. 10. Note that the gain is independent of the tail current.9.66 28. determine the time t1 at which one transistor carries 95 of the tail current.66.67. (a) If V0 = 2 mV. calculate the required tail current. Using the circuit parameters given in Problem 24. Plot the output waveforms.cls v.86 holds in the presence of the Early effect. What value of R1 = R2 allows a voltage gain of 50? 31.68. 10. 2006] June 30. and VCC = 2:5 V. (10. Using a small-signal model and including the output resistance of the transistors. The study in Example 10.214) (10.15 for the circuit shown in Fig. prove that Eq.n = 5 V and VA. 29.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The circuit of Fig. 27. In Fig.9 suggests that a differential pair can convert a sinusoid to a square wave. 25. plot the output waveforms if V0 = 80 mV or 160 mV. where VCM = 1 V denotes the input common-mode level.68 must provide a gain of 50 with R1 = R2 = 5 k . RC = 500 .n = 5 V VA. VCC Vout V in1 Q1 P I EE Q2 Vin2 Figure 10.

Consider the differential pair illustrated in Fig.Gm Rout in some cases. 2007 at 13:42 522 (1) 522 X Q3 R1 Vout V in1 Q1 P I EE Q2 R2 Chap. 10. 10 VCC Q4 Differential Ampliﬁers Vin2 Figure 10. 2006] June 30. (b) Under what condition does the gain become independent of the tail currents? This is an example of a very linear circuit because the gain does not vary with the input or output signal levels. 34.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.68 32.cls v. (a) Determine the voltage gain.71.70. Assuming perfect symmetry and VA 1. Assuming perfect symmetry and VA = 1. . 10. compute the differential voltage gain of each VCC RC Vout RC R2 Q4 V in1 Q2 Vin2 R1 Q1 P I EE R2 Q2 Vin2 (b) VCC R1 Q3 V in1 Q1 P I EE (c) VCC R1 R2 Q4 Vout V in1 Q1 P I EE (d) R2 Vout Q2 Q4 Vin2 Q3 Q2 Vin2 Figure 10. You may need to compute the gain as Av = . Assuming perfect symmetry and VA stage depicted in Fig.69 33. 10. VCC R1 Q3 Vout V in1 Q1 P I EE (a) 1.69. compute the differential voltage gain of each stage depicted in Fig.

what is the required value of ISS ? 38.n = 0:5 V. An adventurous student constructs the circuit shown in Fig. 10. Vin2 .72). prove that P is still a virtual ground for small. What is the minimum allowable supply voltage if the transistors must remain in saturation? Assume VTH. 36. ISS = 1 mA. Formulate the trade-off between VDD and W=L for a given output common-mode level.16 for a supply voltage of 2 V. VCM = 1 V.24. 41.24. 39. (c) the gate oxide thickness is doubled.70 VCC Q3 RC Vout V in1 Q1 RE Q2 Vin2 Q4 RC I EE I EE Figure 10. 10. 10. the “current density” can be deﬁned as the drain current divided by the device width for a given channel length. In Fig. The MOS differential pair of Fig. 2007 at 13:42 523 (1) Sec. 10. Without using the small-signal model. 10.71 35.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Explain how the equilibrium overdrive voltage of a MOS differential pair varies as a function of the current density. Explain which aspects of our differential signals and ampliﬁers this circuit violates. Consider the MOS differential pair of Fig. (b) ISS is doubled.24 must be designed for an equilibrium overdrive of 2 200 mV.25(a). 10. differential inputs. and RD = 1 k . 42. 37. A MOS differential pair contains a parasitic resistance tied between its tail node and ground (Fig. determine a condition among the circuit parameters that guarantees operation of M1 in saturation. In the MOS differential pair of Fig. 2006] June 30. For a MOSFET. What happens to the tail node voltage if (a) the width of M1 and M2 is doubled. . Repeat Example 10. Assuming M2 is off.73 and calls it a “differential ampliﬁer” because ID Vin1 . If n Cox = 100 A=V and W=L = 20=0:18. 10.7 Chapter Summary VCC RC Vout RC RC Vout Q2 RE P RE R SS (a) 523 VCC RC V in1 Q1 Vin2 V in1 Q1 R1 RE P R2 Q2 RE R SS Vin2 (b) Figure 10. Vin1 = 1:5 V and Vin2 = 0:3 V. 40.cls v.

I Gm = @@V D1 . explain what happens to the characteristics of Fig. Explain what happens to the characteristics shown in Fig.134) for the following cases: (a) ID1 = 0.cls v. Figure 10.31 if (a) the gate oxide thickness of the transistor is doubled. (10. 2007 at 13:42 524 (1) 524 Chap.216) Plot the result as a function of Vin1 . deﬁned as I . Prove that the right hand side of Eq.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. From Eq. 47. Vin2 and determine its maximum value. 46. (a) What similarities exist between this circuit and the standard MOS differential pair? (b) Calculate the equilibrium overdrive voltage of T1 and T2 . Suppose a new type of MOS transistor has been invented that exhibits the following I-V characteristic: ID = VGS . Assuming that the mobility of carriers falls at high temperatures. Vin2 does one transistor turn off? 49. Verify p that is result is equal to 2 times the equilibrium overdrive voltage. Examine Eq.73 43. 50. (10. Using the result obtained in Problem 46. compute the small-signal transconductance of a MOS differential pair.217) where is a proportionality factor.74 shows a differential pair employing such transistors. (c) ISS and W=L are halved. From Eq. VD2 : in1 in2 (10. (b) the threshold voltage is halved. (10. Vin2 such that ID1 . (10. Explain the signiﬁcance of these cases.72 VDD RD Vout V in1 M1 Vin2 Figure 10.142). (c) At what value of Vin1 . 10. VTH 3 . 48.31 as the temperature rises. (b) ID1 = ISS =2. determine the value of Vin1 . 45. Vin2 at which the transconductance drops by a factor of 2. 10 VDD RD X V in1 I SS M1 M2 P R SS RD Y Vin2 Differential Ampliﬁers Figure 10. ID2 = ISS .142). 10. 44. 2006] June 30. calculate the value of Vin1 . (10. .139) is always negative if the solution with the negative sign is considered. and (c) ID1 = ISS .

(c) Add the results obtained in (a) and (b) with proper polarities.75. Assume perfect symmetry and 0. calculate vY in terms of vin . . vY =vin . VDD RD X Vout M1 V in P I SS M2 Vb RD Y Figure 10.76 53. You may need to compute the gain as Av = . calculate vX in terms of vin . If the voltage gain is deﬁned as vX . Assume perfect symmetry and 0. 2006] June 30. VDD M3 Vout V in1 M1 M2 I SS Vin2 M4 Vb M5 V in1 M3 Vout M1 M2 I SS I SS (a) (b) (c) VDD M4 M6 Vin2 V in1 Vb M3 R1 Vout M1 M2 R2 VDD M4 Vin2 Figure 10. 10. 10.cls v. Assume perfect symmetry but = 0 for simplicity. hoping to obtain differential outputs.74 51.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.Gm Rout in some cases. 2007 at 13:42 525 (1) Sec.76. how does it compare with the gain of differentially-driven pairs? 52.7 Chapter Summary VDD RD Vout V in1 T1 T2 I SS Vin2 RD 525 Figure 10. Calculate the differential voltage gain of the circuits depicted in Fig. (b) Viewing M1 as a source follower and M2 as a common-gate stage.77. A student who has a single-ended voltage source constructs the circuit shown in Fig. 10.75 (a) Viewing M1 as a common-source stage degenerated by the impedance seen at the source of M2 . Calculate the differential voltage gain of the circuits depicted in Fig. 10.

77 54. Due to a manufacturing error. Repeat Problem 55 for the circuit shown in Fig. VCC Vout Q3 Vb V in1 RP Q1 RP Q2 Q4 Vb Vin2 I EE Figure 10. 10. 2007 at 13:42 526 (1) 526 Chap.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.79 . a parasitic resistance.78 56.79.cls v. The cascode differential pair of Fig. Calculate the voltage gain. If Q1 -Q4 are identical and = 100. 10. has appeared in the circuit of Fig. what is the minimum required Early voltage? 55. 10. 2006] June 30. RP . VCC Vout Q3 Vb V in1 Q1 RP Q2 Vin2 Q4 I EE Figure 10.37(a) must achieve a voltage gain of 4000.78. 10 Differential Ampliﬁers VDD M3 Vout V in1 M1 R1 R2 R SS M2 Vin2 V in1 M4 Vb M3 M4 Vout M1 R SS M2 VDD RS M3 M4 Vout V in1 M1 R SS M2 VDD RS Vb Vin2 Vin2 (a) (b) (c) Figure 10.

81 suffers from a low gain. determine W=L1 = = W=L8 .81 59. 10. determine the required tail current. 2007 at 13:42 527 (1) Sec.38 is to operate as an op amp having an open-loop gain of 800.7 Chapter Summary 527 57. 10. The MOS telescopic cascode of Fig.Gm Rout .82.83. If W=L = 20=0:18 for M1 -M4 and n Cox = 100 A=V2 . n = 0:1 V.p . 10.1 .) VCC Av = Vout Q3 Vb V in1 Q1 RS Q2 Vin2 Q4 Figure 10.n = 2VA. Calculate the voltage gain of this topology. the student makes the modiﬁcation shown in Fig. A student has mistakenly used pnp cascode transistors in a differential pair as illustrated in Fig. where the PMOS cascode transistors are replaced with NMOS devices.41(a) is designed for a voltage gain of 200 with a 2 2 tail current of 1 mA. Calculate the voltage gain of the degenerated pair depicted in Fig. 2006] June 30. Assume = 0:1 V.40(a) must provide a voltage gain of 300. The telescopic cascode of Fig. If Q1 -Q4 are identical and so are Q5 -Q8 . p = 0:2 V 64. 10.) VCC Vout Q3 Vb V in1 Q1 Q2 Vin2 Q4 I EE Figure 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 10.80 58. 10. 61. determine the minimum allowable Early voltage. compute . 63.1 .cls v. 10. (Hint: . Assuming 0. (Hint: Av = . A student adventurously modiﬁes a CMOS telescopic cascode as shown in Fig.80. 10. Determine the voltage gain of the circuit depicted in Fig.84. Assume n = 2 p = 100 and VA. Is this topology considered a telescopic cascode? 62.Gm Rout . Realizing that the circuit of Fig. 60. and . The MOS cascode of Fig. 10. Calculate the voltage gain of the circuit.81.1 . 10. If n Cox = 100 A=V . p Cox = 50 A=V .

VTH eq: (10. 10.cls v.218) 67.175) still holds. 10.85 must exhibit a common-mode gain of less than 0.86. (10. Prove that Eq.01. each having a degeneration resistor equal to 2REE .83 the voltage gain of the circuit. Consider the circuit of Fig. 10 VCC Differential Ampliﬁers Q3 Vb Vout V in1 Q1 Q4 Q2 Vin2 I EE Figure 10. 66. prove that RC IC 0:02VA + VT : (10. Now draw a vertical line of symmetry through the circuit and decompose it to two common-mode half circuits. 2006] June 30. (Hint: the impedance seen looking into the source of M5 or M6 is not equal to 1=gmjjrO .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 528 (1) 528 Chap. Prove RD ISS ACM = 2 . Compute the common-mode gain of the MOS differential pair shown in Fig. 10.82 VCC V b3 Q7 V b2 Q5 Q3 V b1 V in1 Q1 Q2 Vin2 Q6 Vout Q4 Q8 I EE Figure 10. Assume = 0 for M1 and M2 but 6= 0 for M3 .219) . Assuming VA = 1 for Q1 and Q2 but VA 1 for Q3 .) 65.43(a) and replace REE with two parallel resistors equal to 2REE places on the two sides of the current source. The bipolar differential pair depicted in Fig. + VGS .

10.Gm Rout .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and use the relationship Av = . For simplicity.86 68. 69. Repeat Problem 68 for the circuits shown in Fig. 10. Neglect channel-length modulation.7 Chapter Summary VDD M7 V b3 V b2 M5 M3 V b1 V in1 M1 M2 I SS M6 Vout M4 Vin2 M8 529 Figure 10. 2007 at 13:42 529 (1) Sec.88. neglect channel-length modulation in M1 and M2 but not in other transistors. Compute the common-mode rejection ratio of the stages illustrated in Fig. 71. Calculate the common-mode gain of the circuit depicted in Fig. where VGS .85 VDD RD X V in1 Vb M1 M2 M3 RD Y Vin2 Figure 10. .87. gm rO 1. 10. VTH eq: denotes the equilibrium overdrive of M1 and M2 . 2006] June 30. Determine the small-signal gain vout =i1 in the circuit of Fig. 10.84 VCC RC v out1 Q1 v CM Vb Q3 I EE Q2 RC v out2 Figure 10. 70.cls v.90 if W=L3 = N W=L4 .89 and compare the results. 10. Assume 0.

10 VDD V b1 M3 V in1 V b2 Vout M1 M2 M5 Vin2 M4 Differential Ampliﬁers Figure 10.cls v. (b) W=L3 = 2W=L4 73. calculate the voltage at node N . . In the circuit shown in Fig. Consider the circuit of Fig. 2006] June 30.91. 10. (a) Neglecting channel-length modulation.89 72. Neglecting channel-length modulation. I1 changes from I0 to I0 +I and I2 from I0 to I0 .88 VDD RD v out1 V in1 M1 P M2 R D + ∆R D v out2 Vin2 RD v out1 V in1 M1 P M2 VDD R D + ∆R D v out2 Vin2 V b1 M3 V b2 V b3 M3 M4 (b) (a) Figure 10. 10.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. determine the voltage at node Y . I . 2007 at 13:42 530 (1) 530 Chap. Assume M1 and M2 are identical and so are M3 and M4 . where the inputs are tied to a common-mode level.92.87 VDD V b1 M3 V in1 V b2 V b3 Vout M1 M2 M5 M6 Vin2 V in1 V b2 M4 V b3 V b1 M3 Vout M1 M2 M7 (b) VDD M5 M6 M4 Vin2 (a) Figure 10. calculate Vout before and after the change if (a) W=L3 = W=L4 . (b) Invoking symmetry.

n = 5 V. what is the required Early voltage for the pnp transistors? 76. 2007 at 13:42 531 (1) Sec.90 VDD M3 M4 Vout I1 I2 RL Figure 10. If VA. Repeat the analysis in Fig. compute the small-signal gains vout =i1 and vout =i2 in Fig. Assume gm rO 1. 10. Determine the output impedance of the circuit shown in Fig. 10. Neglecting channel-length modulation. 2006] June 30. 10.cls v.92 (c) What happens to the results obtained in (a) and (b) if VDD changes by a small amount V ? 74.7 Chapter Summary VDD M3 M4 Vout I1 RL 531 Figure 10.94 for a voltage gain of 100. We wish to design the stage shown in Fig.56 but by constructing a Norton equivalent for the input differential pair. .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VDD M3 M4 Vout I1 I2 RL Figure 10.54. 10.91 M3 N M1 v CM I SS P Y M2 VDD M4 Figure 10. 77. 10.93.93 75.

Assuming VCC = 2:5 V and VA = 1. 2007 at 13:42 532 (1) 532 VCC Q3 Q4 Chap. Assume VCC Vb Q3 V in1 Q1 Vout Q2 Vin2 Q4 I EE Figure 10. 10.2 V without driving the transistors into saturation. Design the bipolar differential pair of Fig. 10.cls v. Design Problems 79. 80.6(a) must operate with an input common-mode level of 1. 10.95 must provide a gain of 5 and a power budget of 4 VCC RC Vout V in1 Q1 RE Q2 Vin2 RC I EE I EE Figure 10. (Hint: a 10 change in IC leads to a 10 change in gm . Design the circuit of Fig.96 VA.97 for a gain of 100 and a power budget of 1 mW. 10. The bipolar differential pair of Fig.96 for a gain of 50 and a power budget of 1 mW.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.94 78. 10. Assume . the gain of the circuit must change by less than 2 if the collector current of either transistor changes by 10. 81. Assume VCC = 2:5 V.n = 6 V and VCC = 2:5 V. compute the voltage gain of the stage. design the circuit.Gm Rout . Design the circuit of Fig.6(a) for a voltage gain of 10 and a power budget of 2 mW. 2006] June 30. 83. The differential pair depicted in Fig. Assume VCC = 2:5 V and VA = 1. Design the circuit for maximum voltage gain and a power budget of 3 mW.) 82. 10 Differential Ampliﬁers Vout V in1 Q1 Q2 Vin2 I EE Figure 10. Using the result obtained in Problem 77 and the relationship Av = .95 mW. Moreover.

Also. The differential pair depicted in Fig. p = 0:2 V. 10. Assume Q1 -Q4 are identical and so are Q5 -Q8 . Also.98 must provide a gain of 40.38(a) for a voltage gain of 2000.37(a) for a voltage gain of 4000.29 for an equilibrium overdrive voltage of 100 mV and a power budget of 2 mW.1 . Assume Q1 -Q4 are identical and determine the required Early voltage. Assume RD = 500 . n Cox = 100 A=V . 10. 2007 at 13:42 533 (1) Sec. and VCC = 2:5 V.1 . n = 100. VCC = 2:5 V.8 V. 89. VA. Assume = 0. What is the voltage gain of the resulting design? 86. p Cox = 50 A=V . 10. n Cox = 100 A=V2 . 90.29 for a voltage gain of 5 and a power dissipation of 1 mW if the equilibrium overdrive must be at least 150 mV. and VDD = 1:8 V. 10. and VDD = 1:8 V. Assume = 0. 2006] June 30. VTH. Assume an (equilibrium) overdrive of 100 mV for the NMOS devices and 150 mV 2 2 for the PMOS devices. = 100.n = 0:5 V. VA. 10. Design the telescopic cascode of Fig. and . p = 50. 10. 10. Design the circuit of Fig. n Cox = 100 A=V2 .97 84. and the power budget is 1 mW. Design the MOS differential pair of Fig. R1 = R2 . p Cox = 2 100 A=V . Assume n = 0:1 V.n = 5 V. 10. = 0. n Cox = 100 A=V .n = 10 V.p = 5 V.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Design the MOS differential pair of Fig. n Cox = 100 A=V .41(a) for a voltage gain of 600 and a power budget of 4 mW.max = 0:3 V and a power budget of 3 mW. VA.29 for Vin. Design the telescopic cascode of Fig. 88. design 2 the circuit. VCC = 2:5 V. If VDD = 1. and VDD = 1:8 V.98 (equilibrium) overdrive for all of the transistors and a power dissipation of 2 mW. 85. and VDD = 1:8 V.7 Chapter Summary VCC Q3 R1 Vout V in1 Q1 P I EE Q2 Vin2 R2 Q4 533 Figure 10. Also. Assuming the same VDD V b1 M3 V in1 V b2 Vout M1 M2 M5 Vin2 M4 Figure 10. Select the value of RD to place the transistor at the edge of 2 triode region for an input common-mode level of 1 V. and the power budget is 2 mW. Design the MOS differential pair of Fig. 87.cls v.

2 V. and R=R = 2. Also.2 V. The differential pair of Fig. use an independent voltage source for one side and a voltage-dependent voltage source for the other. pnp = 50. . and neglecting channel-length modulation in M1 and M2 . 2006] June 30. n Cox = 2p Cox = 100 A=V . VA. n Cox = 100 A=V2 . 93.pnp = 3:5 V. VA. Assume a power VDD RD v out1 V in1 M1 P M2 R D + ∆R D v out2 Vin2 n = 0:1 V.npn = 5 V. a nominal differential voltage gain of 5.100 (a) Adjust the value of Vb so as to set the output CM level to 1. SPICE Problems In the following problems. VTH.16 A.101 employs two current mirrors to establish the bias for the input and load devices. (Hint: to provide differential inputs.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.0:4 V. The differential ampliﬁer depicted in Fig. 92.54 for a voltage gain of 20 and a power budget of 1 mW with VDD = 1:8 V. Assume W=L = 10 m=0:18 m for M1 -M6 . assume IS. VDD = 1:8 V.2 = 10=0:18. Assume M1 operates at the edge of 2saturation if the input common-mode level is 1 V.16 A.48 for a voltage gain of 200 and a power budget of 3 mW with a 2. 10. Consider the differential ampliﬁer shown in Fig.npn = 5 10. use the MOS device models given in the Appendix I. Design the differential pair of Fig. V b1 M3 Figure 10. Assume W=L1.5 V Vb Vout V in1 Q1 Q2 Vin2 Q4 1 mA I EE Figure 10.cls v. The input CM level is equal to 1. 10. 10.1 .p = .n = 0:5 V.5 V.99 must achieve a CMRR of 60 dB (= 100). npn = 100. determine the required value of p . 10 Differential Ampliﬁers 91. VTH. Assume VA. 10. (b) Determine the small-signal differential gain of the circuit. Assume M1 -M4 are identical and so are M5 -M8 .p . 10. For bipolar transistors. compute the minimum required for M3 .1 .) (c) What happens to the output CM level and the gain if Vb varies by 10 mV? 95. 2007 at 13:42 534 (1) 534 Chap. IS. VCC = 2.100. n = 0:5p = 0:1 V.n = 2VA. Design the circuit of Fig.5-V supply. where the input CM level is equal to 1.pnp = 8 10.99 budget of 2 mW. 94.

102. (Assume L7 = 0:18 m.) (b) Determine the small-signal differential gain of the circuit.cls v. 10. 2006] June 30. I1 so that the output CM level places M3 and M4 at the edge of .8 V M7 1 kΩ 535 M3 V in1 M4 Vout M1 M2 M5 Vin2 M6 Figure 10. 10.5 V.5 V Q3 R1 Vout V in1 Q1 Q2 Vin2 R2 Q4 1 mA I EE Figure 10. 2007 at 13:42 535 (1) Sec. Consider the circuit illustrated in Fig. VDD = 1. In the differential ampliﬁer of Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.103 (a) Select the value of saturation. (c) Plot the differential input/output characteristic.103. 96. 10.102 (a) Select the input CM level to place Q1 and Q2 at the edge of saturation. 97. Assume a small dc drop across R1 and R2 . (b) Select the value of R1 (= R2 ) such that these resistors reduce the differential gain by no more than 20. VCC = 2.7 Chapter Summary VDD = 1. W=L = 10 m=0:18 m for all of the transistors. Assume an input CM level of 1 V and Vb = 1:5 V.101 (a) Select W=L7 so as to set the output CM level to 1.8 V M7 M9 I1 Vb V in1 M1 1 mA M8 Vout M4 M2 I SS Vin2 M3 Figure 10.

Razavi.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (c) Determine the change in the output dc level if W4 changes by 5. 10 Differential Ampliﬁers (b) Determine the small-signal differential gain.104 (a) Determine the output dc level and explain why it is equal to VX / (b) Determine the small-signal gains vout =vin1 . 2001. B. . 98. Assume an input CM VDD = 1.104. In the circuit of Fig. M3 X V in1 M1 0. References 1.5 mA M1 -M4.cls v. 2007 at 13:42 536 (1) 536 Chap. W=L = 10 m=0:18 m for level of 1. vin2 .8 V M4 Vout M2 I SS Vin2 Figure 10. vin2 and vX =vin1 . Design of Analog CMOS Integrated Circuits McGraw-Hill. 2006] June 30.2 V. 10.

11. 2006] June 30. 537 . From radar and television systems in the 1940s to gigahertz microprocessors today.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Before investigating the cause of this roll-off. we study the effects that limit the speed of transistors and circuits. The outline is shown below. As exempliﬁed by Fig. 11. 11. we must ask: why is frequency response important? The following examples illustrate the issue.1(b) to represent the circuit’s behavior at all frequencies of interest.1. the idea is to apply a sinusoid at the input of the circuit and observe the output while the input frequency is varied.cls v.1 General Considerations What do we mean by “frequency response?” Illustrated in Fig. the circuit may exhibit a high gain at low frequencies but a “roll-off” as the frequency increases.1(a). In this chapter. a critical task in the study of stability and frequency compensation (12).1(a). We plot the magnitude of the gain as in Fig. Example 11. identifying topologies that better lend themselves to high-frequency operation. the demand for pushing circuits to higher frequencies has required a solid understanding of their speed limitations.1 Fundamental Concepts 11. We may loosely call f1 the useful bandwidth of the circuit.1 Explain why people’s voice over the phone sounds different from their voice in face-to-face conversation. We also develop skills for deriving transfer functions of circuits. 2007 at 13:42 537 (1) 11 Frequency Response The need for operating circuits at increasingly higher speeds has always challenged designers. Fundamental Concepts Bode’s Rules Association of Poles with Nodes Miller’s Theorem High−Frequency Models of Transistors Bipolar Model MOS Model Transit Frequency Frequency Response of Circuits CE/CS Stages CB/CG Stages Followers Cascode Stage Differential Pair 11. We assume bipolar transistors remain in the active mode and MOSFETs in the saturation region.

5 kHz f Figure 11.2(b). your voice propagates through the air and reaches the audio recorder. the phone system suffers from a limited bandwidth. 11. Exercise Explain what happens to your voice when you have a cold? . men’s or women’s? Example 11.e.2 When you record your voice and listen to it. your skull passes some frequencies more easily than others).5 kHz. Solution Human voice contains frequency components from 20 Hz to 20 kHz [Fig. it sounds somewhat different from the way you hear it directly when you speak.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. exhibiting the frequency response shown in Fig. 11 Frequency Response Av Roll−Off f1 (a) (b) f Figure 11. the way you hear your own voice is different from the way other people hear your voice. on the other hand. circuits 20 Hz (a) 20 kHz f 400 Hz (b) 3. 2007 at 13:42 538 (1) 538 Chap.1 (a) Conceptual test of frequency response. Thus. (b) gain roll-off with frequency.2 processing the voice must accommodate this frequency range. Unfortunately. Since the phone suppresses frequencies above 3.2(a)]. Exercise Whose voice does the phone system alter more. On the other hand. 2006] June 30. each person’s voice is altered. 11. Since the frequency response of the path through your skull is different from that through the air (i.. Explain why? Solution During recording. your voice propagates not only through the air but also from your mouth through your skull to your ear. In high-quality audio systems. the circuits are designed to cover the entire frequency range. when you speak and listen to your own voice simultaneously.

Solution With insufﬁcient bandwidth. 2007 at 13:42 539 (1) Sec. At high frequencies. thus. appears at the output.3 Exercise What happens if the display is scanned from top to bottom? What causes the gain roll-off in Fig.cls v.1? As a simple example.0 Figure 11. nearly zero. and (b) its frequency response. Vout = Vin . CL “steals” some of the signal current and shunts it to ground. remains high.4(a). C1 is nearly open and the current through R1 Vout R1 V in C1 Vout f V in 1. At low frequencies. CL .4 (a) Simple low-pass ﬁlter.. from the small-signal equivalent . 11. As a more interesting example. consider the common-source stage illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Figures 11. 1=CL s. In fact. 11. (The display is scanned from left to right. The circuit therefore exhibits the behavior shown in Fig.1 Fundamental Concepts 539 Example 11. the “sharp” edges on a display become “soft. complete white to complete black from one pixel to the next. the signal current produced by M1 prefers to ﬂow through RD because the impedance of CL . At low frequencies. on the other hand.4(b). let us consider the low-pass ﬁlter depicted in Fig. Explain what happens if the bandwidth of a video system is insufﬁcient. As the frequency increases. leading to a lower voltage swing at the output. This is because the circuit driving the display is not fast enough to abruptly change the contrast from.5(a).g.3(a) and (b) illustrate this effect for a high-bandwidth and low-bandwidth driver. respectively.3 Video signals typically occupy a bandwidth of about 5 MHz. 2006] June 30. For example. the graphics card delivering the video signal to the display of a computer must provide at least 5 MHz of bandwidth.) (a) (b) Figure 11. where a load capacitance. 11. e. 11.” yielding a fuzzy picture. 11. the impedance of C1 falls and the voltage divider consisting of R1 and C1 attenuates Vin to a greater extent.

an ampliﬁer may sense a voice or video signal that bears no resemblance to sinusoids. responses such as that in Fig.5(b). 2007 at 13:42 540 (1) 540 VDD RD Vout V in M1 CL V in Chap. After all. the parallel impedance falls and so does the amplitude of 1 + !s 1 + !s z1 .1) The reader may wonder why we use sinusoidal inputs in our study of frequency response.5 (a) CS stage with load capacitance.5(b) prove useful so long as the circuit remains linear and hence superposition can be applied.1. Thus.gmVin RD jj C1 s : L (11. 11. 2006] June 30.2 The voltage gain therefore drops at high frequencies. such signals can be viewed as a summation of many sinusoids with different frequencies (and phases). (b) small-signal model of the circuit.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Fortunately. 11. 11. circuit of Fig. That is. as the frequency increases.2 Relationship Between Transfer Function and Frequency Response We know from basic circuit theory that the transfer function of a circuit can be written as Vout .cls v.1 we note that RD and CL are in parallel and hence: Vout = . 11 Frequency Response Vout g V in m RD CL (a) (b) Figure 11.

z2 H s = A0 .

s s . 1+ ! 1+ ! p1 p2 .

.

(11. we are primarily concerned with the former. If the input to the circuit is a sinusoid of the form xt = A cos2ft = A cos !t.” jH j! j and 6 H j! respectively reveal the frequency response of the circuit. we may write ! = 5 1010 rad/s = 27:96 GHz: Example 11. For example. respectively. 1 Channel-length modulation is neglected here. In this chapter. then the output can be yt = AjH j!j cos !t + 6 H j! . 11. 2 We use upper case letters for frequency-domain quantities (Laplace transforms) even though they denote small- signal values.5(a). Called the “magnitude” and the “phase. Note that f (in Hz) and ! (in radians per second) are related by a factor of 2 . The frequencies !zj and !pj represent the zeros and poles of the transfer function.2) expressed as where A0 denotes the low frequency gain because H s ! A0 as s ! 0. (11. .4 Determine the transfer function and frequency response of the CS stage shown in Fig.3) where H j! is obtained by making the substitution s = j! .

Assume VA = 1.1). we say the . 11.3-dB bandwidth. rolling off as RD CL ! 2 becomes comparable with unity. the .4) (11.5) For a sinusoidal input.7) 2 3 dB. Since 20 log 11. the low-frequency gain by gm RC = IC =VT RC . and the power consumption by IC VCC .6) 2 2 Vin RD CL !2 + 1 2 2 As expected. we have H s = Vout s = . At ! = 1=RD CL .5(a).7. 2007 at 13:42 541 (1) Sec. . 11.1 Fundamental Concepts 541 Solution From Eq. we replace s = j! and compute the magnitude of the transfer function:3 Vout = p gm RD : (11. Derive a relationship between the gain. the gain begins at gm RD at low frequencies. p Vout = gm RD : p Vin 2 (11. (11.3-dB bandwidth of the circuit is equal to 1=RD CL (Fig.cls v.6). 11. the bandwidth is given by 1=RC CL . Vout V in −3−dB Bandwidth −3−dB Rolloff 1 R D CL ω Figure 11. For the highest performance.gm RD jj C1 s Vin L . 2006] June 30.5 Consider the common-emitter stage shown in Fig. and the power consumption of the circuit. Example 11.gmRD : = R C s+1 D L (11. we wish to maximize both the gain and the bandwidth (and hence the 3 The magnitude of the complex number Solution p a + jb is equal to a2 + b2 . In a manner similar to the CS topology of Fig.6 Exercise Derive the above results if 6= 0.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the load capacitance receives the greatest attention.7 product of the two) and minimize the power dissipation.4 (b) VCC but at the cost of limiting the voltage swings. by immersing the circuit in liquid nitrogen (T around! = 77 K). the overall performance can be improved by lowering (a) the temperature. Equation (11. Exercise Derive the above results if VA 1.9) becomes more complex for CS stages (Problem 15). Example 11.4(a). 2006] June 30. 2007 at 13:42 542 (1) 542 Chap. We therefore deﬁne a “ﬁgure of merit” as IC 1 Gain Bandwidth = VT RC RC CL Power Consumption IC VCC 1 = V 1V C : T CC L (11.12) 4 For example. but requiring that the user carry a tank . we view the circuit as a voltage divider and write H s = Vout s = 1 C1 s Vin C1 s + R1 1 (11.cls v. 11. 11 Frequency Response VCC RC Vout V in Q1 CL Figure 11.9) Thus.10) = R C 1s + 1 : 1 1 1 (11. Solution To obtain the transfer function.6 Explain the relationship between the frequency response and step response of the simple lowpass ﬁlter shown in Fig.8) (11. In practice.11) The frequency response is determined by replacing s with j! and computing the magnitude: jH s = j!j = p R C ! +1 2 2 2 1 1 : (11. or (c) the load capacitance.

cls v.13) The relationship between (11. an effect neglected in Bode’s approximation.9 illustrates the result. the slope of jH j! j increases by 20 dB/dec.5) indicates a pole frequency of j!p1 j = R 1C : D L (11.14) The magnitude thus begins at gm RD at low frequencies and remains ﬂat up to ! = j!p1 j. This observation explains the effect seen in Fig. as R1 C1 increases. (A slope of 20 dB/dec simply means a tenfold change in H for a tenfold increase in frequency. .8 plots this behavior.3(b): since the signal cannot rapidly jump from low (white) to high (black). 2006] June 30. The circuit’s response to a step of the form V0 ut is given by t Vout t = V0 1 . Exercise At what frequency does jH j fall by a factor of two? 11.20 dB/dec. Example 11.C ut: 1 1 (11.12) and (11. In contrast 5 Complex poles may result in sharp peaks in the frequency response.1 Fundamental Concepts 543 The . exp R. it spends some time at intermediate levels (shades of gray). At this point. For this reason.3 Bode’s Rules The task of obtaining jH j! j from H s and plotting the result is somewhat tedious. we often utilize Bode’s rules (approximations) to construct jH j! j rapidly. H 1.0 R 1C 1 R 1C 1 Vout f (a) (b) t Figure 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the slope of jH j! j decreases by 20 dB/dec.5(a).8 11. the slope changes from zero to . Figure 11. revealing that a narrow bandwidth results in a sluggish time response. 11.13) is that. Figure 11. 2007 at 13:42 543 (1) Sec. 11.5 Construct the Bode plot of jH j! j for the CS stage depicted in Fig.) As ! passes each zero frequency. Bode’s rules for jH j! j are as follows: As ! passes each pole frequency.1. the bandwidth drops and the step response becomes slower.3-dB bandwidth is equal to 1=R1 C1 . creating “fuzzy” edges.7 Solution Equation (11.

Setting Vin to zero. The designer must therefore be able to identify the poles intuitively so as to determine which parts of the circuit appear as the “speed bottleneck. Assume = 0 VDD RD RS M1 C in CL Vout Example 11. the Bode approximation ignores the 3-dB roll-off at the pole frequency—but 2 2 it greatly simpliﬁes the algebra.15) .1 . we recognize that the gate of M1 sees a resistance of RS and a capacitance of Cin to ground. (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11.8 V in Figure 11.4 serves as a good example for identifying poles by inspection. RD = 2 k .4 Association of Poles with Nodes The poles of a circuit’s transfer function play a central role in the frequency response.cls v. 11 Frequency Response to Fig. and CL = 100 fF. Applicable to many circuits.9 log ω Exercise Construct the Bode plot for gm = 150 . Solution j!p1 j = R 1 : C S in (11.5) reveals that the pole frequency is given by the inverse of the product of the total resistance seen between the output node and ground and the total capacitance seen between the output node and ground. As evident from Eq. 2007 at 13:42 544 (1) 544 Chap.5(b).” The CS topology studied in Example 11.10. Equation (11.1 to the transfer function. then it contributes a pole of magnitude Rj Cj . 11. 11.10 . Determine the poles of the circuit shown in Fig. Thus. for RD CL ! 2 1.6). this observation can be generalized as follows: if node j in the signal path exhibits a small-signal resistance of Rj to ground and a capacitance of Cj to ground. Bode’s rule provides a good approximation.1. 2006] June 30. V 20log out V in g m RD −2 0 dB e /d c ω p1 Figure 11.

2007 at 13:42 545 (1) Sec. Assume = 0. at what frequency does the gain drop by 3 dB? Compute the poles of the circuit shown in Fig.18) !p1 = .11 .cls v.16) Since the low-frequency gain of the circuit is equal to .11. 11. 11. the “output pole” is given by j!p2 j = R 1C : D L (11. With Vin = 0. Similarly. the small-signal resistance seen at the source of yielding a pole at Solution M1 is given by RS jj1=gm. 2006] June 30.gm RD .9 V in C in Figure 11.1 Fundamental Concepts 545 We may call !p1 the “input pole” to indicate that it arises in the input network. VDD RD Vout RS M1 Vb CL Example 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we can readily write the magnitude of the transfer function as: gm RD Vout = q : Vin 2 2 1 + !2 =!p11 + !2 !p2 (11. (11.17) Exercise If !p1 = !p2 .

The output pole is given by !p2 1 : RS jj g1 Cin m = RD CL .1 . Exercise How do we choose the value of pole frequency? RD such that the output pole frequency is ten times the input .

however.13(a). pears between nodes 1 and 2. 11.21) .. (These requirements guarantee that the circuit does not “feel” the transformation. V2 : ZF Z2 Denoting the voltage gain from node 1 to node 2 by Av . (b) equivalent of (a) as obtained from Miller’s theorem. 2 (11. ap1 ZF 2 1 2 V1 V2 Z1 V1 V2 Z2 (a) (b) Figure 11. 2007 at 13:42 546 (1) 546 Chap. thereby allowing association of one pole with each node.20) (11.cls v. 11. 11 Frequency Response The reader may wonder how the foregoing technique can be applied if a node is loaded with a “ﬂoating” capacitor. In the late 1910s. a capacitor whose other terminal is also connected to a node in the signal path (Fig. 11.12 make it desirable to obtain a method that “transforms” a ﬂoating capacitor to two grounded capacitors. we cannot utilize this technique and must write the circuit’s equations and obtain the transfer function. where the ﬂoating impedance.13(a) must be equal to that drawn by Z1 in Fig. ZF . V2 = . VDD RD CF V in RS M1 Vout Figure 11. 11.13(b). We wish to transform ZF to two grounded impedances as depicted in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. an approximation given by “Miller’s Theorem” can simplify the task in some cases. Consider the general circuit shown in Fig. 2006] June 30. we obtain Z1 = ZF V V1 V 1.) Thus.12 Circuit with ﬂoating capacitor. Miller’s theorem. Miller’s theorem is such a method. and (2) the current injected to node 2 in Fig. To determine Z1 and Z2 .19) (11.13(a) must be equal to that injected by Z2 in Fig. 11. V2 = V1 ZF Z1 V1 . 11. 11.13 (a) General circuit including a ﬂoating impedance. we make two observations: (1) the current drawn by ZF from node 1 in Fig.13(b). was originally conceived for another reason. He then proposed an analysis that led to the theorem.13(b). i.e.1. John Miller had observed that parasitic capacitances appearing between the input and output of an ampliﬁer may drastically lower the input impedance. V1 . while ensuring all of the currents and voltages in the circuit remain unchanged.12). However.5 Miller’s Theorem Our above study and the example in Fig. 11. 11. In general.

Applying (11. we have Z Z1 = 1 . (b) equivalent circuit as obtained from Miller’s theorem. As an important example of Miller’s theorem.22) and (11.. 0 F v (11. A v = (11.1 Fundamental Concepts 547 Z = 1 .FA 1 = 1 + A C s .A0 is made.24): Z2 = ZF 1 1.cls v.25) (11. 2007 at 13:42 547 (1) Sec. 2006] June 30.14(a)].23) (11. a capacitor CF tied between the input and output of an inverting ampliﬁer with a gain of A0 raises the input capacitance by an amount equal to 1+ A0 CF . CF . the results expressed by (11. What type of impedance is Z1 ? The 1=s dependence suggests a capacitor of value 1 + A0 CF . as if CF is “ampliﬁed” by a factor of 1 + A0 .24) prove extremely useful in analysis and design.22) V Z2 = ZF V . 11.22) suggests that the ﬂoating impedance is reduced by a factor of 1 . In particular.22). We say such a circuit suffers from “Miller multiplication” of the capacitor. 2V 1 2 ZF : = 1 1. In other words.24) Called Miller’s theorem.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (11. CF V in −A 0 Vout −A 0 ∆ V V in CF ( 1 + A 0 ( −A 0 Vout CF ( 1 + 1 ( A0 ∆V (a) (b) Figure 11.FA and v (11. Av when “seen” at node 1. tied between the input and output of an inverting ampliﬁer [Fig.27) . 11. let us assume ZF is a single capacitor.26) where the substitution Av = .14 (a) Inverting circuit with ﬂoating capacitor. The effect of CF at the output can be obtained from (11. A v (11.

28) which is close to CF s. 11. The output then goes down by A0 V .1 if A0 1. the voltage across CF increases by 1 + A0 V . Suppose the input voltage in Fig. That is. 1 . The Miller multiplication of capacitors can also be explained intuitively.14(b) summarizes these results. Figure 11.14(a) goes up by a small amount V . 1 1 + A CF s 0 (11. requiring that the input provide a .

By contrast. 11. m RD !in = R 1 C .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. it would experience only a voltage change of V and require less charge. The above study points to the utility of Miller’s theorem for conversion of ﬂoating capacitors to grounded capacitors.cls v.15 Noting that M1 and RD constitute an inverting ampliﬁer having a gain of . 2006] June 30. 2007 at 13:42 548 (1) 548 Chap.30) Cout = 1 + g 1 CF .29) (11. we utilize the results in Fig.gm RD .10 VDD RD Vout C out Figure 11. VDD RD CF V in RS M1 Vout V in RS M1 C in (a) (b) Example 11. The following example demonstrates this principle. 11. 11 Frequency Response proportional charge.15(a). Assume = 0. Estimate the poles of the circuit shown in Fig.14(b) to write: Solution Cin = 1 + A0 CF = 1 + gmRD CF and (11. if CF were not a ﬂoating capacitor and its right plate voltage did not change.

15(b).34) RD 1 + g 1 CF m RD .31) thereby arriving at the topology depicted in Fig.8. (11. we have: = R 1 + g1 R C S m D F S in (11. 11. From our study in Example 11.33) and !out = R 1 D Cout = (11.32) (11.

35) . 1 : (11.

11. if A0 is expressed in terms of circuit parameters at the frequency of interest.38) .10 the “Miller approximation.e. 2006] June 30. we call the procedure in Example 11. and (b) its frequency response.” Without this approximation.6 General Frequency Response Our foregoing study indicates that capacitances in a circuit tend to lower the voltage gain at high frequencies.1 . we say Miller effect raises the input capacitance of the circuit in Fig. 2007 at 13:42 549 (1) Sec.cls v.1. and CF = 80 fF.” For example. gm RD . 11. we know that the existence of CF lowers the voltage gain from the gate of M1 to the output at high frequencies. where the voltage division between C1 and R1 yields Vout C1 v in R1 Vout 1 R 1C 1 (a) (b) V in 1. After all. (11.0 ω Figure 11.37) Vout = p R1 C1 ! : 2 2 2 Vin R1 C1 !1 + 1 (11.15(a) to 1 + gm RD CF .36) (11. Miller’s theorem requires that the ﬂoating impedance and the voltage gain be computed at the same frequency whereas Example 11. It is possible that capacitors reduce the gain at low frequencies as well. The reader may ﬁnd the above example somewhat inconsistent. consider the high-pass ﬁlter shown in Fig.16 (a) Simple high-pass ﬁlter. As a simple example.3.4. even for the purpose of ﬁnding high-frequency poles..16(a). application of Miller’s theorem would be no simpler than direct solution of the circuit’s equations. i.10 uses the low-frequency gain. 11. Another artifact of Miller’s approximation is that it may eliminate a zero of the transfer function. Vout s = R1 Vin R1 + C1 s 1 s = R R1 C1+ 1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Owing to this inconsistency.1 Fundamental Concepts 549 Exercise Calculate Cin if gm = 150 . The general expression in Eq. We return to this issue in Section 11. This reduction of impedance (hence increase in capacitance) is called “Miller effect. 1 C1 s and hence (11. 11. RD = 2 k .22) can be interpreted as follows: an impedance tied between the input and output of an inverting ampliﬁer with a gain of Av is lowered by a factor of 1 + Av if seen at the input (with respect to ground).

out = Cm L = 2 20 kHz.17 lishes a gate bias voltage equal to VDD for M1 .16. 20 kHz. the input network consisting of Ri and Ci attenuates the signal at low frequencies.40) (11.37). and R1 = 100 k . 2006] June 30. thus obtaining Solution Ci = 79:6 nF: (11. we set the corner frequency 1=Ri Ci to 2 20 Hz. The low-frequency roll-off may prove undesirable. gm = 1=200 . the source follower can tolerate a very large load capacitance (for the audio band). this roll-off arises because the zero of the transfer function occurs at the origin. 11. we have g !p.39) This value is. Assume = 0.17 depicts a source follower used in a high-quality audio ampliﬁer. (11. VDD V in Ci Ri M1 Vout I1 CL Ri estab- Figure 11.38) reveals a 3-dB attenuation at ! = 1=Ri Ci . . As seen from Eq.cls v. (11. of course.11 Figure 11.42) An efﬁcient driver. Similar to the high-pass ﬁlter of Fig. much to large to be integrated on a chip. To ensure that audio components as low as 20 Hz experience a small attenuation. CL = 39:8 nF: (11. and recognizing that the resistance seen from the output node to ground is equal to 1=gm .41) and hence (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.16(b). 11 Frequency Response Plotted in Fig. 2007 at 13:42 550 (1) 550 Chap. Here. Exercise Repeat the above example if I1 and the width of M1 are halved. and I1 deﬁnes the drain bias current. in practice we must choose even a larger capacitor if a lower attenuation is desired. the response exhibits a roll-off as the frequency of operation falls below 1=R1 C1 . The following example illustrates this point. Since Eq. lowering the gain at high frequencies. Determine the minimum required value of C1 and the maximum tolerable value of CL . 11. Example 11. The load capacitance creates a pole at the output node. Setting the pole frequency to the upper end of the audio range.

cls v.19 shows a typical frequency response and the terminology used to refer to its H Midband Gain Midband ωL Figure 11. and we would not need perform the above calculations. Since VGS1 + VI 1 may reach 600-700 mV. Ci isolates the bias conditions of the source follower from those of the preceding stage. the band between !L and !H is called the “midband range” and the corresponding gain the “midband gain. thereby maximizing the voltage gain of the CS stage (why?). where VI 1 denotes the minimum voltage required by I1 . 2007 at 13:42 551 (1) Sec.” . VY can be chosen relatively low (placing M2 near the triode region) to allow a large drop across RD . Figure 11. VTH 2 . especially at low supply voltages.18(a) illustrates an example. 2006] June 30.. Figure 11. where a CS stage precedes the source follower. many integrated circuits also employ capacitive coupling. On the other hand. we consider the case of “direct coupling” [Fig.19 Typical frequency response. e. the two stages are quite incompatible in terms of their bias points. if the necessary capacitor values are no more than a few picofarads. Nonetheless. We call !L the lower corner or lower “cut-off” frequency and !H the upper corner or upper cut-off frequency. the circuit’s gain would not fall at low frequencies. 200 mV. necessitating capacitive coupling. 11.g.18(a). at nodes X and Y . The coupling capacitor permits independent bias voltages VDD RD Y Ci V in M2 X I1 (a) VDD RD Ri M1 Vout V in P M2 M1 Vout I1 (b) Figure 11. we wish to set VP just above VGS 2 . the gate of M2 must reside at a voltage of at least VGS 1 + VI 1 . Capacitive coupling (also called “ac coupling”) is more common in discrete circuit design due to the large capacitor values required in many applications (e. Ci in the above audio example).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.1 Fundamental Concepts 551 Why did we use capacitor Ci in the above example? Without Ci .. In other words. Chosen to accommodate the signal frequencies of interest.18 Cascade of CS stage and source follower with (a) capacitor coupling and (b) direct coupling. Here. 11.g. to maximize the voltage gain.18(b)] as well. Called a “coupling” capacitor. Ci allows the signal frequencies of interest to pass through the circuit while blocking the dc content of Vin . ωH ω various attributes. To convince the reader that capacitive coupling proves essential in Fig. 11. For example.

the charge carriers stored in the base must be removed for the collector current to drop to zero. (c) complete model accounting for base charge. if the transistor is suddenly turned on. It is therefore necessary to study these capacitances carefully. we must change the base charge proﬁle by injecting or removing some electrons or holes.2 High-Frequency Models of Transistors The speed of many circuits is limited by the capacitances within each transistor. 6 As mentioned in Chapter 4. proper operation does not begin until enough charge carriers enter the base region and accumulate so as to create the necessary proﬁle. . Since Cb and Cje appear in parallel. The depletion region associated with the junctions6 gives rise to a capacitance between base and emitter. 2006] June 30. and another between base and collector.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. As explained in Chapter 4.cls v. denoted by C [Fig. if the transistor is suddenly turned off. 11. Similarly. both forward-biased and reversed-biased junctions contain a depletion region and hence a capacitance associated with it. this effect is typically more signiﬁcant than the depletion region capacitance. The above phenomenon is quite similar to charging and discharging a capacitor: to change the collector current. 11.20 (a) Structure of bipolar transistor showing junction capacitances. 2007 at 13:42 552 (1) 552 Chap.20(c)]. the operation of the transistor requires a (nonuniform) charge proﬁle in the base region to allow the diffusion of carriers toward the collector. (b) small-signal model with junction capacitances. C n B p Cµ B C je n+ C je rπ Cµ C vπ g vπ m rO E (a) E (b) Cµ B Cπ rπ vπ g vπ m rO C E (c) Figure 11. 11 Frequency Response 11.20(a)].1 High-Frequency Model of Bipolar Transistor Recall from Chapter 4 that the bipolar transistor consists of two pn junctions. Cb . Modeled by a second capacitor between the base and emitter. denoted by Cje . Unfortunately. 11. 11. We may then add these capacitances to the small-signal model to arrive at the representation shown in Fig. they are lumped into one and denoted by C [Fig.20(b). In other words.2. this model is incomplete because the base-emitter junction exhibits another effect that must be taken into account.

22(b). C B E B Cπ rπ vπ g vπ m rO Cµ C C CS B Cπ E E (a) (b) (c) Cµ C C CS p n Substrate n+ C CS Figure 11. Cje . and then construct the small-signal equivalent circuit.12 Identify all of the capacitances in the circuit shown in Fig.cls v. 11. 2007 at 13:42 553 (1) Sec.21 (a) Structure of an integrated bipolar transistor. we add the three capacitances of each transistor as depicted in Fig. 11. the bipolar transistor is fabricated atop a grounded substrate [Fig. 11.21(b). . We may therefore represent the transistor as shown in Fig. 2006] June 30. Example 11. CCS 1 and C2 appear in parallel.21(c). 11. In the analysis of frequency response. The complete model is depicted in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. C . The collector-substrate junction remains reverse-biased (why?).22(a).2 High-Frequency Models of Transistors 553 In integrated circuits. (c) device symbol with capacitances shown explicitly. simplify the result. 11. In modern integrated-circuit bipolar transistors. Interestingly.22 Solution From Fig.21(a)]. (b) small-signal model including collectorsubstrate capacitance. VCC VCC RC Vout V b1 V in Q2 Q1 V in C π1 Vb C π2 C µ1 Q1 C CS1 Q2 C CS2 C µ2 RC Vout (a) (b) Figure 11. 11. and so do C2 and CCS 2 . it is often helpful to ﬁrst draw the transistor capacitances on the circuit diagram. Exercise Construct the small-signal equivalent circuit of the above cascode. We hereafter employ this model in our analysis.21(b). 11. exhibiting a junction capacitance denoted by CCS . and CCS are on the order of a few femtofarads for the smallest allowable devices.

25.26(b). (b) partitioning of gate-channel capacitance between source and drain. this representation consists of: (1) the capacitance between the gate and source. 11. Example 11.2. CGS (including the overlap component). Illustrated in Fig. Two other capacitances in the MOSFET become critical in some circuits. 11.23 (a) Structure of MOS device showing various capacitances. 11. and two associated with the reverse-biased source-bulk and drain-bulk junctions. the MOSFET displays three prominent capacitances: one between the gate and the channel (called the “gate oxide capacitance” and given by WLCox ). C2 n + C1 n + p −substrate (a) (b) Figure 11. . 11. 11. 11. C1 is about 2=3 of the gate-channel capacitance whereas C2 0. the S/D areas protrude under the gate during fabrication. CSB and CDB . 11. 2007 at 13:42 554 (1) 554 Chap.2 High-Frequency Model of MOSFET Our study of the MOSFET structure in Chapter 6 revealed several capacitive components.24.23(b)].2. Depicted in Fig. CGD2 is shorted 7 As mentioned in Chapter 6. 11 Frequency Response 11. The exact partitioning of this capacitance is beyond the scope of this book.13 Identify all of the capacitances in the circuit of Fig. n+ Figure 11. in the saturation region.23(a). Called the gatedrain or gate-source “overlap” capacitance. (3) the junction capacitances between the source and bulk and the drain and bulk.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (We assume the bulk remains at ac ground.25(a). The ﬁrst component presents a modeling difﬁculty because the transistor model does not contain a “channel.25(b)] before constructing the small-signal model. respectively. but. (2) the capacitance between the gate and drain (including the overlap component). 2006] June 30.26(a).) As mentioned in Section 11. we arrive at the circuit in Fig. 11.24 Overlap capacitance between gate and drain (or source). this (symmetric) effect persists even if the MOSFET is off. Solution Adding the four capacitances of each device from Fig. Shown in Fig. these components arise from both the physical overlap of the gate with source/drain areas7 and the fringe ﬁeld lines between the edge of the gate and the top of the S/D regions. we often draw the capacitances on the transistor symbol [Fig.1.cls v. We now study these capacitances in the device in greater detail.” We must therefore decompose this capacitance into one between the gate and the source and another between the gate and the drain [Fig. Note that CSB 1 and CSB 2 are shorted to ac ground on both ends. We now construct the high-frequency model of the MOSFET.

is it possible to deﬁne a quantity that represents the ultimate speed of the transistor? Such a quantity would prove useful in comparing different types or generations of transistors as well as in predicting the performance of circuits incorporating the devices. 2007 at 13:42 555 (1) Sec. 11. 11.25 (a) High-frequency model of MOSFET. The circuit therefore reduces to that in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. (b) device symbol with capacitances shown explicitly. 2006] June 30. . 11. Exercise Noting that M2 is a diode-connected device. A measure of the intrinsic speed of transistors8 is the “transit” or “cut-off” frequency. VDD C GS2 VDD M2 Vout V in M1 V in C GS1 C GD2 C GD1 M1 V in C DB1 C SB1 (a) (b) (c) C SB2 M2 C DB2 Vout C GD1 C SB2 VDD M2 Vout M1 C GS1 C DB1 + C DB2 + C GS2 C SB1 Figure 11.2 High-Frequency Models of Transistors C GD C GD 555 G C GS v GS S C SB g mv GS rO D C DB G C GS D C DB S C SB (a) (b) Figure 11.26(c). fT .3 Transit Frequency With various capacitances surrounding bipolar and MOS devices. CDB 2 .cls v.2. construct the small-signal equivalent circuit of the ampliﬁer.26 “out. 8 By “intrinsic” speed. we mean the performance of the device by itself.” and CDB 1 . and CGS 2 appear in parallel at the output node. without any other limitations imposed or enhancements provided by the circuit.

11.cls v. g !T Cm The transit frequency of MOSFETs is obtained in a similar fashion. the input capacitance of the device lowers the input impedance. Zin .27 (without the biasing circuitry). We note that.46) (11. the magnitude of the current gain falls to unity: 2 2 2 r C !T = 2 (11. is increased. Modern bipolar and MOS transistors boast fT ’s above 100 GHz. We neglect C and CGD here (but take them into account in Problem 26). the idea is to inject a sinusoidal current into I out ac GND I out ac GND Q1 I in Vin C in I in Vin C in M1 Figure 11. the inevitable reduction of the supply voltage has reduced the gate-source overdive voltage from about 400 mV to 100 mV.14 . 2006] June 30. 2007 at 13:42 556 (1) 556 Chap. We therefore write: (11. By what factor has the fT of MOSFETs increased? Example 11.44) (11. Zin = C1 s jjr : Since Iout (11. Also.47) That is.49) Note that the collector-substrate or drain-bulk capacitance does not affect fT owing to the ac ground established at the output. the base or gate and measure the resulting collector or drain current while the input frequency. the speed of complex circuits using such devices is quite lower. 11. fin . The minimum channel length of MOSFETs has been scaled from 1 m in the late 1980s to 65 nm today. and hence the input voltage Vin = Iin Zin and the output current. Illustrated in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. !T = 2fT .27(a).48) g g 2fT Cm or C m : GS (11. as fin increases.45) 2: .27 Conceptual setup for measurement of fT of transistors. For the bipolar device in Fig.43) = gmIin Zin .1 (11. Iout = gm r Iin r C s + 1 = r C s + 1: At the transit frequency. Of course. 11 Frequency Response deﬁned as the frequency at which the small-signal current gain of the device falls to unity.

Speciﬁcally. the supply voltage or constant bias voltages). 6. the frequency response also includes the phase of the transfer function. For example.50) Thus. Miller’s theorem proves helpful in decomposing ﬂoating capacitors into grounded elements. We now apply this procedure to various ampliﬁer topologies. In order to methodically analyze the frequency response of various circuits. Plot the frequency response using Bode’s rules or exact calculations. . 9 In a more general case. Miller’s theorem may prove useful here. the transistor capacitances can be neglected as they typically impact only the high-frequency region. we have observed that: The frequency response refers to the magnitude of the transfer function of a system. Calculate the midband gain by replacing the above capacitors with short circuits while still neglecting the transistor capacitances. Exercise Determine the fT if the channel length is scaled down to 45 nm but the mobility degrades to 300 cm2 =(Vs). 11.3 Analysis Procedure We have thus far seen a number of concepts and tools that help us study the frequency response of circuits. 2.9 Bode’s approximation simpliﬁes the task of plotting the frequency response if the poles and zeros are known. Identify and add to the circuit the capacitances contributed by each transistor. merge the capacitors that are in parallel and omit those that play no role in the circuit. Noting ac grounds (e. 4. 11. In many cases. it is possible to associate a pole with each node in the signal path. Determine which capacitors impact the low-frequency region of the response and compute the low-frequency cut-off.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 557 (1) Sec. 5. 3. VTH : 2 L2 (11.cls v. we prescribe the following steps: 1.g. then 65-nm devices having an overdrive of 100 mV exhibit an fT of 226 GHz. if n = 400 cm2 =(Vs). Determine the high-frequency poles and zeros by inspection or by computing the transfer function.. Bipolar and MOS devices exhibit various capacitances that limit the speed of circuits. 2006] June 30. the transit frequency has increased by approximately a factor of 59.3 Analysis Procedure 557 Solution It can proved (Problem 28) that 2fT = 3 n VGS . as studied in Chapter 12. In this calculation.

min : (11. At low frequencies. this network attenuates the low frequencies.28(b)] so as to remove the effect of degeneration at midband frequencies.16. and note that both R1 and R2 are tied between X and ac ground. (b) effect of bypassed degeneration. To quantify the role of Cb . 2007 at 13:42 558 (1) 558 Chap.28(a)]. we place its impedance. 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the gain of ampliﬁers may fall at low frequencies due to certain capacitors in the signal path.51) (11.4 Frequency Response of CE and CS Stages 11. 1=Cb s.52) Similar to the high-pass ﬁlter of Fig. leaving only Ci as the frequency-dependent component. Thus.28 (a) CS stage with input coupling capacitor.1 Low-Frequency Response As mentioned in Section 11.4. (c) frequency response with bypassed degeneration. negligibly affect the frequency response. 11.6.RD =RS + 1=gm and VX s = R1 jjR2 Vin R1 jjR2 + C1s i R1 jjR2 Ci s : = R jjR C s + 1 1 2 i (11.gmRD RS Cb s + 1 : = R C s+g R +1 S b m S (11.55) Figure 11. and at frequencies well above .53) In applications demanding a greater midband gain. the stage operates as a degenerated CS ampliﬁer. fsig. At frequencies well below the zero.54) (11. the transistor capacitances VDD R1 X V in Ci M1 R2 RS V in RD Vout Ci R1 X M1 R2 RS Cb VDD RD Vout g m RD 1 + g m RS 1 R SCb (a) (b) 1 + g m RS R SCb (c) Vout VX g m RD ω Figure 11. neglect channel-length modulation. dictating that the lower cut-off be chosen below the lowest signal frequency. 2006] June 30. 11 Frequency Response 11.cls v. we place a “bypass” capacitor in parallel with RS [Fig.g. Let us consider a general CS stage with its input bias network and an input coupling capacitor [Fig. We write Vout =Vin = Vout =VX VX =Vin . 20 Hz in audio applications): 1 2 R1 jjR2 Ci fsig. 11.min (e.RD VX RS jj C1 s + g1 b m . Vout =VX = .. in parallel with RS in the midband gain expression: Vout s = .1.28(c) shows the Bode plot of the frequency response in this case.

where the source-bulk capacitance of M1 is grounded on both ends. .29(b). (d) uniﬁed model of both circuits.4 Frequency Response of CE and CS Stages 559 the pole. With this uniﬁed model.10 and can be reduced to one if Vin . we arrive at the complete circuits depicted in Fig. 11. ﬁrst applying Miller’s approximation to develop insight and then performing an accurate analysis to arrive at more general results.2 High-Frequency Response Consider the CE and CS ampliﬁers shown in Fig. where RS may represent the output impedance of the preceding stage. Thus. (c) small-signal equivalents. Identifying the capacitances of Q1 and M1 .e. 2007 at 13:42 559 (1) Sec. 11. RS r and hence RThev RS . (b) inclusion of transistor capacitances.29(a).cls v. 11. In practice. Both types exhibit low-frequency rolloff due to the input coupling capacitor and the degeneration bypass capacitor. Note that the output resistance of each transistor would simply appear in parallel with RL . the circuit experiences no degeneration..4. the pole frequency must be chosen quite smaller than the lowest signal frequency of interest.29 (a) CE and CS stages.29(d)]. i. it is not added deliberately.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. VCC VCC RL V in RS Q1 Vout V in RS M1 RL Vout V in RS Cπ Q1 C CS VDD RL Cµ Vout V in C GS C SB (a) (b) VDD RL C GD M1 Vout C DB Cµ V in RS Vout Cπ rπ vπ g Vπ m C CS RL V in RS C GD Vout C GS v GS g mV GS C DB RL (c) C XY R Thev X V Thev C in VX Y g mV X C out RL Vout (d) Figure 11.29(c)]. The small-signal equivalents of these circuits differ by only r [Fig. 11. The above analysis can also be applied to a CE stage. we now study the high-frequency response. 10 The Early effect and channel-length modulation are neglected here. 2006] June 30. 11. RS and r are replaced with their Thevenin equivalent [Fig. 11.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we can decompose CXY into two grounded components (Fig.10. 2006] June 30.30): CX = 1 + gm RL CXY CY = 1 + g 1 CXY : m RL . we cannot simply associate one pole with each node.4.3 Use of Miller’s Theorem With CXY tied between two ﬂoating nodes. 11. 11 Frequency Response 11. following Miller’s approximation as in Example 11. 2007 at 13:42 560 (1) 560 Chap.cls v. However.

1.57) Now. (11. In accordance with our notations in Section 11. each node sees a resistance and capacitances only to ground.56) (11. we write 1 Thev Cin + 1 + gm RL CXY .

The input pole is approximately given by the source resistance. and the Miller multiplication of the base-collector or gate-drain capacitance. In the CE stage of Fig. = 100.in j = R (11. 11. C = 20 fF.30 Parameters in uniﬁed model of CE and CS stages with Miller’s approximation. (11. and the basecollector or gate-drain capacitance.out j = RL Cout + 1 + g R CXY j!p. The intuition gained from the application of Miller’s theorem proves invaluable. the collector-substrate or drain-bulk capacitance. 1 1 : j!p.59) thus .15 Solution = 2:6 k . and CCS = 30 fF. the base-emitter or gate-source capacitance.59) m L If gm RL 1. RS = 200 . the capacitance at the output node is simply equal to Cout + CXY . Fig.58) and (11.29(a).58) (11. IC = 1 mA. 11.30 and Eqs. (a) Calculate the input and output poles if RL = 2 k . we have RThev = 186 . The output pole is roughly determined by the load resistance. C = 100 fF. The Miller multiplication makes it undesirable to have a high gain in the circuit. R Thev V Thev CX C in X vX Y g mv X C out CY RL Vout CE Stage rπ V Thev = V in r π + RS R Thev = R S r π CS Stage V Thev = V in R Thev = R S C X = C GD ( 1 + g m R L ( 1 ( C Y = C GD ( 1 + g m RL CX = C µ ( 1 + g m RL ( 1 ( CY = C µ ( 1 + g m RL Figure 11. Which node appears as the speed bottleneck (limits the bandwidth)? (b) Is it possible to choose RL such that the output pole limits the bandwidth? (a) Since r Example 11.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. gm RS jjr C RL RS jjr C : (11. then we have CCS + C . As a result.cls v. 11. Solution Both the width and the bias current of the transistor are halved. the left-hand side is negative. gm RL .in j !p. Example 11.60) (11. Thus. The small-signal gain. 11. 2006] June 30.59). is therefore halved. The reader can prove that this holds even if gm RL is not much greater than unity. we can express the poles as 1 R in RS 2 + 1 + gm2 L CXY 2 . Assuming that the bias current is also halved. From Fig. the input pole remains the speed bottleneck here. (11.in j = 2 516 MHz j!p.61) We observe that the Miller effect multiplies C by a factor of 78. the student uses a MOSFET half as wide as that in the original design. Reducing the transistor width by a factor of two also lowers all of the capacitances by the same factor. Unfortunately. determine the gain and the poles of the circuit.30 and Eqs.63) With the values assumed in this example. (b) We must seek such a value of RL that yields j!p.16 An electrical engineering student designs the CS stage of Fig.29(a) for a certain lowfrequency gain and high-frequency response. and so is its transconductance (why?).58) and (11. 2007 at 13:42 561 (1) Sec.out j: 1 RS jjr C + 1 + gmRL C If gm RL 1 : RL CCS + 1 + g 1 C R m L (11. 11. implying that no solution exists.4 Frequency Response of CE and CS Stages 561 give j!p.out j = 2 1:59 GHz: (11. the input pole limits the bandwidth.62) 1. Exercise Repeat the above example if IC = 2 mA and C = 180 fF. in the layout phase. making its contribution much greater than that of C .

in j = C .out j = C out + 1 + 2 RL 2 g R 2 j!p. j!p. 1 CXY .

(11. In other words. .64) (11. CXY and Cout denote the parameters corresponding to the original device width. and !p.out by approximately a factor of two (if gm RL 2). gm . suggesting that the gain-bandwidth product is approximately constant.65) m L where Cin .in has risen in magnitude by more than a factor of two. the gain is halved and the bandwidth is roughly doubled. We observe that !p.

VX CXY s = VX Cin s + VXR VThev At Node Y : VX . That is.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11 Frequency Response Exercise What happens if both the width and the bias current are twice their nominal values? 11. 11. we must carry out a more accurate analysis so as to understand the limitations of Miller’s approximation in this case.cls v.4 Direct Analysis The use of Miller’s theorem in the previous section provides a quick and intuitive perspective of the performance. Vout CXY s = gm VX + Vout R + Cout s : L We compute VX from (11. However.29(d) contains two nodes and can therefore be solved by writing two KCLs. 2006] June 30. At Node X : Vout .4.67): .11 . The circuit of Fig. 2007 at 13:42 562 (1) 562 Chap.

66) (11. Thev 1 (11. CXY s + Cin s + R Thev It follows that .68) Vout CXY s . m and substitute the result in (11.66) to arrive at (11.67) 1 CXY s + R + Cout s VX = Vout C s L g XY .

gm L + Cout s Vout = .70) a = RThev RL Cin CXY + Cout CXY + Cin Cout b = 1 + gmRL CXY RThev + RThev Cin + RL CXY + Cout : (11. (11.70) must be multiplied by r =RS + r to obtain Vout =Vin —without affecting the location of the poles and the zero.71) (11. Let us examine the above results carefully. 1 CXY s + R1 CXY s . where (11.30 that for a CE stage.69) Vout CXY s . (11. gm RL VThev s = as2 + bs + 1 . 11.VThev : R Thev (11.73) .72) Note from Fig. The transfer function exhibits a zero at !z = Cgm : XY 11 Recall that we denote frequency-domain quantities with upper-case letters.

the system contains two poles given by the values of s that force the denominator to zero. the zero typically appears at very high frequencies and hence is unimportant. 2007 at 13:42 563 (1) Sec. we can write .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.) Since CXY (i. Instead. We can solve the quadratic as2 + bs + 1 = 0 to determine the poles but the results provide little insight..12 As expected. 11. 2006] June 30. the base-collector or the gate-drain overlap capacitance) is relatively small. we ﬁrst make an interesting observation in regards to the quadratic denominator: if the poles are given by !p1 and !p2 .cls v.e.4 Frequency Response of CE and CS Stages 563 (The Miller approximation fails to predict this zero.

s .

s as + bs + 1 = ! + 1 ! + 1 p1 .

78) (11. p1 and from (11. !p11 + !p21 !p11 .31(a).76) j!p1 j = 1 + g R C R + R1 C + R C + C : m L XY Thev Thev in L XY out (11. . 1 p2 1 2 s 2 (11.82) 12 As explained in more advanced courses.79) R R R XY = 1 + gm RL CXYC Thev + +Thev Cin ++ LCC + Cout : RThev RL in CXY Cout CXY Cin out Example 11. simplifying the result as illustrated in Fig. we add the remaining capacitances as depicted in Fig.31(b).31(c). CGS 2 ..77) does reveal the Miller effect of CXY but it also contains the additional term RL CXY + Cout [which is close to the output time constant predicted by (11. Then.59)].75) and (11. we recognize from (11. 11. where Solution Cin = CGS1 CXY = CGD1 Cout = CDB1 + CGD2 + CDB2 : (11. and CSB 2 do not affect the circuit (why?). (11.75) = ! ! + ! + ! s + 1: p1 p2 p1 p2 Now suppose one pole is much farther from the origin than the other: !p2 !p1 .81) (11. b = !1 . this zero does become problematic in the internal circuitry of op amps.e.74) (11. Assume both transistors operate in saturation and 6= 0. . Noting that CSB 1 . . 11. To determine the “nondominant” pole.17 Using the dominant-pole approximation. !p2 . compute the poles of the circuit shown in Fig.80) (11.76) that b j!p2 j = a (11. .77) How does this result compare with that obtained using the Miller approximation? Equation (11. i. (This is called the “dominant pole” approximation to emphasize that !p1 dominates the frequency response).72). 11.

out j = 2 428 MHz: (b) The transfer function in Eq.85) (11. 2006] June 30.29(a). we have RS = 200 .84) Exercise Repeat the above example if 6= 0.10 s. Eqs. (11. (c) the dominant-pole approximation. (b) the exact transfer function. Also. (11.31 It follows from (11. (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11.70) gives a zero at gm =CGD a = 2:12 10.83) (11. Thus. gm = 150 . Plot the frequency response with the aid of (a) Miller’s approximation.59) yield j!p.58) and (11.88) j!p1 j = 2 264 MHz j!p2 j = 2 4:53 GHz: . CDB = 100 fF.18 Solution = 13:3.87) (11.86) = 2 13:3 GHz).2 and b = 6:39 10.77) and (11. 2007 at 13:42 564 (1) 564 C SB2 M2 VDD Vb V in RS M1 M2 Vout V in RS M1 C GS1 C DB1 C GD2 C GD1 C DB2 Chap. In the CS stage of Fig.79) that !p1 1 + g r jjr C R + R1 C + r jjr C + C m1 O1 O2 XY S S in O1 O2 XY out 1 + gm1rO1 jjrO2 CXY RS + RS Cin + rO1 jjrO2 CXY + Cout : !p2 RS rO1 jjrO2 Cin CXY + Cout CXY + Cin Cout (11.cls v. and RL = 2 k .in j = 2 571 MHz j!p.20 s. CGD = 80 fF. (a) With gm RL Example 11.1 . 11 Frequency Response Vout V in RS C XY Vout M1 C in C out r O1 r O2 (a) (b) (c) Figure 11. CGS = 250 fF. = 0. (11.

77) and (11.5 Input Impedance The high-frequency input impedances of the CE and CS ampliﬁers determine the ease with which these circuits can be driven by other stages. 20 10 0 −10 −20 −30 7 10 10 8 10 Frequency (Hz) 9 10 10 Figure 11. 11.13 (c) The results obtained in part (b) predict that the dominant-pole approximation produces relatively accurate results as the two poles are quite far apart. (11.89) (11. (11.32 plots the results. From Eqs.outj and j!p2 j results from an effect called “pole splitting” and studied in . j!p. Our foregoing analysis of the frequency response and particularly the Miller approximation readily yield this impedance.79). 2006] June 30. we have j!p1 j = 2 249 MHz j!p2 j = 2 4:79 GHz: Figure 11. 13 The large discrepancy between more advanced courses.32 Exercise Repeat the above example if the device width (and hence its capacitances) and the bias current are halved.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4 Frequency Response of CE and CS Stages 565 Note the large error in the values predicted by Miller’s approximation. Exact Eq.90) 13 and the .4. This error arises because we have multiplied CGD by the midband gain 1 + gm RL rather than the gain at high frequencies.cls v.3-dB 30 Magnitude of Transfer Function (dB) Dominant−Pole Appr. The low-frequency gain is equal to 22 dB bandwidth predicted by the exact equation is around 250 MHz. Miller’s Approx. 2007 at 13:42 565 (1) Sec. 11.

11. How large should Ci be? Since Ci appears in series with RS .92) With a high voltage gain. VDD C GD RD M1 C CS Z in C GS RC Q1 C DB (b) Zin C + 1 + 1 R C s jjr : gm D Similarly. . 2007 at 13:42 566 (1) 566 Chap.1 Low-Frequency Response As with CE and CS stages.cls v. the use of capacitive coupling leads to low-frequency roll-off in CB and CG ampliﬁers.33(a). VCC Cµ Cπ Z in (a) Figure 11. the output impedance of the preceding stage (denoted by RS ) is excluded. (b) resulting frequency response. the input impedance of a CE stage consists of two parallel components: C + 1 + gm RD C and r .91) Zin C + 1 + 1 R C s : gm D GD GS (11.14 That is. 2006] June 30.33 Input impedance of (a) CE and (b) CS stages. 11 Frequency Response As illustrated in Fig. Consider the CB circuit depicted in Fig. the MOS counterpart exhibits an input impedance given by (11.5 Frequency Response of CB and CG Stages 11. 11.34 (a) CB stage with input capacitor coupling. where I1 deﬁnes the bias VCC RC Vout Q1 V in RS Ci I1 Vb Vout V in RD RS + 1 gm gm (1 + g m RS ( Ci (b) ω (a) Figure 11.34(a). 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the Miller effect may substantially lower the input impedance at high frequencies.5. we 14 In calculation of the input impedance. current of Q1 and Vb is chosen to ensure operation in the forward active region (Vb is less than the collector bias voltage).

1 in the midband gain expression.95) and suggesting that this pole must remain quite lower than the minimum signal frequency of interest.35 (a) CB and (b) CG stages including transistor capacitances. 11. RC =RS the resulting transfer function as + 1=gm. 2006] June 30. The high-frequency response of these circuits does not suffer from Miller effect.34(b). (3) no capacitance appears between the input and output networks. These two conditions are equivalent. where rO = 1 and the transistor capacitances are VCC RC C CS Y Q1 V in RS X (a) (b) VDD RD Vout Vout C DB Y C GD M1 V in RS X C SB Vb C GS Cµ Vb Cπ Figure 11. Consider the stages shown in Fig. 11. avoiding Miller effect.93) implies that the signal does not “feel” the effect of Ci if jCi s. 11.1 j RS + 1=gm. included.35. In fact. and so do CGD and CDB of M1 . Since Vb is at ac ground. 2007 at 13:42 567 (1) Sec. the total resistance seen to ground is given by RS jj1=gm . we note that (1) C and CGS + CSB go to ground.94) Vout s = RC Vin RS + Ci s.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. an important advantage in some cases. At node X .2 High-Frequency Response We know from Chapters 5 and 7 that CB and CG stages exhibit a relatively low input impedance ( 1=gm ). From another perspective. revealing a pole at j!p j = 1 + ggmR C m S i (11. Eq. and write (11.94) yields the response shown in Fig. we can readily associate one pole with each node.1 + 1=gm Cs = 1 + ggm RC Cis + g : RS i m m Equation (11.93) (11.5 Frequency Response of CB and CG Stages 567 replace RS with RS + Ci s. yielding j!p.X j = .5. 11.cls v. (11. with all of the capacitances seeing ground at one of their terminals. (2) CCS and C of Q1 appear in parallel to ground.

Similarly. j!p. RS jj g1 CX m (11.96) = C or CGS + CSB . where CX 1 .97) .Y j = R 1C . L Y (11. at Y .

cls v. It is interesting to note that the “input” pole magnitude is on the order of the fT of the transistor: CX is equal to C or roughly equal to CGS while the resistance seen to ground is less than 1=gm.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. For this reason. the input pole of the CB/CG stage rarely creates a speed bottleneck. C SB2 VDD M2 Vout RS M1 Vb V in RS Y M1 Vb VDD M2 Vout C DB1 + C GD1 + C GS2 + C DB2 Example 11.36 Noting that CGD2 and CSB 2 play no role in the circuit.X j = . 11. 2007 at 13:42 568 (1) 568 Chap.36(b).19 V in X C SB1 + C GS1 (a) (b) Figure 11. Assume = 0.15 Compute the poles of the circuit shown in Fig. The input pole is thus given by Solution j!p. 11 Frequency Response where CY = C + CCS or CGD + CDB . we add the device capacitances as depicted in Fig. 11. 2006] June 30.36(a).

Example 11. cellphones).20 .99) Exercise Repeat the above example if constant voltage..98) m1 Since the small-signal resistance at the output node is equal to 1=gm2 . i. RS jj g 1 1 CSB1 + CGD1 : (11..Y j = 1 CDB1 + CGD1 + CGS2 + CDB2 g m2 (11. 15 One exception is encountered in radio-frequency circuits (e.18 is reconﬁgured to a common-gate ampliﬁer (with RS tied to the source of the transistor). we have 1 : j!p.e. M2 operates as a current source. Plot the frequency response of the circuit. its gate is connected to a The CS stage of Example 11. where the input capacitance becomes undesirable.g.

the junction capacitances quite equal. however. CSB = CDB .3-dB bandwidth is around 450 MHz.101) j!p.96) and (11. In Chapters 5 and 7.16 we obtain from Eqs. limits the bandwidth. We thus study the high-frequency behavior here. Also.37 Exercise Repeat the above example if the CG ampliﬁer drives a load capacitance of 150 fF. 11. Figure 11.11 and that of CE/CS stages. (11. 2007 at 13:42 569 (1) Sec.6 Frequency Response of Followers The low-frequency response of followers is similar to that studied in Example 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the low-frequency gain is now equal to RD =RS +1=gm = 5:7.X j = 2 5:31 GHz j!p. more than a factor of two lower than that of the CS stage. CSB and CDB sustain different reverse bias voltages and are therefore not . The lowfrequency gain is equal to 15 dB 5:7 and the .6 Frequency Response of Followers 569 Solution With the values given in Example 11.18 and noting that (11.cls v. 20 Magnitude of Frequency Response (dB) 15 10 5 0 −5 −10 −15 −20 6 10 7 8 9 10 10 10 Frequency (Hz) 10 10 Figure 11. we noted that emitter and source followers provide a high input impedance and a relatively low output impedance while suffering from a sub-unity (positive) 16 In reality. 2006] June 30.37 plots the result.Y j = 2 442 MHz: With no Miller effect.97).100) (11. 11. the input pole has dramatically risen in magnitude. The output pole.

The emitter follower is loaded with CL to create both a more general case and greater similarity between the bipolar and MOS counterparts.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.38 differ by only r . Cµ V in RS Cπ X Y VCC RS C GS Vout CL C GD V in X Y VDD C DB M1 Vout C SB + C L Q1 (a) (b) Figure 11.cls v. Emitter followers.39. We observe that each circuit contains two grounded capacitors and one ﬂoating capacitor. We therefore perform a direct analysis by writing the circuit’s equations. we ﬁrst analyze the emitter follower and subsequently let r (or ) approach inﬁnity to obtain the transfer function of the source follower. out RS r and another at the output node: (11. While the latter may be decomposed using Miller’s approximation.38 (a) Emitter follower and (b) source follower including transistor capacitances. 2007 at 13:42 570 (1) 570 Chap. we write a KCL at node X : RS V in Cµ X Cπ rπ Vπ g Vπ m Vout CL Figure 11.39 Small-signal equivalent of emitter follower. 11. 11 Frequency Response voltage gain.103) V = 1 Vout CL s . 2006] June 30. are utilized as buffers and their frequency characteristics are of interest. Recognizing that VX = Vout + V and the current through the parallel combination of r and C is given by V =r + V C s. Vout + V . Consider the small-signal equivalent shown in Fig.104) .38 illustrates the stages with relevant capacitances. and occasionally source followers. 11.102) V + V C s + g V = V C s: m out L r The latter gives (11. Since the bipolar and MOS versions in Fig. the resulting analysis is beyond the scope of this book. Vin + V + V C s + V + V C s = 0. Figure 11. r + gm + C s (11.

105) C Vout = 1 + gm s . 11.cls v. 2006] June 30. 2007 at 13:42 571 (1) Sec.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. . gm1 leads to (11. upon substitution in (11.102) and with the assumption r . Vin as2 + bs + 1 where a = RS C C + C CL + C CL g m b = RS C + C + 1 + RS CL : gm r gm g j!z j = Cm .6 Frequency Response of Followers 571 which.

108) which.115) . j 2:57 GHz : (11.21 (11. from (11.111). respectively: Solution a = 2:58 10. Vin as2 + bs + 1 where (11. Using the transistor parameters given in Example 11.112) (11.21 s.111) A source follower is driven by a resistance of 200 and drives a load capacitance of 100 fF.114) (11.18.110) and (11. The above results also apply to the source follower if r ! 1 and corresponding capacitance substitutions are made (CSB and CL are in parallel): CGS Vout = 1 + gm s . The zero occurs at gm =CGS = 2 4:24 GHz).106) (11.113) !p1 = 2 .2 b = 5:8 10. necessitating direct solution of the quadratic denominator.107) The circuit thus exhibits a zero at (11.4. we obtain a and b from Eqs.4. however.109) a = RS CGD CGS + CGD CSB + CL + CGS CSB + CL gm C b = RS CGD + CGD + g SB + CL : m Example 11.110) (11. (11.11 s The two poles are then equal to (11. plot the frequency response of the circuit.1:79 GHz + j 2:57 GHz !p2 = 2 .1:79 GHz . The poles of the circuit can be computed using the dominant-pole approximation described in Section 11. (11. is near the fT of the transistor. the two poles do not fall far from each other. In practice. To compute the poles.49).

where M2 acts as a current source.5 GHz.41(a).cls v.40 plots the frequency response. Figure 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.3-dB bandwidth is approximately equal to 3. 2006] June 30. 2007 at 13:42 572 (1) 572 Chap.41 .40 Exercise For what value of gm do the two poles become real and equal? Determine the transfer function of the source follower shown in Fig. C GD1 VDD M1 Vout Vb M2 (a) Example 11. the poles are complex. 11 Frequency Response With the values chosen here. 11. 0 Magnitude of Frequency Response (dB) −2 −4 −6 −8 −10 −12 −14 6 10 10 7 10 Frequency (Hz) 8 10 9 10 10 Figure 11. The .22 VDD C DB1 Vout C DB2 + C SB1 C SB2 V in RS V in RS C GS1 X Y C GD2 M1 Vb C GS2 M2 (b) Figure 11.

2007 at 13:42 573 (1) Sec. 11. 11. we include the transistor capacitances as illustrated in Fig.42.109) can be rewritten as Solution CGS1 Vout s = 1 + gm1 s .38. 11. Av = RL + g1 RL . where C and CGS appear between the input and output and can therefore be decomposed using Miller’s theorem. 11. where RL denotes the load resistance. Since the low-frequency gain is equal to Cµ X C XY = C π Y RL (a) VCC C GD X C XY = C GS Y RL (b) VDD C DB Q1 M1 CL C L+ C SB Figure 11. we observed that the input resistance of the emitter follower is given by r + + 1RL .119) m .117) (11. 11.42 Input impedance of (a) emitter follower and (b) source follower. in Chapter 7.41(b). 2006] June 30. Vin as2 + bs + 1 where (11.1 Input and Output Impedances In Chapter 5.6.cls v. We now employ an approximate but intuitive analysis to obtain the input capacitance of followers.18.116) R a = g S CGD1 CGS1 + CGD1 + CGS1 CSB1 + CGD2 + CDB2 m1 b = RS CGD1 + CGD1 + CSB1g+ CGD2 + CDB2 : m1 (11. Consider the circuits shown in Fig. (11. The result resembles that in Fig. (11. Also. Thus. we noted that the source follower input resistance approaches inﬁnity at low frequencies.6 Frequency Response of Followers 573 Noting that CGS 2 and CSB 2 play no role in the circuit. calculate the pole frequencies. but with CGD2 and CDB 2 appearing in parallel with CSB 1 .118) Exercise Assuming M1 and M2 are identical and using the transistor parameters given in Example 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

43.122) Also. (11. thereby providing Cin = CGD1 + 1 . from Fig. the low-frequency gain of the circuit can be written as Av = rO1 jjrO2 : rO1 jjrO2 + g 1 m1 (11. Av CXY 1 = 1 + g R CXY : m L (11. 11.124) Exercise Repeat the above example if = 0.43 Solution From Chapter 7.42(b). 11.123) (11. Of course.121) Interestingly.44(a). C or CGD directly adds to this value to yield the total input capacitance. As usual. We ﬁrst compute the output impedance of the emitter follower and subsequently .23 M2 Figure 11. where other capacitances and resistances are neglected for the sake of simplicity. if gm1 rO1 jjrO2 10. Consider the followers depicted in Fig. At high frequencies. the input capacitance of the follower contains only a fraction of C or CGS . Assume 6= 0. then only 9 of CGS 1 appears at the input. 11. 2006] June 30. Similarly.120) (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the capacitance appearing between the input and output is equal to CGS1 . Av CGS1 = CGD1 + 1 + g 1 jjr CGS1 : m1 rO1 O2 For example. RS represents the output resistance of a preceding stage or device. Let us now turn our attention to the output impedance of followers. Estimate the input capacitance of the follower shown in Fig. Our study of the emitter follower in Chapter 5 revealed that the output resistance is equal to RS = +1+1=gm. 11 Frequency Response we note that the “input” component of C or CGS is expressed as CX = 1 . 2007 at 13:42 574 (1) 574 Chap. Chapter 7 indicated an output resistance of 1=gm for the source follower.cls v. VDD V in Vb M1 Example 11. depending on how large gm RL is. these circuits display an interesting behavior.

11. let r ! 1 to determine that of the source follower.V and also . 11. 2006] June 30.44(b).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 2007 at 13:42 575 (1) Sec. (b) small-signal model. we have IX + gm V r jj C1 s = .cls v.44 (a) Output impedance of emitter and source followers. From the equivalent circuit in Fig.6 Frequency Response of Followers RS Cπ rπ Vπ g Vπ m 575 V in RS Cπ VCC Q1 V in RS C GS VDD M1 IX Z out Z out VX (a) (b) Figure 11.

45 Output impedance of emitter follower as a function of frequency for (a) small RS and (b) large RS .127) and substituting in (11. 11.126). a meaningful result considering that C becomes a short circuit. On the other hand. at low frequencies VX =IX = r + RS = + 1 1=gm + RS = + 1. Z out RS Z out RS RS β + 1 gm RS (a) + 1 ω β + 1 gm (b) + 1 ω Figure 11. Which case is more likely to occur in practice? Since a follower serves to reduce the driving impedance. VX =IX = RS . (11.IX r C sr+ + 1 (11. The two extreme values calculated above for the output impedance of the emitter follower can be used to develop greater insight. the magnitude of this impedance falls with ! if RS 1=gm + RS = + 1 or rises with ! if RS 1=gm + RS = + 1. we say Zout exhibits a capacitive behavior in the former case and an inductive behavior in the latter. at very high frequencies.126) V = .128) IX r C s + + 1 As expected. Plotted in Fig.125) IX + gm V RS . we obtain VX = RS r C s + r + RS : (11. it is reasonable to assume that the follower low-frequency output impedance is lower .45. V = VX : Finding V from (11. In analogy with the impedance of capacitors and inductors.125) (11.

129). The plots of Fig.46 Output impedance of source follower as a function of frequency for (a) small large RS . IX CGS s + gm (11. 2007 at 13:42 576 (1) 576 Chap. ( It is even possible that the inductive output impedance leads to oscillation if the follower sees a certain amount of load capacitance. the inductive behavior is more commonly encountered. displaying a similar behavior. 11. 11. Assuming 6= 0 for M1 and M2 but = 0 for M3 .47 depicts a two-stage ampliﬁer consisting of a CS circuit and a source follower. we have VX = rO1 jjrO2 CGS3 s + 1 : IX CGS3 s + gm3 17 If the follower output resistance is greater than (11. then it is better to omit the follower! . 11 Frequency Response than RS .” Example 11. which is equal to rO1 jjrO2 . VDD Vb V in M2 M3 M1 Vout Z out (a) (b) VDD r O1 r O2 M3 Figure 11. RS and (b) The inductive impedance seen at the output of followers proves useful in the realization of “active inductors. and C with CGD .17 Thus.24 Figure 11.130) RS . Z out 1 gm Z out RS 1 gm (b) RS (a) ω ω Figure 11.129) where + 1=r is replaced with gm .45 are redrawn for the source follower in Fig.46. and neglecting all capacitances except CGS3 . Assuming RS = rO1 jjrO2 in (11.) The above development can be extended to source followers by factoring r from the numerator and denominator of (11.47 Solution The source impedance seen by the follower is equal to the output resistance of the CS stage. compute the output impedance of the ampliﬁer.128) and letting r and approach inﬁnity: VX = RS CGS s + 1 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30.

We wish to combine the desirable properties of the two topologies.5 reveals that the former provides a relatively high input resistance but it suffers from Miller effect whereas the latter exhibits a relatively low input resistance but it is free from Miller effect.4 and the CB/CG stage in Section 11. but gm1 and gm2 are comparable because of their relatively weak dependence upon W=L. gm1 : m2 (11. we recognize that the impedance seen at Y is equal to 1=gm2 . 2007 at 13:42 577 (1) Sec. how about the Miller multiplication of C1 or CGD1 ? We must ﬁrst compute the voltage gain from node X to node Y . As mentioned in Chapter 9. . Indeed. 11. As such. Q1 or M1 .7 Frequency Response of Cascode Stage 577 Exercise Determine Zout in the above example if 6= 0 for M1 -M3 . followed by a CB/CG device.cls v. 11. 2006] June 30. We therefore say the gain from X to Y remains near . this structure can be VCC RL Vout V b1 C µ1 V in RS X (a) VDD RL Vout Vb C GD1 RS X M2 Y M1 Q2 Y Q1 V in (b) Figure 11. yielding a small-signal gain of v Av.1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. obtaining a circuit with a relatively high input resistance and no or little Miller effect.131) (11. 11. Q2 or M2 .48 (a) Bipolar and (b) MOS cascode stages.132) In the bipolar cascode. M1 and M2 need not be identical.18 But. this thought process led to the invention of the cascode topology in the 1940s. gm1 = gm2 (why?). Assuming rO = 1 for all transistors. resulting in a gain of . Consider the cascodes shown in Fig. In the MOS counterpart.XY = vY X g = . the circuit still exhibits a relatively high (for Q1 ) or inﬁnite (for M1 ) input resistance while providing a voltage gain equal to gm1 RL . viewed as a CE/CS transistor.48.1 in most 18 The voltage division between RS and r1 lowers the gain slightly in the bipolar circuit.7 Frequency Response of Cascode Stage Our analysis of the CE/CS stage in Section 11.

Let us continue our analysis and estimate the poles of the cascode topology with the aid of Miller’s approximation. 11. Since the gain from X to Y in this case may not be equal to . we can say this pole is on the order of fT =2.56). Associating one pole with each node. concluding that the Miller effect of CXY = C1 or CGD1 is given by (11.50 along with its capacitances after the use of Miller’s approximation. we have j!p. 2006] June 30.49 Bipolar cascode including transistor capacitances. the pole at node Y often has negligible effect on the frequency response of the cascode stage.137) It is interesting to note that the pole at node Y falls near the fT of Q2 if C2 CCS1 + 2C1 .135) (11.49 is the bipolar cascode along with the transisVCC RL Vout V b1 V in RS X Y Q1 C CS1 + C π 2+ 2 C µ 1 Q2 C CS2 + C µ 2 C π 1+ 2 C µ 1 Figure 11. 11 Frequency Response practical cases. v.X j = .XY (11. A.XY CXY 2CXY : This result stands in contrast to that expressed by (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. to arrive at a more general solution.1 C1 = 2C1 .cls v. 2007 at 13:42 578 (1) 578 Chap.134) CX = 1 .gm1 =gm2 . The MOS cascode is shown in Fig.Y j = 1 (11.136) gm2 CCS1 + C2 + 2C1 j!p. a frequency typically much higher than the signal bandwidth. . we use the actual value. 11. Even for comparable values of C2 and CCS 1 + 2C1 .out j = R C 1 + C : L CS 2 2 1 j!p.133) (11.1. tor capacitances. Note that the effect of C1 at Associating one pole with each node gives Y is also equal to 1 .X j = R jjr C + 2C S 1 1 1 1 j!p. For this reason. suggesting that the cascode transistor breaks the trade-off between the gain and the input capacitance due to Miller effect. Illustrated in Fig. Av.

1 g RS CGS1 + 1 + m1 CGD1 gm2 m2 m1 (11.out j = R C 1 + C : L DB 2 GD2 .138) j!p.

140) .Y j = 1 g CDB1 + CGS2 + 1 + g CGD1 + CSB2 (11. 1 gm2 j!p.139) (11.

we write from Eqs.18.50 MOS cascode including transistor capacitances. Assume CDB = CSB . The circuit contains the following poles: Example 11.cls v. CGS2 and CDB1 + 1 + gm2=gm1 CGD1 are Example 11. the input pole has risen considerably. Exercise Repeat the above example if the width of Assume gm2 = 100 . and compare the results with those of Example 11.25 The CS stage studied in Example 11. Compared with the exact values derived in that example.X j = .Y is still in the range of fT =2 if comparable. (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and (11. In the cascode shown in Fig. estimate the poles.139). the cascode bandwidth (442 MHz) is nearly twice as large.51 plots the frequency response of the cascode stage.7 Frequency Response of Cascode Stage VDD RL Vout Vb V in C GS1 + C GD1 (1+ RS g m1 g m2 X Y M1 C GS2 + C GD1 (1+ g m2 ) + C DB1 + C SB2 g m1 M2 C GD2 + C DB2 579 ) Figure 11. 11. Estimate the poles of the circuit. thus lowering the corresponding pole (11.26 Solution Y .18. plot the frequency response. allowing M1 to carry a larger current than M2 .142) (11.143) Note that the pole at node Y is quite lower than fT =2 in this particular example. M2 and hence all of its capacitances are doubled.out j = 2 442 MHz: (11. Solution Using the values given in Example 11.140): j!p. Figure 11.X j = 2 1:95 GHz j!p. assuming = 0.1 .144) j!p.Y j = 2 1:73 GHz j!p. Transistor M3 contributes CGD3 and CDB 3 to node magnitude. We note that !p.18. 2007 at 13:42 579 (1) Sec. Compared with the Miller approximation results obtained in Example 11. Assuming the two transistors are identical. transistor M3 serves as a constant current source.141) (11.18 is converted to a cascode topology.138) (11. 11. 2006] June 30.52.

1 gm1 RS CGS1 + 1 + CGD1 gm2 .

51 VDD V b2 M3 V b1 RS X RL Vout M2 Y M1 V in Figure 11.out j = R C 1 + C : L DB 2 GD2 . j!p.52 . 2007 at 13:42 580 (1) 580 Chap. 11 Frequency Response 30 Magnitude of Frequency Response (dB) 20 10 0 −10 −20 −30 6 10 10 7 10 Frequency (Hz) 8 10 9 10 10 Figure 11. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

distinct attributes of this circuit: (1) the ability to provide a high output impedance and .Y j = 1 m2 g CDB1 + CGS2 + 1 + g CGD1 + CGD3 + CDB3 m2 m1 (11. From our studies of the cascode topology in Chapter 9 and in this chapter.146) Note that !p. g1 j!p. we identify two important.18 for M1 -M3 . M3 lowers ID2 and hence Exercise Calculate the pole frequencies in the above example using the transistor parameters given in Example 11.145) (11.X also reduces in magnitude because the addition of gm2 .

The output impedance is equal to (11. we have .7. Both of these properties are exploited extensively. Similarly. 11. 1 1 where Zin does not include RS . 11. for the MOS stage shown in Fig.49. From Fig. 2 CS 2 Zin = 1 g CGS1 + 1 + gm1 CGD1 s (11. 11.148) where the Early effect is neglected.1 Input and Output Impedances The foregoing analysis of the cascode stage readily provides estimates for the I/O impedances.147) Zout = RL jj C +1C s .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.8 Frequency Response of Differential Pairs 581 hence serve as a good current source and/or high-gain ampliﬁer. 11. the input impedance of the bipolar cascode is given by Zin = r1 jj C +12C s . 2007 at 13:42 581 (1) Sec.cls v. (2) the reduction of Miller effect and hence better high-frequency performance. 2006] June 30.50.

54(a)].149) m2 Zout = R C + C . thus reducing the circuit to those studied above.27 A differential pair employs cascode devices to lower the Miller effect [Fig. This calculation is beyond the scope of this book. 11.70): Vout s = CXY s .53(a) depicts two bipolar and MOS differential pairs along with their capacitances. The transfer function is therefore given by (11. the input and output impedances (from each node to ground) are equal to those in (11.54(b). Figure 11.X j = . we utilize the results obtained in Section 11. 11. L GD2 DB 2 (11. Example 11. Solution Employing the half circuit shown in Fig. Estimate the poles of the circuit. the half circuits can be constructed as shown in Fig.151) where the same notation is used for various parameters.53(b). the output resistance of the transistors must be taken into account. 11. VThev as2 + bs + 1 (11.150) where it is assumed = 0 If RL is large. For small differential inputs. Similarly. 11. 1 (11.8 Frequency Response of Differential Pairs The half-circuit concept introduced in Chapter 10 can also be applied to the high-frequency model of differential pairs.7: j!p.91) and (11.92). gm RL . respectively.

1 gm1 RS CGS1 + 1 + CGD1 gm3 (11.152) .

53 (a) Bipolar and MOS differential pairs including transistor capacitances. (b) half circuits.cls v. VDD RD M3 Vb V in1 RS M1 M2 I SS (a) VDD RD Vout Vb M3 Y M1 g m1 g m3 ) RD Vout M4 RS Vin2 V in C GS1 + C GD1 (1+ RS C GD3 + C DB3 X C GS3 + C GD1 (1+ (b) g m3 ) + C DB1 + C SB3 g m1 Figure 11.54 j!p. 11 Frequency Response VDD RC C CS2 C µ2 RS C π1 V in2 V in1 RS C GS1 C SB1 RD C DB1 C GD1 RD C DB2 C GD2 RS V in2 M1 M2 I SS C GS2 C SB2 VCC RC C µ1 V in1 RS C π2 Q1 Vout1 C CS1 V in1 RS C GS1 M1 RD C GD1 VDD C DB1 C SB1 (b) Figure 11. 2007 at 13:42 582 (1) 582 VCC RC C CS1 C µ1 V in1 RS C π2 Q1 Q2 I EE (a) Chap.out j = R C 1+ C : L DB 3 GD3 1. 2006] June 30.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.

154) Exercise .153) (11.Y j = 1 g CDB1 + CGS3 + 1 + gm3 CGD1 g m3 m1 (11. j!p.

appears between node P and ground.56 depicts the transistor capacitances that constitute CSS .186): R 1 = Rgm RDs+SS CSS + + 1 : (11.8. 11.18 Assume p the width and hence the capacitances of M3 are twice those of M1 . The CM gain indeed rises dramatically at high frequencies—by a factor of 2gm RSS (why?).8 Frequency Response of Differential Pairs 583 Calculate the pole frequencies using the transistor parameters given in Example 11. j!p j = C SS (11.158) and the Bode approximation plotted in Fig. where a ﬁnite capacitance VDD RD V out1 M1 V CM I EE P M2 R D + ∆R D Vout2 CM Gain g m ∆R D ∆RD 2 R SS + 1 gm 2 gm C SS R SS C SS 1 R SS C SS ω (a) (b) Figure 11.55(b). we expect the total impedance between P and ground to fall at high frequencies.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. At high frequencies. M3 is typically a wide device so that it can operate with a small VDS . Let us consider the MOS differential pair shown in Fig.cls v. 2gm RSS 1. 11.156) 2gmRSS SS CSS Since RSS is typically quite large. capacitances may raise the CM gain (and lower the differential gain). Figure 11. 11. Also. Since CSS shunts RSS . (10. gm3 = 2gm1 .55(a). we can simply replace RSS with RSS jj 1=CSS s in Eq. leading toa higher CM gain. thus degrading the common-mode rejection ratio. (b) CM frequency response. For example. thereby adding large capacitances to node P . 2007 at 13:42 583 (1) Sec.1 Common-Mode Frequency Response The CM response studied in Chapter 10 included no transistor capacitances.155) j!z j = R 1C SS SS 2gm . In fact. 2006] June 30. .157) (11. 11. This section can be skipped in a ﬁrst reading.55 (a) Differential pair with parasitic capacitance at the tail node. yielding the following zero and pole frequencies: RD Vout = 1 + 2R jj 1 VCM SS C s g m SS (11.

Determine the low-frequency cut-off of the circuit.1 and r1 = 1:49 k . For Q2 .57(a) incorporates capacitive coupling both at the input VCC = 2. Solution We must ﬁrst compute the operating point and small-signal parameters of the circuit. 800 mV.9 Additional Examples Example 11. = 100.161) . IC 1 = VCCR VBE1 B1 = 1:7 mA: It follows that VBE 1 = VT lnIC 1 =IS 1 = 748 mV and IC 1 14:9 . 11 Frequency Response M1 P M2 C SB1 Vb C GD3 C SB3 M3 C SB2 Figure 11.28 The ampliﬁer shown in Fig. and express the base current of Q1 as VCC . 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.5 V 100 k Ω R B1 R C X 1 kΩ 200 nF R B2 50 k Ω C1 V in 200 nF Q1 C2 R in2 (a) Y 1 kΩ Q2 Vout RE Q1 I1 RC C2 VY R in2 V Thev RC C2 VY R in2 (b) (c) Figure 11. 2007 at 13:42 584 (1) 584 Chap. e. gm1 = VCC = IB2 RB2 + VBE2 + RE IC 2 .57 . 2006] June 30. and VA = 1.. From Chapter 5. (11. we begin with an estimate of for VBE 1 .160) = 1:75 mA. Thus.56 Transistor capacitance contributions to the tail node. we have (11. VBE 1 =RB 1 and hence .cls v.16 A.159) (11.g. and between the two stages. Assume IS = 5 10. 11.

Example 11. To compute the cut-off frequency. Let us now consider the ﬁrst stage by itself.168) Since !L2 !L1.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.e.164) (11. we construct the simpliﬁed interface shown in Fig. Exercise Repeat the above example if RE = 500 . Rin2 = RB 2 jj r2 + + 1RE . gm2 = 22:2 . the low-frequency cut-off of this stage is equal to 1 !L1 = r jjR C 1 B 1 1 = 2 542 Hz: (11. C2 s obtaining a pole at (11. 2006] June 30.58(a) is an example of ampliﬁers realized in integrated circuits.9 Additional Examples 585 and.I1 RC . Capacitor C1 forms a high-pass ﬁlter along with the input resistance of the circuit. 11.167) (11. 2007 at 13:42 585 (1) Sec.18. Iteration yields IC 2 = 1:17 mA. the gain drops by 3 dB at !L1 .163) where it is assumed VBE 2 800 mV. V V IC 2 = RCC=. Fig. In this case.165) The second coupling capacitor also creates a high-pass response along with the input resistance of the second stage. +BE2 R = 1:13 mA. thus attenuating low frequencies. Thus. therefore.1 and r2 = 2:22 k .57(c). Assuming M1 and M2 are identical and have the same parameters as those given in Example 11. 11. where VThev = .57(b) and determine VY =I1 . i.. it is simpler to replace I1 and RC with a Thevenin equivalent. Solution . 11.cls v.162) (11. Since Rin1 = r2 jjRB1 . we conclude that !L1 “dominates” the low-frequency response. plot the frequency response of the ampliﬁer.166) !L2 = R + 1 C C Rin2 2 = 22:9 Hz: (11. with moderate values for C1 and C2 . B2 E (11.29 The circuit of Fig. 11. Rin1 . It consists of a degenerated stage and a self-biased stage. We now have Rin2 VY VThev s = RC + 1 + Rin2 .

obtaining Rin2 = 1:30 k . Since RF RD2 . the reader can show that R Rin2 = 1 . (11. and write Av2 = gm2 RL2 8:7 = 5:98. But we continue without this iteration for simplicity.1 8:7 k . Using an analysis similar to that in the previous example.cls v.gm2RD2 = . 11 Frequency Response ac GND VDD R D1 V in RS 200 Ω 1 kΩ C2 10 pF X R D2 RF 10 k Ω 1 kΩ R D1 v in RS 200 Ω 1 kΩ Vout M2 X R D2 RF 10 k Ω 1 kΩ v out M2 M1 R S1 C1 M1 R in2 ac GND (b) 50 pF 200 Ω (a) R D1 C GD1 V in RS C GS1 M1 R D2 RF X C GD2 R D1 R in2 Vout V in RS C GS1 M1 C DB1 + C GS2 + (1− A v2 ) C GD2 C GD1 VX C DB1 M2 C GS2 C DB2 (c) (d) Figure 11.173) 19 With this estimate of the gain. A v2 (11. we have Av2 .172) (11. This resistance can be calculated with the aid of Miller’s theorem: where Av2 denotes the voltage gain from X to the output. .58 .6:67.171) !L2 = R +1R C D1 in2 2 = 2 6:92 MHz: jj .169) (11. 2007 at 13:42 586 (1) 586 Chap. we note that C1 contributes a low-frequency cut-off at 1 1 !L1 = gmRRSC + 1 S1 1 = 2 42:4 MHz: (11. From Eq.19.55) and Fig. we can express the Miller effect of R at the output as R =1 A. (11. Rin2 . Low-Frequency Behavior We begin with the low-frequency region and ﬁrst consider the role of C1 . 2006] June 30. F . .28(c). F F v2 place this resistance in parallel with RL2 .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11.170) A second low-frequency cut-off is contributed by C2 and the input resistance of the second stage.

vX = .58(d). We thus arrive at the simpliﬁed topology shown in Fig.20 The overall midband gain is therefore roughly equal to 25. The two poles can be calculated from Eqs. j!p1 j = 2 308 MHz j!p2 j = 2 2:15 GHz: (11.178) (11. allowing the circuit to be reduced to that in Fig. then the circuit must be solved using a complete small-signal equivalent.4. 11. The zero is given by gm1 =CGD1 = 2 13:3 GHz. The Miller effect of CGD2 at the output is expressed as 1 .58(c).3:77: (11.g R jjR (11. Also. This is primarily due to the use of Miller approximation for RF . 11. 2006] June 30. High-Frequency Behavior To study the response of the ampliﬁer at high frequencies. but how about the effect of RF and CGD2 ? We apply Miller’s approximation to both components so as to convert them to grounded elements.71). C1 and C2 act as a short circuit and the transistor capacitances play a negligible role.1. That is. We note that vout =vin = vX =vin vout =vX and recognize that the drain of M1 sees two resistances to ac ground: RD1 and Rin2 .9 Additional Examples 587 Since !L1 remains well above !L2 . The Miller multiplication of CGD2 is given by 1 . Adding CDB 2 to this value yields the v2 output pole as j!p3 j = R 1:15C 1 + C L2 GD2 DB 2 = 2 1:21 GHz: (11.70). . around 20% lower than the calculated result.175) The voltage gain from node X to the output is approximately equal to . 11. and (11.59 plots the overall response.gm2 RD2 because RF RD2 .3-dB cut-off ( 40 MHz) to the upper . At midband frequencies.58(b). How do we compute VX =Vin in the presence of the loading of the second stage? The two capacitances CDB 1 and CGS 2 are in parallel.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. the “useful” bandwidth can be deﬁned from the lower . 2007 at 13:42 587 (1) Sec.3 GHz.174) m1 D1 in2 vin = . The ﬁrst stage can now be drawn as illustrated in Fig.1 CGD2 1:15CGD2 = 92 fF. 20 If not. Figure 11. we insert the transistor capacitances. Av2 CGD2 = 614 fF. 11. the cut-off is dominated by the former. The midband gain is about 26 dB 20. where the overall transfer function is given by Vout =Vin = VX =Vin Vout =VX .177) The second stage contributes a pole at its output node.cls v. noting that CSB 1 and CSB 2 play no role because the source terminals of M1 and M2 are at ac ground.179) We observe that !p1 dominates the high-frequency response. (11. we compute the midband gain.72): Midband Behavior In the next step. A.176) (11. lending itself to the CS analysis performed in Section 11.3-dB cut-off ( 300 MHz) and is almost one decade wide. The Miller effect of RF was calculated above to be equivalent to Rin2 = 1:3 k . The gain falls to unity at about 2. (11.

A capacitance tied between the input and output of an inverting ampliﬁer appears at the input with a factor equal to one minus the gain of the ampliﬁer. the frequeny response may also exhibit rolloff as the frequency falls to very low values.cls v. capacitances exhibit a lower impedance. The frequency response of a circuit corresponds to the latter test. Bipolar and MOS transistors contain capacitances between their terminals and from some terminals to ac ground. reducing the gain. Miller’s approximation indicates an input pole that embodies Miller multiplication of the basecollector or gate-drain capacitance. Bode’s rules approximate the frequency response if the poles and zeros are known. When solving a circuit. 2007 at 13:42 588 (1) 588 Chap.g. by applying a step) or in the frequency domain (e.. these capacitances must be identiﬁed and the resulting circuit simpliﬁed. calculate the pole frequency as the inverse of the product of the capacitance and resistance seen between the node and ac ground. we must derive the transfer function of the circuit. 2006] June 30. In many circuits.g. it is possible to associate a pole with each node.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. The CE and CS stages exhibit a second-order transfer function and hence two poles. i. To obtain the frequency response.e.. As the frequency of operation increases. The magnitude of the transfer function indicates how the gain varies with frequency. Miller’s theorem allows a ﬂoating impedance to be decomposed into to grounded impedances. by applying a sinusoid).10 Chapter Summary The speed of circuits is limited by various capacitances that the transistors and other components contribute to each node. The gain thus rolls off at high signal frequencies. . This is called Miller effect. 11 Frequency Response 30 Magnitude of Frequency Response (dB) 20 10 0 −10 −20 −30 6 10 10 7 10 Frequency (Hz) 8 10 9 10 10 Figure 11..59 11. The speed can be studied in the time domain (e. Owing to coupling or degeneration capacitors.

The CB and CG stages do not suffer from Miller effect and achieve a higher speed than CE/CS stages. 11. 7. !p = 0. What is the gain of the circuit at arbitrarily low frequencies? .61. the “dominant-pole approximation” can be made to ﬁnd a simple expression for each pole frequency. In the circuit of Fig. The differential frequency response of differential pairs is similar to that of CE/CS stages. 5. equal) poles at !p1 . Emitter and source followers provide a wide bandwidth. RD = 1 k RD and VDD CL = 1 pF.e.62. i. Neglecting channel-length Vout V in M1 CL Figure 11. a cascode stage can be used. Their output impedance.cls v. Assume VA = 1 but 0. Determine the . 6.60 modulation and other capacitances.10 Chapter Summary 589 If the two poles of a circuit are far from each other. 2007 at 13:42 589 (1) Sec.. In the ampliﬁer of Fig. Problems 1. determine the frequency at which the gain falls by 10 ( 1 dB). Construct the Bode plot of jVout =Vin j. To beneﬁt from the higher input impedance of CE/CS stages but reduce the Miller effect. Neglect other capacitances. 2006] June 30. 11. A circuit contains two coincident (i. 11.62. we wish to achieve a . however. What is the maximum (low-frequency) gain that can be achieved with a power dissipation of 2 mW? Assume VCC = 2:5 V and neglect the Early effect and other capacitances.60. Construct the Bode plot of jVout =Vin j for the stages depicted in Fig.3-dB bandwidth of 1 GHz with a load VCC R1 Vout V in Q1 CL Figure 11.. causing instability in some cases.3-dB bandwidth of the circuits shown in Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. but their lower input impedance limits their applicability. An ampliﬁer exhibits two poles at 100 MHz and 10 GHz and a zero at 1 GHz. can be inductive.61 3. 4. Construct the Bode plot of jVout =Vin j. 11. Construct the Bode plot of jVout =Vin j. An ideal integrator contains a pole at the origin.e. 11. capacitance of 2 pF. 2.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.67.cls v. Consider only the load capacitance.66. 11 Frequency Response VCC Q2 Vout V in Q1 CL RB V in VCC Q2 Vout Q1 CL V in Vb VDD M2 Vout M1 CL V in VDD M1 Vout M2 CL (a) Figure 11. (11. i. Repeat Problem 12 for the circuit shown in Fig.63 illustrates a cascade of two identical CS stages. Derive the transfer function assuming 0 but VDD Vout V in M1 CL Figure 11.e. 11. 13. In Problem 9. !z = 0. 2006] June 30. An ideal differentiator provides a zero at the origin. 2007 at 13:42 590 (1) 590 Chap. Apply Miller’s theorem to resistor RF in Fig. a parasitic resistance Rp has appeared in series with the source of M1 in Fig. 11. Explain why the circuit operates as an ideal integrator if ! 0. 11. What is the gain of the circuit at arbitrarily high frequencies? 9. 16. Consider the circuit shown in Fig. 11. Note that Vout =Vin = VX =Vin Vout =VX .64.68 and estimate the voltage gain of the .3-dB bandwidth of the circuit.63 ulation and other capacitances. derive the transfer function of the circuit. Neglecting channel-length modVDD RD X M1 CL RD Vout M2 CL V in Figure 11.. 11. 11.8) for a CS stage.65. Due to a manufacturing error. Repeat Problem 12 for the CS stage depicted in Fig. substitute s = j! . 15. Derive a relationship for the ﬁgure of merit deﬁned by Eq. neglecting other capacitances.62 (b) (c) (d) 8. 14. and obtain an expression for jVout =Vin j. Construct the Bode plot of jVout =Vin j. Figure 11. 10. Assuming = 0 and neglecting other capacitances.64 12. Determine the . determine the input and output poles of the circuit. construct the Bode plot of jVout =Vin j.

Assume rO is large enough to allow the approximation vout =vX = gm RC . Assume VA = 1 and neglect other capacitances. 2006] June 30.67 17.cls v.72.10 Chapter Summary VDD RD Vout Vb RS RP C in CL 591 V in Figure 11.66 VDD RD RS M1 C in RP CL Vout V in Figure 11. explain how the common-base stage illustrated in Fig.73 provides a negative input capacitance.gmRC . Consider the common-base stage illustrated in Fig. estimate the input capacitance of the circuit depicted in Fig. 11. Repeat Problem 19 for the source follower shown in Fig. 11. .70. Using Miller’s theorem. Assume 0 but neglect other capacitances. What happens if ! 0? 20.71. 19. 11. circuit. Using Miller’s theorem.69. 21.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11. 11. Repeat Problem 16 for the source follower in Fig. 18. 2007 at 13:42 591 (1) Sec.65 VDD RD Vout RP RS C in Vb CL V in Figure 11. Assume VA = 1 and RF is large enough to allow the approximation vout =vX = . enough to allow the approximation vout =vX = RL =RL + gm1 . Utilize Miller’s theorem to estimate the gain. Assume = 0 and RF is large . 11. where the output resistance of Q1 is drawn explicitly.

Repeat the derivation without this approximation. 26.68 V in RS VDD X M1 RF Vout RL Figure 11.76. identify all of the transistor capacitances and determine which ones are in parallel and which ones are grounded on both ends.74. we neglected C and CGD . Repeat Problem 22 for the circuit in Fig. 11. .77.75.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 11.49) for the fT of transistors. 11.cls v. 25. For the MOS circuits shown in Fig. 2006] June 30. For the bipolar circuits depicted in Fig. Use Miller’s theorem to estimate the input and output poles of the circuit shown in Fig.71 22. 23. 11. In arriving at Eq. identify all of the transistor capacitances and determine which ones are in parallel and which ones are grounded on both ends.70 VDD CF M1 C in Figure 11. Assume VA = 1 and neglect other capacitances. 24. (11. 11 Frequency Response Vout Figure 11.69 VCC RC Vout rO V in RB X Vb Q1 Figure 11. 2007 at 13:42 592 (1) 592 VCC RC RF V in RB X Q1 Chap.

cls v. (b) Sketch fT as a function of IC . Using Eq. 11.75 27. 2006] June 30. derive an expression for the fT of bipolar transistors in terms of the collector bias current. then Cb = gm F . . 2007 at 13:42 593 (1) Sec. It can be shown that CGS 2=3WLCox for a MOSFET operating in saturation. 28.73 VCC CF V in RB Q1 RC Vout Figure 11.72 VCC RC C1 Vb Q1 C in Figure 11. (a) Writing C = Cb + Cje . It can be shown that.49).10 Chapter Summary VDD M1 CF C in 593 Figure 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. and using Eq.74 VCC RC RB Q1 Vout CF Q2 V in Figure 11. if the minority carriers injected by the emitter into the base take F seconds to cross the base region. assuming that Cje is independent of the bias current. (11.

VTH . VTH : L2 (11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. Using Eq. plot the fT of a MOSFET (a) as a function of W for a constant VGS .49).76 VDD VDD Vb M2 Vout V in M1 Vb M1 V in VDD M2 Vout M1 RS (a) (b) (c) RE V in M2 Vout V b1 Figure 11. we double the device length. 32. a student attempts a different substitution for gm : 2ID =VGS . Assume L remains constant in both cases. Assume L remains constant in both cases. VTH for a constant W . plot the fT of a MOSFET (a) as a function of VGS . Having solved Problem 28 successfully. (b) as a function of ID for a constant W . VTH .181) 30. (11. 29. VTH . (b) as a function of ID for a constant VGS . arriving at 2ID 1 2fT = 3 WLC V .49) and the results of Problems 28 and 29. 2006] June 30. (11. (11.49) and the results of Problems 28 and 29.181). This result suggests that fT decreases as the overdrive voltage increases! Explain this apparent discrepancy between Eqs. (b) as a function of VGS . 11 Frequency Response VCC VCC Q2 Vout V in Q1 CL RB V in VCC Q2 Vout Q1 CL V in V b1 I1 Vout Q1 Q3 VCC V b3 Q2 (a) (b) (c) Figure 11. 33. V : 2 ox GS TH (11.180) and (11. In order to lower channel-length modulation in a MOSFET. 31. Assume L remains constant in both cases. (11.77 (11. Using Eq. prove that 3 2fT = 2 n VGS . VTH for a constant ID .49) and the results of Problems 28 and 29.cls v. (a) How should the device width be adjusted to maintain the same overdrive voltage and the same drain current? (b) How do these changes affect the fT of the transistor? .180) Note that fT increases with the overdrive voltage. Using Eq. plot the fT of a MOSFET (a) as a function of W for a constant ID . 2007 at 13:42 594 (1) 594 Chap.

79 38. and (b) the transfer function given by Eq. CDB = 15 fF. 41.79. 11. VTH = 200 mV. Assuming 0 and using Miller’s theorem.29(a). Determine the poles of the circuit using (a) Miller’s approximation. 2007 at 13:42 595 (1) Sec. RD = 1 k .29(a) while including the output impedance of the transistors. 11. CGD = 10 fF. 2006] June 30. Compare the results. 11. 11. Compare the results. determine the input and output poles of the CE and CS stages depicted in Fig. 40. (11.10 Chapter Summary 595 34.cls v. Consider the ampliﬁer shown in Fig. determine the input and output poles and hence the transfer function of the circuit. 11.81. and VGS .80. 36.80 39. Using Miller’s theorem. Determine the change in the fT if (a) ID is constant and W is increased. VCC Vb RS Q1 Q2 Vout V in Figure 11. Repeat Problem 40 but use the dominant-pole approximation.78 (at low frequencies). Assume L is constant. determine the input and output poles of the stages depicted in Fig. or (b) W is constant and ID is decreased. and (b) the transfer function expressed by Eq. In the CS stage of Fig. where VA = 1. Repeat Problem 36 for the stage shown in Fig. 37. Determine the poles of the circuit using (a) Miller’s approximation.70).BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.70). 11. 35. Assuming VA 1 and using Miller’s theorem. CGS = 50 fF. The common-emitter stage of Fig. RS = 200 . We wish to halve the overdrive voltage of a transistor so as to provide a greater voltage headroom in a circuit.78 employs a current-source load to achieve a high gain VCC V in RS Q1 Vout Figure 11. How do the results compare? . (11. ID1 = 1 mA. 11. VDD M2 RS M1 (a) VDD M2 Vout V in RS M1 (b) V in Vout RS VDD M2 Vout V in Vb (c) M1 Figure 11.

2006] June 30. Assume = 0 for M1 .83 without using Miller’s theorem.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 47. 11 Frequency Response V in RS Q1 Vout Figure 11.cls v. 11. 45. Determine the transfer function of the circuits shown in Fig.87.84 rem.85 without using Miller’s theorem. 46. Use Bode’s rule to plot jZin j as a function of frequency and explain why it exhibits inductive behavior. 43. Assume = 0.86. 11.” Neglecting other capacitances Z in R1 M1 C1 Figure 11. 11.82 and assuming = 0. Consider the source follower shown in Fig.82 is called an “active inductor. Calculate the input impedance of the stage illustrated in Fig. VCC Q1 Z in Z out Figure 11. 2007 at 13:42 596 (1) 596 VCC Chap.83 44. The circuit depicted in Fig. compute Zin . Assume 0.81 42.84 without using Miller’s theoVDD RS M2 Vout M1 V in Figure 11. 11. Assume VA = 1. 11. 11. where the current source is mistakenly . Compute the transfer function of the circuit shown in Fig. Determine the input and output impedances of the stage depicted in Fig.

89. Q3 serves as a constant current source.86 VDD M1 C in M2 Figure 11. 2007 at 13:42 597 (1) Sec. providing 75 of the bias current of Q1 . In the cascode of Fig. Assume VA = 1. Is Miller’s effect more or less signiﬁcant here than in the standard cascode topology of Fig.88.88 49.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.10 Chapter Summary VDD M2 Vout Z in M1 597 Figure 11. including C . Taking into account only CGS 1 . 2006] June 30. Determine the output impedance of the emitter follower depicted in Fig. determine the poles of the circuit. Assume 6= 0. Assuming VA = 1 and using Miller’s theorem.87 replaced with a diode-connected device. 48.48(a)? . 11. 11.85 VDD M2 Vout RS M1 Vb V in (a) VDD Vb M2 Vout RS M1 Vb V in (b) VDD Vout RS M1 Vb M2 V in (c) Figure 11. compute the input capacitance of the circuit. VCC Q1 V in RB Z out Figure 11.cls v. 11. 11. Sketch jZout j as a function of frequency.

We wish to design the CE stage of Fig. 11.63 for a total voltage gain of 20 and a .90.89 50. Assume each stage carries a 2 bias current of 1 mA.89.90 51.3-db bandwidth of 1 GHz. Due to manufacturing error. Using the results obtained in Problems 9 and 10. 53. 11. 2006] June 30. a student constructs the stage depicted in Fig. 11. VDD RD Vout Vb V in RS M1 RP M2 Figure 11. and n Cox = 100 A=V .cls v. Design Problems 52. 11. CL = 50 fF. Assuming = 0 and using Miller’s theorem. In analogy with the circuit of Fig.92 for an input pole at 500 MHz and an output pole VCC RC V in RB Q1 Vout Figure 11. determine the poles of the circuit. 2007 at 13:42 598 (1) 598 VCC V b2 Q3 V b1 V in RB RC Chap.91 compute the poles of the circuit. Assuming V 0 and using Miller’s theorem. 11.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.91 but mistakenly uses an NMOS device for M3 . 11 Frequency Response Vout Q2 Q1 Figure 11. = DD V b2 M3 V b1 V in RG RD Vout M2 M1 Figure 11. design the two-stage ampliﬁer of Fig.92 . a parasitic resistor Rp has appeared in the cascode stage of Fig.

where C0 = 0:2 fF=m denotes the gate-drain capacitance per unit width. RS = 50 . n Cox = 100 A=V2 .) 56.10 Chapter Summary 599 at 2 GHz. and CGS = 2=3WLCox. CCS = 10 fF. (Note that the input and output poles may affect the bandwidth.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.95 pole of 10 GHz. 2006] June 30. and using Miller’s theorem. = 0. We wish to design the MOS cascode of Fig. Determine the maximum allowable value of RC and hence the maximum achievable gain.95 for an input pole of 5 GHz and an output VDD RD Vout Vb V in RG M1 M2 Figure 11. Repeat Problem 53 with the additional assumption that the circuit must drive a load capacitance of 20 fF. 11. VA = 1. ID = 0:5 mA. and IC = 1 mA. Assume M1 and M2 are identical. C = 100 fF.cls v. We wish to design the common-base stage of Fig. 2007 at 13:42 599 (1) Sec. C = 5 fF. VCC RC Vout Vb V in RS Q1 Figure 11. C = 20 fF. Cox = 12 fF/m2 . 11. C = 20 fF. n Cox = 100 A=V .94 fF. determine the values of RB and RC such that the (low-frequency) voltage gain is maximized. Determine the maximum . C = 5 fF. CGD 0.8. what is the minimum tolerable value of RL ? 57. CSB 0. 2 If ID = 1 mA. Assuming IC = 1 mA. VA = 1. If C = 10 fF. An NMOS source follower must drive a load resistance of 100 with a voltage gain of 0.93 Assume IC = 1 mA. 11. and CCS = 20 fF. 54.94 must be designed for an input capacitance of less than 50 VCC V in Q1 Vout RL Figure 11. what is the minimum input capacitance that can be achieved? Assume = 0.93 for a . and CGD = C0 W . Cox = 12 fF/m2 . and L = 0:18 m. L = 0:18 m.3-dB bandwidth of 10 GHz. The emitter follower of Fig. 11. and VA = 1. 55. CGS = 2=3WLCox. 58. You may need to use iteration.

2 V. npn = 100.8 V RD RF V in 100 pF R 1 Vout M1 CL Figure 11. use the MOS device models given in the Appendix A. 59. and the voltage gain. and RD .pnp = 8 10.97 (a) Select the input dc level to obtain an output dc level of 1. 11. VDD = 1. W=L = 10 m=0:18 m for M1 -M4 . (b) Plot the frequency response and compute the low-frequency gain and the width. The circuit of Fig.) . IS. 11 Frequency Response allowable values of RG .3-dB bandwidth. 2006] June 30.96. Repeat Problem 58 if W2 = 4W1 so as to reduce the Miller multiplication of CGD1 . (b) Plot the frequency response and compute the low-frequency gain and the . 11. The self-biased stage depicted in Fig. 61.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.96 (a) Select the input dc level to obtain an output dc level of 0.npn = 5 10.cls v. SPICE models the effect of charge storage in the base by a parameter called F = Cb =gm . RF . VA. 1 kΩ 5 kΩ 1 kΩ . pnp = 50. RD . 62. Also. Repeat Problem 62 for the circuit shown in Fig. SPICE Problems In the following problems.9 V. (c) Repeat (a) and (b) for W = 20 m and compare the results. VDD = 1. 2007 at 13:42 600 (1) 600 Chap.16 A.5 V Vout V in Q1 Q2 Figure 11.98 must drive a load capacitance of 50 fF with a maximum gain-bandwidth product (= midband gain unity-gain bandwidth). Assuming R1 = 500 and L1 = 0:18 m.8 V M2 M3 V in M1 M4 Vout Figure 11. (Determine RF and RC . assume IS. determine W1 . For bipolar transistors.npn = 5 V. CGD1 . Assume F tf = 20 ps. Use Miller’s approximation for Assume an overdrive voltage of 200 mV for each transistor.16 A. 11. VA.99.pnp = 3:5 V.98 63. In the two-stage ampliﬁer shown in Fig. 60.97 must drive a load capacitance of 100 fF.3-dB band- VCC = 2. 11.

10 Chapter Summary VCC = 2. 2006] June 30.100 . 11.cls v. 11. Assuming M1 -M4 have a width of W and a length of 0. The two-stage ampliﬁer shown in Fig.99 64. VDD = 1. 2007 at 13:42 601 (1) Sec.8 V 1 kΩ 1 pF V in RF M2 M4 Vout M1 M3 Figure 11. determine RF and W .18 m.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.100 must achieve maximum gain-bandwidth product while driving CL = 50 fF.5 V RC Q1 V in 100 pF R 1 601 Q 1 1 mA RF Vout CL Figure 11.

2007 at 13:42 602 (1) 12 Feedback Feedback is an integral part of our lives. allowing precise realization of “functions. you may not succeed the ﬁrst time because you have broken a feedback loop that ordinarily “regulates” your motions. eventually becoming a menace on the road. This chapter deals with the fundamentals of (negative) feedback and its application to electronic circuits. dreading his parents’ reaction.1 General Considerations As soon as he reaches the age of 18. (1) The “feedforward” system:1 the main system. John gradually raises his speed so as to catch up with the rest of the drivers on the road.cls v. He then reasons that the speed limit is more of a “recommendation” and exceeding it by a small amount would not be harmful. John continues to observe the speed limit while noting that every other car on the highway drives faster. Try touching your ﬁngertips with your eyes closed. He pulls over to the shoulder of the road. 602 . mechanical. Without the police ofﬁcer’s involvement. John. an ampliﬁer targeting a precise gain of 2. Over the ensuing months. General Considerations Elements of Feedback Systems Loop Gain Properties of Negative Feedback Amplifiers and Sense/Return Methods Types of Amplifiers Amplifier Models Sense/Return Methods Polarity of Feedback Analysis of Feedback Circuits Four Types of Feedback Effect of Finite I/O Impedances Stability and Compensation Loop Instability Phase Margin Frequency Compensation 12. a negative feedback system consists of four essential components.00 is designed much more easily with feedback than without. listens to the sermon given by the police ofﬁcer. Upon his parents’ stern advice. John would probably continue to drive increasingly faster. The regulatory role of feedback manifests itself in biological.” For example. and. probably “wild” and poorly-controlled.1. buys a used car. receives a speeding ticket.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. only to see ﬂashing lights in his rear view mirror one day. John eagerly obtains his driver’s license. and electronic systems. John’s story exempliﬁes the “regulatory” or “corrective” role of negative feedback. The outline is shown below. the gas 1 Also called the “forward” system. drives home—now strictly adhering to the speed limit. 2006] June 30. Shown in Fig. and begins to drive. 12.

The feedback in Fig. XF . the error produced by the subtractor is equal to X . As seen throughout this chapter. (3) Feedback network: a network that generates a “feedback signal. let us determine the closed-loop transfer function Y=X . Note that the input port of the feedback network refers to that sensing the output of the forward system. revealing that negative feedback reduces the gain from A1 (for the open-loop system) to A1 =1 + KA1 . 12.” Why do we deliberately lower the gain of the circuit? As explained in Section 12.1 General feedback system..1 General Considerations Feedforward System 603 X Comparison Mechanism A1 Y Sense Mechanism XF K Feedback Network Input Port of Feedback Network Output Port of Feedback Network Figure 12. 12. Positive feedback.” XF . The quantity A1 =1 + KA1 is called the “closed-loop gain. 2006] June 30. 12. where the input is the amount of pressure that John applies to the gas pedal and the output is the speed of the car. If K = 0. As our ﬁrst step towards understanding the feedback system of Fig. and giving him a speeding ticket. If K 6= 0. ﬁnds application in circuits such as oscillators and digital latches. walking to John’s car. 2007 at 13:42 603 (1) Sec. i. no signal is fed back.1 is called “negative” because XF is subtracted from X . the beneﬁts accruing from negative feedback very well justify this reduction of the gain. which serves as the input of the forward system: X . The quantity K = XF =Y is called the “feedback factor. 12.” E = X . The network Solution . John makes this comparison himself. Example 12. The op amp A1 performs two functions: subtraction of X and XF and ampliﬁcation. then we obtain the “open-loop” system.2. Since XF = KY . analysis of a feedback system requires expressing the closed-loop parameters in terms of the open-loop parameters. (12. applying less pressure to the gas pedal—at least for a while. from the sensed output.cls v.e. (2) Output sense mechanism: a means of measuring the output. we say the system operates in the “closed-loop” mode. KY .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. KY A1 = Y: That is. and the car form the feedforward system.1 Analyze the noninverting ampliﬁer of Fig. The police ofﬁcer acts as the feedback network by reading the radar display.” (4) Comparison or return mechanism: a means of subtracting the feedback signal from the input to obtain the “error.1) Y A1 X = 1 + KA1 : (12.2) This equation plays a central role in our treatment of feedback.2 from a feedback point of view. The police ofﬁcer’s radar serves this purpose here. too.1. pedal.

12. 12.. i. XF X . 12 Feedback X A1 XF R1 R2 Y Figure 12.2. 2006] June 30.cls v. If KA1 Y=X approaches 1 + R1 =R2 as R2 =R1 + R2 A1 becomes almost identical to X . (12. X A1 Good Replica XF R1 R2 Figure 12. Example 12. (12. Thus. XF and (12.4) XF = KA1 E . 2007 at 13:42 604 (1) 604 Chap.3 Feedback signal as a good replica of the input. produced by the subtractor. the feedback signal becomes a close “replica” of the input (Fig. R1 + R2 which is identical to the result obtained in Chapter 8. Since E E = 1 +X .2) gives A1 Y X = 1 + R2 A1 . E . The .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. becomes much greater than unity.3).3) Exercise Perform the above analysis if R2 = 1. = X . It is instructive to compute the error.2 Explain why in the circuit of Fig. This observation leads to a great deal of insight into the operation of feedback systems.e. In other words.2 R1 and R2 also performs two functions: sensing the output voltage and providing a feedback factor of K = R2 =R1 + R2 . KA 1 suggesting that the difference between the feedback signal and the input diminishes as KA1 increases. XF Solution = R2 =R1 + R2 A1 is large.

as shown in Fig.2 The input of A1 is equal to .g. Let us set the input X to zero and “break” the loop at an arbitrary point. the quantity KA1 . with an input M and an output N .4 Computation of the loop gain by (a) breaking the loop and (b) applying a test signal. 2 We use voltage quantities in this example.” KA1 has an interesting interpretation.1 General Considerations 605 voltage divider therefore requires that Y R R2 R X 1+ 2 and hence (12. with the loop gain.1. which is equal to product of the gain of the forward system and the feedback factor. .1 Loop Gain In Fig.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.4(a). 12. let us apply a test signal at M and follow it through the feedback network. 2007 at 13:42 605 (1) Sec.cls v. hence the term “loop gain.8) In other words. e.3) yields the same result if R2 =R1 + R2 A1 Exercise Repeat the above example if R2 (12.” It is important not to confuse the closed-loop gain.6) 1. A1 =1 + KA1 .4(b). the subtractor. Now. if a signal “goes around the loop.KVtest A1 and hence (12.” it experiences a gain equal to . and the forward system to obtain the signal at N . Called the “loop gain. The resulting topology can be viewed as a system A1 N A1 VN K M K V test (b) (a) Figure 12. but other quantities work as well. VVN : test (12. as depicted in Fig.. 12. (12. 12.7) KA1 = . determines many properties of the overall system.1. KA1 .KVtest . 12.KA1 . 12.5) Y R1 X 1 + R2 : Of course. 2006] June 30. yielding VN = . = 1.

5 is the system with the test signal applied to the input of A1 . can we modify the topology of Fig. 12. the signal ﬂows from the input of A1 to its output and from the input of the feedback network to its output.8).3 Compute the loop gain of the feedback system of Fig.6? This would mean applying Vtest to the output of A1 and expecting to observe a signal at its X A1 V test K VN Figure 12.cls v. 12.2 Properties of Negative Feedback 12. input and eventually at N . the .1 Gain Desensitization Suppose A1 in Fig. yielding Solution VN = . For example. The reader may wonder if an ambiguity exists with respect to the direction of the signal ﬂow in the loop gain test.KA1 Vtest and hence the same result as in (12. Illustrated in Fig.2. N VN V test M A1 (12. 2006] June 30. The output of the feedback network is equal to KA1 Vtest . In the feedback system. For example. While possibly yielding a ﬁnite value.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 12. 12 Feedback Example 12.1 is an ampliﬁer whose gain is poorly controlled. 2007 at 13:42 606 (1) 606 Chap. 12. such a test does not represent the actual behavior of the circuit. 12. 12.1 by breaking the loop at the input of A1 . a CS stage provides a voltage gain of gm RD while both gm and RD vary with process and temperature.6 Incorrect method of applying test signal.9) Y K Figure 12.5 Exercise Compute the loop gain by breaking the loop at the input of the subtractor.4(b) as shown in Fig.

15) 3 Some analog-to-digital converters (ADCs) require very precise voltage gains.4) indicates that KA1 1 leads to a small error.4 The circuit of Fig. X K (12. we choose R1 = 3R2 and implement R1 as the series combination of three “unit” resistors equal to R2 .12) implies that R1 =R2 Solution = 3. (a) The actual gain is given by (12. for a closed-loop gain of 4. then Y X = 3:968: (12. so does each unit in R1 and hence the total value of R1 . forcing XF to be nearly equal to X and hence Y nearly equal to X=K .00. R1 R2 Figure 12. 2007 at 13:42 607 (1) Sec. Thus.7. Also. Example 12. 12. 2006] June 30. (12. 12.2) points to a potential solution: if KA1 1.14) Y = A1 X 1 + KA1 = 3:984: Note that the loop gain KA1 = 1000=4 = 250.00. For a nominal gain of 4.13) (12. As an example. (b)If A1 falls to 500. we have a quantity independent of A1 . Illustrated in Fig. (a) Determine the actual gain if A1 = 1000. (b) Determine the percentage change in the gain if A1 drops to 500. The circuit of Fig. For example. a 10-bit ADC may call for a gain of 2. still yielding a gain of 1 + 1:2R1 =1:2R2 = 4.2 exempliﬁes this concept very well.7 Construction of resistors for good matching. . if R2 increases by 20. From another perspective.000. 12.2 is designed for a nominal gain of 4.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.10) Y 1 XK (12. Eq. then A1 impacts Y=X negligibly and a high precision in the gain is attained. suppose we require a voltage gain of 4.3 How can we achieve such precision? Equation (12. (12. if K can be deﬁned precisely.12) Why is R1 =R2 more precisely deﬁned than gm RD is? If R1 and R2 are made of the same material and constructed identically. then the variation of their value with process and temperature does not affect their ratio. If A1 R2 =R1 + R2 1. 12. then Y 1. Eq.11) 2 1 + R1 : R (12.2 Properties of Negative Feedback 607 gain thus may vary by as much as 20. the idea is to ensure that R1 and R2 “track” each other.cls v.

on the other hand. but many other phenomena change the gain as well. KA1 . 12 Feedback Thus. This property of negative feedback is called “gain desensitization. the closed-loop gain changes by only 3:984=3:968=3:984 = 0:4 if A1 drops by factor of 2. The closed-loop transfer function is obtained by substituting (12. 2006] June 30. With negative feedback. negative feedback improves the linearity. makes the gain less sensitive to load variations. the large-signal analysis of differential pairs in Chapter 10 reveals that the smallsignal gain falls at large input amplitudes. That is.g. The gain desensitization property of negative feedback means that any factor that inﬂuences the open-loop gain has less effect on the closed-loop gain.2): s Y = 1 + !0 : X 1 + K A0 s 1+ ! 0 A0 (12. A1 may change.16) Here..17) .BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. we wish to determine the resulting bandwidth improvement. This concept was also extensively employed in the op amp circuits described in Chapter 8. A0 denotes the low-frequency gain and !0 the .2) that negative feedback lowers the low-frequency gain by a factor of 1 + KA1 . The signal amplitude affects A1 because the forward ampliﬁer suffers from nonlinearity. Noting from (12.” We now see why we are willing to accept a reduction in the gain by a factor of 1 + KA1 . e. We now study these properties in greater detail.2. Negative feedback. remains sufﬁciently higher than unity. As the signal frequency rises. however. 12. 2007 at 13:42 608 (1) 608 Chap. If the load resistance changes. we have blamed only process and temperature variations. but poorly-controlled gain and apply negative feedback around it so as to obtain a better-deﬁned. We begin with an ampliﬁer having a high.16) for A1 in (12. A1 may fall. Exercise Determine the percentage change in the gain if A1 falls to 200. but inevitably lower gain.cls v. Thus far.2 Bandwidth Extension Let us consider a one-pole open-loop ampliﬁer with a transfer function A1 s = A0 s : 1+ ! 0 (12. but A1 =1 + KA1 remains relatively constant. The above example reveals that the closed-loop gain of a feedback circuit becomes relatively independent of the open-loop gain so long as the loop gain. the variation of the open-loop gain due to nonlinearity manifests itself to a lesser extent in the closedloop characteristics.3-dB bandwidth. the gain of a CS stage depends on the load resistance. We therefore expect that negative feedback increases the bandwidth (at the cost of gain). For example.

18) (12. 12.2 Properties of Negative Feedback 609 Multiplying the numerator and the denominator by 1 + s=!0 gives A0 Y s = s X 1 + KA0 + ! 0 A0 1 + KA0 : = s 1 + 1 + KA ! 0 0 In analogy with (12.19) for A0 = 200. displaying a constant product.5 Plot the closed-loop frequency response given by (12. 12. Loop Bandwidth = 1 + KA0 !0 : (12. for K = 0:5.20) (12.19) Closed .1.21) In other words.6 Prove that the unity-gain bandwidth of the above system remains independent of 1 + KA0 1 and K 2 1. Example 12. we have 1 + KA0 = 21. noting that the gain decreases and the bandwidth increases by the same factor.16). 0. we conclude that the closed-loop system now exhibits: (12. Similarly.BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. K if .5.cls v.16). Assume For K = 0.8. The results are plotted in Fig. Loop Gain = 1 +A0 KA0 Closed . Solution A0 K=0 K = 0. the feedback vanishes and Y=X reduces to A1 s as given by (12. 2007 at 13:42 609 (1) Sec. K = 0.8 Exercise Repeat the above example for K = 1. For K = 0:1. and 0. the gain and bandwidth are scaled by the same factor but in opposite directions. 1 + KA0 = 101.5 ω Figure 12. yielding a proportional reduction in gain and increase in bandwidth. Example 12. 2006] June 30.1 K = 0.

BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi. 12 Feedback Solution The magnitude of (12. 2006] June 30. we write .19) is equal to Y X j! = s !2 1 + 1 + KA 2 !2 0 0 1 + KA0 A0 : (12.cls v. 2007 at 13:42 610 (1) 610 Chap.22) Equating this result to unity and squaring both sides.

Exercise 12. Example 12.3 Modiﬁcation of I/O Impedances As mentioned above.10 depicts a transistor-level realization of the feedback circuit shown in Fig. A0 2 =1+ 1 + KA0 2 !u 2 1 + KA02 !0 .25) (12. It follows that !u = !0 A2 .26) which is equal to the gain-bandwidth product of the open-loop system.7 Figure 12.9 If A0 = 1000. and K = 0:5. !0 = 2 10 MHz. We will formulate these effects carefully in the following sections.26) and compare the results.24) (12. Figure 12.9 depicts the results. A0 0 dB ω0 A 0 ω0 ω Figure 12.24)and (12. calculate the unity-gain bandwidth from Eqs. q q (12.2. This effect fundamentally arises from the modiﬁcation of the output impedance as a result of feedback.23) where !u denotes the unity-gain bandwidth. 12. (12.2. 1 + KA0 2 0 !0 A2 . (12. . K 2 A2 0 0 !0 A0 . but it is instructive to study an example at this point. Feedback modiﬁes the input impedance as well. negative feedback makes the closed-loop gain less sensitive to the load resistance.

28) RD can be neglected. We therefore simply solve the circuit.open = RD : (12..32) At this point.2 Properties of Negative Feedback 611 Assume = 0 and R1 + R2 RD for simplicity. The closed-loop vou