UG Diploma in Analog VLSI Design
Course: Mini Project Course Code: 10UGVL06 Nature of Project: Analog VLSI Layout Design Project Title: Design of a Static CMOS Tri-state Inverter Defined Specification: Minimum Achievable Delay
Device sizing details 4. Architecture analysis and comparisons 3. DRC and LVS report 10. Delay versus load estimate 7. Layout plan 9.Conclusion. Switching potential estimate 5. Theoretical estimated parameters 6. 11.References
. Introduction 2.Project By: Manasa S Upadhyaya
CONTENTS: 1. SPICE Simulations 8.
Finally the layout of the inverter is captured using standard cell layout technique along with DRC and LVS reports. bus drivers. The device sizing. INTRODUCTION:
A tri state logic comprises the usual true (0) and false (1) states. a large number of devices can communicate over the same channel simply by ensuring only one is enabled at a time. When a digital input is left disconnected (i. when it is given a high impedance signal). The symbol and truth table of a tri state inverter is as shown below:
. The mode of operation of tri state logic circuit is determined by the state of enable input. When the enable is ‘low’ the circuit is in the high impedance state. multiplexers. The tri-state inverter forms the basis for various types of clocked logic. latches. and I/O structures.ABSTRACT:
This project report comprises design of a static CMOS tri state inverter for minimum achievable delay.
1. the digital value interpreted by the input depends on the type of technology used.. TTL technology will reliably default to a "1" state. out of these the best architecture is chosen. When the enable input is ‘high’. driving 10 identical copies of it. On the other hand CMOS technology will temporarily hold the previous state seen on that input (due to the capacitance of the gate input). This is commonly used to connect banks of computer memory and other similar devices to a common data bus. 3 possible architectures for realising the inverter are discussed. with a third high impedance state (or 'off-state') which effectively disconnects the logic output. the device is enabled for normal logic operation. This provides an effective way to connect several logic outputs to a single input.e. allowing the remaining output to operate in the normal binary sense. switching potential estimation is carried out through hand calculations and verified through SPICE simulations. where all but one are put into the high impedance state. Variation of load versus delay is plotted.
A 0 1 0 1
Y Z Z 1 0
ARCHITECTURE ANALYSIS AND COMPARISONS:
Following are the architectures that can be used for realising a tri state inverter: Using Transmission gate: A transmission gate connected to the output of an inverter as shown in Fig2. the output will receive same noise. The disadvantages of the above topology can be avoided by putting a transmission gate inside the inverter.e.En Symbol: Y En Truth table: En/ En 0/1 0/1 1/0 1/0
2. even when gate is disabled in the tri state mode. This topology contributes to dynamic power each time that the input and output (Y’) are switched.1 provides tri state capability. i. It is also a non restoring circuit.1 Circuit topologies:
. if the input is a noisy or degraded signal. The possibilities fig are as follows: 2. but also consumes unnecessary power.
the charges from the internal nodes disturbs the floating output node. Load: 10 copies.
DEVICE SIZING :
Specification: To size the device for minimum achievable delay. This effect may switch the next gate driven by this gate. Due to this. When the output is tri-stated.3. Nomenclature: Subscripts: p – PMOS
. For the circuit of fig2.2.fig2. but the effect of charge sharing comes into picture for the circuit of fig2.2
In general. Method used: RC Delay model. Hence it can cause erroneous output of the circuit. the voltage level of the floating output node will not remain same as its previous value. Hence this circuit topology is best suited for realising a simple tri-state inverter. if the input A toggles.
3. the two topologies shown above are logically equivalent. the effect of charge sharing is not seen in its tri-state condition as the output node Y is completely disconnected from the input and internal nodes.
n – NMOS d – Drain terminal of MOSFET s – Source terminal of MOSFET g – Gate terminal of MOSFET b – Body/Substrate of MOSFET Parameters: Vdd – Supply terminal Vss – Ground terminal R–Drain to Source resistance C – Gate Capacitance µ – mobility of electrons (n) /holes (p) W – Width of MOSFET L – Chanel length Tpdr – Rise time of output Y Tpdf – Fall time of output Y Tpd – Propagation delay time
Since TSMC 180nm technology is used for design of the inverter. Let Wn and Wp be the widths of NMOS and PMOS of the inverter as shown fig3. Lp = Ln = 180nm. so channel length. Consider a unit inverter which has been designed minimum propagation delay.1.
9. The design calculations are carried out by considering En (En) as high (low). 6. The resistance of a transistor:
R∝ 1μ * W ⇒ RpRn= μnμp*2*Wn2*Wp=μnμp*WnWp. The gate capacitance:
Cg∝W*L⟹ Cg-pCg-n= 2*Wp2*Wn=WpWn ∵ Lp=Ln
Now for the tri-state inverter.
Cgs1=Cdb1=Csb2=Cg-n Cgs4=Cdb4=Csb3=Cg-p Cdb4=12*Cg-n Cdb3=12*Cg-p
.3. 8. The same holds good for the PMOSs’ as well. Considering Cdb=Cgs=Csb=Cg for contacted diffusion and Cdb=Cgs=Csb≅Cg/2 for uncontacted shared diffusion. So the transistors M2 and M3 are on.
Let the mobility ratio be μ=μnμp.2. From fig3. let the width of NMOS be 2 times that of unit inverter so that the effective resistance of the 2 NMOSs’ together is equal to that of the unit inverter. as shown in fig3. 7.
A = 1(high). A = 0 (low). Determination
of Fall time (Tpdf): For the output Y to fall from Vdd (high) to Vss (low).5). Which implies that. For the output Y to rise from Vss
(low) to Vdd (high). we get
Tpdf=Rn*Cg-n+Rn*Cpar+Cload= n+Cpar+Cload Tpdf=Rn*Cg-n*(232+212*WpWn) Rn*Cg-
. Determination of Rise time (Tpdr): 11. the rise time is determined. it has to be connected to Vss. it must be connected to Vdd. Using the equivalent second order RC network as shown in fig3.3
The parasitic capacitance is given by:
Since the inverter capacitance is given by:
itself.Propagation delay: The average propagation delay is given by. Hence both NMOSs’ must be on. i.
On substituting equations of step 9 in above equation.
fig3. both PMOSs’ must be turned on.
Cload=Cout=10*Cin=10*Cg-n*(1+WpWn) 10.. The fall time is again determined by equivalent RC network (fig3.The effective input capacitance is given by: Cin=Cgs1+Cgs4=Cg-n+Cg-p=Cg-n*(1+WpWn) (From step 2) fig3 . i.4.
the MOSFETs are operating in saturation region. At the switching point. To find minimum value of Tpd. And the trans conductance parameter. differentiating equation with respect to w and equating to zero. β(=μ*Cox*WL)of the single N MOS is given by βn1+βn2=βn2.Tpd=12*(Tpdr+Tpdf) ⟹Tpd=12*Rn*Cg-n*(212*μnμp*WnWp+232+212*WpWn)
To determine Wn and Wp for defined specification: Let w=WpWn. first consider the NMOSs’.
SWITCHING POTENTIAL ESTIMATE:
The switching point of an inverter is a point on its voltage transfer characteristic at which the input voltage is equal to the output voltage. The 2 NMOSs’ of equal sizes connected in series can be approximated to be a single NMOS with channel length equal to sum of the individual lengths. it is configured as a simple inverter.
dTpddw=0 ⟹12*Rn*Cg-n*212*μnμp+212*-1w2=0 ⟹w2=μnμp ⟹WpWn=μnμp
1. To do this. This potential is termed as the switching potential. Ln1+Ln2=2*Ln .
. hence the drain current of NMOS and PMOS must be equal. Similarly the equal sized PMOSs’ can be approximated as a single PMOS of channel length 2*Lp and β=βp2 . To determine the switching potential of the tri-state inverter.
0 87.07 – 0.0 406. we get
Where.18 microns TRANSISTO NP-CHANNEL UNITS R CHANNEL PARAMETE RS Vth K' (µ*Cox/2) Low-field Mobility (µ) 0.
THEORETICAL ESTIMATED PARAMETERS:
The parameters of the MOSFETs are taken from the measurements of MOSIS test structures obtained by MOSIS. choosing Wn of the unit inverter as 0.∴ βn22*Vsp-Vthn2=βp22*Vdd-Vsp-Vthp2. the devices sizes are:
. Vsp – Switching potential Vthn – Threshold voltage of NMOS Vthp – Threshold voltage of PMOS Vdd – Supply voltage On solving the above equation for Vsp . therefore for the tri-state inverter.50 171.86 volts µA/V^2 cm^2/V *s
From the above derived equations and details.5µm. VENDOR: TSMC TECHNOLOGY: SCN018 FEATURE SIZE: 0.
Transistor NMOS PMOS
Channel Width 1.8289V.18=888. Hence the value of ‘h’ varies from 1 to 10.1620.00µm 2.82
Switching potential. The logical effort of the gate is given by g=Cin-gateCin-inv where Cin-gate input capacitance of the gate and Cin-inv input capacitance of an inverter delivering the same output current as that of the gate. we have the normalised delay of the gate as
Where p –normalised parasitic delay of the gate under zero load.18=1900 βp=2*(μ0*Cox2*WL)p=2*37*2.18µm
Switching potential value:
βn=2*(μ0*Cox2*WL)n=2*171*10.821900)=0.821900*1. f – Stage effort. f=g*h. where g – logical effort and h – fanout of the gate.
Cin-inv=Cg-n*(1+μ) Cin-gate=2*Cg-n*(1+μ) ⟹g=2
The fanout of the tri-state inverter is equal to number of identical copies drawn by the gate. Hence d=g*h+p.18µm 0. The parasitic delay of the gate is given by p=Cpar-gateCin-inv. where Cpar-gate – parasitic capacitance at the output node of the gate and Cin-inv – capacitance at the input node of the unit inverter.162µm
Channel Length 0.49+0.
. Hence for the tri-state inverter. Consider a unit transistor designed to achieve minimum delay.
DELAY VERSUS LOAD ESTIMATE:
From the linear delay model.
Hence the normalised delay. Wn=2*0.p=2.
Tool used: LT SPICE IV Schematic:
1. Consider En/En =1/0. Analysis: transient analysis is carried out to determine the propagation delay.
d=2*h+2. Choosing Wn for inverter as 0.
4. To verify the device size.5µm.
. therefore for the tri-state inverter.
132µm.132 µm.Propagation delay v/s width of the PMOS transistors:
From the transient analysis. Keeping Wn = 1 µm and Wp = 2. Consider En/En =1/0. we get minimum delay at Wp = 2. 2.
. To determine the switching potential. Analysis: dc sweep to determine the switching potential.
. To plot the average propagation delay-versus load.
The gate is made to drive 0 to 10 copies of it and the corresponding delay values are plotted. Vsp = 0.From the dc sweep analysis.833V 3.
1. Stick diagram:
Tool used: The Electric VLSI Design System.
DRC AND LVS REPORT:
Layout v/s Schematic (Network Consistency Checking (NCC) in the tool):
REFERENCES: Neil H. Prentice Hall.The tri-state inverter with a simple architecture has been analysed and designed to achieve the defined specification. 4.Edition. Third edition. David Haris. 1. In the load versus delay plots. Pearson Education. while determining the theoretical values. ‘Digital Integrated Circuits’. This is so because.E Weste. The theoretically estimated values are approximately equal to the simulated values. John P Uyemura. approximate RC delay models have been used. ‘Introduction to VLSI CIRCUITS AND SYSTEMS’.
4. the delay at zero load is not same as estimated but for higher loads the 2 plots match. Ayan Banerjee-‘CMOS VLSI Design A Circuit and systems Perspective’. Rabeay.com
.mosis. 3. 2nd.