# THIRUMALAI ENGINEERING COLLEGE

**DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING KILAMBI , KANCHIPURAM 631551
**

LAB MANUAL

CLASS SEMESTER ACADEMIC YEAR

**: II YEAR EEE : IV SEMESTER : 2011 – 2012
**

1

SUBJECT CODE SUBJECT CIRCUITS LAB

: 131452 : LINEAR AND DIGITAL INTEGRATED

AND GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408 :

CIRCUIT DIAGRAM:

2

Expt. No.1 Date: AIM:

STUDY OF BASIC DIGITAL ICS

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 As required Range Quantity 1 1 1 1 1 1

THEORY: a. AND gate: 3

An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of ‘1’ only if all the input signals are ‘1’. b. OR gate: An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of ‘1’ if any of the input signal is ‘1’. c. NOT gate: A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input. TRUTH TABLE: S.N o 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1

OR GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7432 : 4

d. NAND gate: A NAND gate is a complemented AND gate. The output of the NAND gate will be ‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’. e. NOR gate: A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’. f. EX-OR gate: An Ex-OR gate performs the following Boolean function,

A

B = ( A . B’ ) + ( A’ . B )

It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal ‘0’ when the two input signals are equal either ‘0’ or ‘1’. PROCEDURE: 1. Connections are given as per the circuit diagram 5

1. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 2. Apply the inputs and verify the truth table for all gates.

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.N o 1. 2. 3. 4.

INPUT A 0 0 1 1 B 0 1 0 1

OUTPUT Y=A+B 0 1 1 1

6

NOT GATE

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7404 :

CIRCUIT DIAGRAM:

TRUTH TABLE: INPUT OUTPUT

7

S.N o 1. 2. NAND GATE LOGIC DIAGRAM:

A 0 1

Y = A’ 1 0

PIN DIAGRAM OF IC 7400 :

CIRCUIT DIARAM:

TRUTH TABLE: INPUT OUTPUT 8

S.N o 1. 2. 3. 4.

A 0 0 1 1

B 0 1 0 1

Y = (A . B)’ 1 1 1 0

NOR GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7402 :

CIRCUIT DIAGRAM:

9

TRUTH TABLE: S.N o 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A + B)’ 1 0 0 0

EX-OR GATE LOGIC DIAGRAM

PIN DIAGRAM OF IC 7486 :

10

CIRCUIT DIAGRAM:

TRUTH TABLE: S.N o 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A 0 1 1 0 B

11

RESULT:

The truth table of all the basic digital ICs were verified.

LOGIC SYMBOL: RS FF

CIRCUIT DIAGRAM: RS FF

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Ex.NO:1(b) Date: AIM:

STUDY OF FLIP FLOPS

To verify the characteristic table of RS, D, JK, and T Flip flops. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit NOR gate NOT gate AND gate ( three input ) NAND gate Connecting wires IC 7402 IC 7404 IC 7411 IC 7400 Range Quantity 1 1 1 1 1 As required

THEORY: A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states. RS FLIP FLOP: The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high 13

and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state. D FLIP FLOP: To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other.

CHARACTERISTIC TABLE: RS FF CLOCK PULSE 1 2 3 4 5 6 7 8 S 0 0 0 0 1 1 1 1 INPUT R 0 0 1 1 0 0 1 1 PRESENT STATE (Q) NC NC 0 1 0 1 X X NEXT STATE(Q+1) NC NC 0 0 1 1 X X UNDEFINED SET RESET NO CHANGE STATUS

LOGIC SYMBOL: D FF

CIRCUIT DIAGRAM: D FF

14

JK FLIP FLOP: The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided. T FLIP FLOP: This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop.

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CHARACTERISTIC TABLE: D FF CLOCK PULSE 1 2 3 4 INPUT D 0 0 1 1 PRESENT STATE (Q) 0 1 0 1 NEXT STATE(Q+1) 0 0 1 1 STATUS

LOGIC SYMBOL: JK FF

CIRCUIT DIAGRAM: JK FF

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CHARACTERISTIC TABLE: JK FF

CLOCK PULSE 1 2 3 4 5 6 7 8 J 0 0 0 0 1 1 1 1

INPUT K 0 0 1 1 0 0 1 1

PRESENT STATE (Q) 0 1 0 1 0 1 0 1

NEXT STATE(Q+1) 0 1 0 0 1 1 1 0

STATUS

NO CHANGE

SET

RESET

TOGGLE

LOGIC SYMBOL: T FF

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CIRCUIT DIAGRAM: T FF

CHARACTERISTIC TABLE: T FF

CLOCK

INPUT

PRESENT

NEXT

STATUS 18

PULSE 1 2 3 4

T 0 0 1 1

STATE (Q) 0 1 0 1

STATE(Q+1) 0 0 1 0 TOGGLE

PROCEDURE:

1. Connections are given as per the circuit diagrams.

**2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
**

3. Apply the inputs and observe the status of all the flip flops.

19

RESULT: The Characteristic tables of RS, D, JK, T flip flops were verified.

CIRCUIT DIAGRAM:

20

Expt. No.2 Date: AIM:

IMPLEMENTATION OF BOOLEAN FUNCTIONS

To design the logic circuit and verify the truth table of the given Boolean expression, F (A,B,C,D) = Σ (0,1,2,5,8,9,10) APPARATUS REQUIRED: S.No 1. 2. 3. 4. Name of the Apparatus AND gate OR gate NOT gate NAND gate IC 7408 IC 7432 IC 7404 IC 7400 Range Quantity

21

5. 6. 7.

NOR gate EX-OR gate Connecting wires

IC 7402 IC 7486 As required

DESIGN: Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10) The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a simplified expression for the output. From the K-Map, F = B’ C’ + D’ B’ + A’ C’ D Since we are using only two input logic gates the above expression can be re-written as, F = C’ (B’ + A’ D) + D’ B’ Now the logic circuit for the above equation can be drawn.

TRUTH TABLE: INPUT A 0 0 0 0 0 0 0 B 0 0 0 0 1 1 1 C 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 OUTPUT F=D’B’+C’(B’+ A’D) 1 1 1 0 0 1 0 22

S.N o 1. 2. 3. 4. 5. 6. 7.

8. 9. 10. 11. 12. 13. 14. 15. 16.

0 1 1 1 1 1 1 1 1

1 0 0 0 0 1 1 1 1

1 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 1

0 1 1 1 0 0 0 0 0

PROCEDURE: 1. Connections are given as per the circuit diagram 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the given Boolean expression.

23

RESULT: The truth table of the given Boolean expression was verified.

HALF ADDER TRUTH TABLE: S.N o 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 OUTPUT C 0 0 0 1

DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A B

Carry, C = A . B 24

CIRCUIT DIAGRAM:

Expt. No. 3(a) ADDER Date: AIM:

IMPLEMENTATION OF HALF ADDER & FULL

To design and verify the truth table of the Half Adder & Full Adder circuits. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. Name of the Apparatus AND gate OR gate NOT gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7486 As required Range Quantity

THEORY: The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely, 0 + 0 = 0 ; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 102 25

The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. HALF ADDER: A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. FULL ADDER: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.

FULL ADDER TRUTH TABLE: S.N o 1. 2. 3. 4. 5. 6. 7. 8. INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, 26

SUM = A’B’C + A’BC’ + AB’C’ + ABC CARRY = A’BC + AB’C + ABC’ +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, SUM

SUM = A’B’C + A’BC’ + AB’C’ + ABC = A CARRY

B

C

CARRY = AB + AC + BC CIRCUIT DIAGRAM:

27

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

RESULT: The design of the half adder and full adder circuits was done and their truth tables were verified.

HALF SUBTRACTOR TRUTH TABLE: S.N o 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT DIFF 0 1 1 0 BORR 0 1 0 0

28

DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF = A Borrow, BORR = A’ . B CIRCUIT DIAGRAM: B

Expt. No. 3(b)

IMPLEMENTATION OF HALF SUBTRACTOR & FULL

SUBTRACTOR Date:

AIM: To design and verify the truth table of the Half Subtractor & Full Subtractor circuits. APPARATUS REQUIRED: S.No 1. 2. 3. Name of the Apparatus AND gate OR gate NOT gate IC 7408 IC 7432 IC 7404 29 Range Quantity

4. 5.

EX-OR gate Connecting wires

IC 7486 As required

THEORY: The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely, 0 - 0 = 0; 0 - 1 = 1 with 1 borrow; 1 - 0 = 1; 1-1=0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed. HALF SUBTRACTOR: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.

FULL SUBTRACTOR TRUTH TABLE: S.N o 1. 2. 3. 4. 5. INPUT A 0 0 0 0 1 B 0 0 1 1 0 C 0 1 0 1 0 OUTPUT DIFF 0 1 1 0 1 BORR 0 1 1 1 0 30

6. 7. 8.

1 1 1

0 1 1

1 0 1

0 0 1

0 0 1

DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABC Borrow, BORR = A’BC + AB’C + ABC’ +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, DIFFERENCE

DIFF = A’B’C + A’BC’ + AB’C’ + ABC = A BORROW

B

C

BORR = A’B + A’C + BC CIRCUIT DIAGRAM:

31

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.

RESULT: The design of the half subtractor and full subtractor circuits was done and their truth tables were verified. CIRCUIT DIAGRAM: ODD PARITY GENERATOR

ODD PARITY GENERATOR 32

TRUTH TABLE (ODD PARITY GENERATOR):

INPUT S.N o ( Three bit message)

OUTPUT ( Odd Parity bit)

A 1 2 3 4 5 6 7 8 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

P 1 0 0 1 0 1 1 0

Ex. No. 4 Date: AIM:

PARITY GENERATOR & CHECKER

To design and verify the truth table of a three bit Odd Parity generator and checker. APPARATUS REQUIRED: S.No 1. 2. 3. 4. Name of the Apparatus Digital IC trainer kit EX-OR gate NOT gate Connecting wires IC 7486 IC 7404 As required 33 Range Quantity 1

THEORY: A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity the added parity bit will make the total number of 1’s an even amount and in odd parity the added parity bit will make the total number of 1’s an odd amount. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission. Since the information was transmitted with odd parity the four bits received must have an odd number of 1’s. An error occurs during the transmission if the four bits received have an even number of 1’s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1’s. From the truth table the expression for the output parity bit is, P( A, B, C) = Σ (0, 3, 5, 6) Also written as P = A’B’C’ + A’BC + AB’C + ABC’ = (A B C)

CIRCUIT DIAGRAM: ODD PARITY CHECKER

34

TRUTH TABLE (ODD PARITY CHECKER):

INPUT S.N o A 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 0 0 0 0 0 0 0 0 1 1 1 1 1 ( four bit message Received ) B 0 0 0 0 1 1 1 1 0 0 0 0 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 P 0 1 0 1 0 1 0 1 0 1 0 1 0

OUTPUT (Parity error check) X 1 0 0 1 0 1 1 0 0 1 1 0 1 35

14. 15. 16.

1 1 1

1 1 1

0 1 1

1 0 1

0 0 1

From the truth table the expression for the output parity checker bit is, X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15) The above expression is reduced as,

This X = (A

B

C

P)

PROCEDURE:

1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the Parity generator and checker.

RESULT:

The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified. TRUTH TABLE: | output B3 B2 Binary input | B1 B0 G3 | G2 G1 Gray code G0

0

0

0

0

0

0

0

0 36

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

Ex. No. 4 Date: AIM:

DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

To design and implement 4-bit (i) (ii) Binary to gray code converter Gray to binary code converter

37

APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. COMPONENT X-OR GATE AND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7486 IC 7408 IC 7432 IC 7404 QTY. 1 1 1 1 1 35

THEORY: The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable.

38

G3 = B3

39

LOGIC DIAGRAM :

A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has been used to implement partially each of three outputs.

40

TRUTH TABLE: | | G3 G2 G1 G0 B3 B2 B1 B0 Gray Code | Binary Code

0 0 0 0 0 0 0 0 1

0 0 0 0 1 1 1 1 1

0 0 1 1 1 1 0 0 0

0 1 1 0 0 1 1 0 0

0 0 0 0 0 0 0 0 1

0 0 0 0 1 1 1 1 0

0 0 1 1 0 0 1 1 0

0 1 0 1 0 1 0 1 0 41

1 1 1 1 1 1 1

1 1 1 0 0 0 0

0 1 1 1 1 0 0

1 1 0 0 1 1 0

1 1 1 1 1 1 1

0 0 0 1 1 1 1

0 1 1 0 0 1 1

1 0 1 0 1 0 1

K-map

B3 = G3

42

LOGIC DIAGRAM: GRAY CODE TO BINARY CONVERTOR

43

PROCEDURE: (i) Connections were given as per circuit diagram. 44

(ii) (iii)

Logical inputs were given as per truth table Observe the logical output and verify with the truth tables.

RESULT: The design of the Binary to Gray code converter & gray to binary code converter circuit was done and its truth table was verified.

CIRCUIT DIAGRAM:

45

TRUTH TABLE: For a serial data input of 1101, S.NO CLOCK PULSE 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 D1 1 1 0 1 X X X X INPUTS D2 X 1 1 0 1 X X X D3 X X 1 1 0 1 X X D4 X X X 1 1 0 1 X Q1 1 1 0 1 X 1 0 X OUTPUTS Q2 X 1 1 0 1 X X X Q3 X X 1 1 0 1 X X Q4 X X X 1 1 0 1 X

Ex. No. 5

IMPLEMENTATION OF SHIFT REGISTERS

Date:

46

AIM: To design and implement 4 bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable IC’s. APPARATUS REQUIRED: S.No 1. 2. 3. Name of the Apparatus Digital IC trainer kit D Flip Flop Connecting wires IC 7474 Range Quantity 1 2 As required

THEORY: A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next. The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register.

47

PIN DIAGRAM OF IC 7474:

48

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter

RESULT: The truth table of a serial in serial out left shift register was hence verified.

4 X 1 MULTIPLEXER LOGIC SYMBOL: 49

TRUTH TABLE (4 X 1 MULTIPLEXER): S.No 1. 2. 3. 4. SELECTION INPUT S1 0 0 1 1 S2 0 1 0 1 OUTPUT Y I0 I1 I2 I3

PIN DIAGRAM OF IC 7411:

Expt. No. 6 AIM:

MULTIPLEXER & DEMULTIPLEXER

Date:

50

To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. Name of the Apparatus Digital IC trainer kit OR gate NOT gate AND gate ( three input ) Connecting wires IC 7432 IC 7404 IC 7411 Range Quantity 1 1 1 1 As required

THEORY: Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is ‘many into one’ and it provides the digital equivalent of an analog selector switch. A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines.

CIRCUIT DIAGRAM: 51

1X4 DEMULTIPLEXER LOGIC SYMBOL:

52

TRUTH TABLE (1X4 DEMULTIPLEXER): INPUT S1 1. 2. 3. 4. 5. 6. 7. 8. 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 Din 0 1 0 1 0 1 0 1 Y0 0 1 0 0 0 0 0 0 OUTPUT Y1 0 0 0 1 0 0 0 0 Y2 0 0 0 0 0 1 0 0 Y3 0 0 0 0 0 0 0 1

S.No

CIRCUIT DIAGRAM:

53

PROCEDURE:

1. Connections are given as per the circuit diagrams. 54

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the multiplexer &Demultiplexer.

RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were verified.

PIN DIAGRAM:

55

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

Ex. No.7a Date:

STUDY OF NE555 TIMER IN ASTABLE MULTIVIBRATOR

56

AIM: To design an astable multivibrator circuit for the given specifications using 555 Timer IC. APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes 3 MHz 30 MHz 0 – 30 V IC 555 Range Quantity 1 1 1 1 1 As required As required As required

THEORY: An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave-generating circuit. This circuit does not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by, tc = 0.69 (R1 + R2) C Similarly the time during which the capacitor discharges from 2/3 V cc to 1/3 Vcc is equal to the time the output is low and is given by, td = 0.69 (R2) C Thus the total time period of the output waveform is, T = tc + td = 0.69 (R1 + 2 R2) C 57

**DESIGN: Given f= 4 KHz, Therefore, Total time period, T = 1/f = ____________ We know, duty cycle = tc/ T Therefore, tc
**

= ------------------------

and td = ____________ We also know for an astable multivibrator td = 0.69 (R2) C Therefore, R2 = _____________ tc = 0.69 (R1 + R2) C Therefore, R1 = _____________ OBSERVATIONS: Amplitude S.N o Waveforms ( No. of div x Volts per div ) Time period ( No. of div x Time per div )

tc

td

1.

Output Voltage , Vo

2.

Capacitor voltage , Vc

58

The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed in percentage. In equation form, % duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100

PROCEDURE: 1. 2. 3. 4. Connections are given as per the circuit diagram. + 5V supply is given to the + Vcc terminal of the timer IC. At pin 3 the output waveform is observed with the help of a CRO At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet.

RESULT: The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained.

PIN DIAGRAM: 59

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

Ex. No.7b STUDY OF NE555 TIMER IN MULTIVIBRATOR MONOSTABLE OPERATION Date: 60

AIM: Todesign a monostable multivibrator for the given specifications using 555 timer IC. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes Range 3 MHz, Analog 30 MHz 0 – 30 V IC 555 Quantity 1 1 1 1 1 As required As required As required

THEORY: A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an external trigger pulse is applied, the output is forced to go high (approx. Vcc). The time during which the output remains high is given by, tp = 1.1 R1 C At the end of the timing interval, the output automatically reverts back to its logic low state. The output stays low until a trigger pulse is applied again. Then the cycle repeats. Thus the monostable state has only one stable state hence the name monostable.

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DESIGN:

**[ To design a monostable multivibrator with tp = 0.616 ms , assume C = 0.01 µF ]
**

Given tp = 0.616 ms = 1.1 R1 C Therefore, R1 = _____________

OBSERVATIONS: Amplitude S.N o Observation ( No. of div x Volts per div ) Time period ( No. of div x Time per div )

ton

toff

1.

Trigger input

2.

Output Voltage , Vo

3.

Capacitor voltage , Vc

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PROCEDURE:

1. 2. 3. 4. 5.

Connections are given as per the circuit diagram. + 5V supply is given to the + Vcc terminal of the timer IC. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC At pin 3 the output waveform is observed with the help of a CRO At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet.

RESULT: The design of the Monostable multivibrator circuit was done and the input and output waveforms were obtained.

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

DESIGN: We know for an inverting Amplifier ACL = RF / R1 Assume R1 (approx. 10 KΩ) and find Rf Hence Vo(theoretical) = - ACL Vi

Ex. No.8a AIM

INVERTING AMPLIFIER

Date: 64

To design an Inverting Amplifier for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes 3 MHz 30 MHz 0 – 30 V IC 741 Range Quantity 1 1 1 1 1 As required As required

THEORY: The input signal Vi is applied to the inverting input terminal through R1 and the non-inverting input terminal of the op-amp is grounded. The output voltage Vo is fed back to the inverting input terminal through the Rf - R1 network, where Rf is the feedback resistor. The output voltage is given as, Vo = - ACL Vi Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal.

PRECAUTIONS: Output voltage will be saturated if it exceeds ± 15V.

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PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the OpAmp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

OBSERVATIONS: S.No. Amplitude ( No. of div x Volts per div ) Input Output Theoretical Practical Time period ( No. of div x Time per div )

RESULT: The design and testing of the inverting amplifier is done and the input and output waveforms were drawn

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PIN DIAGRAM:

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN: We know for a Non-inverting Amplifier ACL = 1 + (RF / R1) Assume R1 ( approx. 10 KΩ ) and find Rf Hence Vo = ACL Vi

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Ex. No.8b AIM:

NON - INVERTING AMPLIFIER

Date:

To design a Non-Inverting Amplifier for the given specifications using OpAmp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes 3 MHz 30 MHz (0 – 30) V IC 741 Range Quantity 1 1 1 1 1 As required As required

THEORY: The input signal Vi is applied to the non - inverting input terminal of the op-amp. This circuit amplifies the signal without inverting the input signal. It is also called negative feedback system since the output is feedback to the inverting input terminals. The differential voltage V d at the inverting input terminal of the op-amp is zero ideally and the output voltage is given as,Vo = ACL Vi . Here the output voltage is in phase with the input signal. PRECAUTIONS: Output voltage will be saturated if it exceeds ± 15V.

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PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the OpAmp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

OBSERVATIONS: S.No. Amplitude Time period

( No. of div x Volts per ( No. of div x Time per div ) div ) Input Output Theoretical Practical -

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RESULT: The design and testing of the Non-inverting amplifier is done and the input and output waveforms were drawn.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN: We know the frequency at which the gain is 0 dB, fb = 1 / (2π R1 Cf)

Therefore fb = _____ Since fb = 10 fa, and also the gain limiting frequency fa = 1 / (2π Rf Cf) We get, Rf = _______ and hence R1 = __________ 70

Expt. No.8a AIM:

INTEGRATOR

Date:

To design an Integrator circuit for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Capacitors Connecting wires and probes 3 MHz 30 MHz 0 – 30 V IC 741 Range Quantity 1 1 1 1 1 As required As required As required

THEORY: A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor R f is replaced by a capacitor Cf . The expression for the output voltage is given as, Vo = - (1/Rf C1) ∫ Vi dt Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of f a < fb . The input signal will be 71

integrated properly if the Time period T of the signal is larger than or equal to Rf Cf. That is, T ≥ Rf Cf The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits.

OBSERVATIONS: S.No. Amplitude ( No. of div x Volts per div ) Input Output Time period ( No. of div x Time per div )

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PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the OpAmp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

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RESULT: The design of the Integrator circuit was done and the input and output waveforms were obtained. PIN DIAGRAM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DESIGN: Given fa = --------------We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1) Let us assume C1 = 0.1 µF; then 74

Rf = _________ Since fb = 20 fa, fb = --------------We know that the gain limiting frequency fb = 1 / (2π R1 C1) Hence R1 = _________ Also since R1C1 = Rf Cf Expt. No.8b AIM: To design a Differentiator circuit for the given specifications using OpAmp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Capacitors Connecting wires and probes 3 MHz 30 MHz 0 – 30 V IC 741 Range Quantity 1 1 1 1 1 As required As required As required ; Cf = _________ DIFFERENTIATOR Date:

THEORY: The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1. The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt)

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Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps: 1. Select fa equal to the highest frequency of the input signal to be differentiated. Then, assuming a value of C1 < 1 µF, calculate the value of Rf. 2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf. The differentiator is most commonly used in waveshaping circuits to detect high frequency components in an input signal and also as a rate–of– change detector in FM modulators. OBSERVATIONS: Input - Sine wave S.No. Amplitude Time period

( No. of div x Volts per ( No. of div x Time per div ) div ) Input Output Input – Square wave S.No. Amplitude Time period

( No. of div x Volts per ( No. of div x Time per div ) div ) Input Output

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PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the OpAmp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

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RESULT: The design of the Differentiator circuit was done and the input and output waveforms were obtained.

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