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5

See 'TEXT' in 0MEMO or 1MEMO property in component


Dummy when 'USE EZ4'

Bolsena Block Diagram

Dummy when 'NO EZ4'

91.4C501.001 (04243)

Dummy when use '10/100'


Dummy when use 'GIGA'
D

200-PIN DDR SODIMM

CLK GEN
IDT CV1373

Dummy when use 'UMA'

AMD CPU

Dummy when use 'DIS'

Dummy when use 'IDE'

28

AGTL+ CPU I/F + UMA

PCI Express x16

11,12,13,14

1* Slot Cardbus
1* 1394
CardReader

ATI
M26/M24

RGB CRT

50,51,52

PCI-Express
x2

28
26,27

PCI

ACPI 2.0

1000Mb

30

6xUSB 2.0

TXFM

10/100Mb

30

16

24

USB x 4
24

CODEC
ALC655

MODEM
MDC Card

RJ11
CONN

30

24

Line In 33
MIC In

32

6-CH
AC97 2.2

PCI LAN
Realtek
RTL8110SBL
1000/100/10
RTL8100C
100/10
29

CRT

BlueTooth
miniUSB

AC97

TXFM

Power Block Diag -> Page 40

DVI-D
(EZ4 only ) 15

SB400

31

30

17

TMDS

VRAM x4

ATI

RJ45

LCD

CH7301C 15

(M26/M24 diff.) 53,54

PCI Bus / 33MHz

Mini-PCI
802.11a/b/g

TVOUT 16

RS480M

TI
PCI 7411

SM/MMC/SD
5 in 1

LVDS

ATI

PWR SW
TSP2220A

1394 4pin
Conn 28

SVIDEO/COMP

HyperTransport
6.4GB/S 16b/8b

Dummy when use ''M24'

4,5,6,7

Dummy when use ''M26'

PCMCIA
SLOT
PCMCIA I/F
Support
TypeII
28 MS/xD

DDR x2
8,9,10

17
LEDs
RTC BAT. 18
BUTTONs 35

Dummy when use 'SATA'

DDR 333/400

35W/25W

OP AMP
G1421

Line Out33
33

Int. SPKR33
B

LPC Bus / 33MHz

LPC I/F

HDD

DVD/
CD-RW

25

25

Thermal
& Fan
G792 23

NS SIO
PC87392

SIDE

SATA

18,19,20,21,22

PIDE

ATA 133

37

25

FIR

34

Touch
Pad
37

XBUS

KBC
KB3910

35

Int.
KB

ISA ROM

35

36

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Port Replicator 4 (124 PIN)


AC RJ45-11
IN

SEARIAL
PORT

CRT

PS2 MIC LINE IN LINE TV


OUT OUT

PRINTER

DVI

Title

PCIeX2 SMBUS

BLOCK DIAGRAM
Size
A3

Document Number

Rev
-1

Bolsena

Date: Tuesday, April 12, 2005

Sheet

1
1

of

58

PCI Routing
IDSEL
MiniPCI

21

LAN
7411

IRQ

REQ/GNT

23

22

E (CardBus)

7411

22

G (1394)

7411

22

E (FlashMedia)

Ref. function schematic


BOM
------------------------U81 cpu socket 62.10055.091 (DON'T CHANGE) (3mm high)
U80 north bridge 71.RS48M.00U 71.RS48M.B0U (ver A22)
U43 south bridge 71.SB400.B0U 71.SB400.D0U (ver A32)
U32 clock gen. 71.00137.A0W 71.00137.B0W
--U70 VGA M24
71.0M26P.00U 71.00M24.C0U
U64 VRAM FOR M24 72.55732.B0U 72.52832.E05
U65 VRAM FOR M24 72.55732.B0U 72.52832.E05
U69 VRAM FOR M24 72.55732.B0U 72.52832.E05
U71 VRAM FOR M24 72.55732.B0U 72.52832.E05
--U70 VGA M26
71.0M26P.00U (DON'T CHANGE)
U64 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
U65 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
U69 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
U71 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
--U66 BIOS SOCKET 72.39040.G03 62.10002.032 (NO NEED WHEN PD)
U66 BIOS IC
72.39040.G03 72.39040.H03 (DIP STAGE IN LAB, SMT IN PD)
--LOUT1 AUDIO
22.10257.001 22.10147.031 (NO SPDIF)
--U75 GIGA LAN 71.08110.00G 71.08110.A0G
U75 10/100 LAN 71.08110.00G 71.08100.C0G
--HDD1
20.80175.044 20.80592.044
SATA1
20.F0614.022 20.F0665.022
EZ4
20.80579.120 20.80591.120 (AFTER SB)

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CHANGE HISTORY
Size
A3

Document Number
Bolsena

Date: Thursday, March 31, 2005


5

Rev
-1
Sheet
1

of

58

3D3V_S0

C415
SC10U10V5ZY

C398
SCD1U16V

L12 2
1
0R0603-PAD

C418
SCD1U16V

SC 0308
C414
SC10U10V5ZY

3D3V_CLK_VDDA

1
C397
SCD1U16V

C423
SCD1U16V

1
C421
SCD1U16V

SC 0308

3D3V_CLK_VDD

L14 2
1
0R0603-PAD

3D3V_S0

RN56

C420
SCD1U16V

C417
SCD1U16V

C416
SCD1U16V

C419 3D3V_S0
SCD1U16V

3D3V_CLK_VDD
U32
3D3VDD48_S0

L13 2
1
0R0603-PAD

SC 0308

XI_CLK
2 C400
SC33P50V2JN

2
57 SMBC_SB_EZ4
57 SMBD_SB_EZ4

R278
DUMMY-R3

XO_CLK
2 C422
SC33P50V2JN

1
1

3
4

26 CLK48_CARDBUS
21 CLK48_USB

1
1

8,21 SMBC_SB
8,21 SMBD_SB

R261
R260

SC 0309

21 SB_OSC_CLK

32 CLK14_AUDIO

R279

R280

2
33R2

2
33R2

2 33R2
2
33R2

USB_48M
SMBC_CLK
SMBD_CLK

2
1

X2
X-14D318MHZ-1-U1
RN120

C399
SC2D2U16V5ZY

Dummy when 'NO EZ4'

SRN33-2-U2

3 SRN33-2-U2
4

SBLINK_CLK# 13
SBLINK_CLK 13

1
2

4 RN45
3
SRN33-2-U2

SBSRC_CLK# 18
SBSRC_CLK 18

4
3

CLK_PCIE_DOCK1# 57
CLK_PCIE_DOCK1 57

3D3V_CLK_VDDA

2
1

R264 2 22R2
R263 2 22R2

3
39
32

VDD_48
VDDA
VDD_SRC

21
14
35

VDD_SRC
VDD_SRC
VDD_SRC

56
51
43
48

VDD_REF
VDD_PC1
VDD_CPU
VDD_HTT

1
2

XIN
XOUT

4
7
8

USB_48
SCL
SDA

10
11

CLKREQ0#
CLKREQ1#

9
53
54

SEL24/24_48#
REF1
REF0

SRCC0
SRCT0
SRCC3
SRCT3
SRCC4
SRCT4
SRCC5
SRCT5
SRCC6
SRCT6
SRCC7
SRCT7

33
34
25
24
23
22
19
18
17
16
13
12

CPUC1
CPUT1
CPUC0
CPUT0

40
41
44
45

SRC_CLK0#
SRC_CLK0
SRC_CLK3#
SRC_CLK3
SRC_CLK4#
SRC_CLK4
SRC_CLK5#
SRC_CLK5

RN46

1
2

1
2

SRN33-2-U2
RN47
4
3

CLK_PCIE_DOCK2# 57
CLK_PCIE_DOCK2 57

SRN33-2-U2

Dummy when no EZ4

CPUCLKJ_CY
CPUCLK_CY

1 R296
1 R297

2 15R2J
2 15R2J

CPUCLK# 6
CPUCLK 6

RN55

SRCC1
SRCT1
SRCC2
SRCT2

29
30
28
27

VSS_SRC
VSS_SRC
RESET#
TURBO1

36
20
15
26

VSS_CPU
VSS_PCI
VSS_HTT
VSS_SRC
VSSA
VSS_48
VSS_REF

42
49
46
31
38
5
55

ATI_CLK0#
ATI_CLK0
ATI_CLK1#
ATI_CLK1

2
1

3
4

NBSRC_CLK# 13
NBSRC_CLK 13

SRN33-2-U2
RN44

SC 0309

13 CLK14_NB
37 CLK14_SIO
13 HTREF_CLK

1 R277

2
33R2

1 R274

2
33R2

R273 2
75R2F

FS2
FS1
FS0

CLK_REF2 52
CLK_HTT66 47
50

R272
475R2F

R298
100R2F

37

REF2
HTT66
PCI0
IREF

IREF_CLKGEN

NC#6

1
2

4
3

GFX_CLK# 49
GFX_CLK 49

CLK_PCIE_DOCK1#

1 R253

CLK_PCIE_DOCK1

1 R254

2
49D9R2F
2
49D9R2F
1 R255
2
49D9R2F
1 R256
2
49D9R2F

CLK_PCIE_DOCK2#

SRN33-2-U2

Dummy when use UMA

CLK_PCIE_DOCK2

Dummy when
no EZ4
R294

IDTCV137PAG
CHANGE TO 71.00137.B0W

SBLINK_CLK#

SBLINK_CLK

1 R295

SBSRC_CLK#

1 R251

SBSRC_CLK

1 R252

GFX_CLK#

1 R249

GFX_CLK

1 R250

SB 0219

2
49D9R2F
2
49D9R2F
2
49D9R2F
2
49D9R2F
2
49D9R2F
2
49D9R2F

Dummy when use UMA

NBSRC_CLK#

1 R292

NBSRC_CLK

1 R293

2
49D9R2F
2
49D9R2F

3D3V_CLK_VDD

DY

R281 2
2K2R2

1
1

R275 2
2K2R2

1
1
1

DY

FS1

2
DUMMY-R2
R276

1 R257
1

FS0

2
DUMMY-R2
R299

2
DY
2K2R2
2
DUMMY-R2
R258
for ICS

<Variant Name>

FS2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CLKGEN_IDTCV137
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

of

58

HTT for CPU sideB


Receive power
and NB sideA
Transmit power

HTT for CPU sideA


Transmit power
and NB sideA Receive
power
U81A

C246
SCD22U16V3ZY

C247
SCD22U16V3ZY

NB0CADOUT15
NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8
NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0

11 NB0CADOUT[15..0]
11 NB0CADOUTJ[15..0]

Used SideB Power Plane

1D2V_HT0B_S0

11
11
11
11

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0

1
1

R176 2 49D9R2F
R177 2 49D9R2F

11 NB0HTTCTLOUT
11 NB0HTTCTLOUTJ

T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28

VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B

AH29
AH27
AG28
AG26
AF29
AE28
AF25

LAYOUT: Place bypass cap on topside of board near


HTT power pins that are not connected directly to
HTT device, but connected internally to
other HTT power pins.

D29
D27
D25
C28
C26
B29
B27

1D2V_HT0B_S0

C245
SCD22U16V3ZY

1
C244
SCD22U16V3ZY

1D2V_S0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29

CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8
CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0

C242
downstream
SC4D7U10V5ZY

CPUCADOUT[15..0] 11
CPUCADOUTJ[15..0] 11

Used SideA Power Plane

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0

Y25
W25
Y27
Y28

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

J26
J27
J29
K29

CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
CPUHTTCLKOUT0
CPUHTTCLKOUTJ0

CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
CPUHTTCLKOUT0
CPUHTTCLKOUTJ0

CPUHTTCTLIN1
CPUHTTCTLINJ1
NB0HTTCTLOUT
NB0HTTCTLOUTJ

R27
R26
T29
R29

L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0

L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0

N25
P25
P28
P27

CPUHTTCTLOUT0
CPUHTTCTLOUTJ0

CPUHTTCTLOUT0 11
CPUHTTCTLOUTJ0 11

11
11
11
11

62.10055.091
SB 0127

ME : 60.10055.091
(3MM HEIGHT)
<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(1/4)_HyperTransport I/F
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

of

58

VREF_DDR_MEM
NOTE: Test with passive probes only.

1D25V_S3
U81B

VTT_SENSE

2D5V_S3
C441
SCD1U

AG12
1 R206
1 R205

VREF_DDR_MEM

2 34D8R2F
2 34D8R2F

MEMZN
MEMZP

D14
C14

MEMVREF1
MEMZN
MEMZP

VTT_A
VTT_A
VTT_A
VTT_A
VTT_B
VTT_B
VTT_B
VTT_B

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

R291
100R2F

VREF_DDR_CLAW

9 M_DATA[63..0]

LAYOUT: Locate close to DIMMs.

NOTE: Remove to bypass op-amp


3

VREF_DDR_CLAW
1
C309
SCD1U

VREF_DDR_CLAW

R198
100R2F

1
C311
SCD1U

R197
100R2F

2D5V_S3

C312
SC1000P50V2KX

LAYOUT: Locate close to CPU.

Place it near CPU

R203

1 R204

2
121R2F

M_CLK7
M_CLK#7

2
121R2F

M_CLK6
M_CLK#6
9 M_ADM[7..0]

R199

2
121R2F

M_CLK5
M_CLK#5

R200

2
121R2F

M_CLK4
M_CLK#4

9 M_DQS[7..0]

M_DATA63
M_DATA62
M_DATA61
M_DATA60
M_DATA59
M_DATA58
M_DATA57
M_DATA56
M_DATA55
M_DATA54
M_DATA53
M_DATA52
M_DATA51
M_DATA50
M_DATA49
M_DATA48
M_DATA47
M_DATA46
M_DATA45
M_DATA44
M_DATA43
M_DATA42
M_DATA41
M_DATA40
M_DATA39
M_DATA38
M_DATA37
M_DATA36
M_DATA35
M_DATA34
M_DATA33
M_DATA32
M_DATA31
M_DATA30
M_DATA29
M_DATA28
M_DATA27
M_DATA26
M_DATA25
M_DATA24
M_DATA23
M_DATA22
M_DATA21
M_DATA20
M_DATA19
M_DATA18
M_DATA17
M_DATA16
M_DATA15
M_DATA14
M_DATA13
M_DATA12
M_DATA11
M_DATA10
M_DATA9
M_DATA8
M_DATA7
M_DATA6
M_DATA5
M_DATA4
M_DATA3
M_DATA2
M_DATA1
M_DATA0

A16
B15
A12
B11
A17
A15
C13
A11
A10
B9
C7
A6
C11
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
AC1
AC3
W2
Y1
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16

MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

M_ADM8
M_ADM7
M_ADM6
M_ADM5
M_ADM4
M_ADM3
M_ADM2
M_ADM1
M_ADM0
M_DQS8
M_DQS7
M_DQS6
M_DQS5
M_DQS4
M_DQS3
M_DQS2
M_DQS1
M_DQS0

R1
A13
A7
C2
H1
AA1
AG1
AH7
AH13
T1
A14
A8
D1
J1
AB1
AJ2
AJ8
AJ13

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

C267
SC1000P50V2KX

For REGISTED DIMM Only


UNBUFFER DIMM NC

AG10

MEMRESET#
M_CKE#0
M_CKE#1

M_CKE#0 8,9
M_CKE#1 8,9

D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4

M_CLK7 8
M_CLK#7 8
M_CLK6 8
M_CLK#6 8
M_CLK5 8
M_CLK#5 8
M_CLK4 8
M_CLK#4 8

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

D8
C8
E8
E7
D6
E6
C4
E5

M_CS#7
M_CS#6
M_CS#5
M_CS#4
M_CS#3
M_CS#2
M_CS#1
M_CS#0

M_CS#3
M_CS#2
M_CS#1
M_CS#0

MEMRASA_L
MEMCASA_L
MEMWEA_L

H5
D4
G5

M_ARAS#
M_ACAS#
M_AWE#

M_ARAS# 8,9
M_ACAS# 8,9
M_AWE# 8,9

MEMBANKA1
MEMBANKA0

K3
H3

M_ABS#1
M_ABS#0

M_ABS#1 8,9
M_ABS#0 8,9

NC_E13
NC_C12
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

RSVD_M_AA15
RSVD_M_AA14
M_AA13
M_AA12
M_AA11
M_AA10
M_AA9
M_AA8
M_AA7
M_AA6
M_AA5
M_AA4
M_AA3
M_AA2
M_AA1
M_AA0

MEMRASB_L
MEMCASB_L
MEMWEB_L

H4
F5
F4

M_BRAS#
M_BCAS#
M_BWE#

M_BRAS# 8,9
M_BCAS# 8,9
M_BWE# 8,9

MEMBANKB1
MEMBANKB0

L5
J5

M_BBS#1
M_BBS#0

M_BBS#1 8,9
M_BBS#0 8,9

NC_E14
NC_D12
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

RSVD_M_BA15
RSVD_M_BA14
M_BA13
M_BA12
M_BA11
M_BA10
M_BA9
M_BA8
M_BA7
M_BA6
M_BA5
M_BA4
M_BA3
M_BA2
M_BA1
M_BA0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

N3
N1
U3
V1
N2
P1
U1
U2

MEMCKEA
MEMCKEB

1
2

1
1

C439
SC1000P50V2KX

C440
SCD1U

C266
SCD1U

AE8
AE7

MEMRESET_L

R290
100R2F

DDRVTT_SENSE AE13
4

TP47

TPAD30

NOTE: Install to bypass op-amp

2D5V_S3

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

2D5V_S3
RN36

M_CLK#1
M_CLK#0
M_CLK1
M_CLK0

M_CLK1
M_CLK#1
M_CLK0
M_CLK#0

8
7
6
5

1
2
3
4
SRN10K-2
3

8,9
8,9
8,9
8,9

M_AA[13..0] 8,9

AMD suggested M_AA13


connect to DIMM pin123

M_DQS8
M_ADM8

MEMRESET#
M_CS#7
M_CS#6
M_CS#5
M_CS#4
RSVD_M_AA15
RSVD_M_AA14
RSVD_M_BA15
RSVD_M_BA14

M_BA[13..0] 8,9

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

NOT SUPPORT ECC CHECK


AMD suggested remove
<Variant
Name>
PULL-HI
resistor.

CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0

TP60
TP90
TP59
TP83
TP89
TP88
TP84
TP85

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(2/4)_DDR
Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005


B

TP44
TP53
TP54
TP49
TP61
TP50
TP55
TP51
TP52

AMD suggested M_BA13


connect to DIMM pin123

Size
A3

TP86 TPAD30
TP87 TPAD30

Sheet
E

of

58

2D5V_CPUA_S0

DY

differentially impedance 100

2 C790
SC3900P50V3KX

2 C789
SC3900P50V3KX

3 CPUCLK#
820R3
820R3

1D25V_S3

R189
R190
R606

1
1
1

2 680R3F
2 680R3F
2 680R3F

2D5V_S0

AE12
AF12
AE11

VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE

CLKIN

AJ21
AH21

CLKIN_H
CLKIN_L

AJ23
AH23

NC_AJ23
NC_AH23

AE24
AF24

NC_AE24
NC_AF24

C16
AG15

VTT_A
VTT_B

SRN680-U

DY

DY

1 R207

C15

NC_C15

E20
E17
B21
A21

TMS
TCK
TRST_L
TDI

NC_C18

C18

NC_C18

NC_A19

A19

NC_A19

DY

2
680R3F

DY

CHANGE FROM 1KR3 TO 680R2 FOR AMD


CHECK LIST
NC_AG17
NC_AJ18
NC_D18

NC_B19
NC_C19
NC_D20
NC_C21

1
2
3
4

RN31 SRN680-U
8
7
6
5

1
2
3
4

Validation Test Points


LAYOUT: Place close to the CPU.

8
7
6
5
RN33

NC_C15
NC_AE23
NC_AF23
NC_AF22
NC_AF21

SRN680-U

TP56
TP42
TP39
TP41
TP40

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

VID4
VID3
VID2
VID1
VID0

VID4
VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

AG18
AH18
AG17
AJ18

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

41

TP37 TPAD30
TP36 TPAD30

LAYOUT: Route FBCLKOUT_H/L


differentially impedance 80

FBCLKOUT

FBCLKOUT_H
FBCLKOUT_L

FBCLKOUTJ

R191

NC_AE23
NC_AF23
NC_AF22
NC_AF21

C1
J3
R3
AA2
D3
AG2
B18
AH1
AE21
C20
AG4
C6
AG6
AE9
AG9

NC_C1
NC_J3
NC_R3
NC_AA2
NC_D3
NC_AG2
NC_B18
NC_AH1
NC_AE21
NC_C20
NC_AG4
NC_C6
NC_AG6
NC_AE9
NC_AG9

AE19

DBREQJ

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

D20
C21
D18
C19
B19

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

TDO

A22

TDO

NC_AF18

AF18

2
DUMMY-R3

2D5V_S3

Connect to VDDIO for AMD suggest.

KEY1
KEY0

AE23
AF23
AF22
AF21

R617
80D6R2F

AH19
AJ19

NC_D22
NC_C22

D22
C22

THERMTRIP#Level shift to SB400


2D5V_S0

8
7
6
5
1
2
3
4

SRN680-U
2D5V_S3

THERMDP 23
THERMDN 23
VID[4..0]

AG13
AF14
AG14
AF15
AE15

DBRDY

TMS
TCK
TRST_L
TDI

NC_AE23
NC_AF23
NC_AF22
NC_AF21
RN32

THERMTRIP#

R156
680R3F

A26
A27

DBREQ_L

NC_C15

1
R155
680R3F

DBREQJ
DBRDY
TCK
TMS
TDI
TRST_L
TDO

AH17

A28
AJ28

DY
1
2
3
4

C160
SCD1U

A20

THERMDA
THERMDC

CLKIN#
NC_AJ23
NC_AH23
NC_AE24
NC_AF24

R193 2
680R3F
R194 2
680R3F

1
2

DY

RN28

8
7
6
5

1
2

VDDIOFB
VDDIOFBJ
VDDIOSENSE

DBRDY

2D5V_S0

L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE

2D5V_S0
LDT_RST#
SB_CPUPWRGD
LDT_STP#

AF27
AE26
A23
A24
B23

R618
169R2F

2
2

RESET_L
PWROK
LDTSTOP_L

COREFB
COREFB#
CORE_SENSE

2D5V_S3

1 R616
1 R605

AF20
AE18
AJ27

THERMTRIP_L

NC_B13
NC_B7
NC_C3
NC_K1
NC_R2
NC_AA3
NC_F3
NC_C23
NC_AG7
NC_AE22
NC_C24
NC_A25
NC_C9

R192
680R3F

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

THERMTRIP#

3
Q10
MMBT3904-U1

CPU_THERMTRIP# 23

3 CPUCLK

SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031

VDDA1
VDDA2

AMD suggest voltege


from 2D5V_S0 to 2D5V_S3

41 COREFB
41 COREFB#

C212
SC1000P50V2KX

U81C

C241
SCD22U16V3ZY13,18 LDT_RST#
18 SB_CPUPWRGD
13,18 LDT_STP#

1
C211
SC1000P50V2KX

R2

DY

DY

L0_REF1
L0_REF0

KEMET,NT:5.7, B2 size
ST100U4VBM-1 (80.10716.321)
Iripple=1.1A,ESR=70mohm

R152
20KR2F
C734
SC1U10V3KX

Vout = 1.25*(1+ R1/R2)

C210
SC1U10V3KX

R1

DY

G913C-U

2 44D2R2F
2 44D2R2F
1

AMD SUGGEST TO USE 2D5V_CPUA_S0

AH25
AJ25

1 R153
1 R154

C243
SC3300P50V2KX

C240
SC4D7U10V5ZY
1D2V_HT0B_S0

TC3 SC 0308
ST100U4VBM-U

DY

LAYOUT: Route VDDA trace approx.


50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.

1 R175
2
0R0805-PAD

LAYOUT: Route trace 50 mils wide and


500 to 750 mils long between these
caps.

R174 2
0R3-U

2D5V_VDDA_S0

2D5V_CPUA_S0

Change
L270H

SET
OUT

DY

1
2

C239
SC10U10V5ZY

2D5V_CPUR_S0

1 R173
2
0R0603-PAD

SC 0308

SHDN#
GND
IN

2D5V_VDDA_VREF

1
2
3

U73

DY

R604
20KR2F
C733
SC22P50V2JN-1

Iomax=120mA

AMD SUGGEST TO USE 100 ~ 300UH

3D3V_S0

2D5V_S0

2D5V_VDDA_S0

2D5V_S0
NS3 1

R195 2
1KR2

SB 0201

LDT_RST#
CLKIN
CLKIN#
CORE_SENSE
VDDIOFB
VDDIOFBJ
VDDIOSENSE
NC_AE24
NC_AF24

TP38
TP34
TP35
TP43
TP46
TP45
TP48
TP27
TP26

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(3/4)_Control & Debug


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

of

58

U81E

U81D

SC10U10V5ZY

C793

SC10U10V5ZY

C817

1
2

SC10U10V5ZY

C272

C315
SC10U10V5ZY

C818
SCD22U16V3ZY

1
2

C318
SCD22U16V3ZY

1
C316

SCD22U16V3ZY

SCD22U16V3ZY

C791

SCD22U16V3ZY

C269

SCD22U16V3ZY

C271

LAYOUT: Place on backside of processor.

C816

C813

C794

C815

C814

C792

SCD22U16V3ZY
1

SCD22U16V3ZY
1

SCD22U16V3ZY
1

SCD22U16V3ZY
2

SC10U10V5ZY
2

SC10U10V5ZY

VCC_CORE_S0

10u x 2

0.22u x 4
DY

DY

DY

2D5V_S3

DY

4.7u x 6

1
2

SC4D7U10V5ZY

C366

C367
SC4D7U10V5ZY

C317
SC4D7U10V5ZY

1
2

SC4D7U10V5ZY

C365

C314
SC4D7U10V5ZY

SC10U10V5ZY

10u x 1

C313
SC4D7U10V5ZY

1
C320

4.7u x 2

SC4D7U10V5ZY

C265

SC4D7U10V5ZY

0.22u x 2

C276

C274

C275

SCD22U16V3ZY

1D25V_S3

1D25V_S3

C341

C319

SCD22U16V3ZY

C273

SCD22U16V3ZY
2

C339

SCD22U16V3ZY
2

C340

SCD22U16V3ZY
2

C268

SCD22U16V3ZY
2

VCC_CORE_S0

2D5V_S3

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

10u x 4

0.22u x 6

SCD22U16V3ZY
2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

LAYOUT: Place in uPGA socket cavity.

VCC_CORE_S0

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

L7
AC15
H18
B20
E21
H22
J23
H24
F26
N7
L9
V10
G13
K14
Y14
AB14
G15
J15
AA15
H16
K16
Y16
AB16
G17
J17
AA17
AC17
AE17
F18
K18
Y18
AB18
AD18
AG19
E19
G19
AC19
AA19
J19
F20
H20
K20
M20
P20
T20
V20
Y20
AB20
AD20
G21
J21
L21
N21
R21
U21
W21
AA21
AC21
F22
K22
M22
P22
T22
V22
Y22
AB22
AD22
E23
G23
L23
N23
R23
U23
W23
AA23
AC23
B24
D24
F24
K24
M24
P24
T24
V24
Y24
AB24
AD24
AH24
AE25
K26
P26
V26

SCD22U16V3ZY

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2D5V_S3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC_CORE_S0

Y17
K17
H17
F17
E18
AJ26
AE29
AC16
AA16
J16
G16
E16
AH14
AD15
AB15
K15
E15
D16
AE14
AC14
AA14
J14
G14
AF17
AD13
AB13
Y13
K13
H13
F13
AH12
AC12
AA12
G12
B12
AD11
AB11
Y11
K11
H11
F11
AH10
AC10
W10
U10
R10
N10
L10
J10
G10
B10
AD9
Y9
V9
T9
P9
M9
K9
H9
F9
AH8
AC8
W8
U8
R8
N8
L8
J8
G8
B8
AD7
AB7
V7
T7
P7
M7
K7
H7
F7
AH6
AC6
AA6
U6
R6
N6
L6
J6
G6
B6
AH4
B4
AH2
AD2
AB2
Y2
V2
T2
P2
M2
K2
H2
F2
C29
AH28
AF28
AC28
W28
R28
L28

N20
L20
J20
AF19
AD19
AB19
Y19
K19
H19
F19
D19
AC18
AA18
G18
B16
AD17
AB17
H15
F15
G28
D28
B28
C27
AH26
AF26
AD26
Y26
T26
M26
H26
D26
B26
C25
B25
AJ24
AG24
AC24
AA24
W24
U24
R24
N24
J24
G24
E24
AG23
AD23
AB23
Y23
V23
T23
P23
K23
H23
F23
D23
AJ22
AH22
AG22
AC22
AA22
AG29
U22
R22
N22
L22
J22
G22
E22
B22
AG21
AD21
Y21
V21
T21
P21
M21
K21
H21
F21
D21
AJ20
AG20
AE20
AC20
AA20
W20
U20
R20
G20
J18
AE16
Y15
B14
J12
AA10
AB9
AA8
Y7
W6
AF2
D2
AG27
AG25
L24
M23
W22
AB21
AH20
B2

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(4/4)_Power
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

of

58

BA0
BA1

M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

CKE0
CKE1

96
95

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

11
25
47
61
133
147
169
183
77

M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

12
26
48
62
134
148
170
184
78

M_ADM_R0
M_ADM_R1
M_ADM_R2
M_ADM_R3
M_ADM_R4
M_ADM_R5
M_ADM_R6
M_ADM_R7

CK0
/CK0
CK1
/CK1
CK2
/CK2

35
37
160
158
89
91

DDR_CLK0
DDR_CLK#0

SCL
SDA

195
193

SMBC_SB
SMBD_SB

SA0
SA1
SA2

194
196
198

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
202

85
86
97
98
123
124
200

NC#85
NC#86/(RESET#)
NC#97/A13
NC#98/BA2
NC#123
NC#124
NC#200

5,9 M_ARAS#
5,9 M_ACAS#
5,9 M_AWE#

118
120
119

/RAS
/CAS
/WE

VREF_DDR_MEM

1
2
197
199

VREF
VREF
VDDSPD
VDDID

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

201

GND

GND

71
73
79
83
72
74
80
84

M_AA13

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

C458
SCD1U

1
2

Layout trace 20 mil

3D3V_S0
C456
SCD1U
TP62
TPAD30

M_CS#0 5,9
M_CS#1 5,9
M_CKE#0

M_CKE#0 5,9

M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK5 5
M_CLK#5 5
M_CLK7 5
M_CLK#7 5

2D5V_S3

NOT SUPPORT ECC CHECK


AMD suggested pull-low

M_BA0
M_BA1
M_BA2
M_BA3
M_BA4
M_BA5
M_BA6
M_BA7
M_BA8
M_BA9
M_BA10
M_BA11
M_BA12

112
111
110
109
108
107
106
105
102
101
115
100
99

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 / AP
A11
A12

M_BBS#0
M_BBS#1

117
116

BA0
BA1

M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

REVERSE TYPE 9.2MM

117
116

121
122

/CS0
/CS1

121
122

CKE0
CKE1

96
95

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

11
25
47
61
133
147
169
183
77

M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

12
26
48
62
134
148
170
184
78

M_ADM_R0
M_ADM_R1
M_ADM_R2
M_ADM_R3
M_ADM_R4
M_ADM_R5
M_ADM_R6
M_ADM_R7

CK0
/CK0
CK1
/CK1
CK2
/CK2

35
37
160
158
89
91

SCL
SDA

195
193

SA0
SA1
SA2

194
196
198

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
202

85
86
97
98
123
124
200

NC#85
NC#86/(RESET#)
NC#97/A13
NC#98/BA2
NC#123
NC#124
NC#200

5,9 M_BRAS#
5,9 M_BCAS#
5,9 M_BWE#

118
120
119

/RAS
/CAS
/WE

VREF_DDR_MEM

1
2
197
199

VREF
VREF
VDDSPD
VDDID

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

201

GND

GND

71
73
79
83
72
74
80
84

1ST 62.10017.701 - 2ND 62.10017.201

M_BA13

Part Number = 62.10017.201


DDR-SODIMM-R-U2

Layout trace 20 mil


ME : 62.10017.201
2nd :62.10017.701

M_ABS#0
M_ABS#1

/CS0
/CS1

C497
SCD1U

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 / AP
A11
A12

112
111
110
109
108
107
106
105
102
101
115
100
99

M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA5
M_AA6
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
M_AA12

3D3V_S0
C498
SCD1U
TP63
TPAD30

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

M_CS#2 5,9
M_CS#3 5,9
M_CKE#1 5,9

! NOT THIS LIBRARY

M_ADM_R[7..0] 9

M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7

M_DATA_R_[63..0] 9
M_DQS_R[7..0]

M_AA[13..0] 5,9
M_ABS#[1..0] 5,9
M_BA[13..0] 5,9

M_CLK4 5
M_CLK#4 5
M_CLK6 5
M_CLK#6 5

DDR_CLK1
DDR_CLK#1

M_BBS#[1..0] 5,9

SMBC_SB 3,21
SMBD_SB 3,21
DM_SA0

R312
2
4K7R2

3D3V_S0

2D5V_S3
3

RN62
DDR_CLK#1
DDR_CLK#0
DDR_CLK1
DDR_CLK0

8
7
6
5

1
2
3
4
SRN10K-2

SB 0203

AMD CPU

MD63
SMA11

2D5V_S3

DDR1(Reverse 5.2mm)

DDR2(Reverse 9.2mm)

SMA10
SMA0 SMA14
SMA12
MD0

Pin 199

Pin 1

Pin 200

Pin 2

Pin 199

Pin 1

Pin 200

Pin 2

(Bottom view)
<Variant Name>

Wistron Corporation

62.10017.391
ME : 62.10017.391

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR SO-DIMM SKT


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

SKT-SODIMM2006U1
A

DDR2

REVERSE TYPE 5.2MM

DDR1

Sheet
E

of

58

SERIES DAMPING

PARALLEL TERMINATION

PLACE RNs CLOSE TO FIRST DIMM, < 0.75"


STRICT EQUAL LENGTH LIMITATION WITH DQS,
CB PINS
SRN10J-3

M_DATA4
M_DATA5
M_ADM0
M_DATA6
M_DATA7
M_DATA13
M_DATA12
M_ADM1

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

M_DATA_R_4
M_DATA_R_5
M_ADM_R0
M_DATA_R_6
M_DATA_R_7
M_DATA_R_13
M_DATA_R_12
M_ADM_R1

RN49

PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )
NO EQUAL LENGTH LIMITATION
M_DATA37
M_DATA36
M_ADM4
M_DATA39

4
3
2
1

M_DATA32
M_DATA33
M_DQS4
M_DATA34

4
3
2
1

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1

M_DATA35
M_DATA41
M_DATA40
M_DQS5
M_DATA42
M_DATA43
M_DATA49
M_DATA48

SRN10J-3
M_DATA_R_14
M_DATA_R_15
M_DATA_R_21
M_DATA_R_20
M_ADM_R2
M_DATA_R_23
M_DATA_R_22
M_DATA_R_28

M_DATA38
M_DATA45
M_DATA44
M_ADM5
M_DATA47
M_DATA46
M_DATA53
M_DATA52

8
7
6
5
4
3
2
1

SRN10J-3

4
3
2
1

M_DATA24
M_DQS3
M_DATA26
M_DATA27

4
3
2
1

M_DATA_R_38
M_DATA_R_45
M_DATA_R_44
M_ADM_R5
M_DATA_R_47
M_DATA_R_46
M_DATA_R_53
M_DATA_R_52

9
10
11
12
13
14
15
16

M_DQS_R6
M_DATA_R_50
M_DATA_R_51
M_DATA_R_56
M_DATA_R_57
M_DQS_R7
M_DATA_R_58
M_DATA_R_59

9
10
11
12
13
14
15
16

M_ADM_R6
M_DATA_R_54
M_DATA_R_55
M_DATA_R_61
M_DATA_R_60
M_ADM_R7
M_DATA_R_62
M_DATA_R_63

SRN10J-3

9
10
11
12
13
14
15
16

M_DATA_R_11
M_DATA_R_10
M_DATA_R_17
M_DATA_R_16
M_DQS_R2
M_DATA_R_19
M_DATA_R_18
M_DATA_R_25

M_DQS6
M_DATA50
M_DATA51
M_DATA56
M_DATA57
M_DQS7
M_DATA58
M_DATA59

8
7
6
5
4
3
2
1

RN39

M_DATA29
M_ADM3
M_DATA31
M_DATA30

9
10
11
12
13
14
15
16
RN53

8
7
6
5
4
3
2
1

1D25V_S3

RN43

RN51 SRN10-1
5 M_DATA_R_29
6 M_ADM_R3
7 M_DATA_R_31
8 M_DATA_R_30

5
6
7
8

M_DATA_R_24
M_DQS_R3
M_DATA_R_26
M_DATA_R_27

SRN10J-3
M_ADM6
M_DATA54
M_DATA55
M_DATA61
M_DATA60
M_ADM7
M_DATA62
M_DATA63

8
7
6
5
4
3
2
1
RN54

1D25V_S3

SRN68J-1
M_ADM_R1
M_DATA_R_13
M_DATA_R_12
M_DATA_R_7
M_DATA_R_6
M_ADM_R0
M_DATA_R_5
M_DATA_R_4

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

4
3
2
1

5
6
7
8

M_DATA_R_32
M_DATA_R_33
M_DQS_R4
M_DATA_R_35

4
3
2
1

5
6
7
8

4
3

M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1

8
7
6
5
4
3
2
1

M_DATA_R_28
M_DATA_R_23
M_DATA_R_22
M_ADM_R2
M_DATA_R_21
M_DATA_R_20
M_DATA_R_15
M_DATA_R_14

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

RN59
SRN68J-1

M_DATA_R_36
M_DATA_R_37
M_ADM_R4
M_DATA_R_38

M_BA12
M_BA5

1
2

8
7
6
5
4
3
2
1

1
2
3
4

M_DATA_R_31
M_DATA_R_30
M_ADM_R3
M_DATA_R_29

4
3
2
1

M_DQS_R[7..0]

SRN47J-1-U
M_AA11
M_AA9
M_AA7
M_AA5
M_AA4
M_AA8
M_AA6
M_AA3

9
10
11
12
13
14
15
16

M_DATA_R_48
M_DATA_R_49
M_DATA_R_43
M_DATA_R_42
M_DQS_R5
M_DATA_R_41
M_DATA_R_40
M_DATA_R_34

9
10
11
12
13
14
15
16

M_DATA_R_39
M_DATA_R_44
M_DATA_R_45
M_ADM_R5
M_DATA_R_46
M_DATA_R_47
M_DATA_R_52
M_DATA_R_53

8
7
6
5
4
3
2
1

M_ABS#[1..0] 5,8
M_BA[13..0] 5,8
M_BBS#[1..0] 5,8
M_AWE# 5,8
M_ACAS# 5,8
M_ARAS# 5,8

RN64SRN47-1

4
3
2
1

5
6
7
8

M_BWE# 5,8
M_BCAS# 5,8
M_BRAS# 5,8

RN109

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

5
6
7
8

9
10
11
12
13
14
15
16

M_CS#0
M_CS#1
M_CS#2
M_CS#3

SRN47J
4
3

5,8
5,8
5,8
5,8

RN70
M_BA3
M_BA7

M_DATA_R_59
M_DATA_R_58
M_DQS_R7
M_DATA_R_57
M_DATA_R_56
M_DATA_R_51
M_DATA_R_50
M_DQS_R6

1
2

M_AA1
M_AA10
M_AA2
M_AA0
M_ABS#1
M_ARAS#
M_CS#2
M_BA13

8
7
6
5
4
3
2
1

M_BA9
M_BA6
M_BA10
M_BA1
M_BA2
M_BA0
M_BBS#0
M_BWE#

8
7
6
5
4
3
2
1

SRN47J
4
3
SRN47J-1-U

9
10
11
12
13
14
15
16

5,8 M_CKE#0

M_CKE#0

5,8 M_CKE#1

M_CKE#1

RN65
SRN47J-1-U

RN69
SRN68J-1

RN61 SRN68-1
8
7
6
5

RN67
1
2

M_AWE#
M_ABS#0

M_AA[13..0] 5,8

9
10
11
12
13
14
15
16

M_CS#3
M_BCAS#
M_BRAS#
M_BBS#1

M_DQS[7..0] 5

RN63

RN111
SRN68J-1

RN60
M_DATA_R_27
M_DATA_R_26
M_DQS_R3
M_DATA_R_25

M_DATA_R_[63..0] 8

4
3

RN68
SRN68J-1

RN114
SRN68J-1
M_DATA_R_11
M_DATA_R_10
M_DATA_R_16
M_DATA_R_17
M_DQS_R2
M_DATA_R_19
M_DATA_R_18
M_DATA_R_24

M_ADM[7..0] 5
M_DATA[63..0] 5

RN57
SRN47J

SRN68J-1

RN40 SRN10-1

M_ADM_R6
M_DATA_R_54
M_DATA_R_55
M_DATA_R_60
M_DATA_R_61
M_ADM_R7
M_DATA_R_62
M_DATA_R_63

9
10
11
12
13
14
15
16

RN71
SRN47-1

RN112

M_BA4
M_BA8
M_BA11
M_CKE#1

RN115SRN68-1

1
2

RN110SRN68-1

SRN68J-1

M_ADM_R[7..0] 8

SRN47J
M_CKE#0
M_AA12

RN66 SRN68-1

RN113

M_DATA_R_35
M_DATA_R_41
M_DATA_R_40
M_DQS_R5
M_DATA_R_42
M_DATA_R_43
M_DATA_R_49
M_DATA_R_48

9
10
11
12
13
14
15
16

SRN10J-3

9
10
11
12
13
14
15
16
RN50

M_DATA11
M_DATA10
M_DATA17
M_DATA16
M_DQS2
M_DATA19
M_DATA18
M_DATA25

M_DATA_R_32
M_DATA_R_33
M_DQS_R4
M_DATA_R_34

RN42

8
7
6
5
4
3
2
1

5
6
7
8

8
7
6
5
4
3
2
1

RN38

M_DATA14
M_DATA15
M_DATA21
M_DATA20
M_ADM2
M_DATA23
M_DATA22
M_DATA28

RN52 SRN10-1
5 M_DATA_R_37
6 M_DATA_R_36
7 M_ADM_R4
8 M_DATA_R_39

RN41 SRN10-1
SRN10J-3

SRN10J-3
M_DATA1
M_DATA0
M_DQS0
M_DATA2
M_DATA3
M_DATA8
M_DATA9
M_DQS1

4
3
2
1

5
6
7
8

RN108
SRN47-1
M_AA13
M_CS#0
M_CS#1
M_ACAS#

4
3
2
1

5
6
7
8
RN58

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR DAMPING & TERMINATION

05/10
Remove the damping resistor for AMD suggest.

Size
A3

Document Number

Date: Thursday, March 31, 2005


A

Rev

-1

Bolsena
Sheet
E

of

58

LAYOUT:Place altemating caps to GND and 2D5_S3

1
C310
SCD1U

DY

DY

DY

DY

C337
SCD1U

C362
SCD1U

C361
SCD1U

C385
SCD1U

C386
SCD1U

C404
SCD1U

C405
SCD1U

C437
SCD1U

C436
SCD1U

C496
SCD1U

C878
SCD1U

C876
SCD1U

C874
SCD1U

C872
SCD1U

C870
SCD1U

C868
SCD1U

DY

C455
SCD1U

DY

DY

DY

DY

DY

DY

1
C387
SCD1U

1
C454
SCD1U

1
C338
SCD1U

1
C438
SCD1U

1
C406
SCD1U

1
C407
SCD1U

1
C388
SCD1U

1
C364
SCD1U

1
C363
SCD1U

1
C871
SCD1U

1
C869
SCD1U

1
C867
SCD1U

1
C877
SCD1U

1
C875
SCD1U

1
C873
SCD1U

1D25V_S3

2D5V_S3

C308
SCD1U

DY

2D5V_S3

DY

DY

DY

DY

C448
SCD1U

C449
SCD1U

C412
SCD1U

C390
SCD1U

C371
SCD1U

C343
SCD1U

C322
SCD1U

C411
SCD1U

C370
SCD1U

C504
SCD1U

C884
SCD1U

C880
SCD1U

C890
SCD1U

C888
SCD1U

C886
SCD1U

C882
SCD1U

DY

1
2

C502
SCD1U

C457
SCD1U

C463
SCD1U

C462
SCD1U

C459
SCD1U

C460
SCD1U

C465
SCD1U

DY

DY

DY

DY

DY

DY

C466
SCD1U

1
C447
SCD1U

1
C410
SCD1U

1
C408
SCD1U

1
C389
SCD1U

1
C369
SCD1U

1
C342
SCD1U

1
C321
SCD1U

1
C409
SCD1U

1
C368
SCD1U

1
C503
SCD1U

1
C889
SCD1U

1
C887
SCD1U

1
C885
SCD1U

1
C883
SCD1U

1
C881
SCD1U

1
C879
SCD1U

1
2

1D25V_S3
1D25V_S3

DY

DY

DY

DY

DY

DY

DY

C467
SCD1U

DY

LAYOUT:Place close to Power Pin of DDR socket.


2D5V_S3

LAYOUT:Place at end of the DIMMs

2D5V_S3

DY

2 C445
SCD22U16V3ZY

2 C464
SCD22U16V3ZY

2 C443
SCD22U16V3ZY

2 C501
SCD22U16V3ZY

2 C446 DY
SCD22U16V3ZY

2 C500
SCD22U16V3ZY

2 C444
SCD22U16V3ZY

2 C461
SCD22U16V3ZY

2 C442
SCD22U16V3ZY

2 C499
SCD22U16V3ZY

1
C891
SC10U10V5ZY

1
C865
SC10U10V5ZY

1
C892
SC10U10V5ZY

1
TC26
SE100U10VM

1
TC17
ST100U4VBM-U

1D25V_S3

C866
SC10U10V5ZY

79.10711.4C1

DY

DY

SB

DY

0.22u x 10

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR DECOUPLING
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

10

of

58

CLAW HAMMER TO NB

NB TO CLAW HAMMER

4 CPUCADOUT[15..0]
4 CPUCADOUTJ[15..0]

U80A

1
C221
SCD1U16V

1D2V_S0

C222
SCD1U16V

4 CPUHTTCLKOUT1
4 CPUHTTCLKOUTJ1
4 CPUHTTCLKOUT0
4 CPUHTTCLKOUTJ0

DY

AROUND NB

4 CPUHTTCTLOUT0
4 CPUHTTCTLOUTJ0

1 R162
1 R161

1D2V_S0

T26
R26
U25
U24
V26
U26
W25
W24
AA25
AA24
AB26
AA26
AC25
AC24
AD26
AC26

HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N

CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0

R29
R28
T30
R30
T28
T29
V29
U29
Y30
W30
Y28
Y29
AB29
AA29
AC29
AC28

HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N

Y26
W26

HT_RXCLK1P
HT_RXCLK1N

CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
CPUHTTCLKOUT0
CPUHTTCLKOUTJ0

W29
W28

CPUHTTCTLOUT0
CPUHTTCTLOUTJ0

P29
N29

2 49D9R2F HT_RXCALN
2 49D9R2F HT_RXCALP

D27
E27

HT_RXCLK0P
HT_RXCLK0N
HT_RXCTLP
HT_RXCTLN
HT_RXCALN
HT_RXCALP

PART 1OF6

HYPER TRANSPORT CPU I/F

CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8

NB0CADOUT[15..0] 4
NB0CADOUTJ[15..0] 4

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

R24
R25
N26
P26
N24
N25
L26
M26
J26
K26
J24
J25
G26
H26
G24
G25

NB0CADOUT15
NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

L30
M30
L28
L29
J29
K29
H30
H29
E29
E28
D30
E30
D28
D29
B29
C29

NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0

HT_TXCLK1P
HT_TXCLK1N

L24
L25

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1

NB0HTTCLKOUT1 4
NB0HTTCLKOUTJ1 4

HT_TXCLK0P
HT_TXCLK0N

F29
G29

NB0HTTCLKOUT0
NB0HTTCLKOUTJ0

NB0HTTCLKOUT0 4
NB0HTTCLKOUTJ0 4

HT_TXCTLP
HT_TXCTLN

M29
M28

NB0HTTCTLOUT
NB0HTTCTLOUTJ

HT_TXCALP
HT_TXCALN

B28
A28

HT_TXCALP
HT_TXCALN

NB0HTTCTLOUT 4
NB0HTTCTLOUTJ 4

1 R583

2
100R2F

CHANGE TO 71.RS48M.B0U (VER A22)

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-RS480M (1 of 4) HT
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

11

of

58

49 PEG_TXP[15..0]
49 PEG_TXN[15..0]
49 PEG_RXP[15..0]
49 PEG_RXN[15..0]
U80B

U80C

MEM_DQS0P
MEM_DQS1P
MEM_DQS2P
MEM_DQS3P
MEM_DQS4P
MEM_DQS5P
MEM_DQS6P
MEM_DQS7P

15 IDCKP

15 IDCKN

R634 2
33R2

IDCKN_1

AG25
AH29
AF21
AK25
AJ12
AF13
AK7
AF9

MEM_DQS0N
MEM_DQS1N
MEM_DQS2N
MEM_DQS3N
MEM_DQS4N
MEM_DQS5N
MEM_DQS6N
MEM_DQS7N

R636 2
33R2

AE17
AH18
AE18
AJ19
AF18

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE

Dummy when 'USE DVO' AK16

AJ16

SC 0308
2

C823 SCD47U16V3ZY
1
2MEM_CAP1
AE28
1
2MEM_CAP2
AJ4

MEM_CKP
MEM_CKN

MEM_CAP1
MEM_CAP2

C832 SCD47U16V3ZY
RS480_MEM_VMODE

AK20

MPVDD_PLL

AJ15
AJ14

1 R217
2
0R0603-PAD

1D8V_S0

SC 0308
1D8V_S0

AJ20

MEM_VREF

MEM_VMODE
MEM_VREF
MPVDD
MPVSS

MEM_COMPP
MEM_COMPN

AH5
AD30

D8
D7
D5
D4
E4
F4
G5
G4
H4
J4
H5
H6
G1
G2
K5
K4
L4
M4
N5
N4
P4
R4
P5
P6
P2
R2
T5
T4
U4
V4
W1
W2

DVO_MDA33
DVO_MDA34
DVO_MDA35
DVO_MDA36
DVO_MDA37
DVO_MDA38
DVO_MDA39
57 PCIE_RXP0
57 PCIE_RXN0

DVO_MDA48
DVO_MDA49
DVO_MDA50
DVO_MDA51
DVO_MDA52
DVO_MDA53
DVO_MDA54
DVO_MDA55

GPP_RX0P/SB_RX2P
GPP_RX0N/SB_RX2N

GPP_TX0P/SB_TX2P
GPP_TX0N/SB_TX2N

AD2
AD1

AB2
AC2

GPP_RX1P/SB_RX3P
GPP_RX1N/SB_RX3N

GPP_TX1P/SB_TX3P
GPP_TX1N/SB_TX3N

AA1
AB1

AB5
AB4

GPP_RX2P
GPP_RX2N

57 PCIE_RXP1
57 PCIE_RXN1

Y4
AA4

GPP_RX3P
GPP_RX3N

18 PCIE_RX0P_SB
18 PCIE_RX0N_SB

AG1
AH1

SB_RX0P
SB_RX0N

18 PCIE_RX1P_SB
18 PCIE_RX1N_SB

AC5
AC6

1 R620
2 10KR2 PCE_ISET AH3
PCE_TXISET AJ3
1
2
R633 8K25R3F

C826 1
C827 1

W5
W4

PCIE_TXP1_NB
PCIE_TXN1_NB

C804 1
C808 1

SB_TX0P
SB_TX0N

AF2
AG2

SB_TX0P C829 1
SB_TX0N C828 1

SB_TX1P
SB_TX1N

AC4
AD4

PCE_PCAL
PCE_NCAL

AH2
AJ2

SB_RX1P
SB_RX1N

1D8V_S0
MEM_COMPP
MEM_COMPN

1
1

R211 2 61D9R2F
R630 2 61D9R2F

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V

PEG_RXP15
PEG_RXN15
PEG_RXP14
PEG_RXN14
PEG_RXP13
PEG_RXN13
PEG_RXP12
PEG_RXN12
PEG_RXP11
PEG_RXN11
PEG_RXP10
PEG_RXN10
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0

Dummy when use UMA

2
2 SCD1U16V
SCD1U16V
2
2 SCD1U16V
SCD1U16V

PCIE_TXP0 57
PCIE_TXN0 57
PCIE_TXP1 57
PCIE_TXN1 57

Dummy when no EZ4


PCIE_TX0P_SB 18
PCIE_TX0N_SB 18
PCIE_TX1P_SB 18
PCIE_TX1N_SB 18

DVO_MDA33
DVO_MDA34
DVO_MDA35
DVO_MDA36
DVO_MDA37
DVO_MDA38
DVO_MDA39

15
15
15
15
15
15
15

DVO_MDA48
DVO_MDA49
DVO_MDA50
DVO_MDA51
DVO_MDA52
DVO_MDA53
DVO_MDA54
DVO_MDA55

DVO_MDA48
DVO_MDA49
DVO_MDA50
DVO_MDA51
DVO_MDA52
DVO_MDA53
DVO_MDA54
DVO_MDA55

15
15
15
15
15
15
15
15

Dummy when 'USE DVO'

R214
1KR2F

WITH DVO:
MEM_COMPP = 61.9 OHM TO GND
MEM_COMPN = 61.9 OHM TO VDD_MEM
MEM_CAP1 = NC
MEM_CAP2 = NC
MEM_VMODE = 1.8V(IF VDD_MEM = 1.8V)
MEM_VREF = VDD_MEM / 2

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SC 0308
Title

ATI-RS480M (2 of 4) PCIE
Size
A3

Document Number

Date: Thursday, March 31, 2005


B

1D2V_S0

2
2
1

R210
1KR2

Dummy when 'NO DVO'

MEM_VREF

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2 SCD1U16V
SCD1U16V
SB_TX1P C830 1
2
SB_TX1N C831 1
2 SCD1U16V
SCD1U16V
PCE_PCAL
1 R632
2 150R2F
PCE_NCAL
100R2F
1 R631
2

DVO_MDA33
DVO_MDA34
DVO_MDA35
DVO_MDA36
DVO_MDA37
DVO_MDA38
DVO_MDA39

R209
1KR2

RS480_MEM_VMODE

PCIE_TXP0_NB
PCIE_TXN0_NB

PCIE I/F TO SB

R208
1KR2F

NO DVO:
MEM_COMPP = NC
MEM_COMPN = NC
MEM_CAP1 = 470nF
MEM_CAP2 = 470nF
MEM_VMODE = GND (IF VDD_MEM = 2.5V)
MEM_VREF = VDD_MEM / 2

C742
C743
C744
C745
C746
C747
C748
C749
C751
C750
C774
C772
C777
C776
C770
C773
C781
C780
C775
C771
C779
C778
C799
C801
C807
C803
C797
C800
C805
C806
C802
C798

Y5
Y6

GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

PCE_ISET
PCE_TXISET

PEG_RXP15_NB
PEG_RXN15_NB
PEG_RXP14_NB
PEG_RXN14_NB
PEG_RXP13_NB
PEG_RXN13_NB
PEG_RXP12_NB
PEG_RXN12_NB
PEG_RXP11_NB
PEG_RXN11_NB
PEG_RXP10_NB
PEG_RXN10_NB
PEG_RXP9_NB
PEG_RXN9_NB
PEG_RXP8_NB
PEG_RXN8_NB
PEG_RXP7_NB
PEG_RXN7_NB
PEG_RXP6_NB
PEG_RXN6_NB
PEG_RXP5_NB
PEG_RXN5_NB
PEG_RXP4_NB
PEG_RXN4_NB
PEG_RXP3_NB
PEG_RXN3_NB
PEG_RXP2_NB
PEG_RXN2_NB
PEG_RXP1_NB
PEG_RXN1_NB
PEG_RXP0_NB
PEG_RXN0_NB

CHANGE TO 71.RS48M.B0U (VER A22)

CHANGE TO 71.RS48M.B0U (VER A22)

PCIE I/F TO SLOT

1D8V_S0

SC 0308

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A7
B7
B6
B5
A5
A4
B3
B2
C1
D1
D2
E2
F2
F1
H2
J2
J1
K1
K2
L2
M2
M1
N1
N2
R1
T1
T2
U2
V2
V1
Y2
AA2

AE1
AE2

Dummy when 'NO DVO'

C324
SC1U10V3KX

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

PCIE I/F TO VIDEO

IDCKP_1

AF25
AH30
AG20
AJ25
AH13
AF14
AJ7
AG8

PART 2 OF 6
PEG_TXP15
PEG_TXN15
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_TXP12
PEG_TXN12
PEG_TXP11
PEG_TXN11
PEG_TXP10
PEG_TXN10
PEG_TXP9
PEG_TXN9
PEG_TXP8
PEG_TXN8
PEG_TXP7
PEG_TXN7
PEG_TXP6
PEG_TXN6
PEG_TXP5
PEG_TXN5
PEG_TXP4
PEG_TXN4
PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0

MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7

MEM_DQ0
6 MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63

LANE REVERSE

AG26
AJ29
AE21
AH24
AH12
AG13
AH8
AE8

3 OF

MEM_A I/F

MEM_A0
MEM_A1 PART
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14

AF28
AF27
AG28
AF26
AE25
AE24
AF24
AG23
AE29
AF29
AG30
AG29
AH28
AJ28
AH27
AJ27
AE23
AG22
AF23
AF22
AE20
AG19
AF20
AF19
AH26
AJ26
AK26
AH25
AJ24
AH23
AJ23
AH22
AK14
AH14
AK13
AJ13
AJ11
AH11
AJ10
AH10
AE15
AF15
AG14
AE14
AE12
AF12
AG11
AE11
AJ9
AH9
AJ8
AK8
AH7
AJ6
AH6
AJ5
AG10
AF11
AF10
AE9
AG7
AF8
AF7
AE7

LANE REVERSE

AF17
AK17
AH16
AF16
AJ22
AJ21
AH20
AH21
AK19
AH19
AJ17
AG16
AG17
AH17
AJ18

Rev

-1

Bolsena
Sheet
E

12

of

58

AVDD

AVDDQ

PLLVDD
PLLVSS

M23
L23

HTPVDD
HTPVSS

D14
B15
B12
C12
AH4

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
SUS_STAT#

LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8

G19
E20
F20
H18
G18
F19
H19
F18

LVDS_DIGON
LVDS_BLON
LVDS_BLEN

E14
F14
F13

VDDR3_1
VDDR3_2

3 CLK14_NB
21 SB_OSC_INT

C259
SC1U10V3ZY

R594 2
22R2

A13
B13

NB_OSC_OUT

OSCIN
OSCOUT

CLOCKs

DY

NB_SUS_STAT#

DO NOT SUPPORT SIDEPORT MEMORY


DO NOT SUPPORT SERIAL STRAP ROM
DUMMY IT

TPAD30
TPAD30
TPAD30

TP32
TP24
TP23

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2

B9

DFT_GPIO0/RSV
DFT_GPIO1/RSV
DFT_GPIO2/RSV

RN106

4
3

RN107
3 SRN0-2-U 2
4
1

1
2
SRN10KJ

18 BMREQ#

RS480_CLK
RS480_DAT

F10
C10
C11
AF4
AE4

BMREQb
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

MIS.

A10
E10

AG_RST# 49

TSLCX08MTC-U

2
BLM11A121S

C226

TMDS_UMA_HPD 15
TP33 TPAD28

TESTMODE

E12 TESTMODE_NB

DDC_DATA 15

VCC_CORE_S0

1 2

<Variant Name>
1

11

1 R607

2
0R2-0

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

BL_ON 34,49

TSLCX08MTC-U

Dummy when use Discrete

Title
R739
10KR2

R608
1KR2

R187
4K7R2

Wistron Corporation

13

2
B

R590

TPAD30
TPAD30
TPAD30

ATI-RS480M (3 of 4) LVDS CRT


Size
A3

Document Number

SB 0201
Date: Thursday, March 31, 2005

C225

TP81
TP80
TP79

U22D

12
LVDS_BLON

DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

B10 DDC_DATA

LCDVDD_ON

3D3V_S5

RS480_RST#
C251
DUMMY-C3

2
BLM11A121S

2
0R2-0

TSLCX08MTC-U
6

R159 2
33R2

TPAD30

R591

SBLINK_CLK 3
SBLINK_CLK# 3

DDC_DATA

U22BDY

SC 0307
18,34,37 LPC_RST#

C738

R760 2
33R2

14

NB_PWRGD

3D3V_S5

Place close the two resistor

C227

2
3

39 ALL_PWROK

DY

U22A

TP31

NBSRC_CLK 3
NBSRC_CLK# 3

2
BLM11A121S

R186
DUMMY-R2

14

6,18 LDT_RST#

C739

C737
LVDS_DIGON
LVDS_BLON
LVDS_BLEN_NB

E8
E7

TMDS_HPD

R185
LVDS_DIGON

1 C968
SCD1U16V
SC 0310
1

LVDDR18A_S0

2
P23 HTTST_CLK 1 R196
10KR2
N23
HTREF_CLK 3

STRP_DATA

GMODULE_RST# 34
R759
0R2-0

LVDDR18D_S0

HTTSTCLK
HTREFCLK

DFT_GPIO3/RSV
DFT_GPIO4/RSV
DFT_GPIO5/RSV

Dummy when use Discrete

DY

R183 2
0R2-0
3D3V_S5

14

1D8VLPVDD_S0

B8
A8

C13
C14
C15

CHANGE TO 71.RS48M.B0U (VER A22)

GFX_CLKP
GFX_CLKN

SB_CLKP
SB_CLKN

TVCLKIN

F12
E13
D13

15 RS480_CLK

3D3V_S0

17,49 EDID_CLK
17,49 EDID_DAT

R595 2 10KR2

R592
TP30
TP29

TXBCLK+
TXBCLKTXACLK+
TXACLK-

E18
F17
E19
G20
H20

1D8V_S0

LPVDD
LPVSS
LVDDR18D
LVDDR18A_1
LVDDR18A_2

17,54

TP28
TP22

B20
A20
B18
C17

LCD_VDD_ON

SC2D2U16V5ZY

A14
B14

TXCLK_UP
TXCLK_UN
TXCLK_LP
TXCLK_LN

17,54
17,54
17,54
17,54

Dummy when use Discrete

DAC_VSYNC
DAC_HSYNC
RSET
DAC_SCL
DAC_SDA

TXAOUT0+
B16
TXAOUT0A16
TXAOUT1+
D16
TXAOUT1C16
TXAOUT2+
B17
TXAOUT2A17
TXAOUT3+
E17
D17 TXAOUT3-

LCD_TXBCLK+
LCD_TXBCLKLCD_TXBOUT2+
LCD_TXBOUT2-

SRN0-1-U

1
0R2-0

A11
B11
C26
E11
F11

H13
H12

3D3VDDR_S0

SC 0308
R635
4K7R2

RED
GREEN
BLUE

3D3V_S0

1 R188
2
0R0603-PAD

NB_SUS_STAT#

C25
A26
B26

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

SC10U10V5ZY
2

RS480_RST#
39 NB_PWRGD
6,18 LDT_STP#
18 ALLOW_LDTSTOP

C
Y
COMP

17,54
17,54
17,54
17,54

SCD1U16V

SCD1U16V

C767

B25
A25
A24

4
3
2
1

2 R184

LCD_TXBOUT1+
LCD_TXBOUT1LCD_TXBOUT0+
LCD_TXBOUT0-

SRN0-1-U

C765

SCD1U16V
2

2
C768

SCD1U16V

HTPVDD

IRSET_NB

16 UMA_CRT_DDC_C
16 UMA_CRT_DDC_D

C717

SC2D2U16V5ZY
2

1D8V_S0

C741

SC10U10V5ZY
2

C740

4
3
2
1

RN94
LCDVDD_ON

17,54
17,54
17,54
17,54

SRN0-1-U

1 R163
2
SC 0228
634R3F

AVDDQ
AVSSQ

TXBOUT0+
D18
TXBOUT0C18
TXBOUT1+
B19
TXBOUT1A19
TXBOUT2+
D19
TXBOUT2C19
D20 TXBOUT3+
TXBOUT3C20

16 UMA_VS
16 UMA_HS

E24
D24

TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

LVDS

C254
SC1U10V3ZY

PART 4 OF 6

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

PLL PWR

AVDDQ

CRT/TVOUT

B27
C27
D26
D25
C24
B24

PM

1
2
1
2
1
2
150R2F R588
150R2F R587
150R2F R589

R585 1 102R2F 2
R586 1 102R2F 2
R165 1 102R2F 2

SC 0301

PLVDD

1
BLM11A121S

1D8V_S0

5
6
7
8

4
3
2
1

RN95
U80D

R593

150R5F

TXBCLK+
TXBCLKTXBOUT2+
TXBOUT2-

C220
SC2D2U16V5ZY

57 UMA_R
57 UMA_G
57 UMA_B

1D8V_S0

SC 0308

5
6
7
8

LCD_TXAOUT1+
LCD_TXAOUT1LCD_TXAOUT0+
LCD_TXAOUT0-

SRN0-1-U

RN89
1D8VAVDDD1_S0

57 UMA_CRMA
57 UMA_LUMA
57 UMA_COMP

1
R609

TXBOUT1+
TXBOUT1TXBOUT0+
TXBOUT0-

SC 0308

1 R164
2
0R0603-PAD

Dummy when use Discrete

5
6
7
8

17,54
17,54
17,54
17,54

SC1U10V3ZY

C735
SC2D2U16V5ZY

LCD_TXACLK+
LCD_TXACLKLCD_TXAOUT2+
LCD_TXAOUT2-

SCD1U16V

1D8V_S0

DY

SC10U10V5ZY
2

SC 0308

TXAOUT1+
TXAOUT1TXAOUT0+
TXAOUT0-

4
3
2
1
RN90

C766

SC 0308

5
6
7
8

C769

1 R610
2
0R0603-PAD

1 R584
2
0R0603-PAD

TXACLK+
TXACLKTXAOUT2+
TXAOUT2-

1D8V_S0

SCD1U16V

3D3V_S0

1
SC1U10V3ZY

SC1U10V3ZY

Rev

-1

Bolsena
Sheet
E

13

of

58

F15
E15
D10
E16
H14
H16
H10
H17
AD25
H11
D11
W27
F26
T24
B30
F25
G16
C28
Y27
R19
AC9
Y23
G17
AA28
AD24
D12
AB25
AB28
G30
F16
G11
AD9
D9
D15
E9
G13
Y24
G14
G15
AC27
AD27
AD29
G12
G10

P16
M16
M12
M14
T18
V16
W15
N17
U13
M18
V18
P18
W17
W13
R13
T12
P12
R17
T16
U17
P14
N13
V12
N15
T14
R15
V14
U15

VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1

VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45

AE27
AE26
W19
AK29
AK22
AD21
AC13
AK10
AK5
AC21
AJ30
AD7
AC11
AG27
AC19
AG9
AG24
AF30
AG12
AG15
AD17
AG21
AG6
AG5
AD23
AD19
AD16
AD13
AD11
AD8
AC23
AG18
AC16
U19
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73

G28
F27
F24
AD28
R27
T27
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107

U80F

VSS30

VSS89

PAR 6 OF 6

VSSA68
VSSA67
VSSA66
VSSA65
VSSA64
VSSA63
VSSA62
VSSA61
VSSA60
VSSA59
VSSA58
VSSA57
VSSA56
VSSA55
VSSA54
VSSA53
VSSA52
VSSA51
VSSA50
VSSA49
VSSA48
VSSA47
VSSA46
VSSA45
VSSA44
VSSA43
VSSA42
VSSA41
VSSA40
VSSA39
VSSA38
VSSA37
VSSA36
VSSA35
VSSA34
VSSA33
VSSA32
VSSA31
VSSA30
VSSA29
VSSA28
VSSA27
VSSA26
VSSA25
VSSA24
VSSA23
VSSA22
VSSA21
VSSA20
VSSA19
VSSA18
VSSA17
VSSA16
VSSA15
VSSA14
VSSA13
VSSA12
VSSA11
VSSA10
VSSA9
VSSA8
VSSA7
VSSA6
VSSA5
VSSA4
VSSA3
VSSA2
VSSA1
VSSA59

VSSA22

T8
L5
E5
U6
U5
E6
F6
V7
M7
AJ1
L6
AG3
C2
H8
V6
M3
H7
K7
AD6
Y7
T7
AB8
K3
C4
D6
AD5
J3
R6
J5
C7
C9
AA5
P7
B4
G3
AB7
M5
AF3
AE3
F3
V8
AD3
C8
J6
P8
AB3
A2
AA3
C6
D3
K8
W3
C3
V3
Y8
M8
F8
C5
M6
T3
AA6
R3
F5
F7
N3
V5
AE5
R5

VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
L27
T23
K28
N19
J28
M24
H28
F28

VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122

GROUND

R23
V28
V25
U28
K25
E26
P28
P25
N28
H24
M27

1D2V_S0

1D2V_S0
U80E

1D8V_S0
L11

SC1U10V3KX

1
2

SCD1U16V
2

C258 C291

1D2V_S0

VDD_CORE47
VDD_CORE46
VDD_CORE45
VDD_CORE44
VDD_CORE43
VDD_CORE42
VDD_CORE41
VDD_CORE40
VDD_CORE39

1
1

TC10
ST100U6D3VDM-5

VDDHT30
C736
SC4D7U10V5ZY

DY
VSS30
VDDHT31

VDDA18_13

C296
SCD1U16V

DY

2
1

DY

VSS89

C289
C294
C295
C256
C260
SC10U10V5ZY
SCD1U16V SCD1U16V SCD1U16V SCD1U16V

C796
SC4D7U10V5ZY

1D2V_S0

C292
C290
C286
C297
C298
SC10U10V5ZY
SCD1U16V SCD1U16V SCD1U16V SCD1U16V

DY
<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-RS480M (4 of 4) PWR, GND


Document Number

CHANGE TO 71.RS48M.B0U (VER A22)


Date: Thursday, March 31, 2005
B

C334
SC4D7U10V5ZY

VSSA59

1
2

C332
C302
C303
C262
C300
SC1U10V3KX
SCD1U16V SCD1U16V SCD1U16V SCD1U16V

L9 2
MLB-201209-11

Size
A3

DY

2
1

U25
BAV99-1

1
2

VDD_18_1
VDD_18_2
VDD_18_3

C264
SC4D7U10V5ZY

VDDA18_13

VDDA12_13

H15
AC17
AC15
B21
C21
A22
B22
C22
F21
F22
E21
G21

DY

0R2-0

3D3V_S0

U24
BAV99-1

1
R215
0R2-0

C288

SCD1U16V
2

DY

DY

C346

SCD1U16V
2

R216

1D8VDD_S0

2
BLM11A121S
1

VSSA22

1D8V_S0

DY

VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
VDD_MEM7
VDD_MEM8
VDD_MEM9
VDD_MEM10
VDD_MEM11
VDD_MEM12
VDD_MEM13
VDD_MEM14
VDD_MEM15
VDD_MEM16
VDD_MEM17
VDD_MEM18
VDD_MEMCK

VDDA12_13

TC9
ST100U6D3VDM-5

1D8V_VDDA

DY

C326
C293
C329
C325
C331
C344
C327
C333
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

AK23
AK28
AK11
AK4
AE30
AC14
AD12
AC18
AC20
AD10
AD14
AD15
AD20
AC10
AD18
AC12
AD22
AC22
AH15

C305
SC10U10V5ZY

L10 2
MLB-201209-11

SB 0127

SCD1U16V

VDDHT30
VDDHT31

2
1

2
1

2
1

2
1

2
1

2
1

C821
C825
C285
C330
C287
C323
C328
C345
SC10U10V5ZY
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

DY

C261
C263
C304
C301
C299
SC1U10V3KX
SCD1U16V SCD1U16V SCD1U16V SCD1U16V

1D8V_S0

VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12
VDDA_12_13
VDDA_18_1
VDDA_18_2
VDDA_18_3
VDDA_18_4
VDDA_18_5
VDDA_18_6
VDDA_18_7
VDDA_18_8
VDDA_18_9
VDDA_18_10
VDDA_18_11
VDDA_18_12
VDDA_18_13
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
VDD_CORE36
VDD_CORE37
VDD_CORE38

DY

VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19
VDD_HT20
VDD_HT21
VDD_HT22
VDD_HT23
VDD_HT24
VDD_HT25
VDD_HT26
VDD_HT27
VDD_HT28
VDD_HT29
VDD_HT30
VDD_HT31

1D2V_VDDA_RS480_S0

C278
C280
C281
C282
C283
C279
C277
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

N27
U27
V27
G27
V24
H27
K24
AB24
P27
J27
AA27
K27
P24
AB27
AB23
V23
G23
E23
W23
K23
J23
H23
U23
AA23
D23
F23
C23
B23
A23
A29
AC30

H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7
B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5
AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21

2
1

DY

DY

C284
C253
C252
C257
C255
C223
C224
SC10U10V5ZY
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

PART 5 OF 6 VDDA_12_14

POWER

Rev

-1

Bolsena
Sheet
E

14

of

58

3D3V_S0

1
2

1
2

SRN10KJ

SRN10KJ

RN15

DVI_D_1
RN20

EZ4_DVI_DDC_D

57

TMDS_EZ4_TX0TMDS_EZ4_TX0+
TMDS_EZ4_TXC+
TMDS_EZ4_TXC-

49,57
49,57
49,57
49,57

2
1

SB 0202

21
22
24
25
27
28
30
31
DVI_AS

1 R724

R723
330R2

1D8V_S0

R725 1

2
2

140R2F-GP DVI_ISET

2K4R2F
1KR2 2
R36 1
1KR2 2
R35 1
2
1
SCD1U10V2MX
C25

DVI_VSWING
VREF_DVI

GPIO0
GPIO1/TLDET#
AS

35

ISET

6
11
64

DVDDV

45

TVDD
TVDD
TGND
TGND
TGND

23
29
20
26
32

AVDD
AVDD
AGND
AGND
AGND
VDD
GND
GND

18
44
16
17
41
33
34
40

VSWING
VREF

3D3V_DVI_AVDD_S0
3D3V_S0
R39

CH7301C-T

C27

TMDS_HPD

R43

1
BLM11A121S
C26

1
2

SC10U10V5ZY

1
2

C30

C55

C29

C28

R40
1
BLM11A121S

Dummy when use Discrete


R4

DVI_EZ4_HPD

57

10KR2

3
Q3

2
0R2-0

Dummy when use Discrete CHT2222A

3
Q4
CHT2222A

R3
100KR2

1
2

SB 0127

R41

C56

2
SSM5817S

R56
10KR2

To UMA & CH7301

D51

10KR2

2
1

13 TMDS_UMA_HPD

C24

2
0R2-0

Dummy when use UMA

2
1

C57

3D3V_DVI_VDD_S0

1
BLM11A121S

3D3V_DVI_TVDD_S0

1
1 R42

1D8V_S0

C954
SC10U10V5ZY

SCD1U10V2MX

C953

SB 0127

49 DVI_HPD

R54
1
BLM11A121S

C52

1D8V_DVI_DVDDV_S0

SC2200P50V2KX

C51

3D3V_DVI_DVDD_S0

3D3V_S0

To Discrete

1
75R2F

SC10U10V5ZY

SPD
SPC

10

19

DGND
DGND
DGND

RESET#

CH7301_DATA
14
CH7301_CLK
15
SB 0128
8
DY 2 0R2-0 DVI_GIPO0
0R2-0
DVI_GIPO1
2
7

DY

1
12
49

R721 1
R722 1

DVDD
DVDD
DVDD

R727

DUMMY-C2

3D3V_S0

DY

DY 1

75R2F

SC10U10V5ZY

C955
R720
10KR2

39

R34

SCD1U10V2MX

13
RN118 SRN0-2-U
DVI_D_1 3
2
DVI_C_1 4
1

CVBS/B

R728

3D3V_S0

75R2F

R733 2 0R2-0

DY 1

SCD1U10V2MX

38

R726

SC2200P50V2KX
1

PCIRST_BUF#

H
V

42

18,26,28,29,31,57

3D3V_S0

4
5

C/R

DY 1

DVO_MDA54
DVO_MDA55

12 DVO_MDA54
12 DVO_MDA55

P-OUT/TLDET#

37

SC2200P50V2KX

46

Y/G

SB change much in this page 0127

DE

36

48

CVBS

SC2200P50V2KX

XCLK#
XCLK

C/HSYNC

DVO_MDA53

12 DVO_MDA53

56
57

TMDS_UMA_HPD

47

12 IDCKN
12 IDCKP

BCO

U10

HPDET

SRN0-2-U

D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

XO

2
1

50
51
52
53
54
55
58
59
60
61
62
63

43

3
4

DVO_MDA33
DVO_MDA34
DVO_MDA35
DVO_MDA36
DVO_MDA37
DVO_MDA38
DVO_MDA48
DVO_MDA39
DVO_MDA51
DVO_MDA50
DVO_MDA49
DVO_MDA52

DVO_MDA33
DVO_MDA34
DVO_MDA35
DVO_MDA36
DVO_MDA37
DVO_MDA38
DVO_MDA48
DVO_MDA39
DVO_MDA51
DVO_MDA50
DVO_MDA49
DVO_MDA52

XI/FIN

12
12
12
12
12
12
12
12
12
12
12
12

RN21

TDC0#
TDC0
TDC1#
TDC1
TDC2#
TDC2
TLC
TLC#

To UMA

SCD1U10V2MX

Dummy when use UMA

SCD1U10V2MX
1
2

57

EZ4_DVI_DDC_C
DVI_C_1

SRN0-2-U

13 DDC_DATA
13 RS480_CLK

49,57
49,57
49,57
49,57
4

To EZ4 (5V level)

TMDS_EZ4_TX0TMDS_EZ4_TX0+
TMDS_EZ4_TX1TMDS_EZ4_TX1+
TMDS_EZ4_TX2TMDS_EZ4_TX2+
TMDS_EZ4_TXC+
TMDS_EZ4_TXC-

3
4

49 DIS_DVI_DDC_D
49 DIS_DVI_DDC_C

TMDS_EZ4_TX2TMDS_EZ4_TX2+
TMDS_EZ4_TX1TMDS_EZ4_TX1+

4
3

U11
2N7002DW

4
3

To Discrete

5V_S0

RN16

<Variant Name>

Dummy when no EZ4


1

Place Near Dock

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

UMA DVI - CH7301C


Size
A3

Document Number

Date: Thursday, March 31, 2005


A

Rev

-1

Bolsena
Sheet
E

15

of

58

3D3V_S0

CRT
CONN
200mA Rating/Spec 500mA
1
2

5V_CRT_S0

To SYS and EZ4 CRT Both

1
2

RN82

RN1

5V_S0

SRN10KJ

4
3

4
3

SRN10KJ

U1
2N7002DW

14

U2A

HSYNC_5_1

14

SRN0-2-U

Dummy when use Discrete

HSYNC_5

SRN0-2-U

CRT_DDC_D_1
CRT_DDC_C_1

SYS_CRT_DDC_D5
SYS_CRT_DDC_C5
RN2

Dummy when use Discrete

VSYNC_5

3
4
SRN0-2-U

2
1
SRN0-2-U

Dummy when use UMA

RN5

2
1

EZ4_CRT_DDC_D 57
EZ4_CRT_DDC_C 57

Dummy when no EZ4

D28

EZ4_HS 57
EZ4_VS 57

3
4

Dummy when no EZ4

SRN0-2-U

5V_CRT_S0

RB751V-40-U
C657
SCD01U50V2ZY

SRN0-2-U

DUMMY-C2

3
4

49 DIS_CRT_DDC_D
49 DIS_CRT_DDC_C

2
1

5V_S0
C2

2
1

SYS_VS

2
10R3

SC 0308

C3
DUMMY-C2

TSAHCT125

R2

RN7

3
4

SYS_HS

2
10R3

2
1

RN4

49 DIS_HS
49 DIS_VS

R1

3
4

13 UMA_CRT_DDC_D
13 UMA_CRT_DDC_C

TSAHCT125

U2B

2
1VSYNC_5_1

3
4

13 UMA_HS
13 UMA_VS

RN3

To SYS and EZ4 CRT Both

RN6

Dummy when use UMA

L22
CRT1

L23

SYS_CRT_DDC_D5

2 BLM18BB750SN1D

CRT_G
CRT_R

L24

SYS_HS

2 BLM18BB750SN1D
1

SYS_CRT_DDC_C5

BAV99-2
2

DY

C236
SC100P50V2JN

2
IND-1D2UH

TV_COMP_CON
2
IND-1D2UH

TV_COMP_CON
TV_CRMA_CON
D36

SC270P50V

SC100P50V2JN

4
2
5
7
6
3

5 4
7 2 1

3D3V_S0

DY

COMPOSIT

MINDIN7-11

<Variant Name>

22.10021.D81
ME : 22.10021.D81

C209

SC100P50V2JN

C238

TV_LUMA_CON

LUMA

8
1

BAV99-2

CHROMA

TV1

3D3V_S0

1
1
2
150R2F R172
1
2
150R2F R171
1
2
150R2F R151

TV CONN

DY

C234
SC270P50V

TV_CRMA_CON
2
IND-1D2UH

VIDEO-15-42

ME : 20.20378.015

D35

L8

57 TV_CRMA_SYS
1

20.20378.015

BAV99-2

2 C231
SC47P50V2JN

BAV99-2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRT / TV

SC 0302
Size
A3

SC 0302

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005


A

SYS_CRT_DDC_C5

16

3D3V_S0

1
2

1
2

C237
SC100P50V2JN

SYS_VS

15

C235
SC270P50V

L7

SYS_HS

14

DY

DY

2 C233
SC47P50V2JN

57 TV_COMP_SYS

DY

SYS_CRT_DDC_D5

13

5V_S0

BAV99-2

57 TV_LUMA_SYS

BAV99-2

12

D34

L6
TV_LUMA_CON

SC 0228

SC100P50V2JN

D25

D26

D27
SC 0228

2 C232
SC47P50V2JN

11

C658
SC 0228

DY

C655

C659
C656

6
1

7
CRT_G
2
8
CRT_B
3
5V_CRT_S0 9
4
10
5

SYS_VS

C654
SC8D2P50V2CC

1
2

C653
SC8D2P50V2CC

2
1
150R2FR504
150R2F
R504
2
1
150R2FR505
150R2FR505
2
1
150R2FR506
150R2FR506

SC8D2P50V2CC

C652

1
SC47P50V2JN

DY

SC47P50V2JN

C668

C667

SC47P50V2JN

1
2

C666

DY

CRT_B

57 CRT_B_SYS

17

SC10P50V2JN-1

CRT_R

57 CRT_G_SYS

2 BLM18BB750SN1D

57 CRT_R_SYS

SC10P50V2JN-1
2

Sheet
E

16

of

58

LEDs

5V_S0
D6

on KB Cover

D5

LED-G-31
2

on KB Cover

D4

LED-G-31
2

on KB Cover

D7

LED-G-31
2

on KB Cover

D24

LED-Y-22
2

on Front Panel

D3
1

LED-G-31
2

on KB Cover

D50
1

LED-G-31
2

D48
1

LED-G-31
2

1 R17

2
330R2

CAP_LED#

1 R16

2
330R2

MAIL_LED#

1 R14

2
330R2

MEDIA_LED#

1 R19

WLAN_LED#

?modify R
?half light

Dummy when use IDE


19 SATA_LED#

1 R22

25 HDD_LED#_5

SC 0302

1 R483

2
330R2

1 R10

2
330R2

FRONT_PWRLED# 1 R497

2
330R2

on Front Panel
5V_S5

2
0R2-0
DC_BATFULL#

D8
R21 2
0R2-0

Dummy when use SATA


25 CDROM_LED#_5

2
330R2

SC 0302

LED-G-31
2

NUM_LED#

1 R495

2
330R2

on Front Panel

MEDIA_LED#
SC 0308

1
BAW56

5V_S0
D23

34
34
34
34

BLT_LED#

NUM_LED#
CAP_LED#
MAIL_LED#
BLT_LED#

2
330R2

on Front Panel

1
LED-B-27-U-GP
D49

31 WLAN_LED#

1 R480

STDBY_LED#

34 STDBY_LED#
34 CHARGE_LED#
34 DC_BATFULL#

1 R496

2
330R2

1
D47

CHARGE_LED#

34 FRONT_PWRLED#
RC2
NUM_LED#
CAP_LED#
MAIL_LED#
MEDIA_LED#

1
2
3
4

SRC100P50V-U
8
7
6
5

1 R494

on KB cover

2
330R2

RC9

1
2
3
4

SRC100P50V-U
8
7
6
5

C644SC100P50V2JN
1
2

DC_BATFULL#

FRONT_PWRLED# 1

SC 0302

LED-Y-22
2

on Front Panel

LED-Y-22
2

on Front Panel

SC 0302

LED

Button

V
V

NUM

HDD

POWER1 E-MAIL INTERNET e-BTN


WLAN_LED#
STDBY_LED#
BLT_LED#
CHARGE_LED#

5V_S5

PROGRAM CAPS

Front panel
LED

Button

Charger:
Green : DC only or Battery full with DC
Orange : Charging
Orange Blink : Battery low

BlutTooth Wireless Charger Power2

C229SC100P50V2JN
2

Power2:
Green : S0
Orange : S3
Orange Blinking : Enter S4

(Please See M.E. drawing LED position)


2

1
SC100P50V2JN

C651

C664
SCD1U

1
SC100P50V2JN

C663 C665

SC10U35V0ZY-U
2
1
2
1

LCDPOWER_S0

3D3V_S0

DY
U13

1 R50

2
1KR2

LCDVDD_ON_1
C40

ODD CHANNEL

OUT
GND
ON/OFF#

IN
GND
IN

6
5
4
1

13,54 LCD_VDD_ON

EVEN CHANNEL

1
2
3

C42
SCD1U

AAT4280IGU-3-T1

SB 0202

DCBATOUT

LCD_TXBCLK+ 13,54
LCD_TXBCLK- 13,54
LCD_TXBOUT2+ 13,54
LCD_TXBOUT2- 13,54
LCD_TXBOUT1+ 13,54
LCD_TXBOUT1- 13,54
LCD_TXBOUT0+ 13,54
LCD_TXBOUT0- 13,54
LCD_TXACLK+ 13,54
LCD_TXACLK- 13,54
LCD_TXAOUT2+ 13,54
LCD_TXAOUT2- 13,54
LCD_TXAOUT1+ 13,54
LCD_TXAOUT1- 13,54
LCD_TXAOUT0+ 13,54
LCD_TXAOUT0- 13,54

Layout 40 mil

SCD1U

SC1U10V3KX
2

34 BRIGHTNESS
34 FPBACK

DY

LCD POWER

C38

13,49 EDID_CLK
13,49 EDID_DAT

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C37

2
3D3V_S0

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
41

C39

LCD1

42
2

SCD1U

SC 0310

LCDPOWER_S0

SC10U10V5ZY
2
1

LCD CONN

C43
SC1U10V3KX

<Variant Name>

JST-CONN40A-2

Wistron Corporation

20.F0439.040

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
1ST 20.F0687.040 - 2ND 20.F0439.040
Title

LCD / LEDs
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

17

of

58

5V_S5

21,34,38,39,43,44,55,57

SCD1U16V

3D3V_S0

TP72
TP71

SB_CPUSTP#
SB_PCISTP#
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

13

U2D

11

RSTDRV#_R

1 R13

2
33R2

RSTDRV#_5 25

26
26,31
26
29

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

X1

B1

X2

PCIRST# 3V to 5V level shift for HDD & CDROM

PLT_RST#_R

2
TSLCX08-U

7
1

R368 2
33R2

13 ALLOW_LDTSTOP
6 SB_CPUPWRGD

H_DPRSLP#

CPU_PG
INTR/LINT0
NMI/LINT1
INIT#
SMI#
SLP#/LDT_STP#
IGNNE#
A20M#
FERR#
STPCLK#/ALLOW_LDTSTP
LDT_PG/SSMUXSEL/GPIO0
DPRSLPVR
BMREQ#
LDT_RST#

SB400-1
6

PCI_RST#

R366 2
10R3

LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#

AG25
AH25
AJ25
AH24
AG24
AH26
AG26

SERIRQ

AK27

RTCCLK
RTC_IRQ#/ACPWR_STRAP

C2
F3

VBAT
RTC_GND

A2
A1

RTC_AUX_S5_1

PCIRST_BUF# 15,26,28,29,31,57
RTC2

SC 0228

EC91
SC470P50V2KX

SRN10K-2

SRN10K-2

SRN10K-2

21.D0010.103

8
7
6
5

SRN10K-2

PCI_CBE#0 26,29,31
PCI_CBE#1 26,29,31
PCI_CBE#2 26,29,31
PCI_CBE#3 26,29,31
PCI_FRAME# 26,29,31
PCI_DEVSEL# 26,29,31
PCI_IRDY# 26,29,31
PCI_TRDY# 26,29,31
PCI_PAR 26,29,31
PCI_STOP# 26,29,31
PCI_PERR# 26,29,31
PCI_SERR# 26,29,31
PCI_REQ#0 31
PCI_REQ#1 26
PCI_REQ#2 29

PCI_GNT#0 31
PCI_GNT#1 26
PCI_GNT#2 29

PCI_GNT#3
PCI_GNT#4
PCI_GNT#5
PCI_GNT#6

TP105
TP104
TP106
TP107

PM_CLKRUN# 26,29,31,34,37
RTC_AUX_S5

PCI_LOCK#

SC 0310

34,37

R362
1KR2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

DY

EC61
SC470P50V2KX
SC 0308
3D3V_S0

RTC_AUX_S5_1

Pull up 100k to 3D3V_S0

LPC_LFRAME# 34,37
LPC_LDRQ0# 37

LPC_LDRQ1#

P_SERIRQ 26,34,37

Close to chip

3D3V_AUX_S5

RTC_CLK 22
AUTO_ON# 22
VBAT

P_SERIRQ

1 R326

2
10KR2
2
10KR2
LPC_LDRQ0#1 R327
2
10KR2
LPC_LDRQ1#1 R306

DY

RTC1 SCON3

21.D0010.103
ME : 21.D0010.103
SC 0310

3
C561

U47
BAT54C-U

<Variant Name>

SC1U10V3KX
RTC_AUX_S5

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-SB400 (1 of 5) PCI, PCIE


Size
A3
SC 0310

Document Number

Rev

Bolsena

Date: Thursday, March 31, 2005


A

RN74
LPC_LAD0 1
LPC_LAD3 2
LPC_LAD2 3
LPC_LAD1 4

SRN10K-2

PCI_REQ#3
PCI_REQ#4
PCI_REQ#5
PCI_REQ#6

C565

C587
DUMMY-C2

Secondary PCI Bus reset signal.


SCON3

C592
DUMMY-C2

3D3V_S0

TSLCX08-U

4
PCIRST#

SB_B30
H_A20M#
H_FERR#

C29
A28
C28
B29
D29
E4
B30
F28
E28
E29
D25
E27
D27
D28

CHANGE TO 71.SB400.D0U (VER A32)

U51B

14

TP91

13 BMREQ#
6,13 LDT_RST#

3D3V_S5
R367
8K2R2

6,13 LDT_STP# TP67


LPC_RST# 13,34,37
TP93
TP92

SB_C29
SB_A28
H_NMI
FWH_INIT#
SB_D29

1
2
3

14

U51A

1
A_RST#

SB400 asserts PLTRST# to reset


devices on the platform.

TP66
TP64
TP94
TP65
TP68

RN79

LPC_LAD[0..3]

CPU

3D3V_S5

RN77

32K_X2

B2

XTAL

32K_X1

TSAHCT125

CPU_STP#/DPSLP#
PCI_STP#
INTA#
INTB#
INTC#
INTD#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

AJ8
AK7
AG5
AH5
AJ5
AH6
AJ6
AK6
AG7
AH7

RN80

1
R403
8
7
6
5

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15

H28
F29
H29
H26
F27
G29
L29
J26
L28
J27
N27
M26
K27
P29
P30

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8
PCIE_VDDR_9

1
SCD1U16V

C482

INT_PIRQG#
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#

SRP10K

F26
R29
G26
P26
K26
L26
P28
N26
P27

C593
DUMMY-C2

RN78

5V_S0

10
9
8
7
6

C483

DY

PCIE_PVDD

3D3V_S0

1
2
3
4
5

DY

R30

C584
DUMMY-C2

3D3V_S0

RP4
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQH#

C450

PCIE_CALI

1
2
3

PCIE_PVDD

PCIE_CALRP
PCIE_CALRN

G28

C585
DUMMY-C2

4K12R2F PCIE_CALI

C591
DUMMY-C2

8
7
6
5

G27
H27

CLK33_CBUS 26
CLK33_LAN 22,29
CLK33_MINI 22,31
CLK33_KBC 22,34
CLK33_SIO 22,37
CLK33_LPCROM 22

DY

1 R303

1
2

C486
SCD1U16V

DY

C475
SC10U10V5ZY

1
2

SC 0308

12

PCIE_CALRP
PCIE_CALRN

PCIE_VDDR

1 L15
2
0R0603-PAD

14

150R2F
150R2F

A11, A12 4K53 1%


A21, A22 5K5 1%
A23 4K12 1%
PA_IXP400AC10.PDF

1D8V_S0

A_RST#

2
2

22,26,29,31

1
2
3
4

SCD1U16V

C485

1 R304
1 R305

C480

SC10U10V5ZY

C479

MLB-201209-11

SC1U10V3KX

PCIE_VDDR

2 C588
SC100P50V2JN

CLK32_G791 23

CLK33_CBUS
CLK33_LAN
CLK33_MINI
CLK33_KBC
CLK33_SIO
CLK33_LPCROM

PCI_CLK7 22
PCI_CLK8 22

PCI_AD[31..0]

R349 2
10R3

TSAHCT08-U

8
7
6
5

L16

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
CBE3#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR/ROMA19
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/PDMA_REQ0#
REQ4#/PLL_BP33/PDMA_REQ1#
REQ5#/GPIO13
REQ6#/GPIO31
GNT0#
GNT1#
GNT2#
GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#
GNT5#/GPIO14
GNT6#/GPIO32
CLKRUN#
LOCK#

2
22R2

1
2
3
4

1D8V_S0

EPSON
KDS

M29
N29
M28
N28
J29
K29
J28
K28

1 R399

CLK33_CBUS
CLK33_LAN
CLK33_MINI
CLK33_KBC
CLK33_SIO
CLK33_LPCROM

8
7
6
5

MAIN SOURCE: 82.30001.031


2ND SOURCE: 82.30001.341

PCIE_PVDD

SCD1U16V

32K_X2

PCIE_TX0P_SB
PCIE_TX0N_SB
PCIE_TX1P_SB
PCIE_TX1N_SB

PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

R400
R397
R396
R402
R401
R398

2 C566
SC12P50V2JN-1
CHANGE TO - 3.9P -> 78.3R974.1F1
SB

12
12
12
12

PCI_CLK9_R
PCI_CLK9_FB

2
2
2
2
2
2

32K_X1

AJ7
W3
Y2
W4
Y3
V1
Y4
V2
W2
AA4
V4
AA3
U1
AA2
U2
AA1
U3
T4
AC1
R2
AD4
R3
AD3
R4
AD2
P2
AE3
P3
AE2
P4
AF2
N1
AF1
V3
AB4
AC2
AE4
T3
AC4
AC3
T2
U4
T1
AB2
AB3
AF4
AF3
AG2
AG3
AH1
AH2
AH3
AJ2
AK2
AJ3
AK3
AG4
AH4
AJ4
AG1
AB1

22R2
22R2
22R2
22R2
22R2
22R2

20MR3

XTAL-32D768K-4P

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

1
1
1
1
1
1

SCD1U16V
2

SC 0307

M30
N30
K30
L30
H30
J30
F30
G30

PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R
PCI_CLK6_R

TX0P
TX0N
TX1P
TX1N

3
2

22 RTC_CLK

SCD01U16V2KX
SCD01U16V2KX
SCD01U16V2KX
SCD01U16V2KX

PCI CLKS

2
2
2
2

X5

1
1
1
1

Part 1 of 4

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK8
PCICLK9
PCICLK_FB

PCI INTERFACE

R381
20MR3

C478
C481
C476
C477

PCIE_RX0P_SB
PCIE_RX0N_SB
PCIE_RX1P_SB
PCIE_RX1N_SB

PCIE_RCLKP
PCIE_RCLKN

LPC

R382

12
12
12
12

A_RST#

L27
M27

RTC

3 SBSRC_CLK
3 SBSRC_CLK#

CHANGE TO - 3.9P -> 78.3R974.1F1


2 C579
SC12P50V2JN-1

SB400 SB

AH8

PCI EXPRESS INTERFACE

A_RST#

L4
L3
L2
L1
M4
M3
M2
M1
N4
N3
N2

1
2
3
4

U43A

PM_SLP_S3#

2
8K2R2
1
2
3
4

R365
8K2R2

?3.9p need app PN

U44A

14

32K suspend clock output

-1
Sheet
E

18

of

58

SC 0308
U43B
4

2 C622
2 C621

SCD01U50V3KX SATA_RN0 AK21


SCD01U50V3KX SATA_RP0 AJ21

SATA_RX0SATA_RX0+

AK19
AJ19

SATA_TX1+
SATA_TX1-

Close to SouthBridge

Close to SouthBridge
R342 2
1
1KR2F
1
2 C542
SCD01U50V3KX

17 SATA_LED#

2
1

SATA_X1

AK11
AJ11

SATA_TX3+
SATA_TX3-

AK10
AJ10

SATA_RX3SATA_RX3+

SATA_X1

SATA_X2

AK16

SATA_X2

AK8

1D8V_SP_S0

Dummy when use IDE

1D8V_SATA_S0
SATA_X1

SATA_RX2SATA_RX2+

SATA_CAL

X-25MHZ-11-U
1
2 C544
SC27P50V2JN

R328
0R2-0

SATA_TX2+
SATA_TX2-

AK13
AJ13

AJ16

X4

R344
0R2-0

SATA_RX1SATA_RX1+

AK14
AJ14

AJ15

1D8V_SATA_S0
2 C545
SC27P50V2JN

AK18
AJ18

SATA_X1

Dummy when use SATA

SB400 SB
Part 2 of 4

SATA_ACT#

AH15

PLLVDD_SATA

AH16

XTLVDD_SATA

AG10
AG14
AH12
AG12
AG18
AG21
AH18
AG20

AVDD_SATA_1
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_4
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
AVDD_SATA_8

AG9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AH9
AG11
AG15
AG17
AG19
AG22
AG23
AF9
AH17
AH23
AH13
AH20
AK9
AJ12
AK17
AK23
AH10
AJ23

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVSS_SATA_21
AVSS_SATA_22
AVSS_SATA_23
AVSS_SATA_24
AVSS_SATA_25
AVSS_SATA_26
AVSS_SATA_27
AVSS_SATA_28
AVSS_SATA_29
AVSS_SATA_30
AVSS_SATA_31
AVSS_SATA_32

1D8V_SX_S0

SATA_X2

SATA_TX0+
SATA_TX0-

PRIMARY ATA 66/100

1
1

SCD01U50V3KX SATA_TP0 AK22


SCD01U50V3KX SATA_TN0 AJ22

PIDE_IORDY
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DACK#
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#

AD30
AE28
AD27
AC27
AD28
AD29
AE27
AE30
AE29
AC28
AC29

PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

AF29
AF27
AG29
AH30
AH28
AK29
AK28
AH27
AG27
AJ28
AJ29
AH29
AG28
AG30
AF30
AF28

SIDE_IORDY
SIDE_IRQ
SIDE_A0
SIDE_A1
SIDE_A2
SIDE_DACK#
SIDE_DRQ
SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#

SECONDARY ATA 66/100

25 SATA_RXN0
25 SATA_RXP0

2 C515
2 C516

SERIAL ATA

1
1

SERIAL ATA POWER

25 SATA_TXP0
25 SATA_TXN0

PIDE_IORDY 25
PIDE_IRQ14 25
PIDE_A0 25
PIDE_A1 25
PIDE_A2 25

R463

0R0402-PAD

PIDE_DACK# 25
PDACK# 22

PIDE_DREQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS#0
PIDE_CS#1
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

25
25
25
25
25

also strap function

PIDE_D[15..0]

25

V29
T27
T28
U29
T29
V30
U28
W29
W30
R27
R28

SIDE_IORDY 25
SIDE_IRQ15 25
SIDE_A0 25
SIDE_A1 25
SIDE_A2 25
SIDE_DACK# 25
SIDE_DREQ 25
SIDE_IOR# 25
SIDE_IOW# 25
SIDE_CS#0 25
SIDE_CS#1 25

SIDE_D0/GPIO15
SIDE_D1/GPIO16
SIDE_D2/GPIO17
SIDE_D3/GPIO18
SIDE_D4/GPIO19
SIDE_D5/GPIO20
SIDE_D6/GPIO21
SIDE_D7/GPIO22
SIDE_D8/GPIO23
SIDE_D9/GPIO24
SIDE_D10/GPIO25
SIDE_D11/GPIO26
SIDE_D12/GPIO27
SIDE_D13/GPIO28
SIDE_D14/GPIO29
SIDE_D15/GPIO30

V28
W28
Y30
AA30
Y28
AA28
AB28
AB27
AB29
AA27
Y27
AA29
W27
Y29
V27
U27

AVSS_SATA_33
AVSS_SATA_34
AVSS_SATA_35
AVSS_SATA_36
AVSS_SATA_37
AVSS_SATA_38
AVSS_SATA_39
AVSS_SATA_40
AVSS_SATA_41
AVSS_SATA_42
AVSS_SATA_43
AVSS_SATA_44
AVSS_SATA_45

AG13
AH22
AK12
AH11
AJ17
AH14
AH19
AJ20
AH21
AJ9
AG16
AK15
AK20

SIDE_D0
SIDE_D1
SIDE_D2
SIDE_D3
SIDE_D4
SIDE_D5
SIDE_D6
SIDE_D7
SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15

SIDE_D[15..0]

25

SB400-1

CHANGE TO 71.SB400.D0U(VER A32)

L19

2
0R3-U

SCD1U50V5ZY

1D8V_S0

C540

1
2

C543
SCD1U50V5ZY

1
C518

C541

SCD1U50V5ZY

C546

SCD1U50V5ZY

1D8V_SP_S0

C548
SC2D2U16V5ZY

1D8V_SX_S0

L20

2
0R3-U

<Variant Name>

1D8V_S0

R343 2
0R5J-1

SC10U10V5ZY

1D8V_SATA_S0

1D8V_S0

C547
SC2D2U16V5ZY

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Capacitor PLACE NEAR Capacitor PLACE NEAR


THE ACCORDED BALLS
THE ACCORDED BALLS

ATI-SB400 (2 of 5) IDE
Size
A3

Dummy when use IDE

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

19

of

58

1D8V_S0

2
1
2

SCD1U16V

SCD1U16V

C489

DY

DY

3D3V_SB_S0

SC 0308

SCD1U16V

C567

SCD1U16V

C594

SCD1U16V

SCD1U16V

C586

1
C491

SCD1U16V

C514

C590
SCD1U16V

SC10U10V5ZY

C595

3D3V_S0
R404 1
2
0R0805-PAD

1D8V_S0

DY

DY

SCD1U16V

1
C471

C589
SCD1U16V

1
2

SCD1U16V

1
C488

C597
SCD1U16V

1
2

SCD1U16V

C473

DY

SCD1U16V

C569

SCD1U16V

SCD1U16V

C470

1
C517

SCD1U16V

C490

SCD1U16V

C487

SCD1U16V

C568

DY

DY

3D3V_SB_S5

3D3V_SB_S5

1D8V_S5
SC 0308

SCD1U16V

C578

C558
SCD1U16V

DY

C582
SCD1U16V
2

1
2

SCD1U16V

1D8V_S5

3D3V_S5
1D8V_S5

2
RB751V-40-U

1D8V_S5

1D2V_S0

1D8V_S5

SC 0308
1 R302
2
0R0402-PAD

RB751V-40-UNORMAL

DY
2
1KR2

V5_VREF

RB751V-40-U

C596

2
2

SC1U10V3KX

C598
D17

SCD1U16V

1 R405
3D3V_S0

5.0

MAX 5.5

Vf = 0.38v (@1mA)
1v (@40mA)

2
1

V5_VREF
MIN 4.5

D18

DY

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6

E9
E10
E20
E21

S5_1.8V_1
S5_1.8V_2
S5_1.8V_3
S5_1.8V_4

E13
E14
E16
E17

USB_PHY_1.8V_1
USB_PHY_1.8V_2
USB_PHY_1.8V_3
USB_PHY_1.8V_4

CPU_1D2V C30

C510
C508
C513
SC10U10V5ZY
SC1U10V3KX
SCD1U16V

Part 3 of 4

CPU_PWR

V5_VREF AG6

V5_VREF

A24
B24

AVDDCK
AVSSCK

C472
A4
SCD1U16VA8
A29
B28
C1
E5
E8
E11
E12
E15
E18

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11

VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

E19
E22
E23
E26
E30
F1
F4
G5
H5
J1
J4
K4
L5
M5
P1
R5
R26
T5
T26
T30
W1
W5
W26
Y5
AB26
AB30
AC5
AC26
AD1
AF5
AF8
AF23
AF26
AG8
AJ1
AJ24
AJ30
AK5
AK25
M14
M15
M16
M17
N14
N15
N16
N17
P12
P13
P14
P15
P16
P17
P18
P19
R12
R13
R14
R15
R16
R17
R18
R19
T12
T13
T14
T15
T16
T17
T18
T19
U12
U13
U14
U15
U16
U17
U18
U19
V14
V15
V16
V17
W14
W15
W16
W17

SCD1U16V

5V_S0

1D8VAVDDCK_S0
2
MLB-201209-11

L17

C560

SCD1U16V

C537

SCD1U16V

1
C512

SCD1U16V

SCD1U16V

C539

DY

DY

DY

C562

SCD1U16V

C564

SCD1U16V

C532

SC10U10V5ZY

C559

1D8V_S0

SB400 SB

A3
A7
E6
E7
E1
F5

D16

DY

C563

C583
SCD1U16V

DY

SC10U10V5ZY

C581

3D3V_S5
R383 1
2
0R0805-PAD

M12
M13
M18
M19
N12
N13
N18
N19
V12
V13
V18
V19
W12
W13
W18
W19

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34

POWER

1
C506
SCD1U16V

C549

C468

U43C

A30
D30
E24
E25
J5
K1
K5
N5
P5
R1
U5
U26
U30
V5
V26
Y1
Y26
AA5
AA26
AB5
AC30
AD5
AD26
AE1
AE5
AE26
AF6
AF7
AF24
AF25
AK1
AK4
AK26
AK30

DY

DY

SCD1U16V

SCD1U16V

DY

SCD1U16V

SCD1U16V

C474

1
C519

SCD1U16V

C509

SCD1U16V

SCD1U16V

C469

C484

DY

DY

C451

1
C550

C529

SCD1U16V

SC10U10V5ZY

DY

C505

2
4

SC10U10V5ZY

C507

SCD1U16V

3D3V_SB_S0

SB400-1
CHANGE TO 71.SB400.D0U(VER A32)
<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-SB400 (3 of 5) POWER
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

20

of

58

R384
R378
R379
R386

RN72

8
7
6
5

R324
R325

3D3V_S5

SC 0303

DY DY

SC 0308

3D3V_S5

TP103
24,32 AC97_SYNC
24,32 AC97_RST#
22 SPDIF_OUT_STRAP

R395

2
33R2

AC_BITCLK
AC_SDOUT
AC97_DIN2
AC_SYNC

G1
G2
H4
G3
G4
H1
H3
H2

AC_BITCLK
AC_SDOUT
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_SYNC
AC_RST#
SPDIF_OUT

R393
680R2

AC97_RST#

3D3V_S0

C21
C18
D13
D10
D20
D17
C14
C11

AVDD_USB

AVDDC

A16

3D3V_AVDDC

AVSSC

B16

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

A9
A12
A19
A22
B9
B12
B19
B22
C9
C10
C12
C13
C17
C19
C20
C22
D9
D11
D12
D14
D18
D19
D21
D22

1 L21
2
0R0603-PAD
SC 0308

C580

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3

C530

C536

C531

2
SCD1U16V

USB_PP0 24
USB_PN0 24

A20
B20

USB_HSDP0+
USB_HSDM0-

AVDD_USB
3D3V_S5

SCD1U16V

USB_PP1 24
USB_PN1 24

A21
B21

USB_HSDP1+
USB_HSDM1-

SB 0201

SCD1U16V

USB_PP2 24
USB_PN2 24

DY

DY

C533
SC10U10V5ZY

C538

3D3V_AVDDC
L18
1
2
MLB-201209-11

C527
C528
C535
SC10U10V5ZY
SC1U10V3KX
SCD1U16V

DY

SB400-1
CHANGE TO 71.SB400.D0U(VER A32)

1
1
R262
2K2R2

A17
B17

AC97_BITCLK_SB
AC97_DOUT
AC97_DIN0
AC97_DIN1

R394 2 0R0402-PAD
1 R392
2 33R2

AC97

32
22,24,32
32
24

USB PWR

DDC1_SCL
DDC1_SDA
DDC2_SCL
DDC2_SDA

NC1
NC4
NC3
NC2

(NOT USED)

J2
K3
J3
K2

USB_HSDP2+
USB_HSDM2-

BlueTooth

SMBC_SB_1
SMBD_SB_1
DDC1_SCL
DDC1_SDA
DDC2_SCL
DDC2_SDA

ROM_CS#/GPIO1
GHI#/GPIO6
VGATE/GPIO7
AGP_STP#/GPIO4
AGP_BUSY#/GPIO5
FANOUT0/GPIO3
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
DDC2_SCL/GPIO11
DDC2_SDA/GPIO12

USB_PP3 24
USB_PN3 24

SCD1U16V

2 33R2
2 33R2

B25
C25
C23
D24
D23
A27
C24
A26
B26
B27
C26
C27
D26

USB_HSDP3+
USB_HSDM3-

1 R321
1 R322

8
7
6
5

SMBC_SB
SMBD_SB

AGP_STP#
AGP_BUSY#

1
2
3
4

SRN10K-2

1 R301
1 R300

USB_PP4 24
USB_PN4 24

A18 USB_PP3
B18 USB_PN3

34 KBC_SLP_WAKE
32 SPKR_SB

3D3V_S0

RN73

DY

GPIO1
GPIO6
39,41 VRM_PWRGD
10KR2
2
10KR2
2

A13 USB_PP4
B13 USB_PN4

SB 0201

TP96
TP97

DY

1
0R2-0

USB_HSDP4+
USB_HSDM4-

SRP10K

SB 0202

3D3V_S5
R339

SIO_CLK

USB_HSDP5+
USB_HSDM5-

3D3V_S5
LUSB1# 57

3D3V_S5
10
9 USB_OC#5
LUSB1#
8
7
6 USB_OC#6

1
2
3
4
5

TP95

AK24

TP114
TP115

A14 USB_PP5
B14 USB_PN5

RP3
USB_OC#01
USB_OC#2
USB_OC#4
USB_OC#3

14M_X2

A10 USB_PP6
B10 USB_PN6

14M_X1/OSC

B23

1
2
DY 0R2-0
SB 0211
A15
B15
USB_PCOMP
1 R337
2
C15
11K8R3F
USB_VREFOUT TP102
D16
USB_TE1
TP101
C16
USB_TE0
TP100
D15
B8
USB_OC#01 24
C8
USB_OC#2
C7
USB_OC#2 24
USB_OC#3
B7
USB_OC#3 24
USB_OC#4
B6
SC 0308
USB_OC#5
A6
USB_OC#6 1 R361
2 ECSWI#
B5
SB_LUSB1#
0R0402-PAD
R744 2
1
A5
1KR2
TP70
A11 USB_PP7
TP69
B11 USB_PN7

DY

DY

A23

XO_CLK_SB14_1
SIO_CLK_SB

XO_CLK_SB14
2 C534
SC33P50V2JN

RSMRST#

X1_CLK_SB14_1

R338
1MR2

X-14D318MHZ-1-U1

48M_X1/USBCLK
TALERT#/TEMP_ALERT#/GPIO10
48M_X2
BLINK/GPM6#
USB_RCOMP
PCI_PME#/GEVENT4#
USB_VREFOUT
RI#/EXTEVNT0#
USB_ATEST1
SLP_S3#
USB_ATEST0
SLP_S5#
USB_OC0#/GPM0#
PWR_BTN#
USB_OC1#/GPM1#
PWR_GOOD
USB_OC2#/FANOUT1/GPM2#
SUS_STAT#
USB_OC3#/GPM3#
TEST1
USB_OC4#/GPM4#
TEST0
USB_OC5#/GPM5#
GA20IN
USB_OC6#/FAN_ALERT#/GEVENT6#
KBRST#
USB_OC7#/CASE_ALERT#/GEVENT7#
SMBALERT#/THRMTRIP#/GEVENT2#
LPC_PME#/GEVENT3#
USB_HSDP7+
LPC_SMI#/EXTEVNT1#
USB_HSDM7VOLT_ALERT#/S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
USB_HSDP6+
WAKE#/GEVENT8#
USB_HSDM6-

1
0R2-0

DY

DY X3

R318

Part 4 of 4

USB INTERFACE

XI_CLK_SB14
2 C511
SC33P50V2JN

1
Use CLK GEN REF
14.318M CLK to SB
OSCIN
DUMMY IT

SB400 SB

ACPI / WAKE UP EVENTS

2
10KR22
10KR2

3 SB_OSC_CLK
13 SB_OSC_INT

R341

SC10U10V5ZY

U43D

GPIO

1
2
3
4

1
1
1
1

R317
R363 1
1

KBC_SLP_WAKE
GPIO1
GPIO6

CLK / RST

1
2
3
4

1
2
3
4
SRN4K7

SRN10K-2

C6
23 PM_THRM#
GPM6#
D5
C4
29,34
PME#_SB
SRN4K7
RI#
RI#
D3
S3_STATE
PM_SLP_S3#_SB
B4
PM_SLP_S5#
LUSB2#
E3
34,44,57
PM_SLP_S5#
SB 0202
PCIE_WAKE#
PM_SUS_STAT#
B3
34
PM_PWRBTN#
PME#_SB
KA20GATE
C3
39 SB_PWRGD
PM_SLP_S3#_SB
KBRCIN#
D4
34,37 PM_SUS_STAT#
GPM6#
ECSCI#_KBC
R390
10KR2
1
2
F2
SYS_REST
ECSMI#_KBC
1 R388 2 10KR2
E2
PM_PWRBTN#
AJ26
34 KA20GATE
PM_THRM#
AJ27
34 KBRCIN#
R743 2 1KR2
SB_LUSB2#
1
D6
57 LUSB2#
R364 2 0R0402-PAD
ECSCI#
1
C5
34 ECSCI#_KBC
SB 0202
SC 0308
R320 2 0R0402-PAD
ECSMI#
1
A25
34 ECSMI#_KBC
ECSWI#
R380
0R2-0
S3_STATE
1
2
D8
34
ECSWI#
SYS_REST
1 R323
2
D7
DY
0R0402-PAD
PCIE_WAKE#
1 R319 2
D2
0R2-0 DY
SC 0308
D1
34,46 RSMRST#_KBC
1
1

RN76

2
10KR22
10KR2
2
10KR22
10KR22
10KR22
10KR2

8
7
6
5

8
7
6
5

CLK48_USB 3
RN75

R259
2K2R2

2
2

3D3V_S5

U22C

14
1

SMBC_SB
SMBD_SB

<Variant Name>

9
PM_SLP_S3#_SB

8
10

PM_SLP_S3# 18,34,38,39,43,44,55,57

Wistron Corporation

TSLCX08MTC-U

3,8 SMBC_SB
3,8 SMBD_SB

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-SB400 (4 of 5) USB GPIO


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

21

of

58

3D3V_S0

3D3V_S0

R436
10KR2

R432
10KR2

R433
10KR2

R438
10KR2

R439
10KR2

3D3V_S0

3D3V_S0

R428
10KR2

DY

3D3V_S0

R429
10KR2

DY

DY

DY

SIO 48MHz

48MHZ
-Crytsal Pad

USB PHY
PWRDOWN
ENABLE

USB
EXT.
48MHZ

DY

PCI_CLK6

PCI_CLK5

PCI_CLK7

CPU I/F=K8

H,H=PCI (X Bus) ROM

DEFAULT

H,L=LPC ROM I

DEFAULT

14MHZ
XTAL
MODE

L,L=Firmware Hub ROM

R642
10KR2

3D3V_S0

1
R621
10KR2

3D3V_S0

R622
10KR2

R640
10KR2

PDACK#
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

R644
10KR2

3D3V_S0

L,H=LPC ROM II

CPU I/F=P4

R625
10KR2

3D3V_S0

PCI_CLK8

ROM TYPE

14MHZ
OSC
MODE

R646
10KR2

3D3V_S0

3D3V_S0

3D3V_S0

R435
10KR2

DY

DY

USB INT
PLL48
DEFAULT

R431
10KR2

PCI_CLK4

DEFAULT

PCI_CLK3
USB PHY
PWRDOWN
DISABLE

R434
10KR2

DEFAULT

R628
10KR2

R647
10KR2

PCI_CLK2
48MHZClock
Input
Buffer
DEFAULT

EXTENNAL
RTC (NOT
SUPPORTED
W/IT8712)

3D3V_S0

1
2

SIO 24MHz
INTERNAL RTC

3D3V_S0

R462
10KR2

SPDIF_OUT

IGNORE
DEBUG
STRAPS
DEFAULT

3D3V_S0

DY

DEFAULT

AUTO
PWR
ON

STRAP
LOW

R437
10KR2

SB400 version A31/A32


not the same!

RTC_CLK

DEFAULT

R440
10KR2

USE DEBUG
STRAPS

R427
10KR2

MANUAL
PWR ON

STRAP
HIGH

AC_SDOUT

R430
10KR2

DY

ACPWRON

R425
10KR2

REQUIRED SYSTEM STRAPS

R387
10KR2

R423
10KR2

DY

DY

DY

DY

DY

DY

1
R639
10KR2

DY

R623
10KR2

DY

R641
10KR2

DY

R624
10KR2

DY

R643
10KR2

DY

R626
10KR2

R645
10KR2

R627
10KR2

R648
10KR2

R464
1KR2

3D3V_S0

Place these R close to


SouthBridge if possible

R389
10KR2

19
18,26,29,31
18,26,29,31
18,26,29,31
18,26,29,31
18,26,29,31
18,26,29,31
18,26,29,31
18,26,29,31
18,26,29,31

3D3V_S0

R426
10KR2

R385
10KR2

DY

AUTO_ON#
AC97_DOUT
RTC_CLK
SPDIF_OUT_STRAP
CLK33_LAN
CLK33_MINI
CLK33_KBC
CLK33_SIO
CLK33_LPCROM
PCI_CLK7
PCI_CLK8

3D3V_S0

R424
10KR2

R391
10KR2

18
21,24,32
18
21
18,29
18,31
18,34
18,37
18
18
18

3D3V_S5

C
3D3V_S0

B
3D3V_S5

DEBUG STRAPS

PDACK#

STRAP
HIGH

USE LONG
RESET

PCI_AD31

RESERVED

PCI_AD30

RESERVED

PCI_AD29

RESERVED

PCI_AD28

RESERVED

PCI_AD25

PCI_AD24

PCI_AD27

PCI_AD26

BYPASS
PCI PLL

BYPASS IDE PLL USE


BYPASS ACPI BCLK
EEPROM
PCIE
STRAPS

PCI_AD23
RESERVED
<Variant Name>

DEFAULT

STRAP
LOW

USE SHORT
RESET

Wistron Corporation
USE PCI
PLL

USE ACPI
BCLK

DEFAULT

DEFAULT

USE
IDE
PLL
DEFAULT

USE
DEFAULT
PCIE
STRAPS

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-SB400 STRAPPING(5 of 5)

DEFAULT
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet

22

of

58

FAN1_VCC

C213
SC10U10V5ZY

C215
SC2200P50V2KX

S1N4148-U

*Layout* 15 mil
FAN1_VCC

R137
10KR2
FAN1

1
C214
SCD1U

5V_S0
D10

1
2

*Layout* 15 mil

1
2
3

FAN1_FB

CON3-4
20.D0012.103
C161
SC1000P50V2KX

ME : 20.D0012.103

*Layout* 30 mil
5V_S0

U21

DGND
DGND

5
17

SGND1
SGND2
SGND3

8
10
12

THERMDN 6

THERM_SYS_DP

C250
SC2200P50V2KX

PM_THRM# 21

DY

DY

RN119

DY

T8_RSET:27K SET TO 80C


T8_RSET:20K SET TO 90C
T8_RSET:15K SET TO 100C

5V_AUX_S5

R202
150R2F

5
4

VGA_LOCAL_DP 49,54
VGA_LOCAL_DN 49,54

5V_G709_AUX_S5

G709T1U

Dummy when use UMA

By Sourcer requset:
Main souce 74.00709.07F
Second souce
74.00710.03P
74.06509.07F
74.06510.A7P

VCC
HYST

2
1

C270
SC4D7U10V5ZY

R201
20KR2F

SET
GND
OUT#

1
2
3

To VGA
place back side of GPU

SRN0-2-U

U23
T8_SET

SC 0311

Put RN near thermal diode

3
4

Dummy when G792 enhanced T8 function

3904 on system
(Thermal Sensor)

3
1
2

VGA_THERM_DN

R157 2
0R2-0

Q31
MMBT3904-U1

SC470P50V2KX

Q27
1
MMBT3904-U1
C716
SC470P50V2KX

G13
GAP-CLOSE

G12

ALERT#

VGA_THERM_DP
C219
SC2200P50V2KX
USE 0R2 63.R0034.1D1 WHEN UMA

DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree

V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC

C306

1
THERM_SYS_DN

G792SFX

SB

ALERT#
THERM#
THERM_SET
RESET#

THERMDP 6

To CPU

C249
SC2200P50V2KX

15
13
3
2

CLK32_G791 18
SMBD_G792 34
SMBC_G792 34

DXP1
DXP2
DXP3

1
4
14
16
18
19

SD 0325

R179
10KR2

DY

HW thermal shut down tempature


setting 95 degree . Put Near CPU .

7
9
11

FAN1
FG1
CLK
SDA
SCL
NC

1
R180
49K9R2F

ALERT#
PR_HW_SDN#

2 G792_RST#
R178 0R2-0

VCC
DVCC

DY

39 RUNPWROK

Setting T8 as
100 Degree

R158
10KR2

6
20

C218

1
C217

SCD1U

V_DEGREE

C216

SCD1U
2

SB 0307

R182
10KR2

SC4D7U10V5ZY
2

5V_S0

5V_G792_S0

C248
SCD1U

GAP-CLOSE

R181 2
200R3

5V_S0

Put under CPU Socket


3D3V_AUX_S5

PURE_THRM_SDN#

D43

6 CPU_THERMTRIP#

D38

RSMRST# 34

R611
10KR2

3D3V_AUX_S5

U77

BAW56

BAW56

34 S5_ENABLE

GND

VCC

<Variant Name>

Wistron Corporation

C782
SCD1U16V

DY

DY

NC7S08-U
Title

D39

(dummy, KBC already delay)


48 LOW3_OFF

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

S5PWR_ENABLE 43,44

THERMAL G792

BAT54-1

SD 0324

Size
Document Number
Custom

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet

23

of

58

100 mil

5V_USB0_S0

5V_USB1_S0

USB PORT

5V_USB0_S0

5V_USB0_S0

G5258B2 Active Low 1.5A

5V_USB1_S0

USB_0USB_0+

SB 0127

2
3
4
5

DY

C956

L-63UH

C957

G5258B2

TR4

USB_OC#2 21

R735
1KR2 2
1

USB2

6
1

USB_OC#01 21

8
7
6
5

OC1#
OUT1
OUT2
OC2#

SCD1U

100 mil

34 USB_PWR_EN#

GND
VCC
EN1#/EN1
EN2#/EN2

R734
1KR2 2
1

SCD1U

SE150U10VM

C812
SC1000P50V2KX

C836
SCD1U

TC24

1
2
3
4

USB_0-

21 USB_PN0

U90

5V_S5

68.03216.20B

SKT-USB-97-U

22.10218.H01

USB_0+

21 USB_PP0

SB 0127
D52
SSM5817-U

5V_S5

R736 1

G528P1U

SB 0127

TR5

SKT-USB-97-U

L-63UH

68.03216.20B

22.10218.H01
SB 0127

USB_1+

21 USB_PP1
RN37

3
4

2
1
5V_USB1_S0

SRN0-2-U
USB_2-

21 USB_PN2

TR6

USB4

6
1

BLUETOOTH MODULE

USB_2USB_2+

3D3V_S0

U9

34 BLUETOOTH_EN

3D3V_BT_S0

IN

OUT

L-63UH

3D3V_BT_S0

GND
NC
ON/OFF#

2
3
4
5

DY
4

2
3
4

2
3
4
5

DY
4

SC1000P50V2KX

USB_1USB_1+

C958

USB_OC#3 21

C5

SCD1U

SE100U10VM

6
1

SCD1U

1KR2 2

USB3

USB_1-

21 USB_PN1

OUT
OUT
OUT
FLG

GND
IN
IN
EN#/EN

8
7
6
5

G528P1U Active Low

5V_USB0_S0

SRN0-2-U

USB_PWR_EN#
5V_USB2_S0

C6

2
1

5V_USB2_S0

U59

1
2
3
4

100 mil

TC1

3
4

SC1000P50V2KX

C846

SCD1U

RN34

C435

SE100U10VM

TC15

5V_S0

68.03216.20B

22.10218.H01

USB_2+

21 USB_PP2

AAT4250-U

SKT-USB-97-U

RN48
BLUE1

3
4

10

BT_COEX2 31
BT_COEX1 31

USB_3-

21 USB_PN3

20.D0122.108 - 2ND

MDC 1.5 CONNECTOR

USB1

SB 0131

DY

EC4

L-63UH

SKT-USB-97-U
RN88

4
6
8
10
12
17
18

TP77 TPAD30
3D3V_LAN_S5
<Variant Name>
AC97_BITCLK 32

AMP-CONN12A
2ND : 20.F0604.012

20.F0582.012

ME : 20.F0582.012
2ND : 20.F0604.012

Wistron Corporation

3
5
7
9
11
MH2
16

ME : 22.10218.H01
2ND : 22.10218.C91

TP76 TPAD30

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

15
14
2

R556
100KR2

C128
SC22P50V2JN-1

22.10218.H01

2
1
SRN0-2-U

13
MH1
1

21,32 AC97_RST#

1 AC97_DIN1_MDC
33R2

2
3
4
5

USB_3+

21 USB_PP3

MDC1

2 R105

USB_3USB_3+

68.03216.20B

3
4

21,22,32 AC97_DOUT
21,32 AC97_SYNC
21 AC97_DIN1

6
1

DY
3

MOLEX-CON8-2

TR1

5V_USB2_S0

DY
DY

EC3

2 0R2-0
2 0R2-0

USB_PN4 21
USB_PP4 21

DY

TP1
TPAD30

3D3V_BT_S0

R48
R25

1
1

SC1000P50V2KX
2

ME : 20.D0012.108
2ND : 20.D0122.108
20.D0012.108

TPAD30

SC1000P50V2KX

BT_AUX TP2
BT_GPIO2
BT_GPIO1
BT_LINK_LED

8
7
6
5
4
3
2
1

2
1
SRN0-2-U

C710
SC4D7U10V5ZY

Title

DY

USB / MDC / BLUETOOTH


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet

24

of

58

HDD
19 PIDE_D[15..0]

HDD1

PIDE_IORDY

PIDE_A2 19
PIDE_CS#1 19

ODD1

19 SIDE_D[15..0]

PWR TRACE 100mil


5V_S0

32 CD_AUDR

1
45

SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15

SPD-CONN44D-7-U1

20.80175.044
CHANGE TO 20.80592.044

ME : 20.80592.044
(DIFFERENT FROM ORCAD P/N)

Dummy when use SATA


19 SIDE_DREQ
19 SIDE_IOR#
19 SIDE_DACK#

TPAD30 TP57
TPAD30 TP58

BAY_ID0
BAY_ID1

19 SIDE_A2
19 SIDE_CS#1

SATA Connector

SC 0308

C620
SCD1U16V

2
1

B240LA

ST100U6D3VDM-5

TC19
3D3V_S0

1
SCD1U

C335

1
2

C336

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
52

CD_AUDL 32

5V_S0

CD_AGND 32

RSTDRV#_5
SIDE_D7
SIDE_D6
SIDE_D5
SIDE_D4
SIDE_D3
SIDE_D2
SIDE_D1
SIDE_D0

R212
4K7R2

SIDE_IORDY

SIDE_IOW# 19
SIDE_IORDY 19
SIDE_IRQ15 19
SIDE_A1 19
SIDE_A0 19
SIDE_CS#0 19

CDROM_LED#_5 17

R213 2
4K7R2

5V_S0

CSEL

STC-CONN50-4R

20.80251.050

PIN 49,50 DON'T USE

D20

5V_S0

C307

SCD1U

For HDD & SATA both

SC10U10V5ZY

5V_S0

TC18
ST22U6D3VBM

C624

CDROM
R465
4K7R2

5V_S0

C641

SCD1U

5V_S0
R461
4K7R2

SC10U10V5ZY
2

19 PIDE_DREQ
19 PIDE_IOW#
19 PIDE_IOR#
19 PIDE_IORDY
19 PIDE_DACK#
19 PIDE_IRQ14
19 PIDE_A1
19 PIDE_A0
19 PIDE_CS#0
17 HDD_LED#_5

5V_S0
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

PIDE_D7
PIDE_D6
PIDE_D5
PIDE_D4
PIDE_D3
PIDE_D2
PIDE_D1
PIDE_D0

46
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3

44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4

18 RSTDRV#_5

ME : 20.80251.050

C623
SCD1U

SATA1

23
MH1
1
2
3
4
5
6
7

19 SATA_TXP0
19 SATA_TXN0
19 SATA_RXN0
19 SATA_RXP0

5V_S0

PWR TRACE 100mil


1

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MH2
24

<Variant Name>

Wistron Corporation
CHANGE TO 20.F0665.022

20.F0614.022

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

ME : 20.F0665.022
(DIFFERENT FROM ORCAD P/N)

HDD / CDROM / SATA


Size
A3

Dummy when use IDE

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

25

of

58

3D3V_S0

U97A

1 of 4

G46

DATA
CLOCK
LATCH
SPKROUT

VDPLL

VDPLL_15
VSSPLL

T18
T17

7420_FILTER0

R0
R1

U18
U19

1394_R0
1394_R1

SC 0308
R709 2 0R0402-PAD

2 C928
SCD1U

1394_AGND

U15

1394_TPBIAS0 28

TPA0P
TPA0N

V15
W15

1394_TPA0P 28
1394_TPA0N 28

TPB0P
TPB0N

V14
W14

1394_TPB0P 28
1394_TPB0N 28

PHY_TEST_MA
CPS
CNA

R17
M11
P15

XO
XI

R19
R18

PC0(TEST1)
PC1(TEST2)
PC2(TEST3)

R12
U13
V13

AGND
AGND
AGND

N12
U14
U16

1394_AGND

TPBIAS1

U17

1394_TPBIAS1

TPA1P
TPA1N

V18
W18

TPB1P
TPB1N

V16
W16

1394_PHYTEST

Bypass/Decupoling Capacitors
Should be places as close to
PCI7411 as possible
3D3V_S0

1 R707

2
4K7R2
1 R706

1394_CNA
1394_XO
1394_XI

3D3V_S0

2
4K7R2
1
2

C917
3D3V_S0
SC22P50V2JN-1

X8

82.30023.181
1
2 C929
SC22P50V2JN-1
X-24D576M-2

SD_CD#
MS_CD#
SM_CD#
MS_CLK/SD_CLK/SM_EL_WP#
MS_BS/SD_CMD/SM_WE#

E3
F5
F6
G5
F3

U1-5

MS_DATA3/SD_DAT3/SM_D3
MS_DATA2/SD_DAT2/SM_D2
MS_DATA1/SD_DAT1/SM_D1

H5
G3
G2

U1-6

MS_SDIO(DATA0)/SD_DAT0/SM_D0
SD_CLK/SM_RE#
SD_CMD/SM_ALE

G1
J5
J3

SD_DAT0/SM_D4
SD_DAT1/SM_D5
SD_DAT2/SM_D6
SD_DAT3/SM_D7

H3
J6
J1
J2

3D3V_S0
SRN10KJ

MC_PWR_CTRL 28
C930
SCD1U

CBUS_TP1
TP112
1

TP111
TP113

CBUS_TP2
CBUS_TP3
CBUS_TP4

TP109

L5
L2
K5
K3
K7
L1
L3

SDA
SCL
NC#W17
RSVD
TEST0
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

UNUSED TERMINALS

W17
T19
P12

1394_AGND
MC_PWR_CTRL-0
MC_PWR_CTRL-1
TP108 TPAD30

Q32
PDTC144EU

U1-10

U1-9

SD_CD#
MS_CD#
SM_CD#
MS_CLK
MSCBS

28
28
28
28
28

MS/MS_pro

SM_D[4..7] 28

SD_WP/SM_CE
SM_CLE
SM_R/B#
SM_PHYS_WP#

MS_D3 28
MS_D2 28
MS_D1 28
MSCSDIO 28
SDCCLK 28
SDCCMD 28
SM_D4
SM_D5
SM_D6
SM_D7

MS_D[1..3] 28

MS/MS_pro

3D3V_S0

3D3V_PLL_S0

1 R715
2
0R0603-PAD
SC 0308

XD

28
28
28
28

C932
SC10U10V5ZY

B_USB_EN#
A_USB_EN#

RN117 SRN10KJ

M2
M3

C936
SCD1U

C947
SC1000P50V2KX

E1
E2

C915
SCD1U

4
3

C933
SC1000P50V2KX

R697 1
47KR2

2
1
2

F1
F2

C935
SCD1U

RN116

3D3V_S0

SC 0228

MC_PWR_CTRL_0
MC_PWR_CTRL_1

U1-8

C901
SCD1U

2
10KR2

28 CB_DATA
28 CB_CLOCK
28 CB_LATCH
32 CB_SPKR

C934
SC1000P50V2KX

TPBIAS0

2
6K34R2F

1 R708

SUSPEND#

N1
L6
N2
L7

V19
P14

R2

VDPLL_33
VSSPLL

1 R717

R13
R14
V17

TP110
3D3V_S0

2
GAP-CLOSE
1394_AGND

AVDD
AVDD
AVDD

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#
PCLK
PRST#
GRST#
RI_OUT#/PME#

1394

C/BE0#
C/BE1#
C/BE2#
C/BE3#

SD/SDIO

SC22P50V2JN-1

C964

CLK48_CARDBUS

PCIRST_BUF#

15,18,28,29,31,57

U1-7

P9
V7
R8
U7
W8
N8
7411_IDSEL W5
1 R716
2
100R2F
V8
U8
U1
T2
P5
R3
T1
T3

3D3V_S0
PM_CLKRUN# 18,29,31,34,37

18,29,31 PCI_PERR#
18,29,31 PCI_SERR#
18 PCI_REQ#1
18 PCI_GNT#1
18 CLK33_CBUS

R698 2
4K7R2

CARBUS 1 (INT_PIRQE#)
(WIFI) (INT_PIRQF#)
1394 (INT_PIRQG#)
CardReader (INT_PIRQE#) share

PCI_AD22

INTD#

CB_MFUNC5

INTA#
INTB#
INTC#
INTD#

18,29,31 PCI_PAR
18,29,31 PCI_FRAME#
18,29,31 PCI_TRDY#
18,29,31 PCI_IRDY#
18,29,31 PCI_STOP#
18,29,31 PCI_DEVSEL#

PCI_CBE#0 W11
PCI_CBE#1 W9
PCI_CBE#2 W7
PCI_CBE#3 W4

M1

INT_PIRQE# 18
INT_PIRQF# 18,31
INT_PIRQG# 18
P_SERIRQ 18,34,37

18,29,31 PCI_CBE#[3..0]

CLK_48

INTA#
INTB#
INTC#

3D3V_PLL_S0

CARD BUS

N3
M5
P1
P2
P3
N5
R1

1
2

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

18,22,29,31 PCI_AD[31..0]

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

4
3

PCI_AD31
U2
PCI_AD30
V1
PCI_AD29
V2
PCI_AD28
U3
PCI_AD27 W2
PCI_AD26
V3
PCI_AD25
U4
PCI_AD24
V4
PCI_AD23
V5
PCI_AD22
U5
PCI_AD21
R6
PCI_AD20
P6
PCI_AD19 W6
PCI_AD18
V6
PCI_AD17
U6
PCI_AD16
R7
PCI_AD15
V9
PCI_AD14
U9
PCI_AD13
R9
PCI_AD12
N9
PCI_AD11 V10
PCI_AD10 U10
PCI_AD9
R10
PCI_AD8
N10
PCI_AD7
V11
PCI_AD6
U11
PCI_AD5
R11
PCI_AD4 W12
PCI_AD3
V12
PCI_AD2
U12
PCI_AD1
N11
PCI_AD0 W13

U1-1

VCCP
VCCP

W3
W10

C949
SC1U10V3KX

1394_AGND
<Variant Name>

H7
J7
K1
K2

SD_WP 28
SM_CLE 28
SM_R# 28
SM_PHYS_WP# 28

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

PCI7411

Title

TI_PCI7411(1 of 2)
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

26

of

58

VCC_ASKT_S0

G10

CBB_A13 28

A_CFRAME#/A_A23
A_CTRDY#/A_A22
A_CIRDY#/A_A15
A_CSTOP#/A_A20
A_CDEVSEL#/A_A21
A_CBLOCK#/A_A19

C8
A8
B8
A9
C9
E10

CBB_A23
CBB_A22
CBB_A15
CBB_A20
CBB_A21
CBB_A19

A_CPERR#/A_A14
A_CSERR#/A_WAIT#

F10
B3

CBB_A14 28
CBB_WAIT# 28

A_CREQ#/A_INPACK#
A_CGNT#/A_WE#

E7
B9

28
28
28
28
28
28

CBB_INPACK# 28
CBB_WE# 28

A_CSTSCHG/A_BVD1(STSCHG#/RI#)
A_CCLKRUN#/A_WP(IOIS16#)
A_CCLK/A_A16

B2
C3
E9

A_CINT#/A_READY(IREQ#)
A_CRST#/A_RESET

C4
A6

CBB_RDY 28
CBB_RESET 28

A_CAUDIO/A_BVD2(SPKR#)

A2

CBB_BVD2# 28

A_CCD1#/A_CD1#
A_CCD2#/A_CD2#
A_CVS1/A_VS1#
A_CVS2/A_VS2#

C15
E5
A3
E8

CBB_CD1#
CBB_CD2#
CBB_VS1#
CBB_VS2#

A_RSVD/A_D14
A_RSVD/A_D2
A_RSVD/A_A18

B13
D2
C10

CBB_D14 28
CBB_D2 28
CBB_A18 28

CBB_BVD1# 28
CBB_WP 28
CBB_A16 28

2
33R2

28
28
28
28

F15
G18
K14
M18

RSVD

K13

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

G19
H17
J13
J17
H19
J19

RSVD
RSVD

J18
B18

RSVD
RSVD

E18
J15

RSVD
RSVD
RSVD

F14
A18
H18

RSVD
RSVD
RSVD

B19
F17
C17

RSVD
RSVD
RSVD
RSVD

N13
B17
C18
F19

RSVD
RSVD
RSVD

N17
A15
K15

3D3V_S0
U97D 4

C919
SCD1U16V

H8
H9
H10
H11
H12
J8
M7
J12
M9
M10
M12
K8
K12
N7
G7
G8
G13
H13
J9
J10
J11
K9
K10
K11
L8
L9
L10
L11
L12
M8

PCI7411

PCI7411

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

of 4
3D3V_S0

A_CPAR/A_A13

RSVD
RSVD
RSVD
RSVD

VR_PORT
VR_PORT

R695
10KR2

M19
H1

DY
2

CBB_REG# 28
CBB_A12 28
CBB_A8 28
CBB_CE1# 28

28
28

B15
A16
B16
A17
C16
D17
C19
D18
E17
E19
G15
F18
H14
H15
G17
K17
L13
K18
L15
L17
L18
L19
M17
M14
M15
N19
N18
N15
M13
P18
P17
P19

VR_EN#

H2
1

C5
F9
B10
G12

28
28

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

C918

C916
SCD1U16V
2

A_CC/BE3#/A_REG#
A_CC/BE2#/A_A12
A_CC/BE1#/A_A8
A_CC/BE0#/A_CE1#

U1-3

D19
K19

CBB_D10 28
CBB_D9 28
CBB_D1 28
CBB_D8 28
CBB_D0 28
CBB_A0 28
CBB_A1 28
CBB_A2 28
CBB_A3 28
CBB_A4 28
CBB_A5 28
CBB_A6 28
CBB_A25 28
CBB_A7 28
CBB_A24 28
CBB_A17 28
CBB_IOWR#
CBB_A9 28
CBB_IORD#
CBB_A11 28
CBB_OE#
CBB_CE2#
CBB_A10 28
CBB_D15 28
CBB_D7 28
CBB_D13 28
CBB_D6 28
CBB_D12 28
CBB_D5 28
CBB_D11 28
CBB_D4 28
CBB_D3 28

RSVD
RSVD

SCD1U16V
2

D1
C1
D3
C2
B1
B4
A4
E6
B5
C6
B6
G9
C7
B7
A7
A10
E11
G11
C11
B11
C12
B12
A12
E12
C13
F12
A13
C14
E13
A14
B14
E14

28
28

A_CAD31/A_D10
A_CAD30/A_D9
A_CAD29/A_D1
A_CAD28/A_D8
A_CAD27/A_D0
A_CAD26/A_A0
A_CAD25/A_A1
A_CAD24/A_A2
A_CAD23/A_A3
A_CAD22/A_A4
A_CAD21/A_A5
A_CAD20/A_A6
A_CAD19/A_A25
A_CAD18/A_A7
A_CAD17/A_A24
A_CAD16/A_A17
A_CAD15/A_IOWR#
A_CAD14/A_A9
A_CAD13/A_IORD#
A_CAD12/A_A11
A_CAD11/A_OE#
A_CAD10/A_CE2#
A_CAD9/A_A10
A_CAD8/A_D15
A_CAD7/A_D7
A_CAD6/A_D13
A_CAD5/A_D6
A_CAD4/A_D12
A_CAD3/A_D5
A_CAD2/A_D11
A_CAD1/A_D4
A_CAD0/A_D3

CBB_D[0..15]
CBB_A[0..25]

A5
A11

POWER TERMINALS

VCCA
VCCA

1 R688

of 4

CARDBUS A

U1-2

2 C903
SCD01U16V2KX

U97C

of 4

CARDBUS B

U97B

R696
1KR2

from spec :
this pin is
active low

SB 0201

Place it near to chip

U1-4

PCI7411

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

TI_PCI7411(2 of 2)
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

27

of

58

CBB_VS2#
CBB_A16

CBB_A5
CBB_RESET
CBB_A4
CBB_WAIT#
CBB_A3
CBB_INPACK#
CBB_A2

CBB_REG#
CBB_A1

Place close to pin 19.

CBB_BVD2#

C907
DUMMY-C2

CBB_BVD1#
CBB_D0
CBB_D8
CBB_D1
CBB_D9
CBB_D2
CBB_D10

CBB_A0

Clock AC termination
33MHz clock for 32-bit
Cardbus card I/F

CBB_WP
CBB_CD2#

2
1

1
2

SC220P50V2KX-U

1
2

2
R422 10KR2

3.3V

AVPP

VPP_ASKT_S0
R421
100KR2

C605
SCD1U16V

VPP_ASKT_S0

15

NC
NC
NC
NC
NC
NC
NC
NC
NC

24
23
22
19
18
17
16
14
6

5V_S0
C619
SC4D7U10V5ZY

ME : 21.H0056.001

C606
C607
SCD1U16V SC1U10V3ZY

DY

SB 0202

VCC_ASKT_S0

1
2

5V
5V

7
20

12V
12V

11
25

GND
GND

C608
SCD1U16V

OC#

C618
SCD1U16V

CARD-SKT18-U

21.H0056.001

13

9
10

3D3V_S0

AVCC
AVCC

DATA
CLOCK
LATCH
RESET#
SHDN#

CBB_A16
CBB_A22
CBB_A15
CBB_A23
CBB_A12
CBB_A24
CBB_A7
CBB_A25
CBB_A6

C909
SCD1U

VCC_ASKT_S0

3
4
5
12
21

VPP_ASKT_S0

U53

CB_DATA
CB_CLOCK
CB_LATCH
PCIRST_BUF#

CBB_A21

26
26
26
15,18,26,29,31,57
5V_S0

CBB_RDY

ME : 20.90036.001
2ND : 22.10245.141
R712
4K99R2F

CBB_A20

20.90036.001

1394_AGND

Power switch

PC1

CBB_WE#

22.10245.141 - 2ND

R713
56R2F

1394_TPBIBS

1394_AGND

C904
SC1000P50V2KX

C931
SC1U10V3KX

ACM2012-900-2P-T

R714
56R2F

Close to the cardbus Controller.

1
C905
SCD1U

SC10U10V5ZY

C908

C906

SC10U10V5ZY
2

CBB_IOWR#
CBB_A8
CBB_A17
CBB_A13
CBB_A18
CBB_A14
CBB_A19

CBB_IORD#
CBB_A9

6
4
3
2
1
AMP-CONN4A

C948

C604
SC4D7U

DY

TSP2220A
3D3V_CR_S0
CARD1

CBB_A11

R710
56R2F

26 1394_TPBIAS0

C900

C914

CBB_CE2#
CBB_OE#
CBB_VS1#

R711
56R2F

SCD1U16V

CBB_A10
VCC_ASKT_S0

27
27
27
27
27
27

CBB_D15

CBB_CE1# 27
CBB_CE2# 27
CBB_BVD1#
CBB_BVD2#
CBB_CD1#
CBB_CD2#
CBB_VS1#
CBB_VS2#

CBB_CE1#

27
27

26 1394_TPB0N

1394

TPA0+
TPA0TPB0+
TPB0-

27
27

SC1U10V3ZY

CBB_D4
CBB_D11
CBB_D5
CBB_D12
CBB_D6
CBB_D13
CBB_D7
CBB_D14

26 1394_TPB0P

2
1

3 TR3
4

1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

TR2
4 ACM2012-900-2P-T

CBB_CD1#

1
26 1394_TPA0N

CBB_D3

26 1394_TPA0P

27
27

CBB_IORD# 27
CBB_IOWR# 27
CBB_OE# 27
CBB_WE# 27
CBB_REG# 27
CBB_RDY
CBB_WP
CBB_RESET 27
CBB_WAIT#
CBB_INPACK#

CBB_D[0..15]
CBB_A[0..25]
PCH1

1394 Connector

Cardbus I/F

PCMCIA Socket

C927
SCD1U16V

MSCSDIO
MS_D1
MS_D2
MS_D3

26 MSCSDIO

7
6
12
11

SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS_D1
MS_D2
MS_D3
SM_D4
SM_D5
SM_D6
SM_D7

33
32
31
21
22
23
24

S.M/XD-D1
S.M/XD-D2
S.M/XD-D3
S.M/XD-D4
S.M/XD-D5
S.M/XD-D6
S.M/XD-D7

SM_CD#
MSCSDIO

25
30
34

S.M-LVD
S.M-CD#
S.M-D0

SM-CD-COM
SM-CD-SW
SM-WP-SW

2
3
43

MS-BS
MS-INS
MS-SCLK

13
17
19

RSV#4
XD-CD

4
39

SD-CD-COM
SD-CD-SW
SD-WP-SW
SD-CLK
SD-CMD

41
42
5
8
10

S.M#/XD-CLE
S.M#/XD-ALE
S.M#/XD-WE
S.M#/XD-CE
S.M#/XD-RE
S.M#/XD-R/B
S.M/XD-WP-IN

38
37
36
28
27
26
35

GND
GND
GND
GND

46
45
44
1

SM_CD#
SM_PHYS_WP#

MS_CLK-R

MSCBS 26
MS_CD# 26
MS_CLK 26

1 R694
2
0R0402-PAD

SC 0308
SM_CD# 26
SD_CD# 26
SD_WP_R 1 R705
SD_WP
2
MS_CLK 0R0402-PAD
SC 0308
MSCBS

PCMCIA-12-U

XD-VCC
S.M-VCC
MS-VCC
SD-VCC

15
14
16
18

MS_D1
MS_D2
MS_D3

VCC_ASKT_S0

40
29
20
9

R420
DUMMY-R2

62.10024.131
ME : 62.10024.131

C603
SCD01U16V2KX

POWER SWITCH
3D3V_S0

26 MC_PWR_CTRL

2
3
4

GND
NC
ON/OFF#
AAT4250-U
74.04250.03F

IN

OUT

SD_WP 26
SDCCLK 26
SM_R# 26
R686 2
DY
SM_PHYS_WP# 26
0R2-0
R687
MS_CLK-R
1
2
0R0402-PAD
SC 0308

SM_D[4..7] 26
MS_D[1..3] 26

SKT-MEMO-9-U1
<Variant Name>

62.10051.331
ME : 62.10051.331

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

C893

SC1U10V3ZY

C894

Wistron Corporation

Title

PCMCA / 1394 / CARD READER


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005


A

SM_CLE 26
SDCCMD 26
SC 0308

3D3V_CR_S0

U95

SCD1U16V

47K

SDCCMD
MSCBS
1 R685
2
0R0402-PAD

Sheet
E

28

of

58

TGP1

TGP2

TGP3

TGN0

TGN1

TGN2

TGN3

18,26,31 PCI_CBE#[3..0]
18,22,26,31 PCI_AD[31..0]

CLOSE TO
LAN CHIP

R573
R572
49D9R2F 49D9R2F

R577
R576
49D9R2F 49D9R2F

R579
R578
49D9R2F 49D9R2F

100M_LED# 30

=> LED1 : LINK


1

X7

LAN_X2

D40

RTL_LED1#

2 0R0402-PAD

1 R612

R571
R570
49D9R2F 49D9R2F

2 C725
SC12P50V2JN

2 C759
SC12P50V2JN

TGP0

RTL_LED2#

LAN_X1

U78
BAT54C-L

C729
SCD01U50V3KX

X-25MHZ-11-U

DY

1
C728
SCD01U50V3KX

1G_LED# 3

DY

C727
SCD01U50V3KX

RB731U

Dummy when use 10/100

3D3V_LAN_S5

10M_LED# 30,57

LAVDDH

U79

1
1

3D3V_LAN_S5
3D3V_LAN_S5

SC 0308
LAN_X2

CS
SK
DI
DO

CTRL18
ACT_LED#
LDVDD

3D3V_LAN_S5

PCI_AD23

R603 2 LAN_IDSEL
100R2F

PCI_AD25
PCI_AD24
PCI_CBE#3
LDVDD
LAN_IDSEL
PCI_AD23
PCI_AD22
PCI_AD21

PCI_AD19
LDVDD
PCI_AD20

1
2

2
SCD1U

1
C199
SCD1U

SC 0308

C230

SCD1U

PCI_AD13
PCI_AD14

PCI_PAR 18,26,31
PCI_SERR# 18,26,31

3D3V_LAN_S5

Dummy when use Giga

PM_CLKRUN#

CTRL25

PCI_PERR# 18,26,31
PCI_STOP# 18,26,31
PCI_DEVSEL# 18,26,31
PCI_TRDY# 18,26,31

Q7
BCP69T1-U

R150
0R3-U

Dummy when use 10/100

LAVDDL

PM_CLKRUN# 18,26,31,34,37

<Variant Name>

C159

PCI_IRDY# 18,26,31
PCI_FRAME# 18,26,31

C204

C208

C205

PCI_PERR#
PCI_STOP#
PCI_DEVSEL#
PCI_TRDY#

PCI_AD15
LDVDD
PCI_CBE#1
PCI_PAR
PCI_SERR#

C200

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

G68

3D3V_LAN_S5
3D3V_S5

RTL8110SBL/RTL8100C

3D3V_LAN_S5
Size
A3

GAP-CLOSE-PWR

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005


A

C201

SCD1U

GIGALAN: RTL8110SBL
10/100 LAN:RTL8100C
LDVDD
PCI_IRDY#
PCI_FRAME#
PCI_CBE#2
PCI_AD16
PCI_AD17
PCI_AD18

C788

SCD1U

C761

SCD1U

C760

SCD1U

C731

SCD1U

1
2

RTL8110SBL
C730 (10/100) 71.08100.C0G - (GIGA ver:C) 71.08110.A0G
SC10P50V2JN-1
PCI_AD27
PCI_AD26

1
2

1
2

1
2

SCD1U

CLK33_LAN

C758

PCIAD27
PCIAD26
VDD33
PCIAD25
PCIAD24
CBEB3
VDD18
IDSEL
PCIAD23
GND
PCIAD22
PCIAD21
VSSPST
GND
PCIAD20
VDD18
PCIAD19
VDD33
PCIAD18
PCIAD17
PCIAD16
CBEB2
FRAME#
GND
IRDY#
VDD18

PCI_AD29
PCI_AD28

SCD1U

SCD1U
2

SC 0308

C786

SCD1U
2

CLK33_LAN
PCI_GNT#2
PCI_REQ#2
PME#_LAN
LDVDD
PCI_AD31
PCI_AD30

SCD1U

ISOLATE#
LDVDD
INT_PIRQH#

C783

18 INT_PIRQH#
3D3V_LAN_S5
15,18,26,28,31,57 PCIRST_BUF#
18,22 CLK33_LAN
18 PCI_GNT#2
18 PCI_REQ#2
R582 2
1
21,34 PME#_SB
0R0402-PAD

PCI_AD10
PCI_AD11
PCI_AD12

SC10U10V5ZY
2

PCI_AD8
PCI_AD9

SC 0308 2 D53

3 1
BAT54-1
R581 2
15KR2F

C757
SCD1U

LDVDD_A

C202
SCD1U

L4
1
2
0R0603-PAD

TGP3
TGN3
LAVDDL
R580 2 1KR2

30 TGP3
30 TGN3

3D3V_S0

Dummy when use 10/100

C203
SCD1U

45 Ohm,
600mA

LDVDD
PCI_AD7
PCI_CBE#0

30 TGP2
30 TGN2

TGP2
TGN2
LAVDDL

SC 0308

C762
SCD1U

Q9
BCP69T1-U

1
CTRL18 1
2
R170 0R2-0

Dummy when use Giga

LDVDD
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6

LV_12P

C784
SCD1U

3D3V_LAN_S5

LDVDD

LAVDDH

2
0R2-0
1 R574
2
0R2-0

0R2-0
1 R149

1 R575

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

LAVDDH

PCIAD2
VSSPST
GND
VDD18
PCIAD3
PCIAD4
PCIAD5
PCIAD6
VDD33
PCIAD7
CBEB0
VSSPST
PCIAD8
PCIAD9
M66EN
PCIAD10
PCIAD11
PCIAD12
VDD33
PCIAD13
PCIAD14
VSSPST
GND
PCIAD15
VDD18
CBEB1
PAR
SERR#
NC#74
GND
NC#72
VDD33
PERR#
STOP#
DEVSEL#
TRDY#
VSSPST
CLKRUN#

PCI_AD2

Dummy when use 10/100

C206
SCD1U

TGP1
TGN1
LAVDDL
CTRL25

MDI0+
MDI0AVDDL
VSS
MDI1+
MDI1AVDDL
CTRL25
VSS
AVDDH
HSDAC+
HSDACVSS
MDI2+
MDI2AVDDL
VSS
MDI3+
MDI3AVDDL
VSSPST
GND
ISOLATE#
VDD18
INTA#
VDD33
PCIRST#
PCICLK
GNT#
REQ#
PME#
VDD18
PCIAD31
PCIAD30
GND
PCIAD29
PCIAD28
VSSPST

102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

30 TGP1
30 TGN1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

TGP0
TGN0
LAVDDL

C207
SCD1U

Dummy when use Giga


CTRL25

30 TGP0
30 TGN0

C787
C732
SC10U10V5ZYSCD1U

1
AVDDH
VSSPST
GND
LED0
VDD18
LED1
LED2
LED3
GND
EESK
VDD18
EEDI
EEDO
VDD33
EECS
LANWAKE
PCIAD0
PCIAD1

XTAL1

XTAL2

VSS

VSS

CTRL18

AVDD18

VSS
RSET

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103

121

122

123

124

125

126

128
127

U75

LAVDDH

L5
1
2
0R0603-PAD

PCI_AD0
PCI_AD1

Dummy when use 10/100 RSET

45 Ohm,
600mA

3D3V_LAN_S5

3D3V_LAN_S5

SCD1U
2

=> LED0 : ACT

R569 2
5K6R3F

EEPROM LED OPTION USE '01'


(DEFINED IN SPEC)
=> LED0 : ACT
=> LED1 : LINK
(BOTH 10/100 AND GIGA CHIP)

ACT_LED# 30,57

RTL_LED1#
RTL_LED2#
1G_LED#
LAN_EESK
LDVDD
LAN_EEDI
LAN_EEDO
3D3V_LAN_S5
LAN_EECS_3

Dummy when use Giga

1 R568
2K49R3F

C785
SCD1U

M93C46-W-3

LDVDD_A

8
7
6
5

VCC
DC
ORG
GND

1
2
3
4

LAN_EECS_3
R614 2 10KR2
LAN_EESK
R615 2 3K6R3D LAN_EEDI
LAN_EEDO

DY

LAN_X1

C726
SCD01U50V3KX

MID3X

MID2X

MID1X

MID0X

Sheet
E

29

of

58

Link: Green - 10Mbps/802.11b


Orange - 100Mbps/802.11a
Yellow - 1Gbps

Activity: Yellow

LAN1

2 R20

29,57 ACT_LED#

LAN switch

1
2

29
29
29
29
29
29
29
29

EC2
SCD1U

TGN0
TGP0
TGN1
TGP1
TGN2
TGP2
TGN3
TGP3

10M_LED#
100M_LED#
ACT_LED#
C14

B2:YELLOW

22.10177.721
ME : 22.10177.721
2nd : (canceled)

C10
SC1000P50V2KX

SKT-RJ45+RJ11-2
22.10177.711 - 2ND

C11
SC1000P50V2KX

SC1000P50V2KX

B2
10

ACT:YELLOW BLINKING

SC 0310

MDCW1
MLXCON2

EC1
SCD1U

A3:ORANGE

A3
RJ45_1
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
B1

An to nB2

3D3V_LAN_S5

TDP_RJ45-1
TDN_RJ45-2
RDP_RJ45-3
RJ45-4
RJ45-5
RDN_RJ45-6
RJ45-7
RJ45-8
1 CONN_PWR_B2
470R2
ACT_LED#

A2

29 100M_LED#

1CONN_PWR
470R2

R18

SEL

An to nB1

U12
CONN_PWR_B2
CONN_PWR

3D3V_LAN_S5

A1

Function

10M_LED#

29,57 10M_LED#

LINK:GREEN ON

22.10177.721
22.10177.711
LED COLOR
A1:GREEN

9
RJ11_1
RJ11_2

TIP
RING

2
4
8
10
15
17
21
23

A0
A1
A2
A3
A4
A5
A6
A7

3
5
7
9
11
13
16
18
20
22
27
30
33
37
40
43
46

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

L1
TIP
RING

21.D0010.102

0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2

45
44
39
38
32
31
26
25

D_TTGN0
D_TTGP0
D_RTGN1
D_RTGP1
D_TGN2
D_TGP2
D_TGN3
D_TGP3

NC

14

SEL

24

VDD
VDD
VDD
VDD
VDD

1
6
12
19
36

SYSTEM

RJ45-8
RJ45-7
RJ45-5
RJ45-4

DOCK_ON_1
3D3V_LAN_S5

6
14
11
3

CT
CT
CT
CT

10
9

TDP_RJ45-1
TDN_RJ45-2

RD+
RD-

1
2

S_RTGP1
S_RTGN1

RX+
RX-

16
15

RDP_RJ45-3
RDN_RJ45-6

8
7
6
5

TX+
TX-

1
2
3
4

MCT3
MCT4
V_DAC

TD+
TD-

DOCK

DOCK_ON_1 57

C31
SCD1U10V2MX-1
3

Dummy when no EZ4

U60

7
8

D_TTGN0 57
D_TTGP0 57
D_RTGN1 57
D_RTGP1 57
D_TGN2 57
D_TGP2 57
D_TGN3 57
D_TGP3 57

PI3L301DA

S_TTGP0
S_TTGN0

ME : 21.D0010.102

S_TTGN0
S_TTGP0
S_RTGN1
S_RTGP1
S_TGN2
S_TGP2
S_TGN3
S_TGP3

2 BLM18HG601SN1D
2 BLM18HG601SN1D

L2

10/100M Lan Transformer

1
1

48
47
42
41
35
34
29
28

TIP_MDC
RING_MDC

1
2

0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1

MCT1

RN13

SRN0-1-U
MCT2

XFORM-112
TGN0
TGP0
TGN1
TGP1
TGN2
TGP2
TGN3
TGP3

68.0H80P.301

Dummy when use Giga


CHANGE NETSWAP?

LANKOM 68.0H80P.301

RN98
RN99
RN100
RN101

2
1
2
1
2
1
2
1

SRN0-2-U
SRN0-2-U
SRN0-2-U
SRN0-2-U

S_TTGN0
S_TTGP0
S_RTGN1
S_RTGP1
S_TGN2
S_TGP2
S_TGN3
S_TGP3

Dummy when use EZ4

LANKOM 68.02402.30A
netSWAP 68.62401.301 (GIGA ,Thick)
SC 0310

GIGA Lan Transformer

3
4
3
4
3
4
3
4

NETSWAP GIGA THICK PN IS 68.62401.301, DON'T USE NETSWAP THIN


U61

2
3

TD1+
TD1-

MX1+
MX1-

23
22

RJ45-7
RJ45-8

S_TGP2
S_TGN2

5
6

TD2+
TD2-

MX2+
MX2-

20
19

RJ45-4
RJ45-5

S_RTGP1
S_RTGN1

8
9

TD3+
TD3-

MX3+
MX3-

17
16

RDP_RJ45-3
RDN_RJ45-6

S_TTGP0
S_TTGN0

11
12

TD4+
TD4-

MX4+
MX4-

14
13

TDP_RJ45-1
TDN_RJ45-2

1
4
7
10

TCT1
TCT2
TCT3
TCT4

MCT1
MCT2
MCT3
MCT4

24
21
18
15

MCT1
MCT2
MCT3
MCT4

C35

8
7
6
5

XFORM-153

68.02402.30A

1.route on bottom as differential pairs.


2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

RN12

Dummy when use 10/100

Wistron Corporation
C34
SCD1U

Dummy when use 10/100

C13
2

1
2
3
4

1
2

C36

SCD01U50V3KX

SCD01U50V3KX
2

C33

SCD01U50V3KX

C32

V_DAC

R517 2
0R2-0

SCD01U50V3KX
2

LAVDDL

S_TGP3
S_TGN3

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

SRN75J

LAN_TC_GND
SC1KP2KV

Title

LAN CONN

2 C12
DY
SC1000P50V2KX

Size
A3

Dummy when use Giga

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

30

of

58

MINI-PCI
4

1
C810
SCD1U

1
C834
SCD1U

C809
SC4D7U10V5ZY

18,22,26,29 PCI_AD[31..0]
18,26,29 PCI_CBE#[3..0]

3D3V_S0

C835
SCD1U
3D3V_S0

MINI1

24 BT_COEX2

PCI_CBE#3
PCI_AD23

3D3V_S0

PCI_AD21
PCI_AD19

PCI_AD17
PCI_CBE#2

R637
10KR2

18,26,29 PCI_IRDY#

18,26,29,34,37 PM_CLKRUN#
18,26,29 PCI_SERR#

18,26,29 PCI_PERR#

PCI_CBE#1
PCI_AD14
PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
5V_S0

PCI_AD1

1
2

124
126

123

R565
10KR2

Q29
DTC124EUA-U1

DY

MINI_P_IRQF# 1
R629 2
0R0402-PAD

22 K

INT_PIRQF# 18,26

80211_ACTIVE

2
3

SC 0308

PCIRST_BUF# 15,18,26,28,29,57
22 K

PCI_GNT#0 18
PME#_MINI
BT_COEX1 24

PCI_AD30

TP82
TPAD30

PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL

R638 2 PCI_AD21
100R2F

Q28
DTC124EUA-U1

PCI_AD22
PCI_AD20
22 K

PCI_PAR 18,26,29

PCI_AD18
PCI_AD16

WIRELESS_EN

PCI_FRAME# 18,26,29
PCI_TRDY# 18,26,29
PCI_STOP# 18,26,29

22 K

PCI_DEVSEL# 18,26,29
PCI_AD15
PCI_AD13
PCI_AD11

SB 0214
2

PCI_AD9
PCI_CBE#0

PCI_AD27
PCI_AD25

WLAN_LED# 17

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

Q30
DTC124EUA-U1
22 K

(VCC)

34 WLAN_TEST_LED
(M66EN)

22 K

PCI_AD31
PCI_AD29

C811
SC4D7U10V5ZY

DY

18 PCI_REQ#0

3D3V_S0
C833

18,22 CLK33_MINI

RING

3D3V_S0
3

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122

MINI_P_IRQF#

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121

SCD1U

80211_ACTIVE
34 WIRELESS_EN

R566
10KR2

5V_S0

TIP

125
2

DY

SB 0214

PCIMODEM124A1U1

62.10032.001

<Variant Name>

ME : 62.10032.001
2ND : 62.10032.031

Wistron Corporation

62.10032.031 - 2ND

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

MINI-PCI
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

31

of

58

5V_AUDIO_S0

DY R416

1
1

AC97_RST#

U55

1
33 VREFOUT1

NC7SZ08-U
SB 0219

R419
10KR2

C610

DY

VREFOUT2
ADAF2
ADAF1
VREFOUT1
CODECVREF

5V_AUDIO_S0

16
17

AUDLINL
AUDLINR

2
2 SC1U10V3KX
SC1U10V3KX

23
24

LINE-L
LINE-R

35
36

FRONT-OUT-L
FRONT-OUT-R

21
22

MIC1
MIC2

1
2

1
2

1
2

SCD1U

SPDIFO
SPDIFI/EAPD

SURR-OUT-L
SURR-OUT-R

C602

SCD1U

9
1

2
JD2
JD1/GPIO1

39
41

C615

VDD
VDD

SCD1U

AVDD
AVDD

33
40

27
28
34

SCD1U

XTL-IN
XTL-OUT

SDIN
SDOUT

R700 2
75R2F

CDAUDL

CDAUD_L
2 C924
SC1U10V3KX

CDAGND

CDAUD_GND
2 C925
SC1U10V3KX

XTALIN_CODEC

2
3

0R0402-PAD
1 R689
2

SPDIF_OUT

48
47

CLK14_AUDIO 3

0R0402-PAD
1 R449
2
EAPD 33

C910

AC97_DATIN

8
5

BITCLK
SYNC

6
10

RESET#

11

R690 1
22R2
1 R450
2
0R0402-PAD
SC 0308
R415
2
1
33R2
R414 2
1
DY
10KR2

AC97_CBITCLK

AC97_DIN0 21
AC97_DOUT 21,22,24

BITCLK_BUFF

XTSEL HI: USE 24.576M XTAL


XTSEL LOW: USE 14.318M CLK FROM CLK GEN

4
7

GND
GND

AGND
AGND

1 C921
SCD1U

AUD_SYS_BEEP

CDAUD_R
2 C922
SC1U10V3KX

AUD_PC_BEEP

C926
R702
100KR2

AUD_AGND

R701
2K2R2

1 R691

2 4K7R2 2

1 C911
SC4D7U10V5ZY

1 R692

2 4K7R2 2

1 C912
SC4D7U10V5ZY

SPKR_SB 21

G105
2

GAP-CLOSE
1

1 R693

2 4K7R2 2

1 C913
SC4D7U10V5ZY

KBC_BEEP 34

G106
2

GAP-CLOSE
1

G107
2

GAP-CLOSE
1

G108
2

GAP-CLOSE
1

CB_SPKR 26

R703
100KR2

SC22P50V2JN

AC97_SYNC 21,24
AC97_RST# 21,24

SC2200P50V2KX

R704
100KR2

EC5

26
42

PC-BEEP
PHONE
12
13

CEN-OUT
LFE-OUT

45
46

CDAUDR

GAP-CLOSE-PWR
R699 2
75R2F

25 CD_AUDR

JD0/GPIO0
XTLSEL

SPDIF 33,57

SC 0308

AUD_AGND

R451
25 CD_AGND

43
44

CD-L
CD-R
CD-GND
1

18
20
19

ALC655-U

MONO-OUT-R

AUD_MICIN1
1 C923
SC1U10V3ZY

25 CD_AUDL

DY
C616

AUX-L
AUX-R

37

1
AUD_AGND

33 AUD_MICIN

1
2

AUD_AGND

C938
SC1000P50V2KX

R446
10KR2F-U
C613
SC10U10V5ZY

AUD_AGND

3D3V_S0

2
C937
SC1000P50V2KX

OUT

G923-330T1U-1

SC1000P50V2KX

33 AUD_LOL
33 AUD_LOR

1
1

IN

C920
C946

33 AUD_LINL
33 AUD_LINR

VREF
VREFOUT
FRONT-MIC

AFILT1
AFILT2
14
15

31
32

29
30

U98
C

38
25

SCD1U
2

C617

NC#33
NC#40

DY

AUD_AGND

VRDA
VRAD

DY

C945

SCD1U
2

C944

SC10U10V5ZY

C942

SC1U10V3KX
2

SC1000P50V2KX
2

SC1000P50V2KX
2

C943

SCD1U
2

1
2

C941

5V_AUDIO_S0

AUD_AGND
C614

C940

C939
SCD1U

GND

5VA_SET

SHDN# SET

B
GND

R447
28K7R2F

C611

BITCLK_BUFF

SC22P50V2JN-1
1
2

2
33R2

5V_S0

1
0R2-0

2 AC97_BITCLK_ALL
2
33R2
3D3V_S0
U52
5 VCC

1 R417

24 AC97_BITCLK

SC1U10V3KX

1 R418

21 AC97_BITCLK_SB

AUD_AGND

AUD_AGND
SC 0308
AUD_AGND

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AUDIO (1/2) -- CODEC ALC655


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
1

32

of

58

5V_S0

5VA_OP_S0
ALL AUD_AGND -> AMPGND

G43

Internal Speaker

SB 0203
G109
2

GAP-CLOSE
1

G110
2

GAP-CLOSE
1

SC220P50V2KX-U

G111
2

GAP-CLOSE
1

1 R478

G112
2

GAP-CLOSE
1

SPK1

1
6

SC 0308

C952
1
2CSOUTL2 1

32 AUD_LOL

R719 2
L_LINE_IN
15KR2F

R718 2
18KR2F

C638

C640

C639

2 C632
SC220P50V2KX-U

ETY-CON4-S

C637

AMPGND

SPKR_R-

SC2D2U16V5ZY

SPKR_R+

SC680P50V2KX

2
10KR2

HP_L

R479 2
10KR2

SC680P50V2KX

C636
1
2CSOUTL1

5
4
3
2

SPKR_L+

AMPGND

SPKR_L-

SC680P50V2KX

2 C634

C612
SC4D7U10V5ZY

SC680P50V2KX

GAP-CLOSE-PWR

DOCK_JACK_IN

U57

2ND : 20.D0012.104

ME : 20.D0122.104
2ND : 20.D0012.104

D22

SC2D2U16V5ZY

20.D0122.104

57

SC 0309

Dummy when no EZ4

32 AUD_LINR

R486 2
1KR2

32 AUD_LINL

R484 2
1KR2

100KR2

C645

R487
1KR2

3
3

SC 0309

5VA_OP_S0

SC4D7U10V5ZY

R732
2K2R2

SC100P50V2JN

EC7

2
SC330P50V2KX

EC8

1
2

C648

22.10088.571
22.10271.011 - 2ND

ME : 22.10133.561
2ND : 22.10257.001
2ND : 56.1549C.011

R489
10KR2

3D3V_S0
LOUT1

9
8
7
16
6
5
4
2
3
1

SYS_LOUT_IN

AMPGND

SB 0127
SYS_LOUT_IN#

SB 0127

1 R452

LEVEL SHIFT

R445
10KR2

R764

DY

5V_S0

0R2-0
1MIC_JKIN#_1 2

BAW56-1
Q20
DTC124EUA-U1

ME : 20.D0012.102
20.D0012.102
SB 0204

1 R751

2 0R3-U
1

AMPGND

<Variant Name>
TSAHCT125

32 AUD_MICIN

SYS_EXT_MIC_IN
2
0R0402-PAD
57 DOCK_MIC_JKIN
INT_MIC_IN
2
0R0402-PAD
1 R476
2
DOCK_EXT_MIC 57
0R0402-PAD
C625
SC3300P50V2KX

1 R468
1 R469

22 K

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
22 K
Title

AUDIO (2/2)

R460
10KR2

Dummy when no EZ4

AMPGND

Size
Document Number
Custom

AMPGND

Rev

-1

Bolsena

Date: Thursday, March 31, 2005


A

CON2-10-U2

C631
SC4D7U10V5ZY

22 K

1
R475
2K2R2

AUD_MUTE

2 R459
1
0R0402-PAD

10

14

U2C
8

LOW OFF

1
2

C1

22 K

34 KBC_MUTE

Q22
DTC124EUA-U1

32 VREFOUT1

D21

22.10257.001

INT_MIC

SC1000P50V2KX

Dummy when no EZ4

SC 0308

MINDIN10-1-U2
1ST CHANGE TO 22.10147.031 - 22.10251.031 2ND
EC6
EC9

MIC1

R453
10KR2

Q23
DTC124EUA-U1

close to diode

SB 0201

INT_MIC_IN

22 K

22 K

5V_AUDIO_S0
37

C649

Internal Mic

SB 0201
MIC_JKIN#

5V_AUDIO_S0

SC 0309

BAT54C-U
U56

2AUD_LINE_L
300R2F

C650

SPKR_L_A1
SPKR_R_A1

R467 2
0R2-0

1
SYS_EXT_MIC_IN

Dummy when 'USE EZ4'

AMPGND

R493R491
1KR21KR2

SE100U10VM

79.10711.4C1

AMPGND

TC29

SPKR_R+1

GND
VCC
VIN

2
SC330P50V2KX

K 22

2
22R2
1 R490
2
22R2

SPKR_R+

1 R492

2
SC330P50V2KX

SE100U10VM
SPKR_L+1
2

SC680P50V2KX

SPKR_L+

AMPGND

SYS_LOUT_IN#

DTC124EUA-U1

SC680P50V2KX
2

TC30

K 22
2

32,57 SPDIF

79.10711.4C1

Q33

AUDIO-JK30-U

ME : 22.10088.571
2ND : 22.10271.011

SB 0127

GAP-CLOSE

SYS_LOUT_IN#=LOW after PLUG-IN

LINE OUT

R456

1
1
2
2
AMPGND

HP_R

C646

10KR2
10KR2

AMPGND

2
10KR2

R471 2
18KR2F
1
2 C630
SC220P50V2KX-U
1 R470
2
10KR2
1
2 C628
SC220P50V2KX-U

AUD_LINE_L

R485
R488

R_LINE_IN
2
15KR2F

LIN1

5
4

AMPGND
AUD_LINE_R

SC100P50V2JN

CSOUTR1
1 R455

SC2D2U16V5ZY
C626
R472
1
2 CSOUTR2
1

C629

DOCK_LIN_R 57
DOCK_LIN_L 57

C647

SC4D7U10V5ZY

SC 0309

R466

AMPGND

R_BYPASS
L_BYPASS

5VA_OP_S0

LINE IN/MIC IN

HP_IN_1

57

SC330P50V2KX

C627
1
2

SC2D2U16V5ZY

SC 0308

57

SPKR_R_DOCK

C
AMPGND

32 AUD_LOR

32 EAPD

SPKR_L_DOCK

SPKR_RSPKR_R+

2
0R2-0
2
0R2-0

MIC_JKIN#_1

R454
100KR2

Q21
PDTA124EU

AMPGND

AMPGND

1 R473

Dummy when no EZ4

DY

AMPGND

1 R477

SPKR_R+

RB731U

AMPGND

R457
10KR2

C635

SPKR_L+

E
3

34 AMP_SHUTDOWN

G1421BF3U

37

SC1U10V3ZY

By GMT suggest.
Change from
74.01421.01G
to 74.01421.A1G

21

AMPGND

ROUTROUT+

15
22

ENAUDIO#

R458
10KR2

RVDD
RBYPASS
RHPIN
RLINEIN

AUD_MUTE

SYS_LOUT_IN

R_BYPASS
HP_R

18
19
20
21

SPKR_L+
SPKR_LHP_IN

AMPGND

SHUTDOWN
TJ
HP-IN
VOL

3
10
14
16
11
9
1
12
13
24

SC1U10V3ZY

HP_IN_1
5VA_OP_S0

8
2
17
23

LOUT+
LOUTSE/BTL#
HP/LINE#
MUTEIN
MUTEOUT
GND/HS
GND/HS
GND/HS
GND/HS
GND

1
2

SCD1U

1
2

C633

SC1U10V3KX

C950

SC10U10V5ZY

C951

LLINEIN
LHPIN
LBYPASS
LVDD

4
5
6
7

HP_L
L_BYPASS

25

5VA_OP_S0

Sheet
E

33

of

58

KCOL[1..16] 35
KROW[8..1] 35

3D3V_AUX_S5

5V_S0
KBC_XO

SRN47-1

1
2
3
4

4
3
2
1

2
1

3
4

168
175
171
165
162
156

EZIN_EM#

1 R166

2 100KR2

USB_PWR_EN#1 R731

2 100KR2

17
C

DY

2
1

KA20GATE 21
KEY4# 35
BAT_THERMAL 47,48

1
R126 10KR2

KBRCIN# 21

SB 0201

100K PULL 3.3V


AT EZ4 SIDE

EZIN_EM# 57
ECSMI#_KBC 21
WIRELESS_EN 31
PM_CLKRUN# 18,26,29,31,37
FPBACK 17
NUM_LED# 17

R740 2 1KR2
SB 0201

PRE_CHG
EZ_PWROK
R561
1MR2

R555
10KR2

3D3V_S5

BLUETOOTH_EN 24
DC_BATFULL# 17
BLT_LED# 17
WLAN_TEST_LED 31
MAIL_LED# 17
CHARGE_LED# 17

R102
100KR2
C123

VCC3VSB
KBC_PCIRST#

AMP_SHUTDOWN 33
R103 2
LPC_RST# 13,18,37
0R0402-PAD
BL_ON 13,49
CHK_PW# 36

2 0R2-0

SC 0307

2
Q6
1
CH3906

R145

1
10KR2

RSMRST# 23

<Variant Name>

R600
13K3R2F

SB 0201

R601
100KR2F

Title

KBC KB3910
Size
A3

Document Number

Date: Thursday, March 31, 2005


4

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

24 USB_PWR_EN#

GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended)


GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended)

DY

Wistron Corporation

A1 for the internal pull-up resistors on XIOCS[F:0] pins==>High=enable,Low=Disable


A4 for DMRP==>High=Disable,Low=Enable

A5 for EMWB==>High=Enable,Low=Disable

2
0R2-0

PME#_SB 21,29

1
SC10U10V5ZY
2

3
Q8
DTC124EUA-U1
1 R168

AC_VOL_SENSE
BAT_SENSE

DY

R602
560KR2F

ECSCI#_KBC 21

R146 KBC_PME#
10KR2

C198

BT+

R599
100KR2F

18,21,38,39,43,44,55,57 PM_SLP_S3#
R127 35 KBC_PWRBTN#
47 AC_IN#
10KR2
35 KBC_LID#
21 KBC_SLP_WAKE
BRIGHTNESS 1 R746
SB 0201

R167
10KR2

1
SB 0201
1KR2
R742 2
1

AD_IA 47
KBC_BB_ENABLE# 36

2
0R0402-PAD

17
35
46
122
137
167

GND
GND
GND
GND
GND
GND

AGND
BATGND
96
159

ECRST#
ECSCI#
19
31

KB3910SF
CHANGE TO 71.03910.B0G

10KR2

3D3V_AUX_S5

KBC_BB_ENABLE#
AD_IA

TP120

AD+

1 R745

13 GMODULE_RST#

3
4
SRN8K2J

PE_REQ1# 57

EZ_PWROK 57

WIRELESS_BTN# 35

KBCRST#
2
1
R738 10KR2
SB

3D3V_AUX_S5
EC_RST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
81
82
83
84
87
88
89
90
AC_VOL_SENSE
BAT_SENSE

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
99
100
101
102
1
42
47
174
TP25

R128

DUMMY-R2

DUMMY-R2

R129

3
4

SB 0201

21 PM_PWRBTN#
21,46 RSMRST#_KBC
23 S5_ENABLE
17 BRIGHTNESS

TP119

1KR2
SB 0201

TP118

DUMMY-R2

R741 2

BRIGHTNESS_DA
GMODULE_RST#

RSMRST#_KBC

R125

DY

R130

2
1

48 BAT_SCL_5
48 BAT_SDA_5

160
158
XCLKO
XCLKI

GPIOI2D
GPIO2F
GPIO2E
GPIO2C
GPIO2B
GPIO2A

RN104
R562
1KR2

KBC_MUTE 33
KEY5# 35

FAN3FB
FAN3PWM

CAP_LED# 17
FRONT_PWRLED#

SD 0324

3
2

BAT_SCL_5
BAT_SDA_5
KBC_SCL2
KBC_SDA2

SCL1
SDA1
SCL2
SDA2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

71
72
73
74
77
78
79
80

163
164
169
170

KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8

KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16

GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
GPWU6
GPWU7
2
26
29
30
44
76
172
176

43
40
39
38
37
36
33
32
1

21 ECSWI#

R124

DY

R132
10KR2

DUMMY-R2

1
R133
10KR2

DUMMY-R2

32 KBC_BEEP

R131
10KR2

98
97
94
93
92
91

R560 2 1KR2

3D3V_AUX_S5

3D3V_S0

22 K

3D3V_AUX_S5

SC 0308

A1
A4
A5
FAN3PWM
FAN3FB

GPIO1F
GPIO1E
GPIO1D
GPIO1C
GPIO1B
GPIO1A

R148
100KR2

TP20 TPAD28
TP21

INTERNET# 35
MAIL# 35
PM_SLP_S5# 21,44,57
4S1P_I 47
PM_SUS_STAT# 21,37
SB 0128
SB 0213

1 R737
2 DY
2
1 0R2-0
R563 10KR2

SMBD_G792 23

3D3V_AUX_S5

STDBY_LED# 17

TP116

22 K

SRN10KJ

KBC_PME#

TDATA_5
TCLK_5

4
3

R134

41
28
27
25
24
23

TPAD28

3D3V_S5

RN105

1
2

VCCBAT

PS/2

GPIO0F
GPIO0E
GPIO0D
GPIO0C
GPIO0B
GPIO0A

TP19

SMBC_G792
SMBD_G792

PSDAT3
PSCLK3
PSDAT2
PSCLK2
PSDAT1
PSCLK1

KB3910

A20
E51TXD
E51RXD
E51CS#

117
116
115
114
111
110

X-bus
ROM

MATRIXID2# 36
MATRIXID1# 36
PRE_CHG 47
BLT_BTN# 35
CHG_ON# 47
AD_OFF 48

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00

155
149
148
119
118
109
108
107
106
105
86
85
75
70
69
63
62
55
54
48
22
21
20
12
11
8
6
5
4
3

KBC_SCL2

RN26

SRN10K-2

5V_S0

5
6
7
8

35 TDATA_5
35 TCLK_5

124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103

KBC_SDA2

LPC

BRIGHTNESS_PWM

57 PS2_MDAT
57 PS2_MCLK
57 PS2_KDAT
57 PS2_KCLK
5V_S0
RN27
8
7
6
5

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

D0
D1
D2
D3
D4
D5
D6
D7

KBC_SCL2
KBC_SDA2

KB Matrix

PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0

36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36

138
139
140
141
144
145
146
147

23 SMBC_G792

U20

2N7002DW

RD#
WR#
MEMCS#
IOCS#

U72

SC1U10V3ZY

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

150
151
173
152

SRN10KJ
SRN10KJ

36 KBC_D[0..7]

LFRAME#
LCLK
SERIRQ

2 C126
SC8D2P50V2CC

TP15

9
18
7

KBC_XI

KBCBIOS_RD#
KBCBIOS_WE#
KBCBIOS_CS#

36 KBCBIOS_RD#
36 KBCBIOS_WE#
36 KBCBIOS_CS#

LAD0
LAD1
LAD2
LAD3

RN102

18,37 LPC_LFRAME#
18,22 CLK33_KBC
18,26,37 P_SERIRQ

15
14
13
10

RN103

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

X6
X-32D768KHZ-12-U

18,37 LPC_LAD[0..3]

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154

2
16
34
45
123
136
157
166
95
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

C724
SCD1U16V

3D3V_KBC_AUX_S5

1
2

SCD1U16V

C709
SCD1U16V

3D3V_AUX_S5

2 C125
SC8D2P50V2CC

3D3V_S0

L3
1
2
BLM11P600S

C152

161

1
C127
SCD1U16V

C153
SCD1U16V

C228
SCD1U16V

C124
SCD1U16V

1
2

3D3V_AUX_S5

C723
SCD1U16V

Rev

-1

Bolsena
Sheet
1

34

of

58

POWER BUTTON

3D3V_AUX_S5

Cover Up Switch

3D3V_S5

Power
PWRBTN#_1
1 PWR1
2

R11
10KR2

R23
47KR2

SB 0204
R12

KBC_PWRBTN# 34

2
470R2

2
100R2F

C15
SC1000P50V2KX

34 KBC_LID#

C8
SCD1U

ME : 62.40009.241
(ALL 11 PCS)

R24

62.40009.241
4

LID1

PWRBTN#_1

3
4
SW-TACT-34-U2

LID_SW

1
2
4
4

CON2-10-U2

20.D0012.102
ME : 20.D0012.102

3D3V_S5

Buttons

1R754
1R753
1R755
1R756

10KR2
10KR2
10KR2
10KR2

MAIL#_1
KEY4#_1
KEY5#_1
INTERNET#_1

1
1
1
1

R47
R46
R45
R44

2
2
2
2

470R2
470R2
470R2
470R2

MAIL# 34
KEY4# 34
KEY5# 34
INTERNET# 34

5V_S0

TOUCH PAD

5V_S0

P2

P1

C347
SCD1U

TPAD1
C350
SC1U10V3KX

Internet

RC1
SRC100P50V-U

Mail

RN35

4
3
2
1

SB 0204

1
2

2
2
2
2

MLX-CON12-7

3
4
SW-TACT-34-U2

62.40009.241

3
4
SW-TACT-34-U2

62.40009.241

3
4
SW-TACT-34-U2

62.40009.241

R219 2 100R2F TP_DATA


1
R218 2 100R2F TP_CLK
1
TP_SCROLL_UP
C348
1 SCRL1
2

62.40009.241

3
4
SW-TACT-34-U2

62.40009.241
BlueTooth ON/OFF
1
3

WLAN1

WIRELESS_BTN#_1

4
PUSH-SW89

3
4
PUSH-SW89

?ESD ?

34 WIRELESS_BTN#
34 BLT_BTN#

1
1

R482 2 470R2
R481 2 470R2

WIRELESS_BTN#_1
BLT_BTN#_1

20.K0063.012
ME : 20.K0063.012

1 LEFT1

TP_RIGHT
1 RIGHT1
2

3
4
SW-TACT-34-U2

3
4
SW-TACT-34-U2

62.40009.241

KROW[8..1] 34
KCOL[1..16] 34

KB1

25

NC#26
C01
C02
C03
R01
R02
R03
C04
R04
R05
R06
R07
R08
R09
C05
R10
C06
C07
R11
R12
C08
R13
R14
R15
R16
NC#25
NC#27

........

3
4
SW-TACT-34-U2

62.40009.241

62.40009.241

26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27

KROW1
KROW2
KROW3
KCOL1
KCOL2
KCOL3
KROW4
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KROW5
KCOL10
KROW6
KROW7
KCOL11
KCOL12
KROW8

MLX-CON25

KCOL13
KCOL14
KCOL15
KCOL16

TP_RIGHT

EC13
1

TP_SCROLL_RIGHT

EC14
1

TP_SCROLL_UP

EC15
1

TP_SCROLL_LEFT

EC16
1

TP_SCROLL_DOWN

EC17
1

TP_LEFT

EC18
1

SC1000P50V2KX

RC7

Pin1 ==>*R01
Pin2 ==>*R02
Pin3 ==>*R03
Pin4 ==> C01
Pin5 ==> C02
Pin6 ==> C03
Pin7 ==>*R04
Pin8 ==> C04
Pin9 ==> C05
Pin10 ==> C06
Pin11 ==> C07
Pin12 ==> C08
Pin13 ==> C09
Pin14 ==>*R05
Pin15 ==> C10
Pin16 ==>*R06
Pin17 ==>*R07
Pin18 ==> C11
Pin19 ==> C12
Pin20 ==>*R08
Pin21 ==> C13
Pin22 ==> C14
Pin23 ==> C15
Pin24 ==> C16
Pin25 ==> NC

KROW7
KCOL11
KCOL12
KROW8

1
2
3
4

8
7
6
5

KCOL5
KCOL6
KCOL7
KCOL8

1
2
3
4

SRC100P50V-U
RC5
8
7
6
5

KCOL2
KCOL3
KROW4
KCOL4

1
2
3
4

SRC100P50V-U
RC4
8
7
6
5

KCOL9
KROW5
KCOL10
KROW6

1
2
3
4

SRC100P50V-U
RC6
8
7
6
5

KROW1
KROW2
KROW3
KCOL1

1
2
3
4

SRC100P50V-U
RC3
8
7
6
5

1
2
3
4

SRC100P50V-U
RC8
8
7
6
5

20.K0090.025
KCOL13
KCOL14
KCOL15
KCOL16

ME : 20.K0090.025

DY

SC1000P50V2KX

DY
SC1000P50V2KX

DY

SC1000P50V2KX

DY

SC1000P50V2KX

DY

SC1000P50V2KX

DY
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BUTTONs / KB / TOUCHPAD
Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005


B

SB 0203

<Variant Name>

SRC100P50V-U
A

TP_LEFT
2

EMI Bypass cap.

Internal KeyBoard CONN


1

1
2

SB 0127

SRN10KJ
4
3

1
13

62.40009.241

3D3V_S5
RN81

TP_LEFT

3
4
SW-TACT-34-U2

62.40009.241

SC 0310

TP_RIGHT
TP_SCROLL_RIGHT
TP_SCROLL_UP
TP_SCROLL_LEFT
TP_SCROLL_DOWN

3
4
SW-TACT-34-U2
TP_SCROLL_DOWN
1 SCRL4
2

C643
SCD1U

1
C642
SCD1U

C349

TP_SCROLL_RIGHT
1 SCRL3
2

ME : 62.40082.081
(2 PCS)

SC 0310

WIRELESS_BTN#
BLT_BTN#

TP_SCROLL_LEFT
1 SCRL2
2

Wireless ON/OFF

BLUE2
BLT_BTN#_1

14
12
11
10
9
8
7
6
5
4
3
2

4
3
34 TDATA_5
34 TCLK_5

SC47P50V2JN

3
4
SW-TACT-34-U2

1 P2

P1

KEY5#_1
2

KEY4#_1
2

SC47P50V2JN

1 MAIL1

INTERNET#_1
1 NET1
2

5
6
7
8

SRN10KJ
MAIL#_1
2

Sheet
E

35

of

58

KBC_D[0..7]

34

34 KBCBIOS_WE#
34 KBCBIOS_RD#
34 KBCBIOS_CS#
A18 34
A17 34
A16 34

1
30
2
A18
A17
A16

22
24
31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A15
A14
A13
A12
A11
A10
A9
A8

3
29
28
4
25
23
26
27

A15 34
A14 34
A13 34
A12 34
A11 34
A10 34
A9 34
A8 34

A0
A1
A2
A3
A4
A5
A6
A7

13
14
15
17
18
19
20
21

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

VSS

34
34
34
34
34
34
34
34

CE#
OE#
WE#

32

C686
U66
SCD1U16V

VDD

3D3V_AUX_S5

12
11
10
9
8
7
6
5

16

SST39VF040-70-1
(SOCKET) 62.10002.032 - (IC)72.39040.H03 IN DIP,SMT

34
34
34
34
34
34
34
34

2
1

2
1

3D3V_S0

RN30
B

SRN100KJ

3
4

3
4

RN29
SRN10KJ

ROM SIZE MAX. 512KBYTE

PLCC32 Socket P/N:


SSKT3262.10002.032
SSKT32 62.10005.032

3D3V_S0

A0
A1
A2
A3
A4
A5
A6
A7

SW1
34 KBC_BB_ENABLE#

34 CHK_PW#

34 MATRIXID1#

34 MATRIXID2#

5
SW-2184LPSTR

Keyboard matrix ( from vendor )

<Variant Name>

US

Jap

Eur

Other

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Low Bit

MATRIXID1#

High Bit

MATRIXID2#

Title

BIOS ROM
Size
A3

Document Number

Date: Thursday, March 31, 2005


5

Rev

-1

Bolsena
Sheet
1

36

of

58

PCIRST_BUF#_SIO

18,22 CLK33_SIO

LPC_LFRAME#_1
LPC_LAD0_1

3 CLK14_SIO

R63

1
33R2

1 R62
2 0R0402-PAD
1 R61
2 0R0402-PAD
SC 0308

LPC_RST# 13,18,34
P_SERIRQ 18,26,34
LPC_LDRQ0# 18
LPC_LFRAME# 18,34

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LAD[0..3]

2 R106
DUMMY-R2

1
C64
C62
3D3V_S0

DUMMY-C2

GPIO10/XA12/RI2#/JOYABTN1
GPIO11/XA13/DTR2_BOUT2#/JOYBBTP1
GPIO12/XA14/CTS2#/JOYAY
GPIO13/XA15/SOUT2/JOYBY
GPIO14/XA16/RTS2#/JOYBX
GPIO15/XA17/SIN2/JOYAX
GPIO16/XA18/DSR2#/JOYBBTN0
GPIO17/XA19/DCD2#/JOYABTN0

86
87
72
91
92
93
94
95

GPIO27/XA7/PIRQB
GPIO26/XA6/PIRQA/XSTB2#
GPIO25/XCS0#/XRDY/DR1#
GPIO24/XA4/XSTB0#
GPIO23/XA3
GPIO22/XA2
GPIO21/XA1
GPIO20/XA0

SIN1
CTS1#
DSR1#
DCD1#
RI1#

57
60
56
55
62

20
9
8
10
11
12
15
16
17
18
7
CLKIN
LRESET#
LCLK
SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LPCPD#

71
6
19
5
82
83
84
85

DTR1_BOUT1/BADDR
RTS1#/TEST
SOUT1/XCNF0
XWR#/XCNF1
XSTB1#/XCNF2/NC
XCS1#/MTR1#/DRATEO/XIOWR#

61
58
59
4
90
73

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
TRK0#
INDEX#
DSKCHG#
WP#
MTR0#
DR0#
DENSEL
DRATEO/IRSL2

23
27
26
22
29
28
25
32
21
24
31
30
33
34

ERR#/HDSEL#
AFD_DSTRB#/DENSEL/DRATE1
STB_WRITE#
PNF/XRDY#

GPIO37/DR1#/IRSL2/XIORD#
GPIO36/CLKRUN#
GPIO35/SMI#
GPIO34/XRD#/WDO#
GPIO33/XA11/MDTX/XIOWR#
GPIO32/XA10/MDRX/XIORD#
GPIO31/XA9/PIRQD/MTR1#
GPIO30/XA8/PIRQC

3D3V_S0

ENAUDIO# 33
PM_CLKRUN# 18,26,29,31,34

R104
10KR2

!for test, after ok, delete R

DY

DTR1_BOUT1_5 57
RTS1#_5 57
SOUT1_5 57
XFD_INST#

PC87392-U

51
53
54
35

89
64
38
13

PCB_VER0
PCB_VER1

VSS
VSS
VSS
VSS

1
R316
10KR2

DY

R315
10KR2

SIO_PNF

R313
10KR2

STROB#_5 58
AUTOFD#_5 58
ERROR#_5 58

R314
10KR2

DY

Infineon FIR Module

SC 0308

3D3V_S0

PRINIT#_5 58
SLCTIN#_5 58
PRNACK#_5 58
BUSY_5 58
PE_5 58
SLCT_5 58

IR1

40mil
1

58

C860
SC1U10V3KX

EZ4_PD[7..0]

EZ4_PD7
EZ4_PD6
EZ4_PD5
EZ4_PD4
EZ4_PD3
EZ4_PD2
EZ4_PD1
EZ4_PD0

0
1
0
1

PCB_VER1

0
0
1
1

PCB_VER0

Ver.
SA
SB
SC
1

Board Version Setting

PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1

SIO PC87392

52
50
48
46
45
44
43
42

3D3V_S0

81
80
79
78
77
76
75
74

SLCT/WGATE#
PE/WDATA#
BUSY_WAIT#/MTR1#
ACK#/DR1#
SLIN_ASTRB#/STEP#
INIT#/DIR#

SC 0310

GPIO00/XD0/JOYABTN1
GPIO01/XD1/JOYBBTN1
GPI002/XD2/JOYAY
GPIO03/XD3/JOYBY
GPIO04/XD4/JOYBX
GPIO05/XD5/JOYAX
GPIO06/XD6/JOYBBTN0
GPIO07/XD7/JOYABTN0

36
37
40
41
47
49

33 MIC_JKIN#

3
2
1
100
99
98
97
96

U16

SC 0310
PCB_VER0
PCB_VER1

LPCPD#

IRRX_3
IRSL0_3
IRTX_3

65

IRRX1
IRRX2_IRSL0
IRTX
IRSL1
PWUREQ#/IRSL3

VDD
VDD
VDD
VDD

SRP10K

69
68
70
67
66

C88
SCD1U16V

NC

C63
SCD1U16V

88
63
39
14

C129
SCD1U16V

3D3V_S0

C89
SC1U10V3ZY

SIO_PNF
XFD_INST#
ENAUDIO#

10
9
8
7
6

LPCPD#

RP2

1
2
3
4
5

DUMMY-C2

18,34

PM_SUS_STAT# 21,34
SIN1_5 57
CTS1#_5 57
DSR1#_5 57
DCD1#_5 57
RI1#_5 57

IRTX_3
IRRX_3
IRSL0_3

10mil
10mil
10mil

C864
SC4D7U10V5ZY

R677 2 IRMODE
10KR2

DY

1
2
3
4
5
6
7
8

VCC2/IRED_ANODE
IRED_CATHODE
TXD
RXD
SD
VCC1
MODE
GND

FIR-TFDU6102
SC 0310
<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

SUPER IO NC87392
Size
A3

Document Number

Rev
-1

Bolsena

Date: Thursday, March 31, 2005

Sheet

37

of

58

Run Power

41 12VGATE_S0

DY C574 SCD1U 5V_S0

5V_S5
U49

2
3D3V_S0
C452 SCD1U

3D3V_S5
U37

1
2
3
4

DY

C453
SCD1U

SB 0201
3

2D5V_S3

2D5V_S0

DY C763 SCD1U
1D8V_S0

2D5V_S0

D37

1
SB 0201

U76

1
2
3
4

AO4422

RB751V-40-U

8
7
6
5
1

SC1U10V3KX

AO4422
Q17
PDTC144EU

1
C600

8
7
6
5

2
1K5R3

1
R408

G
S
S
S

PM_SLP_S3#

C575
SCD1U

SB 0201
SC 0308

D
D
D
D

18,21,34,39,43,44,55,57

D19

8
7
6
5

1
2
3
4

1
G

2
Q19
2N7002

AO4422

SCD22U25V5ZY

C601

DY

R410
1KR2

R409
330KR2

MMGZ5242B

Q18
TP0610T

R413
47KR2

R411 2 PM_RUNCTL_G
330KR2

G
S
S
S

D
D
D
D

R412 2 PM_RUNCTL
10KR2

G
S
S
S

1
1

D
D
D
D

DCBATOUT

C795
SCD1U

SB 0201

1D8V_S5

1D8V_S0

DY C401 SCD1U

AO4422

8
7
6
5
1

1
2
3
4

G
S
S
S

D
D
D
D

U33

C402
SCD1U

SB 0201

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PWR CTL LOGIC / PWR PLANE


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
E

38

of

58

U54A

U54B

18,21,34,38,43,44,55,57
R442

R441 2
270KR2F

TSAHCT08-U
73.07408.0JB
4

3D3V_S5
U51C

14

1D2V_S0_EN 44

TSLCX14MTC-L-U

C609
SC1U10V3ZY

9
8

10

13 ALL_PWROK

R406 2
330R2

SB_PWRGD 21
C599
DUMMY-C3

TSLCX08-U

SD 0324

1D2V_S0_EN

VRM_PWRGD

1KR2
2

2D5V_S3

2D5V_S0

R346
10KR2

5V_S5

5V_S5
5V_S5
U44C

2D5V_S3_PG

3D3V_S5

13

VDDA_2D5_PG

11

10

12

73.07408.0JB
PM_SLP_S3#

73.07408.0JB

5V_S5

DY

TSAHCT08-U

SB 0201

R348
10KR2

SB 0201
5V_S5

DY

1
2
3
4

1D8V_S0_FB

R372
10KR2

SCD1U

DY

1OUT
1IN1IN+
GND

VCC
2OUT
2IN2IN+

8
7
6
5

DY

DY

SB 0201

1D25V_S3

R376 2
1MR2

LM393ADR
5V_S5

C572
SC1U10V3KX
2

DY
1

R374 2
47KR2

1D25V_PG_SET

DY

DY

DY

DY

C571
SCD1U

C554
SC1U10V3KX

DY

U48

Q15
PDTC144EU

1
2

1
2

DY

R373
0R2-0

1
1D8V_PG_SET
R370 2
27KR2F

1D25V_S3_PG#
R347 2
4K7R2

DY
C553

R371
1MR2
5V_S5

1D8V_S0

DY

1D25V_S3_PG

DY
DY

C570
SCD1U

R369
4K7R2

Q16
PDTC144EU

1D8V_S0_PG#

1D8V_S0_PG

VCORE_EN 41

TSAHCT08-U
73.07408.0JB

5V_S5

U41A

TSAHCT08-U

C551
SCD1U

VTT_VDDA_PG

8
7

C552
SCD1U

SD 0324

SD 0325
R407
10KR2

2D5V_S0_PG

U44D

14

14

R345
10KR2

14

SB_PWRGD IS 35MS
AFTER NB_PWRGD

U44B

PM_SLP_S3#

?U54 CHOOSE CHEAPER

220KR2J

R443

DY

5V_S5

TSLCX14MTC-L-U

NB_PWRGD_N

NB_PWRGD

Reduce leakage
(WHEN 3D3V_AUX_S5 ON, 3D3V_S0 OFF)

3D3V_AUX_S5

14

14

3D3V_AUX_S5

14

DY

R375
10KR2

DY
3D3V_S5

13 ALL_PWROK
1D8V_S0_PG

5V_S5

13

21,41 VRM_PWRGD

VRM_PWRGD

11

NB_PWRGD 13

13
7

TSLCX08-U

U41D

10

12

8
7

73.07408.0JB

VTT_VRM_PG

11
TSAHCT08-U

12

U41C

TSAHCT08-U
73.07408.0JB

ALL_PWROK

ALL_PWROK 13

9
7

VTT_1D2V_PG

14

14

PM_SLP_S3#

5V_S5

U41B

14
VTT_VDDA_PG

U51D

14

SC 0307
5V_S5

TSAHCT08-U

<Variant Name>

Wistron Corporation

23 RUNPWROK

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

POWERGOOD&ENABLES
Size
Document Number
Custom

Rev

Date: Thursday, March 31, 2005


A

-1

Bolsena
Sheet
E

39

of

58

5V_AUX_S5

CPU_CORE
MAX1544ETL
VID0_PWM
VID1_PWM
4

VID2_PWM
VID3_PWM
VID4_PWM

DCBATOUT

VID0(I / 3.3V)

INPUT

AUX_SD

Output Signal

VID Setting

VROK()

VID1(I / 3.3V)

5V_AUX_S5

OUT

SD

MAX1544_VRM

LP2951ACM
4

VID2(I / 3.3V)

1D25V_S3
2D5V_S3

VID3(I / 3.3V)

Output Power

VID4(I / 3.3V)

TI TPS5130
2D5V/1D2V/1D8V

VCC_CORE_S0(Imax=27.3A)

VCC_CORE_PWR(O)

VIN

5V_S5
APL5331_1D25V_VREF

Output Signal

Input Signal

1D25V_S0

VOUT

VCNTL
VREF

APL5331KAC
FOR
PM_SLP_S5#
SS_STBY1(I / 5V) 2.5V

Input Signal
VCORE_EN

EN (I / 3.3V)

1D2V_S0_EN

Voltage Sense
COREFB
COREFB#

S5PWR_ENABLE

VSEN(I / Vcore)
RGND(I / Vcore)

GND

FOR
SS_STBY2(I / 5V) 1.2V

DCBATOUT
5V_S0
3D3V_S0

DCBATOUT_5130

VCC(I)
DCBATOUT_5130
VCC(I)
VCC(I)

5V_S5
5V_AUX_S5

Max1999
5V/3D3V

5V_S0
2

Input Signal

Input Power

STBY_LDO(I / 5V)

5V_S0

STBY_VREF5(I / 28V)

2D5(O)

STBY_VREF3.3(I / 28V)

1D2V(O)

Output Signal

1D8V(O)

Output Power

VCC

DCBATOUT

Output Power

Input Power
DCBATOUT

FAN5234_VGA_Core
1D15V or 1D20V

Pull High (5V)

SS_STBY3(I / 5V) FOR


1.8V

Input Power

PGOUT(OD / 5V)

1D15V (O)
or
1D20V (O)

VIN

SHUTDOWN_S5
DCBATOUT
PM_SLP_S3#

ON3

Input Signal
PM_SLP_S3#

1D2V (5A)

EN
Output Signal

1D8V (5A)

PG

VIN (I / 28V)
LDO(O)

REG5V_IN(I / 5V)

Adapter

5V_AUX_S5

AD_OFF

Input Signal

Output Signal

Output Power

BT_TH

SKIP#

V+

5V(O)

5V_S5 (6A)

BAT+SENSE
BT_SCL_5

3D3V(O)

LDO5(O)

3D3V_S5 (4A)

MAX1999_LDO5 (30mA)

BT_SDA_5
FLASH_GPIO1
FLASH_GPIO2

LDO3 (O)

MAX1999_LDO3 (30mA)

AD_JK

Charger_Max8725
CHARGE_OFF

SHDN#

AD_IN

(O)

(I)

For PGOUT

MAX1999_PGD

ON5

Input Power
DCBATOUT

PGOOD(OD / 5V)

2D5V (9A)

Input Power
SHUTDOWN_S5

1D15V (5.2A)
or
1D20V (9A)

AC_IN

Input Signal

Output Signal

CLS (I / 3.3V)
THM (I / 3.3V)
BATT (I / 3.3V)

LDO (O / 5.4V)
XTAL2/PB4 (O/5V)
XTAL1/PB3 (O/5V)

5V_AUX_S5
AD_IN

Output Power

VCC(I)

AD+

VCC(O)

VCC(I)

CHARGE_LED#
BL2#

SCL (IO / 5V)


SDA (IO / 5V)
RESET#/PB5 (I/5V)
PB0/MOSI/AIN0

Output Power
VCC (O)
VCC (O)

DCBATOUT
BT+

<Variant Name>

PB0/MOSI/AIN0

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

AD+

Input Power

Title

DCIN (I)

POWER BLOCK DIAGRAM


(Power Team)

Size
A3

Document Number

Date: Thursday, March 31, 2005


A

Rev

-1

Bolsena
Sheet
E

40

of

58

5V_S0

CPU_VCORE
VID=1.20V
Iomax=27.3A (35W)
OCP=40A~45A

D42

R245
10R3

1
2
1
2

40
39

38
37

CSP
CSN

MAX1544_CCV
MAX1544_DLS 42
MAX1544_LXS 42,56

MAX1544_ILIM

MAX1544_BSTS
2 C424
SCD22U16V3KX-1

C394
SC270P50V

SC
1544_AGND
1544_AGND

41
11

R244
26K7R2F

R247
100R2F

COREFB# 6

1544_AGND

MAX1544_CCI

For alone test==>short C395 pin1 and pin2

MAX1544_CMP
COREFB 6

1
R230
0R0402-PAD

VID0
MAX1544_CMN
MAX1544_CSN

MAX1544_BSTM

GND
GND

GNDS
PGND

BSTS
35

13
31

R248
1MR2

MAX1544_FB

1
2 C373
SCD22U16V3KX-1
R223 2
3D3V_S0
100KR2

MAX1544_CSP

U28
2N7002DW

MAX1544_DLM 42
MAX1544_DHM 42
MAX1544_LXM 42,56

R226
1KR2F

SB

C395
SC1000P25V

SC470P50V
2

16
17
1

1
2

1
2

FB

OAINOAIN+
2

1
1
2

SB

MAX1544_CSP 42
MAX1544_CSN 42

1544_AGND
MAX1544_GNDS

C393
R228
511R3F

R750
1KR3F

12VGATE_S0 38

MAX1544_BSTS

SC

R246
511R3F

R749
R227
1KR3F 1KR2F
1544_AGND

MAX1544_FB

C413
SCD22U16V3KX-1

1
2
0R0402-PAD

For Dummy Phase 2

MAX1544_VCC

VRM_PWRGD 21,39

SC

R271

33

12
32
34
9

MAX1544_OAIN+
MAX1544_OAIN-

R241
80K6R3F

DHS

CCV
DLS
LXS
ILIM

MAX1544ETL

C392
SC100P

D0
D1
D2
D3
D4
OVP

1544_AGND
1544_AGND

MAX1544_V+

VID0_PWM
24
VID1_PWM
23
VID2_PWM
22
VID3_PWM
21
VID4_PWM
20
MAX1544_OVP19

100KR2

Frequency:
550KHz
300KHz
200KHz
100KHz

18
6

27
26
25

15

LXM
BSTM
VROK

1 R225

DY

29
28

MAX1544_VCC

0R2-0

DLM
DHM

S0
S1

MAX1544_ILIM

R240
60K4R3F

2 R243
1
100KR2F

1 R239

TIME
TON
SUS
OFS
REF
CCI

4
5

2
121KR2F

MAX1544_CMN 42
MAX1544_CMP 42

MAX1544_TIME 1
2
3
MAX1544_OFS 7
MAX1544_REF 8
MAX1544_CCI 14

MAX1544_REF 1 R242

VCORE_EN 39
MAX1544_DHS 42

CMN
CMP

SC

V+

10
30

U29

VCC
VDD

C372

36

MAX1544_VCC

1544_AGND

SC2D2U10V5KX
2
1

SC1U25V-U

C391

DY

R224
100KR2

SKIP#
SHDN#

1
2

R238
12K7R2F

TON:
GND
REF
OPEN
VCC

MAX1544_VCC

SC1U10V3KX

SC 0308

MAX1544_V+

1544_AGND

VCC_CORE_S0

SC 0308

VID3_PWM

U27
2N7002DW

VID2

MAX1544_BSTM

BAW56-1

C396

1544_AGND

VID1_PWM

MAX1544_SKIP#

TABLE 1. VOLTAGE IDENTIFICATION CODES


VID4 VID3 VID2 VID1 VID0 DAC
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.300
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown

VID3

MAX1544_BSTS

DCBATOUT_MAX1544

R237
0R0603-PAD

VID0_PWM

2
3

VCC_CORE_S0 feedback
6 VID[4..0]

VID1

VID2_PWM

SC:
1. Change R246 and R228 to 511R3F(64.51105.651).
2. Change R224 to 26K7R2F(64.26725.6D1).
3. Cut off a trace between pin7 and pin8 of U29.
<Variant Name>

Wistron Corporation
G

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

VID4_PWM

Title

CPU Vcore 1

2N7002
Q12
S

VID4

From KBC

Size
A3

(Power Team)
A

Document Number

Date: Thursday, March 31, 2005

Rev

-1

Bolsena
Sheet
E

41

of

58

GAP-CLOSE-PWR
GAP-CLOSE-PWR

2 DUMMY-C3

5
6
7
8

SC1U25V5ZY

TC25
SE100U25VM-1-U

D
D
D
D

SC 0310

1
TC4

TC6

TC8

TC7

ST330U3VDM-1-GP

SB

C970

TC23

ST330U3VDM-1-GP

TC5

C824

DCBATOUT_MAX1544

DY
1

2 C820
SC10U35V0ZY-L

GAP-CLOSE-PWR

G75

DY

ST330U3VDM-1-GP

VCC_CORE_S0

2 C819
SC10U35V0ZY-L

ST330U3VDM-1-GP

GAP-CLOSE-PWR

ST330U3VDM-1-GP

2 C822
SC10U35V0ZY-L

GAP-CLOSE-PWR

2
G74

SC 0311

ST330U3VDM-1-GP

G73

SC1U25V5ZY

GAP-CLOSE-PWR

C969

2
G72

G71

DCBATOUT

2
G70

GAP-CLOSE-PWR

G69

SC 0310

SB
AO4422
U100

Panasonic 0.56uH, 10*10*4


DCR=1.6mohm,
Imax=15A(0.56uH), 27A(0.5uH)

4
3
2
1

G
S
S
S

SC 0311

L33

41 MAX1544_DHM

41,56 MAX1544_LXM
3

KEMET 330uF / 3V / 80.3371X.L02


ESR=9mohm / Iripple=3.7A
7.3/4.3/1.9, NT:9.0

VCC_CORE_S0

41 MAX1544_DLM

1 R619

D001R7520F
3

L-D56UH-U
D
D
D
D

5
6
7
8

U101

R229
0R0402-PAD

AO4430

4
3
2
1

S
S
S
G

Place 0R0402-PAD close to the resistor


SB 0201
MAX1544_CMN 41
MAX1544_CMP 41

DCBATOUT_MAX1544

4
3
2
1

G
S
S
S

D
D
D
D

5
6
7
8

SC 0311

2 C960
SC10U35V0ZY-L

AO4422
U99

SB

Panasonic 0.56uH, 10*10*4


DCR=1.6mohm,
Imax=15A(0.56uH), 27A(0.5uH)
VCC_CORE_S0

L34

41 MAX1544_DHS

41,56 MAX1544_LXS
41 MAX1544_DLS

D001R7520F

L-D56UH-U

1 R752

5
6
7
8

U102

D
D
D
D

AO4430

<Variant Name>

4
3
2
1

S
S
S
G

SB 0203
R282
0R0402-PAD

Wistron Corporation

MAX1544_CSN 41
MAX1544_CSP 41

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU Vcore 2
(Power Team)

Size
A3

Document Number

Date: Thursday, March 31, 2005


A

Rev

-1

Bolsena
Sheet
E

42

of

58

SYSTEM DC/DC
3D3V_S5/5V_S5

DCBATOUT

GAP-CLOSE-PWR
G101
2

GAP-CLOSE-PWR
G39
2

GAP-CLOSE-PWR
G104
2

GAP-CLOSE-PWR
G38
2

GAP-CLOSE-PWR
G103
2

GAP-CLOSE-PWR
G40
2

GAP-CLOSE-PWR
G102
2

GAP-CLOSE-PWR
G100
2

GAP-CLOSE-PWR
G99
2

GAP-CLOSE-PWR
G93
2

MAX1999_LDO5
DCBATOUT_MAX1999_1

MAX1999_LX5

2
2

C899
SCD1U16V

R352 2
100KR2

AO4422

R681
2MR2

SHDN#

R333 C522
SC100P50V2JN

MAX1999_ILIM5

ILIM3

MAX1999_ILIM3

MAX1999_PGD

REF

PGOOD

25

23

R331
51K1R2F

R354
33KR2F

DY

MAX1999_LDO5

R353
9K76R2F

Open Drian

SC

MAX1999EEI

GND

R682
DUMMY-R3

LDO5

Ton = VCC : 200KHz/300KHz


Ton = GND : 400KHz/500KHz
(5V/3D3V)

18

SKIP#

LDO3

12

C520
MAX1999_SKIP#
SCD22U16V3ZY

MAX1999_FB5
R310 2
10KR2

11

2
8

ILIM5
TON

R356
2
DUMMY-R3
MAX1999_REF

13

MAX1999_REF

MAX1999_TON

KEMET, NT:8.22
ESR=25mohm
Iripple=2.2A
7.3/4.3/1.9

15KR2F

DY

2
10KR2
1

TC28
80.22715.191
ST220U6D3VDM-4

SC 0308

MAX1999_PRO#1

10
1

PRO#
NC

1 R357

MAX1999_VCC

C863
SC47P50V2JN

DY
MAX1999_LX5_1

MAX1999_FB3

R332
10K2R2F

2
U46

MAX1999_FB5

ON3
ON5

5V_DC_S5

2
IND-6D8UH-14
68.6R810.10A

MAX1999_SHDN#

FB5

MAX1999_DL5

5
6
7
8
2 0R2-0
SC 0308
R334 2
1
3
23,44 S5PWR_ENABLE 0R0402-PAD 4

Imax=6.0A,
DCR=25mohm
12*12*3.9

L32

21

OUT5

FB3

Iomax=5A
OCP:8A~10A

OUT3

7
1

SB 0127

22

MAX1999_REF

C576
SC10U35V0ZY-L

15
19

84.04422.037

AO4422

LX5
DL5

DY
R309

GAP-CLOSE-PWR

1
MAX1999_DH5

DL3

44 5130_PGOUT

1
16

LX3

DCR=25mohm DY
MAX1999_LX3_1
12*12*3.9

C557
SCD1U

17
VCC
DH5

24

DY

C577
SC4D7U25V6KX-U

MAX1999_LX5 56

27

R679
2MR2

5
6
7
8

2
V+

14

MAX1999_DL3

R329
6K65R2F

DY

SC 0310

MAX1999_BST5_1

BST5

MAX1999_LX3

KEMET, NT=6.35
ST150U6D3VDM-9
80.15715.191
ESR=40mohm
Iripple=1.7A
7.3/4.3/1.9

20

MAX1999_BST3_1
28 BST3

DH3

1
2

SC100P50V2JN

1
1
2

SC 0308

R358

C555
SCD1U
GAP-CLOSE-PWR

U42

26

2
IND-6D8UH-14
68.6R810.10A
C862
Imax=6.0A,
SC47P50V2JN

C521

1
2
300KR2F

S
S
S
G

1
2
3
4

GAP-CLOSE-PWR

MAX1999_DH3

TC16
C859
ST150U6D3VDM-9
80.15715.191
SCD1U16V

U50
MAX1999_BST5

R311

L31

DCBATOUT_MAX1999
78.47522.521

SB 0127

56 MAX1999_LX3

3D3V_DC_S5

2 C556
SC1U10V3KX

BAW56-1

C493
SCD1U

SC 0310
SB 0202

2
10R3

D15

1
2
3
4

8
7
6
5
D
D
D
D

U38
AO4406
84.04406.037

Iomax=4.0A
OCP:7A~9A

C523

MAX1999_BST3
R680

AO4422

C524

SCD1U

1
2

C494 DY
SC10U35V0ZY-L

84.04422.037

G
S
S
S

C495
SCD1U

SB 0127

U39

SC1U25V5ZY
2

8
7
6
5

1 R360

D
D
D
D

R336 2
4D7R5

MAX1999_VCC

G
S
S
S

D
D
D
D

GAP-CLOSE-PWR

GAP-CLOSE-PWR

5V_S5

4
3
2
1

GAP-CLOSE-PWR
G91
2

5V_DC_S5

D
D
D
D

GAP-CLOSE-PWR
G88
2

DCBATOUT_MAX1999

DCBATOUT_MAX1999

G
S
S
S

3D3V_S5

GAP-CLOSE-PWR
G37
2

4
3
2
1

GAP-CLOSE-PWR
G92
DCBATOUT_MAX1999
2

GAP-CLOSE-PWR
G87
2

G98

3D3V_DC_S5

2
GAP-CLOSE-PWR
G89
2

G36

G90

R359
MAX1999_ILIM5_3

MAX1999_VCC

GAP-CLOSE-PWR

OCP Setting
MAX1999_LDO5

MAX1999_LDO3

30mA MAX.

30mA MAX.

MAX1999_ILIM5_3

MAX1999_SHDN#

SB 0201
C525
SC1U25V5ZY

R678
100KR2

2N7002DW

C861
SCD1U

R355
100KR2
U45

2
5V_AUX_S5
0R3-U

DY

R350
100KR2

1 R335

MAX1999_VCC

MAX1999_VCC

SC1U25V5ZY

C526

MAX1999_SKIP#

MAX1999_ILIM5

Wistron Corporation
R330
10KR2F-U

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

R351
10KR2F-U

MAX1999_SKIP

<Variant Name>

MAX1999_ILIM3

PM_SLP_S3# 18,21,34,38,39,44,55,57

Max1999 / 3D3V / 5V
Size
A3

Adjust 3V/5V current limit

(Power Team)

Document Number

Date: Thursday, March 31, 2005

Rev

-1

Bolsena
Sheet
E

43

of

58

(2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3)


For 1.2V
SETTING=1.2172V

2 C840
SC4700P50V3KX

C352
1
2

R653
2
4K32R2F

close to IC
1

R234
2KR2F

close to IC

5130_5V_LDO

C378
SC3300P50V3KX

2 C374
SC5600P50V3KX

2
1
330R2

5130_FB2

78.56224.2B1
2
19K6R3F

Condition

R231
2KR2F

Voltage

H : Auto PWM/SKIP

PWM_SEL

1 2

L : PWM fixed (300KHz)

1D8V_OCP
R222

5130_OUT1U 45
5130_OUT1D 45

SC

10

3
2

5130_SS_STBY2 6

5130_SS_STBY1

4
PM_SLP_S5 5

1D2V_S0_EN#

R657
100KR2

5130_FB1
5130_SS_STBY1
5130_INV2
5130_FB2
5130_SS_STBY2
5130_PWMSEL
5130_CT

PM_SLP_S3#

2
DUMMY-R2

5130_REF

SC4700P50V3KX

R658
R656
100KR2

C379

DCBATOUT_5130

1 R235

2
100KR2

STBY_REF
5130_STBY_LDO

1
2
3
4
5
6
7
8
9
10
11
12

5130_LH2 1

C354
2

LL2
OUT2_U
LH2
VIN
VREF3.3
VREF5
REG5V_IN
LDO_IN
LDO_CUR
LDO_GATE
LDO_OUT
INV_LDO

5130_LL2 45,56

36
35
34
33
32
31
30
29
28
27
26
25

close to IC

2
7

5130_LH3 1

2N7002DW

5130_OUT2U

5130_REGIN

5130_OUT2U 45

1 R651
2
0R0805-PAD

5130_3D3V_LDO

5130_5V_LDO
2 C355
SCD1U50V3KX

R660
10KR2

S5PWR_ENABLE 23,43
5130_SS_STBY3

DY

1
2

84.27002.03F

C384
SC1500P50V3KX

43 5130_PGOUT

5V_AUX_S5

5130_3D3V_LDO

GAP-CLOSE
ZZ.CON2C.XX1
SC 0310

C357
SC4D7U10V5ZY
78.47593.411

C356
SC4D7U10V5ZY
78.47593.411

0R3-U

5130_OUT3D 45
5130_OUT3U 45

2 C358
5130_LL3 45,56
SCD1U50V3KX
SC 0310
5130_5V_LDO

PWM_SEL
*

3
83.00054.L03

Condition

Voltage

H : Auto PWM/SKIP

2.2V(Min)~

L : PWM fixed (300KHz)

~0.3V(Max)

2
DCBATOUT_5130

BAT54-1
5130_TRIP3

<Variant Name>

1
5130_REF

C382
SC2200P50V2KX

Wistron Corporation

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

1
R661
0R0402-PAD

DY

5130_STBY_LDO

2
0R2-0
1

1 R659

PM_SLP_S3#

SB 0201

A
18,21,34,38,39,43,55,57

5V_S5

SC 0308

1
5130_PG_DELAY

G79

TPS5130PT-U

D13
R664 2
TPS5130_1D8V_EN#
100KR2

GAP-CLOSE-PWR
G83
2

5130_SS_STBY3
5130_FB3
5130_INV3

5V_S0

SB 0201

13
14
15
16
17
18
19
20
21
22
23
24

C380
SC47P50V2JN
78.47034.1F1

TSLCX14MTC-L-U

U89

GAP-CLOSE-PWR
G84
2

GAP-CLOSE
ZZ.CON2C.XX1
G114
1
2

DCBATOUT_5130

SS_STBY3
FB3
INV3
PGOUT
PG_DELAY
TRIP3
VIN_SENSE3
LH3
OUT3_U
LL3
OUT3_D
OUTGND3

5130_CT

5130_OUT3D
5130_LL3
5130_OUT3U
5V_AUX_S5

5130_LL2
SCD1U50V3KX

1 R650

1D2V_S0_EN#

GAP-CLOSE-PWR
G77
2

SC 0310

14

G113

TPS5130

B
9

GAP-CLOSE-PWR
G80
2

U26

FB1
SS_STBY1
INV2
FB2
SS_STBY2
PWM_SEL
CT
GND
REF
STBY_VREF5
STBY_VREF3.3
STBY_LDO

3D3V_AUX_S5

39 1D2V_S0_EN

GAP-CLOSE
ZZ.CON2C.XX1

LDO SETTING

U54D

GAP-CLOSE-PWR
G81
2

5130_OUT2D 45

48
47
46
45
44
43
42
41
40
39
38
37

SC1500P50V3KX
5130_3D3V_LDO

11

GAP-CLOSE-PWR
G78
2

OCP
8.4A=>R229=12.65K
10A=>R229=22K

21,34,57 PM_SLP_S5#

2N7002DW

14

U54E
TSLCX14MTC-L-U

5130_OUT2D

INV1
FLT
LH1
OUT1_U
LL1
OUT1_D
OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2
OUT2_D

U88

GAP-CLOSE-PWR
SCD1U

close to IC
5130_FLT
5130_INV1

C375
SCD01U16V2KX

T(soft)=1.736ms

3D3V_AUX_S5

DCBATOUT_5130

2
12K1R2F
C359
1
2

DCBATOUT_5130

5130_FLT

1
C377

5130_TRIP1
5130_TRIP2

OCP
8.4A=>R226=13K
10A=>R226=22K

5130_TRIP3

~0.3V(Max)

C376 5130_INV1
SC3900P50V3KX
5130_FB1
SB 0201

SCD1U

close to IC

5130_LL1 45,56

5130_OUT1U
5130_OUT1D

2.2V(Min)~

close to IC
*

2 C353 5130_LL1
SCD1U50V3KX

DCBATOUT_5130

C351
1
2

D11
83.00054.L03
BAT54-1

BAT54-1
5130_LH1

1 R655

2
GAP-CLOSE-PWR
G82
2

2
11K3R2F

5130_TRIP2

SC 0310

R649 2
10KR2F-U

5130_INV2

2D5V_PWR

1 R232

R220

SC
83.00054.L03

OCP
12A=>R225=18K
18A=>R225=28K

1D2V_OCP

D12

1 2

For 2.5V
SETTING=2.516V

SCD1U

5130_5V_LDO

C383 5130_INV3
SC3900P50V3KX
5130_FB3

2
1
680R3F

2
10KR2F-U

1 2

close to IC

DCBATOUT_5130

18KR2F

5130_TRIP1

1 R233

G76

R221

SC

1D2V_PWR

1 R654

R652
2KR2F

DCBATOUT_5130

2D5V_OCP

2 C360
SC5600P50V3KX

78.56224.2B1
R663 2
11K5R2F

DCBATOUT

Vo=(R1*0.85)/R2+0.85

R236 2
1
680R3F

R662 2
10KR2F-U

1D8V_PWR

TI TPS5130 for 2.5V, 1.2V, 1.8V

For 1.8V
SETTING=1.8275V
1

C381
SC1U10V3ZY

SB 0201

Title

TPS5130 1D2V/1D8V2D5V/ (1/2)


SC 0308

Size
A3

SB 0201

(Power Team)

Document Number

Rev

Bolsena

Date: Thursday, March 31, 2005

-1
Sheet

44

of

58

TI TPS5130 for 2D5V, 1D2V, 1D8V

(2D5V=>CH1 , 1D2V=>CH2 , 1D8V =>CH3)

2D5V_PWR
L28

2
IND-4D7UH-16-GP
68.4R71B.101

D
D
D
D

SB 0127

2D5V
Iomax=9A
OCP>18A

TC12
ST220U4VDM-10

TC13
ST330U6D3VDM-7

5130_OUT1D

DCBATOUT_5130

GAP-CLOSE-PWR
G28
2

GAP-CLOSE-PWR
G22
2

GAP-CLOSE-PWR
G26
2

GAP-CLOSE-PWR
G25
2

GAP-CLOSE-PWR
G23
2

GAP-CLOSE-PWR
G24
2

SC 0310

SC 0310

2
GAP-CLOSE-PWR
G27
2

DY

KEMET, NTD:10.5 (Q1)


ESR=25mohm
Iripple=2.2A
7.3*4.3*1.9

4
3
2
1

SC 0310

44 5130_OUT1D

SC 0310

G
S
S
S

U86
AO4422

2D5V_S3
G21

5130_OUT1U
5130_LL1

Imax=9.3A
Rdson=19.6~24mohm

5
6
7
8

44 5130_OUT1U
44,56 5130_LL1

2D5V_PWR
C841
SC10U35V0ZY-L

D
D
D
D

4
3
2
1

G
S
S
S

U91
AO4422

C839
SCD1U

5
6
7
8

DCBATOUT_5130

1
2

C837
SCD1U

C838
SC10U35V0ZY-L
SB 0127

D
D
D
D

U84
AO4422

5
6
7
8

GAP-CLOSE-PWR

1D2V_PWR

1D2V_S0

G
S
S
S

4
3
2
1
44 5130_OUT2U
44,56 5130_LL2

Imax=9.3A
Rdson=19.6~24mohm
1D2V_PWR

L27

5130_OUT2U
5130_LL2

TC11
ST220U4VDM-10

GAP-CLOSE-PWR
G19
2

GAP-CLOSE-PWR
G16
2

GAP-CLOSE-PWR
G17
2

GAP-CLOSE-PWR
G18
2

GAP-CLOSE-PWR
G14
2

GAP-CLOSE-PWR
G15
2

SB 0127

Imax=9.3A
Rdson=19.6~24mohm

5130_OUT2D

G
S
S
S

1
2

Imax=9.3A
Rdson=19.6~24mohm
1D8V_PWR

L29

5130_OUT3U
5130_LL3

4
3
2
1

G
S
S
S

Imax=5.5A
DCR=40mOhm
7*7*3.0

44 5130_OUT3D

5130_OUT3D

Imax=9.3A
Rdson=19.6~24mohm

2
GAP-CLOSE-PWR

1D8V
Iomax=5A
OCP>10A

TC14
ST220U4VDM-13

KEMET, NTD:7.8 (Q1)


ESR=25mohm
Iripple=2.2A
7.3*4.3*1.9

GAP-CLOSE-PWR
G34
2

GAP-CLOSE-PWR
G33
2

GAP-CLOSE-PWR
G32
2

GAP-CLOSE-PWR
G31
2

GAP-CLOSE-PWR
G30
2

GAP-CLOSE-PWR
G29
2

U93
AO4422

D
D
D
D

5
6
7
8

IND-4D7UH-16-GP

G65

1D8V_S5

1
SB 0127

4
3
2
1
44 5130_OUT3U
44,56 5130_LL3

GAP-CLOSE-PWR

G35

C848
SC10U35V0ZY-L

D
D
D
D

5
6
7
8

1D8V_PWR

U92
AO4422

GAP-CLOSE-PWR

DCBATOUT_5130

C847
SCD1U

B
44 5130_OUT2D

1D2V_VGA_S0
G66

4
3
2
1

G
S
S
S

1D2V
Iomax=5A
OCP>10A

Imax=6A
DCR=30mOhm
7*7*3.0

D
D
D
D

5
6
7
8

IND-3D3UH-35
U87
AO4422

1D2V_S0

G20

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GAP-CLOSE-PWR

(Power Team)

<Variant Name>

TPS5130 1D2V/1D8V2D5V/ (2/2)


Size
A3

Document Number

Date: Thursday, March 31, 2005

Rev
-1

Bolsena
Sheet

45

of

58

3D3V_G913_S5

3D3V_G913_S5
C965

U103

1
1

Output = 3.5V
output=1.25(1+(Rx/Ry))

Ra change from 169K to 182K for output = 3.4827V


output=1.235(1+(Ra/Rb))

3D3V_AUX_S5

R135

3D3V_G913_S5 D54

182KR2F

Ra

3D3V_AUX_LP2951_S5

2 C156 LP2951ACM_FB
SC330P50V2KX
DCBATOUT

CH521S-30

CH521S-30

OUT
INPUT
SENSE
FB
SD
5V/TAP
100mA
GND
ERROR

8
7
6
5

C157
DUMMY-C5

R136
100KR2F

LP2951ACM

C158
SC1U50V5ZY
78.10594.411

Rb
2

C154
SC1U10V3ZY

C155
SCD1U

U19

1
2
3
4

Ry

D55

R762
10KR2F-U

C967

1
2

G913C-U

3D3V_G913_SET

OUT

3D3V_AUX_S5

SET

SC1U10V3KX

SHDN#
GND
IN

C966
SC1U10V3KX

1
2
3

5V_S5

Rx
R761
18KR2F

SC22P50V2JN-1

DY

21,34 RSMRST#_KBC
3

SD 0303

5V_S5
C895
SC10U10V5ZY
78.10693.411

1
2

2D5V_S3 DY

C902
SCD1U

1D25V_S3
Iomax=1.5A

G95 GAP-CLOSE-PWR
2

G97 GAP-CLOSE-PWR
2

NC
NC
NC

8
7
5

DY

G96 GAP-CLOSE-PWR
2
1D25V_S3

G94 GAP-CLOSE-PWR
2

GND
GND

TC27
SE100U10VM

2
9

1
C897
SCD1U

VOUT

C898
SC22U10V6ZY-L

SB 0127

79.10711.4C1

R684
1KR2F

VIN
VREF
VCNTL

4
1

APL5331_1D25V_VREF

1
3
6

1D25V_LDO

U96

Vo(cal.)=1.250V
R683
1KR2F

C896
SC10U10V5ZY
78.10693.411

2D5V_S3

APL5331KAC-TR

SO-8-P

SB 0127

KEMET
100uF / 4V / B2 Size / NTD:5.615
Iripple=1.1A / ESR=70mohm

Trace Length=1cm (500mils)


Trace Width=8mils
Trace Resistance>25mohm

<Variant Name>
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1D2V_S3 / 3D3V_AUX
Size
A3

(Power Team)
A

Document Number

Date: Thursday, March 31, 2005

Rev

-1

Bolsena
Sheet
E

46

of

58

BT+
DCBATOUT

For EMI

C430
SCD1U

G51

G52

R285
DUMMY-R3

SC 0308

C687
SC1U50V5ZY

MAX1909_ACIN

Close to
MAX1909 pin 24

R283

D46

CCV
CCI
CCS

MAX8725ETI

C844
SCD1U16V3KX

C842
SCD1U16V3KX

1
2

SC10U25V0KX

1
2

SC10U25V6KX

SC10U25V0KX

1
1

G115 GAP-CLOSE
2

G116 GAP-CLOSE
2

SB 0127

MAX1909_LDO

R289
68KR2F
R286
2

34,48 BAT_THERMAL

MAX1909_CLS
SC 0310

PKPRES#

0R0402-PAD

R287
100KR2

90W ADAPTER

R673
63K4R3F
64.63425.651

Rx

C431

BAT+SENSE 48

From Battery Connector

1
MAX1909_LDO

1
2

4
3
2
1
5
6
7
8
5
6
7
8
D
D
D
D

2
GAP-CLOSE-PWR

R674
49K9R2F

C854
SC1U10V3KX

GAP-CLOSE-PWR

17
16
15

CSIN
BATT
GND

18

V_REF :4.2235V (<500uA)

CSIP

G86
1

C432

C845
SCD01U50V3KX
C843
SCD01U50V3KX

29

DY
C428

DY

PKPRES

1
1

1
10KR2F-U

19

PGND

G42

13
12
14

PGND

G41

MAX1909_CCV
MAX1909_CCI
MAX1909_CCS

SC 0310

ACOK

MAX1909_REF

R666

B220LFA

CLS
G
S
S
S

MAX1909_ACOK 6

BT+

R284 2
D015R2512F-1

D14

MAX1909_DLO

1
1

20

1
IND-15UH-30

2 CHG_PWR-3 1

DLO

G85
GAP-CLOSE-PWR

2
2

U30
SI4800BDY
84.04800.B37

4
3
2
1

2N7002
Q34

From Battery Connector

25
CSSN

26
CSSP

IINP

CHG_PWR-2

SC 0310

L30

2N7002
Q14

CHG_PWR-3 56
CHG_PWR-2 56
SC 0310

C858
SC1U10V3KX

GAP-CLOSE-PWR

R670
10KR2
1

8
9

PKPRES#
D

MAX1909_DHI

C426
SC10U25V6KX

SC 0310

Near MAX1909
Pin 21

REF

3 2
2

1
G

34 4S1P_I

CELL is 4 Cell

SB 0202

34 AD_IA

ACIN

SB 0213

1
G

DHI

23

C427
SC10U25V6KX

R675
33R2

SB 0202

34 PRE_CHG

MAX1909_DLOV

2
1

MAX1909_IINP
MAX1909_CLS

Pre charge=2.967A

DLOV

21

VCTL
ICTL
MODE

R270
2K8R3F-L

DHIV
PDL
LDO

1
2

2
1

R757
33KR2F

R667
51K1R2F

2N7002
Q13

PDS
SRC
DCIN

C425
SCD1U

From KBC

Icharge=2.967A

1
G

34 CHG_ON#

MAX1909_VCTL 11
MAX1909_ICTL 10
MAX1909_MODE 7

R269
100KR2

R668
49K9R2F

R669
100KR2

22
28
2

U34
SI4431BDY
84.04431.C37

D
D
D
D

R268
100KR2

MAX1909_PDS27
AD+_TO_SYS 24
MAX1909_DC_IN
1

2 C434
SC1U10V3KX

S
S
S
G

3D3V_S5

U94

Near MAX1909
Pin 2

C857
SCD1U

MAX1909_DHIV

MAX1909_REF

DCBATOUT

MAX1909_LDO

C433
SCD1U

MAX1909_LDO

8
7
6
5

1
C855
SCD1U

1
2

C856
SCD1U

CH521S-30

D
D
D
D

DUMMY-R3

AD+_TO_SYS

2
1

AD+

DY

C429
SCD1U

AO4407

ACOK is 17.8V

8
7
6
5

GAP-CLOSE-PWR
GAP-CLOSE-PWR

R514
13K3R2F

1
2
3
4

AO4407
U36
S
S
S
G

D
D
D
D

AC_IN Threshold 2.089V Max.


AC_IN > 2.089V --> AC DETECT

MAX1909_PDL

U35
S
S
S
G

AO4407

1
2
3
4

D01R2512F-1-GP

R518 2

AD+_TO_SYS

1
2
3
4
1

1
R513
100KR2F

S
S
S
G

Rx

U62
D
D
D
D

8
7
6
5

AD+

DY

MAX1909_ACOK

ISOURCE_MAX = (0.075/Rx)*(VCLS/VREF)
TOTAL_POWER :
Adapter=65W,Total_Power=58.5W

C853
SC1U10V3KX

<Variant Name>

Wistron Corporation

R665
15KR2F

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

TSLCX14MTC-L-U

34 AC_IN#

R288
10KR2

U54C
2

14

3D3V_AUX_S5

Title

SC 0302

CHARGER MAX8725
Size
Custom

(Power Team)

Document Number

Rev

Bolsena

Date: Thursday, March 31, 2005

-1
Sheet

47

of

58

Adaptor in to generate DCBATOUT


SB 0127
R8

0R5J-1
2
R729 0R5J-1
2
R730 0R5J-1
2

1
1
DOCK_AD+

AD_JK_1

D31

G48 GAP-CLOSE-PWR
1
2

Dummy when 'USE EZ4'

AD+

PZM24NB1
AD_JK_1

AD_JK

8
7
6
5

C670
SCD1U

AO4407
R502

ID = -10A/70deg
Rds(ON) = 24mohm
SO-8

DC-JACK75-U

22.10037.701
ME : 22.10037.701

Q2
PDTA124EU

100KR2
C7
SCD1U50V3ZY

Dummy when no EZ4

5
6
MH1

D
D
D
D

SBM1040CT-13

SCD1U50V3ZY

AD+_2

C662

SCD1U50V3ZY

1
C661

DY
U63
S
S
S
G

R503
56KR3F

Q1
DTC124EUA-U1

G49 GAP-CLOSE-PWR
1
2

1
2
3
4

DC1

G50 GAP-CLOSE-PWR
1
2

D29

G47 GAP-CLOSE-PWR
1
2

22 K

2
1

34 AD_OFF
R9
1KR2

22 K

5V_AUX_S5

D45

BATTERY CONNECTOR
D44

DY

83.00099.L01
BAV99-2

SC10P50V2JN-1

SC1000P50V2KX

C849

SC1000P50V2KX

SC10P50V2JN-1
2

1
SCD1U50V3ZY
2

SCD1U50V3ZY

C852

ME : 20.80269.007

SD 0324

1
2
3

HTH
GND
LTH

11.25V (Low)
VCC

RESET#/RESET

Turn Off
LOW3_OFF 23

DY

R266
15KR2F

G680LT1

<Variant Name>

Output type: DY
Open-Drain RESET#

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY
Title
SB

AD/BATT CONN
Size
A3

R265
110KR2F

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005


A

20.80269.007

U31
HTH

C851

SYN-CON7-9

EC11

Turn On

DY

HTH

C850

EC12

12.78V (High)

DY

C403
SCD1U10V2MX-1

R267
1MR2

BTSMCLK
BTSMDATA

MAX1999_LDO5

DCBATOUT

L3# at 11.25V

Put close to battery connector

DY

Low3 Circuit :

2
3
4
5
6
7

R672 2
0R0402-PAD

SD 0324

83.00099.L01
BAV99-2
1 R671
2
27R3F
R676 2
27R3F

DY

34 BAT_SCL_5
34 BAT_SDA_5
BT+ 34,47 BAT_THERMAL
47 BAT+SENSE

BAT1

CHANGE TO 20.80605.007

Sheet
E

48

of

58

U70A

3D3V_S0

3D3V_S0

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

SCD1U16V
C195
C193
C194
C192
C190
C188
C191
C189
C187
C185
C183
C181
C186
C184
C182
C180
C178
C176
C179
C177
C175
C173
C171
C169
C174
C172
C170
C168
C166
C164
C167
C165

PEG_TXP0_VGA
PEG_TXP1_VGA
PEG_TXP2_VGA
PEG_TXP3_VGA
PEG_TXP4_VGA
PEG_TXP5_VGA
PEG_TXP6_VGA
PEG_TXP7_VGA
PEG_TXP8_VGA
PEG_TXP9_VGA
PEG_TXP10_VGA
PEG_TXP11_VGA
PEG_TXP12_VGA
PEG_TXP13_VGA
PEG_TXP14_VGA
PEG_TXP15_VGA

R123
DUMMY-R2

R118
10KR2

AF26
PEG_TXN0_VGA AE26
AC25
PEG_TXN1_VGA AB25
AC27
PEG_TXN2_VGA AB27
AC26
PEG_TXN3_VGA AB26
Y25
PEG_TXN4_VGA W25
Y27
PEG_TXN5_VGA W27
Y26
PEG_TXN6_VGA W26
U25
PEG_TXN7_VGA T25
U27
PEG_TXN8_VGA T27
U26
PEG_TXN9_VGA T26
P25
PEG_TXN10_VGA N25
P27
PEG_TXN11_VGA N27
P26
PEG_TXN12_VGA N26
L25
PEG_TXN13_VGA K25
L27
PEG_TXN14_VGA K27
L26
PEG_TXN15_VGA K26

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_3
VREFG

PCIE_REFCLKP
PCIE_REFCLKN

PCIE_CALP_VGA
PCIE_CALN_VGA
PCIE_CALI_VGA

AC23
AB24
AB23

PCIE_CALRP
PCIE_CALRN
PCIE_CALI

PCIE_TESTIN

AE25

PCIE_TESTIN

AD25
AD24

PERSTb
PERSTb_MASK

AH21

R2SET

AK21
AJ22
AK22

Y_G
C_R_PR
COMP_B_PB

2
1
2 150R2F 1 R551
2 150R2F 1 R542
150R2F
R541

2 715R3F

3D3V_S0

RN22

4
3

SRN10KJ
1
2

AJ24
AK24

VGA_SMB_CLK
VGA_SMB_DAT

54 VGA_SMB_CLK
54 VGA_SMB_DAT
13,17 EDID_CLK
13,17 EDID_DAT

PWRGD_MASK

RN23 3 SRN0-2-U 2
4
1

1 R553
1 R120

2 10KR2
2 10KR2

VGA_SSIN
VGA_SSOUT
XTALIN_M24

SB 0127

TP75

1 R122
1 R77
1 R69

2 1KR2
2 1KR2
2 1KR2

TESTEN

TP18
STERE0SYNC

H2SYNC
V2SYNC

AG22
AG23

DDC3CLK
DDC3DATA

AJ23
AH24

SSIN
SSOUT

AH28

XTALIN

AJ29

XTALOUT

AH27
E8
B6
AF25

TESTEN
TEST_YCLK
TEST_MCLK
PLLTEST

AH25

STEREOSYNC

TMDS

13 AG_RST#

The PERSTB must deplay 4ms from M24 bug.


1 R101

57 DIS_LUMA
57 DIS_CRMA
57 DIS_COMP

10KR2

DAC1

R111 2

THERM

SC 0308

2 150R2F
2 100R2F
2 10KR2F-U

DAC2

R121
0R0402-PAD

R119
DUMMY-R2

1 R97
1 R144
1 R110

CLK SS

PWRGD_MASK

STERE0SYNC

1D2V_VGA_S0

3D3V_S0

1
1
1
1

1D8V_S0
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD

2
2
2
2

TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
BLON

AE12
AG12

ATI_LCDVDD_ON
BL_ON 13,34

TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP

AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12

TMDS_DIS_TX0TMDS_DIS_TX0+
TMDS_DIS_TX1TMDS_DIS_TX1+
TMDS_DIS_TX2TMDS_DIS_TX2+
TMDS_DIS_TXCTMDS_DIS_TXC+

DDC2CLK
DDC2DATA

AE13
AE14

HPD1

AF12

R
G
B

AK27
AJ27
AJ26

HSYNC
VSYNC

AJ25
AK25

RSET

AH26

DDC1DATA
DDC1CLK

AG25
AF24

GPIO_AUXWIN

AG24

DPLUS
DMINUS

AF11
AE11

ATI_TXAOUT0ATI_TXAOUT0+
ATI_TXAOUT1ATI_TXAOUT1+
ATI_TXAOUT2ATI_TXAOUT2+
ATI_TXAOUT3TP74
ATI_TXAOUT3+
TP17

ATI_TXBOUT3ATI_TXBOUT3+

DEFAULT

CAL_BG_BACKUP

GPIO0

GPIO1

PCIE_MODE(1:0)

GPIO(3:2)

00

CAL_OFF

GPIO4

BYPASS_PLL

GPIO5

ICOMP

GPIO6

GPIO8

SB 0219

SB 0219

ROMIDCFG(3:0)

GPIO(9,13:11)

0000

MULTIFUNC(1:0)

LCDDATA(17:16)

00

VIP_DEVICE

LCDDATA(20)

DWNGR0

LCDDATA(21)
0
(internal pull-down)

0
C

ATI Ref. Datasheets(page 3-32)


DOC.NO.:CHS-216M24-03
GPIO[0..13] are internal
pull-down.
TMDS_DIS_TX0TMDS_DIS_TX1TMDS_DIS_TX2TMDS_DIS_TXC-

R83

1
1
1
1

R95
R96
R98
R94

2
2
2
2

330R2
330R2
330R2
330R2

TMDS_DIS_TX0+
TMDS_DIS_TX1+
TMDS_DIS_TX2+
TMDS_DIS_TXC+

SC 0225

DVPDATA_2,
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

ATI_TXACLK- 54
ATI_TXACLK+ 54
ATI_TXBOUT0- 54
ATI_TXBOUT0+ 54
ATI_TXBOUT1- 54
ATI_TXBOUT1+ 54
ATI_TXBOUT2- 54
ATI_TXBOUT2+ 54

TP14
TP13

PIN

PLL_CAL_FORCE_EN

R84
100R2F

54
54
54
54
54
54

1, 0
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB

Hynix
Samsung
X brand
Y brand
Hynix
Samsung
X brand
Y brand

FOR M24

FOR M26

ATI_TXBCLK- 54
ATI_TXBCLK+ 54

RN25
TMDS_DIS_TX0TMDS_DIS_TX0+
TMDS_DIS_TXC+
TMDS_DIS_TXC-

54

1
2
3
4

8
7
6
5
SRN0-1-U

TMDS_DIS_TX2TMDS_DIS_TX2+
TMDS_DIS_TX1TMDS_DIS_TX1+

TMDS_EZ4_TX0TMDS_EZ4_TX0+
TMDS_EZ4_TXC+
TMDS_EZ4_TXC-

15,57
15,57
15,57
15,57

TMDS_EZ4_TX2TMDS_EZ4_TX2+
TMDS_EZ4_TX1TMDS_EZ4_TX1+

15,57
15,57
15,57
15,57

RN24

1
2
3
4

SB 0213

8
7
6
5
SRN0-1-U

DIS_DVI_DDC_C
DIS_DVI_DDC_D

15
15

RN17

Place Near To EZPORT4


DVI_HPD 15
DIS_R 57
DIS_G 57
DIS_B 57

DIS_HS 16
DIS_VS 16

1 R552

GPIO_AUXWIN 54

2
470R2F

SC 0228

DIS_CRT_DDC_D
DIS_CRT_DDC_C

16
16

VGA_LOCAL_DP 23,54
VGA_LOCAL_DN 23,54

1
2
VGA_GPIO11 3
VGA_GPIO10 4

8
7
6
5

VGA_GPIO9 1
VGA_GPIO6 2
VGA_GPIO7 3
4

SRN10K-2
RN18
8
7
6
5

R93
100KR2

SC 0228
<Variant Name>

SRN10K-2

Wistron Corporation

R117 2
10KR2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

Dummy when use ''M24'

ATI M26 PCIE LVDS (1/3)


Size
A3

M26-P-1
(M24)71.00M24.C0U - (M26)71.0M26P.00U
5

STRAPS

VGA_VREFG

AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20

DEBUG_ACCESS

TP6
TP5

C82

AF27
AE27

3 GFX_CLK
3 GFX_CLK#

M26 : HYNIX 128MB 1.8V,64MB 1.8V


M24 : HYNIX 64MB 1.8V

AJ10 DVPCNTL0_VGA
AK10 DVPCNTL1_VGA
AJ11 DVPCNTL2_VGA
AH11 DVPCNTL3_VGA
AG4

DUMMY-R2
3D3V_S0

SC 0225

SC 0308
R543
R532
R539
R540

R81 1

DUMMY-R2

Dummy when use ''M24'

VGA_SDA1
VGA_SCL1

2 DUMMY-R2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2 DUMMY-R2

VGA_GPIO5

PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PEG_TXP4
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXP9
PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15

adjust SWING at 1.2v

2 DUMMY-R2

VGA_GPIO3 R527 1

NO USE DVPDATA

100R2F

R85
105R3F

DVPDATA_0 R533 1
2
CHECK VRAM TYPE AND SIZE
DVPDATA_1 R528 1
2
CHECK VRAM TYPE AND SIZE
DVPDATA_2
R529 2
1
1KR2
CHECK VRAM TYPE AND SIZE

VGA_GPIO2 R530 1

C53
SC270P50V

AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

3D3V_S0

3.3V MODE
to 1.8V 1.8V MODE

C54
SCD01U16V2KX

XTALIN_M24

DVOMODE
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DPVDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

SB 0215
for REVERSE LANE
VGA_GPIO0
R531 2 10KR2
1
VGA_GPIO4
R526 2 10KR2
1

2
620R2F

R86
180R2F

R53

ORIGNAL
P2779A-08TT
USE W180-01
GEOMETRY

C698
SCD1U

P2779A-08ST
71.02779.00A

SC27P50V2JN

C83

SC 0308

3D3V_SS_S0
P2779A_REF
VGA_GPIO16

8
7
6
5

VDD
REF
MODOUT
VSS

12

XIN/CLKIN
XOUT
PD#
LF

VGA_GPIO0
3D3V_S0
VGA_GPIO1
R758 2 10KR2
1
VGA_GPIO2
for EYE DIAGRAM
SC 0219
VGA_GPIO3
VGA_GPIO4
VGA_GPIO5
VGA_GPIO6
VGA_GPIO7
VGA_GPIO8
VGA_GPIO9
TP10
MUST TO CHECK
VGA_GPIO10
VGA_GPIO11
DVOMODE=VSS
VGA_GPIO12
TP11
VGA_GPIO13
TP9
DVOMODE=VDDC
VGA_ALERT#
VGA_ALERT# 54
R82 1
2
GPIO_PWRCNTL 55
DVOMODE=GND
0R0402-PAD
SC 0309
VGA_GPIO16
VGA_DVOMODE 1 R92
2 0R0402-PAD

SCD1U16V

1
2
3
4

X-27MHZ-7-U
P2779A_XO

1MR2

R55

AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

R554 1 102R2F 2
R549 1 102R2F 2
R550 1 102R2F 2

X1

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO_PWRCNTL
GPIO_MEMSSIN

Part 1 of 6

DVO / EXT TMDS / GPIO

2
1

P2779A_XI

1
1

U14

C58
SC27P50V2JN
2

R534
0R0805-PAD

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N

LVDS

3D3V_S0

12 PEG_TXP[15..0]
12 PEG_TXN[15..0]
12 PEG_RXP[15..0]
12 PEG_RXN[15..0]

AH30
AG30
AG29
AF29
AE29
AE30
AD30
AD29
AC29
AB29
AB30
AA30
AA29
Y29
W29
W30
V30
V29
U29
T29
T30
R30
R29
P29
N29
N30
M30
M29
L29
K29
K30
J30

PCI EXPRESS

Dummy when use UMA (WHOLE PAGE)

PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
PEG_RXP4
PEG_RXN4
PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
PEG_RXP7
PEG_RXN7
PEG_RXP8
PEG_RXN8
PEG_RXP9
PEG_RXN9
PEG_RXP10
PEG_RXN10
PEG_RXP11
PEG_RXN11
PEG_RXP12
PEG_RXN12
PEG_RXP13
PEG_RXN13
PEG_RXP14
PEG_RXN14
PEG_RXP15
PEG_RXN15

Document Number

Rev
-1

Bolsena

Date: Thursday, March 31, 2005

Sheet
1

49

of

58

LPVDD
TPVDD

AF13
AF14

TXVDDR#AF13
TXVDDR#AF14

SC 0308

SC1U10V3KX

C151 C150

1 R114
2
0R0603-PAD

SC1U10V3KX

SC 0308

SC10U10V5ZY SC10U10V5ZY
2
1
2
1

C149 C148

R116 2
1
0R0603-PAD
1 R115
2
0R0603-PAD

AF21
AE20

A2VDD#AF21
A2VDD#AE20

1D8V_A2VDDQ_S0

AF23

A2VDDQ

1D8V_AVDD

AH23

AVDD

1 R112
21D8V_DDQ
0R0603-PAD

AE23
AE22

VDD1DI
VDD2DI

SC 0308
1D8V_PVDD_S0

AK28

PVDD

1D8V_A2VDD_S0

1D8V_S0

A7

MPVDD

LVSSR#AF18
LVSSR#AH17
LVSSR#AG15
LVSSR#AG18

AF18
AH17
AG15
AG18

LPVSS
TPVSS

AH18
AH12

TXVSSR#AH12
TXVSSR#AG13
TXVSSR#AG14

AH14
AG13
AG14

A2VSSN#AH20
A2VSSN#AG21

AH20
AG21

A2VSSQ

AF22

AVSSN

AH22

VSS1DI
VSS2DI

AE24
AE21

PVSS

AJ28

MPVSS

M26-P-1
(M24)71.00M24.C0U - (M26)71.0M26P.00U

2
SCD01U16V2KX

2
SCD01U16V2KX

2
SCD01U16V2KX

2
SCD01U16V2KX

2
SCD01U16V2KX

2
SCD01U16V2KX

2
SCD01U16V2KX

2
SC1U10V3KX

2
SC1U10V3KX

2
ST100U6D3VDM-5

SCD01U16V2KX

A6

DIODE SUPPLIES POWER


TO VDDC RAIL
WHILE VDDC REGULATOR
STABALIZES DURING POWER ON

C109

SC1U10V3KX

C102

SC1U10V3KX

C96

SC1U10V3KX

1
1
2

SCD01U16V2KX
2

SC330P50V2KX

SC10U10V5ZY
2

1
C140

C141C718C139

SC 0308

C146 C147C720
SCD01U16V2KX

SC1U10V3KX

2
1

C719
SCD01U16V2KX
2

1
2

AD22

DIODE SUPPLIES POWER


TO VDDC RAIL
WHILE VDDC REGULATOR
STABALIZES DURING POWER ON

2 R557
1
0R0603-PAD
SC 0308
PCIE_PVDD_12
M22 Power
150mA + margin (transition, 4us duration)
andUP
90mA + margin (continuous).

Squence

3D3_VDDR3

T1 < 1mS

3D3_VDDR4

T2 < 1mS
T3 < 1uS

2D5_VDDR1

T4 < 100nS

1D2_VDDC
1D8V_S0

C142

PCIE_VDDR_12

T5 < 100nS

PCIE_PVDD_12

T6 < 1uS

C145

C143

C144
SC10U10V5ZY

C107

2 R113
1
0R0603-PAD
SC330P50V2KX

F19
M6

2 R558
1
0R0603-PAD

1D2V_VGA_PVDD

AVSSQ

VSSRH0
VSSRH1

2
SCD01U16V2KX

1
2

SCD01U16V2KX

1
2

SCD01U16V2KX

SC10U10V5ZY

SCD01U16V2KX

1
2
1

C196

C197

VDDRH0
VDDRH1

C714 C715

2
1
2

C721

SCD01U16V2KX

F18
N6

SC1U10V3KX

SC10U10V5ZY
2
1

SC 0308

C103

1D2V_VGA_S0
1D2V_VGA_VDDR

SCD01U16V2KX
2

AH19
AH13

C99

PCIE_VDDR_12
1.6A + margin (transition, 4us duration) and
1.1A + margin (continuous).

SC 0308

SCD01U16V2KX
2

LVDDR_25#AE16
LVDDR_25#AE17
LVDDR_18#AF15
LVDDR_18#AE15

SC10U10V5ZY

D9
D13
D19
D25
E4
T4
AB4

C81

1D8V_VGA_PVDD
1D8V_TVDD_S0

C119 C111

1 R545
2
0R0603-PAD

1 R67
2
0R0603-PAD

NC#D9
NC#D13
NC#D19
NC#D25
NC#E4
NC#T4
NC#AB4

1D8V_S0

2D5V_S0

U23
T23
V23
W23

C80

SCD01U16V2KX

SC100P50V2JN

SC1U10V3KX
2
1

C118 C117

SC 0308

AE16
AE17
AF15
AE15

C100 C106 C97

1 R80
2
0R0603-PAD

1 R100
2
0R0603-PAD

SC100P50V2JN

C116

PCIE_PVDD_18#U23
PCIE_PVDD_18#T23
PCIE_PVDD_18#V23
PCIE_PVDD_18#W23

3D3V_VDDR4

SC 0308

N24
N23
P23

SC 0308

C722
C752
SC1U10V3KX
SC1U10V3KX

SC330P50V2KX
2

1 R99
2
0R0603-PAD

C105 C110 C98

C137

1 R559
2
0R0603-PAD

1D8V_S0

PCIE_PVDD_12#N24
PCIE_PVDD_12#N23
PCIE_PVDD_12#P23

3D3V_S0
3D3V_VDDR3

SB 0201

DY

1D5V_VGA_S0

SCD01U16V2KX

C115

AG26
AK29
AJ30
AG28
AG27

TC20

C112

SB

2
0R3-U

PCIE_VDDR_12#AG26
PCIE_VDDR_12#AK29
PCIE_VDDR_12#AJ30
PCIE_VDDR_12#AG29
PCIE_VDDR_12#AH29

C114

DY

1 R544

CHANGE TO 74.05308.E31

AG7
AD9
AC9
AC10
AD10

C113

SSM5818SL

SC1U10V3KX

2D5V_S0

VDDR4#AG7
VDDR4#AD9
VDDR4#AC9
VDDR4#AC10
VDDR4#AD10

C101

DY
3D3V_S0

SSM5818SL
VGA_CORE_S0
2

D33

APL5308-15AC-TR

VDDR3#AD7
VDDR3#AD19
VDDR3#AD21
VDDR3#AC22
VDDR3#AC8
VDDR3#AC21
VDDR3#AC19

AD7
AD19
AD21
AC22
AC8
AC21
AC19

3D3V_S0

DY

SC1U10V3KX
2

2
SC1U10V3KX

DY

2
0R3-U

DY

P8
Y8
AC11
AC20
H20
H11
M23
Y23

SC10U10V5ZY

C121

VDD15#P8
VDD15#Y8
VDD15#AC11
VDD15#AC20
VDD15#H20
VDD15#H11
VDD15#M23
VDD15#Y23

C104

1 R546

2
1

AC13
AD13
AD15
AC15
AC17

I/O POWER

VOUT
VIN
GND

SCD1U16V

2D5V_2D8V_LVDDR_S0

C122

2D8V_S0

U17

DY

3D3V_S0

VDDC#AC13
VDDC#AD13
VDDC#AD15
VDDC#AC15
VDDC#AC17

2D8V_S0

VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L8
VDDR1#K23
VDDR1#K24
VDDR1#N4
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1#A9
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#L23

ST100U6D3VDM-5

TC2

T7
R4
R1
N8
N7
M4
L8
K23
K24
N4
J8
J7
J4
J1
H10
H13
H15
H17
T8
V4
V7
V8
AA1
AA4
AA7
AA8
A3
A9
A15
A21
A28
B1
B30
D26
D23
D20
D17
D14
D11
D8
D5
E27
F4
G7
G10
G13
G15
G19
G22
G27
H22
H19
AD4
L23

Part 4 of 6

1
2

SCD01U16V2KX

C76

C135
SC10U10V5ZY

SC1U10V3KX

C74

SC1U10V3KX
2

C95
SCD01U16V2KX

1
1

SCD01U16V2KX

1
SCD01U16V2KX

C79

SC1U10V3KX
2

C77

SCD01U16V2KX

C136

C78

SCD01U16V2KX

C92

C75

C94
SCD01U16V2KX

1
2

SCD01U16V2KX

C93

current of power to VDDC on M26 is up to


10A + margin (25% or more).

U70D

1D8V_S0

E
D32

SC1U10V3KX

SC10U10V5ZY

A
Dummy when use UMA (WHOLE PAGE)

SC 0308

T7 < 100nS

VDD_15
PCIE_PVDD_18

PCIE_PVDDR_18
800mA + margin (transition, 4us duration) and
330mA + margin (continuous).

ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED


PLACED CLOSE TO THE POWER/GND PINS
WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC

<Variant Name>

Wistron Corporation

1D8V_MPVDD_S0

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

SC 0308
Title

ATI M26 POWER (2/3)


Size
A3

Document Number

Date: Thursday, March 31, 2005

Rev

-1

Bolsena
Sheet

50

of

58

RASA#

A19

CASA#

E18

CASA# 52

WEA#

E19

WEA# 52

CSA0#

E20

CSA1#

F20

CKEA

B19

CKEA

1 R90

2
10KR2

CKEB

1 R78

2
10KR2

RASA# 52

CSA#0 52
CSA#1

CSA#1 52
CKEA 52

B21
C20

CLKA0 52
CLKA#0 52

CLKA1
CLKA1#

C18
A18

CLKA1 52
CLKA#1 52

1D8V_S0
SB 0201

CLKA0
CLKA0#

ATI_MVREFS

D30 DIMA_0
B13 DIMA_1

1D8V_S0

R71
100R2F
TP16
TP12

SB 0201
C73
SCD1U16V

DIMA_0
DIMA_1

B8

ATI_MVREFD

MVREFS

B7

MVREFD

R70
100R2F

R68
100R2F

2
1
2

R89
100R2F

C91
SCD1U16V

As close to
CHIP as
possible

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

E6
B2
J5
G3
W6
W2
AC6
AD2

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

F6
B3
K6
G1
V5
W1
AC5
AD1

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

MAB[13..0] 53
VGA_CORE_S0

U70F

QSB[7..0] 53

RASB#

R2

RASB# 53

CASB#

T5

CASB# 53
WEB# 53

WEB#

T6

CSB0#

R5

CSB1#

R6

CSB#0 53
CSB#1

CKEB

R3

CKEB 53

N1
N2

CLKB0 53
CLKB#0 53

CLKB1
CLKB1#

T2
T3

CLKB1 53
CLKB#1 53

DIMB_0
DIMB_1

E3
AA3

TP3
TP4

TPAD30
TPAD30

ROMCS#

AF5

TP7

TPAD30

C6
C7

MEMTEST

C8

VGA_CORE_S0
R91
1

SC 0308

M22,24,26P
:Not
connected

MEMORY CHANNEL B
M24 use 45ohm 1%
M26 use 240ohm 1%

R75
45R2F

R76
240R2F

W16
M15
R19
T12

C108
SC330P50V2KX

1D8V_S0

R74

When use M22/24P

DY

10KR2

R73

M26-P-1
(M24)71.00M24.C0U - (M26)71.0M26P.00U

M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16

VDDC#P17Part 6 of 6 VSS#M16
VDDC#P18
VSS#N16
VDDC#P19
VSS#N15
VDDC#U12
VSS#P15
VDDC#U13
VSS#P16
VDDC#U14
VSS#R18
VDDC#U17
VSS#R17
VDDC#U18
VSS#R16
VDDC#U19
VSS#R15
VDDC#V19
VSS#R14
VDDC#V18
VSS#R13
VDDC#V17
VSS#R12
VDDC#V14
VSS#T13
VDDC#V13
VSS#T14
VDDC#V12
VSS#T15
VDDC#N18
VSS#W15
VDDC#N17
VSS#V16
VDDC#N14
VSS#V15
VDDC#W17
VSS#U15
VDDC#W18
VSS#U16
VDDC#W12
VSS#T19
VDDC#W13
VSS#T18
VDDC#W14
VSS#T17
VDDC#N13
VSS#T16
VDDC#N19
VDDC#M19
VDDC#M18
VDDC#M12
VDDC#N12
VDDC#M13
VDDC#M14
VDDC1#W16
VDDC#P12
VDDC1#M15
VDDC#P13
VDDC1#R19
VDDC#P14
VDDC1#T12
VDDC#M17
VDDC#W19

M26-P-1
(M24)71.00M24.C0U - (M26)71.0M26P.00U
VGA_CORE_VDDCI
0R0603-PAD
2

CSB#1 53

CLKB0
CLKB0#

MEMVMODE_0
MEMVMODE_1

P17
P18
P19
U12
U13
U14
U17
U18
U19
V19
V18
V17
V14
V13
V12
N18
N17
N14
W17
W18
W12
W13
W14
N13
N19
M19
M18
M12
N12
M13
M14
P12
P13
P14
M17
W19

DQMB#[7..0] 53

R72
10KR2

PIN

C6

C7

1.8V =

PD

PU

2.5V =

PU

PD

10KR2

R51
10KR2

DY

Dummy when use ''M26'


*When use M26, pin C6 = GPIO_17, C7 = NC

M22,24,26P
:Not
connected

MEMORY CHANNEL A

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

CENTER ARRAY

J27
F30
F24
B27
E16
B16
B11
F10

QSA[7..0] 52

N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

Part 3 of 6

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

DQMA#[7..0] 52

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

D7
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

J25
F29
E25
A27
F15
C15
C11
E11

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

M26-P-1
(M24)71.00M24.C0U - (M26)71.0M26P.00U

E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19

MAA[13..0] 52

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

Part 2 of 6

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63

MEMORY INTERFACE A

H28
H29
J28
J29
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8

MEMORY INTERFACE B

U70B
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

D
U70C

52 MDA[63..0]

53 MDB[63..0]

A
Dummy when use UMA (WHOLE PAGE)

K28
L28
M27
M26
M24
M25
M28
P28
N28
R25
R23
R24
R26
R27
R28
T28
T24
U28
V24
V26
V27
V25
V28
Y28
W24
W28
AA26
AA27
AA23
AA24
AA25
AA28
AB28
AC28
AD28
AD26
AD27
AE28
AF28
AH29

CORE GND

Part 5 of 6

VSS#U4
VSS#U8
VSS#W7
VSS#W8
VSS#Y4
VSS#AB8
VSS#AB7
VSS#AB1
VSS#AC4
VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD18
VSS#AK2
VSS#AJ1

U70E

PCIE_VSS#K28
PCIE_VSS#L28
PCIE_VSS#M27
PCIE_VSS#M26
PCIE_VSS#M24
PCIE_VSS#M25
PCIE_VSS#M28
PCIE_VSS#P28
PCIE_VSS#N28
PCIE_VSS#R25
PCIE_VSS#R23
PCIE_VSS#R24
PCIE_VSS#R26
PCIE_VSS#R27
PCIE_VSS#R28
PCIE_VSS#T28
PCIE_VSS#T24
PCIE_VSS#U28
PCIE_VSS#V24
PCIE_VSS#V26
PCIE_VSS#V27
PCIE_VSS#V25
PCIE_VSS#V28
PCIE_VSS#Y28
PCIE_VSS#W23
PCIE_VSS#W28
PCIE_VSS#AA26
PCIE_VSS#AA27
PCIE_VSS#AA23
PCIE_VSS#AA24
PCIE_VSS#AA25
PCIE_VSS#AA28
PCIE_VSS#AB28
PCIE_VSS#AC28
PCIE_VSS#AD28
PCIE_VSS#AD26
PCIE_VSS#AD27
PCIE_VSS#AE28
PCIE_VSS#AF28
PCIE_VSS#AH29

U4
U8
W7
W8
Y4
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD18
AK2
AJ1

Dummy when use ''M24'

MVDDQ=
1.8v/ 2.5v

VDDR1

1.8V

MEMVMODE_0

GND

MEMVMODE_1

+VDDC_CT
SB 0127

2.5V

+VDDC_CT

2.8V

+VDDC_CT

GND

+VDDC_CT

VSS#R7
VSS#P4
VSS#M7
VSS#M8
VSS#L4
VSS#K1
VSS#K7
VSS#K8
VSS#R8
VSS#T1

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R7
P4
M7
M8
L4
K1
K7
K8
R8
T1

VSS#AD12
VSS#AG5
VSS#AG9
VSS#AG11
AD12
AG5
AG9
AG11

VSS#F27
VSS#G9
VSS#G12
VSS#G16
VSS#G18
VSS#G21
VSS#G24
VSS#H27
VSS#H23
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9
VSS#H8
VSS#H4
VSS#J23
VSS#J24
F27
G9
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
H9
H8
H4
J23
J24

A2
A10
A16
A22
A29
C1
C3
C28
C30
D27
D24
D21
D18
D15
D12
D10
D6
D4

VSS#A2
VSS#A10
VSS#A16
VSS#A22
VSS#A29
VSS#C1
VSS#C3
VSS#C28
VSS#C30
VSS#D27
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#D10
VSS#D6
VSS#D4

SB 0127

Title

ATI M26 MEM (3/3)


Size
A3

Document Number

Date: Thursday, March 31, 2005

Rev

-1

Bolsena
Sheet

51

of

58

Dummy when use UMA (WHOLE PAGE)

1D8V_S0

SB 0201

SB 0201

MCL/DSF

1
2

C65
SCD1U16V

DQMA#2
QSA2

H12
H13

H12
H13

DM1
DQS1

HY5DS573222F-28
HY5DS573222F-28 (M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
4 of 5
4 of 5
U69D

U71D

G3
K3
J3
F3
J2
G2
F2
K2

DQ18
DQ23
DQ20
DQ16
DQ21
DQ19
DQ17
DQ22

H3
H2

DM2
DQS2

MDA37
MDA35
MDA34
MDA39
MDA33
MDA36
MDA38
MDA32

G3
K3
J3
F3
J2
G2
F2
K2

DQ18
DQ23
DQ20
DQ16
DQ21
DQ19
DQ17
DQ22

H3
H2

DM2
DQS2

M13

VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
MCL/DSF

HY5DS573222F-28

VREF

1
SC10U10V5ZY

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

SB 0201
1D8V_S0

N13

R520
1KR2F

C689
SCD1U16V

MDA6
MDA2
MDA0
MDA7
MDA1
MDA4
MDA5
MDA3

DQMA#6
QSA6

DM1
DQS1

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

C702

R64

1
1

HY5DS573222F-28
HY5DS573222F-28
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
3 of 5
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U U69C
3 of 5
U71C
MDA49 K13
MDA21 K13
MDA53 G13 DQ8
MDA18 G13 DQ8
MDA54 G12 DQ12
MDA17 G12 DQ12
MDA50 J13 DQ13
MDA22 J13 DQ13
MDA52 F13 DQ10
DQ10
MDA19 F13
MDA48 K12 DQ14
MDA23 K12 DQ14
MDA55 F12 DQ9
MDA16 F12 DQ9
MDA51 J12 DQ15
DQ11
MDA20 J12 DQ15
DQ11

CKE
CLK
CLK#

60D4R2F

R49

2
2

51 CKEA
10R3
N12
VDDRA_CLK1+
1
M11
VDDRA_CLK1- M12
1
10R3

60D4R2F

2 R66
R65
2

CLOSE TO MEM !!

SC10U10V5ZY

SCD01U16V2KX

SC330P50V2KX

DM0
DQS0

51 CLKA1
51 CLKA#1

C692

DQMA#0
QSA0

DQMA#4
QSA4

HY5DS573222F-28
HY5DS573222F-28
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
U71E 5 of 5
U69E 5 of 5
MDA26
MDA31
MDA30
MDA24
MDA27
MDA25
MDA29
MDA28

SB 0201
1D8V_S0

D12
D13
E13
C9
B10
B8
C13
B9

DQ26
DQ25
DQ24
DQ30
DQ28
DQ31
DQ27
DQ29

B12
B13

DM3
DQS3

MDA58
MDA63
MDA61
MDA56
MDA59
MDA57
MDA62
MDA60

D12
D13
E13
C9
B10
B8
C13
B9

DQ26
DQ25
DQ24
DQ30
DQ28
DQ31
DQ27
DQ29

B12
B13

DM3
DQS3

VDDR_VREF2

(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U

N13

B3
B2

DQMA#5
QSA5

BA0
BA1
NC#M10

MAA12
MAA13

C688
SCD1U16V

R519
1KR2F

VREF

DQ3
DQ1
DQ2
DQ0
DQ6
DQ5
DQ4
DQ7

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

1
2

SC330P50V2KX

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DM0
DQS0

B5
C6
B6
B7
D2
D3
C2
E2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

SB 0201

1D8V_S0

Layout trace 20 mil

R547
1KR2F

C708
SCD1U16V

DQMA#3
QSA3

DQMA#7
QSA7

HY5DS573222F-28

NC#C4
NC#C11
NC#H4
NC#H11
NC#L12
NC#L13
NC#M3
NC#N3

M13

VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL

C4
C11
H4
H11
L12
L13
M3
N3

F6
C132
F7
SCD1U16V F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

B3
B2

N4
M5
M10

2 of 5

U69B
MDA45
MDA46
MDA43
MDA44
MDA42
MDA40
MDA47
MDA41

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
NC#L9

D7
D8
E4
E11
L4
L7
L8
L11

BC751_1

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

C711

DQ3
DQ1
DQ2
DQ0
DQ6
DQ5
DQ4
DQ7

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
L9

NC#C4
NC#C11
NC#H4
NC#H11
NC#L12
NC#L13
NC#M3
NC#N3

60D4R2F

R108

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQMA#1
QSA1
SB 0201

C703

2 of 5

U71B

B5
C6
B6
B7
D2
D3
C2
E2

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C4
C11
H4
H11
L12
L13
M3
N3

CKE
CLK
CLK#

2
2

N12
VDDRA_CLK0+
M11
VDDRA_CLK0- M12

60D4R2F

R88

BA0
BA1
NC#M10

51 CKEA

1
1

R107
2 R109
1
2 10R3
1
10R3

CLOSE TO MEM !!

51 CLKA0
51 CLKA#0

N4
M5
M10

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

C69
C71
SC330P50V2KX SCD01U16V2KX

RAS#
CAS#
WE#
CS#
NC#M4

MAA12
MAA13

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

1D8V_S0

SC10U10V5ZY

D7
D8
E4
E11
L4
L7
L8
L11

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
NC#L9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

MAA0
N5
MAA1
N6
MAA2
M6
MAA3
N7
MAA4
N8
MAA5
M9
MAA6
N9
MAA7 N10
MAA8 N11
MAA9
M8
MAA10 L6
MAA11 M7
L9

C162

MDA12
MDA11
MDA9
MDA10
MDA13
MDA8
MDA15
MDA14

RAS#
CAS#
WE#
CS#
NC#M4

C701

M2
L2
L3
N2
M4

BC752_1

M2
L2
L3
N2
M4

C138

1 of 5

U71A

51 RASA#
51 CASA#
51 WEA#
51 CSA#0
51 CSA#1

1
2

SC330P50V2KX

C713
SC330P50V2KX

1
C712

SC330P50V2KX

C163

SC330P50V2KX

C131

SC330P50V2KX

C66

SC330P50V2KX

RASA#
CASA#
WEA#
CSA#0
CSA#1

SC10U10V5ZY

C133
SCD1U16V

C72
SCD1U16V

51 MAA[13..0]
C705
51 DQMA#[7..0]
SCD01U16V2KX

1
C690
SCD1U16V

C704
SCD1U16V

1
2

C691
SCD1U16V

51 QSA[7..0]

C134

1 of 5

U69A

51 MDA[63..0]

1
C41
SCD1U16V

C67
SCD1U16V

C68
SCD1U16V

C70
SCD1U16V

All dampings in this page must near the VRAM.


C90
SCD1U16V

1D8V_S0

<Variant Name>

1
C707
SCD1U16V

R548
1KR2F

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

CLOSE TO MEM

HY5DS573222F-28
HY5DS573222F-28
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U

VDDR_VREF1

(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U

Title

ATI VRAM (1/2)

Layout trace 20 mil

Size
A3

Document Number

Rev

Date: Thursday, March 31, 2005


5

-1

Bolsena
Sheet
1

52

of

58

1D8V_S0

51 MDB[63..0]

MCL/DSF

VREF

DM0
DQS0

BA0
BA1
NC#M10

51 CKEB
51 CLKB1
51 CLKB#1

2
2

R31
R32

1 10R3
1 10R3

N12
VDDRC_CLK1+M11
VDDRC_CLK1- M12

CKE
CLK
CLK#

MDB14
MDB9
MDB11
MDB13
MDB10
MDB15
MDB12
MDB8
DQMB#1
QSB1

DQ8
DQ12
DQ13
DQ10
DQ14
DQ9
DQ15
DQ11

1
1
1

K13
G13
G12
J13
F13
K12
F12
J12

F6 VSS_THERMAL
F7 VSS_THERMAL
F8 VSS_THERMAL
F9 VSS_THERMAL
G6 VSS_THERMAL
DQMB#7
H12 DM1
H12 DM1
G7 VSS_THERMAL
QSB7
H13 DQS1
H13 DQS1
G8 VSS_THERMAL
G9 VSS_THERMAL
H6 VSS_THERMAL
H7 VSS_THERMAL
HY5DS573222F-28
HY5DS573222F-28
H8 VSS_THERMAL
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB)
(M24 72.55732.B0U
HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
4 of 5
4 of 5
U64D
U65D
H9 VSS_THERMAL
J6 VSS_THERMAL
MDB43
G3 DQ18
G3 DQ18
J7 VSS_THERMAL
MDB47 K3
K3 DQ23
J8 VSS_THERMAL
DQ23
MDB45 J3
J3 DQ20
J9 VSS_THERMAL
MDB42 F3 DQ20
F3 DQ16
DQ16
MDB44
J2 DQ21
J2 DQ21
M13 MCL/DSF
MDB40 G2
G2 DQ19
MDB41 F2 DQ19
F2 DQ17
MDB46 K2 DQ17
K2 DQ22
DQ22
H3
H2

DQMB#5
QSB5

DM2
DQS2

H3
H2

C23

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

VREF

N13

C684

C679

SB 0201

1D8V_S0

R510
1KR2F

C682
HY5DS573222F-28
SCD1U16V
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U

DM2
DQS2

DQMB#3
QSB3

MDB63
MDB59
MDB58
MDB60
MDB56
MDB62
MDB57
MDB61

DQ8
DQ12
DQ13
DQ10
DQ14
DQ9
DQ15
DQ11

SCD1U16V

C675
SC10U10V5ZY

K13
G13
G12
J13
F13
K12
F12
J12

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

N4
M5
M10

2
2

B3
B2

MAB12
MAB13

SB 0201

DQMB#4
QSB4

DQ3
DQ1
DQ2
DQ0
DQ6
DQ5
DQ4
DQ7

CLOSE TO MEM !!

MDB28
MDB29
MDB31
MDB25
MDB26
MDB27
MDB24
MDB30

HY5DS573222F-28
HY5DS573222F-28
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
U64E 5 of 5
U65E 5 of 5

DQMB#2
QSB2

D12
D13
E13
C9
B10
B8
C13
B9

DQ26
DQ25
DQ24
DQ30
DQ28
DQ31
DQ27
DQ29

B12
B13

DM3
DQS3

MDB53
MDB54
MDB52
MDB51
MDB50
MDB49
MDB55
MDB48
DQMB#6
QSB6

CLOSE TO MEM
D12
D13
E13
C9
B10
B8
C13
B9

DQ26
DQ25
DQ24
DQ30
DQ28
DQ31
DQ27
DQ29

B12
B13

DM3
DQS3

C681
SCD1U16V

R509
1KR2F

MDB20
MDB23
MDB22
MDB16
MDB19
MDB17
MDB21
MDB18

VDDR_VREF4

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

C672

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DM0
DQS0

B5
C6
B6
B7
D2
D3
C2
E2

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

Layout trace 20 mil

1D8V_S0

N13

SB 0201

HY5DS573222F-28

HY5DS573222F-28
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U

R516
1KR2F

C676
SCD1U16V

HY5DS573222F-28

NC#C4
NC#C11
NC#H4
NC#H11
NC#L12
NC#L13
NC#M3
NC#N3

M13

VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL
VSS_THERMAL

SB 0201

C4
C11
H4
H11
L12
L13
M3
N3

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

B3
B2

MDB32
MDB33
MDB34
MDB35
MDB36
MDB38
MDB37
MDB39

2 of 5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

1D8V_S0

1
1
2

C19
SCD1U16V

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ3
DQ1
DQ2
DQ0
DQ6
DQ5
DQ4
DQ7

U65B

D7
D8
E4
E11
L4
L7
L8
L11

C4
C11
H4
H11
L12
L13
M3
N3

R27
60D4R2F

60D4R2F

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

B5
C6
B6
B7
D2
D3
C2
E2

2 of 5

R33
R30
60D4R2F
60D4R2F
HY5DS573222F-28
HY5DS573222F-28
(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB)
(M24 72.55732.B0U
HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U
3 of 5
3 of 5
U64C
U65C

1D8V_S0

2
2

R26

CKE
CLK
CLK#

CLOSE TO MEM !!

CKEB
N12
VDDRC_CLK0+M11
VDDRC_CLK0- M12

1
110R3
10R3

BC753_1

2 R28
2 R29

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQMB#0
QSB0

BA0
BA1
NC#M10

D7
D8
E4
E11
L4
L7
L8
L11

N4
M5
M10

MAB12
MAB13

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SC10U10V5ZY

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
NC#L9

RAS#
CAS#
WE#
CS#
NC#M4

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
L9

MDB7
MDB6
MDB5
MDB4
MDB1
MDB0
MDB2
MDB3

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11

U64B

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
NC#L9

BC754_1

M2
L2
L3
N2
M4

RASB#
CASB#
WEB#
CSB#0
CSB#1

C22
C673
SC330P50V2KX SCD01U16V2KX

C50
SCD01U16V2KX

1 of 5

U64A

51 CLKB0
51 CLKB#0

C694
C683
C48
C20
C130
C21
C49
C678
SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX SC330P50V2KX

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
L9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SC10U10V5ZY

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11

RAS#
CAS#
WE#
CS#
NC#M4

C671
SCD01U16V2KX

M2
L2
L3
N2
M4

SC10U10V5ZY

51 RASB#
51 CASB#
51 WEB#
51 CSB#0
51 CSB#1

51 QSB[7..0]

C18
SCD1U16V

C693
SCD1U16V

C680
SCD1U16V

1
C16
SCD1U16V

C674
SCD1U16V

C44
SCD1U16V

C46
SCD1U16V

1
C17
SCD1U16V

C45
SCD1U16V

1
2

C47
SCD1U16V

51 DQMB#[7..0]

1D8V_S0
SB 0201

1 of 5

U65A

51 MAB[13..0]

SB 0201

Dummy when use UMA (WHOLE PAGE)

All dampings in this page must near the VRAM.

NC#C4
NC#C11
NC#H4
NC#H11
NC#L12
NC#L13
NC#M3
NC#N3

<Variant Name>

VDDR_VREF3

C677
SCD1U16V

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R515
1KR2F
Title

CLOSE TO MEM

(M24 HYNIX 64MB) 72.52832.F0U - (M26 HYNIX 128MB) 72.55732.B0U

ATI VRAM (2/2)

Layout trace 20 mil

Size
A3

Document Number

Date: Thursday, March 31, 2005


5

Rev

-1

Bolsena
Sheet
1

53

of

58

SB 0201

SRN0-1-U
49
49
49
49

ATI_TXBCLK+
ATI_TXBCLKATI_TXBOUT2+
ATI_TXBOUT2-

4
3
2
1

49
49
49
49

ATI_TXBOUT1+
ATI_TXBOUT1ATI_TXBOUT0+
ATI_TXBOUT0-

4
3
2
1

5
6
7
8

LCD_TXBCLK+ 13,17
LCD_TXBCLK- 13,17
LCD_TXBOUT2+ 13,17
LCD_TXBOUT2- 13,17

5
6
7
8

LCD_TXBOUT1+
LCD_TXBOUT1LCD_TXBOUT0+
LCD_TXBOUT0-

5
6
7
8

LCD_TXACLK+ 13,17
LCD_TXACLK- 13,17
LCD_TXAOUT2+ 13,17
LCD_TXAOUT2- 13,17

5
6
7
8

LCD_TXAOUT1+
LCD_TXAOUT1LCD_TXAOUT0+
LCD_TXAOUT0-

RN97
SRN0-1-U
13,17
13,17
13,17
13,17

RN96
SRN0-1-U
49
49
49
49

ATI_TXACLK+
ATI_TXACLKATI_TXAOUT2+
ATI_TXAOUT2-

4
3
2
1

ATI_TXAOUT1+
ATI_TXAOUT1ATI_TXAOUT0+
ATI_TXAOUT0-

4
3
2
1

RN92
SRN0-1-U
49
49
49
49

13,17
13,17
13,17
13,17

RN91

1 R160

49 ATI_LCDVDD_ON

2
0R2-0

LCD_VDD_ON

13,17

3D3V_S0

R521
2K2R2

3D3V_S0

U67

23,49 VGA_LOCAL_DP

3D3V_S0

DY

SMBCLK
SMBDATA
ALERT#
GND

8
7
6
5

VGA_SMB_CLK 49
VGA_SMB_DAT 49

SB 0201

DY

C697
SCD1U

To M24

To M26

G781

DY

1 R535

2
0R2-0

GPIO_AUXWIN 49

DY Q26 DY
PDTC144EU
2

DY

R536
10KR2

VGA_ALERT# 49

23,49 VGA_LOCAL_DN

VCC
DXP
DXN
THERM#

3 2

1
2
3
4

C695
SC2200P50V2KX

DY
A

Dummy
<Variantwhen
Name> use ''M26'
A

Dummy when use UMA

Wistron Corporation

SB

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

VGA SELECTOR
Size
A3

Document Number

Date: Thursday, March 31, 2005


5

Rev
-1

Bolsena
Sheet
1

54

of

58

FAN5234 FOR VGA_Core

VGA_CORE_S0
DCBATOUT

Dummy when use 'UMA' (whole page)

VGA_CORE_PWR

VGA_CORE_S0

DCBATOUT_5234
GAP-CLOSE-PWR

G63

GAP-CLOSE-PWR
GAP-CLOSE-PWR

G61

GAP-CLOSE-PWR
GAP-CLOSE-PWR

G8

GAP-CLOSE-PWR

G7

G3

2
GAP-CLOSE-PWR

G57

G2

GAP-CLOSE-PWR

G58

2
GAP-CLOSE-PWR

G60

2
GAP-CLOSE-PWR

G59

G9

GAP-CLOSE-PWR

GAP-CLOSE-PWR

G54
G10

GAP-CLOSE-PWR

GAP-CLOSE-PWR

2
GAP-CLOSE-PWR

G56
G62

2
GAP-CLOSE-PWR

G55

DCBATOUT_5234

2
GAP-CLOSE-PWR

G53

1
5V_S5

SC10U25V0KX

GAP-CLOSE-PWR

G5

2
GAP-CLOSE-PWR

G1

2
GAP-CLOSE-PWR

G4

1
G
S
S
S

SB 0127

4
3
2
1

SB 0127

FDS6612A

SCD1U25V3KX

1
TC22
ST330U2D5VDM-3

C706
SCD1U

TC21
ST330U2D5VDM-3

D
Q5
2N7002

PWM Mode:
FPWM (High)=>Fixed PWM Mode.
FPWM (Low)=>Hysteretic Mode.

GPIO_PWRCNTL 49
R87
10KR2

2KR2F
DUMMY-R3

R538

2
R58

2
5234_VSEN

Rilim=(11.2/Iilim)*((100+Rsense)/Rdson)

High(3.3V)=>Vo=1.0V
Low(0V)=>Vo=1.2V

KEMET V Size 330uF 2.5V


ESR=9mohm, Iripple=3.7A
NTD:9.0

KEMET B2 Size 220uF 2.5V


ESR=35mohm Iripple=1.6A
NTD:6.0

2
2

4
3
2
1

C61
SCD1U25V3KX

SC2200P50V2KX

C700

R57
10KR2

TP73
TPAD30

FAN5234MTCX

R59
464R3F

R537
698R2F
C699
SCD01U16V2JX

G
S
S
S

R523
40K2R2F

SC 0308
C696
SCD22U16V3ZY

5V_S0

300KHz
1

FDS6690A

PGOOD

IND-2D2UH-4
U15

5234_HDRV
5234_LDRV

14
10

VGA_CORE_PWR

HDRV
LDRV

SC 0303

L25

VSEN
VOUT
VIN
VCC

1K2R2F
1 R522
2

5234_ISEN
5234_SW

12
13

ISNS
SW

9
8

PGND
AGND

5
6
7
8

FPWM
BOOT
SS
ILIM
EN

D
D
D
D

6
5
1
11

5234_VIN

R60 2
1
0R0603-PAD

16
15
7
4
3

5234_SS
5234_ILIM
5234_EN

2
10KR2
DCBATOUT_5234

DY

1D2V or 1D15V
Iomax=10 or 5.2A
OCP>20A

U68

2
R525

C87

R524
DUMMY-R2

SB 0131

5234_BOOT

1
SSM5818SL

PM_SLP_S3#

C85
SCD1U

18,21,34,38,39,43,44,57

SC10U25V0KX

U18

D
D
D
D

C60
SCD1U16V

D9

5V_S0

GAP-CLOSE-PWR

1
2
5
6
7
8

1
2

1
2

C59
SC4D7U10V5ZY

C84

2
G6

C86

Vout Setting:
0.9V/Rlow=(Vout-0.9V)/Rhigh

M24/M26 POWER PLAY (GPIO_PWRCNTL)


high (3.3V) = set lower core voltage (VDDC = 1.0V)
low (0V) = set higher core voltage (VDDC = 1.2V)

3D3V_S0

1D5V_VGA_1_S0

GAP-CLOSE-PWR
C755
SC10U25V6KX

G64

GAP-CLOSE-PWR

<Variant Name>

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

R596
10KR2F-U
Title

DY
2

VGA CORE 1D2V or 1D0V


Size
A3

(Power Team)
A

Wistron Corporation

APL5332KAC
U74
C753
SCD1U

8
7
6
5
9

NC#8
NC#7
GND
NC#5
GND

R597
8K66R2F

<VGA>

VIN
BS
FB
VOUT

1
2
3
4

C756
SC10U10V5ZY

1
C754
SC10U10V5ZY

1
2

1D5V_VGA_S0
G67

Document Number

Date: Thursday, March 31, 2005

Rev

-1

Bolsena
Sheet
E

55

of

58

DY

2HOLE3

HOLE8
HOLE

HOLE

HOLE6
HOLE

HOLE7
HOLE

HOLE5
HOLE

HOLE10
HOLE

HOLE28
HOLE

HOLE9
HOLE

1HOLE18

HOLE20
HOLE

HOLE2
HOLE

HOLE

HOLE22
HOLE

3D3V_S5

DY

5V_AUX_S5

EC23
SCD1U16V

3D3V_LAN_S5

CHG_PWR-2 47

AD+

5130_LL1 44,45
5130_LL2 44,45

EC21
SCD1U16V

EC20
SCD1U16V

HOLE23
HOLE

DY

EC19
SCD1U16V

HOLE4
HOLE

1D2V_S0

HOLE1
HOLE

1D8V_S0

HOLE24
HOLE

VGA_CORE_PWR

HOLE13
HOLE

5130_LL3 44,45

MAX1544_LXM 41,42

DY

EC89

DY

EC88

MAX1544_LXS 41,42

1
2

DY

1
2

1
2

2
1

1
2

DY

EC87

DY

DY

EC90

3D3V_S5

EC45

SCD1U16V

5VA_OP_S0

EC44
SCD1U16V

1
EC43
SCD1U16V

1
EC42
SCD1U16V

1
EC41
SCD1U16V

1
EC40
SCD1U16V

1
EC39
SCD1U16V

1
EC38
SCD1U16V

2D5V_S0

DOCK_AD+

DY

EC52
SCD1U16V

EC53
SCD1U16V

EC51
SCD1U16V

EC50
SCD1U16V

EC49
SCD1U16V

EC48
SCD1U16V

EC47
SCD1U16V

EC46
SCD1U16V

EC22
SCD1U

EC62
SCD1U

DY

EC35
SCD1U

DCBATOUT

DY

EC34
SCD1U

DY

EC33
SCD1U16V

DCBATOUT

DY

DCBATOUT

EC37
SCD1U16V

2
1

1
2

DY

EC86

EC82

SC1000P50V2KX

DY

SC1500P50V3KX

3D3V_LAN_S5

EC32
SCD1U16V

DY

SC1000P50V2KX

DY

EC85

SC1500P50V3KX

DY

DY

SC 0310

3D3V_S0

EC84

SC1000P50V2KX

3D3V_BT_S0

EC31
SCD1U16V

EC83

EC30
SCD1U16V
EC36
SCD1U16V

2D5V_S0

DY

MAX1999_LX5 43

1D2V_PWR

EC29
SCD1U16V

MAX1999_LX3 43

DY

SC1500P50V3KX

EC28
SCD1U16V

DY

SC1000P50V2KX

2D5V_PWR

DY

SC1500P50V3KX

1D8V_PWR

1
2

1
2

DY

EC27
SCD1U16V

DY

SC 0310

1
2

EC74
SCD1U

SC1000P50V2KX

EC73
SCD1U

EC81
SC1500P50V3KX

EC72
SCD1U

EC80
SC1000P50V2KX

DY

EC26
SCD1U16V

EC71
SCD1U16V

EC79
SC1500P50V3KX

DY

EC25
SCD1U16V

EC70
SCD1U16V

EC78
SC1000P50V2KX

DY

EC24
SCD1U16V

EC69
SCD1U16V

EC77
SC1500P50V3KX

EC68
SCD1U16V

2D5V_S0

EC76
SC1000P50V2KX

2D5V_S3

EC75
SC1500P50V3KX

CHG_PWR-3 47

FAN1_VCC

FOR MDC

HOLE12
DCBATOUT
HOLE11

EC66
SCD1U

34.42E05.001
HOLE16

SC 0308

34.42E05.001
EC67
SCD1U
SC 0309

GND16

GND17

GND1

GND2

13

14

1
TSLCX125

TSLCX125

34.40V16.001

DY

DY

34.42E05.001

Dummy when no EZ4

34.40V16.001

GND12

U54F

DY

GND9

SPRING-1 SPRING-1

<Variant Name>

34.42E05.001

14

DY

13

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

12

GND11

34.40V16.001

DY

34.40V16.001

34.40V16.001

HOLE19

11

3D3V_AUX_S5

34.40V16.001

GND10

34.40V16.001

34.49U24.001

GND8

DY

14
12

GNDPAD

34.42T14.001

U40D

HOLE21

GND6

34.45T31.001

34.45T31.001

34.40V16.001

U40A

GND3

34.40V16.001

GND7

FOR NORTH BRIDGE


HOLE17

DY

SPRING-1 SPRING-24 SPRING-24 SPRING-1 SPRING-1 SPRING-1 SPRING-1

DY

DY

GND4

GND5

3D3V_S5

SPRING-1 SPRING-1 SPRING-1


34.49U24.001

34.40V16.001

34.45T31.001

SPRING-24 SPRING-1

DY

34.40V16.001

GND18

3D3V_S5

34.42E05.001

SC 0301

GND15
SPRING-29

GND14

34.42E05.001

34.42E05.001

DY
GND20

GND13

ZZ.NDPAD.XXX

34.39S07.001

34.40V16.001

SPRING-1 SPRING-23

34.39S07.001

34.39S07.001

SPRING-23 SPRING-23

34.39S07.001

SPRING-23

GND24

GNDPAD

DY
GND23

ZZ.NDPAD.XXX

DY
GND21

34.42E05.001

BT+

GREEN COLOR FOR INSTALL

GND22

HOLE15

GND19

HOLE14

SCD1U => VOLTAGE 25V

IMPORTANT:
SCD1U => VOLTAGE 25V
SCD1U16V => VOLTAGE 16V

DY

1
EC64
SCD1U

1
EC65
SCD1U

1
EC59
SCD1U

EC58
SCD1U

1
EC57
SCD1U

EC60
SCD1U

1
EC56
SCD1U

EC55
SCD1U

1
EC54
SCD1U

SC 0308

FOR VGA CHIP


EC63
SCD1U16V

TSLCX14MTC-L-U

Title
Size
A3

EMI
Document Number

Rev
-1

Bolsena

Date: Thursday, March 31, 2005

Sheet

56

of

58

PPD[7..0]

126

15 EZ4_DVI_DDC_D
15,49 TMDS_EZ4_TXC+
15,49 TMDS_EZ4_TXC34 EZIN_EM#
15 EZ4_DVI_DDC_C

2
R498 1KR2

33 DOCK_LIN_R
33 DOCK_MIC_JKIN

TV_COMP_DOCK
TV_LUMA_DOCK

33 DOCK_LIN_L

TV_CRMA_DOCK

33 SPKR_R_DOCK
33 DOCK_EXT_MIC
CRT_R_DOCK
33 SPKR_L_DOCK

CRT_G_DOCK
CRT_B_DOCK

16 EZ4_HS

16 EZ4_CRT_DDC_D
16 EZ4_VS
12 PCIE_RXP0
12 PCIE_RXN0

5V_S0

16 EZ4_CRT_DDC_C

SC 0309

R501
1KR2

3 SMBC_SB_EZ4
12 PCIE_TXP0
12 PCIE_TXN0
3 SMBD_SB_EZ4
34 EZ_PWROK

SC 0309
34 PE_REQ1#
3 CLK_PCIE_DOCK1
3 CLK_PCIE_DOCK1#
12 PCIE_RXN1
12 PCIE_RXP1

U3

LUSB1# 21

3
4
33
34
5
6
35
36
7
8
37
38
9
10
39
40
11
12
41
42
13
14
43
44
15
16
45
46
17
18
47
48
19
20
49
50
21
22
51
52
23
24
53
54
25
26
55
56
27
28
57
58
29
30
59
60
122
121

D_RTGP1

D_RTGP1 30
D_TGP2 30
D_RTGN1 30

D_TGN2

D_TGN2 30

1
2
3
4

49 DIS_COMP
49 DIS_LUMA
49 DIS_CRMA

FOR LINK LED (GREEN)


D_TGP3 30
D_TGN3 30
PSTROB# 58
PAUTOFD# 58

DOCK_JACK_IN
PPD0
PERROR#

DOCK_JACK_IN

33
13 UMA_LUMA
13 UMA_CRMA
13 UMA_COMP

SUSON
MAINON

1 R6

TV_CRMA

4
5
6

TV_LUMA
TV_CRMA
TV_COMP

0R0402-PAD
1 R15
2

1
2
3
4

8
7
6
5

4
5
6

PCIRST_BUF# 15,18,26,28,29,31

8
7
6
5

CRT_G_1
CRT_B_1
CRT_R_1

U6
CRT_R_1

4
5
6

0R0402-PAD
1 R7
2

DOCK_ON_1 30
R507

NC7SZ08-U

CRT_G_SYS 16

NC7SB3157P6X-U
CRT_B_DOCK

3
2
1

B0
GND
B1

CRT_B_SYS 16

NC7SB3157P6X-U
CRT_R_DOCK

3
2
1

B0
GND
B1

CRT_R_SYS 16
2

Dummy when no EZ4


SRN0-1-U
8
7
6
5

RN87

1
2
3
4

3D3V_S5
18,21,34,38,39,43,44,55

DTR1_BOUT1_5
RI1#_5
RTS1#_5

EZIN_EM#
U40C

MAINON

TSLCX125

SUSON

TSLCX125

Dummy when no EZ4

<Variant Name>

4
3
2
1

Dummy when no EZ4

RC14

4
3
2
1

EZIN_EM#
U40B

21,34,44 PM_SLP_S5#

SOUT1_5

10KR2

PM_SLP_S3#

3D3V_S5

CTS1#_5
SIN1_5
DSR1#_5
DCD1#_5

DOCK_ON_2#
Q25
CHT2222A

21

RC15

Wistron Corporation

5
6
7
8

5
6
7
8

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

SRC100P50V-U SRC100P50V-U

EASY PORT4 (1/2)


Size
A3

Dummy when no EZ4


A

Dummy when use EZ4

GND

DOCK_CRT_ON#

R508
10KR2

1
R500
1MR2

DOCK
CRT_G_DOCK

3
2
1

B0
GND
B1

14

TV

NC7SB3157P6X-U

A
VCC
S

5V_S0

EZ_PWROK

Q24
CHT2222A

DOCK

RN85

1
2
3
4

13 UMA_G
13 UMA_B
13 UMA_R

CRT_G_1
CRT_B_1
CRT_R_1

CRT

SYSTEM

1
2
3

DY
EZIN_EM# 1

A
VCC
S

SC 0308

U58

VCC

A
VCC
S

U8
CRT_B_1

SRN0-1-U

ME : 20.80591.120

4
5
6

Function

CRT_R_1
CRT_G_1
CRT_B_1

DOCK_ON_2#

LAN

8
7
6
5

5V_S0

CRT_G_1

SB 0127

1
2
3
4

U7

Dummy when use Discrete

SYSTEM

TV_CRMA_SYS 16

RN84 SRN0-1-U

Dummy when use UMA

D2
2 1
1KR2
3
2 BAT54-1
CLK_PCIE_DOCK2 3
CLK_PCIE_DOCK2# 3
PCIE_TXP1 12
PCIE_TXN1 12

Function

TV_CRMA_DOCK

3
2
1

B0
GND
B1

C4
SCD1U16V

49 DIS_R
49 DIS_G
49 DIS_B

20.80591.120

DOCK_IN

NC7SB3157P6X-U

RN86

FOX-CONN120-2-GP

3D3V_S5

TV_LUMA_SYS 16

Dummy when use EZ4

CRT SWITCH

DOCK_AD+

R499
10KR2

TV_LUMA_DOCK

3
2
1

B0
GND
B1

DOCK_TV_ON#

SRN0-1-U

3D3V_S5

NC7SB3157P6X-U

TV_COMP
TV_LUMA
TV_CRMA

SC 0308

DOCK_ON_2#

A
VCC
S

125

TV_COMP_SYS 16

Dummy when no EZ4

Dummy when use Discrete

PACK# 58
PS2_KDAT 34
PS2_KCLK 34
PBUSY 58
PPE 58
PS2_MDAT 34
PS2_MCLK 34
PSLCT 58
LUSB2# 21
3D3V_S0
?10K PULL TOO SLOW - 0324
R5 1
10KR22

PSLCT

8
7
6
5
SRN0-1-U

DCD1#_5 37

PBUSY
PPE

A
VCC
S

U5

SIN1_5 37
DSR1#_5 37

PPD5
PPD6

4
5
6

TV_COMP_DOCK

3
2
1

B0
GND
B1

A to B1

RN93

1
2
3
4

PSLCTIN# 58
SOUT1_5 37
RTS1#_5 37

PPD3
PPD4

U4
TV_LUMA

Dummy when use UMA

PINIT# 58
DTR1_BOUT1_5 37
CTS1#_5 37

PPD2
PSLCTIN#

TV_COMP
TV_LUMA
TV_CRMA

8
7
6
5

A
VCC
S

A to B0

SC 0309

PERROR# 58
SPDIF 32,33
RI1#_5 37

PPD1
PINIT#

4
5
6

SRN0-1-U

10M_LED# 29,30

D_TGP3
D_TGN3
PSTROB#
PAUTOFD#

TV_COMP

RN83

D_TGP2
D_RTGN1

PPD7
PACK#

C9
SCD1U16V

NC7SB3157P6X-U

Function

14

15,49 TMDS_EZ4_TX0+
4

D_TTGP0 30
D_TTGN0 30
ACT_LED# 29,30

93
94
64
63
95
96
66
65
97
98
68
67
99
100
70
69
101
102
72
71
103
104
74
73
105
106
76
75
107
108
78
77
109
110
80
79
111
112
82
81
113
114
84
83
115
116
86
85
117
118
88
87
119
120
90
89
123
124

15,49 TMDS_EZ4_TX015 DVI_EZ4_HPD

TV SWITCH

58

5V_S0

D_TTGP0
D_TTGN0

1
2
31
32

91
92
62
61

TMDS_EZ4_TX1TMDS_EZ4_TX1+
TMDS_EZ4_TX2+
TMDS_EZ4_TX2-

15,49
15,49
15,49
15,49

10

EZ1

Document Number

Rev

Bolsena

Date: Thursday, March 31, 2005


D

-1
Sheet
E

57

of

58

PRINT PORT
PRN5V

2 C685
SCD1U16V

1
2
3
4

8
7
6
5

PACK#
PBUSY
PSLCT
PPE

SRN33
R511
2
33R2

PSTROB#

PACK# 57
PBUSY 57
PSLCT 57
PPE 57

EZ4_PD1
ERROR#_5
EZ4_PD0
AUTOFD#_5

1
2
3
4
5

2 C669
SCD1U16V

10
9
8
7
6

PRINIT#_5
EZ4_PD2
SLCTIN#_5
EZ4_PD3

10
9
8
7
6

EZ4_PD4
EZ4_PD5
EZ4_PD6
EZ4_PD7

PSTROB# 57
RP6

1
2
3
4

RC11

SRC100P50V-U

SRC100P50V-U

SRP1K

PE_5
SLCT_5
BUSY_5
PRNACK#_5

RN10
EZ4_PD4
EZ4_PD5
EZ4_PD7
EZ4_PD6

RC13

8
7
6
5

PPD4
PPD5
PPD7
PPD6

1
2
3
4
5

SRN33

SRP1K

PSTROB#
PPD6
PPD7
PPD5
PPD4
PPD1
PERROR#
PPD0
PAUTOFD#

37 STROB#_5

CH751H-40-U
RP5

SRN33
RN11
37 PRNACK#_5
37 BUSY_5
37 SLCT_5
37 PE_5

PSLCTIN# 57

EZ4_PD3

D30

PINIT# 57

5
6
7
8

EZ4_PD2

PINIT#
PPD2
PSLCTIN#
PPD3

4
3
2
1

37 PRINIT#_5
37 SLCTIN#_5

8
7
6
5

5
6
7
8

5V_S0
RN9

1
2
3
4

4
3
2
1

PPD3
PSLCTIN#
PPD2
PINIT#
PSLCT
PPE
PBUSY
PACK#

57 PPD[7..0]
37 EZ4_PD[7..0]

C660
SC100P50V2JN

37 ERROR#_5

8
7
6
5

PAUTOFD#
PPD0
PPD1
PERROR#

PAUTOFD# 57
PERROR# 57

SRN33

STROB#_5

R512 2
1KR2

RC10

RC12

4
3
2
1

1
2
3
4

Place near Dock1


5
6
7
8

EZ4_PD0
EZ4_PD1

5
6
7
8

37 AUTOFD#_5

4
3
2
1

RN8

SRC100P50V-U SRC100P50V-U

For EMI
Place near Dock1

Dummy when no EZ4


cap. between moat
(for UMA RGB signal)

1D2V_S0

1D8V_S0

C961

1
SCD1U16V

5V_S0
C962

C963

SCD1U16V

SCD1U16V

<Variant Name>
SB 0213

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

EASY PORT4 (2/2)


Size
A3

Document Number

Rev

-1

Bolsena

Date: Thursday, March 31, 2005

Sheet

58

of

58