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TDM Pulse Code Modulation Transmitter and Receiver Trainer ST2103 and ST2104

Operating Manual Ver.1.1

An ISO 9001 : 2000 company

94-101, Electronic Complex Pardesipura, Indore- 452010, India Tel : 91-731- 2570301/02, 4211100 Fax: 91- 731- 2555643 e mail : info@scientech.bz Website : www.scientech.bz Toll free : 1800-103-5050

ST2103 & ST2104

Scientech Technologies Pvt. Ltd.

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ST2103 & ST2104

TDM Pulse Code Modulation Transmitter and Receiver Trainer ST2103 and ST2104 Table of Contents 1. 2. 3. 4. 5. 6. 7. TDM PCM ST2103’s Features TDM PCM ST2103’s Technical Specifications ST2104’s Features ST2104’s Technical Specifications Pulse Modulation Techniques Pulse Code Modulation Digital Communication System • Experiment 1 Study of Error Check Codes A/D Conversion • 9. Experiment 2 Study of Analog to Digital Conversion Digital Transmission Experiment 3 Study of Control Signals and their Timings Experiment 4 Study of Time Division Multiplexing Experiment 5 Study of Pseudo Random Sync Code Generator Experiment 6 Study of Three Modes of Transmission Experiment 7 Computer Communication using RS232 interface via ST2103 & ST2104 Experiment 8 Multi point to multipoint communication using RS232 interface via ST2103 & ST2104 4 4 5 5 6 9 12 16 19 21 23 26 29 32 33 35 44

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Time Division Multiplexing • • • •

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Experiment 9 Point to multipoint communication using RS232 interface via ST2103 & ST2104 Switched Faults Setting up the Receiver’s clock regeneration circuit Warranty List of Accessories

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ST2103 & ST2104

ST2103 : Features • • • • • • • • Crystal Controlled Clock. On-board Sine wave generator (Synchronized). 2 TDM Analog Channels. PCM Transmitter. Fast & Slow modes for real time operation and data flow examination. Error check code options (odd-even parity, Hamming Code). 4 Switched faults allow different Error Check Options. PC-PC Communication via RS232 interface. Technical Specifications Crystal Frequency On Board Analog Signal : : 12 MHz 1 KHz, 2 KHz (sine wave synchronized to sampling pulse Adjustable amplitude and separate variable DC level) Two Time Division Multiplexing Pulse Code Modulation Pseudo random sync code generator 'Off'-Odd - Even - Hamming Fast: 240 KHz / channel (approximately) Slow: 1Hz/ channel (approximately) PC -PC communication Port Baud Rate Test Points Interconnections Power Supply Power Consumption Dimensions (mm) Weight : : : : : : : : : Using 2 channels via RS232 9 Pin D type connector - 2Nos Selectable from 300 to 2400 49 in numbers 4 mm Sockets 230 V ±10%, 50 Hz 4 VA (approximately) W 420 x H100 x D255 2.5 Kgs. (approximately)

Input Channels Multiplexing Modulation Sync Signal Error Check Code Operating Mode

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ST2103 & ST2104

ST2104 : Features • • • • • • • • • • • Input accepts two channel multiplexed data. On board De-multiplexed PCM Receiver. On board Low Pass Filter. Fast & Slow modes for real time operation and data flow examination. On board PLL for clock regeneration. On board sync code detector. Error check code options. Odd or Even Parity-Single bit error detection. Hamming code single bit error detection and correction. 4 Switched faults allow different error check code option. PC-PC Communication via RS232 interface. Technical Specifications Input Channel Demodulation Clock Regeneration Operating Speeds : : : : Time Division Multiplexed Serial Input Pulse code Demodulation By phase Locked loop Fast – 240 KHz/Channel, Slow 1Hz/ Channel 'Off'-Odd- Even parity& Hamming code Hamming code using 2 channels via RS232 9 pin D type connector-2 Nos selectable from 300 to 2400 56 in numbers 4 mm sockets 230V +/- 10%, 50Hz, 4VA W420 x H100 x D255 2.5 Kgs. (approximately)

Error Detection (Single bit) : Error Correction PC- PC communication Port Baud rate Test Points Interconnections Power Requirement Dimensions (mm) Weight : : : : : : : : :

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Pulse Width Modulation (PWM) : In PWM system the width of the pulse is varied in accordance with the instantaneous level of the modulating signal.e. The phenomenon is called 'dispersion’. The very fact that the variation of a particular pulse parameter is continuous rather than being in the discrete steps makes the system analog in nature. Therefore some frequency component of the square wave arrives later as compared to the other. This causes widening of the pulse width. The channel introduces noise on the signal from various sources. dispersion & noise is so large that the pulse is impaired & introduced at the receiver as shown in figure 1. Pulse Position Modulation (PPM) : In PPM System. Pulse Modulation System : 1. As a result of this. 6 . Now days. the position of the pulse relative to the zero reference level is varied in accordance with the instantaneous level of the modulating signal. & R) limit the velocity at which a particular frequency can travel. Also the receiver is not noise free. the PAM signals are vulnerable to noise & dispersion of the pulse. G. 2. The primary line constants (L. The pulses also suffer attenuation & dispersion as they pass through the channel.ST2103 & ST2104 Pulse Modulation Techniques Pulse code modulation. Pulse Code Modulation (PCM) : In PCM System the amplitude of the sampled waveform at definite time intervals is represented as a binary code. more popularly known as PCM is the most widely used digital modulation system. The combined effect of attenuation. It is a widely known fact that the analog modulation systems are most prone to the noise present in the channel and receiver. Pulse Amplitude Modulation (PAM) : In pulse amplitude modulation system the amplitude of the pulse is varied in accordance with the instantaneous level of the modulating signal. Ltd. As we will see further that the digital modulation systems are far less sensitive to noise as compared to analog modulation. The result is different frequency travel at different velocities in the medium. but it forms the first stage of the other types of pulse modulation. The first three techniques of the above described systems are not truly digital but in fact are analog in nature. 4. The basis of digital modulation systems lies on pulse modulation i. Scientech Technologies Pvt. the PAM system is not generally used. C. 3. a particular characteristic of the pulse is varied in accordance with the information signal.

Ltd. Store & forward (S & F) facility : That information which has been binary coded in digital format can be easily stored in the computer or memory elements. facsimile. & information can be forwarded at the desired time. The information is coded in binary form.e. c. It is required at the time of channel congestion. the source of information / sample. i. Multiplexing : The information once sampled & coded can be multiplexed in time domain. becomes unimportant. Therefore many different sources such as telephone. the coded information from different sources can be sent. the message can be forwarded to the called party. b. Noise & Distortion : Pulse which becomes distorted by the addition of noise can be reshaped at the regenerators installed at pre-determined intervals along the link. Once the channel becomes clear. Scientech Technologies Pvt. if it can be re-routed to the corresponding channels at the receiver. Thus within certain threshold the error will not creep in. one after another.ST2103 & ST2104 Pulse Train distortion due to Channel Characteristics Figure 1 Advantages of digital modulation system : a. The message can be stored in memory. telegraphy and video cap are transmitted over same channel & circuitry. 7 .

the digital circuits / IC's are becoming more and more cheaper Still prices are slightly at the higher side. Scientech Technologies Pvt. But the advantage offered by the digital techniques far overweighs this consideration. Power requirement : To transmit the digital data over the same channel requires less signal power than that would be required for same performance of the receiver for analog systems. e. Disadvantages of digital modulation communication system : a. Ltd. The data can not be correctly interpreted if the receiver has no proper decoder. This adds to complexity as well as to the cost of the communications system. Encryption & security : The digital devices today are capable of high grade encryption. Hence the digital communication can be highly secured. Band with requirement : The digital communication systems need very large bandwidth as compared to its analog counter part. Complexity : The digital transmitter & receivers is the complex due to the requirement of highly reliable timing information. 8 . b. With the advent of new technology.ST2103 & ST2104 d.

This process is called as Quantization & it is generally carried out by the A/D converter. The sampled value is then approximated to the nearest amplitude level. which is then transmitted. 9 . Sampling Frequency ≥ 2 fm ≥ 2 x 3. the sampling rate must be at least twice the highest frequency component present in the signal. See figure 2. Figure 2 Scientech Technologies Pvt.4 KHz.4 KHz ≥ 6. Sample quantifies the instantaneous value of the analog signal point at sampling point to obtain pulse amplitude output. Allocation of Binary Codes : Each binary word defines a particular narrow range of amplitude level.ST2103 & ST2104 Pulse Code Modulation Steps in Pulse Code Modulation : Sampling : The analog signal is sampled according to the Nyquist criteria. Ltd. The sample is then assigned a code corresponding to the amplitude level. In telephony the standard sampling rate is 8 KHz. So. The nyquist criteria states that for faithful reproduction of the band limited signal. the sampling frequency is kept slightly more than the required rate.8 KHz Practically. For audio signals the highest frequency component is 3.

This causes a great amount of distortion at the receiver for low level signals. The difference between the analog signal value & its approximated one (quantized one) is random & unpredictable. the quantization levels are uniform for all the amplitude range. This is a sort of unwanted. Ltd. the discrepancy creeps in. Here the quantization levels are clear together for low level than they are for the high levels. Increasing the number of bits to represent a sample increases the system's bandwidth requirement b. the duration of sampled pulse is much smaller than the A/D converter's sampling time. Finite sampling time of A/D converter : Another problem associated with quantization is that the A/D Converter requires finite time to convert the analog information to digital data. remain unchanged till the conversion is complete. The quantization noise plays havoc with the low level signals because the % approximation compared to the signal amplitude is very high. Quantization noise : As we have seen the signal is approximated to the nearest level (step).ST2103 & ST2104 There are two important problems associated with quantization. But in practice. But this method of encoding has disadvantages of its own. The sample & hold circuitry holds the sample value till the next sample. a non-uniform encoding scheme is used. The input/output characteristics for compression signal passed through a comparator network 'prior to compression (See figure 3). Also the quieter part of music or speech could become severely distorted & would make them unpleasant to listen. This process is called compression. The encoding method described above is called as uniform encoding i. The A/D Converter requires that the value at its input. Increasing the number of levels to reduce quantization noise has the effect of increasing the number of bits. This problem can be overcome by using a sample & hold circuit prior to A/D converter output. But nothing comes without price. To overcome this problem. But it can never be eliminated. Quantization noise can be reduced by increasing the number of levels. hence reducing the approximation. a. random signal which accompanies the information signal and is termed as 'Quantization noise'. 10 . This has an effect of compression on the extreme ends of the signal. Scientech Technologies Pvt. Refer page 18 & 19 A/D conversion for details. unpredictable.e. Since the levels are discrete where as the signal is continuous.

e. Here the multi frame consists of 16 frames. Multi Frame : When the number of bits in allocated channels is insufficient to cope with the synchronization & signaling information then it is spread on defined channels over a number of frames. is termed as expanding. a separate channel is used for signaling & synchronization information.g. At receiver. Ltd. In Europe. This information is termed as signaling information. Various channels can be multiplexed in time domain i. These three n bit words forms the basis of a frame. Let us assume a 3 channel PCM system. the data is decoded by the D/A converter. The two processes are combined are known as compounding this feature is not provided on trainer but you should be aware of its existence. control & routing information have to be included. Some error correcting codes & synchronization can also be transmitted along with the information signal. Besides these channels. a 30 channel PCM System is followed which is specified by CCITT (International Radio Consultative Committee). the recovered samples are filtered & reconstructed to provide the original waveform. The frame contains these three n bit words also contains some synchronization & reference positioning information.ST2103 & ST2104 An input output characteristic providing compression Figure 3 The opposite effect is utilized at the receiver to undo the effect of compression. The system samples 0-2 samples sequentially providing 3 samples to be converted to 3 "n" bit words. On more complex multi-channel systems. 11 . If all these information can not be fitted in a single frame. This sequence of frames is known as a Multi Frames. two separate channels are used for signaling & synchronization information. Scientech Technologies Pvt. the information data from various sources are sequentially transmitted over the same transmission medium e.

12 . Suppose that the signal to noise ratio on the channel is such that we can be nearly certain that not more than one error will be made in triplet. Ltd. Suppose that when a '0' is to be transmitted we transmit 000 & we transmit 111 to represent a digit 1. Then we transmit a stream of binary digits 0's or 1's. Impulse Noise : It can be defined as a high noise level occurring for a very short time. c. Coding accomplishes its purpose by deliberate introduction of redundancy in the message. As noise is unpredictable. One important parameter which measures the unsuccessful recognition of data bits is BER (bit error rate). 010. Our main concern is that we do not confuse a 0 for a 1 or a '1' for a '0'.000 will be in error. This fact mostly makes the digital communication systems very popular. we would actually be certain that the transmitted data was actually 0. The source of impulse noise may be lightning strike or sudden heavy current flow through a system or electromagnetic radiation etc. the characteristic of the transmission medium causes attenuation and dispersion. For acceptable quality speech signals the BER/ Pbe should not be more than 10 while some data transmission systems may require values of Pbe = 10 or less. A probability of bit error Pbe-(or BER as it is usually referred) 10 means that. the method of coding the signal is adopted. Thus the redundancy. Late Switching : The late switching by some ageing devices or due to loss of synchronization leads to change in average level & this causes errors to permit us to detect the errors caused by noise in some cases & to be able to correct them. 101. b. In this case we will know that the error has occurred. leading to the indecision pulse level recognition.00. Then. Their degree of success depends upon the redundancy which they introduce e. 1 bit in every 1. deliberately introduced has enabled us to detect and even correct the error.g. if we received 001. Scientech Technologies Pvt. producing noise spikes superimposed upon the signal waveform. or 100. The other two 0's or 1's add no information to the message & hence are redundant. Consider that we are transmitting information by means of binary PCM.ST2103 & ST2104 Digital Communication System Digital communication systems are less sensitive to noise as compared to their analog counter part. or 110 we would be rather certain that the message was actually 111. Reasons for induced errors in digital system : a. Transmission medium characteristics : As it has been mentioned earlier. on an average. Although the digital communication systems are mostly unaffected by noise. there is always a finite possibility that those two errors may occur. But the introduction of redundancy can't guarantee that an error will either be detectable or correctable. This can lead to errors. still there is a probability that the bits are recognized wrongly at the receiver due to noise. if we received 011. Similarly.

however small. Even There is an over possibility. The correction is done automatically by receiver. But it does not really solve the problem. a '1' bit is added to each word containing odd '1' and a '0' bit is added to each word containing even '1 'so the result is that all the code words contain an even number of 1 bits after encoding. the parity bit remains and the data is passed to the user. If it does. If it does not. In such cases it is called as odd parity. Thus we conclude that while coding allows us a great deal of detection & correction it generally cannot detect or correct all errors. Continuing with the example of even parity. If even parity is to be established (known as Even parity). A better solution would be to introduce a method of error detection and correction. 13 . the parity coding can ensure that the total number of '1's in the encoded word is odd.ST2103 & ST2104 but we will be inclined to read a '0' as a '1' & a '1' as a '0'. Hence the required increased bit rate will undo some of the advantage that will accrue from redundancy coding. It is for this reason that parity coding is normally only used on transmission systems where the probability of error occurring is deemed to be low. The commonly used Codes employed in ST2103 & ST2104 are : a) Parity Coding : It is the simplest method of error coding. Many different types of codes have been developed and are in use. we shall have to transmit more no of bits in time TS otherwise allocated to a single bit. In this case. the presence of an error is indicated. that all the three bits are in error. However coding yields a very worthwhile net advantage. In such number of '1's in the encoded word is odd. Similarly. Parity is a method of encoding such that the number of 1's in a codeword is either even or odd Signal parity is established as follows. each code word is examined to see if it contains an even number of 1 bits. It is clear that if the redundant message is to be transmitted at the same rate as the original binary signal. Scientech Technologies Pvt. after transmission. However it does offer the system ability to record and evaluate system error rate. The degree of success depends upon the redundancy which they introduce. Note that single bit parity code can detect single errors only and it cannot provide error correction because there is no way of knowing which bit is in error. not only we will misread the digits but we would not even suspect that an error has been made. The price to be paid is increased hardware complexity both for transmitter & receiver where encoding & decoding is affected respectively. Each word is examined to determine whether it contains an odd or even number of '1' bits. Detection of errors allows the system to request re-transmission of data. Ltd. And it is an established fact that the increase in bit rate may increase the error rate.

Ltd.C2 Parity Bit . decode each word at the transmitter into a new code by stuffing the word with extra redundant bits.C1 Parity Bit – C0 The Groups & Parity bit forms an even parity check group. the parity is lost & can be detected at receiver e. Let us encode binary value D6. D3 D6. The ST2103 & ST2104 involves the use of 7 bit word. C1 & C0 are Hamming Code Bits The Hamming code was invented by R. Three bit hamming code provides single bit error detection and correction. D3 of '1101' Group 1 Group 2 Group 3 D6 1 D6 1 D6 1 D6 1 D5 1 D4 0 D5 1 D5 1 D4 0 D3 1 D4 0 D3 1 D3 1 C2 0 C2 0 C1 1 C0 0 C1 1 C0 0 So.W. Therefore only four bits are used for transmitting data if hamming code is selected. The format becomes. Group 1 D6 D5 D4 C2 14 Scientech Technologies Pvt. If an error occurs in any of the digits. the four digits representing a particular quantized value are taken in as three groups. D4. The Error Detection/ Correction Logic carries out even parity checks on the three groups. D5. But it provides a facility of single bit error detection & correction. the data word after coding will be At the receiver. D5. It uses three redundant bits. . D3 Parity Bit . the redundant bits do not convey information but also provides a method of allowing the receiver to decide when an error has occurred & which bit is in error since the system is binary. D4 D6. the bit in error is easily corrected. D4. D6 D5 D4 D3 C2 C1 C0 Where C2. as opposed to the single redundant bit needed by simple parity checking.g. Hamming.ST2103 & ST2104 b) Hamming Coding : Hamming coding. As the name suggests. D5. Code Generation on Trainer The code on this trainer is generated by addicting parity check bit to each group as shown below : Group 1 Group 2 Group 3 D6.

the receiver can now make changes in D5 to convert it to other possible value i. the passing of Group 3 means that all D6. Scientech Technologies Pvt. 15 . Parity Check Results on ST2104 Group-l D6 D5 D4 C2 PASS PASS PASS PASS PASS PASS PASS PASS 1. D4. As D6 is received correctly clear from Group 3 the only bit which can be in error is Bit 5 i. Thus the data word is corrected to 0001010. Group-2 D6 D5 D3 C1 PASS PASS PASS PASS PASS PASS PASS PASS Group-3 D6 D3 C0 PASS FAIL PASS FAIL PASS FAIL PASS FAIL Location of Error No Error C0 C1 D3 C2 D4 D5 D6 Recommended testing instruments needed for experiments in this work book Oscilloscope 20 MHz. D3 & C0 are valid. Since the corrupted bit has been detected. The receiver now discards the redundant check bits (C2. In the above two groups the only common element except D6. Ltd. where the following parity check was carried out & the listed groups failed. Dual Trace. ALT Trigger with bandwidth Oscilloscope Probes X1 – X10 etc. a case. 2.ST2103 & ST2104 Group 2 Group 3 D6 D6 D5 D4 D3 D3 C1 C0 If none of them fails. Suppose. C1 & C0) and passes the valid data (0001) to the input of D/a converter table given below gives the location of possible single bit errors. Group 1 Group 2 Group 3 D6 0 D6 0 D6 0 D5 1 D5 1 D4 0 D4 0 D3 1 D3 1 C2 0 C1 1 C0 1 Passed Failed Failed If we suppose only a signal bit corruption. is D5. then no error has occurred in transmission & all bit values are valid.e. D5. '0'.e.

ST2103 & ST2104 Experiment 1 Objective : Study of Error Check Codes Procedure : 1. Set Up the following initial conditions on ST2103 : a) b) c) d) e) f) 2. Error check code selector switches A & B in A = 0 & B =0 Position ('Off' Mode). Pseudo random sync code generator switched ‘On’. Turn ‘On’ the power. DC l Output to CH 0 input (TP 10). CH 0 Input (TP10) to CH 1 input (TP12). Connect the grounds of both the trainers. Mode Switch in FAST Position. All switched faults 'Off'. . a) b) 6. 7. Pulse generator delay adjusts control in fully clockwise position. 16 Scientech Technologies Pvt. All switched faults 'Off'.4. Pseudo random sync code generator switched ‘On’. DC l & DC 2 amplitude controls in function generator block in fully clockwise position. PCM output (TP44) of ST2103 to PCM data input (TP1) of ST2104. Mode Switch in FAST Position. Set ~1 KHz & 2 KHz signal levels in function generator block to 10Vpp. Set Up the following initial conditions on ST2104 : Make the following connections on ST2103 (See Figure 4) : Make the following connections between ST2103 & ST2104 see Figure. PCM data input (TP1) to clock regeneration circuit input (TP3). Output of clock regeneration circuit (TP8) to RX clock input (TP46). Ltd. a) b) c) d) e) 3. a) b) 4. This ensures that the two channels contain the same information. Error check code selector switches A & B in A = 0 & B =0 positions ('Off' Mode). Make the following connections on ST2104 (See figure 4) : a) b) 5. Ensure that the frequency of the VCO in the receiver clock regeneration circuit has been correctly adjusted Connect a) Channel 1 of oscilloscope to (TP10) on ST2103.

11. You can verify that the data in the A/D converter Block of ST2103 is always the same as the data in D/A converter Block of ST2104 also the output voltage of TP33 of ST2104 should be same as the input voltage at TP10 of ST2103 for all DC input levels. 9.ST2103 & ST2104 b) c) Channel 2 of oscilloscope to (TP33) on ST2104. Adjust the 1 KHz amplitude level fully clock wise. Notice the number of '1's in the transmitted data streams. But since D0 bit was used as parity bit. Once the error detection logic has decided whether an error has occurred. Carry out the same experiment with 1 KHz sine wave applied at CH 0 & CH1 Input of ST2103. it is always forced to a '0'. 17 . on both the trainers. but odd parity selected this time. Vary DC l and note that the data is transferred correctly between the two trainers. Ltd. Is it ever ‘Odd’? Note : ST2103 uses the least significant bit (LSB) of the 7 bit word to transmit the parity bit. Scientech Technologies Pvt. Select even parity with error check code selector switches A & B at A=0 & B=1 position. Set up various codes from A/D Converter's output LEDs some containing even no of l's & some odd. Compare the output of the data latch led (TP16 to 22) with input to the D/A Converter LED in each case. Check the error check code generator output of ST2103. Set up the error check selector A & B switches to A = 1 & B = 0 position on both trainers to select the odd parity mode carry out steps 8 & 9 again. Its value is changed to achieve the correct parity for each word. Data latch output (TP16 to 22) on ST2104 & D / A Converter input (TP23 to 29) on ST2104. 10. 8. it must pass the received code to the D/A converter. Notice that the quantized values on output of A/D Converter is not necessary but same to be applied to D/ A Converter receiver end due to the action of error detection logic.

ST2103 & ST2104 Figure 4 Scientech Technologies Pvt. 18 . Ltd.

time division multiplex and many such channels. quantizes it & code it by analog to digital conversion. this is discussed in forth coming parts. If we take an 8 bit word. 19 . Ltd. Since binary value changes in discrete steps & is not continuous like analog waveform. As with all engineering processes. The group of n bits is called as word and is used to distinguish one code from the other. Every binary number indicates one level.e. It is not possible to represent all the analog values (which are infinite in number) by limited binary words e. The range of decimal numbers represented by such n bits code is equal to 2n (including 0) e. The range of binary values used is the design feature of the system & depends upon the amplitude range of the signal and the accuracy of the conversion to be achieved. the number or different codes possible is equal to 28 = 256 i.g. we have 0 to 255 code levels available. Most systems use an 8 bit word length which is practically found most suitable to cover the sufficient range & provide the accuracy needed for speech signals. The two major problems associated with quantization are : 1) One major problem associated with quantization is due to the discrete nature of binary numbers which are used to represent continuously variable analog waveform. if in the figure 5. what will happen? Figure 5 Scientech Technologies Pvt.g. some distortion creeps in at the time of value assignment. The process of allocating the binary values to each sample taken in PAM system is known as quantization.ST2103 & ST2104 A/D Conversion The PCM Transmitter samples the analog input. As it is known. the analog value lies in between the two voltages represented by 0011 & 0100 binary words. This range can be used to indicate any range of voltage. the binary number system consists of binary digits '0' and '1'. quantization produces its own problems & an engineering compromise is then called for.

The Status pin goes High indicating that a conversion is in process. This leads to distortion of the information signal & the approximation is random for different voltage levels. 20 . & CE pins. CS. The CE & CS pins are tied to logic 0. Quantization noise can be reduced by increasing the number of bits used to represent a sample. but usually the duration of the sample pulse is much smaller than the conversion time. At the end of the conversion the Status pin goes Low. On ST2103 the A/D converter used is AD670. The LSB (D0) is ignored. 2) The second problem is associated with the finite time taken by the A/D Converter to complete the translation from analog to binary code. The sample and hold circuit holds the sample value for the A/D Conversion time. Only 7 most significant bits out of 8 data outputs are used on ST2103. Ltd. An A/D Converter requires that the sample value should remain unchanged till the conversion is complete. But it can never be eliminated. This problem can be overcome by using a sample and hold circuit prior to A/D input. This EC is used to latch the valid data into Dtype Flip-Flops (see circuit description in operating manual). Hence it is known as quantization noise. The R/W pin directs the converter to read or start a conversion. The quantization & Coding process is carried by the A/D Converter. It is an 8 bit A/D converter. Scientech Technologies Pvt.ST2103 & ST2104 In such cases the system allocate a binary number closest to the sample value. On ST2103 the R/W pin is named as SC (TP7) and pin after inversion is named as EC (TP8). Increasing the number of bits in a word has an effect of increasing the number of quantization levels. The A/D conversions are controlled by R/W.

Observe the output on the A/D converter block LEDs (D0 to D6). 2. Pseudo . e. DC l output to CH 0 input DC 2 output to CH 1 input Connect on ST2103 : Turn ‘On’ the power. The LEDs represent the state of the binary PCM word allocated to the PAM sample being processed. Observe that the output for +5V is as follows : D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1 Where for the negative values it is less than 1000000 for -5V the output is as follows D6 D5 D4 D3 D2 D1 D0 21 Scientech Technologies Pvt. c. d. This output is the digital representation of 0V input to CH 0 5. 3. Adjust the DC1 amplitude control clockwise to increase the amplitude & anticlockwise to decrease it. . An illuminated LED represent a '1' state. Ensure the following initial conditions on the ST2103. b. Take care that the input value is within the specified range of +/20mV. a. fully counter clockwise. All switched faults 'Off'.5V in steps of 1V. fully clockwise.ST2103 & ST2104 Experiment 2 Objective : Study of Analog to Digital Conversion Procedure : 1. DC l & DC 2 Controls in function generator block. With the help of digital voltmeter / oscilloscope. The LED output looks as follows. while non illuminated LED indicates a '0' state. Ltd. Error check code selector switches A & B in A = 0 & B= 0 position ('Off' Mode). ~ 1 KHz & ~2 KHz signal controls set to 10Vpp. adjust the DC l amplitude control until the DC 1 output measures 0V: The accuracy should be within +/-20mV. b. D6 is the MSB & D0 is the LSB. Try varying the DC input from + 5V to . f.random sync code generator switched 'Off'. a. D6 1 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 4. Mode switch in fast position. Turn the DC 2 amplitude control.

Once again take the precaution of maintaining the set input within +/. Connect oscilloscope channel 1 input to SC test points (TP7) & oscilloscope channel 2 input to EC test point (TP8). Switch 'Off' the trainer. Scientech Technologies Pvt. Observe the phase relation between the two SC & EC test point. Disconnect the DC 1 & DC 2 supply from CH 0 & CH 1. Ltd. 6. Turn the DC 1 control fully anti-clockwise and repeat the above procedure by varying DC 2 control. 9. Observe the signal at CH 0 & CH 1 sample output (TP5) with reference to the SC Signal (TP7) on the second trace. Give a special attention to the phase relation between the two signals. 10. Trigger the dual trace oscilloscope externally by the CH 1 signal available at TP12. Notice that EC goes high at the end of conversion & remains latched until next SC Pulse. 22 .ST2103 & ST2104 0 0 0 0 0 0 0 This is obtained at the approximately full anti-clockwise position of the DC Control.20mV range of the specified voltage. Connect ~1 KHz signal to CH 0 & 2 KHz signal to CH 1 input. Now connect the oscilloscope channel 1 to CH 1 sample (TP6) sketch the three waveforms with utmost importance to the relationship between the three waveforms. Check that the digital code for the set voltage value is identical to that of the DC 1 setting. 7. 8.

The two important parameters in serial signaling are 1. Thus the signal in the form of a word is passed. Ltd. b. This mode is faster. For long distances. format over parallel wires. namely a. The modulation rate or the signaling rate (in Bauds) & data transmission rate or bit rate (in Bits per second) The signaling rate or modulation rate is defined as the maximum rate at which the signal is switched between signaling rate (or number of symbols transmitted per second). 2. the signals are passed in parallel. It is a wasteful of transmission media as each bit requires a separate link. even more than few feet’s. See figure 6. The other way of defining modulation rate is that it is the reciprocal of the shortest time for which the signal remains in any state. Therefore the digital signals are transmitted serially over a single link. Figure 6 Scientech Technologies Pvt. The modulation rate is measured in Baud which is equal to one unit signal element per second. Parallel transmission Serial transmission In short distance communication like inside terminal equipment or two computer terminals located near each other. 23 . this is uneconomical & inefficient way of transmission.ST2103 & ST2104 Digital Transmission There are two methods for sending digital data over a distance.

then the modulation rate is S = 1 / 5 x 10-3 = 200 Bauds.e. As you can notice from figure 8 whatever is on parallel inputs (A. The operation of the shift register is shown in figure 8. Similarly. When S/L is high the subsequent shifting occurs on each positive edge of clock pulse. B. QB. When S/L is low & there is a positive (rising) edge of clock pulse. Its unit is Bits / second (also written as bps). D) is reflected as parallel outputs (QA. QD). the data on out board is transmitted serially by loading it into the shift register. Ltd. Signaling rate S = 1 / T 1 Bauds While the data transmission rate is Bit rate = 1 / T 1 log 2 2 = 1 / T 1 bits second If we use 4 state signaling the data transmission rate becomes Bit rate = 1 / T 1 log 24 = 1 / T 1 x 2 = 2 (1/T 1) = 2 (signaling rate) i.ST2103 & ST2104 From figure 6 it is clear that S = 1 / T 1 Bauds e. Each shift register can shift only 4 bits and make it a 7 bit register. Scientech Technologies Pvt. The two terms are often confused in computing because of the use of binary (0 or 1 state) system. if the shortest pulse duration is 5 ms.g. The data transmission rate is defined as the rate at which the data is transmitted over a channel. 24 . C. The ST2103 uses two 4 bits parallel to serial converter (shift Register). They are arranged as shown in figure 7. it is twice the signaling (modulating rate) Bit rate = 1/T 1 log 2 4 = 2/T1 log 22 = 2/T 1 bits/second In this case the Bit rate is twice the modulation rate. Where T 1 is the duration of unit signal element and L is the number of levels or the signaling states. QC. The data transmission rate is calculated as Bit rate = (1 / T1) x log 2 L bits / second.

Ltd.ST2103 & ST2104 The ST2103's A/D Converter outputs data in parallel format which is change into serial format by the shift register. This is known as parallel to serial conversion. Shift Register Organization Figure 7 Figure 8 Scientech Technologies Pvt. 25 .

These LEDs represent the latched output from the A/D Converter for every sample of CH 0 & CH 1 Channels. 5. Mode switch in fast position b. This is due to the slight change in voltage at Sample / Hold circuit at the time of switching. the two channels are sampled at different time. after 10 seconds. Note : You may find the A/D Converter's output may not be identical every time you switch the circuit from fast to slow mode for the same DC Control setting. Scientech Technologies Pvt. 4. Ltd. Notice that a particular combination of LEDs is lit in the A/D converter Block for approximately 7 seconds. Adjust the DC1 amplitude control such that the voltage measured at TP10 (CH 0) with the help of DMM / oscilloscope is + 3 Volts. 26 . Also since the trainer is working in fast mode. e. Turn ‘On’ the power. f. The LED outputs of A/D Converter & shift register are a combination of the two input voltages. Approximately. d. Pseudo random sync code generator on / 'Off' switch in 'Off' Position. 2. All switched faults 'Off'. ~1 KHz & -2 KHz control levels set to give 10Vpp. when the system has settled down to slow mode.ST2103 & ST2104 Experiment 3 Objective : Study of Control Signals and their Timings Procedure : 1. Set up the following initial conditions on ST2103 : a. Adjust the DC 2 amplitude control so that the voltage at TP12 (CH 1) is 2 V. Error check code generator switches A & B m A= 0 & B = 0 Position ('Off' Mode). Note the output of the A/D Converter. As stated earlier. DC 1 TO CH 0 II. However the change in code will only be 1 Bit. observe the LEDs of A/D converter Block. Make the following connections as shown in figure 9: I. DC 2 TO CH 1 3. DC 1 & DC 2 Controls in function generator block fully clock wise c. it is impossible to detect the code.

Ltd.ST2103 & ST2104 Figure 9 Scientech Technologies Pvt. 27 .

System Timing Diagram for ST2103 Figure 10 Scientech Technologies Pvt. 28 . Observe the interdependence of S/L. Ltd. Connect the oscilloscope at following points : a) Oscilloscope channel 1 to TX. clock output (TP3) b) Oscilloscope channel 2 to S/L test point (TP9) c) External trigger to TX. TX clock output and the shift register outputs as shown by their respective LEDs. to output (TP4) You may have to adjust the oscilloscope trigger levels to obtain a stable display. 7. The timing diagram for the process is shown in figure 10. The parallel data from the A/D Converter is then loaded in the shift register which converts in serial output. Record the waveforms.ST2103 & ST2104 6.

As can be noticed from the figure 11 below the samples consists of short pulses followed by another pulse after a long time interval. Clock (TP3). The basic 4 channel TDM is shown in figure 12 The switches S1 & S2 are rotating in the shown direction in a synchronized manner. This synchronization between S1 & S2 must be established by some means for reliable communication. The timing of the two switches is very important to ensure that the samples of one channel are received only by the corresponding channel at the receiver. This no-activity time intervals can be used to include samples from the other channels as well. Pulse Amplitude Modulated wave with large time Intervals between samples Figure 11 On ST2103. where S1 is sampling channel to the transmission media. The sequence of operation is repeated after every 15 bits. The time occupied by each clock pulse is called a Bit. TDM is widely used in digital communication systems to increase the efficiency of the transmitting medium.ST2103 & ST2104 Time Division Multiplexing Time division multiplexing is a technique of transmitting more than one information on the same channel. One such method is to send synchronization code (information) along itself to the transmitter all the time. the sequence of operation is synchronized to the transmitter clock TX.TO signal (TP4) which goes high during the bit time 0. 29 . In practice. The start of the timing frame is denoted by the TX. The various bits reserved for the data appearing in the middle of each transmitter clock cycle is shown in figure the figure 12 shows the complete timing frame Scientech Technologies Pvt. This means that several information signals can be transmitted over a single channel by sending samples from different information sources at different moments in time. Ltd. This technique is known as time division multiplexing or TDM. the switches S1 & S2 are simulated electronically. TDM can be achieved by electronically switching the samples such that they inter leave sequentially at a correct instant in time without mutual interference. The complete cycle of 15 bits is called timing frame.

All these requirements can be achieved by transmitting two essential information signals : I. Scientech Technologies Pvt. This results in a simplest receiver. Bit 1 to 7 : These carry a 7 bit data word corresponding to the last sample taken from the analog channel CH 0. b. 30 . Since the present timeslot corresponds to channel 0 it is known as timeslot 0. This time interval during which the coded information regarding the analog information is transmitted is called the timeslot. Ltd. As with channel 0 the least significant bit is transmitted first. A Frame synchronization signal. Synchronization signal.ST2103 & ST2104 Principle of 4-Channel TDM System Figure 12 Bit 0 : This bit is reserved for the synchronization of information generated by the Pseudo random sync code generator block More about its operation in the later section. The simplest method is to transmit the synchronization information & the clock over a separate transmission link. A Transmit clock signal. II. Bit 8 to 14 : This timeslot termed timeslot 1 contains the 7 bit word corresponding to the last sample taken of analog channel1. Remember that the trainer transmits the lowest significant bit (LSB) first. which allows the receiver to synchronizes its clock/operation with the transmitter’s clock operation. a. namely. The receiver requires two signals for its correct operation & reliable communication. However it is a waste of media & is not economical for long distance communications. Receiver clock operating at the same frequency as that of the ST2103 clock. When the Pseudo Random Sync Code is switched 'Off' a '0' is transmitted. It is used in data communication LAN (Local Area Network) & in telemetry systems.

e. The synchronization is established by sync codes transmitted along with the data stream. Mode 3 : Mode 3 is TDM system of one link between transmitter & receiver. Hence there is minimal loss of transmitted information. The ST2103 involves the use of a pseudo-random sync code generator. The Pseudo random sync code generator & Detector are switched 'Off' in this case. 31 . No need to say that the pseudo random sync generator & detector are switched ‘On’. These codes are bit streams of '0's & '1's whose occurrence is detected by some rules. which incoming data bit is associated with which transmitter timeslot The advantage of this technique is that if the synchronization is temporarily lost. TX clock & TX. Scientech Technologies Pvt. Clock output (TP3) & TX. In this mode the Pseudo random sync code generator & detector (on ST2104) are switched 'Off'. Also this technique also reduces the separate link required for the synchronization signal of transmission. These are information & TX clock signal links.TO output (TP4).TO (synchronization) signal links. there is equal probability of occurrence of '0' and '1 '. namely the link carrying information. Mode 2 : Mode 2 is TDM system of two transmission links between transmitter & receiver. They are information. Mode 1 : Mode 1 is TDM system of three transmission links between transmitter & receiver.ST2103 & ST2104 The ST2103 provides these two signals at TX. The Pseudo Random Sync Code gets its name from the fact that the occurrence of '0's & '1 's in the stream is random for a portion of sequence i. The second technique is to transmit the synchronization code along with transmitted data to be sufficiently different from the information samples. it can be re-established as the signal clears. Synchronization is again established by the sync codes. Ltd. This portion of sequence is 15 bit long on ST2103. On the receiver the pseudo-random sync code detector recognizes the Pseudo random code & use it to identify. The clock signal is regenerated by the phase locked loop (PLL) circuit at the receiver from the transition of the information data bits. due to noise corruption.

6. 5. Observe the timing & phase relation between the sampling signal TP10 & the sampled waveform at TP15. Connect channel 1 of the oscilloscope to TP12 & channel 2 of the oscilloscope to TP15. 32 . 12&15. 7. 4. Mode Switch in fast position DC 1 & DC2 Controls in function generator block fully clockwise. 3. Error check code generator switch A & B in A=0 & B=0 position ('Off' Mode) All switched faults 'Off'. Observe & explain the timing relation between the signals at TP10. First. 6. Scientech Technologies Pvt. connect only the 1 KHz output to CH 0 Turn ON the power. 5. Now connect also the 2 KHz supply to CH 1. Set up the following initial conditions on ST2103: a) b) c) d) e) f) 2. ~ 1 KHz and ~2 KHz control levels set to give 10Vpp. Connect channel 1 of the oscilloscope to TP10 & channel 2 of the oscilloscope to TP15. Check that the PAM output of 1 KHz sine wave is available at TP15 of the ST2103. Pseudo . Ltd. Turn 'Off' the power supply.ST2103 & ST2104 Experiment 4 Objective : Study of Time Division Multiplexing Procedure : 1.random sync code generator on/'Off' switch in 'Off' Position.

Set a value of 4Vpp for channel 0. Ensure the following initial conditions on ST2104 3. Display channel CH 0 Input (TP10) on oscilloscope channel 1 & use it to trigger the oscilloscope. d) Pseudo random sync code generator switched 'Off'. e) All switched faults 'Off'. (‘Off’ Mode) c) All four switched faults 'Off'. Make the following connections between ST2103 & ST2104. 9. 33 . f) Error check code selector switches. Mode switch in fast position. b) DC l & DC 2 Controls in function generator block. 2. Observe how the output at receiver changes. A & B in A=0 & B=0 position (‘Off’ Mode). Ltd. Also observe the two input signals TP10 & TP12 of ST2103 with the received sine wave samples TP32 & 35 of ST2104 and at the respective low pass filter outputs CH 0 & CH 1 (TP33 & 36) of ST2104. ST2103 ST2104 TX. Clock output TP3 RX clock input TP46 TX. Make following connection on board of ST2103 : 1 KHz To CH 0 Input 2 KHz To CH 1 Input 5. Display the ST2103 PCM output (TP44) on channel 2 of the oscilloscope. fully clockwise. To output TP4 RX sync input TP47 PCM output TP44 PCM input TP1 6. b) Error check code selector Switches A=0 & B=0 Position. 7. d) Pulse generator delay adjust control fully clockwise. c) ~ 1 KHz & ~2 KHz signal control set at 10Vpp. Scientech Technologies Pvt. Vary the amplitude of ~1 KHz & ~2 KHz signals at the ST2103. Note what is the output voltage of the received signal. 8.ST2103 & ST2104 Experiment 5 Objective : Study of Pseudo Random Sync Code Generator Procedure : 1. 4. a) Pseudo random sync code detector switched ‘Off’. Vary the amplitude of the 1 KHz & 2 KHz sine wave signal & note that the transmitted data changes. Ensure the following initial conditions on ST2103 : a) Mode Switch in fast position.

. 34 Scientech Technologies Pvt. Turn ‘On’ the trainer. Notice the waveforms & confirm that they are different. Now notice the two waveforms again. Notice that the sync bit counter LED goes 'Off' indicating that the synchronization has been lost. They should be identical when frame synchronization has been achieved. Observe the TX. ST2103 ST2104 TX. Turn ‘On’ the power. Notice the sync Bit counter LED. 17. in pseudo random sync code detector Block of ST2104 is ‘On’ in FAST Mode. Do you notice any change in the observed waveform at TP36 on ST2104. Turn 'Off' the power. This also confirms that the two are in 'Frame Synchronization'.TO (TP48) output signal on ST2104.TO (TP4) output signal on ST2103 & RX. Explain the reason behind the mismatch. Notice the sync coded output for a high level occurrence at the TX to output. 11. Notice the changes observed waveform at TP36 of ST2104. Turn 'Off' the power Remove the link between RX. Rearrange the connections between ST2103 & ST2104 as follows. 14. If necessary switch the two trainers to slow mode. 12. Vary the setting of ~2 KHz signal & observe the waveform at TP36. There fore observe carefully. But now the synchronization has been established because of the separate link between ST2103 & ST2104. 18. To be able to perceive the pattern of the sync code generated. 19. 13. Do you notice any change? Why it has happened? Now you must have observed the importance of synchronization. clock output RX clock input PCM output PCM input Connect Channel 1 of the oscilloscope to TP12 on ST2103.TO output from ST2103 to RX sync input on ST2104. Turn ‘Off’ the power.SYNC & TX. connect the oscilloscope probes to TP4 (TX. This is an indication that the receiver has identified the transmitted bit time 0 & is using it for all its timing operations.TO. Notice at the same time that the sync error counter led goes ‘On’. This goes to show that synchronization has been lost. 21. Observe the two mismatched waveforms.TO output & TP42) (Pseudo random sync code generator output). Connect TX. Ltd.ST2103 & ST2104 10. Turn ‘On’ the power. 20. Note the LED indication may be faint. Channel 2 of the oscilloscope to TP36 on ST2104. Switch 'Off' the pseudo random sync code generator. Turn the pseudo random sync code detector on ST2104 ON. 15. 16. Now turn ‘On’ the pseudo random sync code generator on ST2103.

DC l & DC 2 Controls in function generator block fully clockwise. All switched faults 'Off'. ~ KHz Signal to CH 0 Input. 35 . Set up following initial conditions on the ST2103: a) b) c) d) e) 2. Turn ‘On’ the power. II.ST2103 & ST2104 Experiment 6 Objective : Study of Three Modes of Transmission Procedure : 1. Vary the ST2103's ~1 KHZ and ~2 KHz controls (which vary the amplitude of the two sine waves) and note how the transmitter data changes. 5. Observe that the 1 KHz sine wave input appears at TP10 (CH 0 Input) & 2 KHz sine wave input appears at TP12 (CH 1 Input). All switched faults 'Off'. Ltd. Mode Switch in fast Position. ~2 KHz Signal to CH 1 Input. Clock output TX. Observe the two waveforms. ‘On’ ST2103 : I. Pulse generator delay adjusts control in fully clockwise position. b. Pseudo random sync code generator switched 'Off'. Set up following initial conditions on ST2104 : Make connections as shown in figure 13. Connect Channel 1 of oscilloscope to CH 0 Input (TP10) Channel 2 of oscilloscope to PCM output (TP44) Trigger the oscilloscope with CH 0 input. Between ST2103 & Receiver trainer ST2103 TX. Mode Switch in fast Position. a. Pseudo random sync code detector switched 'Off'. Clock input RX sync input PCM data input 4. Scientech Technologies Pvt. Error check code selector switches A & B in A=0 & B=0 Position. Error check code selector switches A & B in A=0 & B=0 position.TO output PCM output ST2104 RX. a) b) c) d) e) 3.

The A/D converter 7 Bit word output can be monitored on LEDs provided in the A/D converter block. Observe that the D/A Converter LED contain the same data for a particular set of input amplitude. The output logic block adds a half timeslot delay to it. Scientech Technologies Pvt. The sequence of operation on ST2103 is fully synchronized to the TX. Vary the DC. 7. Make following connection on ST2103 : a. Turn 'Off' the trainer. a '0' is transmitted in this timeslot. Vary the amplitude of the input signal observe that the same changes are reflected at the receiver. These 15 timeslots are collectively called 'Timing Frame'. 36 . In this case also the least significant bit is transmitted first. Thus the output (TP44) of output logic block contains transitions halfway through each timeslot. Since the length of the code is 15 bits. Clock signal.1 control. DC. BIT 8 to 14 : These bits carry the 7 bit data word of the last sample taken from channel 1. Observe the receiver channel output with the corresponding transmitter channel input on a dual trace oscilloscope. Each clock cycle is known as timeslot. 9. The operations of the trainer repeat after 15 timeslots. the Sync code repeats after 15 timing frames.ST2103 & ST2104 6.1 to CH 0 b. CH 0 to CH 1 8. Observe on the oscilloscope at TP10. The start of the timing frame or Bit 0 is indicated by high level at TX. The data appears at the output logic block at the start of each timeslot. Set the amplitude of each sine wave to 8Vpp. Display CH 0 (TP33) & CH 1 (TP36) of ST2104 on two channels of the oscilloscope. This is because the input exceeds the dynamic range of the A/D Converter. This clock signal can be monitored at TP3. The output may get flattened at peaks if the input sinusoidal signal voltage exceeds 10Vpp. The amplitude should vary between -5 to + 5V. Notice the output waveform at CH 0 (TP33) or CH 1 (TP36) of ST2104. Ltd. Turn ‘On’ the power. Notice that the two outputs are identical to that transmitter by the transmitter. code). Observe the PCM output (TP44) with respect to the input signal to output logic block (TP43) & with TX. The information appearing at the middle of the timeslots is as follows. BIT 1 to 7 : These bits carry the 7 Bit data word of the last sample taken from the channel o. The Pseudo random sync code generator outputs a single bit in this timeslot. Variation of the input voltage from -5V to +5V will cause the output of A/D Converter to vary from 00 Hex to 7F Hex. Clock signal (TP3). BIT 0 : This carries the synchronization information (sync. At this instance the pseudo random sync code generator is 'Off'. Notice that the least significant bit (LSB) is transmitted first.TO output (TP4).

ST2103 & ST2104 Figure 13 Scientech Technologies Pvt. Ltd. 37 .

.... b.. the receiver must be able to detect & distinguish these sync bits from the normal information bits.. We say that the receiver is 'Frame Synchronized' to the transmitter. 11. This ability is imparted by the Pseudo random sync code generator & detector present on ST2103 & receiver trainer respectively. 14. Switch 'Off' the pseudo random sync code generator...TO (TP 4) & RX sync (TP 47).... We say that the receiver has lost the frame synchronization.. TX clock signals clocks the receiver at the same rate where as the TX.. TO signal helps the receiver to identify the timeslot 0.TO & RX. Remove the link connecting TX.. Ltd. Switch the boards to FAST mode. The three wire connections can be reduced to two wires by developing the ST2103's ability to transmit the synchronization information along the data. Similarly. e..... The above mode is termed as 'connecting Mode 2'..... c. 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 .A..TO signals on separate links. One bit of this sequence is transmitted in every frame at timeslot 0. Switch ‘On’ the pseudo random sync code generator on ST2103. As it has been discussed earlier.. 38 ... d. The receiver detects it & uses it to decide which timeslot is for which frame.... You can observe the two waveform at TP4 of ST2103 & at TP48 of ST2104 respectively.. Connect DC 1 to CH 0 & CH 0 to CH 1 13....TO signals are identical.... 12... Notice that the A/D converter block output observed on LEDs is not similar to the D/ A Converter Block input.... the TX. Repeating.... a. The ST2103 / Receiver can be configured in this mode as shown in figure 14.. The Receiver indicates this by turning 'Off' the sync bit counter led in pseudo random sync code detector block..... for correct operation the receiver needs to be clocked" at the same rate as the transmitter & it should be able to decide which timeslot is for which information transmit TX clock & TX. This signifies that the receiver knows the transmitted timeslot & can identify them.. Scientech Technologies Pvt.... converter of ST2104 always carries the same code..... The pseudo random sync code is a sequence of 15 bits generated by the pseudo random sync code generator. Vary DC 1 and note that the LEDs on the A/D converter block on ST2103 & D.ST2103 & ST2104 10... Also observe that the sync bit counter led in the pseudo random sync code detector block is ‘On’. Once the transmitter & receiver is frame synchronized... Switch ‘On’ the pseudo random sync code detector on ST2104.

39 .ST2103 & ST2104 Figure 14 Scientech Technologies Pvt. Ltd.

Link between TX clock (TP3) & RX clock (TP46) has been removed. 20. data. b. Observe the ST2104 analog outputs (TP33 & 36). PCM data input (TP1) on ST2104 is connected to the input (TP3) of phase locked loop circuit on the same trainer. switch the ST2103 & receiver into slow mode. The receiver establishes the synchronization from pseudo random sync code transmitted along with the P. b. 40 . The number of connecting links can be reduced further to one by configuring the ST2103 & receiver in connecting Mode 3. Both trainers are switched in FAST Mode. ~ 1 KHz Signal to CH 0 input.M.ST2103 & ST2104 15. Scientech Technologies Pvt. c. You can observe the two signals at TP10 & 12). a. Ltd. Verify that the two outputs are identical to that applied at the transmitter's inputs. The phase locked loop output (TP8) is connected to the RX clock input (TP46) on the ST2104. 19. If you desire to examine the timing of data flow & control signal in detail. Follow the procedures given below to trim the VCO frequency : a. (This happens when there is a long stream of '0's to '1's in the. In this case it has to regenerate the clock signal as well. b. The receiver does this by on board phase locked loop circuit which regenerates the clock from the transitions of the data bit whose timing with respect to the clock signal is fixed. Slowly. Repeat the above steps till position of the control is found such that the sync bit counter led remains ‘On’ for both fully clock wise & anticlockwise positions of the DC1 Control. The only connecting link between transmitter & receiver is the data/information link. Note : Turn 'Off' the power when new connections are made or disconnected. so that the regenerated clock remains in synchronization with the incoming data even when few transitions occur. At the ST2103. Turn the DC1 control in the function generator block on ST2103 fully clockwise.C. Before operating in connecting Mode 3 it may be necessary to trim the voltage controlled oscillator (VCO) frequency. Configure the ST2103 & receiver as shown in figure 15 and ensure the following statements : a. Adjust the outputs of the two generators to 8Vpp by the amplitude controls provided in the Function generator block. remove the CH 0 & CH 1 inputs & connect. 16. d. ~ 2 KHz Signal to CH 1 input. 18. turn the VCO frequency adjust control on ST2104 until the sync bit counter led in the pseudo random sync code detector Block turns ‘On’. 17. c. NRZ (L) waveform).

it can detect the error in the transmitted data. Even Parity : This option is selected by placing A & B switches in the error check code generator block in ST2103. b. d. If the Error Check Code Detector in ST2104 is switched into same . C1 & C0 are the Hamming check bits. The Error check code generator replaces some least significant bits of the 7 Bit word with some error check bits. but cannot tell which bit is in error. No error check code is inserted in the 7 Bit word. 'Off' : The error check generator is 'Off' when this mode is selected by switching the A & B switches in the error check code generator block in ST2103 in A = 0 & B = 0 position. This provides an opportunity to detect & if possible to correct the erroneous trainer data. c. The word format is. it can detect the error & even connect the erroneous transmitted data bit (only single). The word format is : D6 D5 D4 D3 D2 D1 C0 Where C0 is the parity check bit which is chosen such that the total no of '1's in the 7 bit word are even. It indicates the erroneous bit by lighting the corresponding LED in hamming code error block. it can detect the error in the transmitted data. Illustration of various check codes are given in steps 22nd to 29th : 41 Scientech Technologies Pvt. The trainers have on board error check generator & detector (on ST2103 & ST2104 respectively). The word format is D6 D5 D3 D2 D1 D0 Where D6-D0 are the A/D Converters latched outputs. The word format is : D6 D5 D4 D3 C2 C1 C0 Where C2. Odd Parity : This option is selected by placing the A & B switches in the error check generator block in A = l & B = 0 position.Bit word is replaced by a single parity bit.mode. If the error check code detector in ST2104 is also configured in this mode. The following error check options are available on board : a.ST2103 & ST2104 21. In this case the three check bits replace the three least significant bits of the 7 bit word. Ltd. Hamming Code : This option is selected when the A & B switches in the Error check code generator on ST2103 are placed in A=1 & B=1 position. In A = 0 & B=1 position. It indicates 'the error by switching ‘On’ of the Parity Error LED. . The least significant bit of the 7 bit word is replaced by a single parity bit. but it cannot tell which bit is in error. D6 D5 D4 D3 D2 D1 C0 Where C0 is the parity check bit such that the total no of '1's in the 7 bit word are odd. It indicates the error by switching ‘On’ of the parity error LED. If the error check code detector in ST2104 is also included in this mode. The least significant bit of the 7 .

You can induce any switched fault /faults in the ST2103 & ST2104 trainer to investigate the effect of particular faults on the whole system. Connect the ST2104's CH 0 (TP33) & CH 1 output (TP36) to the two channels of the oscilloscope. Switch ''Off'' the fault. Ltd.e. the receiver has detected the error in transmitted data but is not in a position to locate which bit is in error. You can carry on the same experiment by selecting the odd parity option. 24. Notice the distortion in the output in the output sine waves at the ST2104's CH 0 (TP33) & CH 1 (TP36) outputs. This also allows you the opportunity to practice & test your skills in fault detection trouble shooting. 23. The list of various faults that can be induced in the system is given in this manual. This fault forces the D6 bit (MSB) of the transmitted 7 bit word to be always '1' even when there must have been a '0'. You will get the same result as the earlier ones. Note switch 'Off' the fault prior to selecting the Error check code option. Introduce even parity error check code option on both the trainers by switching the A & B switches in the corresponding block to A=0 & B=1 position. Notice. Select the hamming code option by placing the A & B switches in the corresponding block to A = 1 & B = 1 position. now that the outputs at CH 0 & CH 1 on ST2104 are now distortion less. 26. 27. Switch ‘On’ fault '2' again. This is because the erroneous bit has even been corrected by the receiver. Therefore the output at CH 0 & CH 1 on ST2104 still remains distorted. It reveals the erroneous bit in the data format by lighting the corresponding LED (D6 in the present case). 25. Observe the two output waveforms at ST2104's CH 0 (TP33) & CH 1 (TP36) outputs are distortion less & also observe the LEDs in the error check code detector block are 'Off'. Scientech Technologies Pvt. Switch 'Off' the fault. 28. it can detect as well as correct one bit error in a sample. Switch ‘On’ fault '2' Observe that the D6 LED marked in error check code detector's hamming code error bit glows. Observe that the parity error indicator LED in error check code detector glows i. Since its 3 bit hamming code.ST2103 & ST2104 22. 29. 42 . Now introduce the switched fault '2' in the trainer system by switching ‘On’ the pole 2 of switched faults Block.

43 .ST2103 & ST2104 Figure 15 Scientech Technologies Pvt. Ltd.

You can reduce the baud rate of both PCs and you will observe that the transmit rate is lower. 11. Install the Software on both the PCs. 98. 10. 5. (Before connecting perform the experiment no. Now type a message in the message window of PC1 and click send. Ltd. It will need the following : System : Microsoft Windows 95. Keep PCs on either side of the ST2103 & ST2104. Switch ‘On’ the trainers. It utilizes these two channels to communicate between two computers. 9. 7. Scientech Technologies Pvt. Connect the RS232 cable to the serial port of the computer and the other end to ST2103 & ST2104 as shown in figure 16. select the com port in the "COM Port" window. you will see that the data transmission has failed. 44 . After establishing a connection. Make the interconnections between ST2103 & ST2104 as shown in the figure 16. 8.6 in mode 3). you will see the message in receiver window of PC2 and in transmit window of PC1. 4. 6. If you send a message from PC2 you will receive the message in the receiver window of PC1 and in transmitter window of PC2. Follow this procedure for both the computers. or above Software : Supplied with the trainer in CD Procedure : 1. thus forming a full duplex link.ST2103 & ST2104 Experiment 7 Objective : Computer Communication using RS232 interface via ST2103 & ST2104 There are two channels provided on ST2103 & ST2104. If you disconnect any of the transmitting or receiving wire. 2. and select Baud rate (same on both PC’s). 3.

ST2103 & ST2104 Figure 16 Scientech Technologies Pvt. 45 . Ltd.

46 . Install the software provided with the trainer in all the four PCs. Procedure : 1. 6. 3. Connect the RS232 cable to the serial port of the computer and the other end to ST2103 & ST2104 as shown in figure 17. It utilizes these two links to communicate from two PCs on one end to two PCs on other end. 98. and those connected to ST2104 will act as receiver. 7. Pulse code modulated and transmitted via single wire and then.ST2103 & ST2104 Experiment 8 Objective : Multi point to multipoint communication using RS232 interface via ST2103 & ST2104 There are two channels provided on ST2103 & ST2104. demodulated–demultiplexed and received by PC 3 and PC4 respectively. 4. or above Software : Supplied with the trainer in CD. Make the interconnections between ST2103 & ST2104 as shown in the figure 17 (Before connecting perform the experiment no. 5. Switch ‘On’ the trainers. This will be a one way communication. Keep the PCs on either sides of the ST2103 & ST2104.6 in mode 3). It will need the following: System : Microsoft Windows 95. Now the data transmitted by PC1 and PC2 will be multiplexed. Run the software in all the PCs and select the respective COM ports and the same baud rate in all the PCs. Scientech Technologies Pvt. Ltd. 2. The two PCs connected to ST2103 will act as transmitter.

Ltd. 47 .ST2103 & ST2104 Figure 17 Scientech Technologies Pvt.

3. Keep one PC to the left of ST2103 (master) & two PCs to ST2104 (slaves) as shown in figure 18. Make the interconnections between ST2103 & ST2104 as shown. 2. 4. or above Software : Supplied with the trainer in CD Procedure : 1. It utilizes these two links to communicate from one PC to the two other PC's on the other end.ST2103 & ST2104 Experiment 9 Objective : Point to multipoint communication using RS232 interface via ST2103 & ST2104 There are two channels provided on ST2103 & ST2104. This will also be a one way communication. 48 . 98. Switch ‘On’ the trainers. Scientech Technologies Pvt. Ltd. Now the data or instructions transmitted by the master will be received by the two slaves. Install the software provided with the trainer in all the three PCs. System : Microsoft Windows 95. Connect the RS232 cable to the serial port of the computer and the other end to ST2103 & ST2104 as shown in the figure 18. 6. 5. The PC on the transmitter side will act as master and the PCs on receiver side will act as slaves. Run the software and select the respective COM ports and same BAUD rate in all the PCs.

49 . Ltd.ST2103 & ST2104 Figure 18 Scientech Technologies Pvt.

Transmitter Switched Faults : Following faults can be induced in the ST2103 to study their effects on the system & to practice fault-diagnosis techniques. Hence if the receiver is relying on pseudo random sync code for synchronization as in connecting Modes 2 & 3. The fault occurs before error check code generator & hence cannot be detected by the receiver’s error detection correction logic. This fault is induced after the error check code generator block & hence can be detected & in case of hamming code selected. In case of hamming code. the receiver may try to correct the wrongly diagnosed 'error' thus distorting the output in this process. It causes the generator to generator a sequence which is not Pseudo Random in Nature. the receiver loses frame synchronization. Receiver Switched Faults The Following faults can be induced in the ST2104 receiver trainer to study their effects on the system & to practice fault diagnosis techniques Switched Fault 1 : This fault breaks the loop between phase locked loop output & loop filter's input on ST2104 receiver trainer. can be corrected also if the same mode is selected on error detection & correction logic on receiver trainer also. Hence the output of the receiver is not always a true representation of the applied analog input at the transmitter. Switched Fault 2 : The switching ‘On’ of this fault cause D6 bit of the P. This fault can be used to study the utility of the error check codes in case of bit corruption in the P.M. Switched Fault 4 : This fault affects the pseudo random sync code generator. Switched Fault 3 : This fault causes the error check code generator to treat the A/D converter's D5 output to be always high irrespective of the actual D5 bit in P. This distorts the receiver's output. Hence the receiver doesn't clock into synchronization in connecting Mode 3. Switched Fault 1 : Switching ON of this fault causes the A/D Converter's D6 Output to be always '0'. irrespective of the applied analog input.C. output of the transmitter to be always '1' irrespective of the connect D6 bit level.C.ST2103 & ST2104 Switched Faults 1. Remember PLL circuit is used to extract clock information in connecting Mode 3.C.M. data transmitted. data along the transmission path. 50 . data has a fault. 2.C. Ltd. This fault has no effect when none of the error check code option is selected the receiver may wrongly decide that the P. Thus induction of this fault cause the malfunctioning of phase locked loop circuit.M.M. Scientech Technologies Pvt.

Indicated Error C1 D3 C1 D5 D3 D6 D5 D6 Bit Corrected None D3 None D5 D3 D6 D5 D6 Scientech Technologies Pvt. the receiver may decide that the wrong bit is in error. If the received data actually contains an incorrect bit. Hence in connecting Mode 2 & 3 in which the ST2104 depends on sync code detection for frame synchronization this fault cause the receiver to continuously try to resynchronize but to do so every time. Switched Fault 3 : This fault affects the ST2104's error detection/correction logic when the hamming option is selected. 51 . the receiver cannot detect the transmitted pseudo random sync code. try to correct it. Ltd. This causes the receiver's channel 1 output CH 1 (TP36) to drift down to 10V supply. and if that bit is a data bit. The effect of this fault is detailed in the table below.ST2103 & ST2104 Switched Fault 2 : This fault affects the functioning of ST2104's pseudo random sync code detector. It causes an error in C1 to be indicated when the received data and check bits are correct. When this fault is induced. Bit Received In Error None C0 C1 C2 D3 D4 D5 D6 Switched Fault 4 : This fault open circuits the ST2104's channel 1 sample & hold amplifier.

on ST2103 fully clock wise. 7. See figure 1. 3. providing that there are at least occasional rising transitions at PCM data output. a. Turn the VCO frequency adjust preset. Turn the DC 1 preset fully counter clockwise and check that the sync bit counter LED is still ‘On’ If the LED switches to 'Off'. c. Switch ‘On’ the ST2103's pseudo random sync code generator block and the ST2104's pseudo random sync code detector block. in the sync code detector block of ST2104 is ‘On’. retrim the VCO frequency adjust preset until the LED stays on for both extreme positions of the DC 1 preset. After following this procedure. Ensure 'that the ST2104's pulse generator delay control is in the fully clockwise position. CH 0 input to CH 1 input Switch on the power to the boards. Before connection mode 3 is used. Scientech Technologies Pvt. 6. Ltd. Ensure in ST2104 circuits that : All switched faults are 'Off'.ST2103 & ST2104 Setting Up the Receiver's Clock Regeneration Circuit The receiver's clock regeneration circuit contains a preset labeled VCO frequency adjusts. 2. Turn the DC 1 preset. even when the transitions in the data are only occasional. b. it may be necessary to trim the frequency of the VCO to ensure that the generated clock signal remains synchronized to the incoming data. The procedure for making this adjustment in ST2104 check regeneration circuit is as follows: 1. 8. 9. a. 5. 52 . b. The error check code selector switched are in the '00' ('Off') position FAST Mode is selected. Set up the system in connection mode 3. the receiver clock regeneration circuit should be able to synchronize on any transmitted data stream. The preset adjusts the free-running frequency of the phase-locked loop's voltage controlled oscillator (VCO). 4. on ST2104 until a position it is found where the sync bit counter LED. Make the following links at the ST2103 : DC 1 to CH 0 input.

......... 5......... 53 ..........Manual ...........................................2 Nos Patch Cord 20" ......................... serial number of the product and date of purchase etc............... List of Accessories 1...................... 6.................... 3.............1 No......................ST2103 & ST2104 Warranty 1.. if a) b) c) d) 3.............................. 4. Ltd.............. The repair work will be carried out.................. 4........ CD (Demo VCD) Supplied with Full Set ......2 Nos e.............2 Nos Patch Cord 16" ........................................................... The agreed payment terms and other conditions of sale are not followed........................... The transportation charges shall be borne by the customer.......... 7.... Mains Cord............................. Consumables like dry cell etc.......... 2.1 No.......... RS232 Cable .... The product is not operated as per the instruction given in the operating manual..... The customer resells the instrument to another party.......................1 No...........1 No............. provided the product is dispatched securely packed and insured................................ The guarantee will become void... Updated 05-08-2008 Scientech Technologies Pvt......................... Any attempt is made to service and modify the instrument............................... are not covered under warranty............................. 2............ Patch Cord 8" ... The non-working of the product is to be communicated to us immediately giving full details of the complaints and defects noticed specifically mentioning the type................... We guarantee the product against all manufacturing defects for 24 months from the date of sale by us or through our dealers.......