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Published by: Jannathul Firdous Mohamed on Feb 03, 2012
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The ARM architecture (previously, the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture that is widely used in a number of embedded designs. Due to their power saving features, ARM CPUs are dominant in the mobile electronics market, where low power consumption is a critical design goal.

ARM Evolution 

Evolved from the BBCs Microcomputer Developed by Acorn Computers Ltd of Cambridge, England between 1983 and 1985. First RISC processor available for commercial use. Lot of initial ideas borrowed from Berkeley RISC I and II and Stanford MIPS processors. Initially known as Acorn RISC Machine ARM Limited formed in 1990 after which the name got changed to Advanced RISC Machine

Steve furber Father of ARM

Memory Management Table Structure.     Instruction Set.Computer Architecture   Describes Users view of the Computer Eg. Exception Handling Models etc . Visible Registers.

Translation Look Aside Buffers etc .Computer Organization   Describes User Invisible Implementation of the Architecture Eg.    Pipeline Structure. Transparent Cache.

What is a Processor?    Finite State Automation Executes Instructions held in Memory State depends on values hold by registers & memory .

Switching to privileged mode .Instructions Types     Data Processing Data Movement Control Flow Special Instructions  Eg.

How will u improve the Processor Performance? Instruction Type Data Movement Control Flow Arithmetic Comparisons Logical Other Dynamic Range 43% 23% 15% 13% 5% 1% .

Pipelines       Fetch Decode Register Access ALU Memory. if necessary Write Back Pipeline Hazards .

RISC Organization    Hard Wired Instruction Decode Logic Efficiently Pipelined Single Cycle Execution .

RISC Advantages    A Smaller Die Size A Shorter Development Time Higher Performance (Bit Tricky) .

RISC Disadvantages 

Generally poor code density (Fixed Length Instruction)

Architectural Inheritance The ARM Programmers Model The ARM Development Tools Examples and Exercises

ARM History 


Acorn RISC Machine(1983 1985)

Acorn Computers Limited, Cambridge, England 


Advanced RISC Machine 1990

ARM Limited, 1990 ARM has been licensed to many semiconductor manufacturers

Features Used from Berkeley RISC 

A Load/Store Architecture Fixed Length 32-bit Instructions 323- Address Instruction Formats

Features Rejected from Berkeley RISC  Register Windows  Large no of registers out of which 32 Regs are Visible at a time. Procedure Entry & Exit move visible window to each procedure as new regs And thereby reduce Traffic between Processor & Memory.  Reason for Rejecting this feature:  Large Chip Area due to large no of regs.  In ARM Shadow Registers used to handle Exceptions are of similar concepts .

Not suitable for superscalar architectures .Features Rejected from Berkeley RISC  Delayed Branches Branches cause problem in Pipelines  Most RISC Processor overcome this problem using delayed branches where the branch takes effect after the followin instrn is excuted    Not implemented in ARM to avoid the complexity involved during exception and interrupt handling.

Features Rejected from Berkeley RISC  Single Cycle Execution of ALL Instructions    Single Memory for Instruction & Data Even a simple load/store will require at least two cycles Separate Data & Instruction was the solution but was too costly those times .

The ARM Programmers Model  When writing user level programs only    1515-general purpose 32-bit registers(r0-r14) & 32.registers(r0the Program Counter (r15) & the CPSR need to be considered  The remaining registers are only for system level programming & for handling exceptions .

32 1 dedicated program counter  1 dedicated current program status register  5 dedicated saved program status registers  30 general purpose registers However these are arranged into several banks.The Registers  ARM has 37 registers in total. Each mode can access  a particular set of r0-r12 registers r0 a particular r13 (the stack pointer) and r14 (link register)  r15 (the program counter)  cpsr (the current program status register) and privileged modes can also access  a particular spsr (saved program status register)  . all of which are 32-bits long. with the accessible bank being governed by the processor mode.

General registers and Program Counter User32 / System FIQ32 Supervisor32 Abort32 IRQ32 Undefined32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_svc r14_svc r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_abt r14_abt r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_irq r14_irq r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_undef r14_undef r15 (pc) Program Status Registers cpsr cpsr sprsr_fiq spsr_fiq cpsr spsr_svc cpsr spsr_abt cpsr sprsr_fiq spsr_irq cpsr spsr_undef sprsr_fiq .

Register Banks   Registers are divided into sets Each operating mode can access a unique set of registers containing     R0 to R12 : general purpose registers R13 : stack pointer R14 : link register R15 : Program counter  Each operating mode can access a unique set of status registers   CPSR : Current Program Status Register SPSR : Saved Program Status Register (only privileged modes) .

R14= link register(lr) and is where the core puts the return address whenever it calls the subroutine R15= program counter(pc) and contains the address of the next instruction to be fetched by the processor   .Special purpose registers  R13= stack pointer(sp) and stores the head of the stack in the current processor mode.

CPSR  In user level programs uses CPSR to store the condition code bits as a result of comparision & Arithmatic and logic opns  N. Z. mode[4:0] . F. T. C. V  The bottom bits are protected by the user level program  I.


Program Status Registers (CPSR and SPSRs) 31 28 8 4 0 N Z CV I F T Mode Copies of the ALU status flags (latched if the instruction has the "S" bit set). * Interrupt Disable bits. T Bit (Architecture v4T only) T = 0. disables the IRQ. C = ALU operation Carried out V = ALU operation oVerflowed Mode Bits M[4:0] define the processor mode. Z = Zero result from ALU flag. disables the FIQ. Processor in ARM state T = 1. I = 1. * Condition Code Flags N = Negative result from ALU flag. Processor in Thumb state * * . F = 1.

ARM Modes of Operations ° ° ° ° ° ° ° 10000 10001 10010 10011 10111 11011 Non-Privileged User Normal user code Mode FIQ Processing fast interrupts IRQ Processing standard interrupts SVC Processing software interrupts (SWIs) Abort Processing memory faults Undef Handling undefined instruction traps 11111 System Running privileged operating system tasks Privileged Modes .

used to ± service interrupts ± exceptions ± access protected resources (via SWI Instruction) ‡ Privileged modes ‡ User mode User mode OK Privileged modes NOT OK ± Only possible through Controlled mechanisms: SWI. Exceptions.User Mode vs Privileged Modes ‡ User Applications run in User Mode ‡ Privileged modes. Interrupts .

e least two bits are zero Half Words are aligned on even boundaries .The Memory System     Memory may be viewed as linear array of bytes number from 0 to 2^32 1 Data Bytes may be 8-bit (B). 16-bit (HW). 816or 32-bit (W) 32Words are always aligned at 4-byte 4boundaries i.

ARM Memory Organization bit 31 23 19 15 11 7 3 22 18 14 10 6 2 21 17 13 9 5 1 bit 0 20 16 12 8 4 0 word16 half-word14 half-word12 word8 byte6 half-word4 byte3 byte2 byte1 byte0 byte address .

LoadLoad-Store Architecture    Data Processing Instructions Data Transfer Instructions Control Flow Instruction .

ARM Instruction Set        LoadLoad-Store Architecture 3-Address Data Processing Instructions Conditional Execution of Instructions Powerful Load/Store Multiple Register General Shift Operation (Single Cycle) Extension of Instruction Set Co-processor Co1616-bit Compressed Instruction Set .

I/O System     Memory Mapped with Interrupt Support Internal Registers in devices will act as addressable locations in ARM s Memory Map Peripheral may use IRQ or FIQ May have DMA Support .

ARM Exceptions  ARM supports range of Interrupts. Traps. all grouped under general heading of Exceptions . Supervisor Calls.

ARM Development Tools  Software Development   ARM Ltd GNU Tools tools run on different architecture from one for which they produce code  CrossCross-development  .

ARM Development Tools C source C libraries asm source C compiler .axf debug object libraries system model ARMsd ARMulator development board .aof as sembler linker .


Agenda      Data Processing Instructions Data Transfer Instructions Control Flow Instructions Writing Simple Assembly Language Programs Examples and Exercises .

Data Processing Instructions   These are the only Instruction that modify the data values in ARM Typically require two operands & produce single results (though there are exceptions) .

if there is any. is 32-bits wide and is 32placed in a register (Exception: Long Multiplications) Each of the operand registers & the results are independently specified in the instruction (ARM 3-Address Instruction format) .Rules for Data Processing Instructions    All operands are 32-bits wide & come from 32registers or are specified as literals in the instruction itself The result.

Operands in Data Processing    Simple Register Operands Immediate Operands Shifted Register Operands .

Data Processing Operations     Arithmetic Operations BitBit-wise Operations Register Movement Operations Comparison Operations .

r1. r1. r2 r0 := r1 + r2 r0 := r1 + r2 + C r0 := r1 .Arithmetic Operations ADD r0. r2 ADC r0. r1.r2 + C . r1. r2 SUB r0.1 r0 := r2 ² r1 r0 := r2 ² r1 + C . r1.1 . r2 RSB r0. r1.r2 r0 := r1 . r2 RSC r0. r2 SBC r0.

r2 BIC r0. r1. r1. r2 r0 := r1 and r2 r0 := r1 or r2 r0 := r1 xor r2 r0 := r1 and (not) r2 .BitBit-wise Logical Operations AND r0. r2 ORR r0. r1. r2 EOR r0. r1.

r2 MVN r0.Register Movement Operations MOV r0. r2 r0 := r2 r0 := not r2 .

r2 set cc on r1 + r2 set cc on r1 and r2 set cc on r1 xor r2 . r2 CMN r1.Comparison Operations CMP r1. r2 TST r1. r2 set cc on r1 . r2 TEQ r1.

r3 := r3 + 1 AND r8.Immediate Operands  If we need to add constant   ADD r3. r8 := r7[7:0] Immediate Operands imm = (0->255) * 2^n (0<=n<=12) (0- . #1 . #&ff . r7. r3.

r2. r3 := r2 + (r1*8) . r1. LSL #3 .Shift Register Operands  Second register operand is subjected to shift before it is combined with first operand ADD r3.

Arithmetic Shift Right RORROR.Logical Shift Right ASLASL.ARM Shift Operations       LSLLSL.Logical Shift Left LSRLSR.Rotate Right RRXRRX.Rotate Right Extended .Arithmetic Shift Left ASRASR.

RRX 31 0 31 0 00000 00000 LSL #5 31 0 0 31 1 LSR #5 0 00000 0 1 1111 1 ASR #5 . ROR. positive operand 31 0 C ASR #5 . LSR.LSL. negative operand 31 0 C C ROR #5 RRX . ASL. ASR.

Shift Value in Register  It is also possible to use a register value to specify the number of bits the second operand should be shifted by: ADD r5. r5. r3. LSL r2 r5: r5 + r3 * 2^r2 .

Setting the Condition Codes     All DPI can affect the condition codes For all DPI except comparisons a special request needs to be made At assembly level the request is made by adding an S to opcode Eg: ADDS r0. r0. r3. r1 ADC r3. r2 .

r2 Some Rules    Immediate second operand not supported The result register must not be the same as the first source register If the S bit is set the V flag is preserved & the C flag is rendered meaningless .Multiplies   MUL r4. r3.

half-word.Data Transfer Instructions  Single Register Load & Store  transfer of a data item (byte. to copy blocks of data around memory allow exchange between a register and memory in one instruction used to implement semaphores to ensure mutual exclusion on accesses to shared data in multis  Multiple Register Load & Store    Single Register Swap Instructions   . to save/restore workspace registers. word) halfbetween ARM registers and memory enable transfer of large quantities of data used for procedure entry and exit.

RegisterRegister-Indirect Addressing LDR r0. [r1] r0 := mem32[r1] mem32[r1] := r0 r1 =baase register containing address of memory location . [r1] STR r0.

Pre Indexed Addressing LDR r0. [r1. #4] r0 := mem32[r1+4] .

#4 r0 := mem32[r1] r1 := r1 + 4 . [r1].Post Indexed Addressing LDR r0.

[r1. #4]! r0 := mem32[r1 + 4] r1 := r1 + 4 Where do I use this? .Auto Indexing Addressing LDR r0.

Exercise   Copy Data from Table1 to Table2 Algorithm:       Pointer to Table1 Pointer to Table2 Load [Table1] Store [Table2] Add 4 to Table1 Add 4 to Table2 .

#4 ADD r2. [r1] STR r0.. . r1 points to TABLE1 ... r2. r1. r2 points to TABLE2 . [r2] ADD r1.. TABLE2 LOOP: LDR r0. #4 . TABLE1 ADR r2. TABLE1: ...Answer COPY: ADR r1. TABLE2:.

.. TABLE1 ADR r2. [r1]. #4 STR r0.... r2 points to TABLE2 . TABLE2:.. TABLE2 LOOP: LDR r0.Better Answer COPY: ADR r1. r1 points to TABLE1 . #4 . . TABLE1: . [r2].

i.Multiple Register Transfer   When large quantity of data needs to be transferred But there is a trade off.e less addressing modes .

{r0.Example Multiple Transfer LDMIA r1. r5} r0:=mem32[r1] r2 := mem32[r1 + 4] r5 := mem32[r1 + 8] Base Address should be Word Aligned Order of Registers do not matter Normal practice to specify in increasing order Including r15 is also possible . r2.

correct the problem & then write the code!! .Exercise  Write a code to add two numbers a & b which are at memory locations 0x80000x80002000 & 0x8000-2001? Check the question 0x8000if some thing is wrong.

Exercise  Write a code to covert the following C Statements       X= X= X= X= X= X= A+B A B B A A + B*4 A + (B*5) A + (B*5) + (C*8) .

ARM Advanced RISC Machines The ARM Instruction Set .

ARM Instruction Set  LoadLoad-Store Architecture 3-Address Data Processing Instructions Conditional Execution of Instructions Powerful Load/Store Multiple Register General Shift Operation (Single Cycle) Extension of Instruction Set CoCoprocessor 1616-bit Compressed Instruction Set       .

Processor Modes  The ARM has six operating modes:       User (unprivileged mode under which most tasks run) (10000) FIQ (entered when a high priority (fast) interrupt is raised) (10001) IRQ (entered when a low priority (normal) interrupt is raised) (10010) Supervisor (entered on reset and when a Software Interrupt instruction is executed) (10011) Abort (used to handle memory access violations) (10111) Undef (used to handle undefined instructions) (11011) System (privileged mode using the same registers as user mode) (11111)  ARM Architecture Version 4 adds a seventh mode:  .

    1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers  However these are arranged into several banks.The Registers  ARM has 37 registers in total. with the accessible bank being governed by the processor mode. all of which are 3232bits long. Each mode can access     a particular set of r0-r12 registers r0a particular r13 (the stack pointer) and r14 (link register) r15 (the program counter) cpsr (the current program status register) a particular spsr (saved program status register) and privileged modes can also access  .

Register Organisation General registers and Program Counter User32 / System r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) FIQ32 r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) Supervisor32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_svc r14_svc r15 (pc) Abort32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_abt r14_abt r15 (pc) IRQ32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_irq r14_irq r15 (pc) Undefined32 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_undef r14_undef r15 (pc) Program Status Registers cpsr cpsr sprsr_fiq spsr_fiq cpsr spsr_svc cpsr spsr_abt cpsr sprsr_fiq spsr_irq cpsr spsr_undef sprsr_fiq .

.  All instructions can access r0-r14 directly.  Specific instructions to allow access to CPSR and SPSR.Accessing Registers using ARM Instructions  No breakdown of currently accessible registers. r0 Most instructions also allow use of the PC.

disables the IRQ. Z = Zero result from ALU flag. Processor in ARM state T = 1. Processor in Thumb state * * . disables the FIQ. F = 1. * Interrupt Disable bits. * Condition Code Flags N = Negative result from ALU flag. C = ALU operation Carried out V = ALU operation oVerflowed Mode Bits M[4:0] define the processor mode. I = 1.The Program Status Registers (CPSR and SPSRs) 31 28 8 4 0 N Z CV I F T Mode Copies of the ALU status flags (latched if the instruction has the "S" bit set). T Bit (Architecture v4T only) T = 0.

Condition Flags Logical Instruction Flag Negative been set (N=µ1¶) number in Zero zero (Z=µ1¶) Carry bits (C=µ1¶) oVerflow bits (V=µ1¶) corruption of No meaning Bit 31 of the result has Indicates a negative signed operations Result is all zeroes Result of operation was Arithmetic Instruction After Shift operation µ1¶ was left in carry flag No meaning Result was greater than 32 Result was greater than 31 Indicates a possible the sign bit in signed numbers .

  R14 is used as the subroutine link register (LR) and stores the return address when Branch with Link operations are performed.lr or  . Thus to return from a linked branch  MOV r15.The Program Counter (R15)  When the processor is executing in ARM state:    All instructions are 32 bits in length All instructions must be word aligned Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to zero (as instruction cannot be halfword or byte aligned). calculated from the PC.r14 MOV pc.

Register Example: User to FIQ Mode Registers in use Registers in use User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq FIQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) EXCEPTION r8 r9 r10 r11 r12 r13 (sp) r14 (lr) Return address calculated from User mode PC value and stored in FIQ mode LR spsr_fiq cpsr spsr_fiq User mode CPSR copied to FIQ mode SPSR Disable FIQ .

IRQ.Exceptions  Exceptions generated as the direct effect of executing an instruction  Software Interrupts. Undefined Instructions & Prefetch Aborts  Exceptions generated as a side effect of an Instruction  Data Aborts (Caused by Load/Store Instructions)  Exceptions generated externally. unrelated to Instruction flow  Reset. FIQ .

° Software Interrupt (SWI): This is a user-defined intentional synchronous interrupt instruction. ° IRQ: Occurs when the processor external Interrupt ReQuest pin is asserted ° FIQ: Occurs when the processor external Fast Interrupt reQuest pin is asserted Exception Sources in ARM . does not recognize the currently executing instruction. ° Prefetch Abort: Occurs when the processor attempts to execute an instruction that was not fetched.° Reset: Occurs when the processor reset pin is asserted. ° Data Abort: Occurs when a data transfer instruction attempts to load or store data at an illegal address. because the address was illegal. (Signalling power-up) ° Undefined Instruction: Occurs if the processor.

Exception Entry      Changes Operating Mode Save Address of next Instruction in r14 of the new mode Saves Old value of CPSR into SPSR of new mode Disables either IRQ or FIQ if the exception is IRQ or FIQ respectively Forces PC to vector to new address .

two technics are used to carry out these steps simultaneously .Exception Return    Any modified user registers should be restored from the Stack The CPSR should be restored from appropriate SPSR The PC must be changed to relevant User Instruction Stream Problem: Last two cannot be carried out independently.

#8 The S modifier signifies special form of Instruction when the destination is PC  To return from IRQ. r14 SUBS pc. FIQ or Prefetch Abort   To return from Data Aborts  . r14. #4 SUBS pc.Solution 1  To return from SWI  MOVS pc. r14.

Data abort must return two instructions early to retry the data transfer instruction.Note how the return instruction incorporates an adjustment to the return address where necessary:  IRQ and FIQ must return one instruction early in order to execute the instruction that was 'usurped' for the exception entry. Prefetch abort must return one instruction early to execute the instruction that had caused a memory fault when first requested. which was the instruction before the one usurped for exception entry  .

which will always be the last item transferred from memory since the registers are loaded in increasing order. for example. . restore and return {r0The CPSR is restored at the same time that the PC is loaded from memory. though note that in this case the SPSR must be saved as well as the PC) the restoration of the user registers and the return may be implemented with a single multiple register transfer instruction such as: LDMFD r13!.SOLUTION2    If the handler has copied the return address out onto a stack (in order.pc}" . to allow re-entrant rebehaviour. {r0-r3.

EXCEPTION PRIORITIES       Reset Data Abort FIQ IRQ Prefetch Abort SWI. Undefined Instruction .

then  ARM state is entered. the core:  Copies CPSR into SPSR_<mode>  Sets appropriate CPSR bits  0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C Reset Undefined Instruction Software Interrupt Prefetch Abort Data Abort Reserved IRQ FIQ If core implements ARM Architecture 4T and is currently in Thumb state.Exception Handling and the Vector Table  When an exception occurs.   Maps in appropriate banked registers  Stores the return address in LR_<mode>  Sets PC to vector address To return.   Mode field bits Interrupt disable flags if appropriate. exception handler needs to:   Restore CPSR from SPSR_<mode> Restore PC from LR_<mode> .

What happens on Exception Entry & Exception Exit? . or modes has the fewest available number of registers available? How many and why? Name the exceptions in the ARM? Mention their priorities.Verbal       What register is used to store the program counter ? What is r13 often used to store? Which mode.Quiz .

ARM Instruction Set Format 31 2827 1615 87 0 Instruction type Data processing / PSR Transfer Multiply Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond 0 0 I Opcode S Rn Rd RdHi Rn Rn Rn Rn Rn Rd Rn RdLo Rd Rd Rs Rs Operand2 1 0 0 1 1 0 0 1 Rm Rm Rm 0 0 0 0 0 0 A S 0 0 0 0 1 U A S 0 0 0 1 0 B 0 0 0 1 I P U B W L 1 0 0 P U S W L 0 0 0 P U 1 W L 0 0 0 P U 0 W L Long Multiply Swap (v3M / v4 only) 0 0 0 0 1 0 0 1 Offset Register List Load/Store Byte/Word Load/Store Multiple Halfword transfer : Immediate offset Halfword transfer: Register offset (v4 only) Branch Rd Rd Offset1 1 S H 1 Offset2 0 0 0 0 1 S H 1 Rm 1 0 1 L 0 0 0 1 Offset 0 0 1 0 1 1 1 1 1 1 1 1 Rn CRn L CRn CRd CRd Rd 1 1 1 1 0 0 0 1 CPNum CPNum CPNum Op2 Op2 Offset 0 1 CRm CRm Rn Branch Exchange (v4T only) 1 1 0 P U N W L 1 1 1 0 1 1 1 0 1 1 1 1 Op1 Op1 Coprocessor data transfer Coprocessor data operation Coprocessor register transfer SWI Number Software interrupt .

However by reusing the condition evaluation hardware. NonNon-executed instructions soak up 1 cycle. which stall the pipeline (3 cycles to refill).   All instructions contain a condition field which determines whether the CPU will execute them.Conditional Execution   Most instruction sets only allow branches to be executed conditionally.  This removes the need for many branches. ARM effectively increases number of instructions. .  Still have to complete cycle so as to allow fetching and decoding of following instructions.

always 1111 = NV . or =) 1110 = AL .or N clear and V set (<. .C set and Z clear (unsigned higher) 1001 = LS . or N set and V clear. or N clear and V set (>) 1101 = LE . and either N set and V set.N clear (positive or zero) 0110 = VS .C clear (unsigned lower) 0100 = MI -N set (negative) 0101 = PL .C set (unsigned higher or same) 0011 = LO / CC . or N clear and V clear (>or =) 1011 = LT .N set and V clear.reserved.The Condition Field 31 28 24 20 16 12 8 4 0 Cond 0000 = EQ .Z clear (not equal) 0010 = HS / CS .C clear or Z (set unsigned lower or same) 1010 = GE .V set (overflow) 0111 = VC .Z set (equal) 0001 = NE . or N clear and V set (>) 1100 = GT .V clear (no overflow) 1000 = HI .Z set.Z clear.N set and V set.

and set flags . r0 = r1 + r2 By default..r1..r2 . If zero flag set then« . To cause the condition flags to be updated.Using and updating the Condition Field   To execute an instruction conditionally.r2 .r1.. data processing operations do not affect the condition flags (apart from the comparisons where this is the only effect).  For example to add two numbers and set the condition flags:  ADDS r0. .r2 . .r1.. r0 = r1 + r2 (ADDAL)  To execute this only if the zero flag is set:  ADDEQ r0. the S bit of the instruction needs to be set by postfixing the instruction (and any condition code) with an S . r0 = r1 + r2 . simply postfix it with the appropriate condition:  For example an add instruction takes the form:  ADD r0.

.  This gives a range of ± 32 Mbytes.Branch instructions (1)   Branch : B{<cond>} label Branch with Link : BL{<cond>} sub_routine_label 31 28 27 25 24 23 0 Cond 1 0 1 L Offset Link bit 0 = Branch 1 = Branch with link Condition field  The offset for branch instructions is calculated by the assembler:  By taking the difference between the branch instruction and the target address minus 8 (to allow for the pipeline).  This gives a 26 bit offset which is right shifted 2 bits (as the bottom two bits are always zero as instructions are word aligned) and stored into the instruction encoding.

pipeline has to refill before execution continues.Branch instructions (2)       When executing the instruction. BX  See Thumb Instruction Set Module for details. simply need to restore the PC from the LR:  MOV pc. lr  Again. The "Branch" instruction does not affect LR. once the pipeline has been refilled. To return from subroutine. The "Branch with link" instruction implements a subroutine call by writing PCPC-4 into the LR of the current bank. .e. the processor:  shifts the offset left two bits. Note: Architecture 4T offers a further ARM branch instruction. the address of the next instruction following the branch with link (allowing for the pipeline). sign extends it to 32 bits. and adds it to PC. Execution then continues from the new PC.  i.

They each perform a specific operation on one or two operands.Data processing Instructions      Largest family of ARM instructions.Rn  Second operand sent to the ALU via barrel shifter. all sharing the same instruction format.just set condition codes)  Logical operations  Data movement between registers Remember.  First operand always a register . NOT memory. Contains:  Arithmetic operations  Comparisons (no results . We will examine the barrel shifter shortly. this is a load / store architecture  These instruction only work on registers. .


#1  RSBLES r4. r2  SUBGT r3. Rn.Arithmetic Operations  Operations are:  ADD  ADC  SUB  SBC  RSB  RSC operand1 operand1 operand1 operand1 operand2 operand2 + operand2 + operand2 + carry .operand1 + carry .operand2 + carry -1 .operand1 . Operand2  Examples ADD r0.operand2 . #5  .1  Syntax:  <Operation>{<cond>}{S} Rd. r1. r3. r5.

but result not written  TEQ operand1 EOR operand2.Comparisons     The only effect of the comparisons is to  UPDATE THE CONDITION FLAGS. but result not written  CMN operand1 + operand2. but result not written Syntax:  <Operation>{<cond>} Rn. Operations are:  CMP operand1 . #5 . but result not written  TST operand1 AND operand2.operand2. FLAGS. Operand2 Examples:  CMP r0. Thus no need to set S bit. r1  TSTEQ r2.

Logical Operations  Operations are:     AND EOR ORR BIC operand1 operand1 operand1 operand1 AND operand2 EOR operand2 OR operand2 AND NOT operand2 [ie bit clear]  Syntax:  <Operation>{<cond>}{S} Rd.r0  Examples:   . r1. Rn. r2 r1.r3. Operand2 AND EORS r0.

Syntax:  <Operation>{<cond>}{S} Rd. r1 MOVS r2.#0  Examples:    .Data Movement  Operations are:   MOV MVN operand2 NOT operand2  Note that these make no use of operand1. #10 MVNEQ r1. Operand2 MOV r0.

So what operations does the barrel shifter support?   .The Barrel Shifter  The ARM doesn t have actual shift instructions. Instead it has a barrel shifter which provides a mechanism to carry out shifts as part of other instructions.

g.Barrel Shifter .Left Shift  Shifts left by the specified amount (multiplies by powers of two) e. LSL #5 = multiply by 32 Logical Shift Left (LSL) CF Destination 0 .

. ASR #5 = divide by 32 Logical Shift Right .0 Destination CF Arithmetic Shift Right Destination Sign bit shifted in CF . for 2's complement operations.g.Right Shifts Logical Shift Right ‡ Shifts right by the specified amount (divides by powers of two) e.Barrel Shifter .g. LSR #5 = divide by 32 Arithmetic Shift Right ‡ Shifts right (divides by powers of two) and preserves the sign bit. e..

Rotations Rotate Right (ROR) Similar to an ASR but the bits wrap around as they leave the LSB and appear as the MSB. Rotate Right Destination CF Rotate Right through Carry Destination CF .g. e. Rotate Right Extended (RRX) This operation uses the CPSR C flag as a 33rd bit. ROR #5 Note the last bit rotated is also used as the Carry Out.Barrel Shifter . Encoded as ROR #0. Rotates right by 1 bit.

ALU * Immediate value ‡ 8 bit number ‡ Can be rotated right through an even number of positions. Result . Shift value can be either be:  5 bit unsigned integer  Specified in bottom byte of another register. ‡ Assembler will calculate rotate for you from constant. optionally with shift operation applied.Using the Barrel Shifter: The Second Operand Operand 1 Operand 2 Barrel Shifter   Register.

Second Operand : Shifted Register  The amount by which the register is to be shifted is contained in either:  the immediate 5-bit field in the instruction 5  NO OVERHEAD Shift is done for free .executes in single cycle.e.  Then same as on other processors where shift is separate instruction. If no shift is specified then a default shift is applied: LSL #0  i. barrel shifter has no effect on value in register.  the bottom byte of a register (not PC)   Then takes extra cycle to execute  ARM doesn t have enough read ports to read 3 registers at once. .

r2 = r2 * 7 . r3. r1.Second Operand : Using a Shifted Register     Using a multiplication instruction to multiply by a constant means first loading the constant into a register and then waiting a number of internal cycles for the instruction to complete. r2 = r3 * 15 RSB RSB r2. LSL #2 Example: r2 = r3 * 105 Example: r2 = r3 * 15 * 7 Example: r2 = r3 * (16 . LSL #4 . r3. LSL #3 .1) * (8 .1) RSB RSB r2. Example: r0 = r1 * 5 Example: r0 = r1 + (r1 * 4) ADD ADD r0. ADDs. r2. SUBs and RSBs with shifts. A more optimum solution can often be found by using some combination of MOVs. r1.  Multiplications by a constant equal to a ((power of 2) ± 1) can be done in one cycle. r2.

Second Operand : Immediate Value (1)     There is no single instruction which will load a 32 bit immediate constant into a register without performing a data load from memory.30). though some constants will still need to be loaded from memory. These 8 bits can then be rotated right through an even number of positions (ie RORs by 0. Instead it is used to store 8 bit constants.. The data processing instruction format has 12 bits available for operand2  If used directly this would only give a range of 4096. 2..  This gives a much larger range of constants that can be directly loaded.  All ARM instructions are 32 bits long  ARM instructions do not use the instruction stream as data. giving a range of 0 .255. 4. .

260. #0xFFFFFFFF .. => MOV r0. 0x40-0xff ror [0x10000x4026] These can be loaded using.1040. step 16. #4096 .0xff]  256. 26 ... => MOV r0..4080 [0x400-0xff0..16320 [0x1000-0x3fc0. step 64. 0x40-0xff ror 30] [0x1000x40 1024. step 4. #0x1000 (ie 4096) To make this easier.1056. the assembler will convert to this form for us if simply given the required constant:  MOV r0.264.. 0x40-0xff ror 28] [0x4000x40 4096. for example:  MOV r0. #0x1000 (ie 0x40 ror 26) The bitwise complements can also be formed using MVN:  MOV r0. #0 If the required constant cannot be generated.Second Operand : Immediate Value (2)      This gives us:  0 . an error will be reported. #0x40..1020 [0x100-0x3fc.4160... 4224. assembles to MVN r0.255 [0 . .

=numeric constant If the constant can be constructed using either a MOV or MVN then this will be the instruction actually generated. sometimes this mechansim will not generate the required constant. it is the recommended way of loading constants. generates MOV r0. Otherwise.Loading full 32 bit constants      Although the MOV/MVN mechansim will load a large range of constants into a register. the assembler will produce an LDR instruction with a PCPCrelative address to read the constant from a literal pool.=0x42 .=0x55555555 . Therefore.#0x42  LDR r0. generate LDR r0. the assembler also provides a method which will load ANY 32 bit constant:  LDR rd. .  LDR r0. offset to lit pool] As this mechanism will always generate the best instruction for a given case.[pc.

These will be picked up by the assembler if overlooked.  Cannot use PC. This works because multiplication is commutative. Rm. Multiply  MUL{<cond>}{S} Rd. Rd = (Rm * Rs) + Rn Restrictions on use:  Rd and Rm cannot be the same register  Can be avoid by swapping Rm and Rs around.does addition for free  MLA{<cond>}{S} Rd.Rn . Rd = Rm * Rs Multiply Accumulate . Rs. Rm. Operands can be considered signed or unsigned  Up to user to interpret correctly. Rs .Multiplication Instructions      The Basic ARM provides two multiplication instructions. .

RdHi.Rs  UMLAL{<cond>}{S} RdLo.MultiplyMultiply-Long and MultiplyMultiply-Accumulate Long     Instructions are  MULL which gives RdHi.RdLo:=Rm*Rs  MLAL which gives RdHi. non- . Rm. Rm.RdLo However the full 64 bit of the result now matter (lower precision multiply instructions simply throws top 32bits away)  Need to specify whether operands are signed or unsigned Therefore syntax of new instructions are:  UMULL{<cond>}{S} RdLo.RdLo:=(Rm*Rs)+RdHi. RdHi.Rm.RdHi.Rm.Rs  SMULL{<cond>}{S} RdLo. Warning : Unpredictable on non-M ARMs. Rs  SMLAL{<cond>}{S} RdLo. Rs Not generated by the compiler.RdHi.

LSL #2 b) RSB r2. r1. r1. LSL #4 ADD r0. What does the following instruction sequence do? ADD r0. Specify instructions which will implement the following: a) r0 = 16 b) r1 = r0 * 4 c) r0 = r1 / 16 ( r1 signed 2's comp. #0 3. LSL #1 SUB r0.Example 1. r1. What will the following instructions do? a) ADDS r0. r1.) d) r1 = r2 * 7 2. r0. r0. r1. r1. LSL #7 . r1.

 Block data transfer (LDM/STM).  Store results from registers out to memory.  Must move data values into registers before using them. .Load / Store Instructions    The ARM is a Load / Store Architecture:  Does not support memory to memory data processing operations.  Single Data Swap (SWP). The ARM has three sets of instructions which interact with main memory. This might sound inefficient. but in practice isn t:  Load data values from memory into registers. These are:  Single register data transfer (LDR / STR).  Process data in registers using a number of data processing instructions which are not slowed down by memory access.

Single register data transfer    

The basic load and store instructions are:  Load and Store Word or Byte  LDR / STR / LDRB / STRB ARM Architecture Version 4 also adds support for halfwords and signed data.  Load and Store Halfword  LDRH / STRH  Load Signed Byte or Halfword - load value and sign extend it to 32 bits.  LDRSB / LDRSH All of these instructions can be conditionally executed by inserting the appropriate condition code after STR / LDR.  e.g. LDREQB Syntax:  <LDR|STR>{<cond>}{<size>} Rd, <address>

Load and Store Word or Byte: Base Register 

The memory location to be accessed is held in a base register  STR r0, [r1] ; Store contents of r0 to location pointed to ; by contents of r1.  LDR r2, [r1] ; Load r2 with contents of memory location ; pointed to by contents of r1.
r0 Source Register for STR 0x5 Memory

r1 Base Register 0x200

r2 0x5 0x5

Destination Register for LDR

Load and Store Word or Byte: Offsets from the Base Register 

As well as accessing the actual location contained in the base register, these instructions can access a location offset from the base register pointer. This offset can be  An unsigned 12bit immediate value (ie 0 - 4095 bytes).  A register, optionally shifted by an immediate value This can be either added or subtracted from the base register:  Prefix the offset value or register with + (default) or - . This offset can be applied:  before the transfer is made: Pre-indexed addressing Pre optionally auto-incrementing the base register, by postfixing the autoinstruction with an ! .  after the transfer is made: Post-indexed addressing Post causing the base register to be auto-incremented. auto-incremented.

Load and Store Word or Byte: PrePre-indexed Addressing 

Example: STR r0, [r1,#12]
Offset 12 r1


r0 0x5

Source Register for STR


Base Register




To store to location 0x1f4 instead use: STR r0, [r1,#-12] [r1,#To auto-increment base pointer to 0x20c use: STR r0, [r1, #12]! autoIf r2 contains 3, access 0x20c by multiplying this by 4:  STR r0, [r1, r2, LSL #2]

r2. LSL #2 . #-12 #If r2 contains 3. auto-incremenet base register to 0x20c by automultiplying this by 4:  STR r0. [r1]. #12 r1 0x20c Offset 12 0x20c Memory r0 0x5 Updated Base Register Source Register for STR Original Base Register  r1 0x200 0x200 0x5  To auto-increment the base register to location 0x1f4 instead use: auto STR r0.Load and Store Word or Byte: PostPost-indexed Addressing  Example: STR r0. [r1]. [r1].

 LDR r2. the first element of which is pointed to by the contents of r0. r1. for instance 0 r0 to produce sum of elements in the array. [r1]. element Offset then we can use pre-indexed addressing: pre r1 is element we want. Memory If we want to access a particular element.Example Usage of Addressing Modes   Imagine an array. #4 Use a further register to store the address of final element. LSL #2] 12 3 If we want to step through every 1 element of the array. then we can use post-indexed addressing within a loop: post r1 is address of current element (initially equal to r0). so that the loop can be correctly terminated. Pointer to start of array 2 8 4 0  .  LDR r2. [r0.

Offsets for Halfword and Signed Halfword / Byte Access   The Load and Store Halfword and Load Signed Byte or Halfword instructions can make use of prepre. . However the actual offset formats are more constrained:   The immediate value is limited to 8 bits (rather than 12 bits) giving an offset of 0-255 bytes. 0The register form cannot have a shift applied to it.and post-indexed addressing in much the postsame way as the basic load and store instructions.

 Which byte / halfword is accessed will depend on the endianess of the system involved. Least significant byte of a word is stored in bits 2424-31 of an addressed word.Effect of endianess   The ARM can be set up to access its data in either little or big endian format. .  Big endian:   This has no real relevance unless data is stored as words and then accessed in smaller sized quantities (halfwords or bytes). Little endian:  Least significant byte of a word is stored in bits 0-7 of an addressed word.

[r1] 44 33 22 11 r1 = 0x100 Little-endian 31 24 23 16 15 87 0 Big-endian 31 24 23 16 15 87 0 00 00 00 44 00 00 00 11 r2 = 0x44 r2 = 0x11 . [r1] 31 24 23 16 15 87 0 31 24 23 16 15 87 0 r1 = 0x100 11 22 33 44 Memory LDRB r2.Endianess Example r0 = 0x11223344 31 24 23 16 15 87 0 11 22 33 44 STR r0.

you should assume that:  r0 points to the start of the array. Elements  r1 = x  r2 = n n elements { x + (n . The segment should use post-indexed addressing. where the element x=0 is the first element of the array.1) x+1 x r0 0 . Each element of the array is word sized (ie. 32 bits).Example     Write a segment of code that add together elements x to x+(n-1) of x+(nan array. postAt the start of your segments.

repeat for . #4 next ADD r1. LSL#2 n+1 MOV r1. [r0]. Have we reached element x+n? . Add contents to counter .Sample Solution ADD r0. r1. r1. r0. r0. Set r2 to address of element . on exit sum contained in r1 . Initialise counter . #0 loop LDR r3. r2. If not . Access element and move to . r2 BLT loop . Set r0 to address of element x . next element . r3 CMP r0. LSL#2 ADD r2.

back bit 0 = no write-back 1 = write address into base At least one register must be transferred as the list cannot be empty. For example: ‡ Bit 0 set causes r0 to be transferred. add offset to base Base register Load/Store bit 0 = Store to memory 1 = Load from memory Each bit corresponds to a particular register. 31 28 27 24 23 22 21 20 19 16 15 0 Cond 1 0 0 P U S W L Rn Register list Condition field Up/Down bit 0 = Down. Pre/Post indexing bit 0 = Post. add offset after transfer.Block Data Transfer (1)   The Load and Store Multiple instructions (LDM / STM) allow betweeen 1 and 16 registers to be transferred to or from memory. ‡ Bit 0 unset causes r0 not to be transferred. PSR and force user bit 0 = don¶t load PSR or force user mode 1 = load PSR or force user mode .  Any subset of the user mode bank of registers when in a priviledged mode (postfix instruction with a ^ ). 1 = Pre . subtract offset from base 1 = Up . The transferred registers can be either:  Any subset of the current bank of registers (default). add offset before transfer Write.

 These instructions are very efficient for  Saving and restoring context  For this useful to view memory as a stack.Block Data Transfer (2)  Base register used to determine where memory access should occur. Base register can be optionally updated following the transfer (by appending it with an ! .    4 different addressing modes allow increment and decrement inclusive or exclusive of the base register location. Lowest register number is always transferred to/from lowest memory location accessed.  Moving large blocks of data around memory  For this useful to directly represent functionality of the instructions. .

and shrinks as data is popped off the top.3} SP 3 2 SP BASE 2 1 1 BASE POP Result of pop = 3 SP BASE .Stacks   A stack is an area of memory which grows as new data is pushed onto the top of it.2.  A stack pointer  used to point the current top of the stack. PUSH {1. Two pointers define the current limits of the stack.  A base pointer  used to point to the bottom of the stack (the first location).

 STMED / LDMED : Empty Descending stack  STMEA / LDMEA : Empty Ascending stack Note: ARM Compiler will always use a Full descending stack. . where the stack structure grows up through memory. The ARM also supports ascending stacks. with the last pushed value at the lowest address.Stack Operation     Traditionally. a stack grows down in memory. The value of the stack pointer can either:  Point to the last occupied address (Full stack)  and so needs pre-decrementing (ie before the push) pre Point to the next occupied address (Empty stack)  and so needs post-decrementing (ie after the push) postThe stack type to be used is given by the postfix to the instruction:  STMFD / LDMFD : Full Descending stack  STMFA / LDMFA : Full Ascending stack.

{r0.r3-r5} STMED sp!.r1.r3-r5} 0x418 SP r5 r4 r3 r1 r0 SP r5 r4 r3 r1 r0 Old SP Old SP SP r5 r4 r3 r1 r0 r5 r4 r3 r1 r0 Old SP Old SP 0x400 SP 0x3e8 .r1. {r0.r1.Stack Examples STMFD sp!. {r0. {r0.r1.r3-r5} STMFA sp!.r3-r5} STMEA sp!.

{r0-r12.{r0. and the return address ..{r0. and return automatically . Any registers that are needed can be pushed onto the stack at the start of the subroutine and popped off again at the end so as to restore them before return to the caller : STMFD sp!... lr} sp!....Stacks and Subroutines  One use of stacks is to create temporary register workspace for subroutines.. stack all registers . . LDMFD sp!....{r0-r12.. load all the registers .... pc} sp!.

it is clearer to specify exactly what functionality of the instruction is:  i.e. specify whether to increment / decrement the base pointer.Direct functionality of Block Data Transfer  When LDM / STM are not being used to implement stacks. LDM / STM support a further syntax in addition to the stack one:     STMIA / LDMIA : Increment After STMIB / LDMIB : Increment Before STMDA / LDMDA : Decrement After STMDB / LDMDB : Decrement Before . before or after the memory access.  In order to do this.

{r0-r11} {r0. check for the end BNE loop . r14 points to the end of the source data .Example: Block Copy  Copy a block of memory. load 48 bytes STMIA r13!. and loop until done   r13 r14 Inc M This loop transfers 48 bytes in 31 cycles Over 50 Mbytes/sec at 33 MHz r12 . {r0-r11} {r0. r13 points to the start of the destination data loop LDMIA r12!. r12 points to the start of the source data . . and store them CMP r12. which is an exact multiple of 12 words long from the location pointed to by r12 to the location pointed to by r13. r14 points to the end of block to be copied. r14 .

Quiz  The contents of registers r0 to r6 need to be swapped around thus:        r0 r1 r2 r3 r4 r5 r6 moved moved moved moved moved moved moved into into into into into into into r3 r4 r6 r5 r0 r1 r2  Write a segment of code that uses full descending stack operations to carry this out. and hence requires no use of any other registers for temporary storage. .

r4.r6} LDMFD sp!.Quiz . {r0-r6} Old SP LDMFD sp!. {r0-r2} S P r6 r5 r4 r3 r2 r1 r0 S P r6 r5 r4 r3 S P r6 r5 r4 r3 = r0 r4 = r1 r6 = r2 r5 = r3 r0 = r4 r1 = r5 r2 = r6 . {r3. {r5} SP LDMFD sp!.Sample Solution STMFD sp!.

[Rn] 1 temp 2 Memory Rm Rd 3 Rn   Thus to implement an actual swap of contents make Rd = Rm. . The compiler cannot produce this instruction. Syntax:  SWP{<cond>}{B} Rd. Atomic operation of a memory read followed by a memory write which moves byte or word Rm.Swap and Swap Byte Instructions   quantities between registers and memory.

Software Interrupt (SWI) 31 28 27 24 23 0 Cond 1 1 1 1 Comment field (ignored by Processor) Condition Field      In effect. plus the associated state saving). a SWI is a user-defined instruction. See Exception Handling Module for further details. The handler can then examine the comment field of the instruction to decide what operation has been requested. By making use of the SWI mechansim. . an operating system can implement a set of privileged operations which applications running in user mode can request. userIt causes an exception trap to the SWI hardware vector (thus causing a change to supervisor mode. thus causing the SWI exception handler to be called.

Every instruction can be conditionally executed.  32 bit and 8 bit data types  and also 16 bit data types on ARM Architecture v4.  Flexible multiple register load and store instructions  Instruction set extension via coprocessors . A load/store architecture  Data processing instructions act only on registers   Three operand format Combined ALU and shifter for high speed bit manipulation  Specific memory access instructions with powerful autoauto-indexing addressing modes. Most instructions execute in a single cycle.Main features of the ARM Instruction Set     All instructions are 32 bits long.

Operating States  Supports 2 instruction sets  ARM Thumb 32 bit instruction set 16 bit instruction set  .

ARM State   

Able to access more large memories efficiently 32 bit integer arithmetic in a single cycle More number of instructions Better performance

Thumb Mode: What is Thumb? 

Thumb ISA: 16-bit instruction, dynamically 16decompressed into ARM Instruction before execution Fewer directly accessible GPRs (Only R0-R8) R0The CPU can be switched between ARM ISA mode and Thumb ISA mode dynamically

Switching State 

ARM to Thumb 

Execute the BX instruction with state bit=1 

Thumb to ARM
Execute the BX instruction with state bit=0  An interrupt or exception occurs 

Which state to use 

Low memory system : use thumb 16 bit memory : use thumb Performance is critical : use ARM 

Example : in execution of interrupt routines 

Performance is critical AND Memory is low : use both ARM and thumb example : in interrupt routines

Thumb Decode Stage .

ARM Thumb T (Thumb)-extension shrinks the ARM instruction set to 16-bit word length > 35-40% saving in amount of memory compared to 32-bit instruction set ‡ Extension enables simpler and significantly cheaper realization of processor system. Instructions take only half of memory than with 32-bit instruction set without significant decrease in performance or increase in code size. ‡ Extension is made to instruction decoder at the processor pipeline ‡ Registers are preserved as 32-bit but only half of them are available .

Thumb-instruction decoder is placed in pipeline ‡ Change to Thumb-mode happens by turning the state of multiplexers feeding the instruction decoders and data bus ‡ A1 selects the 16-bit half word from the 32-bit bus ‡ Example ADD Rd.# 8 bit connstsnt .

Thumb State Registers .


This instruction sets the T bit if the bottom bit of the specified register was set. The normal way they switch to execute Thumb instructions is by executing a Branch and Exchange instruction BX . Other instructions which change from ARM to Thumb code include exception returns. . either using a special form of data processing instruction or a special form of load multiple register instruction. and switches the program counter to the address given in the remainder of the register. after reset.THUMB ENTRY    ARM cores start up. executing ARM instructions.

THUMB EXIT An explicit switch back to an ARM instruction stream can be caused by executing a Thumb BX instruction  An implicit return to an ARM instruction stream takes place whenever an exception is taken.  . since exception entry is always handled in ARM code.

THUMB SYSTEMS    All Thumb systems include some ARM code. . A typical embedded system will include a small amount of fast 32-bit memory on the same chip as the ARM core and will execute speed-critical routines (such as digital signal processing algorithms) in ARM code from this memory. Most of the Thumb applications will make more than this minimal use of ARM code. if only to handle initialization and exception entry. The bulk of the code will not be speed critical and may execute from a 16-bit off-chip ROM.

data transfer and control flow instructions. . Support for 8-bit byte. They map onto ARM instructions so they inherit many properties of the ARM instruction set The load-store architecture with data processing. 16-bit half-word and 32-bit word data types where half-words are aligned on 2-byte boundaries and words are aligned on 4-byte boundaries.Thumb-ARM Similarities     All Thumb instructions are 16 bits long.

Thumb ± Arm Differences     

To achieve a 16-bit instruction length a number of characteristic features of the ARM instruction set have been abandoned: Most Thumb instructions are executed unconditionally. (All ARM instructions are executed conditionally.) Many Thumb data processing instructions use a 2address format (the destination register is the same as one of the source registers). (ARM data processing instructions, with the exception of the 64-bit multiplies, use a 3-address format.) Thumb instruction formats are less regular than ARM instruction formats, as a result of the dense encoding.

Thumb Exceptions  

All exceptions cause the processor to switch into ARM state and are handled within the ARM programmer's model. Since the T bit resides in the CPSR, it is saved on exception entry in the appropriate SPSR, and the same return from exception instruction will restore the state of the processor and leave it executing ARM orThumb instructions according to the state when the exception arose.

The Instruction Pipeline 

The ARM uses a pipeline in order to increase the speed of the flow of instructions to the processor.  Allows several operations to be undertaken simultaneously, rather than serially.
ARM PC FETCH Instruction fetched from memory

PC - 4


Decoding of registers used in instruction

PC - 8


Register(s) read from Register Bank Shift and ALU operation Write register(s) back to Register Bank 

Rather than pointing to the instruction being executed, the PC points to the instruction being fetched.

.Thumb branch instructions  control flow instructions include the various forms of PC-relative branch and branch-and-link instruction and the branch-and-exchange instruction for switching between the ARM and Thumb instruction sets.

Thumb Branch Instruction Binary Coding .

3. 2.     Typical uses of branch instructions include: 1. medium-range unconditional branches to 'goto' sections of code. long-range subroutine calls. ARM handles all these with the same instructions but 24-bit offset in the first two cases . short conditional branches to control (for example) loop exit.

to give a combined 22-bit half-word offset (which is sign-extended to 32 bits). both with this format.  Third Format-The branch and link subroutine mechanism often needs to have a long range. (H=l) PC := LR + (offset shifted left 1 place).In the first two formats . offset is shifted left one bit (to give half-word alignment) and sign-extended to 32 bits. (H=0) LR := PC + (sign-extended offset shifted left 12 places). 1. 2. which is difficult within a 16-bit instruction format. LR := oldPC + 3. the return address has two bytes added to point to the next instruction and the bottom bit set to indicate that the caller is a Thumb routine.  Here oldPC' is the address of the second instruction.  . Therefore Thumb uses two instructions.

format 3 .is available only in architecture v5T. 3aAssembler Format of Branch Instrns B<cond> <label> . format 3a . format 2 .ARM or Thumb targ . format 1 .  Format 3a.Thumb target BL <label> .Thumb target BLX <label> .Thumb target B <label> . format 4 .ARM target B{L}X Rm .

Thumb data processing instructions .

Description of Data processing Instn .

Rm ADDS Rd. Rn. #<#imm8> . Rm #imm3. Rn.#imm8 . MVN Rd. TST Rn. Rm . Rn.P.I. #<#imm8> . Rn. #<#imm8> .Arm D. ADD Rd.3 & 8 bit immediate field #sh . CMN Rn. ADD Rd. #<#imm3> ADDS Rd. Rm CMN Rn. #<#imm8> CMP Rn. MOV Rd. Rd. #<#imm3> . ADD Rd. Rm . Rm .Examples of Eq.5 bit shift amount . Rm . #<#imm8> MVNS Rd. CMP Rn. Rm CMP Rn. Rm .             ARM instruction Thumb instruction MOVS Rd. CMP Rn. #<#imm8> ADDS Rd. Rm TST Rn.

Thumb single register data transfer instructions .


. LDR/LDRH/LDRSH/LDRB/LDRSB/STR/STRH/STRB LDR Rd. Rm] . #<#off5>] . range of the 5-bit offset is 32 bytes in a load or store byte instruction. #<#off8> <op> Rd. 64 bytes in a load or store half-word instruction and 128 bytes in a load or store word instruction     <Op> Rd. #<#off8>] . [Rn. = LDRILDRB|STRISTRB <Op> Rd. [PC. = LDRHISTRH <op> Rd. = . [SP.Description & Assembler Format   In all cases the offset is scaled to the size of the data type. #<#off5>] . [Rn. [Rn.= LDR/STR   .

Thumb multiple register data transfer instructions  Thumb multiple register transfer instructions are useful both for procedure entry and return and for memory block copy .

      Assembler format <reg list> is a list of registers and register ranges from r0 to r7. {<reg list>) STMIA Rn!. lr}} . pc}} PUSH {<reg list>{. {<reg list>} POP {<reg list>{. LDMIA Rn!.

pc}} Push: STMFD SP!.Equivalent ARM Instruction    The equivalent ARM instructions have the same assembler format in the first two cases. and replace POP and PUSH with the appropriate addressing mode in the second two cases. lr}} . Block copy: LDMIA Rn!. {<reg list>{. {<reg list>{. {<reg list>} STMIA Rn!. {<reg list>} Pop: LDMFD SP!.

Thumb implementation .

Thumb properties      The Thumb code requires 70% of the space of the ARM code. Thumb code uses 30% less external memory power than ARM code. With 16-bit memory. With 32-bit memory. the Thumb code is 45% faster than the ARM code. . the ARM code is 40% faster than the Thumb code. The Thumb code uses 40% more instructions than the ARM code.

A low-end 16-bit system may have a small amount of on-chip 32-bit RAM for critical routines running ARM code. . but use offchip Thumb code for all non-critical routines.Thumb applications   A high-end 32-bit ARM system may use Thumb code for certain non-critical routines to save power or memory requirements.

and so on. saving cost and improving battery life. battery management system.but these are tightly coded routines that can fit in a small amount of on-chip memory. The more complex and much larger code that controls the user interface. Mobile telephone and pager applications incorporate real-time digital signal processing (DSP) functions that may require the full power of the ARM.or 16-bit bus. and the use of Thumb code will enable off-chip ROMs to give good performance on an 8. . is less time-critical.

ARM architecture  Architecture version  Version 1 (obsolete)      Basic data processing Byte. word and multi-word load/store multiSoftware interrupt 26 bit address bus No Multiply & Coprocessor Support Multiply Coprocessor support 26 bit address bus First ARM with on-chip Cache (Coprocessor CP15) onSWAP Instruction Introduced  Version 2 (obsolete)      .

ARM architecture  Architecture version (cont¶d) (cont¶  Version 3   32 bit address bus Separate CPSR. SPSR  Add MRS. MSR. Modify exception handler    Add µAbort Mode¶ and µUndef Mode¶ Mode¶ Mode¶ Was Backward Compatible with 26-bit 26MUL & MLA Half word transfer Introduce THUMB processor state Add µPrivileged mode¶ for operating system mode¶ 2 word distance of PC from current instruction   Version 4     µPC+8¶ behavior (at ARM state) PC+8¶  First fully formalized architecture .

ARM architecture  Architecture version (cont¶d) (cont¶  Version 5 Improve ARM/THUMB inter-working inter Add CLZ instruction for efficient integer divide  Add software breakpoint  Add more coprocessor support  More tight definition of arithmetic flags  .

ARM architecture  Architecture Variants  THUMB ( symbol as a µT¶)  THUMB instruction set: 16 bit re-encoded subset of 32 rebit ARM instruction set  Small code size ( up to 40 % compression)  Simplified design .

ARM Roadmap .

On-chip breakpoint On- .ARM architecture  Architecture Variants (cont¶d) (cont¶  Long Multiply Instruction (µM¶ variant) (µ  32x32 = 64 bit. Provide full 64 bit result Carefully chosen addition to native ARM instruction for DSP application Saturation 64 bit transfer First introduced in v5  Enhanced DSP instructions (µE¶ variant) (µ      Variants in Processor core   D: On-chip debug. Halt in response OnI: Embedded ICE.

bus AB One write port from ALU.Processor Cores  ARM7  Two main blocks: datapath and decoder  Register bank (r0 to r15)  Two read ports to A.bus ALU Additional read/ write ports for program counter r15  Barrel shifter / ALU  Address registers/ incrementer  Single Memory Port  holds either PC address (with increment) or operand address A[31:0] address register P C control incrementer PC register bank instruction decode A L U b u s A b u s multiply register B b u s & control barrel shifter ALU data out register D[31:0] data in register .bus/ B.

shifting.register read. owns´ ALU results generated and write.back writefetch decode execute 1 PC 2 PC+4 fetch R15 decode execute PC+4 3 instruction PC+8 fetch decode execute time .Processor Cores  ARM7 (cont¶d) (cont¶  Pipeline: 3 Stage pipeline    Fetch : fetch instruction code from memory into the instruction pipeline Decode : instruction decoded to obtain control signals for the datapath ready for the next stage Execute : instruction ³owns´ the datapath .

load/store Multi 1 fetch ADD decode execute 2 fetch STR decode calc.Processor Cores  ARM7(cont¶ ARM7(cont¶d)  MultiMulti-cycle operation Single cycle throughput for almost simple data processing instruction  Multi-cycle for mul. addr. data xfer 3 fetch ADD decode execute 4 fetch ADD decode execute ADD STR ADD ADD ADD execute 5 instruction fetch ADD decode time .


ARM Processor Cores ‡ The main ARM cores used today are: ARM7TDMI ± small. cheap ARM9TDMI ± moderate performance ARM10TDMI ± high performance .

long multiply Embedded ICE hardware 32 bit data bus Data size can be byte . or word Words : 4 byte aligned Half word : 2 byte aligned  Von neumann Architecture     .ARM 7TDMI   Version 4 Supports     Thumb : 16 bit compressed instruction set Debug : On chip debug support Enhanced Multiply : higher performance. half word.

Fetch Decode Execute Data/Buffer Write Back . 2. 3. 2. 3.ARM7TDMI Pipeline ARM7 1. Fetch Decode Execute ARM9 1. 4. 5.



thus still 32-bit 32-  In an typical application. performanceperformancesensitive code can be in ARM ISA.The Thumb Mode: Why Thumb?  Addresses higher code density by packing common instructions into 16-bit 16  Reduces bus width and activities Datapath remain unchanged. while other code in Thumb  Denser code. less performance impact .

ARM/THUMB Mode switch   Switch to ARM ISA mode automatically on exception Can also be switch by BX (Branch and Exchange) Instruction BX Instruction ARM ISA Mode Exception/Interrupt/ Software Interrupt THUMB ISA Mode  Note: gcc-3.X now have support for gcc³ARM/Thumb inter-working´ (Unsupported inter-working´ in 2.9x) .

Thumb/ARM differences  Most Thumb instructions are unconditional  ALL ARM instructions are conditional  Many Thumb data processing instructions use a 2-address format  ARM data processing instructions use a 3-address 3format  Thumb Instructions are less regular than ARM Instructions  For higher code density .

non-predicated ISA 16non- .Summary     Thumb: Try to make higher code density Thumb use a ³decompressor´ to decode decompressor´ 1616-bit Thumb instruction into 32-bit ARM 32instruction in the decode stage Adding Thumb support does not change original ARM datapath (except for the Thumb decompressor) Thumb: 16-bit.

3 0 1985 .The History of ARM MIPS 100 StrongARM ARM9.610 ARM2.90 1991 1992 1993 1994 1995 1996 1997 ARM7TDMI 40 .810 60 ARM7D.60.7DM ARM7.920 80 ARM8.710 20 ARM6.






Branch Instruction .

Data Processing Instruction .

Change processor mode and/or state. Initialize stacks and registers. Enable interrupts. . Initialize any critical I/O devices. if using MMU. Initialize the memory system. Initialize variables required by C and call the main application.Operations Done by Reset Handlers  For example        Set up exception vectors.

Undefined Instruction Handlers  It often used to emulate a coprocessor. Otherwise the emulator must pass the exception onto the original handler using the vector stored when the emulator was installed. . Examine the undefined instruction to see if it should be emulated. Such an emulator must:    Attach itself to the Undefined Instruction vector.

Prefetch Abort Handler or Data Abort   If no MMU. report error. the related handler is executed to deal with the virtual memory fault. Otherwise. Depending on whether the instruction that causes abort is re-executed or not.  Prefetch abort    INSTINST-aborted INSTINST-1 INSTINST-2 executed decoded fetched PCPC-8 PCPC-4 PC . the return readdress should be properly set.

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