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Lecture 15: MOS Transistor models: Body effects, SPICE models

Prof. J. S. Smith

Department of EECS

University of California, Berkeley

EECS 105 Spring 2004, Lecture 15

Prof. J. S. Smith

Context

In the last lecture, we discussed the modes of operation of a MOS FET:

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Voltage controlled resistor model I-V curve (Square-Law Model) Saturation model add a correction due to the changing depletion region, called the body effect Produce small signal models for the FET and look at how MOS Transistors are modeled in SPICE

University of California, Berkeley

**In this lecture, we will:
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Department of EECS

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Berkeley 2 . Lecture 15 Prof. and develop small signal models: Chapter 6 we will then take a week on bipolar junction transistor (BJT): Chapter 7 Then go on to design of transistor amplifiers: chapter 8 Department of EECS University of California. Then we look at the analog characteristics of simple digital devices. Smith Reading Today. we will cover PN diodes again in forward bias.4 And following the midterm. Berkeley EECS 105 Spring 2004. S. 5. Smith MOS operation An inversion mode MOS transistor operates by producing a sheet carriers just under the oxide The names source and drain are picked so that the inversion charge is larger at the source end Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel Department of EECS University of California. and Friday we will finish the material from chapter 4. J. J.EECS 105 Spring 2004. S.2→5. Lecture 15 Prof.

Lecture 15 Prof. Lecture 15 Prof. If this assumption is not true. This is in the text. etc. and QN(y) is the charge density of the electrons under the gate Department of EECS University of California. using the average charge and average velocity. due to the variation in the depletion width to the body (substrate). Smith Gradual channel approximation We have played pretty fast and loose. its called a short channel device. A more accurate model of the physics includes the fact that the charge density under the gate and the velocity vary along the channel length The current at each point along the length of the device must be independent of position in steady state (no buildup of charge) I D = −Wv y ( y )QN ( y ) Where ID is the drain current. section 4. y is the distance in the direction from the source to the drain. S. (perpendicular to the oxide). with the main difference from the simple approximation being the back gate effect. are significantly larger than the distances in the x direction. Smith Gradual channel approximation -2 For most FET’s the distances in y.EECS 105 Spring 2004. vy is the component of velocity in the source→drain direction. the Source→Drain direction. This means that the fields in the x direction are much stronger than the fields in the y direction.3. Berkeley 3 . J. J. Berkeley EECS 105 Spring 2004. S. Department of EECS University of California.

S. Berkeley EECS 105 Spring 2004. J.EECS 105 Spring 2004. Lecture 15 Prof. S.for PMOS ) γ= 2qN Aε S Cox Department of EECS University of California. Berkeley 4 . J. Lecture 15 Prof. Smith Effect of substrate voltage What is the effect of different substrate voltages? – – Depletion width W changes Need to account for different depletion region charge (VSB = 0): (VSB ≠ 0): QB 0 = − 2qN Aε S − 2φ P QB = − 2qN Aε S − 2φ P + VSB Department of EECS University of California. Smith Threshold voltage: general General form (with substrate bias): VT = VFB − 2φ P − QB 0 Qox − Cox Cox Substituting the capacitance as a function of voltage: VT = VT 0 + γ Where: ( − 2φ P + VSB − 2φ P + for NMOS .

or back gate effect.EECS 105 Spring 2004. Berkeley 5 . The threshold voltage will also vary along the gate. Department of EECS University of California. S. S. Smith Threshold voltage. This is called the body effect. summary If VSB = 0 (no substrate bias): VT 0 = VFB − 2φ F − QB Qox − Cox Cox If VSB ≠ 0 (non-zero substrate bias) VT = VT 0 + γ ( − 2φ P + VSB − 2φ P ) Body effect (substrate-bias) coefficient: 2qN Aε S γ= Cox (NMOS) Threshold voltage increases as VSB increases. Lecture 15 Prof. J. PMOS) NMOS (p-substrate) PMOS (n-substrate) Substrate Fermi potential Depletion charge density Substrate bias coefficient Substrate bias voltage Threshold voltage (enhancement devices) φp < 0 QB < 0 γ>0 VSB > 0 VT0 > 0 φn > 0 QB > 0 γ<0 VSB < 0 VT0 < 0 Department of EECS University of California. Berkeley EECS 105 Spring 2004. Lecture 15 Prof. Smith Threshold Voltage (NMOS vs. J.

Berkeley 6 . Body normally connected to ground for PMOS. S. J. Smith Body effect Voltage VSB changes the threshold voltage of transistor – – – For NMOS. J. S. body normally connected to Vcc Raising source voltage increases VT of transistor G B p+ S n+ D n+ B S p+ G D p+ L xj n+ L xj N well NMOS PMOS p-type substrate Department of EECS University of California. Smith Threshold voltage adjustment Threshold voltage can be changed by doping the channel region with donor or acceptor ions For NMOS: – – The threshold voltage is increased by adding acceptor ions The threshold voltage is decreased by adding donor ions The threshold voltage is increased by adding donor ions The threshold voltage is decreased by adding acceptor ions Density of implanted ions = NI [cm-2] For PMOS: – – Approximate change in threshold voltage: – ∆VT 0 = Department of EECS qN I Cox University of California.EECS 105 Spring 2004. Lecture 15 Prof. Berkeley EECS 105 Spring 2004. Lecture 15 Prof.

S. Berkeley EECS 105 Spring 2004. VDS > VGS − VTP L [ ] Saturation VGS ≥ VTN . Lecture 15 Prof. need to calculate VT Department of EECS University of California. VDS ≥ VGS − VTN W 2 ⇒ I D = 1 µCox (VGS − VT ) (1 + λVDS ) 2 VGS ≤ VTP . J. J. Smith Channel Length Modulation As VDS is increased. shortening the channel length The drain current increases due to shorter channel L' = L − ∆L I D = 1 µ nCox 2 W (VGS − VTN )2 (1 + λVDS ) L λ = channel length modulation coefficient Department of EECS University of California.EECS 105 Spring 2004. VDS ≤ VGS − VTP L Note: if VSB ≠ 0. VDS < VGS − VTN W 2 (VGS − VT )VDS − 1 VDS ⇒ I D = µCox 2 VGS ≤ VTP . Berkeley 7 . Smith Review VGS < VTN ⇒ ID = 0 VGS < VTP Cutoff Linear VGS ≥ VTN . the pinch-off point moves closer to source. S. Lecture 15 Prof.

Smith PMOS Slope due to Channel length modulation VDS = VGS − VT Department of EECS University of California. Lecture 15 Prof. S. Berkeley EECS 105 Spring 2004. J. S.EECS 105 Spring 2004. Berkeley 8 . Lecture 15 Prof. Smith NMOS i VDS = VGS − VT Slope due to Channel length modulation VGS Steps Department of EECS University of California. J.

Smith We now have reasonable mathematical models for NMOS and PMOS field effect transistors. S. The whole idea will be to make models that you can manipulate easily. Smith Small signal models: two terminals The current into a device depends on the history of voltages which have been applied to it I (t ) = F{V (τ < t )} Let’s say this can be written as a function of the voltage. Berkeley But that it is a nonlinear function Department of EECS 9 . Berkeley EECS 105 Spring 2004. allowing us to make equivalent circuits. and analyze and design circuits with FETs. J.EECS 105 Spring 2004. Lecture 15 Prof. J. We will now develop small signal models. We will also look at how SPICE models FETs for both small signal models and large signal models Department of EECS University of California. dV (t ) ⎞ ⎜ ⎟ ⎝ dt ⎠ University of California. and its derivative with respect to time I (t ) = f ⎛V (t ). S. Lecture 15 Prof.

Lecture 15 Prof.0 ) + v(t )⎜ f (V . dt ⎠ dt ⎠ ⎝ ⎝ Let’s assume that v(t) is very small.EECS 105 Spring 2004. ξ ) ⎟ dt ⎜ ∂ξ ⎝ ⎠ ξ =0 University of California. Berkeley EECS 105 Spring 2004. ⎟ ⎟ = f ⎜V0 + v(t ). J. dv(t ) ⎞ + v(t )⎛ ⎜ ⎟ ⎜ ⎝ 0 dt ⎠ dv(t ) ⎞ ∂ f (V . ⎟ dt ⎠ V =V0 ⎝ ∂V Doing the same about the second argument: ⎞ dv(t ) ⎛ ∂ ⎛ ∂ ⎞ ⎜ + I (t ) ≈ f (V0 . Berkeley Department of EECS 10 . so we can do a Taylor expansion around 0 Department of EECS University of California. ).0) 0 1 ⎛ ∂ ⎞ =⎜ f (V . S.0) ⎟ R ⎝ ∂V ⎠ V =V0 C= ⎞ dv(t ) ⎛ ∂ ⎜ ⎟ f (0. ξ ) ⎟ ⎟ dt ⎜ ∂ξ ⎝ ∂V ⎠ V =V ⎝ ⎠ ξ =0 We can then write: 0 I (t ) ≈ I 0 + v(t ) 1 dv(t ) + C R dt Where I0 = f (V . Smith linearization Taylor expansion about the first argument: ⎛ df ( x) ⎞ f ( x) ≈ f ( x0 ) + x⎜ +L ⎟ ⎝ dx ⎠ x = x0 I (t ) ≈ f ⎛V . We write this: V (t ) = V0 + v(t ) If we plug this back into our equation: dV (t ) ⎞ dv(t ) ⎞ ⎛ ⎛ I (t ) = f ⎜V (t ). and then have the time varying signal be small compared to the DC voltage. J. Smith Often we will be interested in running devices at a particular steady voltage or operating point.0) ⎟ f (0. S. Lecture 15 Prof.

Smith From math to equivalent circuit We can then take: I (t ) = I 0 + i (t ) Where i(t) is the small signal current. J. in series or parallel Department of EECS University of California. The linear equations can often be translated back into a circuit which would have the equivalent set of linear equations. Lecture 15 Prof. of course! Department of EECS C R − University of California. S. Smith Since a small change to a voltage or current into a device with other voltages or currents held constant generally results in a small. proportionate change. S.EECS 105 Spring 2004. Why would we do this? Because we can develop and use intuition about linear circuit elements. J. like resistors and capacitors. we can often model a device for small changes with linear equations. Berkeley EECS 105 Spring 2004. Then: i (t ) ≈ v(t ) 1 dv(t ) + C R dt But this mathematical formula relating the small signal voltage to the small signal currents can be i (t ) → represented as a circuit again: + v(t ) Which is why we picked R and C. Lecture 15 Prof. Berkeley 11 .

you can look at a device and create a equivalent circuit Charge storage is modeled as a capacitor Currents proportional to voltages are modeled by resistors. Smith VLSI resistor Lets construct a small signal model for a VLSI resistor: Department of EECS University of California. S. Lecture 15 Prof. Berkeley 12 . Smith Constructing by inspection Many times. Lecture 15 Prof. S. J.EECS 105 Spring 2004. Berkeley EECS 105 Spring 2004. No model is perfect. build a simple model first. J. and then add to it as necessary Remember: Parallel: current gets a choice Series: current must go through both Department of EECS University of California. rather than going through a process of deriving a mathematical formula and then translating it back into a circuit model.

Smith Substrate potential Lets look at the back gate effect in a small signal model Effect: changes threshold voltage. which changes the drain current … substrate acts like a “backgate” ∂i ∆i g mb = D = D ∆v BS Q ∂v BS Q Q = (VGS. Smith Back to the FET The current from the drain of our FET can be modeled for small signals: iDS (t ) = I DS + ids For a given operating point voltage for Vgs and Vds. VDS. Berkeley EECS 105 Spring 2004. Lecture 15 Prof. J. we get: ids = Which we will then label: ∂iDS ∂i vgs + DS vds ∂vgs ∂vds ids = g m vgs + 1 vds ro Transconductance Conductance Department of EECS University of California. S. Lecture 15 Prof. J. VBS) ← are all held constant Department of EECS University of California. Berkeley 13 . S.EECS 105 Spring 2004.

Smith Notice that we have terms in our equations which give the small signal current into one terminal in as a constant times the small signal voltage into another terminal.EECS 105 Spring 2004. Berkeley EECS 105 Spring 2004. S. Berkeley 14 . In order to translate that into an equivalent circuit. J. we will use variable current sources + v1 − i2 = gv1 Where g is called the transconductance Department of EECS University of California. S. Lecture 15 Prof. Lecture 15 Prof. Smith Backgate Transconductance VT = VT 0 + γ ( VSB − 2φ p − −2φ p ) Result: Department of EECS g mb = ∂iD ∂vBS = Q ∂iD ∂VTn Q ∂VTn ∂vBS = Q γ gm 2 −VBS − 2φ p University of California. J.

EECS 105 Spring 2004. There are also stray capacitances to the drain and source contacts Department of EECS University of California. J. Smith Capacitances While adequate for some purposes. for high frequencies we need to account for the current necessary to charge up the gate to supply the field across the oxide. S. Smith Combining terms: Small-Signal Model We now have three small singnal contributions to the current into the drain terminal for our FET. the model so far implies that the current into the gate is zero. and Vds ids = g m vgs + g mb vbs + Department of EECS 1 vds ro University of California. Lecture 15 Prof. from changes in Vgs. J. Berkeley Notice that the change in the small signal current into the drain from A small signal change in Vds can be modeled as a resistor. This is a good approximation for low frequencies. Lecture 15 Prof. Vbs. Berkeley 15 . EECS 105 Spring 2004. S.

fringing fields will make The overlap capacitance larger) Department of EECS University of California. S. because it is pinched off from the charge in the channel. J. Gate-source capacitance: There is fringing charge between the edge of the gate and the source. S. J. Smith MOSFET Capacitances in Saturation The gate-drain capacitance is only the fringe capacitance when in saturation. Berkeley 16 . Berkeley EECS 105 Spring 2004. Lecture 15 Prof. Smith Gate-Source Capacitance Cgs Wedge-shaped charge in saturation (see H&S 4.EECS 105 Spring 2004.5. Lecture 15 Prof.4 for details) effective area is (2/3)WL C gs = (2 / 3)WLCox + Cov Overlap capacitance along source edge of gate Cov = LDWCox (This is an underestimate. but also to the channel Department of EECS University of California.

J. Berkeley 17 . S. Lecture 15 Junction Capacitances Prof. just overlap capacitance between drain and source Department of EECS University of California. Lecture 15 Prof. Smith The source. and since VSB and VDB = VSB + VDS reverse biases are different.EECS 105 Spring 2004. Smith Gate-Drain Capacitance Cgd There is no contribution due to change in inversion charge in channel. Berkeley EECS 105 Spring 2004. S. Capacitances to the drain and source will be junction capacitances. gate. J. and drain will also have capacitances between them and the well or substrate. the capacitances will be different Department of EECS University of California.

S. J. use the simplest one that is sufficient. Lecture 15 Prof. Smith Seeking perfection… Remember that all of the capacitances. because it is the main way we can deal intuitively with these devices! Department of EECS University of California.EECS 105 Spring 2004. Berkeley 18 . resistances and transimpedances will change as the operating point changes There is no such thing as a perfect small signal model. Sometimes a small signal model is used well outside of where it is accurate.

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