OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 1

Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 2

Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 3

New Delhi-63. 4 .Learning Objective Understand the purpose of the operating system Distinguish between a resource. U1. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. a program..

by Parul Arora.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 5 .. New Delhi-63.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. • Operating system goals: Execute user programs and make solving user problems easier. 6 . • Use the computer hardware in an efficient manner. by Parul Arora. Make the computer system convenient to use.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware.

I/O devices). 3. memory. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. 2. 7 .. database systems. business programs). video games. by Parul Arora.Computer System Components 1. 4. Hardware – provides basic computing resources (CPU. Users (people. machines. other computers). Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. New Delhi-63.

. U1. 8 .Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

9 . U1. New Delhi-63.Operating System Definitions • Resource allocator – manages and allocates resources. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Kernel – the one program running at all times (all else being application programs).. • Control program – controls the execution of user programs and operations of I/O devices .

. 10 .Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. New Delhi-63.

. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. First rudimentary operating system.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. 11 . U1. New Delhi-63.

New Delhi-63. 12 .. by Parul Arora. U1.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

13 . New Delhi-63.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1..

New Delhi-63. U1. • CPU scheduling – the system must choose among several jobs ready to run. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Allocation of devices.OS Features Needed for Multiprogramming • I/O routine supplied by the system. • Memory management – the system must allocate the memory to several jobs.. by Parul Arora. 14 .

U1. it seeks the next “control statement” from the user’s keyboard.. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. On-line communication between the user and the system is provided. when the operating system finishes the execution of one command. by Parul Arora. . New Delhi-63. A job swapped in and out of memory to the disk.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory).

Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • I/O devices – keyboards. display screens. New Delhi-63. • May run several different types of operating systems (Windows.Desktop Systems • Personal computers – computer system dedicated to a single user. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. mice. MacOS. U1. UNIX. small printers.. by Parul Arora. 16 . • User convenience and responsiveness.

17 . • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. • Tightly coupled system – processors share memory and a clock. communication usually takes place through the shared memory. New Delhi-63..

master processor schedules and allocated work to slave processors. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. New Delhi-63. Many processes can run at once without performance deterioration. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Parallel Systems (Cont. 18 . U1.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system..

U1. by Parul Arora. 19 .Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

processors communicate with one another through various communications lines. • Loosely coupled system – each processor has its own local memory. 20 . New Delhi-63. such as high-speed buses or telephone lines.Distributed Systems • Distribute the computation among several physical processors. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Advantages of distributed systems.. by Parul Arora. U1.

U1. New Delhi-63. by Parul Arora.Distributed Systems (cont) • Requires networking infrastructure. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.. 21 .

U1.General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 22 . by Parul Arora. New Delhi-63..

• Asymmetric clustering: one server runs the application while other servers standby. by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Clustered Systems • Clustering allows two or more systems to share storage. 23 . • Symmetric clustering: all N hosts are running the application. U1. • Provides high reliability.

by Parul Arora. and some display systems.. New Delhi-63. 24 .Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. medical imaging systems. U1. • Well-defined fixed-time constraints. • Real-Time systems may be either hard or soft real-time. industrial control systems.

U1. not supported by general-purpose operating systems.. data stored in short term memory. virtual reality) requiring advanced operating-system features. or read-only memory (ROM) Conflicts with time-sharing systems.Real-Time Systems (Cont. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) • Hard real-time: Secondary storage limited or absent. New Delhi-63. . by Parul Arora. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens.. 26 .

New Delhi-63. by Parul Arora.. U1. 27 .Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1..Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 28 .

by Parul arora U1.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63. 29 .

by Parul Arora. U1. New Delhi-63.strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 30 .how memory is structured Memory management .Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization ..

New Delhi-63. by Parul Arora.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 31 .

. 32 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • User programs go through several steps before being run. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. New Delhi-63.Background • Program must be brought into memory and placed within a process for it to be run. by Parul Arora.

U1. base and limit registers). must recompile code if starting location changes. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Load time: Must generate relocatable code if memory location is not known at compile time. Need hardware support for address maps (e...Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.g. absolute code can be generated. New Delhi-63. 33 . by Parul Arora. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.

Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 34 . by Parul Arora. New Delhi-63. U1.

U1. Logical address – generated by the CPU. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. 35 . New Delhi-63. also referred to as virtual address.Logical vs. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. logical (virtual) and physical addresses differ in execution-time address-binding scheme. by Parul Arora. Physical address – address seen by the memory unit.. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.

• The user program deals with logical addresses. it never sees the real physical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • In MMU scheme. U1. by Parul Arora. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory..Memory-Management Unit • Hardware device that maps virtual to physical address. 36 .

. New Delhi-63. by Parul Arora. 37 .Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Useful when large amounts of code are needed to handle infrequently occurring cases.. • No special support from the operating system is required implemented through program design. by Parul Arora. unused routine is never loaded. New Delhi-63. 38 . U1.

by Parul Arora. used to locate the appropriate memory-resident library routine. and executes the routine. stub. • Stub replaces itself with the address of the routine. 39 . • Dynamic linking is particularly useful for libraries. • Operating system needed to check if routine is in processes’ memory address. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Small piece of code.Dynamic Linking • Linking postponed until execution time. U1. New Delhi-63..

no special support needed from operating system. 40 . U1.. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Implemented by user. by Parul Arora. • Needed when process is larger than amount of memory allocated to it.Overlays • Keep in memory only those instructions and data that are needed at any given time. New Delhi-63.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 41

Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 42

Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 43

Contiguous Allocation • Main memory usually into two partitions: Resident operating system. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. limit register contains range of logical addresses – each logical address must be less than the limit register. U1. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. and from changing operating-system code and data. 44 .. User processes then held in high memory. Relocation register contains value of smallest physical address. usually held in low memory with interrupt vector.

by Parul Arora. 45 .Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63..

.) Multiple-partition allocation Hole – block of available memory. holes of various size are scattered throughout memory.Contiguous Allocation (Cont. When a process arrives. U1. it is allocated memory from a hole large enough to accommodate it. by Parul Arora. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 46 .

Best-fit: Allocate the smallest hole that is big enough. Produces the smallest leftover hole. Produces the largest leftover hole. must also search entire list.. must search entire list. unless ordered by size. 47 . by Parul Arora. New Delhi-63.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. U1. Worst-fit: Allocate the largest hole. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

this size difference is memory internal to a partition. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Compaction is possible only if relocation is dynamic. Do I/O only into OS buffers. I/O problem Latch job in memory while it is involved in I/O. • Internal Fragmentation – allocated memory may be slightly larger than requested memory.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. but not being used. U1. but it is not contiguous. 48 .. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. by Parul Arora. and is done at execution time. New Delhi-63.

by Parul Arora. U1. • Divide physical memory into fixed-sized blocks called frames (size is power of 2.Paging • Logical address space of a process can be noncontiguous. between 512 bytes and 8192 bytes). process is allocated physical memory whenever the latter is available. New Delhi-63. • To run a program of size n pages. • Divide logical memory into blocks of same size called pages. need to find n free frames and load program. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Set up a page table to translate logical to physical addresses. 49 . • Internal fragmentation. • Keep track of all free frames..

New Delhi-63. 50 . Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. by Parul Arora. U1..

by Parul Arora. U1..Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 51 . New Delhi-63.

New Delhi-63.. U1. by Parul Arora. 52 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 53 . New Delhi-63..

Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 54 . by Parul Arora..

• In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. • Page-table base register (PTBR) points to the page table. New Delhi-63.. 55 . U1.Implementation of Page Table • Page table is kept in main memory. • Page-table length register (PRLR) indicates size of the page table. by Parul Arora. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

A´´) If A´ is in associative register. U1. get frame # out.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. 56 .. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

U1. by Parul Arora. 57 ..Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

58 . ration related to number of associative registers. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.. New Delhi-63. by Parul Arora.

. “invalid” indicates that the page is not in the process’ logical address space. 59 . U1.Memory Protection • Memory protection implemented by associating protection bit with each frame. by Parul Arora. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. New Delhi-63. and is thus a legal page. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. 60 . by Parul Arora. New Delhi-63. U1.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.. 61 . by Parul Arora.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • A simple technique is a two-level page table. U1.Hierarchical Page Tables • Break up the logical address space into multiple page tables. by Parul Arora. 62 ..

New Delhi-63. Since the page table is paged. 63 . a 10-bit page offset.. the page number is further divided into: Thus.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. by Parul Arora. U1. a page offset consisting of 12 bits.

64 . New Delhi-63.Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1.

U1. by Parul Arora.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 65 .

This page table contains a chain of elements hashing to the same location. 66 . • The virtual page number is hashed into a page table. U1. the corresponding physical frame is extracted. If a match is found.Hashed Page Tables • Common in address spaces > 32 bits. by Parul Arora. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Virtual page numbers are compared in this chain searching for a match.

New Delhi-63.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. by Parul Arora. 67 .

but increases time needed to search the table when a page reference occurs. New Delhi-63. • Use hash table to limit the search to one — or at most a few — page-table entries. with information about the process that owns that page.. • Entry consists of the virtual address of the page stored in that real memory location. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Decreases memory needed to store each page table. 68 .Inverted Page Table • One entry for each real page of memory. U1.

U1. 69 . by Parul Arora..Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

compilers. Shared code must appear in same location in the logical address space of all processes. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. text editors. New Delhi-63. 70 .. by Parul Arora. The pages for the private code and data can appear anywhere in the logical address space. window systems).e.. Private code and data Each process keeps a separate copy of the code and data. U1.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.

. New Delhi-63.Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. 71 .

stack. 72 . local variables. symbol table. A program is a collection of segments. procedure. New Delhi-63. method. A segment is a logical unit such as: main program. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. global variables.Segmentation Memory-management scheme that supports user view of memory. common block. function. object. U1. by Parul Arora..

by Parul Arora. New Delhi-63.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 73 .. U1.

New Delhi-63. 74 . U1. by Parul Arora.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

. limit – specifies the length of the segment. offset>. U1. each table entry has: base – contains the starting physical address where the segments reside in memory. 75 . Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. • • • Segment-table base register (STBR) points to the segment table’s location in memory.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. Segment table – maps two-dimensional physical addresses. by Parul Arora.

first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. dynamic by segment table • Sharing. New Delhi-63. by Parul Arora.. U1. shared segments same segment number • Allocation.Segmentation Architecture (Cont.) • Relocation. 76 .

• Since segments vary in length.) • Protection. 77 . code sharing occurs at segment level. New Delhi-63. by Parul Arora. U1.Segmentation Architecture (Cont. memory allocation is a dynamic storage-allocation problem. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.

by Parul Arora.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 78 .. U1.

79 .Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora. New Delhi-63.

U1.. New Delhi-63. 80 . by Parul Arora.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

but rather the base address of a page table for this segment. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. New Delhi-63. 81 .

.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 82 . New Delhi-63.

Segmentation with Paging – Intel 386 As shown in the following diagram. New Delhi-63. by Parul Arora. U1. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 83 .

New Delhi-63. 84 . U1. by Parul Arora..Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1. 85 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Evaluate the trade-offs in terms of memory size (main memory. • Describe the reason for and use of cache memory.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. 86 . • Discuss the concept of thrashing.. • Summarize the principles of virtual memory as applied to caching and paging. auxiliary memory) and processor speed. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. by Parul Arora. cache memory. New Delhi-63.

Allows for more efficient process creation. New Delhi-63. Logical address space can therefore be much larger than physical address space.. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Only part of the program needs to be in memory for execution. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. by Parul Arora. . Allows address spaces to be shared by several processes.Background • Virtual memory – separation of user logical memory from physical memory.

by Parul Arora. U1. 88 .Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

U1.Demand Paging Bring a page into memory only when it is needed. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 89 . New Delhi-63..

90 . U1. by Parul Arora. New Delhi-63.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. but valid-invalid bit 1 Example of a page table snapshot. by Parul Arora.. 91 . New Delhi-63.

92 .Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. by Parul Arora.

93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Page Fault • If there is ever a reference to a page. • • • • Get empty frame. New Delhi-63. by Parul Arora.. . Reset tables. validation bit = 1. Restart instruction: Least Recently Used block move U1. Just not in memory. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. Swap page into frame.

94 .. by Parul Arora. New Delhi-63. U1.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

What happens if there is no free frame? • Page replacement – find some page in memory. • Same page may be brought into memory several times. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. swap it out. algorithm performance – want an algorithm which will result in minimum number of page faults. by Parul Arora. 95 . but not really in use. U1.

96 .. U1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.0 if p = 0 no page faults if p = 1.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1.

New Delhi-63. by Parul Arora. U1.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. 97 .000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Swap Page Time = 10 msec = 10.

98 .. U1.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

• Free pages are allocated from a pool of zeroed-out pages.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. only then is the page copied. 99 . by Parul Arora. New Delhi-63..If either process modifies a shared page. U1. • COW allows more efficient process creation as only modified pages are copied.

. by Parul Arora. • A file is initially read using demand paging. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. • Also allows several processes to map the same file allowing the pages in memory to be shared. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. New Delhi-63.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. A page-sized portion of the file is read from the file system into a physical page.. U1. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.. 101 .Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. New Delhi-63.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. 102 . U1. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk.

103 . by Parul Arora. U1. New Delhi-63..Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

If there is no free frame. New Delhi-63. • Find a free frame: . U1. • Read the desired page into the (newly) free frame. • Restart the process. 104 . Update the page and frame tables.. . use it.If there is a free frame. use a page replacement algorithm to select a victim frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Basic Page Replacement • Find the location of the desired page on disk.

by Parul Arora. New Delhi-63.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 105 .

2. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 4. the reference string is 1. 3. 5. 2. by Parul Arora. New Delhi-63. 1. 3. 4. U1. 5. In all our examples. 1. 2. 106 .Page Replacement Algorithms Want lowest page-fault rate.

107 . by Parul Arora. New Delhi-63.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 1. 3. 5. 4. 4. U1. 108 . 2. 2.First-In-First-Out (FIFO) Algorithm Reference string: 1. by Parul Arora. 3. 2. New Delhi-63. 1.

New Delhi-63. U1.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 109 .

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

by Parul Arora. 113 .Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1..

4. 3. by Parul Arora. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. When a page needs to be changed. 1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 114 . every time page is referenced through this entry. copy the clock into the counter. 5. 2.. U1. 1. New Delhi-63.Least Recently Used (LRU) Algorithm Reference string: 1. look at the counters to determine which are to change. 2. 4. 2. 3.

New Delhi-63. U1.. 115 .LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

New Delhi-63. U1.LRU Algorithm (Cont. 116 ..) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

117 . New Delhi-63.. U1.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

Replace the one which is 0 (if one exists). rules. replace next page (in clock order).LRU Approximation Algorithm Reference bit With each page associate a bit. If page to be replaced (in clock order) has reference bit = 1. initially = 0 When page is referenced bit set to 1. then: set reference bit 0. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 118 . leave page in memory. U1.. Clock replacement. We do not know the order. Second chance Need reference bit. however. by Parul Arora. New Delhi-63.

Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 119 . New Delhi-63. U1..

120 . by Parul Arora. New Delhi-63. LFU Algorithm: replaces page with smallest count.Counting Algorithms • Keep a counter of the number of references that have been made to each page.. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. U1. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

2 pages to handle to. 2 pages to handle from. might span 2 pages. U1. 121 . • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. by Parul Arora. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Allocation of Frames • Each process needs minimum number of pages. New Delhi-63. • Two major allocation schemes.

if 100 frames and 5 processes. New Delhi-63. 122 . by Parul Arora.g.. U1. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. give each 20 pages.. • Proportional allocation – Allocate according to the size of process.Fixed Allocation • Equal allocation – e.

Priority Allocation • Use a proportional allocation scheme using priorities rather than size. select for replacement a frame from a process with lower priority number. by Parul Arora.. U1. New Delhi-63. • If process Pi generates a page fault. 123 . select for replacement one of its frames. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

one process can take a frame from another. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Global vs. 124 . Local Allocation • Global replacement – process selects a replacement frame from the set of all frames. New Delhi-63. by Parul Arora. U1.. • Local replacement – each process selects from only its own set of allocated frames.

New Delhi-63. another process added to the system. This leads to: low CPU utilization. the page-fault rate is very high.. by Parul Arora. Thrashing ≡ a process is busy swapping pages in and out. operating system thinks that it needs to increase the degree of multiprogramming. 125 .Thrashing If a process does not have “enough” pages. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

U1.. New Delhi-63.Thrashing Why does paging work? Locality model Process migrates from one locality to another. Localities may overlap. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 126 .

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

New Delhi-63. process loses frame.. U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. If actual rate too low. 130 . If actual rate too high.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. process gains frame.

by Parul Arora. New Delhi-63. U1.Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 131 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. the working set of each process is stored in the TLB.The amount of memory accessible from the TLB. Otherwise there is a high degree of page faults.Other Considerations (Cont. 132 . U1.) TLB Reach .. TLB Reach = (TLB Size) X (Page Size) Ideally. by Parul Arora. New Delhi-63.

New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This may lead to an increase in fragmentation as not all applications require a large page size. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation..Increasing the Size of the TLB • Increase the Page Size. U1. • Provide Multiple Page Sizes. 133 .

length. i < A.length. j++) for (i = 0. j++) A[i.length. U1. 134 .j] = 0. 1024 x 1024 page faults Program 2 for (i = 0. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.length.Other Considerations (Cont. New Delhi-63. Each row is stored in one page Program 1 for (j = 0. i < A. by Parul Arora.j] = 0. j < A. i++) A[i. j < A.. i++) for (j = 0.) Program structure int A[][] = new int[1024][1024].

.and also allows degree of multiprogramming to be raised. New Delhi-63. by Parul Arora. Multiprogramming increased the performance of computer system. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Memory management algorithms differ in many concepts. Virtual memory frees application programers from worrying about memory availability U1.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Virtual memory allows extremely large processes to be run.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. personal computing and dedicated. Second Chance. First In First Out. Least Recently Used. . Operating systems are a type of system software that allow applications to interface with computer hardware.Summary • In the introduction. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. and Least Frequently U1. Resources are any objects that can be allocated within a system. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. 136 Used. New Delhi-63. Policies for determining which pages to load and remove from memory include Random Replacement. and the operating system is responsible for managing them. Four major categories of operating systems are batch. we saw that software can be roughly divided into two groups: application software and system software. by Parul Arora. timesharing.

U1. New Delhi-63. The Hardware mechanism that enables a device to notify the CPU is called __________..Review Questions (OBJ) 1. a) Polling b) Interrupt c) System Call d) None of the above 2. 137 . by Parul Arora. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. 138 . _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 4. by Parul Arora.Review Questions (OBJ) 3. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. U1. Virtual memory is __________.

a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 5. U1. by Parul Arora.. The term " Operating System " means ________. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. New Delhi-63. 139 .

a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. The principle of locality of reference justifies the use of ________. ) Routine a) b) c) d) is not loaded until it is called. by Parul Arora. 140 .Review Questions (OBJ) 7. The main program is loaded into memory & is executed. All routines are kept on disk in a relocatable load format. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8.. New Delhi-63.

141 . ) The problem of thrashing is effected scientifically by ________.Review Questions (OBJ) 9. a) Program structure b) Program size c) Primary storage size d) None of the above U1.. New Delhi-63. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. a) 10 b) 7 c) 8 d) 9 10. the total number of page faults caused by the process will be __________. If all page frames are initially empty. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

What are the three main purposes of an operating system? 4. Explain the difference between internal and external fragmentation 10. How do I/O-bound and CPU-bound programs differ? 6. 9. Explain the difference between logical and physical addresses. What are the main differences between operating systems for mainframe computers and personal computers? 3. How does a real-time system differ from time-share? 8. by Parul Arora. U1. What is the main advantage of multiprogramming 2. How do MULTICS and UNIX differ? 7. 142 . List the four steps that are necessary to run a program on a completely dedicated machine 5. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..Review Questions (Short) 1.

What is reentrant code? 14. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What is virtual memory? 17. What are overlays? 12. How was memory mapping used in extending the usefulness of minicomputers? 13. New Delhi-63. 143 . What is Belady’s anomaly? 19.Review Questions (Short) 11. 16. What is meant by locality? 21.. by Parul Arora. When do page faults occur? 15. How do global and local allocation differ? 20. Describe the actions taken by the operating system when a page fault occurs. Why is there a valid/invalid bit? Where is it kept? 18. U1.

for four page frames? 1. List ways to implement LRU. 4. and 600K (in order). 417K. how would each of the First-?t.)If a memory reference takes 200 nanoseconds. 4. 4. 7. 8. 8. 4.. 200K. 144 . Consider a paging system with the page table stored in memory. How many page faults occur for your algorithm for the following reference string. and 75 percent of all pagetable references are found in the associative registers. 7. 9.) 3. if the entry is there. New Delhi-63. 2. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (Long) 1. Given memory partitions of 100K. 3. 300K. to determine which page is victim. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 7. 8. 500K. by Parul Arora. how long does a paged memory reference take? b. 5. 112K. 4. Best-?t. U1. 5. 3. 1. 2. 5.)If we add associative registers. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 6. and Worst-?t algorithms place processes of 212K. a. 9.

”Operating System”: TMH.Recommended reading • Silbersachatz and Galvin.. by Parul Arora.. 2001 • "Operating Systems” Tannenbaum PHI..6th Ed.. New Delhi-63. U1. “Operating System Concepts” Peason. Donovan J. 4th Edition.2001 • Madnick E. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 145 .

Sign up to vote on this title
UsefulNot useful