OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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4 . by Parul Arora. New Delhi-63.Learning Objective Understand the purpose of the operating system Distinguish between a resource. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. a program.

by Parul Arora. 5 . New Delhi-63.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. by Parul Arora. U1. • Use the computer hardware in an efficient manner. New Delhi-63. Make the computer system convenient to use. 6 . • Operating system goals: Execute user programs and make solving user problems easier..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. 7 . Hardware – provides basic computing resources (CPU. U1. I/O devices). machines. business programs). Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. 2. other computers). 3. New Delhi-63. video games. database systems.. Users (people.Computer System Components 1. 4. memory.

Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 8 . U1. by Parul Arora. New Delhi-63..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Kernel – the one program running at all times (all else being application programs). 9 . New Delhi-63..Operating System Definitions • Resource allocator – manages and allocates resources. by Parul Arora. • Control program – controls the execution of user programs and operations of I/O devices .

. U1.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 10 .

11 . New Delhi-63. First rudimentary operating system.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another.. by Parul Arora. U1. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 12 . New Delhi-63. by Parul Arora.

New Delhi-63. 13 . U1..Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 14 . • CPU scheduling – the system must choose among several jobs ready to run. by Parul Arora. • Allocation of devices. New Delhi-63.OS Features Needed for Multiprogramming • I/O routine supplied by the system. • Memory management – the system must allocate the memory to several jobs. U1.

it seeks the next “control statement” from the user’s keyboard. New Delhi-63. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. On-line communication between the user and the system is provided.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). when the operating system finishes the execution of one command. A job swapped in and out of memory to the disk. by Parul Arora. .

display screens. New Delhi-63. small printers. U1. UNIX. • I/O devices – keyboards. by Parul Arora. mice. 16 . Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. MacOS. • May run several different types of operating systems (Windows..Desktop Systems • Personal computers – computer system dedicated to a single user. • User convenience and responsiveness. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features.

Parallel Systems • Multiprocessor systems with more than on CPU in close communication. New Delhi-63. communication usually takes place through the shared memory.. 17 . U1. • Tightly coupled system – processors share memory and a clock. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1. master processor schedules and allocated work to slave processors. New Delhi-63. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Parallel Systems (Cont. 18 . Many processes can run at once without performance deterioration.. by Parul Arora.

. U1. New Delhi-63.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 19 . by Parul Arora.

by Parul Arora. New Delhi-63. processors communicate with one another through various communications lines. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Distributed Systems • Distribute the computation among several physical processors. such as high-speed buses or telephone lines. 20 . • Loosely coupled system – each processor has its own local memory.. U1. • Advantages of distributed systems.

• Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems. U1. 21 . New Delhi-63.Distributed Systems (cont) • Requires networking infrastructure. by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

22 . U1. by Parul Arora..General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

by Parul Arora. New Delhi-63.Clustered Systems • Clustering allows two or more systems to share storage. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • Symmetric clustering: all N hosts are running the application. • Provides high reliability. 23 . U1. • Asymmetric clustering: one server runs the application while other servers standby.

by Parul Arora. • Well-defined fixed-time constraints. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. and some display systems. 24 .. • Real-Time systems may be either hard or soft real-time. medical imaging systems. industrial control systems. New Delhi-63. U1.

• Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. by Parul Arora..) • Hard real-time: Secondary storage limited or absent. . data stored in short term memory. or read-only memory (ROM) Conflicts with time-sharing systems.Real-Time Systems (Cont. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. virtual reality) requiring advanced operating-system features. U1. New Delhi-63. not supported by general-purpose operating systems.

26 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. New Delhi-63. by Parul Arora.

27 .. U1. New Delhi-63.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

by Parul Arora. U1.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 28 . New Delhi-63..

by Parul arora U1.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63. 29 .

U1. by Parul Arora. 30 . New Delhi-63.strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management..how memory is structured Memory management .Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .

by Parul Arora. New Delhi-63.. U1.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 31 .

U1. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program..Background • Program must be brought into memory and placed within a process for it to be run. • User programs go through several steps before being run. 32 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

New Delhi-63. 33 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. Need hardware support for address maps (e. must recompile code if starting location changes. absolute code can be generated.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.g. by Parul Arora. base and limit registers). • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. • Load time: Must generate relocatable code if memory location is not known at compile time...

Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 34 . U1. by Parul Arora.. New Delhi-63.

Logical vs. U1. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. 35 . logical (virtual) and physical addresses differ in execution-time address-binding scheme. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.. by Parul Arora. Logical address – generated by the CPU. Physical address – address seen by the memory unit. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. also referred to as virtual address.

by Parul Arora. 36 . • In MMU scheme. U1.. • The user program deals with logical addresses.Memory-Management Unit • Hardware device that maps virtual to physical address. New Delhi-63. it never sees the real physical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.

37 . by Parul Arora.Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63..

• Useful when large amounts of code are needed to handle infrequently occurring cases.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. • No special support from the operating system is required implemented through program design. unused routine is never loaded. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 38 . U1.

New Delhi-63. • Operating system needed to check if routine is in processes’ memory address. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. stub. and executes the routine. U1. used to locate the appropriate memory-resident library routine. 39 ..Dynamic Linking • Linking postponed until execution time. • Dynamic linking is particularly useful for libraries. • Stub replaces itself with the address of the routine. • Small piece of code.

by Parul Arora. 40 .Overlays • Keep in memory only those instructions and data that are needed at any given time. no special support needed from operating system. New Delhi-63. U1.. • Needed when process is larger than amount of memory allocated to it. • Implemented by user. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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U1.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. limit register contains range of logical addresses – each logical address must be less than the limit register. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. usually held in low memory with interrupt vector. Relocation register contains value of smallest physical address. by Parul Arora. 44 .. User processes then held in high memory. New Delhi-63. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. and from changing operating-system code and data.

. New Delhi-63. U1. by Parul Arora. 45 .Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

When a process arrives. by Parul Arora. New Delhi-63.Contiguous Allocation (Cont.. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. holes of various size are scattered throughout memory. 46 . it is allocated memory from a hole large enough to accommodate it.) Multiple-partition allocation Hole – block of available memory. U1.

Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. unless ordered by size. must search entire list. Produces the smallest leftover hole. New Delhi-63. must also search entire list. Best-fit: Allocate the smallest hole that is big enough. Produces the largest leftover hole. by Parul Arora. 47 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Worst-fit: Allocate the largest hole.. U1.

by Parul Arora. Do I/O only into OS buffers. • Internal Fragmentation – allocated memory may be slightly larger than requested memory.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. and is done at execution time. 48 . New Delhi-63. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block.. U1. I/O problem Latch job in memory while it is involved in I/O. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but it is not contiguous. Compaction is possible only if relocation is dynamic. but not being used. this size difference is memory internal to a partition.

• Divide logical memory into blocks of same size called pages. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 49 . • Keep track of all free frames. • Internal fragmentation. • Set up a page table to translate logical to physical addresses. need to find n free frames and load program. • To run a program of size n pages. between 512 bytes and 8192 bytes).. by Parul Arora. New Delhi-63. • Divide physical memory into fixed-sized blocks called frames (size is power of 2.Paging • Logical address space of a process can be noncontiguous. U1. process is allocated physical memory whenever the latter is available.

Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. New Delhi-63. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 50 .. by Parul Arora.

51 . by Parul Arora. New Delhi-63. U1.Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1.. 52 .

. by Parul Arora.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. 53 .

Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 54 . U1. New Delhi-63. by Parul Arora.

by Parul Arora. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. One for the page table and one for the data/instruction. • In this scheme every data/instruction access requires two memory accesses. • Page-table length register (PRLR) indicates size of the page table. U1. 55 .Implementation of Page Table • Page table is kept in main memory. • Page-table base register (PTBR) points to the page table.

A´´) If A´ is in associative register. U1.. New Delhi-63. by Parul Arora. get frame # out. 56 . Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´.

57 .. U1. New Delhi-63. by Parul Arora.Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.. ration related to number of associative registers.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. 58 . Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

and is thus a legal page. “invalid” indicates that the page is not in the process’ logical address space.. U1. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 59 . by Parul Arora.Memory Protection • Memory protection implemented by associating protection bit with each frame. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space.

Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. U1. 60 .

by Parul Arora. 61 ..Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

by Parul Arora.Hierarchical Page Tables • Break up the logical address space into multiple page tables. 62 . • A simple technique is a two-level page table.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

U1. 63 .Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. Since the page table is paged. the page number is further divided into: Thus. New Delhi-63.. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. a page offset consisting of 12 bits. by Parul Arora. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a 10-bit page offset.

by Parul Arora. U1. New Delhi-63..Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 64 .

New Delhi-63.. U1. by Parul Arora. 65 .Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Virtual page numbers are compared in this chain searching for a match. If a match is found. This page table contains a chain of elements hashing to the same location. 66 . the corresponding physical frame is extracted. New Delhi-63. • The virtual page number is hashed into a page table. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Hashed Page Tables • Common in address spaces > 32 bits.. by Parul Arora.

67 . by Parul Arora. U1. New Delhi-63.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. but increases time needed to search the table when a page reference occurs.Inverted Page Table • One entry for each real page of memory. with information about the process that owns that page. 68 . • Decreases memory needed to store each page table. • Entry consists of the virtual address of the page stored in that real memory location. U1. • Use hash table to limit the search to one — or at most a few — page-table entries. New Delhi-63.

New Delhi-63. U1..Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 69 .

by Parul Arora.e.. text editors.. Shared code must appear in same location in the logical address space of all processes. New Delhi-63. window systems). Private code and data Each process keeps a separate copy of the code and data. compilers. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 70 .Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. The pages for the private code and data can appear anywhere in the logical address space.

by Parul Arora.Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. 71 .

by Parul Arora. 72 . object. U1. method. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Segmentation Memory-management scheme that supports user view of memory. procedure. A program is a collection of segments. function. local variables. symbol table.. global variables. common block. stack. A segment is a logical unit such as: main program.

by Parul Arora. New Delhi-63.. 73 . U1.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 74 . New Delhi-63. U1.

• • • Segment-table base register (STBR) points to the segment table’s location in memory. by Parul Arora. each table entry has: base – contains the starting physical address where the segments reside in memory. Segment table – maps two-dimensional physical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. limit – specifies the length of the segment. U1. offset>. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. New Delhi-63.. 75 .Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number.

76 ..) • Relocation.Segmentation Architecture (Cont. shared segments same segment number • Allocation. by Parul Arora. U1. dynamic by segment table • Sharing. New Delhi-63. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. 77 . • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Since segments vary in length..Segmentation Architecture (Cont. U1. memory allocation is a dynamic storage-allocation problem. code sharing occurs at segment level.) • Protection. New Delhi-63. by Parul Arora.

. New Delhi-63. 78 . U1.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 79 . U1. New Delhi-63. by Parul Arora..

by Parul Arora. 80 . New Delhi-63.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

but rather the base address of a page table for this segment. U1.Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. by Parul Arora. 81 .

MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1. 82 .

by Parul Arora. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. U1. 83 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation with Paging – Intel 386 As shown in the following diagram. New Delhi-63.

84 . U1.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora..

New Delhi-63. 85 .Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1.

auxiliary memory) and processor speed. by Parul Arora. New Delhi-63. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. cache memory. 86 . U1.. • Discuss the concept of thrashing. • Summarize the principles of virtual memory as applied to caching and paging. • Evaluate the trade-offs in terms of memory size (main memory. • Describe the reason for and use of cache memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software.

New Delhi-63. .. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. by Parul Arora. Allows for more efficient process creation. Only part of the program needs to be in memory for execution. Allows address spaces to be shared by several processes. Logical address space can therefore be much larger than physical address space.Background • Virtual memory – separation of user logical memory from physical memory. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63..Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. 88 .

89 . New Delhi-63.Demand Paging Bring a page into memory only when it is needed. by Parul Arora. U1. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

New Delhi-63.. U1.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 90 . by Parul Arora.

Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. by Parul Arora.. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. but valid-invalid bit 1 Example of a page table snapshot. 91 .

92 . by Parul Arora. U1.. New Delhi-63.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. Just not in memory. • • • • Get empty frame. New Delhi-63. Swap page into frame. by Parul Arora. validation bit = 1. Reset tables. Restart instruction: Least Recently Used block move U1.Page Fault • If there is ever a reference to a page. .

.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 94 . U1.

• Same page may be brought into memory several times. algorithm performance – want an algorithm which will result in minimum number of page faults. U1.What happens if there is no free frame? • Page replacement – find some page in memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. swap it out. 95 . by Parul Arora. but not really in use. New Delhi-63.

Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. New Delhi-63. 96 . by Parul Arora..0 if p = 0 no page faults if p = 1. U1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Swap Page Time = 10 msec = 10. U1. by Parul Arora..000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 97 . New Delhi-63.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out.

U1.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 98 . by Parul Arora..

Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. only then is the page copied. U1. • COW allows more efficient process creation as only modified pages are copied. • Free pages are allocated from a pool of zeroed-out pages.If either process modifies a shared page. by Parul Arora. New Delhi-63. 99 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Subsequent reads/writes to/from the file are treated as ordinary memory accesses. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Also allows several processes to map the same file allowing the pages in memory to be shared..Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. A page-sized portion of the file is read from the file system into a physical page. by Parul Arora. • A file is initially read using demand paging. New Delhi-63. U1. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. .

101 .. New Delhi-63. by Parul Arora. U1.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 102 . • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.. by Parul Arora.

U1. 103 . New Delhi-63.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora..

New Delhi-63. by Parul Arora. • Find a free frame: . U1. • Read the desired page into the (newly) free frame.If there is no free frame. .. • Restart the process. Update the page and frame tables. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Basic Page Replacement • Find the location of the desired page on disk. 104 . use it.If there is a free frame. use a page replacement algorithm to select a victim frame.

. U1. by Parul Arora. 105 .Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. 2. New Delhi-63. 3. the reference string is 1..Page Replacement Algorithms Want lowest page-fault rate. 4. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 1. 106 . 1. U1. 5. 2. 3. 2. by Parul Arora. 5. In all our examples.

by Parul Arora.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. 107 ..

2. by Parul Arora. 2. 3. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. 4. 3. 108 . 5.First-In-First-Out (FIFO) Algorithm Reference string: 1. 4. U1. New Delhi-63.. 1. 1.

First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 109 . by Parul Arora. U1..

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

by Parul Arora.. New Delhi-63. U1. 113 .Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

look at the counters to determine which are to change. 3. U1. 2. 3. When a page needs to be changed. 1. 2. by Parul Arora. 2. New Delhi-63. 1. 114 . copy the clock into the counter. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5. 4.. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. every time page is referenced through this entry. 4.Least Recently Used (LRU) Algorithm Reference string: 1.

LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. New Delhi-63. by Parul Arora. 115 .

by Parul Arora.LRU Algorithm (Cont.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 116 . New Delhi-63.

117 .. U1. New Delhi-63.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

118 . replace next page (in clock order). however. Second chance Need reference bit. Clock replacement. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management.LRU Approximation Algorithm Reference bit With each page associate a bit. New Delhi-63. Replace the one which is 0 (if one exists). initially = 0 When page is referenced bit set to 1. leave page in memory. then: set reference bit 0. If page to be replaced (in clock order) has reference bit = 1. U1. rules. by Parul Arora. We do not know the order..

U1. 119 .Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63..

MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. by Parul Arora.Counting Algorithms • Keep a counter of the number of references that have been made to each page. New Delhi-63. U1. LFU Algorithm: replaces page with smallest count. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 120 ..

U1.Allocation of Frames • Each process needs minimum number of pages. by Parul Arora. might span 2 pages. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 2 pages to handle to. • Two major allocation schemes. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. 2 pages to handle from. 121 .

.Fixed Allocation • Equal allocation – e. U1. by Parul Arora. • Proportional allocation – Allocate according to the size of process..g. 122 . si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. if 100 frames and 5 processes. give each 20 pages. New Delhi-63.

• If process Pi generates a page fault. New Delhi-63. U1. 123 . select for replacement one of its frames. select for replacement a frame from a process with lower priority number. © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Priority Allocation • Use a proportional allocation scheme using priorities rather than size. by Parul Arora.

124 . U1. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Global vs.. • Local replacement – each process selects from only its own set of allocated frames. New Delhi-63. one process can take a frame from another. by Parul Arora.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. another process added to the system.Thrashing If a process does not have “enough” pages. by Parul Arora. U1. Thrashing ≡ a process is busy swapping pages in and out. operating system thinks that it needs to increase the degree of multiprogramming. This leads to: low CPU utilization. the page-fault rate is very high. 125 .

Thrashing Why does paging work? Locality model Process migrates from one locality to another. Localities may overlap. by Parul Arora. U1. 126 .. New Delhi-63. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

by Parul Arora. If actual rate too low. process gains frame.. U1. process loses frame. If actual rate too high. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 130 .Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. New Delhi-63.

by Parul Arora.Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. 131 .

Other Considerations (Cont. New Delhi-63.) TLB Reach . the working set of each process is stored in the TLB. Otherwise there is a high degree of page faults. by Parul Arora.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. TLB Reach = (TLB Size) X (Page Size) Ideally. 132 .The amount of memory accessible from the TLB.

New Delhi-63.. 133 . This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. by Parul Arora. • Provide Multiple Page Sizes.Increasing the Size of the TLB • Increase the Page Size. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This may lead to an increase in fragmentation as not all applications require a large page size.

U1.j] = 0.length.length. 1024 x 1024 page faults Program 2 for (i = 0. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 134 . i < A. i++) A[i.length.length. j < A. i++) for (j = 0. Each row is stored in one page Program 1 for (j = 0.Other Considerations (Cont. j++) for (i = 0. by Parul Arora. i < A. j++) A[i. j < A..) Program structure int A[][] = new int[1024][1024]. New Delhi-63.j] = 0.

Memory management algorithms differ in many concepts. by Parul Arora. Multiprogramming increased the performance of computer system.and also allows degree of multiprogramming to be raised. Virtual memory frees application programers from worrying about memory availability U1. .. New Delhi-63.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Virtual memory allows extremely large processes to be run.

Resources are any objects that can be allocated within a system. Second Chance. timesharing. New Delhi-63. Operating systems are a type of system software that allow applications to interface with computer hardware. Least Recently Used. 136 Used. Policies for determining which pages to load and remove from memory include Random Replacement.. . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. Four major categories of operating systems are batch. by Parul Arora. and the operating system is responsible for managing them.Summary • In the introduction. personal computing and dedicated. and Least Frequently U1. we saw that software can be roughly divided into two groups: application software and system software. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. First In First Out.

U1. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 137 . by Parul Arora.. a) Polling b) Interrupt c) System Call d) None of the above 2. The Hardware mechanism that enables a device to notify the CPU is called __________.Review Questions (OBJ) 1.

. Virtual memory is __________. by Parul Arora. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. New Delhi-63. 138 .Review Questions (OBJ) 3. U1. 4. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. The term " Operating System " means ________. by Parul Arora. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. 139 . U1.Review Questions (OBJ) 5..

U1. 140 . The main program is loaded into memory & is executed. The principle of locality of reference justifies the use of ________. All routines are kept on disk in a relocatable load format.. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. New Delhi-63. ) Routine a) b) c) d) is not loaded until it is called. by Parul Arora.Review Questions (OBJ) 7. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

.Review Questions (OBJ) 9. a) Program structure b) Program size c) Primary storage size d) None of the above U1. If all page frames are initially empty. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ) The problem of thrashing is effected scientifically by ________. by Parul Arora. New Delhi-63. 141 . and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. a) 10 b) 7 c) 8 d) 9 10. the total number of page faults caused by the process will be __________.

Explain the difference between logical and physical addresses.. How do MULTICS and UNIX differ? 7. New Delhi-63. What are the three main purposes of an operating system? 4. What is the main advantage of multiprogramming 2. 142 . Explain the difference between internal and external fragmentation 10. How does a real-time system differ from time-share? 8. by Parul Arora. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How do I/O-bound and CPU-bound programs differ? 6. What are the main differences between operating systems for mainframe computers and personal computers? 3. U1. List the four steps that are necessary to run a program on a completely dedicated machine 5.Review Questions (Short) 1. 9.

What is reentrant code? 14. How do global and local allocation differ? 20..Review Questions (Short) 11. When do page faults occur? 15. by Parul Arora. What is meant by locality? 21. 143 . New Delhi-63. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Why is there a valid/invalid bit? Where is it kept? 18. What are overlays? 12. Describe the actions taken by the operating system when a page fault occurs. What is virtual memory? 17. 16. What is Belady’s anomaly? 19. U1. How was memory mapping used in extending the usefulness of minicomputers? 13.

9. 3.. 4. Best-?t. how long does a paged memory reference take? b.Review Questions (Long) 1. 4. Given memory partitions of 100K. 417K. and 600K (in order). 8. Consider a paging system with the page table stored in memory. 4. 144 . if the entry is there.) 3. 1. 2. How many page faults occur for your algorithm for the following reference string. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 9. 3. for four page frames? 1. 5.)If we add associative registers. how would each of the First-?t. 500K. 4. 7. 5. by Parul Arora. 2. a.)If a memory reference takes 200 nanoseconds. and Worst-?t algorithms place processes of 212K. 6. and 75 percent of all pagetable references are found in the associative registers. New Delhi-63. 5. 4. 200K. 8. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. to determine which page is victim. U1. 7. 7. 112K. 8. 300K. List ways to implement LRU.

Donovan J.6th Ed. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 2001 • "Operating Systems” Tannenbaum PHI.... by Parul Arora.2001 • Madnick E.Recommended reading • Silbersachatz and Galvin. U1. New Delhi-63. “Operating System Concepts” Peason. 145 . 4th Edition. ”Operating System”: TMH.

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