OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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. by Parul Arora. a program. 4 . New Delhi-63.Learning Objective Understand the purpose of the operating system Distinguish between a resource. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 5 . by Parul Arora.

New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. • Operating system goals: Execute user programs and make solving user problems easier.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. by Parul Arora. 6 . Make the computer system convenient to use. • Use the computer hardware in an efficient manner.

Users (people. other computers). New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. 3. memory.. by Parul Arora. machines. 4. video games. Hardware – provides basic computing resources (CPU. database systems. I/O devices). Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. 7 .Computer System Components 1. 2. business programs).

U1.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 8 . by Parul Arora.

by Parul Arora..Operating System Definitions • Resource allocator – manages and allocates resources. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 9 . • Kernel – the one program running at all times (all else being application programs). New Delhi-63. • Control program – controls the execution of user programs and operations of I/O devices . U1.

New Delhi-63..Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 10 . U1.

New Delhi-63. 11 . by Parul Arora.. First rudimentary operating system.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. U1. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 12 . New Delhi-63. U1..

13 .Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. by Parul Arora.

by Parul Arora. • Allocation of devices. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • CPU scheduling – the system must choose among several jobs ready to run. U1. • Memory management – the system must allocate the memory to several jobs.. 14 .OS Features Needed for Multiprogramming • I/O routine supplied by the system.

Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). U1.. New Delhi-63. by Parul Arora. when the operating system finishes the execution of one command. . A job swapped in and out of memory to the disk. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. On-line communication between the user and the system is provided. it seeks the next “control statement” from the user’s keyboard.

U1. UNIX. New Delhi-63. • May run several different types of operating systems (Windows. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. mice.. display screens. • User convenience and responsiveness. 16 .Desktop Systems • Personal computers – computer system dedicated to a single user. MacOS. • I/O devices – keyboards. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. small printers.

Parallel Systems • Multiprocessor systems with more than on CPU in close communication. • Tightly coupled system – processors share memory and a clock. 17 . communication usually takes place through the shared memory. New Delhi-63. by Parul Arora. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. master processor schedules and allocated work to slave processors. by Parul Arora. Many processes can run at once without performance deterioration. New Delhi-63..) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system.Parallel Systems (Cont. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. 18 . U1.

U1.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 19 . by Parul Arora..

New Delhi-63. by Parul Arora.Distributed Systems • Distribute the computation among several physical processors. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. processors communicate with one another through various communications lines. • Loosely coupled system – each processor has its own local memory. • Advantages of distributed systems. 20 . such as high-speed buses or telephone lines. U1..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.Distributed Systems (cont) • Requires networking infrastructure. by Parul Arora.. U1. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems. New Delhi-63. 21 .

by Parul Arora. 22 . U1.. New Delhi-63.General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.. U1. New Delhi-63. • Asymmetric clustering: one server runs the application while other servers standby. • Symmetric clustering: all N hosts are running the application. 23 .Clustered Systems • Clustering allows two or more systems to share storage. • Provides high reliability. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. medical imaging systems.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. 24 . U1. New Delhi-63. • Well-defined fixed-time constraints. industrial control systems. • Real-Time systems may be either hard or soft real-time. by Parul Arora. and some display systems.

or read-only memory (ROM) Conflicts with time-sharing systems.) • Hard real-time: Secondary storage limited or absent. virtual reality) requiring advanced operating-system features. . 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Real-Time Systems (Cont. New Delhi-63. by Parul Arora. not supported by general-purpose operating systems.. data stored in short term memory. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.

. by Parul Arora.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. 26 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

U1. by Parul Arora. 27 . New Delhi-63.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

U1.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. by Parul Arora. 28 .

New Delhi-63.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1. 29 .

30 . New Delhi-63.how memory is structured Memory management .strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .

by Parul Arora.. U1. New Delhi-63. 31 .Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.Background • Program must be brought into memory and placed within a process for it to be run. • User programs go through several steps before being run. New Delhi-63. 32 . U1.

New Delhi-63. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. 33 . absolute code can be generated. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.g.. must recompile code if starting location changes.. base and limit registers). • Load time: Must generate relocatable code if memory location is not known at compile time. Need hardware support for address maps (e. by Parul Arora.

.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 34 . U1.

also referred to as virtual address. U1. 35 .Logical vs. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. by Parul Arora. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Physical address – address seen by the memory unit. Logical address – generated by the CPU. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. logical (virtual) and physical addresses differ in execution-time address-binding scheme.

36 . U1.Memory-Management Unit • Hardware device that maps virtual to physical address.. • The user program deals with logical addresses. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. it never sees the real physical addresses. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • In MMU scheme.

37 . New Delhi-63.Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. by Parul Arora.

by Parul Arora. • No special support from the operating system is required implemented through program design. U1.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. 38 . New Delhi-63.. unused routine is never loaded. • Useful when large amounts of code are needed to handle infrequently occurring cases. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. used to locate the appropriate memory-resident library routine. 39 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Stub replaces itself with the address of the routine. • Small piece of code. • Dynamic linking is particularly useful for libraries. stub. New Delhi-63. and executes the routine. • Operating system needed to check if routine is in processes’ memory address.. by Parul Arora.Dynamic Linking • Linking postponed until execution time.

Overlays • Keep in memory only those instructions and data that are needed at any given time. no special support needed from operating system. New Delhi-63.. 40 . • Implemented by user. U1. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Needed when process is larger than amount of memory allocated to it.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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U1. User processes then held in high memory. Relocation register contains value of smallest physical address. limit register contains range of logical addresses – each logical address must be less than the limit register. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. and from changing operating-system code and data. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. usually held in low memory with interrupt vector. 44 .Contiguous Allocation • Main memory usually into two partitions: Resident operating system.

Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 45 .. New Delhi-63.

Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 46 .Contiguous Allocation (Cont. by Parul Arora. New Delhi-63. holes of various size are scattered throughout memory. U1..) Multiple-partition allocation Hole – block of available memory. it is allocated memory from a hole large enough to accommodate it. When a process arrives.

Worst-fit: Allocate the largest hole. New Delhi-63. Produces the smallest leftover hole. by Parul Arora.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. unless ordered by size.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Best-fit: Allocate the smallest hole that is big enough. must search entire list. Produces the largest leftover hole. must also search entire list. 47 .

.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. by Parul Arora. New Delhi-63. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. this size difference is memory internal to a partition. Do I/O only into OS buffers. Compaction is possible only if relocation is dynamic. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. I/O problem Latch job in memory while it is involved in I/O. but not being used. 48 . but it is not contiguous. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. and is done at execution time.

• Set up a page table to translate logical to physical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Paging • Logical address space of a process can be noncontiguous. between 512 bytes and 8192 bytes). • To run a program of size n pages. • Internal fragmentation. need to find n free frames and load program. by Parul Arora. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. • Keep track of all free frames. U1. 49 . • Divide logical memory into blocks of same size called pages. process is allocated physical memory whenever the latter is available. New Delhi-63..

Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. U1. by Parul Arora. 50 .

Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 51 . New Delhi-63. U1.. by Parul Arora.

. U1. 52 . by Parul Arora.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.. U1. 53 .

U1. 54 . by Parul Arora.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

55 . • In this scheme every data/instruction access requires two memory accesses. • Page-table base register (PTBR) points to the page table. U1.Implementation of Page Table • Page table is kept in main memory. • Page-table length register (PRLR) indicates size of the page table. One for the page table and one for the data/instruction. by Parul Arora. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. 56 . U1. New Delhi-63. A´´) If A´ is in associative register. by Parul Arora. get frame # out. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

U1.Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 57 . by Parul Arora.. New Delhi-63.

. 58 . Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ration related to number of associative registers. New Delhi-63. by Parul Arora.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. U1.

by Parul Arora. and is thus a legal page. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. “invalid” indicates that the page is not in the process’ logical address space. New Delhi-63.Memory Protection • Memory protection implemented by associating protection bit with each frame. 59 .

U1. 60 . by Parul Arora.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

New Delhi-63.. 61 . U1.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

• A simple technique is a two-level page table.Hierarchical Page Tables • Break up the logical address space into multiple page tables. 62 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. by Parul Arora. U1.

Since the page table is paged. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. U1. a page offset consisting of 12 bits.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. the page number is further divided into: Thus. a 10-bit page offset. by Parul Arora. 63 .. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

. by Parul Arora.Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 64 .

U1. New Delhi-63.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 65 .

If a match is found. by Parul Arora.Hashed Page Tables • Common in address spaces > 32 bits. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. This page table contains a chain of elements hashing to the same location. the corresponding physical frame is extracted. • Virtual page numbers are compared in this chain searching for a match. • The virtual page number is hashed into a page table. 66 .

Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 67 . by Parul Arora.. New Delhi-63. U1.

• Use hash table to limit the search to one — or at most a few — page-table entries. 68 . but increases time needed to search the table when a page reference occurs. by Parul Arora.Inverted Page Table • One entry for each real page of memory. with information about the process that owns that page.. • Decreases memory needed to store each page table. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Entry consists of the virtual address of the page stored in that real memory location. U1.

. U1. New Delhi-63.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 69 . by Parul Arora.

compilers. New Delhi-63. text editors. Private code and data Each process keeps a separate copy of the code and data.. 70 .. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. The pages for the private code and data can appear anywhere in the logical address space. window systems). Shared code must appear in same location in the logical address space of all processes. U1.e.

Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 71 .. U1. New Delhi-63. by Parul Arora.

A segment is a logical unit such as: main program. A program is a collection of segments. local variables. object. by Parul Arora. New Delhi-63. stack. function.. global variables. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. symbol table. procedure. common block. U1.Segmentation Memory-management scheme that supports user view of memory. method. 72 .

New Delhi-63. U1.. by Parul Arora. 73 .User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

74 . U1. New Delhi-63. by Parul Arora..Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. • • • Segment-table base register (STBR) points to the segment table’s location in memory. each table entry has: base – contains the starting physical address where the segments reside in memory. New Delhi-63. offset>. 75 . Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. Segment table – maps two-dimensional physical addresses. limit – specifies the length of the segment.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 76 . dynamic by segment table • Sharing..Segmentation Architecture (Cont. by Parul Arora. New Delhi-63. U1. shared segments same segment number • Allocation.) • Relocation.

. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. by Parul Arora. 77 . U1. New Delhi-63.) • Protection. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Architecture (Cont. code sharing occurs at segment level. • Since segments vary in length. memory allocation is a dynamic storage-allocation problem.

New Delhi-63.. 78 . by Parul Arora.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 79 . U1.

Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. 80 . New Delhi-63..

Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. New Delhi-63. but rather the base address of a page table for this segment. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora. 81 .

U1. by Parul Arora. New Delhi-63. 82 ..MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. New Delhi-63.Segmentation with Paging – Intel 386 As shown in the following diagram. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 83 .

84 . by Parul Arora.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63..

Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 85 . New Delhi-63. by Parul arora U1.

Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. by Parul Arora. auxiliary memory) and processor speed. • Discuss the concept of thrashing. 86 . • Evaluate the trade-offs in terms of memory size (main memory. cache memory. • Summarize the principles of virtual memory as applied to caching and paging.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. • Describe the reason for and use of cache memory. U1.

New Delhi-63. • Virtual memory can be implemented via: Demand paging Demand segmentation U1.Background • Virtual memory – separation of user logical memory from physical memory. by Parul Arora. . Allows for more efficient process creation.. Only part of the program needs to be in memory for execution. Allows address spaces to be shared by several processes. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Logical address space can therefore be much larger than physical address space.

. U1. New Delhi-63. 88 . by Parul Arora.Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

.Demand Paging Bring a page into memory only when it is needed. by Parul Arora. New Delhi-63. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 89 . U1.

New Delhi-63. 90 . U1..Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

91 .Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. by Parul Arora. New Delhi-63.. but valid-invalid bit 1 Example of a page table snapshot. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

. 92 . by Parul Arora.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

New Delhi-63.Page Fault • If there is ever a reference to a page. Reset tables. . Just not in memory.. validation bit = 1. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. • • • • Get empty frame. Restart instruction: Least Recently Used block move U1. by Parul Arora. Swap page into frame. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. U1.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 94 ..

algorithm performance – want an algorithm which will result in minimum number of page faults. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Same page may be brought into memory several times. but not really in use. by Parul Arora.. swap it out.What happens if there is no free frame? • Page replacement – find some page in memory. 95 . U1.

0 if p = 0 no page faults if p = 1. 96 . New Delhi-63.. by Parul Arora. U1.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. 97 .. Swap Page Time = 10 msec = 10. U1. New Delhi-63.

New Delhi-63.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 98 ..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. only then is the page copied. • Free pages are allocated from a pool of zeroed-out pages. • COW allows more efficient process creation as only modified pages are copied.. U1.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. 99 .If either process modifies a shared page. by Parul Arora. New Delhi-63.

.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. U1. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • A file is initially read using demand paging. New Delhi-63. A page-sized portion of the file is read from the file system into a physical page. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. by Parul Arora. • Also allows several processes to map the same file allowing the pages in memory to be shared. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. .

Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 101 .. by Parul Arora. U1.

U1. 102 . by Parul Arora. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement.

. New Delhi-63. 103 . U1. by Parul Arora.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. use it. 104 .. . • Read the desired page into the (newly) free frame. by Parul Arora.If there is a free frame.Basic Page Replacement • Find the location of the desired page on disk. • Find a free frame: . U1. • Restart the process.If there is no free frame. Update the page and frame tables. use a page replacement algorithm to select a victim frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 105 . by Parul Arora. New Delhi-63.

5. 2. 106 . In all our examples. by Parul Arora. 3. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. New Delhi-63. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 3.. 2. 5.Page Replacement Algorithms Want lowest page-fault rate. 1. the reference string is 1. 2. U1. 1. 4.

by Parul Arora. U1.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 107 ..

2. U1. 108 . by Parul Arora. 4. 3.. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 2. 1. 5.First-In-First-Out (FIFO) Algorithm Reference string: 1. 2. 3. 1. 4.

U1. 109 .First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora..

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 113 .. by Parul Arora. New Delhi-63. U1.

5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. 3. 3.Least Recently Used (LRU) Algorithm Reference string: 1. 4. copy the clock into the counter. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. every time page is referenced through this entry. 4. look at the counters to determine which are to change. 5. 114 . 2. by Parul Arora. When a page needs to be changed. New Delhi-63.. U1. 1. 1. 2.

LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 115 . New Delhi-63. by Parul Arora. U1.

116 .) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1.LRU Algorithm (Cont.

117 .Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1.

however. initially = 0 When page is referenced bit set to 1. We do not know the order. replace next page (in clock order). by Parul Arora. leave page in memory.. If page to be replaced (in clock order) has reference bit = 1. Clock replacement. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. then: set reference bit 0. U1. Second chance Need reference bit. New Delhi-63. rules.LRU Approximation Algorithm Reference bit With each page associate a bit. Replace the one which is 0 (if one exists). 118 .

by Parul Arora. 119 . U1..Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

.Counting Algorithms • Keep a counter of the number of references that have been made to each page. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 120 . U1. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. New Delhi-63. by Parul Arora. LFU Algorithm: replaces page with smallest count.

• Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. New Delhi-63. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2 pages to handle to. 2 pages to handle from. • Two major allocation schemes. 121 . might span 2 pages.. by Parul Arora.Allocation of Frames • Each process needs minimum number of pages. U1.

. New Delhi-63. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. if 100 frames and 5 processes..g. U1. by Parul Arora.Fixed Allocation • Equal allocation – e. • Proportional allocation – Allocate according to the size of process. 122 . give each 20 pages.

. New Delhi-63. U1. select for replacement a frame from a process with lower priority number. by Parul Arora. • If process Pi generates a page fault. 123 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. select for replacement one of its frames.Priority Allocation • Use a proportional allocation scheme using priorities rather than size.

by Parul Arora. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames. U1. New Delhi-63. 124 .Global vs.. one process can take a frame from another. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Local replacement – each process selects from only its own set of allocated frames.

U1.Thrashing If a process does not have “enough” pages. New Delhi-63. operating system thinks that it needs to increase the degree of multiprogramming. 125 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. the page-fault rate is very high. another process added to the system.. Thrashing ≡ a process is busy swapping pages in and out. This leads to: low CPU utilization.

New Delhi-63. U1. by Parul Arora.Thrashing Why does paging work? Locality model Process migrates from one locality to another. Localities may overlap. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 126 .

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

If actual rate too low. 130 .Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. process loses frame. process gains frame. If actual rate too high. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.. New Delhi-63.

131 .Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. U1. New Delhi-63.

the working set of each process is stored in the TLB. U1. New Delhi-63. by Parul Arora.) TLB Reach .Other Considerations (Cont.The amount of memory accessible from the TLB.. 132 . Otherwise there is a high degree of page faults. TLB Reach = (TLB Size) X (Page Size) Ideally. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63.Increasing the Size of the TLB • Increase the Page Size. 133 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. • Provide Multiple Page Sizes. This may lead to an increase in fragmentation as not all applications require a large page size. U1. by Parul Arora.

i++) A[i. by Parul Arora.length.j] = 0.Other Considerations (Cont. j < A. 134 . i < A. U1. i++) for (j = 0. New Delhi-63.length. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management..) Program structure int A[][] = new int[1024][1024]. 1024 x 1024 page faults Program 2 for (i = 0. j < A.length. j++) A[i. Each row is stored in one page Program 1 for (j = 0.length. i < A. j++) for (i = 0.j] = 0.

and also allows degree of multiprogramming to be raised. Virtual memory allows extremely large processes to be run. Multiprogramming increased the performance of computer system. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. .Conclusion • • • • • Operating systems provide an environment for development and execution of programs. New Delhi-63. Virtual memory frees application programers from worrying about memory availability U1. Memory management algorithms differ in many concepts.

• • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. Policies for determining which pages to load and remove from memory include Random Replacement. timesharing. Resources are any objects that can be allocated within a system. we saw that software can be roughly divided into two groups: application software and system software. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . Operating systems are a type of system software that allow applications to interface with computer hardware. First In First Out. and Least Frequently U1. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. 136 Used. Least Recently Used. by Parul Arora. and the operating system is responsible for managing them.. Four major categories of operating systems are batch. Second Chance. personal computing and dedicated.Summary • In the introduction.

U1. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 1. 137 . a) Polling b) Interrupt c) System Call d) None of the above 2. by Parul Arora.. New Delhi-63. The Hardware mechanism that enables a device to notify the CPU is called __________.

New Delhi-63.. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Virtual memory is __________. U1.Review Questions (OBJ) 3. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. 138 . by Parul Arora. 4.

a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. U1.. 139 . The term " Operating System " means ________. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6.Review Questions (OBJ) 5.

The main program is loaded into memory & is executed. U1. New Delhi-63. All routines are kept on disk in a relocatable load format.. by Parul Arora. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 7. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. The principle of locality of reference justifies the use of ________. ) Routine a) b) c) d) is not loaded until it is called. 140 .

141 . If all page frames are initially empty. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. New Delhi-63. the total number of page faults caused by the process will be __________. ) The problem of thrashing is effected scientifically by ________. a) Program structure b) Program size c) Primary storage size d) None of the above U1. a) 10 b) 7 c) 8 d) 9 10. by Parul Arora.Review Questions (OBJ) 9.

by Parul Arora.Review Questions (Short) 1. New Delhi-63. 142 . How does a real-time system differ from time-share? 8. How do MULTICS and UNIX differ? 7. Explain the difference between internal and external fragmentation 10. U1. Explain the difference between logical and physical addresses. What are the main differences between operating systems for mainframe computers and personal computers? 3.. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What are the three main purposes of an operating system? 4. 9. How do I/O-bound and CPU-bound programs differ? 6. What is the main advantage of multiprogramming 2. List the four steps that are necessary to run a program on a completely dedicated machine 5.

by Parul Arora. 143 . How was memory mapping used in extending the usefulness of minicomputers? 13.Review Questions (Short) 11. When do page faults occur? 15. What is Belady’s anomaly? 19. New Delhi-63. What is meant by locality? 21. U1. 16. What are overlays? 12. What is virtual memory? 17.. Describe the actions taken by the operating system when a page fault occurs. Why is there a valid/invalid bit? Where is it kept? 18. How do global and local allocation differ? 20. What is reentrant code? 14. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

5. to determine which page is victim. 7. New Delhi-63. 5. if the entry is there. 112K. how long does a paged memory reference take? b. 500K. 144 . 2. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 8. U1. List ways to implement LRU. Best-?t. and 75 percent of all pagetable references are found in the associative registers. and 600K (in order).)If we add associative registers. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 4. 6. 8. for four page frames? 1. 4. 2. 9. 7. 3. and Worst-?t algorithms place processes of 212K. 5. Consider a paging system with the page table stored in memory. how would each of the First-?t. 200K. 8. 4. 417K. How many page faults occur for your algorithm for the following reference string. 1. 4.Review Questions (Long) 1. 7. 3. Given memory partitions of 100K.. 300K. 9.) 3. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.)If a memory reference takes 200 nanoseconds. 4. a.

U1.. 2001 • "Operating Systems” Tannenbaum PHI. by Parul Arora. ”Operating System”: TMH. 145 .6th Ed. “Operating System Concepts” Peason. New Delhi-63. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Recommended reading • Silbersachatz and Galvin..2001 • Madnick E. Donovan J.. 4th Edition.

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