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Sections

  • Introduction
  • What is an Operating System?
  • Computer System Components
  • Operating System Definitions
  • Operating System View
  • Mainframe Systems
  • Desktop Systems
  • Parallel Systems
  • Parallel Systems (Cont.)
  • Distributed Systems
  • Distributed Systems (cont)
  • Clustered Systems
  • Real-Time Systems
  • Real-Time Systems (Cont.)
  • Handheld Systems
  • Computing Environments
  • Learning Objective
  • Memory Management
  • Background
  • Dynamic Loading
  • Dynamic Linking
  • Overlays
  • Swapping
  • Schematic View of Swapping
  • Contiguous Allocation
  • Contiguous Allocation (Cont.)
  • Fragmentation
  • Paging
  • Address Translation Scheme
  • Free Frames
  • Implementation of Page Table
  • Associative Memory
  • Paging Hardware With TLB
  • Effective Access Time
  • Memory Protection
  • Page Table Structure
  • Hierarchical Page Tables
  • Two-Level Paging Example
  • Two-Level Page-Table Scheme
  • Address-Translation Scheme
  • Hashed Page Tables
  • Hashed Page Table
  • Inverted Page Table
  • Shared Pages
  • Shared Pages Example
  • Segmentation
  • User’s View of a Program
  • Logical View of Segmentation
  • Segmentation Architecture
  • Segmentation Hardware
  • Example of Segmentation
  • Sharing of Segments
  • Learning Objectives
  • Demand Paging
  • Valid-Invalid Bit
  • Page Fault
  • Steps in Handling a Page Fault
  • Performance of Demand Paging
  • Demand Paging Example
  • Process Creation
  • Copy-on-Write
  • Memory-Mapped Files
  • Memory Mapped Files
  • Page Replacement
  • Need For Page Replacement
  • Basic Page Replacement
  • Page Replacement Algorithms
  • FIFO Page Replacement
  • Optimal Algorithm
  • Optimal Page Replacement
  • LRU Page Replacement
  • LRU Algorithm (Cont.)
  • LRU Approximation Algorithm
  • Counting Algorithms
  • Allocation of Frames
  • Fixed Allocation
  • Priority Allocation
  • Global vs. Local Allocation
  • Working-Set Model
  • Working-set model
  • Page-Fault Frequency Scheme
  • Other Considerations
  • Increasing the Size of the TLB
  • Conclusion
  • Summary

OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 1

Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 2

Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 3

and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1.Learning Objective Understand the purpose of the operating system Distinguish between a resource. 4 . a program..

U1. by Parul Arora.. New Delhi-63.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5 .

U1. Make the computer system convenient to use. • Use the computer hardware in an efficient manner.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. • Operating system goals: Execute user programs and make solving user problems easier. 6 .

. New Delhi-63. business programs). Hardware – provides basic computing resources (CPU. by Parul Arora. 7 . U1. memory. database systems.Computer System Components 1. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. Users (people. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. other computers). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. I/O devices). video games. 4. machines. 3.

by Parul Arora.. New Delhi-63.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 8 . U1.

Operating System Definitions • Resource allocator – manages and allocates resources. by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Control program – controls the execution of user programs and operations of I/O devices . • Kernel – the one program running at all times (all else being application programs). 9 . U1. New Delhi-63.

U1.. 10 . by Parul Arora. New Delhi-63.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

First rudimentary operating system. by Parul Arora.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 11 . New Delhi-63.

New Delhi-63. U1. 12 .Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.

Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 13 . U1. New Delhi-63.. by Parul Arora.

. • Memory management – the system must allocate the memory to several jobs. U1. by Parul Arora. 14 . • Allocation of devices. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • CPU scheduling – the system must choose among several jobs ready to run. New Delhi-63.OS Features Needed for Multiprogramming • I/O routine supplied by the system.

. by Parul Arora. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. when the operating system finishes the execution of one command.. U1. A job swapped in and out of memory to the disk. New Delhi-63.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). On-line communication between the user and the system is provided. it seeks the next “control statement” from the user’s keyboard.

New Delhi-63.. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. • I/O devices – keyboards. 16 . MacOS. U1. • User convenience and responsiveness. mice. display screens. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. UNIX.Desktop Systems • Personal computers – computer system dedicated to a single user. small printers. • May run several different types of operating systems (Windows.

• Tightly coupled system – processors share memory and a clock. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. communication usually takes place through the shared memory. 17 . by Parul Arora. U1.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. New Delhi-63..

More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. New Delhi-63. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. by Parul Arora..Parallel Systems (Cont. Many processes can run at once without performance deterioration. U1. master processor schedules and allocated work to slave processors. 18 .

Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 19 . U1..

such as high-speed buses or telephone lines. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. • Loosely coupled system – each processor has its own local memory. processors communicate with one another through various communications lines.. • Advantages of distributed systems.Distributed Systems • Distribute the computation among several physical processors. by Parul Arora. 20 .

by Parul Arora. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.Distributed Systems (cont) • Requires networking infrastructure.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 21 .

22 . by Parul Arora. New Delhi-63..General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63. • Symmetric clustering: all N hosts are running the application. • Provides high reliability. 23 . • Asymmetric clustering: one server runs the application while other servers standby..Clustered Systems • Clustering allows two or more systems to share storage. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

• Real-Time systems may be either hard or soft real-time. 24 . medical imaging systems. and some display systems. U1. • Well-defined fixed-time constraints. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments.. industrial control systems. New Delhi-63. by Parul Arora.

virtual reality) requiring advanced operating-system features.) • Hard real-time: Secondary storage limited or absent. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. . not supported by general-purpose operating systems. data stored in short term memory. U1. by Parul Arora.Real-Time Systems (Cont. New Delhi-63. or read-only memory (ROM) Conflicts with time-sharing systems.. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. 26 .

by Parul Arora..Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 27 . New Delhi-63. U1.

by Parul Arora.. U1. 28 . New Delhi-63.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. by Parul arora U1.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 29 .

strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 30 . U1.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .. by Parul Arora.how memory is structured Memory management . New Delhi-63.

. U1. by Parul Arora. New Delhi-63. 31 .Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. • User programs go through several steps before being run.Background • Program must be brought into memory and placed within a process for it to be run. 32 . • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. by Parul Arora. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. New Delhi-63. must recompile code if starting location changes. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. absolute code can be generated. • Load time: Must generate relocatable code if memory location is not known at compile time. Need hardware support for address maps (e.. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. base and limit registers).Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.g. by Parul Arora. 33 . U1.

U1. by Parul Arora.. 34 . New Delhi-63.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.. logical (virtual) and physical addresses differ in execution-time address-binding scheme. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 35 . Physical address – address seen by the memory unit.Logical vs. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Logical address – generated by the CPU. also referred to as virtual address. U1. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. New Delhi-63.

U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • The user program deals with logical addresses. 36 . the value in the relocation register is added to every address generated by a user process at the time it is sent to memory..Memory-Management Unit • Hardware device that maps virtual to physical address. • In MMU scheme. it never sees the real physical addresses. New Delhi-63.

New Delhi-63. 37 .Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora..

Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. • No special support from the operating system is required implemented through program design. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. by Parul Arora.. 38 . • Useful when large amounts of code are needed to handle infrequently occurring cases. unused routine is never loaded.

stub. 39 .. and executes the routine. by Parul Arora.Dynamic Linking • Linking postponed until execution time. • Operating system needed to check if routine is in processes’ memory address. used to locate the appropriate memory-resident library routine. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Dynamic linking is particularly useful for libraries. New Delhi-63. • Stub replaces itself with the address of the routine. • Small piece of code.

programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Implemented by user. U1. by Parul Arora. New Delhi-63. no special support needed from operating system. 40 . • Needed when process is larger than amount of memory allocated to it..Overlays • Keep in memory only those instructions and data that are needed at any given time.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 41

Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 42

Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 43

usually held in low memory with interrupt vector. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Relocation register contains value of smallest physical address. by Parul Arora.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. limit register contains range of logical addresses – each logical address must be less than the limit register. 44 . • Single-partition allocation Relocation-register scheme used to protect user processes from each other. User processes then held in high memory.. and from changing operating-system code and data. U1.

. 45 . U1. New Delhi-63.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

. U1. New Delhi-63. holes of various size are scattered throughout memory. by Parul Arora.) Multiple-partition allocation Hole – block of available memory. 46 . Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. it is allocated memory from a hole large enough to accommodate it.Contiguous Allocation (Cont. When a process arrives.

U1.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. must search entire list. New Delhi-63. must also search entire list. Produces the smallest leftover hole.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. Produces the largest leftover hole. 47 . unless ordered by size. Best-fit: Allocate the smallest hole that is big enough. Worst-fit: Allocate the largest hole.

by Parul Arora.. Compaction is possible only if relocation is dynamic. New Delhi-63. but it is not contiguous. this size difference is memory internal to a partition. and is done at execution time. I/O problem Latch job in memory while it is involved in I/O. but not being used. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. 48 .Fragmentation • External Fragmentation – total memory space exists to satisfy a request. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. Do I/O only into OS buffers. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. • Divide logical memory into blocks of same size called pages. New Delhi-63.Paging • Logical address space of a process can be noncontiguous. need to find n free frames and load program. • Keep track of all free frames. 49 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Set up a page table to translate logical to physical addresses. between 512 bytes and 8192 bytes). process is allocated physical memory whenever the latter is available. • Internal fragmentation. • To run a program of size n pages.. • Divide physical memory into fixed-sized blocks called frames (size is power of 2.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. by Parul Arora. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. New Delhi-63. 50 .

by Parul Arora. U1.Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 51 . New Delhi-63.

New Delhi-63. U1.. 52 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

by Parul Arora. U1. New Delhi-63. 53 ..Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

54 . by Parul Arora.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63.

• Page-table length register (PRLR) indicates size of the page table. • In this scheme every data/instruction access requires two memory accesses.Implementation of Page Table • Page table is kept in main memory. • Page-table base register (PTBR) points to the page table. One for the page table and one for the data/instruction. 55 . New Delhi-63. U1.. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. get frame # out. 56 . New Delhi-63. by Parul Arora.. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A´´) If A´ is in associative register. U1.

U1. New Delhi-63. by Parul Arora..Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 57 .

by Parul Arora. 58 . New Delhi-63.. ration related to number of associative registers. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. U1.

and is thus a legal page. “invalid” indicates that the page is not in the process’ logical address space. U1. 59 . • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. by Parul Arora. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Memory Protection • Memory protection implemented by associating protection bit with each frame.

. New Delhi-63. U1.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 60 . by Parul Arora.

61 .. U1. New Delhi-63.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

62 . New Delhi-63.Hierarchical Page Tables • Break up the logical address space into multiple page tables. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. • A simple technique is a two-level page table.

New Delhi-63. by Parul Arora.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. Since the page table is paged. a page offset consisting of 12 bits. a 10-bit page offset. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. the page number is further divided into: Thus. 63 ..

64 . U1..Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

U1.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 65 .. by Parul Arora. New Delhi-63.

the corresponding physical frame is extracted. 66 .Hashed Page Tables • Common in address spaces > 32 bits.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Virtual page numbers are compared in this chain searching for a match. • The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. by Parul Arora. New Delhi-63. If a match is found. U1.

. 67 . by Parul Arora.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

. • Entry consists of the virtual address of the page stored in that real memory location. but increases time needed to search the table when a page reference occurs. • Use hash table to limit the search to one — or at most a few — page-table entries. • Decreases memory needed to store each page table. U1. 68 . with information about the process that owns that page. New Delhi-63.Inverted Page Table • One entry for each real page of memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

by Parul Arora.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 69 . New Delhi-63.

text editors.e. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1. The pages for the private code and data can appear anywhere in the logical address space. Shared code must appear in same location in the logical address space of all processes. Private code and data Each process keeps a separate copy of the code and data.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. window systems). compilers. 70 ...

U1..Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 71 .

symbol table. object. function. A segment is a logical unit such as: main program. U1.Segmentation Memory-management scheme that supports user view of memory.. stack. 72 . by Parul Arora. global variables. New Delhi-63. A program is a collection of segments. local variables. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. method. procedure. common block.

73 . New Delhi-63.. U1. by Parul Arora.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. New Delhi-63.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 74 . U1..

U1. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. • • • Segment-table base register (STBR) points to the segment table’s location in memory.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. Segment table – maps two-dimensional physical addresses. by Parul Arora. limit – specifies the length of the segment. offset>. New Delhi-63.. each table entry has: base – contains the starting physical address where the segments reside in memory. 75 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

76 .. U1. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Architecture (Cont. New Delhi-63. dynamic by segment table • Sharing. by Parul Arora. shared segments same segment number • Allocation.) • Relocation.

Segmentation Architecture (Cont. 77 . With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. by Parul Arora. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. memory allocation is a dynamic storage-allocation problem.) • Protection. • Since segments vary in length. code sharing occurs at segment level..

by Parul Arora. New Delhi-63. U1.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 78 .

.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 79 . U1. by Parul Arora.

. New Delhi-63. 80 .Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.. 81 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. New Delhi-63. by Parul Arora. but rather the base address of a page table for this segment.

. U1.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 82 . New Delhi-63. by Parul Arora.

U1. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. 83 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation with Paging – Intel 386 As shown in the following diagram. New Delhi-63. by Parul Arora.

New Delhi-63. 84 .Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora.

Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 85 . by Parul arora U1. New Delhi-63.

Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. • Describe the reason for and use of cache memory. • Evaluate the trade-offs in terms of memory size (main memory. cache memory. auxiliary memory) and processor speed. by Parul Arora. • Summarize the principles of virtual memory as applied to caching and paging. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. • Discuss the concept of thrashing.. U1. 86 . New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Virtual memory can be implemented via: Demand paging Demand segmentation U1.Background • Virtual memory – separation of user logical memory from physical memory. Only part of the program needs to be in memory for execution. New Delhi-63.. Allows for more efficient process creation. Allows address spaces to be shared by several processes. by Parul Arora. . Logical address space can therefore be much larger than physical address space.

. by Parul Arora. New Delhi-63.Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 88 .

U1. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Demand Paging Bring a page into memory only when it is needed. by Parul Arora. 89 ..

by Parul Arora. 90 .Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63..

Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.. but valid-invalid bit 1 Example of a page table snapshot. U1. 91 . New Delhi-63.

U1. by Parul Arora. 92 .. New Delhi-63.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Just not in memory.Page Fault • If there is ever a reference to a page. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort.. Swap page into frame. validation bit = 1. Reset tables. New Delhi-63. . 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Restart instruction: Least Recently Used block move U1. • • • • Get empty frame. by Parul Arora.

94 .. U1. New Delhi-63.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1. algorithm performance – want an algorithm which will result in minimum number of page faults.What happens if there is no free frame? • Page replacement – find some page in memory. New Delhi-63.. • Same page may be brought into memory several times. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. swap it out. 95 . but not really in use.

by Parul Arora.0 if p = 0 no page faults if p = 1. U1. New Delhi-63.. 96 .Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. New Delhi-63. U1. by Parul Arora. 97 .000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. Swap Page Time = 10 msec = 10.

98 . by Parul Arora.. U1. New Delhi-63.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• COW allows more efficient process creation as only modified pages are copied. • Free pages are allocated from a pool of zeroed-out pages. by Parul Arora. only then is the page copied.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.If either process modifies a shared page. 99 . U1. New Delhi-63.

U1.. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. . New Delhi-63. A page-sized portion of the file is read from the file system into a physical page.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. • A file is initially read using demand paging. • Also allows several processes to map the same file allowing the pages in memory to be shared. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

by Parul Arora. U1. New Delhi-63..Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 101 .

New Delhi-63. by Parul Arora. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.. U1.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. 102 .

103 . U1.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63.

. • Find a free frame: . New Delhi-63.If there is a free frame. • Restart the process. • Read the desired page into the (newly) free frame. by Parul Arora. use a page replacement algorithm to select a victim frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 104 . Update the page and frame tables. U1. use it. .Basic Page Replacement • Find the location of the desired page on disk.If there is no free frame.

by Parul Arora. 105 . New Delhi-63. U1.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

4. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. New Delhi-63. 2. 5. 3. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5. the reference string is 1. In all our examples. 1. 2. U1. by Parul Arora.. 3. 2. 4. 1.Page Replacement Algorithms Want lowest page-fault rate. 106 .

107 . U1.. New Delhi-63.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

New Delhi-63. 3. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 3. 2.First-In-First-Out (FIFO) Algorithm Reference string: 1. 108 . 2. 4. 4. 1. 2. U1.. 1. 5.

. 109 . New Delhi-63.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

by Parul Arora. 113 . U1. New Delhi-63..Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

4. New Delhi-63.. 4. 3. 1. 3. 114 . by Parul Arora. every time page is referenced through this entry. look at the counters to determine which are to change. U1.Least Recently Used (LRU) Algorithm Reference string: 1. copy the clock into the counter. 1. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. 2. 5. 2. 2. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. When a page needs to be changed.

LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 115 . U1.. by Parul Arora. New Delhi-63.

) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.LRU Algorithm (Cont. 116 . by Parul Arora. New Delhi-63.

New Delhi-63.. by Parul Arora.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 117 . U1.

. Clock replacement. leave page in memory. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. If page to be replaced (in clock order) has reference bit = 1. initially = 0 When page is referenced bit set to 1. New Delhi-63. Second chance Need reference bit. then: set reference bit 0. replace next page (in clock order).LRU Approximation Algorithm Reference bit With each page associate a bit. U1. however. rules. 118 . Replace the one which is 0 (if one exists). We do not know the order.

by Parul Arora.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 119 . New Delhi-63. U1.

LFU Algorithm: replaces page with smallest count. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. by Parul Arora. 120 . New Delhi-63. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..Counting Algorithms • Keep a counter of the number of references that have been made to each page.

by Parul Arora. New Delhi-63. 2 pages to handle from. U1. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. might span 2 pages. • Two major allocation schemes. 121 . • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes.. 2 pages to handle to.Allocation of Frames • Each process needs minimum number of pages.

.Fixed Allocation • Equal allocation – e. by Parul Arora. 122 .g. if 100 frames and 5 processes. U1. New Delhi-63.. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Proportional allocation – Allocate according to the size of process. give each 20 pages.

• If process Pi generates a page fault. New Delhi-63. select for replacement a frame from a process with lower priority number. U1.. 123 . select for replacement one of its frames. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. by Parul Arora.

124 . by Parul Arora. New Delhi-63. one process can take a frame from another.Global vs.. • Local replacement – each process selects from only its own set of allocated frames. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Thrashing If a process does not have “enough” pages. operating system thinks that it needs to increase the degree of multiprogramming.. the page-fault rate is very high. 125 . Thrashing ≡ a process is busy swapping pages in and out. This leads to: low CPU utilization. another process added to the system. U1. New Delhi-63.

by Parul Arora.. U1.Thrashing Why does paging work? Locality model Process migrates from one locality to another. Localities may overlap. New Delhi-63. 126 . Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

If actual rate too high.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. 130 . process gains frame.. U1. If actual rate too low. by Parul Arora. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. process loses frame.

Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 131 . by Parul Arora. New Delhi-63. U1..

Other Considerations (Cont. U1. 132 . Otherwise there is a high degree of page faults. TLB Reach = (TLB Size) X (Page Size) Ideally. the working set of each process is stored in the TLB.The amount of memory accessible from the TLB. by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.) TLB Reach .

U1.. • Provide Multiple Page Sizes. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. This may lead to an increase in fragmentation as not all applications require a large page size.Increasing the Size of the TLB • Increase the Page Size. by Parul Arora. 133 .

length. j < A.j] = 0. Each row is stored in one page Program 1 for (j = 0.length. 134 . j++) for (i = 0. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 1024 x 1024 page faults Program 2 for (i = 0. i < A. U1.length. i++) for (j = 0.) Program structure int A[][] = new int[1024][1024]. i < A.length.Other Considerations (Cont. i++) A[i. New Delhi-63. j++) A[i. by Parul Arora.j] = 0. j < A.

135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Multiprogramming increased the performance of computer system. . Virtual memory frees application programers from worrying about memory availability U1. by Parul Arora.and also allows degree of multiprogramming to be raised. New Delhi-63. Memory management algorithms differ in many concepts.Conclusion • • • • • Operating systems provide an environment for development and execution of programs.. Virtual memory allows extremely large processes to be run.

Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. Least Recently Used. and the operating system is responsible for managing them. New Delhi-63. 136 Used. we saw that software can be roughly divided into two groups: application software and system software. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. personal computing and dedicated. Second Chance.. First In First Out.Summary • In the introduction. Policies for determining which pages to load and remove from memory include Random Replacement. and Least Frequently U1. . Four major categories of operating systems are batch. timesharing. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Operating systems are a type of system software that allow applications to interface with computer hardware. Resources are any objects that can be allocated within a system.

The Hardware mechanism that enables a device to notify the CPU is called __________. 137 . by Parul Arora. U1. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 1.. New Delhi-63. a) Polling b) Interrupt c) System Call d) None of the above 2.

. New Delhi-63. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers.Review Questions (OBJ) 3. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 138 . U1. 4. by Parul Arora. Virtual memory is __________.

New Delhi-63. U1. 139 . a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 5.. The term " Operating System " means ________. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. by Parul Arora.

140 . New Delhi-63. by Parul Arora. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. All routines are kept on disk in a relocatable load format.. U1. ) Routine a) b) c) d) is not loaded until it is called.Review Questions (OBJ) 7. The main program is loaded into memory & is executed. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. The principle of locality of reference justifies the use of ________.

a) Program structure b) Program size c) Primary storage size d) None of the above U1. ) The problem of thrashing is effected scientifically by ________. the total number of page faults caused by the process will be __________.Review Questions (OBJ) 9. by Parul Arora. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. If all page frames are initially empty. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 141 . a) 10 b) 7 c) 8 d) 9 10.

What are the three main purposes of an operating system? 4. Explain the difference between internal and external fragmentation 10. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What is the main advantage of multiprogramming 2. New Delhi-63. How do I/O-bound and CPU-bound programs differ? 6. 9. by Parul Arora. List the four steps that are necessary to run a program on a completely dedicated machine 5. Explain the difference between logical and physical addresses. U1.. What are the main differences between operating systems for mainframe computers and personal computers? 3. 142 .Review Questions (Short) 1. How do MULTICS and UNIX differ? 7. How does a real-time system differ from time-share? 8.

What is Belady’s anomaly? 19. Describe the actions taken by the operating system when a page fault occurs.Review Questions (Short) 11. How do global and local allocation differ? 20. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. When do page faults occur? 15. Why is there a valid/invalid bit? Where is it kept? 18. 143 .. What are overlays? 12. How was memory mapping used in extending the usefulness of minicomputers? 13. What is meant by locality? 21. What is virtual memory? 17. What is reentrant code? 14. 16. U1. New Delhi-63. by Parul Arora.

4. U1. 6. if the entry is there. 1. how long does a paged memory reference take? b. New Delhi-63. 7. 300K. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 8. a. 9. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 2. 200K. by Parul Arora.Review Questions (Long) 1. and 75 percent of all pagetable references are found in the associative registers. 5. 417K. 9. 3. Best-?t. 4. 5. 5. how would each of the First-?t. 4. Consider a paging system with the page table stored in memory. to determine which page is victim. List ways to implement LRU.)If a memory reference takes 200 nanoseconds. 4.) 3. 3. 8. 2. 8. and 600K (in order).. How many page faults occur for your algorithm for the following reference string. Given memory partitions of 100K. 7. 500K. 144 . for four page frames? 1. 112K. 7. and Worst-?t algorithms place processes of 212K.)If we add associative registers.

6th Ed.. “Operating System Concepts” Peason.. U1. 4th Edition.2001 • Madnick E.. New Delhi-63. 145 . ”Operating System”: TMH. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. Donovan J.Recommended reading • Silbersachatz and Galvin. 2001 • "Operating Systems” Tannenbaum PHI.

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