OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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New Delhi-63. U1. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a program. by Parul Arora. 4 .Learning Objective Understand the purpose of the operating system Distinguish between a resource..

New Delhi-63.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 5 .. by Parul Arora.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. 6 . Make the computer system convenient to use.. New Delhi-63. by Parul Arora. • Use the computer hardware in an efficient manner. • Operating system goals: Execute user programs and make solving user problems easier. U1.

7 . New Delhi-63. by Parul Arora. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. U1. 2. 3. other computers). memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Computer System Components 1. I/O devices). 4. business programs).. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. database systems. video games. Hardware – provides basic computing resources (CPU. machines. Users (people.

8 .Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.. by Parul Arora.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 9 . by Parul Arora. U1.. New Delhi-63.Operating System Definitions • Resource allocator – manages and allocates resources. • Kernel – the one program running at all times (all else being application programs). • Control program – controls the execution of user programs and operations of I/O devices .

. by Parul Arora. U1. New Delhi-63. 10 .Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

11 . New Delhi-63. by Parul Arora. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. First rudimentary operating system.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. U1.

. by Parul Arora. U1.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 12 .

Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. by Parul Arora. 13 .

• Allocation of devices. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Memory management – the system must allocate the memory to several jobs.. New Delhi-63. • CPU scheduling – the system must choose among several jobs ready to run. U1. by Parul Arora.OS Features Needed for Multiprogramming • I/O routine supplied by the system. 14 .

by Parul Arora.. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). U1. New Delhi-63. . A job swapped in and out of memory to the disk. On-line communication between the user and the system is provided. it seeks the next “control statement” from the user’s keyboard. when the operating system finishes the execution of one command.

New Delhi-63. display screens. • User convenience and responsiveness. by Parul Arora.Desktop Systems • Personal computers – computer system dedicated to a single user. MacOS. 16 . U1. • I/O devices – keyboards.. • May run several different types of operating systems (Windows. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. small printers. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. UNIX. mice.

communication usually takes place through the shared memory.. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. U1. 17 . • Tightly coupled system – processors share memory and a clock.Parallel Systems • Multiprocessor systems with more than on CPU in close communication.

New Delhi-63. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Many processes can run at once without performance deterioration.. 18 . master processor schedules and allocated work to slave processors. U1. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.Parallel Systems (Cont.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. by Parul Arora.

New Delhi-63.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora. 19 .

• Advantages of distributed systems. by Parul Arora. processors communicate with one another through various communications lines. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Loosely coupled system – each processor has its own local memory. U1. such as high-speed buses or telephone lines. New Delhi-63..Distributed Systems • Distribute the computation among several physical processors. 20 .

. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems. New Delhi-63.Distributed Systems (cont) • Requires networking infrastructure. U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 21 .

General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 22 . U1. by Parul Arora.

23 . New Delhi-63. U1. • Asymmetric clustering: one server runs the application while other servers standby. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Clustered Systems • Clustering allows two or more systems to share storage.. • Symmetric clustering: all N hosts are running the application. • Provides high reliability. by Parul Arora.

Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. New Delhi-63. • Well-defined fixed-time constraints. industrial control systems. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Real-Time systems may be either hard or soft real-time. U1.. 24 . medical imaging systems. and some display systems.

data stored in short term memory. or read-only memory (ROM) Conflicts with time-sharing systems.) • Hard real-time: Secondary storage limited or absent..Real-Time Systems (Cont. U1. New Delhi-63. . virtual reality) requiring advanced operating-system features. not supported by general-purpose operating systems. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.

by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. 26 . New Delhi-63..

. by Parul Arora. U1.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 27 .

U1.. New Delhi-63. 28 .Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

by Parul arora U1. New Delhi-63.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 29 .

. U1. by Parul Arora.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . New Delhi-63.how memory is structured Memory management . 30 .strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

31 .Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63. U1.

Background • Program must be brought into memory and placed within a process for it to be run.. by Parul Arora. New Delhi-63. U1. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. 32 . • User programs go through several steps before being run. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Load time: Must generate relocatable code if memory location is not known at compile time. base and limit registers). must recompile code if starting location changes.g.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. New Delhi-63.. U1. 33 . absolute code can be generated.. Need hardware support for address maps (e. by Parul Arora. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.

by Parul Arora. New Delhi-63..Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 34 . U1.

by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Logical address – generated by the CPU. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. New Delhi-63. U1.. 35 . also referred to as virtual address. Physical address – address seen by the memory unit.Logical vs. logical (virtual) and physical addresses differ in execution-time address-binding scheme. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.

36 .Memory-Management Unit • Hardware device that maps virtual to physical address. New Delhi-63. • The user program deals with logical addresses. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. U1.. it never sees the real physical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • In MMU scheme.

U1..Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 37 .

• Useful when large amounts of code are needed to handle infrequently occurring cases. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. 38 . • No special support from the operating system is required implemented through program design.. unused routine is never loaded.

• Small piece of code. • Stub replaces itself with the address of the routine. U1. by Parul Arora. • Operating system needed to check if routine is in processes’ memory address. used to locate the appropriate memory-resident library routine. 39 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Dynamic Linking • Linking postponed until execution time. • Dynamic linking is particularly useful for libraries.. stub. and executes the routine.

U1. • Implemented by user. 40 .Overlays • Keep in memory only those instructions and data that are needed at any given time. by Parul Arora. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Needed when process is larger than amount of memory allocated to it.. New Delhi-63. no special support needed from operating system.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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U1. User processes then held in high memory. 44 . Relocation register contains value of smallest physical address. by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. limit register contains range of logical addresses – each logical address must be less than the limit register. • Single-partition allocation Relocation-register scheme used to protect user processes from each other.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. New Delhi-63. and from changing operating-system code and data. usually held in low memory with interrupt vector.

45 . by Parul Arora.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63.

Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Contiguous Allocation (Cont. When a process arrives. it is allocated memory from a hole large enough to accommodate it. by Parul Arora.) Multiple-partition allocation Hole – block of available memory. U1. New Delhi-63. 46 . holes of various size are scattered throughout memory.

Best-fit: Allocate the smallest hole that is big enough. Produces the largest leftover hole. U1. unless ordered by size.. Worst-fit: Allocate the largest hole. 47 . Produces the smallest leftover hole.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. must also search entire list. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. must search entire list.

Compaction is possible only if relocation is dynamic. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but it is not contiguous. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. this size difference is memory internal to a partition. by Parul Arora. but not being used. Do I/O only into OS buffers. U1. and is done at execution time. 48 . • Internal Fragmentation – allocated memory may be slightly larger than requested memory.Fragmentation • External Fragmentation – total memory space exists to satisfy a request.. New Delhi-63. I/O problem Latch job in memory while it is involved in I/O.

• Internal fragmentation.. between 512 bytes and 8192 bytes). by Parul Arora. U1. • To run a program of size n pages. • Divide logical memory into blocks of same size called pages.Paging • Logical address space of a process can be noncontiguous. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. need to find n free frames and load program. • Set up a page table to translate logical to physical addresses. 49 . process is allocated physical memory whenever the latter is available. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Keep track of all free frames.

by Parul Arora. New Delhi-63. U1.. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. 50 .Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

51 .Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1. New Delhi-63.

U1. by Parul Arora.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 52 .. New Delhi-63.

Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. 53 . U1.

New Delhi-63. by Parul Arora.. U1.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 54 .

55 .Implementation of Page Table • Page table is kept in main memory. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Page-table base register (PTBR) points to the page table. • In this scheme every data/instruction access requires two memory accesses. New Delhi-63. by Parul Arora. • Page-table length register (PRLR) indicates size of the page table.. One for the page table and one for the data/instruction.

get frame # out.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. A´´) If A´ is in associative register. by Parul Arora. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 56 . New Delhi-63.

U1. New Delhi-63..Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 57 . by Parul Arora.

Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 58 . U1. by Parul Arora. ration related to number of associative registers. New Delhi-63..Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.

59 . New Delhi-63. and is thus a legal page. U1.Memory Protection • Memory protection implemented by associating protection bit with each frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. “invalid” indicates that the page is not in the process’ logical address space. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space.

U1. 60 . New Delhi-63.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.

61 . New Delhi-63.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1..

U1.. by Parul Arora.Hierarchical Page Tables • Break up the logical address space into multiple page tables. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 62 . • A simple technique is a two-level page table.

by Parul Arora. U1. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the page number is further divided into: Thus. New Delhi-63. Since the page table is paged..Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a 10-bit page offset. a page offset consisting of 12 bits. 63 .

Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 64 . U1..

U1. 65 ..Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

This page table contains a chain of elements hashing to the same location. • Virtual page numbers are compared in this chain searching for a match.Hashed Page Tables • Common in address spaces > 32 bits. 66 . If a match is found. the corresponding physical frame is extracted. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora. • The virtual page number is hashed into a page table.

. 67 .Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. New Delhi-63.

U1. with information about the process that owns that page.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Decreases memory needed to store each page table. New Delhi-63. 68 . by Parul Arora. • Entry consists of the virtual address of the page stored in that real memory location.Inverted Page Table • One entry for each real page of memory. • Use hash table to limit the search to one — or at most a few — page-table entries. but increases time needed to search the table when a page reference occurs.

. New Delhi-63. U1.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 69 .

e. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. window systems).Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. Shared code must appear in same location in the logical address space of all processes.. The pages for the private code and data can appear anywhere in the logical address space.. 70 . compilers. text editors. U1. Private code and data Each process keeps a separate copy of the code and data.

New Delhi-63. U1. by Parul Arora. 71 ..Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

stack. object. procedure. common block. A program is a collection of segments. by Parul Arora. 72 . New Delhi-63. symbol table..Segmentation Memory-management scheme that supports user view of memory. local variables. global variables. function. U1. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. method. A segment is a logical unit such as: main program.

by Parul Arora.. New Delhi-63. 73 .User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63. by Parul Arora.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 74 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. New Delhi-63. U1. Segment table – maps two-dimensional physical addresses.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. limit – specifies the length of the segment. each table entry has: base – contains the starting physical address where the segments reside in memory. • • • Segment-table base register (STBR) points to the segment table’s location in memory. offset>. 75 . by Parul Arora.

dynamic by segment table • Sharing. shared segments same segment number • Allocation. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Segmentation Architecture (Cont. 76 .) • Relocation. New Delhi-63. by Parul Arora..

With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.Segmentation Architecture (Cont. 77 . New Delhi-63. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. memory allocation is a dynamic storage-allocation problem. • Since segments vary in length.) • Protection.. by Parul Arora. U1. code sharing occurs at segment level.

by Parul Arora.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 78 . New Delhi-63. U1.

. 79 . New Delhi-63. U1.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.. 80 . U1.

• Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. by Parul Arora. U1. 81 ..Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. New Delhi-63. but rather the base address of a page table for this segment. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. by Parul Arora. U1.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 82 . New Delhi-63.

Segmentation with Paging – Intel 386 As shown in the following diagram. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. 83 .

U1. by Parul Arora. 84 . New Delhi-63.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1. 85 . New Delhi-63.

• Discuss the concept of thrashing. • Summarize the principles of virtual memory as applied to caching and paging. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. • Describe the reason for and use of cache memory. auxiliary memory) and processor speed. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. U1. by Parul Arora. cache memory. • Evaluate the trade-offs in terms of memory size (main memory.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. 86 .

. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Allows address spaces to be shared by several processes. by Parul Arora. New Delhi-63. Only part of the program needs to be in memory for execution.Background • Virtual memory – separation of user logical memory from physical memory. . • Virtual memory can be implemented via: Demand paging Demand segmentation U1. Allows for more efficient process creation. Logical address space can therefore be much larger than physical address space.

by Parul Arora. U1.Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 88 .

U1. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Demand Paging Bring a page into memory only when it is needed. by Parul Arora. New Delhi-63. 89 .

by Parul Arora. New Delhi-63..Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 90 . U1.

1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. by Parul Arora. 91 . but valid-invalid bit 1 Example of a page table snapshot.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory.. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.

. New Delhi-63.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 92 . U1.

New Delhi-63. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort.. • • • • Get empty frame. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Swap page into frame. .Page Fault • If there is ever a reference to a page. validation bit = 1. by Parul Arora. Restart instruction: Least Recently Used block move U1. Reset tables. Just not in memory.

Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 94 . U1. by Parul Arora.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. algorithm performance – want an algorithm which will result in minimum number of page faults. by Parul Arora.. • Same page may be brought into memory several times. but not really in use. swap it out.What happens if there is no free frame? • Page replacement – find some page in memory. 95 .

. New Delhi-63. U1. 96 . by Parul Arora.0 if p = 0 no page faults if p = 1.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1..Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 97 . Swap Page Time = 10 msec = 10. New Delhi-63. by Parul Arora.

Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 98 . U1. by Parul Arora. New Delhi-63.

only then is the page copied. • COW allows more efficient process creation as only modified pages are copied. • Free pages are allocated from a pool of zeroed-out pages.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. U1.. by Parul Arora.If either process modifies a shared page. 99 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

U1. . • Also allows several processes to map the same file allowing the pages in memory to be shared. A page-sized portion of the file is read from the file system into a physical page.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. • A file is initially read using demand paging. by Parul Arora. New Delhi-63.. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Subsequent reads/writes to/from the file are treated as ordinary memory accesses.

by Parul Arora. New Delhi-63. 101 . U1.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

102 . by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. U1. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.

. 103 . New Delhi-63.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

• Read the desired page into the (newly) free frame. U1. by Parul Arora. • Find a free frame: . • Restart the process. New Delhi-63. 104 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. .If there is no free frame. Update the page and frame tables. use a page replacement algorithm to select a victim frame.Basic Page Replacement • Find the location of the desired page on disk.. use it.If there is a free frame.

. by Parul Arora. U1. 105 . New Delhi-63.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

4. 5. 2. 3. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the reference string is 1.Page Replacement Algorithms Want lowest page-fault rate.. 1. 3. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. New Delhi-63. 5. In all our examples. by Parul Arora. 4. 2. 2. 1. 106 .

107 .Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. New Delhi-63. by Parul Arora.

by Parul Arora. 1. 4. U1. 108 . 2. 4. 1. 3. 2. New Delhi-63. 2. 5. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..First-In-First-Out (FIFO) Algorithm Reference string: 1. 3.

109 .First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. New Delhi-63..

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

113 . New Delhi-63..Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

4. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter.Least Recently Used (LRU) Algorithm Reference string: 1. copy the clock into the counter. 3. by Parul Arora. New Delhi-63. every time page is referenced through this entry. 2.. 5. 1. U1. 2. look at the counters to determine which are to change. When a page needs to be changed. 4. 2. 114 . 1. 3. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. 115 .. by Parul Arora.LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

. by Parul Arora.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.LRU Algorithm (Cont. 116 . New Delhi-63. U1.

New Delhi-63. 117 . by Parul Arora..Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63. however. We do not know the order. then: set reference bit 0. 118 . initially = 0 When page is referenced bit set to 1. If page to be replaced (in clock order) has reference bit = 1. Replace the one which is 0 (if one exists). replace next page (in clock order). Clock replacement. Second chance Need reference bit. rules.LRU Approximation Algorithm Reference bit With each page associate a bit. leave page in memory.. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

U1.. New Delhi-63.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 119 .

New Delhi-63. LFU Algorithm: replaces page with smallest count.. 120 . MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. by Parul Arora. U1. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Counting Algorithms • Keep a counter of the number of references that have been made to each page.

2 pages to handle from.. New Delhi-63. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes.Allocation of Frames • Each process needs minimum number of pages. 121 . U1. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2 pages to handle to. might span 2 pages. • Two major allocation schemes. by Parul Arora.

. • Proportional allocation – Allocate according to the size of process. by Parul Arora. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management.g. 122 . U1. give each 20 pages.Fixed Allocation • Equal allocation – e. if 100 frames and 5 processes.. New Delhi-63.

Priority Allocation • Use a proportional allocation scheme using priorities rather than size. • If process Pi generates a page fault. select for replacement one of its frames. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 123 . New Delhi-63. by Parul Arora. select for replacement a frame from a process with lower priority number. U1..

New Delhi-63. one process can take a frame from another. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 124 . by Parul Arora. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.. • Local replacement – each process selects from only its own set of allocated frames.Global vs.

another process added to the system. the page-fault rate is very high. 125 .Thrashing If a process does not have “enough” pages. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. operating system thinks that it needs to increase the degree of multiprogramming. This leads to: low CPU utilization. Thrashing ≡ a process is busy swapping pages in and out. U1. New Delhi-63..

New Delhi-63..Thrashing Why does paging work? Locality model Process migrates from one locality to another. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Localities may overlap. by Parul Arora. 126 . U1.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. 130 .. by Parul Arora. U1. If actual rate too high. If actual rate too low. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. process loses frame. New Delhi-63. process gains frame.

U1. by Parul Arora.Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 131 . New Delhi-63..

The amount of memory accessible from the TLB. 132 .Other Considerations (Cont. by Parul Arora. Otherwise there is a high degree of page faults. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) TLB Reach . the working set of each process is stored in the TLB. U1. TLB Reach = (TLB Size) X (Page Size) Ideally..

. This may lead to an increase in fragmentation as not all applications require a large page size. 133 . New Delhi-63.Increasing the Size of the TLB • Increase the Page Size. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. by Parul Arora. • Provide Multiple Page Sizes.

length. New Delhi-63.j] = 0.length. 134 .) Program structure int A[][] = new int[1024][1024]. U1.length. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. i++) A[i. Each row is stored in one page Program 1 for (j = 0. by Parul Arora. j < A. i++) for (j = 0. 1024 x 1024 page faults Program 2 for (i = 0.j] = 0. j++) A[i. i < A. i < A. j < A..Other Considerations (Cont.length. j++) for (i = 0.

New Delhi-63. . by Parul Arora.and also allows degree of multiprogramming to be raised.. Virtual memory allows extremely large processes to be run. Memory management algorithms differ in many concepts. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Multiprogramming increased the performance of computer system. Virtual memory frees application programers from worrying about memory availability U1.Conclusion • • • • • Operating systems provide an environment for development and execution of programs.

we saw that software can be roughly divided into two groups: application software and system software. Four major categories of operating systems are batch. by Parul Arora.. Resources are any objects that can be allocated within a system. Policies for determining which pages to load and remove from memory include Random Replacement. Second Chance. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. Operating systems are a type of system software that allow applications to interface with computer hardware.Summary • In the introduction. Least Recently Used. personal computing and dedicated. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. timesharing. 136 Used. New Delhi-63. and the operating system is responsible for managing them. and Least Frequently U1. First In First Out.

New Delhi-63. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. The Hardware mechanism that enables a device to notify the CPU is called __________.. 137 . by Parul Arora.Review Questions (OBJ) 1. a) Polling b) Interrupt c) System Call d) None of the above 2. U1.

by Parul Arora. New Delhi-63. Virtual memory is __________.. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 3. 4. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. 138 . U1.

. The term " Operating System " means ________. 139 . New Delhi-63. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. U1. by Parul Arora.Review Questions (OBJ) 5.

by Parul Arora. 140 . This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ) Routine a) b) c) d) is not loaded until it is called. U1.Review Questions (OBJ) 7.. All routines are kept on disk in a relocatable load format. New Delhi-63. The main program is loaded into memory & is executed. The principle of locality of reference justifies the use of ________.

and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. by Parul Arora. 141 . a) 10 b) 7 c) 8 d) 9 10. the total number of page faults caused by the process will be __________. a) Program structure b) Program size c) Primary storage size d) None of the above U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. If all page frames are initially empty. ) The problem of thrashing is effected scientifically by ________.Review Questions (OBJ) 9.

Explain the difference between internal and external fragmentation 10. 142 . Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. How do I/O-bound and CPU-bound programs differ? 6.. What are the three main purposes of an operating system? 4. List the four steps that are necessary to run a program on a completely dedicated machine 5. Explain the difference between logical and physical addresses. What are the main differences between operating systems for mainframe computers and personal computers? 3. by Parul Arora. 9. How do MULTICS and UNIX differ? 7. How does a real-time system differ from time-share? 8. What is the main advantage of multiprogramming 2.Review Questions (Short) 1. New Delhi-63.

What are overlays? 12. U1. 16. How was memory mapping used in extending the usefulness of minicomputers? 13. Describe the actions taken by the operating system when a page fault occurs. When do page faults occur? 15. 143 . What is meant by locality? 21. What is reentrant code? 14. What is Belady’s anomaly? 19. Why is there a valid/invalid bit? Where is it kept? 18. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. What is virtual memory? 17.Review Questions (Short) 11. How do global and local allocation differ? 20..

Consider a paging system with the page table stored in memory.Review Questions (Long) 1.)If we add associative registers. and Worst-?t algorithms place processes of 212K. 6. 4. 500K. and 75 percent of all pagetable references are found in the associative registers. 417K. 4. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How many page faults occur for your algorithm for the following reference string. List ways to implement LRU. Given memory partitions of 100K. U1. Best-?t. if the entry is there. 7. and 600K (in order). 3. 8. 7. 3. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2.) 3. 4. 5. how would each of the First-?t. 8.)If a memory reference takes 200 nanoseconds. 8. 7. 4. 2. New Delhi-63. 300K. how long does a paged memory reference take? b. 112K. a. 144 . 9. 9. for four page frames? 1. 5. 5. 2.. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 200K. 1. to determine which page is victim. 4.

.. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 145 .2001 • Madnick E. “Operating System Concepts” Peason.. U1. New Delhi-63. by Parul Arora.6th Ed. ”Operating System”: TMH.. Donovan J.Recommended reading • Silbersachatz and Galvin. 4th Edition. 2001 • "Operating Systems” Tannenbaum PHI.

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