OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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. New Delhi-63.Learning Objective Understand the purpose of the operating system Distinguish between a resource. U1. by Parul Arora. 4 . a program. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. 5 ..Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

U1.. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. by Parul Arora. • Operating system goals: Execute user programs and make solving user problems easier. 6 . Make the computer system convenient to use. • Use the computer hardware in an efficient manner.

7 . 4. Hardware – provides basic computing resources (CPU. business programs). © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 2. other computers). 3. I/O devices). video games. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. database systems. machines. by Parul Arora. New Delhi-63. Users (people. memory.Computer System Components 1.

by Parul Arora.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. 8 .

.Operating System Definitions • Resource allocator – manages and allocates resources. 9 . New Delhi-63. • Kernel – the one program running at all times (all else being application programs). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Control program – controls the execution of user programs and operations of I/O devices . U1.

10 .. by Parul Arora. New Delhi-63. U1.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. First rudimentary operating system. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. 11 .

by Parul Arora. 12 ..Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

U1. by Parul Arora.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 13 .

.OS Features Needed for Multiprogramming • I/O routine supplied by the system. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Allocation of devices. 14 . • Memory management – the system must allocate the memory to several jobs. by Parul Arora. U1. • CPU scheduling – the system must choose among several jobs ready to run.

A job swapped in and out of memory to the disk. . by Parul Arora. New Delhi-63. when the operating system finishes the execution of one command. U1. it seeks the next “control statement” from the user’s keyboard.. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). On-line communication between the user and the system is provided.

16 . by Parul Arora. • I/O devices – keyboards. UNIX. • User convenience and responsiveness.. • May run several different types of operating systems (Windows. display screens. small printers. New Delhi-63. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features.Desktop Systems • Personal computers – computer system dedicated to a single user. U1. mice. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. MacOS.

• Tightly coupled system – processors share memory and a clock. 17 . New Delhi-63. U1.Parallel Systems • Multiprocessor systems with more than on CPU in close communication.. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. communication usually takes place through the shared memory. by Parul Arora.

by Parul Arora. U1. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.Parallel Systems (Cont.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Many processes can run at once without performance deterioration. New Delhi-63. master processor schedules and allocated work to slave processors. 18 ..

by Parul Arora. 19 . U1.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

U1. • Loosely coupled system – each processor has its own local memory. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. processors communicate with one another through various communications lines. by Parul Arora.Distributed Systems • Distribute the computation among several physical processors. New Delhi-63. • Advantages of distributed systems. such as high-speed buses or telephone lines. 20 .

.Distributed Systems (cont) • Requires networking infrastructure. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 21 . • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.

. by Parul Arora. U1. New Delhi-63. 22 .General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Asymmetric clustering: one server runs the application while other servers standby. by Parul Arora.Clustered Systems • Clustering allows two or more systems to share storage. • Symmetric clustering: all N hosts are running the application.. • Provides high reliability. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 23 . U1. New Delhi-63.

Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. New Delhi-63. industrial control systems. medical imaging systems. • Well-defined fixed-time constraints. and some display systems. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Real-Time systems may be either hard or soft real-time. 24 .. U1.

) • Hard real-time: Secondary storage limited or absent. data stored in short term memory. New Delhi-63. . by Parul Arora. U1.Real-Time Systems (Cont. or read-only memory (ROM) Conflicts with time-sharing systems. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. not supported by general-purpose operating systems. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.. virtual reality) requiring advanced operating-system features.

New Delhi-63. 26 .Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. by Parul Arora. U1.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.. U1.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 27 .

28 . U1.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. by Parul Arora.

by Parul arora U1. New Delhi-63.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 29 .

New Delhi-63. 30 . by Parul Arora.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.how memory is structured Memory management ..

31 .Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. New Delhi-63. by Parul Arora.

• Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. by Parul Arora. • User programs go through several steps before being run. 32 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Background • Program must be brought into memory and placed within a process for it to be run.. New Delhi-63. U1.

must recompile code if starting location changes. by Parul Arora. Need hardware support for address maps (e.g. U1.. absolute code can be generated. • Load time: Must generate relocatable code if memory location is not known at compile time. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 33 .Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.. New Delhi-63. base and limit registers).

34 . U1. by Parul Arora..Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

also referred to as virtual address. New Delhi-63. 35 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Logical vs. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Physical address – address seen by the memory unit. U1.. logical (virtual) and physical addresses differ in execution-time address-binding scheme. by Parul Arora. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. Logical address – generated by the CPU.

36 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Memory-Management Unit • Hardware device that maps virtual to physical address.. by Parul Arora. U1. • The user program deals with logical addresses. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. it never sees the real physical addresses. • In MMU scheme.

U1.Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. 37 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 38 . New Delhi-63.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. • No special support from the operating system is required implemented through program design. by Parul Arora. unused routine is never loaded.. U1. • Useful when large amounts of code are needed to handle infrequently occurring cases.

by Parul Arora. • Stub replaces itself with the address of the routine. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Dynamic Linking • Linking postponed until execution time. • Operating system needed to check if routine is in processes’ memory address. used to locate the appropriate memory-resident library routine. • Dynamic linking is particularly useful for libraries.. stub. 39 . U1. • Small piece of code. and executes the routine.

no special support needed from operating system. • Implemented by user.Overlays • Keep in memory only those instructions and data that are needed at any given time. U1.. • Needed when process is larger than amount of memory allocated to it. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 40 . by Parul Arora. New Delhi-63.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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44 . usually held in low memory with interrupt vector. limit register contains range of logical addresses – each logical address must be less than the limit register. Relocation register contains value of smallest physical address. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. and from changing operating-system code and data. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. User processes then held in high memory. by Parul Arora. U1. New Delhi-63.Contiguous Allocation • Main memory usually into two partitions: Resident operating system..

New Delhi-63.. U1. by Parul Arora. 45 .Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

) Multiple-partition allocation Hole – block of available memory. it is allocated memory from a hole large enough to accommodate it. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. When a process arrives. U1. by Parul Arora.. holes of various size are scattered throughout memory. New Delhi-63.Contiguous Allocation (Cont. 46 .

. U1.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. unless ordered by size. must also search entire list. Best-fit: Allocate the smallest hole that is big enough. 47 . New Delhi-63. Worst-fit: Allocate the largest hole. by Parul Arora. Produces the largest leftover hole. must search entire list. Produces the smallest leftover hole.

but it is not contiguous. by Parul Arora. and is done at execution time. New Delhi-63. 48 . but not being used. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. U1. Do I/O only into OS buffers. this size difference is memory internal to a partition. Compaction is possible only if relocation is dynamic. I/O problem Latch job in memory while it is involved in I/O. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block..Fragmentation • External Fragmentation – total memory space exists to satisfy a request. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. • Internal fragmentation. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 49 . • Set up a page table to translate logical to physical addresses. • Keep track of all free frames.Paging • Logical address space of a process can be noncontiguous. process is allocated physical memory whenever the latter is available. • To run a program of size n pages. need to find n free frames and load program. between 512 bytes and 8192 bytes). • Divide logical memory into blocks of same size called pages. U1. • Divide physical memory into fixed-sized blocks called frames (size is power of 2.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 50 . U1. by Parul Arora. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit..Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. New Delhi-63.

Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 51 . New Delhi-63. U1. by Parul Arora.

New Delhi-63. U1. by Parul Arora.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 52 ..

by Parul Arora. New Delhi-63. 53 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..

Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. New Delhi-63.. 54 .

U1.Implementation of Page Table • Page table is kept in main memory.. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 55 . New Delhi-63. • Page-table length register (PRLR) indicates size of the page table. • Page-table base register (PTBR) points to the page table. One for the page table and one for the data/instruction. • In this scheme every data/instruction access requires two memory accesses. by Parul Arora.

56 . U1. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora..Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. New Delhi-63. A´´) If A´ is in associative register. get frame # out.

New Delhi-63. 57 ..Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

. by Parul Arora. 58 .Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. ration related to number of associative registers. U1. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

U1.Memory Protection • Memory protection implemented by associating protection bit with each frame. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 59 . “invalid” indicates that the page is not in the process’ logical address space. and is thus a legal page. by Parul Arora..

U1.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. 60 . New Delhi-63.

. U1. 61 . New Delhi-63.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

New Delhi-63. U1.Hierarchical Page Tables • Break up the logical address space into multiple page tables. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. 62 . • A simple technique is a two-level page table.

a 10-bit page offset. New Delhi-63. Since the page table is paged. U1. 63 . by Parul Arora. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. a page offset consisting of 12 bits. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. the page number is further divided into: Thus.

New Delhi-63.. U1.Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 64 .

by Parul Arora. U1. 65 . New Delhi-63.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

If a match is found. the corresponding physical frame is extracted. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Virtual page numbers are compared in this chain searching for a match. 66 .Hashed Page Tables • Common in address spaces > 32 bits. New Delhi-63. by Parul Arora. This page table contains a chain of elements hashing to the same location.. • The virtual page number is hashed into a page table.

New Delhi-63. by Parul Arora. 67 .. U1.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

with information about the process that owns that page.Inverted Page Table • One entry for each real page of memory. but increases time needed to search the table when a page reference occurs. • Use hash table to limit the search to one — or at most a few — page-table entries. by Parul Arora. • Decreases memory needed to store each page table. • Entry consists of the virtual address of the page stored in that real memory location. 68 . New Delhi-63. U1.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. New Delhi-63. by Parul Arora.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 69 .

. U1. New Delhi-63. text editors. compilers. window systems). Shared code must appear in same location in the logical address space of all processes. 70 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.e.. by Parul Arora. The pages for the private code and data can appear anywhere in the logical address space. Private code and data Each process keeps a separate copy of the code and data.

New Delhi-63..Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 71 . by Parul Arora. U1.

stack. U1. symbol table. procedure.. A program is a collection of segments. object. method. 72 . local variables. common block. by Parul Arora. A segment is a logical unit such as: main program. New Delhi-63. function. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Memory-management scheme that supports user view of memory. global variables.

by Parul Arora. New Delhi-63.. 73 .User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

by Parul Arora. New Delhi-63. 74 .Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

New Delhi-63. • • • Segment-table base register (STBR) points to the segment table’s location in memory.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. Segment table – maps two-dimensional physical addresses. each table entry has: base – contains the starting physical address where the segments reside in memory.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. limit – specifies the length of the segment. offset>. U1. by Parul Arora. 75 .

dynamic by segment table • Sharing.Segmentation Architecture (Cont. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 76 .. shared segments same segment number • Allocation. U1. New Delhi-63.) • Relocation.

code sharing occurs at segment level.. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. by Parul Arora.) • Protection. U1. • Since segments vary in length. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. memory allocation is a dynamic storage-allocation problem.Segmentation Architecture (Cont. 77 .

New Delhi-63. U1. 78 ..Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

New Delhi-63. U1.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. 79 .

by Parul Arora. U1. New Delhi-63..Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 80 .

• Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment.. by Parul Arora. New Delhi-63. 81 . U1. but rather the base address of a page table for this segment. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.

New Delhi-63. by Parul Arora.. 82 .MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

. U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation with Paging – Intel 386 As shown in the following diagram. 83 . the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. New Delhi-63.

Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 84 . U1. New Delhi-63.

New Delhi-63.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1. 85 .

by Parul Arora.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. cache memory.. • Evaluate the trade-offs in terms of memory size (main memory. auxiliary memory) and processor speed. • Describe the reason for and use of cache memory. U1. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. 86 . • Summarize the principles of virtual memory as applied to caching and paging. • Discuss the concept of thrashing.

Only part of the program needs to be in memory for execution. New Delhi-63. . Logical address space can therefore be much larger than physical address space..Background • Virtual memory – separation of user logical memory from physical memory. Allows for more efficient process creation. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. Allows address spaces to be shared by several processes. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

by Parul Arora. 88 .. U1.Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

. by Parul Arora. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 89 .Demand Paging Bring a page into memory only when it is needed.

Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. U1. 90 ..

1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but valid-invalid bit 1 Example of a page table snapshot. 91 .. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. U1. New Delhi-63. by Parul Arora.

U1.. by Parul Arora.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 92 .

New Delhi-63. . first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. validation bit = 1.. Swap page into frame. • • • • Get empty frame. Reset tables. by Parul Arora.Page Fault • If there is ever a reference to a page. Restart instruction: Least Recently Used block move U1. Just not in memory.

Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 94 .. U1. by Parul Arora.

U1. New Delhi-63. algorithm performance – want an algorithm which will result in minimum number of page faults.What happens if there is no free frame? • Page replacement – find some page in memory. 95 . swap it out.. • Same page may be brought into memory several times. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but not really in use. by Parul Arora.

every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. New Delhi-63. U1. 96 .0 if p = 0 no page faults if p = 1. by Parul Arora.

000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Swap Page Time = 10 msec = 10. 97 . U1. by Parul Arora. New Delhi-63.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out.

U1. by Parul Arora. New Delhi-63.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 98 .

. • COW allows more efficient process creation as only modified pages are copied.If either process modifies a shared page. New Delhi-63. • Free pages are allocated from a pool of zeroed-out pages. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. only then is the page copied. 99 . U1.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory.

• Also allows several processes to map the same file allowing the pages in memory to be shared. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. . U1. by Parul Arora. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. New Delhi-63. A page-sized portion of the file is read from the file system into a physical page. • A file is initially read using demand paging..

. U1. 101 . by Parul Arora. New Delhi-63.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. New Delhi-63. U1. 102 .. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk.

Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.. 103 . by Parul Arora.

use a page replacement algorithm to select a victim frame. Update the page and frame tables. • Find a free frame: . use it.If there is a free frame. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.If there is no free frame. • Restart the process..Basic Page Replacement • Find the location of the desired page on disk. • Read the desired page into the (newly) free frame. U1. 104 . . New Delhi-63.

U1.. 105 .Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

1. by Parul Arora. 1. 4. 5. New Delhi-63. In all our examples. 2. 2. 106 .Page Replacement Algorithms Want lowest page-fault rate.. 3. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 3. 5. 4. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. the reference string is 1. 2.

Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 107 . by Parul Arora.. U1.

2. 4. 3. 1.. 4.First-In-First-Out (FIFO) Algorithm Reference string: 1. New Delhi-63. 2. by Parul Arora. U1. 5. 108 . 2. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 1. 3.

. U1. 109 . by Parul Arora.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

New Delhi-63. by Parul Arora. U1.Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 113 .

4. New Delhi-63. 2. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. by Parul Arora. 3. every time page is referenced through this entry. 5. look at the counters to determine which are to change. copy the clock into the counter. 1.Least Recently Used (LRU) Algorithm Reference string: 1.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. 3. 4. 114 . When a page needs to be changed. U1. 1. 2.

LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 115 . by Parul Arora. U1.

U1.LRU Algorithm (Cont. by Parul Arora. 116 ..) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 117 . U1. New Delhi-63..

by Parul Arora. U1.LRU Approximation Algorithm Reference bit With each page associate a bit. replace next page (in clock order). Clock replacement. rules. New Delhi-63. We do not know the order. Second chance Need reference bit. initially = 0 When page is referenced bit set to 1. 118 . then: set reference bit 0. If page to be replaced (in clock order) has reference bit = 1.. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. however. Replace the one which is 0 (if one exists). leave page in memory.

by Parul Arora..Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 119 . U1. New Delhi-63.

MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used.Counting Algorithms • Keep a counter of the number of references that have been made to each page. 120 . New Delhi-63. by Parul Arora. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. LFU Algorithm: replaces page with smallest count. U1..

U1. 2 pages to handle to. by Parul Arora. 2 pages to handle from. 121 . • Two major allocation schemes. might span 2 pages.Allocation of Frames • Each process needs minimum number of pages. New Delhi-63. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes..

U1.. if 100 frames and 5 processes. by Parul Arora.g. New Delhi-63. 122 . si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. give each 20 pages.Fixed Allocation • Equal allocation – e. • Proportional allocation – Allocate according to the size of process..

123 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. select for replacement a frame from a process with lower priority number. U1. select for replacement one of its frames.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. by Parul Arora.. • If process Pi generates a page fault.

by Parul Arora. U1. New Delhi-63. • Local replacement – each process selects from only its own set of allocated frames. 124 .Global vs.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. one process can take a frame from another. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.

New Delhi-63. U1. the page-fault rate is very high. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 125 .Thrashing If a process does not have “enough” pages. This leads to: low CPU utilization.. by Parul Arora. Thrashing ≡ a process is busy swapping pages in and out. another process added to the system. operating system thinks that it needs to increase the degree of multiprogramming.

by Parul Arora. U1. 126 . New Delhi-63.Thrashing Why does paging work? Locality model Process migrates from one locality to another.. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Localities may overlap.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

by Parul Arora. U1. process loses frame.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. If actual rate too high. 130 . If actual rate too low. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. process gains frame.

U1. 131 .. New Delhi-63. by Parul Arora.Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

the working set of each process is stored in the TLB. 132 . by Parul Arora.The amount of memory accessible from the TLB. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) TLB Reach .Other Considerations (Cont. TLB Reach = (TLB Size) X (Page Size) Ideally. U1. Otherwise there is a high degree of page faults.

. 133 . New Delhi-63. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Provide Multiple Page Sizes. This may lead to an increase in fragmentation as not all applications require a large page size.Increasing the Size of the TLB • Increase the Page Size. by Parul Arora.

. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.j] = 0. j < A.length.length. i < A. 134 .) Program structure int A[][] = new int[1024][1024]. j < A.length. i++) A[i. New Delhi-63. i++) for (j = 0. Each row is stored in one page Program 1 for (j = 0. j++) for (i = 0.Other Considerations (Cont.j] = 0. U1. 1024 x 1024 page faults Program 2 for (i = 0. i < A.length. by Parul Arora. j++) A[i.

by Parul Arora. New Delhi-63.and also allows degree of multiprogramming to be raised.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Memory management algorithms differ in many concepts. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Virtual memory frees application programers from worrying about memory availability U1. . Virtual memory allows extremely large processes to be run. Multiprogramming increased the performance of computer system.

136 Used. Least Recently Used. . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Operating systems are a type of system software that allow applications to interface with computer hardware. First In First Out.. Second Chance. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. timesharing. personal computing and dedicated. New Delhi-63. Policies for determining which pages to load and remove from memory include Random Replacement. by Parul Arora. Resources are any objects that can be allocated within a system. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames.Summary • In the introduction. Four major categories of operating systems are batch. we saw that software can be roughly divided into two groups: application software and system software. and Least Frequently U1. and the operating system is responsible for managing them.

Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 137 . The Hardware mechanism that enables a device to notify the CPU is called __________. U1.Review Questions (OBJ) 1. a) Polling b) Interrupt c) System Call d) None of the above 2. New Delhi-63. by Parul Arora..

Virtual memory is __________. by Parul Arora. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers.Review Questions (OBJ) 3. 4. New Delhi-63. U1.. 138 . _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

139 . U1. by Parul Arora.. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 5. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. The term " Operating System " means ________. New Delhi-63.

by Parul Arora. 140 ..Review Questions (OBJ) 7. New Delhi-63. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. All routines are kept on disk in a relocatable load format. The main program is loaded into memory & is executed. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ) Routine a) b) c) d) is not loaded until it is called. The principle of locality of reference justifies the use of ________. U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 141 .Review Questions (OBJ) 9. a) Program structure b) Program size c) Primary storage size d) None of the above U1.. New Delhi-63. a) 10 b) 7 c) 8 d) 9 10. ) The problem of thrashing is effected scientifically by ________. the total number of page faults caused by the process will be __________. by Parul Arora. If all page frames are initially empty. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO.

Explain the difference between internal and external fragmentation 10. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What is the main advantage of multiprogramming 2. What are the main differences between operating systems for mainframe computers and personal computers? 3. Explain the difference between logical and physical addresses. 142 . 9.Review Questions (Short) 1. List the four steps that are necessary to run a program on a completely dedicated machine 5. U1. How do I/O-bound and CPU-bound programs differ? 6.. New Delhi-63. How does a real-time system differ from time-share? 8. How do MULTICS and UNIX differ? 7. by Parul Arora. What are the three main purposes of an operating system? 4.

143 . When do page faults occur? 15. U1. 16. What is meant by locality? 21. How was memory mapping used in extending the usefulness of minicomputers? 13. What is reentrant code? 14. What is Belady’s anomaly? 19.. Why is there a valid/invalid bit? Where is it kept? 18. How do global and local allocation differ? 20. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. What is virtual memory? 17. What are overlays? 12. by Parul Arora.Review Questions (Short) 11. Describe the actions taken by the operating system when a page fault occurs.

9. 7. 500K. 4. by Parul Arora. 8. New Delhi-63.)If a memory reference takes 200 nanoseconds. for four page frames? 1. 7. 300K. How many page faults occur for your algorithm for the following reference string. 4.) 3. Given memory partitions of 100K. Consider a paging system with the page table stored in memory. 5.)If we add associative registers. 9. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time.Review Questions (Long) 1. 3. 7. 2. 6. 4. 5. 8. U1. 1. 112K. 417K. and Worst-?t algorithms place processes of 212K. 4. how would each of the First-?t. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. how long does a paged memory reference take? b. and 600K (in order). 5. if the entry is there. 8. 200K. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. and 75 percent of all pagetable references are found in the associative registers. 4. to determine which page is victim. 144 . 3. 2.. List ways to implement LRU. Best-?t. a.

. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.Recommended reading • Silbersachatz and Galvin. by Parul Arora.2001 • Madnick E. “Operating System Concepts” Peason. 4th Edition. U1.. 145 . Donovan J.6th Ed. ”Operating System”: TMH. 2001 • "Operating Systems” Tannenbaum PHI..

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