OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 1

Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 2

Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 3

Learning Objective Understand the purpose of the operating system Distinguish between a resource. 4 . U1.. by Parul Arora. a program. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

by Parul Arora..Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 5 . U1.

6 .What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. Make the computer system convenient to use.. • Use the computer hardware in an efficient manner. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Operating system goals: Execute user programs and make solving user problems easier. U1. New Delhi-63.

database systems. 2. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Users (people. business programs). by Parul Arora. Hardware – provides basic computing resources (CPU. other computers). Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. New Delhi-63.Computer System Components 1.. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. memory. 3. 7 . U1. video games. machines. I/O devices).

New Delhi-63.. 8 . by Parul Arora.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

by Parul Arora. New Delhi-63. • Kernel – the one program running at all times (all else being application programs). U1.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Control program – controls the execution of user programs and operations of I/O devices .Operating System Definitions • Resource allocator – manages and allocates resources. 9 .

New Delhi-63. U1.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 10 .. by Parul Arora.

by Parul Arora.. New Delhi-63. U1. First rudimentary operating system. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. 11 .

Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. by Parul Arora. 12 .

U1. by Parul Arora..Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 13 .

• Memory management – the system must allocate the memory to several jobs. New Delhi-63. • CPU scheduling – the system must choose among several jobs ready to run. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 14 . by Parul Arora.OS Features Needed for Multiprogramming • I/O routine supplied by the system. U1. • Allocation of devices..

U1. On-line communication between the user and the system is provided.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). A job swapped in and out of memory to the disk.. . by Parul Arora. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. it seeks the next “control statement” from the user’s keyboard. New Delhi-63. when the operating system finishes the execution of one command.

• I/O devices – keyboards. small printers. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features.. 16 . Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • May run several different types of operating systems (Windows. MacOS. display screens. mice. New Delhi-63.Desktop Systems • Personal computers – computer system dedicated to a single user. U1. • User convenience and responsiveness. UNIX.

• Tightly coupled system – processors share memory and a clock. communication usually takes place through the shared memory. 17 . by Parul Arora.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. New Delhi-63.. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

18 . master processor schedules and allocated work to slave processors.. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.Parallel Systems (Cont.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. Many processes can run at once without performance deterioration. by Parul Arora. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

. 19 . New Delhi-63. by Parul Arora. U1.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. U1. 20 . • Advantages of distributed systems. processors communicate with one another through various communications lines. • Loosely coupled system – each processor has its own local memory. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. such as high-speed buses or telephone lines.Distributed Systems • Distribute the computation among several physical processors.

Distributed Systems (cont) • Requires networking infrastructure. by Parul Arora. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 21 . U1.

. New Delhi-63. 22 . U1.General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

• Provides high reliability. U1. • Symmetric clustering: all N hosts are running the application. by Parul Arora. • Asymmetric clustering: one server runs the application while other servers standby. New Delhi-63.. 23 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Clustered Systems • Clustering allows two or more systems to share storage.

24 . by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Well-defined fixed-time constraints. and some display systems. New Delhi-63.. industrial control systems.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. • Real-Time systems may be either hard or soft real-time. medical imaging systems.

data stored in short term memory. U1. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. . New Delhi-63. or read-only memory (ROM) Conflicts with time-sharing systems.) • Hard real-time: Secondary storage limited or absent.Real-Time Systems (Cont.. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. not supported by general-purpose operating systems. virtual reality) requiring advanced operating-system features. by Parul Arora.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 26 . by Parul Arora.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. U1.. New Delhi-63.

U1.. New Delhi-63. 27 . by Parul Arora.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. U1. by Parul Arora..Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 28 .

Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1. 29 . New Delhi-63.

how memory is structured Memory management . by Parul Arora. U1. 30 .strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .

New Delhi-63. by Parul Arora.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 31 .. U1.

32 . • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program.Background • Program must be brought into memory and placed within a process for it to be run. New Delhi-63. U1. by Parul Arora. • User programs go through several steps before being run.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Need hardware support for address maps (e. 33 . • Load time: Must generate relocatable code if memory location is not known at compile time. New Delhi-63. base and limit registers). U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. must recompile code if starting location changes. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.. absolute code can be generated. by Parul Arora.g.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.

34 . New Delhi-63. U1. by Parul Arora.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

35 . Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. by Parul Arora. Logical address – generated by the CPU. Physical address – address seen by the memory unit.Logical vs.. New Delhi-63. logical (virtual) and physical addresses differ in execution-time address-binding scheme. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. also referred to as virtual address. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

U1.Memory-Management Unit • Hardware device that maps virtual to physical address.. New Delhi-63. • The user program deals with logical addresses. it never sees the real physical addresses. 36 . • In MMU scheme. by Parul Arora. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63..Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 37 . U1.

U1. • No special support from the operating system is required implemented through program design.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. • Useful when large amounts of code are needed to handle infrequently occurring cases. 38 . by Parul Arora.. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. unused routine is never loaded.

New Delhi-63. U1. 39 . • Stub replaces itself with the address of the routine. • Dynamic linking is particularly useful for libraries. • Operating system needed to check if routine is in processes’ memory address. by Parul Arora. • Small piece of code.Dynamic Linking • Linking postponed until execution time. stub. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. used to locate the appropriate memory-resident library routine. and executes the routine.

U1.. • Needed when process is larger than amount of memory allocated to it. • Implemented by user. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Overlays • Keep in memory only those instructions and data that are needed at any given time. New Delhi-63. by Parul Arora. no special support needed from operating system. 40 .

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 41

Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 42

Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 43

usually held in low memory with interrupt vector. limit register contains range of logical addresses – each logical address must be less than the limit register. User processes then held in high memory.Contiguous Allocation • Main memory usually into two partitions: Resident operating system.. New Delhi-63. Relocation register contains value of smallest physical address. U1. and from changing operating-system code and data. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 44 . by Parul Arora. • Single-partition allocation Relocation-register scheme used to protect user processes from each other.

. by Parul Arora. 45 . New Delhi-63.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

. by Parul Arora. it is allocated memory from a hole large enough to accommodate it.) Multiple-partition allocation Hole – block of available memory. When a process arrives. U1.Contiguous Allocation (Cont. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 46 . holes of various size are scattered throughout memory. New Delhi-63.

must search entire list. U1. Worst-fit: Allocate the largest hole. Produces the largest leftover hole.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. must also search entire list. 47 . by Parul Arora. Produces the smallest leftover hole. unless ordered by size. New Delhi-63. Best-fit: Allocate the smallest hole that is big enough.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough.

and is done at execution time. Compaction is possible only if relocation is dynamic. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. U1. I/O problem Latch job in memory while it is involved in I/O. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but it is not contiguous. Do I/O only into OS buffers. 48 .Fragmentation • External Fragmentation – total memory space exists to satisfy a request. this size difference is memory internal to a partition.. but not being used.

process is allocated physical memory whenever the latter is available. between 512 bytes and 8192 bytes). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Divide logical memory into blocks of same size called pages. • Divide physical memory into fixed-sized blocks called frames (size is power of 2.Paging • Logical address space of a process can be noncontiguous. by Parul Arora. • Keep track of all free frames. • To run a program of size n pages.. • Internal fragmentation. New Delhi-63. 49 . U1. • Set up a page table to translate logical to physical addresses. need to find n free frames and load program.

U1. 50 . Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

U1.. New Delhi-63. by Parul Arora. 51 .Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

52 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1. New Delhi-63.

U1. 53 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora.

Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. 54 . by Parul Arora.

U1. One for the page table and one for the data/instruction. • Page-table base register (PTBR) points to the page table.Implementation of Page Table • Page table is kept in main memory. by Parul Arora. 55 . • In this scheme every data/instruction access requires two memory accesses. • Page-table length register (PRLR) indicates size of the page table. New Delhi-63.. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

A´´) If A´ is in associative register. New Delhi-63. U1.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. 56 .. by Parul Arora. get frame # out. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. by Parul Arora. U1.Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 57 .

by Parul Arora.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. ration related to number of associative registers. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. 58 ..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management..Memory Protection • Memory protection implemented by associating protection bit with each frame. U1. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. New Delhi-63. and is thus a legal page. 59 . by Parul Arora. “invalid” indicates that the page is not in the process’ logical address space.

. by Parul Arora. U1. 60 .Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

61 . U1.. by Parul Arora. New Delhi-63.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• A simple technique is a two-level page table.Hierarchical Page Tables • Break up the logical address space into multiple page tables. U1. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 62 . by Parul Arora.

. the page number is further divided into: Thus. U1. Since the page table is paged. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. by Parul Arora. New Delhi-63. a page offset consisting of 12 bits. a 10-bit page offset. 63 . number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits.

U1. by Parul Arora. New Delhi-63. 64 ..Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 65 . U1. by Parul Arora. New Delhi-63.

New Delhi-63. • The virtual page number is hashed into a page table. the corresponding physical frame is extracted.Hashed Page Tables • Common in address spaces > 32 bits. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 66 . This page table contains a chain of elements hashing to the same location. by Parul Arora. • Virtual page numbers are compared in this chain searching for a match. U1. If a match is found.

67 . U1.. New Delhi-63.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

with information about the process that owns that page.Inverted Page Table • One entry for each real page of memory. but increases time needed to search the table when a page reference occurs.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Use hash table to limit the search to one — or at most a few — page-table entries. • Entry consists of the virtual address of the page stored in that real memory location. New Delhi-63. 68 . • Decreases memory needed to store each page table. by Parul Arora.

by Parul Arora. New Delhi-63. 69 .Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..

by Parul Arora. New Delhi-63.. window systems). compilers. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. text editors.. The pages for the private code and data can appear anywhere in the logical address space. Shared code must appear in same location in the logical address space of all processes. 70 . Private code and data Each process keeps a separate copy of the code and data.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.e.

Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. New Delhi-63. 71 ..

global variables. New Delhi-63. 72 . local variables. U1. method. function. procedure. by Parul Arora. A segment is a logical unit such as: main program. common block. symbol table. stack.Segmentation Memory-management scheme that supports user view of memory. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. object.. A program is a collection of segments.

U1. by Parul Arora..User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 73 . New Delhi-63.

New Delhi-63.. by Parul Arora.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 74 .

Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. limit – specifies the length of the segment. 75 . each table entry has: base – contains the starting physical address where the segments reside in memory. • • • Segment-table base register (STBR) points to the segment table’s location in memory. U1.. by Parul Arora. offset>. New Delhi-63. Segment table – maps two-dimensional physical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR.

first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 76 . shared segments same segment number • Allocation.) • Relocation. U1. dynamic by segment table • Sharing.Segmentation Architecture (Cont. New Delhi-63.

New Delhi-63. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. code sharing occurs at segment level. memory allocation is a dynamic storage-allocation problem. • Since segments vary in length. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 77 .. U1.) • Protection.Segmentation Architecture (Cont. by Parul Arora.

. U1.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 78 .

Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. U1. 79 .

New Delhi-63. 80 . U1. by Parul Arora.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. 81 .Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. New Delhi-63. but rather the base address of a page table for this segment.

. 82 . U1. New Delhi-63.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Segmentation with Paging – Intel 386 As shown in the following diagram. U1. 83 .

U1.. by Parul Arora.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 84 .

by Parul arora U1. New Delhi-63.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 85 .

• Discuss the concept of thrashing. • Describe the reason for and use of cache memory. • Summarize the principles of virtual memory as applied to caching and paging. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. by Parul Arora.. 86 . New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. cache memory.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. U1. auxiliary memory) and processor speed. • Evaluate the trade-offs in terms of memory size (main memory.

Only part of the program needs to be in memory for execution. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Background • Virtual memory – separation of user logical memory from physical memory. Allows address spaces to be shared by several processes. Logical address space can therefore be much larger than physical address space. by Parul Arora. Allows for more efficient process creation. New Delhi-63. . • Virtual memory can be implemented via: Demand paging Demand segmentation U1.

88 . U1. by Parul Arora.Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

U1..Demand Paging Bring a page into memory only when it is needed. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 89 . New Delhi-63.

. by Parul Arora. New Delhi-63. U1. 90 .Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. 91 . by Parul Arora. but valid-invalid bit 1 Example of a page table snapshot. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.

92 .Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. U1..

New Delhi-63. Swap page into frame. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Reset tables. by Parul Arora. validation bit = 1. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. Just not in memory. . • • • • Get empty frame.Page Fault • If there is ever a reference to a page. Restart instruction: Least Recently Used block move U1.

94 . by Parul Arora. U1. New Delhi-63.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

by Parul Arora.. 95 .What happens if there is no free frame? • Page replacement – find some page in memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. swap it out. • Same page may be brought into memory several times. but not really in use. U1. algorithm performance – want an algorithm which will result in minimum number of page faults.

96 .Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.0 if p = 0 no page faults if p = 1.. U1.

000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Swap Page Time = 10 msec = 10. 97 . by Parul Arora. U1.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out.. New Delhi-63.

New Delhi-63.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 98 .. by Parul Arora. U1.

• Free pages are allocated from a pool of zeroed-out pages.If either process modifies a shared page. U1. only then is the page copied..Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. 99 . • COW allows more efficient process creation as only modified pages are copied. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

. A page-sized portion of the file is read from the file system into a physical page.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. New Delhi-63. • A file is initially read using demand paging. • Also allows several processes to map the same file allowing the pages in memory to be shared. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . Subsequent reads/writes to/from the file are treated as ordinary memory accesses. U1. by Parul Arora.

U1. New Delhi-63..Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 101 . by Parul Arora.

New Delhi-63. 102 . by Parul Arora..Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk.

U1.. by Parul Arora. New Delhi-63. 103 .Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. . use a page replacement algorithm to select a victim frame. • Read the desired page into the (newly) free frame. New Delhi-63. • Find a free frame: . • Restart the process.If there is a free frame. use it.Basic Page Replacement • Find the location of the desired page on disk.If there is no free frame. by Parul Arora. 104 . Update the page and frame tables. U1..

Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 105 . New Delhi-63. by Parul Arora.

In all our examples. 106 . 4. 4. New Delhi-63.. 3. by Parul Arora.Page Replacement Algorithms Want lowest page-fault rate. the reference string is 1. 5. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. 5. 1. 1. 2. 3. 2. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string.

New Delhi-63.. by Parul Arora. U1.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 107 .

108 . 2.. 5. by Parul Arora. 3. 2. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 1. 2. New Delhi-63. U1.First-In-First-Out (FIFO) Algorithm Reference string: 1. 1. 4. 3. 4.

U1. New Delhi-63.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 109 .. by Parul Arora.

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

by Parul Arora.Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.. 113 .

1. 3. 2. U1. When a page needs to be changed.Least Recently Used (LRU) Algorithm Reference string: 1. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. 1. 2. 5. 114 . look at the counters to determine which are to change. copy the clock into the counter. 3. every time page is referenced through this entry. 2. 4. New Delhi-63. 4.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

115 .LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63. U1.

by Parul Arora. U1.LRU Algorithm (Cont..) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 116 .

117 . New Delhi-63. by Parul Arora.. U1.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. New Delhi-63. If page to be replaced (in clock order) has reference bit = 1. Second chance Need reference bit. U1. leave page in memory. then: set reference bit 0. We do not know the order. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 118 .LRU Approximation Algorithm Reference bit With each page associate a bit. initially = 0 When page is referenced bit set to 1. Replace the one which is 0 (if one exists). Clock replacement. replace next page (in clock order). rules. however.

U1.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 119 . by Parul Arora.

• • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Counting Algorithms • Keep a counter of the number of references that have been made to each page. LFU Algorithm: replaces page with smallest count. U1. New Delhi-63. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. 120 .. by Parul Arora.

• Two major allocation schemes. 2 pages to handle to. 2 pages to handle from. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. might span 2 pages. 121 . • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. U1.. New Delhi-63.Allocation of Frames • Each process needs minimum number of pages.

New Delhi-63.. U1..g. if 100 frames and 5 processes. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Proportional allocation – Allocate according to the size of process. by Parul Arora. give each 20 pages.Fixed Allocation • Equal allocation – e. 122 .

select for replacement one of its frames. select for replacement a frame from a process with lower priority number.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. U1. • If process Pi generates a page fault.. by Parul Arora. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 123 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Local replacement – each process selects from only its own set of allocated frames. U1. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames..Global vs. by Parul Arora. 124 . one process can take a frame from another. New Delhi-63.

operating system thinks that it needs to increase the degree of multiprogramming. by Parul Arora. Thrashing ≡ a process is busy swapping pages in and out. the page-fault rate is very high. 125 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. another process added to the system. New Delhi-63. U1. This leads to: low CPU utilization..Thrashing If a process does not have “enough” pages.

U1. by Parul Arora.Thrashing Why does paging work? Locality model Process migrates from one locality to another. 126 . New Delhi-63.. Localities may overlap. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

If actual rate too high. process loses frame. by Parul Arora. New Delhi-63. U1. process gains frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. 130 . If actual rate too low..

New Delhi-63. by Parul Arora..Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 131 .

Otherwise there is a high degree of page faults.) TLB Reach . New Delhi-63.Other Considerations (Cont. 132 . by Parul Arora.The amount of memory accessible from the TLB.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the working set of each process is stored in the TLB. TLB Reach = (TLB Size) X (Page Size) Ideally. U1.

. 133 . U1.Increasing the Size of the TLB • Increase the Page Size. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. by Parul Arora. This may lead to an increase in fragmentation as not all applications require a large page size. • Provide Multiple Page Sizes.

Each row is stored in one page Program 1 for (j = 0.j] = 0.length. by Parul Arora. i < A. j < A. 134 .length. i < A. j++) for (i = 0. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) Program structure int A[][] = new int[1024][1024].j] = 0.Other Considerations (Cont. i++) A[i.length.. j < A. New Delhi-63. U1. i++) for (j = 0. j++) A[i.length. 1024 x 1024 page faults Program 2 for (i = 0.

.and also allows degree of multiprogramming to be raised. Virtual memory frees application programers from worrying about memory availability U1. by Parul Arora.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Multiprogramming increased the performance of computer system. Memory management algorithms differ in many concepts. New Delhi-63. Virtual memory allows extremely large processes to be run. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Summary • In the introduction. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. New Delhi-63. and the operating system is responsible for managing them. Operating systems are a type of system software that allow applications to interface with computer hardware. we saw that software can be roughly divided into two groups: application software and system software. Second Chance.. Least Recently Used. by Parul Arora. Four major categories of operating systems are batch. timesharing. personal computing and dedicated. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. First In First Out. 136 Used. Policies for determining which pages to load and remove from memory include Random Replacement. Resources are any objects that can be allocated within a system. and Least Frequently U1. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. .

by Parul Arora. U1. New Delhi-63.Review Questions (OBJ) 1. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 137 . The Hardware mechanism that enables a device to notify the CPU is called __________. a) Polling b) Interrupt c) System Call d) None of the above 2..

Review Questions (OBJ) 3. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. Virtual memory is __________.. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. New Delhi-63. 4. U1. 138 .

Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6.Review Questions (OBJ) 5.. U1. The term " Operating System " means ________. New Delhi-63. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 139 .

by Parul Arora. New Delhi-63.Review Questions (OBJ) 7. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8.. The main program is loaded into memory & is executed. ) Routine a) b) c) d) is not loaded until it is called. 140 . U1. All routines are kept on disk in a relocatable load format. The principle of locality of reference justifies the use of ________.

and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. a) Program structure b) Program size c) Primary storage size d) None of the above U1.. New Delhi-63. by Parul Arora. If all page frames are initially empty. a) 10 b) 7 c) 8 d) 9 10. the total number of page faults caused by the process will be __________. 141 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 9. ) The problem of thrashing is effected scientifically by ________.

How does a real-time system differ from time-share? 8. U1. Explain the difference between internal and external fragmentation 10. How do MULTICS and UNIX differ? 7. What are the three main purposes of an operating system? 4. 142 .Review Questions (Short) 1.. Explain the difference between logical and physical addresses. What are the main differences between operating systems for mainframe computers and personal computers? 3. How do I/O-bound and CPU-bound programs differ? 6. 9. List the four steps that are necessary to run a program on a completely dedicated machine 5. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. What is the main advantage of multiprogramming 2. New Delhi-63.

What is meant by locality? 21. 143 .. Why is there a valid/invalid bit? Where is it kept? 18. How was memory mapping used in extending the usefulness of minicomputers? 13. What is virtual memory? 17. U1. What are overlays? 12. What is reentrant code? 14. Describe the actions taken by the operating system when a page fault occurs. How do global and local allocation differ? 20.Review Questions (Short) 11. New Delhi-63. by Parul Arora. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. When do page faults occur? 15. What is Belady’s anomaly? 19. 16.

5. how would each of the First-?t. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 8. U1. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 7. and 75 percent of all pagetable references are found in the associative registers. 2. 500K. Given memory partitions of 100K.)If a memory reference takes 200 nanoseconds. 112K. 3. 4. to determine which page is victim. 4. by Parul Arora. a. 417K. 5. Consider a paging system with the page table stored in memory. 9. 7. 200K. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 144 . 3. 4. 8. for four page frames? 1. how long does a paged memory reference take? b. 2. New Delhi-63. 8. and 600K (in order). 300K. 4. 4. 7. if the entry is there.Review Questions (Long) 1. 5.) 3. 6. 9.)If we add associative registers. 1. How many page faults occur for your algorithm for the following reference string. and Worst-?t algorithms place processes of 212K. Best-?t. List ways to implement LRU.

2001 • "Operating Systems” Tannenbaum PHI.. ”Operating System”: TMH.Recommended reading • Silbersachatz and Galvin. Donovan J. by Parul Arora. 145 .. “Operating System Concepts” Peason.2001 • Madnick E.. New Delhi-63. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.6th Ed.. 4th Edition.

Sign up to vote on this title
UsefulNot useful