OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective Understand the purpose of the operating system Distinguish between a resource. 4 .. U1. by Parul Arora. a program. New Delhi-63. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. by Parul Arora. 5 .. U1.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

6 . New Delhi-63. • Operating system goals: Execute user programs and make solving user problems easier. U1. • Use the computer hardware in an efficient manner.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. by Parul Arora. Make the computer system convenient to use.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

2. I/O devices). database systems. 4. Hardware – provides basic computing resources (CPU.Computer System Components 1. New Delhi-63. 7 . memory. video games. business programs). Users (people. machines. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. 3.. by Parul Arora. U1. other computers). © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. 8 .Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1.

9 . by Parul Arora. U1..Operating System Definitions • Resource allocator – manages and allocates resources. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Control program – controls the execution of user programs and operations of I/O devices . • Kernel – the one program running at all times (all else being application programs). New Delhi-63.

U1. New Delhi-63.. by Parul Arora.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 10 .

U1. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 11 . New Delhi-63. First rudimentary operating system.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another.. by Parul Arora.

New Delhi-63. U1.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 12 ..

U1. by Parul Arora. New Delhi-63.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 13 ..

. • Memory management – the system must allocate the memory to several jobs. • Allocation of devices. 14 . New Delhi-63. U1.OS Features Needed for Multiprogramming • I/O routine supplied by the system. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • CPU scheduling – the system must choose among several jobs ready to run.

U1. On-line communication between the user and the system is provided. . New Delhi-63. A job swapped in and out of memory to the disk. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. it seeks the next “control statement” from the user’s keyboard. when the operating system finishes the execution of one command. by Parul Arora.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory).

by Parul Arora. small printers. • I/O devices – keyboards. • May run several different types of operating systems (Windows. • User convenience and responsiveness. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. MacOS. display screens. 16 . mice.. New Delhi-63. U1.Desktop Systems • Personal computers – computer system dedicated to a single user. UNIX.

17 . communication usually takes place through the shared memory.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. New Delhi-63. by Parul Arora.. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Tightly coupled system – processors share memory and a clock.

U1. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Parallel Systems (Cont.. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. Many processes can run at once without performance deterioration. 18 . master processor schedules and allocated work to slave processors.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. by Parul Arora.

. by Parul Arora. U1. 19 . New Delhi-63.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

such as high-speed buses or telephone lines. processors communicate with one another through various communications lines. 20 . • Loosely coupled system – each processor has its own local memory.Distributed Systems • Distribute the computation among several physical processors.. by Parul Arora. • Advantages of distributed systems. New Delhi-63. U1. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. by Parul Arora. 21 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Distributed Systems (cont) • Requires networking infrastructure. New Delhi-63. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.

U1. 22 . New Delhi-63. by Parul Arora.General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Clustered Systems • Clustering allows two or more systems to share storage. by Parul Arora. U1. • Provides high reliability. • Symmetric clustering: all N hosts are running the application. • Asymmetric clustering: one server runs the application while other servers standby. 23 .

New Delhi-63. medical imaging systems. industrial control systems.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. U1. by Parul Arora. • Well-defined fixed-time constraints. • Real-Time systems may be either hard or soft real-time. and some display systems. 24 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. not supported by general-purpose operating systems. by Parul Arora. data stored in short term memory.Real-Time Systems (Cont. or read-only memory (ROM) Conflicts with time-sharing systems. U1. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. . virtual reality) requiring advanced operating-system features. New Delhi-63.) • Hard real-time: Secondary storage limited or absent.

by Parul Arora. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 26 .Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. U1.

Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 27 . by Parul Arora. U1.

by Parul Arora.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 28 . U1.. New Delhi-63.

Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63. by Parul arora U1. 29 .

.how memory is structured Memory management .Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . U1. 30 .strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 31 .. U1.

U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 32 . • User programs go through several steps before being run.Background • Program must be brought into memory and placed within a process for it to be run. New Delhi-63.. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program.

must recompile code if starting location changes.. by Parul Arora.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.. Need hardware support for address maps (e. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.g. absolute code can be generated. 33 . • Load time: Must generate relocatable code if memory location is not known at compile time. base and limit registers). U1.

Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63. 34 . U1.

logical (virtual) and physical addresses differ in execution-time address-binding scheme. by Parul Arora.Logical vs. New Delhi-63.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. also referred to as virtual address. Logical address – generated by the CPU. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. 35 . Physical address – address seen by the memory unit.

• In MMU scheme. it never sees the real physical addresses. by Parul Arora. 36 . New Delhi-63. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Memory-Management Unit • Hardware device that maps virtual to physical address. • The user program deals with logical addresses.. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory.

by Parul Arora.. U1. New Delhi-63. 37 .Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.. New Delhi-63. 38 .Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. • No special support from the operating system is required implemented through program design. • Useful when large amounts of code are needed to handle infrequently occurring cases. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. unused routine is never loaded. by Parul Arora.

U1. 39 .Dynamic Linking • Linking postponed until execution time. used to locate the appropriate memory-resident library routine. • Dynamic linking is particularly useful for libraries. • Stub replaces itself with the address of the routine. • Operating system needed to check if routine is in processes’ memory address.. and executes the routine. by Parul Arora. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Small piece of code. stub.

40 . • Needed when process is larger than amount of memory allocated to it. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Overlays • Keep in memory only those instructions and data that are needed at any given time. by Parul Arora. New Delhi-63. no special support needed from operating system.. • Implemented by user.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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by Parul Arora. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. User processes then held in high memory. limit register contains range of logical addresses – each logical address must be less than the limit register. and from changing operating-system code and data. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. usually held in low memory with interrupt vector. New Delhi-63.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. 44 .. Relocation register contains value of smallest physical address. U1.

45 .Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. by Parul Arora.

Contiguous Allocation (Cont. holes of various size are scattered throughout memory. by Parul Arora. When a process arrives. it is allocated memory from a hole large enough to accommodate it.. 46 . U1. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) Multiple-partition allocation Hole – block of available memory. New Delhi-63.

Best-fit: Allocate the smallest hole that is big enough. U1.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. New Delhi-63.. must search entire list. Produces the largest leftover hole. 47 . unless ordered by size. Produces the smallest leftover hole. by Parul Arora. Worst-fit: Allocate the largest hole. must also search entire list. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

this size difference is memory internal to a partition. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. I/O problem Latch job in memory while it is involved in I/O. Do I/O only into OS buffers. Compaction is possible only if relocation is dynamic.. New Delhi-63. U1. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. and is done at execution time. but not being used. by Parul Arora. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. 48 . but it is not contiguous.Fragmentation • External Fragmentation – total memory space exists to satisfy a request.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. • To run a program of size n pages. between 512 bytes and 8192 bytes). • Keep track of all free frames.Paging • Logical address space of a process can be noncontiguous. • Internal fragmentation. by Parul Arora. process is allocated physical memory whenever the latter is available.. • Divide logical memory into blocks of same size called pages. need to find n free frames and load program. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. • Set up a page table to translate logical to physical addresses. New Delhi-63. 49 . U1.

Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. by Parul Arora. 50 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

51 . by Parul Arora. New Delhi-63..Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 52 . by Parul Arora. New Delhi-63.. U1.

New Delhi-63. U1.. by Parul Arora. 53 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 54 . by Parul Arora. New Delhi-63..

• Page-table length register (PRLR) indicates size of the page table. • Page-table base register (PTBR) points to the page table. by Parul Arora.Implementation of Page Table • Page table is kept in main memory. • In this scheme every data/instruction access requires two memory accesses.. 55 . U1. One for the page table and one for the data/instruction. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

A´´) If A´ is in associative register. 56 .Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. by Parul Arora.. New Delhi-63. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. get frame # out. U1.

.Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. New Delhi-63. 57 .

ration related to number of associative registers. by Parul Arora. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 58 . New Delhi-63.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. U1..

and is thus a legal page..Memory Protection • Memory protection implemented by associating protection bit with each frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. “invalid” indicates that the page is not in the process’ logical address space. by Parul Arora. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. U1. 59 .

. U1. 60 . New Delhi-63. by Parul Arora.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

61 . by Parul Arora.. U1.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

New Delhi-63. 62 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Hierarchical Page Tables • Break up the logical address space into multiple page tables.. U1. • A simple technique is a two-level page table.

the page number is further divided into: Thus. U1. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. New Delhi-63. Since the page table is paged. a page offset consisting of 12 bits. a 10-bit page offset. 63 .. by Parul Arora.

.Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 64 . New Delhi-63.

. 65 .Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. by Parul Arora.

• Virtual page numbers are compared in this chain searching for a match. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Hashed Page Tables • Common in address spaces > 32 bits. 66 . the corresponding physical frame is extracted. • The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. by Parul Arora. If a match is found.. U1.

by Parul Arora.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 67 . New Delhi-63.. U1.

but increases time needed to search the table when a page reference occurs. 68 . New Delhi-63. by Parul Arora. • Use hash table to limit the search to one — or at most a few — page-table entries. • Decreases memory needed to store each page table.. • Entry consists of the virtual address of the page stored in that real memory location. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. with information about the process that owns that page. U1.Inverted Page Table • One entry for each real page of memory.

New Delhi-63. by Parul Arora.. U1. 69 .Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

window systems). The pages for the private code and data can appear anywhere in the logical address space. Private code and data Each process keeps a separate copy of the code and data. Shared code must appear in same location in the logical address space of all processes. U1.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. text editors..e.. by Parul Arora. New Delhi-63. 70 . compilers.

Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. by Parul Arora.. 71 .

New Delhi-63. U1. procedure. A segment is a logical unit such as: main program. function. object. symbol table. common block.Segmentation Memory-management scheme that supports user view of memory. method. 72 .. A program is a collection of segments. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. global variables. stack. by Parul Arora. local variables.

. New Delhi-63. U1.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 73 . by Parul Arora.

U1. 74 ..Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

offset>. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR.. Segment table – maps two-dimensional physical addresses. each table entry has: base – contains the starting physical address where the segments reside in memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • • • Segment-table base register (STBR) points to the segment table’s location in memory. U1. 75 .Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. limit – specifies the length of the segment. New Delhi-63. by Parul Arora.

Segmentation Architecture (Cont. U1. 76 . dynamic by segment table • Sharing. by Parul Arora.) • Relocation.. shared segments same segment number • Allocation. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

• Since segments vary in length. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.Segmentation Architecture (Cont. 77 . code sharing occurs at segment level. memory allocation is a dynamic storage-allocation problem. New Delhi-63..) • Protection. U1. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1. by Parul Arora.. 78 . New Delhi-63.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 79 . by Parul Arora. New Delhi-63.. U1.

.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 80 . U1. New Delhi-63. by Parul Arora.

U1. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. but rather the base address of a page table for this segment. by Parul Arora. 81 .Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

. U1. 82 .MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. 83 . the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.Segmentation with Paging – Intel 386 As shown in the following diagram.

Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. 84 . by Parul Arora.

85 . New Delhi-63.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1.

Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. by Parul Arora. • Describe the reason for and use of cache memory. cache memory. auxiliary memory) and processor speed. • Discuss the concept of thrashing. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Summarize the principles of virtual memory as applied to caching and paging. New Delhi-63. • Evaluate the trade-offs in terms of memory size (main memory. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. 86 .. U1.

Background • Virtual memory – separation of user logical memory from physical memory. Allows for more efficient process creation. Logical address space can therefore be much larger than physical address space. Only part of the program needs to be in memory for execution. New Delhi-63.. by Parul Arora. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . • Virtual memory can be implemented via: Demand paging Demand segmentation U1. Allows address spaces to be shared by several processes.

. by Parul Arora. U1. New Delhi-63. 88 .Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.Demand Paging Bring a page into memory only when it is needed.. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 89 . New Delhi-63.

by Parul Arora. New Delhi-63..Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 90 . U1.

91 . but valid-invalid bit 1 Example of a page table snapshot.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. New Delhi-63. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. by Parul Arora. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.

Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1. 92 .

Restart instruction: Least Recently Used block move U1. Reset tables. • • • • Get empty frame. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . Just not in memory. New Delhi-63. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. Swap page into frame. by Parul Arora.Page Fault • If there is ever a reference to a page.. validation bit = 1.

by Parul Arora.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 94 . New Delhi-63. U1.

New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but not really in use. • Same page may be brought into memory several times. swap it out. algorithm performance – want an algorithm which will result in minimum number of page faults. 95 . U1.. by Parul Arora.What happens if there is no free frame? • Page replacement – find some page in memory.

every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. New Delhi-63. U1. 96 . by Parul Arora.0 if p = 0 no page faults if p = 1..

Swap Page Time = 10 msec = 10. U1. by Parul Arora.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 97 .. New Delhi-63.

. New Delhi-63. 98 . by Parul Arora. U1.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• COW allows more efficient process creation as only modified pages are copied. U1. 99 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.If either process modifies a shared page. New Delhi-63.. by Parul Arora. only then is the page copied. • Free pages are allocated from a pool of zeroed-out pages.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory.

• A file is initially read using demand paging. • Also allows several processes to map the same file allowing the pages in memory to be shared.. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. New Delhi-63. . • Simplifies file access by treating file I/O through memory rather than read() write() system calls. A page-sized portion of the file is read from the file system into a physical page.

New Delhi-63. by Parul Arora. U1..Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 101 .

• Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. by Parul Arora. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 102 . • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement.

103 . New Delhi-63.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora.

U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. use it.. use a page replacement algorithm to select a victim frame. 104 . New Delhi-63.If there is no free frame.If there is a free frame.Basic Page Replacement • Find the location of the desired page on disk. • Restart the process. • Find a free frame: . . Update the page and frame tables. • Read the desired page into the (newly) free frame.

New Delhi-63. U1. 105 .. by Parul Arora.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. 1. 1.. In all our examples. 4. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. 3. 2. 2. by Parul Arora. the reference string is 1. 5. 106 . 4. U1. 5.Page Replacement Algorithms Want lowest page-fault rate. 3.

107 . U1..Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

2. 4. 2.First-In-First-Out (FIFO) Algorithm Reference string: 1. 5. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 1. New Delhi-63. 1.. 2. 4. 108 . 3. U1. 3.

First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. U1. New Delhi-63. 109 .

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

by Parul Arora.Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 113 . U1.

by Parul Arora. 2. 2. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 1. 5. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. 2. When a page needs to be changed. every time page is referenced through this entry. 114 . 1. copy the clock into the counter.Least Recently Used (LRU) Algorithm Reference string: 1. 3. U1. New Delhi-63. 4. 4. look at the counters to determine which are to change. 3.

by Parul Arora.. 115 . U1.LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

116 .LRU Algorithm (Cont. New Delhi-63..) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

U1. by Parul Arora. 117 . New Delhi-63.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

then: set reference bit 0. Clock replacement. If page to be replaced (in clock order) has reference bit = 1. We do not know the order. rules. initially = 0 When page is referenced bit set to 1. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Replace the one which is 0 (if one exists).LRU Approximation Algorithm Reference bit With each page associate a bit. leave page in memory. Second chance Need reference bit. U1. replace next page (in clock order). by Parul Arora. however. 118 . New Delhi-63.

New Delhi-63. U1.. 119 . by Parul Arora.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. New Delhi-63. by Parul Arora.Counting Algorithms • Keep a counter of the number of references that have been made to each page. LFU Algorithm: replaces page with smallest count. U1. 120 .. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Allocation of Frames • Each process needs minimum number of pages. 2 pages to handle from. 121 .. might span 2 pages. • Two major allocation schemes. U1. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 2 pages to handle to.

by Parul Arora.Fixed Allocation • Equal allocation – e. New Delhi-63. if 100 frames and 5 processes. • Proportional allocation – Allocate according to the size of process. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management.g. U1.. 122 . give each 20 pages..

New Delhi-63. by Parul Arora. • If process Pi generates a page fault. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. 123 . select for replacement a frame from a process with lower priority number. select for replacement one of its frames..

by Parul Arora.Global vs. New Delhi-63. • Local replacement – each process selects from only its own set of allocated frames. U1.. 124 . Local Allocation • Global replacement – process selects a replacement frame from the set of all frames. one process can take a frame from another. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. the page-fault rate is very high. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Thrashing ≡ a process is busy swapping pages in and out. operating system thinks that it needs to increase the degree of multiprogramming. by Parul Arora. New Delhi-63. 125 .Thrashing If a process does not have “enough” pages. This leads to: low CPU utilization. U1. another process added to the system.

by Parul Arora..Thrashing Why does paging work? Locality model Process migrates from one locality to another. New Delhi-63. U1. Localities may overlap. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 126 .

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

process loses frame.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 130 . U1. by Parul Arora. If actual rate too low. process gains frame. New Delhi-63. If actual rate too high.

New Delhi-63. U1. by Parul Arora.Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 131 ..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 132 . Otherwise there is a high degree of page faults. New Delhi-63. U1. TLB Reach = (TLB Size) X (Page Size) Ideally. the working set of each process is stored in the TLB.The amount of memory accessible from the TLB.) TLB Reach . by Parul Arora.Other Considerations (Cont..

. • Provide Multiple Page Sizes. U1. by Parul Arora. This may lead to an increase in fragmentation as not all applications require a large page size. 133 .Increasing the Size of the TLB • Increase the Page Size. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

j < A.. by Parul Arora. Each row is stored in one page Program 1 for (j = 0. New Delhi-63.j] = 0.) Program structure int A[][] = new int[1024][1024].Other Considerations (Cont. i < A.j] = 0. i < A.length.length.length. i++) for (j = 0. j++) for (i = 0. j++) A[i. U1. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 134 .length. 1024 x 1024 page faults Program 2 for (i = 0. i++) A[i. j < A.

Conclusion • • • • • Operating systems provide an environment for development and execution of programs. New Delhi-63. by Parul Arora. Virtual memory allows extremely large processes to be run. . Memory management algorithms differ in many concepts. Multiprogramming increased the performance of computer system.and also allows degree of multiprogramming to be raised.. Virtual memory frees application programers from worrying about memory availability U1. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. Least Recently Used..Summary • In the introduction. Four major categories of operating systems are batch. and Least Frequently U1. . First In First Out. 136 Used. Resources are any objects that can be allocated within a system. personal computing and dedicated. by Parul Arora. we saw that software can be roughly divided into two groups: application software and system software. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Second Chance. timesharing. and the operating system is responsible for managing them. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. Policies for determining which pages to load and remove from memory include Random Replacement. Operating systems are a type of system software that allow applications to interface with computer hardware. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames.

New Delhi-63.Review Questions (OBJ) 1. a) Polling b) Interrupt c) System Call d) None of the above 2. 137 . The Hardware mechanism that enables a device to notify the CPU is called __________.. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

. by Parul Arora.Review Questions (OBJ) 3. 4. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. Virtual memory is __________. U1. New Delhi-63. 138 . _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 139 . Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6.Review Questions (OBJ) 5. New Delhi-63.. by Parul Arora. The term " Operating System " means ________.

The principle of locality of reference justifies the use of ________. ) Routine a) b) c) d) is not loaded until it is called.Review Questions (OBJ) 7. All routines are kept on disk in a relocatable load format. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 140 .. The main program is loaded into memory & is executed. by Parul Arora. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. U1.

. the total number of page faults caused by the process will be __________. a) 10 b) 7 c) 8 d) 9 10. 141 . a) Program structure b) Program size c) Primary storage size d) None of the above U1. by Parul Arora. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO.Review Questions (OBJ) 9. ) The problem of thrashing is effected scientifically by ________. New Delhi-63. If all page frames are initially empty. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

How do MULTICS and UNIX differ? 7. 142 . List the four steps that are necessary to run a program on a completely dedicated machine 5. by Parul Arora. What are the three main purposes of an operating system? 4. Explain the difference between internal and external fragmentation 10. New Delhi-63. How do I/O-bound and CPU-bound programs differ? 6. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Explain the difference between logical and physical addresses. 9.Review Questions (Short) 1.. How does a real-time system differ from time-share? 8. What are the main differences between operating systems for mainframe computers and personal computers? 3. What is the main advantage of multiprogramming 2. U1.

What are overlays? 12. Describe the actions taken by the operating system when a page fault occurs. New Delhi-63. What is Belady’s anomaly? 19. How do global and local allocation differ? 20. Why is there a valid/invalid bit? Where is it kept? 18. 16. What is meant by locality? 21. What is reentrant code? 14. U1. When do page faults occur? 15. by Parul Arora. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (Short) 11. How was memory mapping used in extending the usefulness of minicomputers? 13. What is virtual memory? 17. 143 ..

Given memory partitions of 100K. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 5. List ways to implement LRU. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5. 9. 144 . and Worst-?t algorithms place processes of 212K. 7. how would each of the First-?t. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 300K. a. 112K. 500K. 7. 4. 1. 200K. U1. for four page frames? 1. Consider a paging system with the page table stored in memory. Best-?t. 5. 4. 4. if the entry is there. by Parul Arora. and 600K (in order).)If we add associative registers.. 9. to determine which page is victim. 3. 2. 2. how long does a paged memory reference take? b. 4.)If a memory reference takes 200 nanoseconds. 8. 3. 417K. 7.Review Questions (Long) 1. and 75 percent of all pagetable references are found in the associative registers.) 3. How many page faults occur for your algorithm for the following reference string. 8. 6. New Delhi-63. 8.

.Recommended reading • Silbersachatz and Galvin. by Parul Arora..2001 • Madnick E.. New Delhi-63. 145 . 4th Edition.. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. “Operating System Concepts” Peason. 2001 • "Operating Systems” Tannenbaum PHI.6th Ed. Donovan J. U1. ”Operating System”: TMH.

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