OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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4 .Learning Objective Understand the purpose of the operating system Distinguish between a resource. a program.. New Delhi-63. U1. by Parul Arora. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

5 .. by Parul Arora. New Delhi-63. U1.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. Make the computer system convenient to use. U1.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. • Use the computer hardware in an efficient manner. New Delhi-63.. • Operating system goals: Execute user programs and make solving user problems easier. 6 . by Parul Arora.

7 .. 4. video games. Hardware – provides basic computing resources (CPU. 2. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. other computers). by Parul Arora. 3.Computer System Components 1. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. I/O devices). New Delhi-63. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. Users (people. database systems. memory. business programs). machines.

Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 8 .. by Parul Arora.

New Delhi-63.Operating System Definitions • Resource allocator – manages and allocates resources. by Parul Arora. U1. • Kernel – the one program running at all times (all else being application programs).. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Control program – controls the execution of user programs and operations of I/O devices . 9 .

10 . New Delhi-63. U1.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.

U1. First rudimentary operating system. New Delhi-63. by Parul Arora. 11 .Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another.. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

12 . by Parul Arora. U1. New Delhi-63.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

13 . New Delhi-63. by Parul Arora..Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

OS Features Needed for Multiprogramming • I/O routine supplied by the system. 14 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Memory management – the system must allocate the memory to several jobs. • CPU scheduling – the system must choose among several jobs ready to run. • Allocation of devices.. U1. New Delhi-63. by Parul Arora.

15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. when the operating system finishes the execution of one command. by Parul Arora. U1.. On-line communication between the user and the system is provided. New Delhi-63. A job swapped in and out of memory to the disk.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). . it seeks the next “control statement” from the user’s keyboard.

. by Parul Arora. • User convenience and responsiveness. MacOS. • May run several different types of operating systems (Windows. • I/O devices – keyboards. small printers. New Delhi-63. U1. mice. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. UNIX. display screens.Desktop Systems • Personal computers – computer system dedicated to a single user. 16 . Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 17 . • Tightly coupled system – processors share memory and a clock. U1.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. communication usually takes place through the shared memory.

Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. New Delhi-63.. master processor schedules and allocated work to slave processors. 18 .Parallel Systems (Cont. Many processes can run at once without performance deterioration. U1. by Parul Arora.

. U1. by Parul Arora.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 19 . New Delhi-63.

processors communicate with one another through various communications lines. New Delhi-63.. 20 .Distributed Systems • Distribute the computation among several physical processors. by Parul Arora. such as high-speed buses or telephone lines. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Loosely coupled system – each processor has its own local memory. • Advantages of distributed systems. U1.

Distributed Systems (cont) • Requires networking infrastructure. New Delhi-63. U1. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 21 .

General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 22 . U1.. by Parul Arora. New Delhi-63.

New Delhi-63. U1. • Asymmetric clustering: one server runs the application while other servers standby. by Parul Arora. • Provides high reliability. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 23 ..Clustered Systems • Clustering allows two or more systems to share storage. • Symmetric clustering: all N hosts are running the application.

Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. and some display systems. U1. industrial control systems. • Well-defined fixed-time constraints. 24 .. by Parul Arora. • Real-Time systems may be either hard or soft real-time. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. medical imaging systems.

virtual reality) requiring advanced operating-system features. U1. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. by Parul Arora. . not supported by general-purpose operating systems. or read-only memory (ROM) Conflicts with time-sharing systems.) • Hard real-time: Secondary storage limited or absent.. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Real-Time Systems (Cont. data stored in short term memory.

U1.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. New Delhi-63.. 26 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1.. New Delhi-63.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 27 .

U1. 28 .. by Parul Arora. New Delhi-63.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

29 . New Delhi-63.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1.

. New Delhi-63. by Parul Arora.strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.how memory is structured Memory management . U1.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . 30 .

New Delhi-63. U1.. 31 . by Parul Arora.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. by Parul Arora.Background • Program must be brought into memory and placed within a process for it to be run. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. 32 . • User programs go through several steps before being run. U1..

. absolute code can be generated. 33 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. base and limit registers). • Load time: Must generate relocatable code if memory location is not known at compile time.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. New Delhi-63..g. must recompile code if starting location changes. Need hardware support for address maps (e. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.

U1. by Parul Arora. New Delhi-63.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 34 .

Logical vs. New Delhi-63. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. U1. Physical address – address seen by the memory unit. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. logical (virtual) and physical addresses differ in execution-time address-binding scheme. by Parul Arora.. Logical address – generated by the CPU. also referred to as virtual address. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 35 .

36 . the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. • In MMU scheme. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. it never sees the real physical addresses. by Parul Arora..Memory-Management Unit • Hardware device that maps virtual to physical address. • The user program deals with logical addresses.

Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 37 . by Parul Arora. U1.. New Delhi-63.

.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. unused routine is never loaded. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • No special support from the operating system is required implemented through program design. by Parul Arora. • Useful when large amounts of code are needed to handle infrequently occurring cases. 38 . U1.

New Delhi-63. • Small piece of code. stub. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Stub replaces itself with the address of the routine.. used to locate the appropriate memory-resident library routine.Dynamic Linking • Linking postponed until execution time. by Parul Arora. and executes the routine. 39 . • Operating system needed to check if routine is in processes’ memory address. • Dynamic linking is particularly useful for libraries.

U1. by Parul Arora. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Overlays • Keep in memory only those instructions and data that are needed at any given time. 40 . New Delhi-63. • Implemented by user. no special support needed from operating system. • Needed when process is larger than amount of memory allocated to it..

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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by Parul Arora.. and from changing operating-system code and data. U1. usually held in low memory with interrupt vector. Relocation register contains value of smallest physical address. 44 . User processes then held in high memory. • Single-partition allocation Relocation-register scheme used to protect user processes from each other.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. New Delhi-63. limit register contains range of logical addresses – each logical address must be less than the limit register. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 45 . by Parul Arora.

New Delhi-63. 46 . it is allocated memory from a hole large enough to accommodate it.Contiguous Allocation (Cont. When a process arrives.. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. holes of various size are scattered throughout memory.) Multiple-partition allocation Hole – block of available memory.

Best-fit: Allocate the smallest hole that is big enough. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 47 . Produces the smallest leftover hole. Worst-fit: Allocate the largest hole. by Parul Arora. Produces the largest leftover hole.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. New Delhi-63.. U1. unless ordered by size. must also search entire list. must search entire list.

this size difference is memory internal to a partition.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. but not being used. but it is not contiguous.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. I/O problem Latch job in memory while it is involved in I/O. 48 . Do I/O only into OS buffers. Compaction is possible only if relocation is dynamic. U1. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. by Parul Arora. and is done at execution time.

New Delhi-63.. 49 .Paging • Logical address space of a process can be noncontiguous. U1. • To run a program of size n pages. • Divide logical memory into blocks of same size called pages. process is allocated physical memory whenever the latter is available. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. need to find n free frames and load program. • Keep track of all free frames. • Set up a page table to translate logical to physical addresses. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. by Parul Arora. between 512 bytes and 8192 bytes). • Internal fragmentation.

. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 50 . U1. New Delhi-63.

51 .. U1. by Parul Arora. New Delhi-63.Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. by Parul Arora. 52 .

Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 53 .. New Delhi-63.

. New Delhi-63. 54 .Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

• The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. One for the page table and one for the data/instruction. 55 . • Page-table base register (PTBR) points to the page table. New Delhi-63. • Page-table length register (PRLR) indicates size of the page table.Implementation of Page Table • Page table is kept in main memory.. • In this scheme every data/instruction access requires two memory accesses. by Parul Arora. U1.

U1. get frame # out. New Delhi-63. by Parul Arora.. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 56 .Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. A´´) If A´ is in associative register.

New Delhi-63.. U1. 57 .Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

New Delhi-63.. by Parul Arora. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ration related to number of associative registers.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. U1. 58 .

U1.. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. “invalid” indicates that the page is not in the process’ logical address space.Memory Protection • Memory protection implemented by associating protection bit with each frame. 59 . and is thus a legal page. by Parul Arora.

by Parul Arora. 60 . U1. New Delhi-63.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 61 . U1. by Parul Arora. New Delhi-63.

Hierarchical Page Tables • Break up the logical address space into multiple page tables. 62 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. • A simple technique is a two-level page table.

a 10-bit page offset. a page offset consisting of 12 bits. 63 . New Delhi-63. by Parul Arora. the page number is further divided into: Thus..Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. U1. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. Since the page table is paged.

64 . U1.. New Delhi-63. by Parul Arora.Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. by Parul Arora..Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 65 . U1.

New Delhi-63. • Virtual page numbers are compared in this chain searching for a match. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • The virtual page number is hashed into a page table.. If a match is found. This page table contains a chain of elements hashing to the same location. the corresponding physical frame is extracted. U1. 66 .Hashed Page Tables • Common in address spaces > 32 bits.

New Delhi-63.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 67 . U1. by Parul Arora.

New Delhi-63. U1. 68 . with information about the process that owns that page. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Entry consists of the virtual address of the page stored in that real memory location. but increases time needed to search the table when a page reference occurs.. • Use hash table to limit the search to one — or at most a few — page-table entries.Inverted Page Table • One entry for each real page of memory. • Decreases memory needed to store each page table.

69 . U1.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63.

New Delhi-63. window systems).Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. compilers.. text editors. Private code and data Each process keeps a separate copy of the code and data. U1. by Parul Arora.e.. The pages for the private code and data can appear anywhere in the logical address space. 70 . Shared code must appear in same location in the logical address space of all processes. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63. by Parul Arora. 71 .

local variables.Segmentation Memory-management scheme that supports user view of memory. New Delhi-63. function. method. A segment is a logical unit such as: main program. common block. symbol table. global variables. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. A program is a collection of segments. procedure. object. stack. 72 .. by Parul Arora.

New Delhi-63. by Parul Arora. U1.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 73 ..

74 . U1. New Delhi-63. by Parul Arora.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

• • • Segment-table base register (STBR) points to the segment table’s location in memory. U1. offset>.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Segment table – maps two-dimensional physical addresses. by Parul Arora. each table entry has: base – contains the starting physical address where the segments reside in memory. limit – specifies the length of the segment. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. 75 . New Delhi-63.

U1. by Parul Arora.) • Relocation. 76 . shared segments same segment number • Allocation. New Delhi-63.. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Architecture (Cont. dynamic by segment table • Sharing.

New Delhi-63. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.Segmentation Architecture (Cont.) • Protection. code sharing occurs at segment level. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Since segments vary in length. memory allocation is a dynamic storage-allocation problem.. U1. 77 .

. 78 . U1.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

New Delhi-63. U1..Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 79 . by Parul Arora.

80 . by Parul Arora.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1..

Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. but rather the base address of a page table for this segment. by Parul Arora.. U1. 81 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

New Delhi-63. U1. 82 .MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora..

83 .. U1. by Parul Arora. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.Segmentation with Paging – Intel 386 As shown in the following diagram. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

84 . U1.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63.

Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63. 85 . by Parul arora U1.

• Discuss the concept of thrashing. by Parul Arora. • Summarize the principles of virtual memory as applied to caching and paging. auxiliary memory) and processor speed.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. 86 . cache memory. U1. • Describe the reason for and use of cache memory. New Delhi-63. • Evaluate the trade-offs in terms of memory size (main memory..

. Logical address space can therefore be much larger than physical address space. Only part of the program needs to be in memory for execution. Allows for more efficient process creation. . New Delhi-63. Allows address spaces to be shared by several processes. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Background • Virtual memory – separation of user logical memory from physical memory. by Parul Arora. • Virtual memory can be implemented via: Demand paging Demand segmentation U1.

by Parul Arora. 88 . New Delhi-63..Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63.Demand Paging Bring a page into memory only when it is needed. U1.. 89 . Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

90 .Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. by Parul Arora.

U1. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. New Delhi-63. but valid-invalid bit 1 Example of a page table snapshot. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 91 . by Parul Arora.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory.

92 . U1.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. by Parul Arora.

Restart instruction: Least Recently Used block move U1.Page Fault • If there is ever a reference to a page. Just not in memory. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Swap page into frame. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. Reset tables. by Parul Arora. . New Delhi-63.. • • • • Get empty frame. validation bit = 1.

U1.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 94 . by Parul Arora.. New Delhi-63.

. • Same page may be brought into memory several times. but not really in use. algorithm performance – want an algorithm which will result in minimum number of page faults. by Parul Arora. 95 . swap it out. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.What happens if there is no free frame? • Page replacement – find some page in memory. New Delhi-63.

New Delhi-63. 96 . U1. by Parul Arora.0 if p = 0 no page faults if p = 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1.

Swap Page Time = 10 msec = 10..000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. New Delhi-63. 97 .

by Parul Arora.. New Delhi-63. 98 . U1.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

only then is the page copied.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory..If either process modifies a shared page. New Delhi-63. by Parul Arora. U1. • Free pages are allocated from a pool of zeroed-out pages. • COW allows more efficient process creation as only modified pages are copied. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 99 .

. • Also allows several processes to map the same file allowing the pages in memory to be shared. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. New Delhi-63. A page-sized portion of the file is read from the file system into a physical page. U1. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. by Parul Arora. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • A file is initially read using demand paging..Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory.

. U1.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 101 . New Delhi-63.

• Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. 102 . U1.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. by Parul Arora. New Delhi-63.

by Parul Arora. 103 . New Delhi-63.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..

• Read the desired page into the (newly) free frame.Basic Page Replacement • Find the location of the desired page on disk.If there is no free frame. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.If there is a free frame. New Delhi-63. use a page replacement algorithm to select a victim frame. • Find a free frame: . 104 . . U1. Update the page and frame tables.. use it. • Restart the process.

.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 105 . U1.

3. by Parul Arora.Page Replacement Algorithms Want lowest page-fault rate. 5. 3. 1. 4. 1. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. New Delhi-63. 106 . the reference string is 1. In all our examples. 2. 2. 2.. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 5.

U1.. by Parul Arora. 107 .Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

2. 5. 3. 2. 1. 2. 1. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 108 ..First-In-First-Out (FIFO) Algorithm Reference string: 1. 3. New Delhi-63. by Parul Arora. U1. 4. 4.

109 .First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1.

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

. New Delhi-63. by Parul Arora. 113 . U1.Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 1. New Delhi-63. by Parul Arora. copy the clock into the counter.Least Recently Used (LRU) Algorithm Reference string: 1. 2. every time page is referenced through this entry. 3. 2. 4. U1. 3. 114 . 4. look at the counters to determine which are to change. 5. When a page needs to be changed. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. 2. 1.

U1.LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 115 ..

116 . U1.LRU Algorithm (Cont.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63.

Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 117 . by Parul Arora. U1..

then: set reference bit 0. We do not know the order. by Parul Arora. New Delhi-63. If page to be replaced (in clock order) has reference bit = 1.LRU Approximation Algorithm Reference bit With each page associate a bit. Second chance Need reference bit. however. leave page in memory.. rules. 118 . Clock replacement. U1. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. initially = 0 When page is referenced bit set to 1. Replace the one which is 0 (if one exists). replace next page (in clock order).

New Delhi-63. 119 .. by Parul Arora. U1.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. LFU Algorithm: replaces page with smallest count. New Delhi-63.Counting Algorithms • Keep a counter of the number of references that have been made to each page. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. 120 .. by Parul Arora.

New Delhi-63. U1. • Two major allocation schemes. by Parul Arora.Allocation of Frames • Each process needs minimum number of pages. 121 .. 2 pages to handle from. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. might span 2 pages. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. 2 pages to handle to.

if 100 frames and 5 processes.. 122 . by Parul Arora. give each 20 pages. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.g. • Proportional allocation – Allocate according to the size of process.Fixed Allocation • Equal allocation – e.. New Delhi-63.

U1.. by Parul Arora. select for replacement a frame from a process with lower priority number. select for replacement one of its frames. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 123 . • If process Pi generates a page fault.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. New Delhi-63.

U1. by Parul Arora. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames. 124 .Global vs.. • Local replacement – each process selects from only its own set of allocated frames. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. one process can take a frame from another. New Delhi-63.

operating system thinks that it needs to increase the degree of multiprogramming. New Delhi-63. U1. the page-fault rate is very high. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. another process added to the system.. This leads to: low CPU utilization. Thrashing ≡ a process is busy swapping pages in and out.Thrashing If a process does not have “enough” pages. 125 .

by Parul Arora. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Localities may overlap. New Delhi-63.Thrashing Why does paging work? Locality model Process migrates from one locality to another. 126 . U1..

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. If actual rate too high. 130 . by Parul Arora. process loses frame. New Delhi-63.. If actual rate too low. U1.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. process gains frame.

131 .Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1.

the working set of each process is stored in the TLB. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. Otherwise there is a high degree of page faults. TLB Reach = (TLB Size) X (Page Size) Ideally..The amount of memory accessible from the TLB. 132 .Other Considerations (Cont.) TLB Reach .

Increasing the Size of the TLB • Increase the Page Size. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Provide Multiple Page Sizes. 133 . This may lead to an increase in fragmentation as not all applications require a large page size. by Parul Arora. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation.. U1.

) Program structure int A[][] = new int[1024][1024].length. 134 . 1024 x 1024 page faults Program 2 for (i = 0. j < A. j < A.length.length.j] = 0. i < A. j++) A[i. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. i++) for (j = 0. Each row is stored in one page Program 1 for (j = 0.. i++) A[i. U1. New Delhi-63.Other Considerations (Cont. i < A. j++) for (i = 0.j] = 0.length. by Parul Arora.

and also allows degree of multiprogramming to be raised.Conclusion • • • • • Operating systems provide an environment for development and execution of programs.. Memory management algorithms differ in many concepts. by Parul Arora. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. Virtual memory allows extremely large processes to be run. . Multiprogramming increased the performance of computer system. Virtual memory frees application programers from worrying about memory availability U1.

Resources are any objects that can be allocated within a system. First In First Out.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. we saw that software can be roughly divided into two groups: application software and system software. Four major categories of operating systems are batch. Least Recently Used. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. 136 Used. Second Chance.Summary • In the introduction. . timesharing. personal computing and dedicated. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. and Least Frequently U1. by Parul Arora. New Delhi-63. Operating systems are a type of system software that allow applications to interface with computer hardware. Policies for determining which pages to load and remove from memory include Random Replacement. and the operating system is responsible for managing them.

U1.. The Hardware mechanism that enables a device to notify the CPU is called __________. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 1. 137 . by Parul Arora. a) Polling b) Interrupt c) System Call d) None of the above 2. New Delhi-63.

U1. New Delhi-63. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. Virtual memory is __________. by Parul Arora. 138 . _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Review Questions (OBJ) 3. 4.

by Parul Arora. U1. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 5.. 139 . Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. The term " Operating System " means ________. New Delhi-63.

U1.Review Questions (OBJ) 7. The main program is loaded into memory & is executed.. ) Routine a) b) c) d) is not loaded until it is called. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. 140 . by Parul Arora. The principle of locality of reference justifies the use of ________. All routines are kept on disk in a relocatable load format.

141 .Review Questions (OBJ) 9. a) Program structure b) Program size c) Primary storage size d) None of the above U1. the total number of page faults caused by the process will be __________. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. ) The problem of thrashing is effected scientifically by ________. If all page frames are initially empty. by Parul Arora.. a) 10 b) 7 c) 8 d) 9 10. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

How do MULTICS and UNIX differ? 7. U1. What is the main advantage of multiprogramming 2. What are the main differences between operating systems for mainframe computers and personal computers? 3. Explain the difference between internal and external fragmentation 10. 142 . How does a real-time system differ from time-share? 8. What are the three main purposes of an operating system? 4. New Delhi-63. 9. by Parul Arora. Explain the difference between logical and physical addresses. List the four steps that are necessary to run a program on a completely dedicated machine 5.. How do I/O-bound and CPU-bound programs differ? 6. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (Short) 1.

Describe the actions taken by the operating system when a page fault occurs. What is Belady’s anomaly? 19. 143 .. What is virtual memory? 17. What is reentrant code? 14. What are overlays? 12. Why is there a valid/invalid bit? Where is it kept? 18. When do page faults occur? 15. 16. How do global and local allocation differ? 20. What is meant by locality? 21. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How was memory mapping used in extending the usefulness of minicomputers? 13. U1. New Delhi-63.Review Questions (Short) 11. by Parul Arora.

by Parul Arora. and 75 percent of all pagetable references are found in the associative registers. How many page faults occur for your algorithm for the following reference string. 112K. 8.)If we add associative registers. 3. Consider a paging system with the page table stored in memory. 417K..) 3. how long does a paged memory reference take? b. 500K. for four page frames? 1. 7. 6. U1. Best-?t. and 600K (in order). Given memory partitions of 100K. 4. 1. 2. to determine which page is victim. how would each of the First-?t.)If a memory reference takes 200 nanoseconds. 7. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 5. if the entry is there. 300K. 4. 144 . 4. 4. 8.Review Questions (Long) 1. 4. 5. List ways to implement LRU. New Delhi-63. 200K. 3. 7. a. 8. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 9. 9. 2. and Worst-?t algorithms place processes of 212K. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 5.

2001 • Madnick E.. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. “Operating System Concepts” Peason. 2001 • "Operating Systems” Tannenbaum PHI. 145 . by Parul Arora.6th Ed. ”Operating System”: TMH. New Delhi-63.Recommended reading • Silbersachatz and Galvin.. 4th Edition... Donovan J. U1.

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