OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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U1. a program.Learning Objective Understand the purpose of the operating system Distinguish between a resource. by Parul Arora. New Delhi-63.. 4 . and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. by Parul Arora. 5 . U1. New Delhi-63.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. • Operating system goals: Execute user programs and make solving user problems easier. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. U1.. New Delhi-63. 6 . • Use the computer hardware in an efficient manner. Make the computer system convenient to use.

Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. 4. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. New Delhi-63. U1.Computer System Components 1. Users (people. 7 . machines. business programs). other computers). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. video games.. Hardware – provides basic computing resources (CPU. I/O devices). 3. by Parul Arora. database systems. memory. 2.

8 . by Parul Arora. New Delhi-63..Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • Control program – controls the execution of user programs and operations of I/O devices . by Parul Arora. • Kernel – the one program running at all times (all else being application programs).Operating System Definitions • Resource allocator – manages and allocates resources. 9 . U1. New Delhi-63.

. U1. New Delhi-63. 10 . by Parul Arora.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. First rudimentary operating system. U1. New Delhi-63. by Parul Arora.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. 11 .

U1..Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 12 .

U1. 13 . New Delhi-63.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.

• CPU scheduling – the system must choose among several jobs ready to run.. • Allocation of devices. • Memory management – the system must allocate the memory to several jobs. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.OS Features Needed for Multiprogramming • I/O routine supplied by the system. 14 . New Delhi-63.

by Parul Arora. U1.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). when the operating system finishes the execution of one command.. it seeks the next “control statement” from the user’s keyboard. . 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A job swapped in and out of memory to the disk. New Delhi-63. On-line communication between the user and the system is provided.

MacOS. by Parul Arora. display screens. • User convenience and responsiveness. • I/O devices – keyboards. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. • May run several different types of operating systems (Windows.Desktop Systems • Personal computers – computer system dedicated to a single user. UNIX. New Delhi-63. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. mice. small printers. U1. 16 ..

communication usually takes place through the shared memory. New Delhi-63.. • Tightly coupled system – processors share memory and a clock. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. 17 . U1.

New Delhi-63.Parallel Systems (Cont. 18 . U1. by Parul Arora.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Many processes can run at once without performance deterioration. master processor schedules and allocated work to slave processors.

Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 19 .. by Parul Arora. New Delhi-63. U1.

such as high-speed buses or telephone lines. 20 .Distributed Systems • Distribute the computation among several physical processors. by Parul Arora. • Advantages of distributed systems. New Delhi-63. • Loosely coupled system – each processor has its own local memory. U1. processors communicate with one another through various communications lines. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63. 21 .Distributed Systems (cont) • Requires networking infrastructure. by Parul Arora. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.

General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.. New Delhi-63. 22 .

• Asymmetric clustering: one server runs the application while other servers standby. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. • Provides high reliability.Clustered Systems • Clustering allows two or more systems to share storage. 23 . by Parul Arora. • Symmetric clustering: all N hosts are running the application. U1.

by Parul Arora. 24 . New Delhi-63. • Real-Time systems may be either hard or soft real-time. • Well-defined fixed-time constraints..Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. industrial control systems. medical imaging systems. U1. and some display systems. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

not supported by general-purpose operating systems. New Delhi-63.) • Hard real-time: Secondary storage limited or absent. U1.Real-Time Systems (Cont. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. data stored in short term memory. or read-only memory (ROM) Conflicts with time-sharing systems. . by Parul Arora. virtual reality) requiring advanced operating-system features.. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1. 26 .Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens..

New Delhi-63. 27 . U1. by Parul Arora.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

. U1.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 28 . New Delhi-63.

Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 29 . by Parul arora U1. New Delhi-63.

how memory is structured Memory management . 30 .Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . U1. New Delhi-63..strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

New Delhi-63..Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 31 .

• User programs go through several steps before being run.. New Delhi-63. 32 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. by Parul Arora.Background • Program must be brought into memory and placed within a process for it to be run.

• Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.g. by Parul Arora. absolute code can be generated.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. U1.. • Load time: Must generate relocatable code if memory location is not known at compile time. New Delhi-63.. must recompile code if starting location changes. Need hardware support for address maps (e. 33 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. base and limit registers).

Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 34 .. by Parul Arora. New Delhi-63. U1.

also referred to as virtual address. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes.. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. 35 . logical (virtual) and physical addresses differ in execution-time address-binding scheme. by Parul Arora.Logical vs. New Delhi-63. Physical address – address seen by the memory unit. U1. Logical address – generated by the CPU. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Memory-Management Unit • Hardware device that maps virtual to physical address. 36 . the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. by Parul Arora. • In MMU scheme.. U1. • The user program deals with logical addresses. New Delhi-63. it never sees the real physical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. 37 .Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1.

38 . • No special support from the operating system is required implemented through program design. unused routine is never loaded. • Useful when large amounts of code are needed to handle infrequently occurring cases. by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization.

• Dynamic linking is particularly useful for libraries. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Stub replaces itself with the address of the routine. • Small piece of code..Dynamic Linking • Linking postponed until execution time. and executes the routine. 39 . by Parul Arora. New Delhi-63. stub. used to locate the appropriate memory-resident library routine. • Operating system needed to check if routine is in processes’ memory address.

by Parul Arora. 40 . U1. • Implemented by user. • Needed when process is larger than amount of memory allocated to it..Overlays • Keep in memory only those instructions and data that are needed at any given time. no special support needed from operating system. New Delhi-63. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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usually held in low memory with interrupt vector. U1. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. User processes then held in high memory.. by Parul Arora. and from changing operating-system code and data. New Delhi-63. limit register contains range of logical addresses – each logical address must be less than the limit register. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. Relocation register contains value of smallest physical address. 44 .

U1. New Delhi-63. 45 .. by Parul Arora.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora..Contiguous Allocation (Cont. New Delhi-63. it is allocated memory from a hole large enough to accommodate it. holes of various size are scattered throughout memory. When a process arrives. U1.) Multiple-partition allocation Hole – block of available memory. 46 .

. U1. must also search entire list. Best-fit: Allocate the smallest hole that is big enough. Produces the smallest leftover hole.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. 47 . New Delhi-63. Worst-fit: Allocate the largest hole. by Parul Arora. unless ordered by size. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. must search entire list. Produces the largest leftover hole.

by Parul Arora. and is done at execution time. but not being used. New Delhi-63.. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. this size difference is memory internal to a partition. 48 . Do I/O only into OS buffers. I/O problem Latch job in memory while it is involved in I/O. U1. Compaction is possible only if relocation is dynamic. but it is not contiguous.

• Internal fragmentation. 49 . • Keep track of all free frames. between 512 bytes and 8192 bytes). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. • To run a program of size n pages. • Set up a page table to translate logical to physical addresses.. • Divide logical memory into blocks of same size called pages. New Delhi-63. process is allocated physical memory whenever the latter is available. U1.Paging • Logical address space of a process can be noncontiguous. need to find n free frames and load program. by Parul Arora.

by Parul Arora.. New Delhi-63. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. 50 .

U1. 51 .Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora.

New Delhi-63..Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 52 . by Parul Arora. U1.

. U1. by Parul Arora. 53 . New Delhi-63.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

54 .. by Parul Arora. U1.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

• Page-table base register (PTBR) points to the page table. U1. New Delhi-63. • In this scheme every data/instruction access requires two memory accesses. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. One for the page table and one for the data/instruction. 55 . • Page-table length register (PRLR) indicates size of the page table..Implementation of Page Table • Page table is kept in main memory. by Parul Arora.

. A´´) If A´ is in associative register. get frame # out. U1. New Delhi-63. 56 . by Parul Arora. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´.

Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63. by Parul Arora. 57 .

by Parul Arora.. ration related to number of associative registers. U1. New Delhi-63. 58 . Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. New Delhi-63. “invalid” indicates that the page is not in the process’ logical address space. 59 .Memory Protection • Memory protection implemented by associating protection bit with each frame. U1. by Parul Arora. and is thus a legal page.

60 . U1..Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

U1.. 61 . by Parul Arora. New Delhi-63.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. • A simple technique is a two-level page table.Hierarchical Page Tables • Break up the logical address space into multiple page tables. U1.. 62 .

New Delhi-63.. a page offset consisting of 12 bits. U1. by Parul Arora. 63 .Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. Since the page table is paged. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a 10-bit page offset. the page number is further divided into: Thus. a logical address is as follows: pi p2 d 10 10 a 10-bit page number.

U1..Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 64 . by Parul Arora.

65 . U1.. New Delhi-63. by Parul Arora.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Virtual page numbers are compared in this chain searching for a match. New Delhi-63. U1.Hashed Page Tables • Common in address spaces > 32 bits. This page table contains a chain of elements hashing to the same location.. If a match is found. the corresponding physical frame is extracted. 66 . by Parul Arora. • The virtual page number is hashed into a page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 67 . by Parul Arora..

by Parul Arora. U1. • Decreases memory needed to store each page table.Inverted Page Table • One entry for each real page of memory. with information about the process that owns that page. but increases time needed to search the table when a page reference occurs. • Entry consists of the virtual address of the page stored in that real memory location.. 68 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Use hash table to limit the search to one — or at most a few — page-table entries.

. by Parul Arora. 69 . New Delhi-63. U1.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

window systems). text editors.e.. Private code and data Each process keeps a separate copy of the code and data. New Delhi-63. 70 . Shared code must appear in same location in the logical address space of all processes.. The pages for the private code and data can appear anywhere in the logical address space. by Parul Arora. U1.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. compilers.

New Delhi-63.Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. 71 ..

New Delhi-63. function.Segmentation Memory-management scheme that supports user view of memory. A segment is a logical unit such as: main program. method. A program is a collection of segments. common block. procedure. U1. stack. local variables. symbol table. global variables. 72 .. by Parul Arora. object. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.. New Delhi-63. 73 .

. New Delhi-63.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 74 . U1.

75 . U1.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. Segment table – maps two-dimensional physical addresses. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • • • Segment-table base register (STBR) points to the segment table’s location in memory.. offset>. each table entry has: base – contains the starting physical address where the segments reside in memory. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. limit – specifies the length of the segment. by Parul Arora.

76 . shared segments same segment number • Allocation.Segmentation Architecture (Cont. by Parul Arora.) • Relocation. New Delhi-63. dynamic by segment table • Sharing. U1. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Segmentation Architecture (Cont.) • Protection. 77 .. New Delhi-63. U1. • Since segments vary in length. code sharing occurs at segment level. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. memory allocation is a dynamic storage-allocation problem. by Parul Arora.

U1. New Delhi-63..Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 78 . by Parul Arora.

by Parul Arora. New Delhi-63. U1.. 79 .Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63.. 80 . by Parul Arora. U1.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. but rather the base address of a page table for this segment. New Delhi-63. by Parul Arora.. 81 . U1. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. U1. 82 .

New Delhi-63. 83 . the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.Segmentation with Paging – Intel 386 As shown in the following diagram..

Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63. 84 . by Parul Arora.

Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1. New Delhi-63. 85 .

U1. 86 . • Discuss the concept of thrashing. • Evaluate the trade-offs in terms of memory size (main memory. by Parul Arora. cache memory. New Delhi-63.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. auxiliary memory) and processor speed. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. • Describe the reason for and use of cache memory.. • Summarize the principles of virtual memory as applied to caching and paging. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. . Allows address spaces to be shared by several processes. Logical address space can therefore be much larger than physical address space.. by Parul Arora. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Allows for more efficient process creation.Background • Virtual memory – separation of user logical memory from physical memory. Only part of the program needs to be in memory for execution.

by Parul Arora. 88 .Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63..

Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Demand Paging Bring a page into memory only when it is needed. U1. New Delhi-63.. by Parul Arora. 89 .

Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 90 .. New Delhi-63. by Parul Arora.

. but valid-invalid bit 1 Example of a page table snapshot.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. by Parul Arora. 91 . 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.

by Parul Arora. U1.. New Delhi-63. 92 .Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Page Fault • If there is ever a reference to a page. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Restart instruction: Least Recently Used block move U1. Swap page into frame. validation bit = 1. . Reset tables. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. New Delhi-63. by Parul Arora. Just not in memory. • • • • Get empty frame.

U1..Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 94 . by Parul Arora.

by Parul Arora. U1.What happens if there is no free frame? • Page replacement – find some page in memory. • Same page may be brought into memory several times. 95 . swap it out. algorithm performance – want an algorithm which will result in minimum number of page faults. but not really in use. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.0 if p = 0 no page faults if p = 1.. by Parul Arora. New Delhi-63. 96 .

by Parul Arora.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. New Delhi-63. Swap Page Time = 10 msec = 10.. 97 .

Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 98 . U1.. by Parul Arora.

only then is the page copied. U1. • Free pages are allocated from a pool of zeroed-out pages. 99 .Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. New Delhi-63.. • COW allows more efficient process creation as only modified pages are copied.If either process modifies a shared page. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Simplifies file access by treating file I/O through memory rather than read() write() system calls. U1. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. • Also allows several processes to map the same file allowing the pages in memory to be shared. A page-sized portion of the file is read from the file system into a physical page. by Parul Arora. .Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. • A file is initially read using demand paging.

by Parul Arora.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. 101 .

U1. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 102 .Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. New Delhi-63. by Parul Arora. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory..

Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 103 .. by Parul Arora. U1. New Delhi-63.

U1. by Parul Arora. • Restart the process. 104 . • Read the desired page into the (newly) free frame.If there is a free frame. Update the page and frame tables..If there is no free frame. • Find a free frame: . use a page replacement algorithm to select a victim frame. use it. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Basic Page Replacement • Find the location of the desired page on disk. .

105 . U1.. by Parul Arora. New Delhi-63.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

the reference string is 1. 1. 106 . 2.Page Replacement Algorithms Want lowest page-fault rate. 4. 4. In all our examples.. 2. 5. 3. New Delhi-63. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. 2. 1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5. by Parul Arora. 3. U1.

107 .Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1.

3. 1.First-In-First-Out (FIFO) Algorithm Reference string: 1. U1. 1. 5. by Parul Arora. 108 . 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 3. New Delhi-63. 4. 2. 2.. 4. 2.

by Parul Arora..First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. 109 .

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

by Parul Arora. 113 ..Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

by Parul Arora. 4. 2. every time page is referenced through this entry. 2. 1. look at the counters to determine which are to change. New Delhi-63.Least Recently Used (LRU) Algorithm Reference string: 1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 114 . 1. copy the clock into the counter. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. U1.. 3. 3. 5. 2. 4. When a page needs to be changed.

LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63. 115 . U1.

116 . by Parul Arora. U1.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.LRU Algorithm (Cont..

by Parul Arora. New Delhi-63.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 117 . U1..

Replace the one which is 0 (if one exists).LRU Approximation Algorithm Reference bit With each page associate a bit.. then: set reference bit 0. 118 . replace next page (in clock order). U1. however. Second chance Need reference bit. initially = 0 When page is referenced bit set to 1. New Delhi-63. If page to be replaced (in clock order) has reference bit = 1. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Clock replacement. rules. leave page in memory. We do not know the order. by Parul Arora.

Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63. 119 . U1.

120 . New Delhi-63. by Parul Arora. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Counting Algorithms • Keep a counter of the number of references that have been made to each page. LFU Algorithm: replaces page with smallest count. U1. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used..

2 pages to handle from.Allocation of Frames • Each process needs minimum number of pages. by Parul Arora.. U1. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 121 . New Delhi-63. might span 2 pages. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. • Two major allocation schemes. 2 pages to handle to.

122 . si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Proportional allocation – Allocate according to the size of process. New Delhi-63. U1..g.. if 100 frames and 5 processes.Fixed Allocation • Equal allocation – e. by Parul Arora. give each 20 pages.

123 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. select for replacement a frame from a process with lower priority number.. • If process Pi generates a page fault. U1. select for replacement one of its frames.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. by Parul Arora. New Delhi-63.

• Local replacement – each process selects from only its own set of allocated frames. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames. New Delhi-63.Global vs. by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 124 . one process can take a frame from another.

. This leads to: low CPU utilization. U1. by Parul Arora. 125 . the page-fault rate is very high. New Delhi-63. operating system thinks that it needs to increase the degree of multiprogramming. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Thrashing If a process does not have “enough” pages. another process added to the system. Thrashing ≡ a process is busy swapping pages in and out.

New Delhi-63. by Parul Arora. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Localities may overlap. U1.Thrashing Why does paging work? Locality model Process migrates from one locality to another. 126 .

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

If actual rate too low.. by Parul Arora. 130 . process loses frame. U1. process gains frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. If actual rate too high.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate.

New Delhi-63. by Parul Arora. U1.. 131 .Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Other Considerations (Cont. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the working set of each process is stored in the TLB.The amount of memory accessible from the TLB. 132 .. U1. New Delhi-63.) TLB Reach . Otherwise there is a high degree of page faults. TLB Reach = (TLB Size) X (Page Size) Ideally.

by Parul Arora. • Provide Multiple Page Sizes.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. New Delhi-63.Increasing the Size of the TLB • Increase the Page Size. This may lead to an increase in fragmentation as not all applications require a large page size. U1. 133 .

U1.length. New Delhi-63. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.length. i < A. j++) for (i = 0.length. by Parul Arora. 1024 x 1024 page faults Program 2 for (i = 0.) Program structure int A[][] = new int[1024][1024]. i++) for (j = 0. j < A.length. Each row is stored in one page Program 1 for (j = 0. j++) A[i. i++) A[i.. 134 . i < A.j] = 0.Other Considerations (Cont.j] = 0. j < A.

135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Memory management algorithms differ in many concepts. Multiprogramming increased the performance of computer system.and also allows degree of multiprogramming to be raised. Virtual memory frees application programers from worrying about memory availability U1. by Parul Arora.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Virtual memory allows extremely large processes to be run. . New Delhi-63.

New Delhi-63. 136 Used. Second Chance. timesharing. Least Recently Used. First In First Out. by Parul Arora. personal computing and dedicated. Four major categories of operating systems are batch. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. Operating systems are a type of system software that allow applications to interface with computer hardware. Resources are any objects that can be allocated within a system. . Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. and Least Frequently U1. and the operating system is responsible for managing them. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. we saw that software can be roughly divided into two groups: application software and system software. Policies for determining which pages to load and remove from memory include Random Replacement.Summary • In the introduction.

U1. The Hardware mechanism that enables a device to notify the CPU is called __________.. 137 . a) Polling b) Interrupt c) System Call d) None of the above 2.Review Questions (OBJ) 1. by Parul Arora. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

New Delhi-63. U1. 138 .Review Questions (OBJ) 3. 4. Virtual memory is __________. by Parul Arora. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers.

. 139 . U1. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. The term " Operating System " means ________. by Parul Arora.Review Questions (OBJ) 5. New Delhi-63.

by Parul Arora.. The main program is loaded into memory & is executed. All routines are kept on disk in a relocatable load format. The principle of locality of reference justifies the use of ________. 140 . This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8.Review Questions (OBJ) 7. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ) Routine a) b) c) d) is not loaded until it is called. U1. New Delhi-63.

by Parul Arora. 141 .Review Questions (OBJ) 9. the total number of page faults caused by the process will be __________. ) The problem of thrashing is effected scientifically by ________.. a) 10 b) 7 c) 8 d) 9 10. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. If all page frames are initially empty. a) Program structure b) Program size c) Primary storage size d) None of the above U1. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. New Delhi-63.

142 . Explain the difference between logical and physical addresses. by Parul Arora. 9. List the four steps that are necessary to run a program on a completely dedicated machine 5. How do MULTICS and UNIX differ? 7. What are the main differences between operating systems for mainframe computers and personal computers? 3. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. Explain the difference between internal and external fragmentation 10. New Delhi-63. What is the main advantage of multiprogramming 2. How do I/O-bound and CPU-bound programs differ? 6.Review Questions (Short) 1. What are the three main purposes of an operating system? 4. How does a real-time system differ from time-share? 8..

How was memory mapping used in extending the usefulness of minicomputers? 13. What is virtual memory? 17. 16. When do page faults occur? 15. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How do global and local allocation differ? 20. What is Belady’s anomaly? 19. Why is there a valid/invalid bit? Where is it kept? 18. 143 . by Parul Arora.Review Questions (Short) 11. What are overlays? 12. Describe the actions taken by the operating system when a page fault occurs. What is reentrant code? 14. New Delhi-63.. What is meant by locality? 21. U1.

4. a. 8. 300K. 5. List ways to implement LRU.Review Questions (Long) 1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Consider a paging system with the page table stored in memory. 500K. 200K.)If we add associative registers. 3. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2..) 3. 4. 8. 2. 4. New Delhi-63. by Parul Arora. 144 . 1. how long does a paged memory reference take? b. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 6. for four page frames? 1. 7. and 600K (in order). 5. How many page faults occur for your algorithm for the following reference string. and 75 percent of all pagetable references are found in the associative registers. 5. 4. 9. 112K. 3. 417K. 7. 8. if the entry is there. 4. 7. to determine which page is victim.)If a memory reference takes 200 nanoseconds. 9. Given memory partitions of 100K. and Worst-?t algorithms place processes of 212K. Best-?t. how would each of the First-?t. 2. U1.

145 .6th Ed.Recommended reading • Silbersachatz and Galvin.. “Operating System Concepts” Peason. ”Operating System”: TMH. Donovan J.. by Parul Arora.. U1. 4th Edition. New Delhi-63.2001 • Madnick E.. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2001 • "Operating Systems” Tannenbaum PHI.

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