OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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. U1. 4 . by Parul Arora.Learning Objective Understand the purpose of the operating system Distinguish between a resource. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a program. New Delhi-63.

by Parul Arora. New Delhi-63. 5 .Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

by Parul Arora. Make the computer system convenient to use.. 6 . • Operating system goals: Execute user programs and make solving user problems easier. • Use the computer hardware in an efficient manner. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. U1.

Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. 3. video games. by Parul Arora. business programs). Hardware – provides basic computing resources (CPU. New Delhi-63. 2. other computers). memory. database systems. 7 . Users (people. 4..Computer System Components 1. U1. machines. I/O devices). Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.. New Delhi-63. 8 .

• Control program – controls the execution of user programs and operations of I/O devices . 9 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Operating System Definitions • Resource allocator – manages and allocates resources. by Parul Arora. • Kernel – the one program running at all times (all else being application programs).. U1.

10 .Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. by Parul Arora.

. 11 . • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. First rudimentary operating system.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. New Delhi-63.

by Parul Arora. U1.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 12 . New Delhi-63.

by Parul Arora. 13 .. New Delhi-63.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. • CPU scheduling – the system must choose among several jobs ready to run. New Delhi-63. 14 . • Allocation of devices. U1. by Parul Arora..OS Features Needed for Multiprogramming • I/O routine supplied by the system. • Memory management – the system must allocate the memory to several jobs.

On-line communication between the user and the system is provided. when the operating system finishes the execution of one command. . 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory).. A job swapped in and out of memory to the disk. New Delhi-63. U1. it seeks the next “control statement” from the user’s keyboard. by Parul Arora.

MacOS. 16 . small printers. • I/O devices – keyboards.. UNIX. New Delhi-63. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. U1. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • User convenience and responsiveness. display screens.Desktop Systems • Personal computers – computer system dedicated to a single user. by Parul Arora. mice. • May run several different types of operating systems (Windows.

communication usually takes place through the shared memory. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 17 . • Tightly coupled system – processors share memory and a clock. by Parul Arora. U1.Parallel Systems • Multiprocessor systems with more than on CPU in close communication.

master processor schedules and allocated work to slave processors. 18 . Many processes can run at once without performance deterioration. by Parul Arora. New Delhi-63. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system.Parallel Systems (Cont..

New Delhi-63. U1.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 19 .. by Parul Arora.

Distributed Systems • Distribute the computation among several physical processors. • Loosely coupled system – each processor has its own local memory. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 20 . by Parul Arora.. processors communicate with one another through various communications lines. such as high-speed buses or telephone lines. New Delhi-63. U1. • Advantages of distributed systems.

Distributed Systems (cont) • Requires networking infrastructure. 21 . by Parul Arora. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

by Parul Arora. U1..General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 22 .

New Delhi-63. • Asymmetric clustering: one server runs the application while other servers standby. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 23 . • Symmetric clustering: all N hosts are running the application.. • Provides high reliability.Clustered Systems • Clustering allows two or more systems to share storage. by Parul Arora.

24 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. industrial control systems.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. • Well-defined fixed-time constraints.. • Real-Time systems may be either hard or soft real-time. New Delhi-63. U1. and some display systems. by Parul Arora. medical imaging systems.

virtual reality) requiring advanced operating-system features.Real-Time Systems (Cont. not supported by general-purpose operating systems. U1. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.) • Hard real-time: Secondary storage limited or absent. . data stored in short term memory.. or read-only memory (ROM) Conflicts with time-sharing systems. by Parul Arora.

Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. U1. by Parul Arora. New Delhi-63. 26 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. by Parul Arora. U1..Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 27 .

Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 28 . New Delhi-63.. U1.

Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 29 . New Delhi-63. by Parul arora U1.

U1. New Delhi-63.strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 30 ..how memory is structured Memory management . by Parul Arora.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .

by Parul Arora..Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 31 . U1. New Delhi-63.

New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program.Background • Program must be brought into memory and placed within a process for it to be run. • User programs go through several steps before being run. U1. 32 ..

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. by Parul Arora..g. base and limit registers). New Delhi-63. • Load time: Must generate relocatable code if memory location is not known at compile time. 33 . • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. must recompile code if starting location changes. Need hardware support for address maps (e. absolute code can be generated.

.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. 34 . U1.

Physical address – address seen by the memory unit. by Parul Arora. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.Logical vs. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. logical (virtual) and physical addresses differ in execution-time address-binding scheme. 35 . • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. U1.. Logical address – generated by the CPU. also referred to as virtual address. New Delhi-63.

U1.. by Parul Arora. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. New Delhi-63. • In MMU scheme. it never sees the real physical addresses. • The user program deals with logical addresses. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Memory-Management Unit • Hardware device that maps virtual to physical address. 36 .

Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. 37 .. New Delhi-63.

New Delhi-63. • Useful when large amounts of code are needed to handle infrequently occurring cases.. U1. 38 . unused routine is never loaded. • No special support from the operating system is required implemented through program design.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 39 . • Operating system needed to check if routine is in processes’ memory address. U1.. • Dynamic linking is particularly useful for libraries. by Parul Arora. and executes the routine. used to locate the appropriate memory-resident library routine. stub. New Delhi-63.Dynamic Linking • Linking postponed until execution time. • Small piece of code. • Stub replaces itself with the address of the routine.

Overlays • Keep in memory only those instructions and data that are needed at any given time. 40 . • Implemented by user. U1.. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Needed when process is larger than amount of memory allocated to it. no special support needed from operating system. New Delhi-63. by Parul Arora.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. Relocation register contains value of smallest physical address. 44 . and from changing operating-system code and data.Contiguous Allocation • Main memory usually into two partitions: Resident operating system.. User processes then held in high memory. limit register contains range of logical addresses – each logical address must be less than the limit register. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. usually held in low memory with interrupt vector.

New Delhi-63.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 45 . U1.. by Parul Arora.

) Multiple-partition allocation Hole – block of available memory. U1. holes of various size are scattered throughout memory. When a process arrives. by Parul Arora.Contiguous Allocation (Cont. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. it is allocated memory from a hole large enough to accommodate it. New Delhi-63. 46 .

Produces the smallest leftover hole. New Delhi-63. 47 .Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. Produces the largest leftover hole. Best-fit: Allocate the smallest hole that is big enough. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. unless ordered by size. Worst-fit: Allocate the largest hole. must also search entire list. must search entire list. by Parul Arora.

U1. and is done at execution time. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. this size difference is memory internal to a partition.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. by Parul Arora. Compaction is possible only if relocation is dynamic. but not being used. 48 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Internal Fragmentation – allocated memory may be slightly larger than requested memory.. Do I/O only into OS buffers. I/O problem Latch job in memory while it is involved in I/O. New Delhi-63. but it is not contiguous.

New Delhi-63. • To run a program of size n pages.Paging • Logical address space of a process can be noncontiguous. • Internal fragmentation. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. process is allocated physical memory whenever the latter is available.. need to find n free frames and load program. • Set up a page table to translate logical to physical addresses. U1. between 512 bytes and 8192 bytes). 49 . • Divide logical memory into blocks of same size called pages. by Parul Arora. • Keep track of all free frames.

Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 50 .. by Parul Arora. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. U1. New Delhi-63.

U1.Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 51 . by Parul Arora. New Delhi-63.

by Parul Arora. 52 .. New Delhi-63. U1.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. New Delhi-63. U1.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 53 .

.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 54 . U1. by Parul Arora. New Delhi-63.

One for the page table and one for the data/instruction.. • Page-table base register (PTBR) points to the page table. 55 . U1. New Delhi-63. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page-table length register (PRLR) indicates size of the page table. by Parul Arora.Implementation of Page Table • Page table is kept in main memory. • In this scheme every data/instruction access requires two memory accesses.

56 .Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´.. New Delhi-63. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A´´) If A´ is in associative register. U1. get frame # out. by Parul Arora.

New Delhi-63. 57 .Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora.

58 . by Parul Arora. U1. ration related to number of associative registers. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.. New Delhi-63.

• Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. and is thus a legal page. 59 .Memory Protection • Memory protection implemented by associating protection bit with each frame. “invalid” indicates that the page is not in the process’ logical address space. by Parul Arora.. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

. by Parul Arora.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 60 . U1. New Delhi-63.

61 . U1. New Delhi-63. by Parul Arora..Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • A simple technique is a two-level page table. 62 .. New Delhi-63.Hierarchical Page Tables • Break up the logical address space into multiple page tables.

New Delhi-63. a page offset consisting of 12 bits. a 10-bit page offset. by Parul Arora. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the page number is further divided into: Thus.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. 63 . Since the page table is paged. U1.. a logical address is as follows: pi p2 d 10 10 a 10-bit page number.

Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.. 64 . by Parul Arora.

U1. by Parul Arora. 65 .. New Delhi-63.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Virtual page numbers are compared in this chain searching for a match. the corresponding physical frame is extracted.Hashed Page Tables • Common in address spaces > 32 bits. 66 . If a match is found. New Delhi-63. U1. • The virtual page number is hashed into a page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. This page table contains a chain of elements hashing to the same location..

New Delhi-63. U1. 67 ..Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

with information about the process that owns that page. • Decreases memory needed to store each page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. but increases time needed to search the table when a page reference occurs. 68 . • Use hash table to limit the search to one — or at most a few — page-table entries. • Entry consists of the virtual address of the page stored in that real memory location. by Parul Arora..Inverted Page Table • One entry for each real page of memory.

New Delhi-63.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 69 . U1.. by Parul Arora.

. by Parul Arora. 70 . window systems).e. The pages for the private code and data can appear anywhere in the logical address space. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. text editors.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. New Delhi-63. Private code and data Each process keeps a separate copy of the code and data. compilers. U1. Shared code must appear in same location in the logical address space of all processes..

. New Delhi-63.Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 71 . U1.

arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 72 . symbol table. global variables. object. A segment is a logical unit such as: main program. method. procedure. U1. A program is a collection of segments. stack. by Parul Arora. common block. function.Segmentation Memory-management scheme that supports user view of memory. local variables.

.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 73 . by Parul Arora. U1.

U1. New Delhi-63.. 74 .Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

limit – specifies the length of the segment. 75 . each table entry has: base – contains the starting physical address where the segments reside in memory. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. by Parul Arora. • • • Segment-table base register (STBR) points to the segment table’s location in memory. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. offset>..Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. Segment table – maps two-dimensional physical addresses.

by Parul Arora. 76 . dynamic by segment table • Sharing. U1.. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Architecture (Cont. New Delhi-63. shared segments same segment number • Allocation.) • Relocation.

Segmentation Architecture (Cont. New Delhi-63. by Parul Arora. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.. memory allocation is a dynamic storage-allocation problem. U1. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. code sharing occurs at segment level.) • Protection. • Since segments vary in length. 77 .

. U1.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 78 . New Delhi-63.

U1. by Parul Arora.. New Delhi-63.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 79 .

by Parul Arora. 80 .. New Delhi-63.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

• Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. but rather the base address of a page table for this segment. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 81 .Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. by Parul Arora.

U1.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 82 . by Parul Arora. New Delhi-63.

U1. 83 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.Segmentation with Paging – Intel 386 As shown in the following diagram.. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.

New Delhi-63. U1.. by Parul Arora.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 84 .

New Delhi-63. by Parul arora U1.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 85 .

U1. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. by Parul Arora. • Summarize the principles of virtual memory as applied to caching and paging.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. cache memory. • Describe the reason for and use of cache memory. • Discuss the concept of thrashing. auxiliary memory) and processor speed. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Evaluate the trade-offs in terms of memory size (main memory. 86 .

Allows for more efficient process creation. by Parul Arora. .Background • Virtual memory – separation of user logical memory from physical memory. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. New Delhi-63. Allows address spaces to be shared by several processes.. Logical address space can therefore be much larger than physical address space. Only part of the program needs to be in memory for execution. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. 88 ..Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. U1. 89 .Demand Paging Bring a page into memory only when it is needed. New Delhi-63.

. 90 . by Parul Arora.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

but valid-invalid bit 1 Example of a page table snapshot. 91 . by Parul Arora. New Delhi-63.. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. U1. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory.

92 ..Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. New Delhi-63.

Restart instruction: Least Recently Used block move U1. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. validation bit = 1. New Delhi-63.Page Fault • If there is ever a reference to a page. Reset tables. by Parul Arora. Swap page into frame.. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Just not in memory. • • • • Get empty frame. .

by Parul Arora.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 94 . New Delhi-63.

New Delhi-63. 95 .. • Same page may be brought into memory several times. swap it out. but not really in use. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.What happens if there is no free frame? • Page replacement – find some page in memory. algorithm performance – want an algorithm which will result in minimum number of page faults. by Parul Arora.

by Parul Arora. 96 .0 if p = 0 no page faults if p = 1.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. U1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. by Parul Arora.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 97 . New Delhi-63. Swap Page Time = 10 msec = 10.. U1.

Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.. New Delhi-63. 98 .

99 . • Free pages are allocated from a pool of zeroed-out pages.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. New Delhi-63. only then is the page copied. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • COW allows more efficient process creation as only modified pages are copied.If either process modifies a shared page. by Parul Arora.

. Subsequent reads/writes to/from the file are treated as ordinary memory accesses.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. A page-sized portion of the file is read from the file system into a physical page. U1. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • A file is initially read using demand paging. by Parul Arora. • Also allows several processes to map the same file allowing the pages in memory to be shared. • Simplifies file access by treating file I/O through memory rather than read() write() system calls.. New Delhi-63.

101 .Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. New Delhi-63..

U1.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. New Delhi-63. by Parul Arora. 102 . • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk.

. by Parul Arora. New Delhi-63. 103 .Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63. use it. use a page replacement algorithm to select a victim frame..If there is no free frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Read the desired page into the (newly) free frame. . Update the page and frame tables. by Parul Arora. • Restart the process. 104 .If there is a free frame. • Find a free frame: . U1.Basic Page Replacement • Find the location of the desired page on disk.

by Parul Arora. U1..Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 105 .

2. 1. 5. 3. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. 2. 1. 4. In all our examples.Page Replacement Algorithms Want lowest page-fault rate. 106 . New Delhi-63.. 5. the reference string is 1. U1. 3. 4. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. by Parul Arora.

Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 107 . by Parul Arora. New Delhi-63.

4. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 3.. 3. New Delhi-63. 2. U1. 2. 5. 2. 1. 108 . by Parul Arora. 4.First-In-First-Out (FIFO) Algorithm Reference string: 1. 1.

U1.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. by Parul Arora. 109 .

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

New Delhi-63. U1. 113 .Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.

every time page is referenced through this entry. 1. New Delhi-63. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. 4.. 3. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5. 2. look at the counters to determine which are to change. 4.Least Recently Used (LRU) Algorithm Reference string: 1. by Parul Arora. 1. U1. copy the clock into the counter. 3. 2. 114 . 2. When a page needs to be changed.

U1.. by Parul Arora. New Delhi-63. 115 .LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. 116 .LRU Algorithm (Cont. U1. by Parul Arora.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

New Delhi-63.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 117 . by Parul Arora. U1..

rules. Second chance Need reference bit. leave page in memory.LRU Approximation Algorithm Reference bit With each page associate a bit. by Parul Arora. replace next page (in clock order). however. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. We do not know the order. Clock replacement. Replace the one which is 0 (if one exists). 118 . If page to be replaced (in clock order) has reference bit = 1.. initially = 0 When page is referenced bit set to 1. then: set reference bit 0. U1. New Delhi-63.

119 ..Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. by Parul Arora.

LFU Algorithm: replaces page with smallest count. New Delhi-63. 120 . MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. U1. by Parul Arora.Counting Algorithms • Keep a counter of the number of references that have been made to each page. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

New Delhi-63.. 2 pages to handle to. 2 pages to handle from. 121 . by Parul Arora. U1.Allocation of Frames • Each process needs minimum number of pages. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Two major allocation schemes. might span 2 pages. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes.

si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Proportional allocation – Allocate according to the size of process.. if 100 frames and 5 processes. by Parul Arora. New Delhi-63. U1..Fixed Allocation • Equal allocation – e. 122 .g. give each 20 pages.

Priority Allocation • Use a proportional allocation scheme using priorities rather than size. • If process Pi generates a page fault. select for replacement one of its frames. New Delhi-63.. select for replacement a frame from a process with lower priority number. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. 123 .

one process can take a frame from another. by Parul Arora. U1. 124 .. New Delhi-63.Global vs. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Local replacement – each process selects from only its own set of allocated frames. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. Thrashing ≡ a process is busy swapping pages in and out. 125 . another process added to the system. the page-fault rate is very high. operating system thinks that it needs to increase the degree of multiprogramming. This leads to: low CPU utilization..Thrashing If a process does not have “enough” pages. U1. by Parul Arora.

Thrashing Why does paging work? Locality model Process migrates from one locality to another. 126 .. U1. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. Localities may overlap.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

130 .. If actual rate too high. process gains frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. If actual rate too low. U1.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. by Parul Arora. New Delhi-63. process loses frame.

by Parul Arora. 131 . U1. New Delhi-63..Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

132 . by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Otherwise there is a high degree of page faults. the working set of each process is stored in the TLB.Other Considerations (Cont.The amount of memory accessible from the TLB. New Delhi-63..) TLB Reach . TLB Reach = (TLB Size) X (Page Size) Ideally. U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 133 . by Parul Arora. • Provide Multiple Page Sizes.. U1. This may lead to an increase in fragmentation as not all applications require a large page size. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation.Increasing the Size of the TLB • Increase the Page Size.

j] = 0.) Program structure int A[][] = new int[1024][1024]. i < A.length. j++) for (i = 0. j < A. j++) A[i. New Delhi-63. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management..j] = 0.length. by Parul Arora. U1. Each row is stored in one page Program 1 for (j = 0. j < A. i++) for (j = 0.length. 134 . i < A. 1024 x 1024 page faults Program 2 for (i = 0. i++) A[i.length.Other Considerations (Cont.

by Parul Arora.. Virtual memory allows extremely large processes to be run.and also allows degree of multiprogramming to be raised. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. New Delhi-63. Virtual memory frees application programers from worrying about memory availability U1. Multiprogramming increased the performance of computer system. Memory management algorithms differ in many concepts. .

Summary • In the introduction. by Parul Arora. First In First Out. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. Second Chance.. Resources are any objects that can be allocated within a system. 136 Used. Operating systems are a type of system software that allow applications to interface with computer hardware. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. we saw that software can be roughly divided into two groups: application software and system software. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Policies for determining which pages to load and remove from memory include Random Replacement. Least Recently Used. and the operating system is responsible for managing them. . personal computing and dedicated. timesharing. and Least Frequently U1. Four major categories of operating systems are batch. New Delhi-63.

137 . U1. The Hardware mechanism that enables a device to notify the CPU is called __________. by Parul Arora. a) Polling b) Interrupt c) System Call d) None of the above 2.Review Questions (OBJ) 1. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. 138 . 4. U1. by Parul Arora.. Virtual memory is __________. New Delhi-63. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 3.

. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. The term " Operating System " means ________. by Parul Arora. U1.Review Questions (OBJ) 5. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 139 .

) Routine a) b) c) d) is not loaded until it is called. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Review Questions (OBJ) 7. The principle of locality of reference justifies the use of ________.. by Parul Arora. All routines are kept on disk in a relocatable load format. New Delhi-63. 140 . This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. The main program is loaded into memory & is executed.

a) 10 b) 7 c) 8 d) 9 10. If all page frames are initially empty. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the total number of page faults caused by the process will be __________. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. by Parul Arora. ) The problem of thrashing is effected scientifically by ________. a) Program structure b) Program size c) Primary storage size d) None of the above U1. 141 ..Review Questions (OBJ) 9.

How does a real-time system differ from time-share? 8.Review Questions (Short) 1. by Parul Arora. What is the main advantage of multiprogramming 2.. What are the three main purposes of an operating system? 4. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. List the four steps that are necessary to run a program on a completely dedicated machine 5. New Delhi-63. Explain the difference between internal and external fragmentation 10. U1. Explain the difference between logical and physical addresses. What are the main differences between operating systems for mainframe computers and personal computers? 3. How do I/O-bound and CPU-bound programs differ? 6. How do MULTICS and UNIX differ? 7. 9. 142 .

. Why is there a valid/invalid bit? Where is it kept? 18. 16. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How do global and local allocation differ? 20. What is meant by locality? 21. Describe the actions taken by the operating system when a page fault occurs. What is Belady’s anomaly? 19. What are overlays? 12. New Delhi-63. 143 .Review Questions (Short) 11. by Parul Arora. How was memory mapping used in extending the usefulness of minicomputers? 13. What is virtual memory? 17. When do page faults occur? 15. What is reentrant code? 14. U1.

a. 4. 144 . 3. how long does a paged memory reference take? b. and 75 percent of all pagetable references are found in the associative registers. and 600K (in order). 4. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. New Delhi-63. 7. List ways to implement LRU. 7. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. to determine which page is victim.) 3.)If a memory reference takes 200 nanoseconds. 8. 5. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. for four page frames? 1. Best-?t. 8. 500K. 9. 1. 112K. 8. by Parul Arora. 4. Consider a paging system with the page table stored in memory. 9. 4. 2. if the entry is there.Review Questions (Long) 1. 7. 200K. 6. How many page faults occur for your algorithm for the following reference string. Given memory partitions of 100K. 2. 5.)If we add associative registers. 300K. 417K. and Worst-?t algorithms place processes of 212K. 5.. 3. U1. how would each of the First-?t.

2001 • "Operating Systems” Tannenbaum PHI.. 4th Edition. Donovan J.6th Ed.. New Delhi-63.. U1.Recommended reading • Silbersachatz and Galvin. by Parul Arora.. “Operating System Concepts” Peason. ”Operating System”: TMH.2001 • Madnick E. 145 . 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.