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Sections

  • Introduction
  • What is an Operating System?
  • Computer System Components
  • Operating System Definitions
  • Operating System View
  • Mainframe Systems
  • Desktop Systems
  • Parallel Systems
  • Parallel Systems (Cont.)
  • Distributed Systems
  • Distributed Systems (cont)
  • Clustered Systems
  • Real-Time Systems
  • Real-Time Systems (Cont.)
  • Handheld Systems
  • Computing Environments
  • Learning Objective
  • Memory Management
  • Background
  • Dynamic Loading
  • Dynamic Linking
  • Overlays
  • Swapping
  • Schematic View of Swapping
  • Contiguous Allocation
  • Contiguous Allocation (Cont.)
  • Fragmentation
  • Paging
  • Address Translation Scheme
  • Free Frames
  • Implementation of Page Table
  • Associative Memory
  • Paging Hardware With TLB
  • Effective Access Time
  • Memory Protection
  • Page Table Structure
  • Hierarchical Page Tables
  • Two-Level Paging Example
  • Two-Level Page-Table Scheme
  • Address-Translation Scheme
  • Hashed Page Tables
  • Hashed Page Table
  • Inverted Page Table
  • Shared Pages
  • Shared Pages Example
  • Segmentation
  • User’s View of a Program
  • Logical View of Segmentation
  • Segmentation Architecture
  • Segmentation Hardware
  • Example of Segmentation
  • Sharing of Segments
  • Learning Objectives
  • Demand Paging
  • Valid-Invalid Bit
  • Page Fault
  • Steps in Handling a Page Fault
  • Performance of Demand Paging
  • Demand Paging Example
  • Process Creation
  • Copy-on-Write
  • Memory-Mapped Files
  • Memory Mapped Files
  • Page Replacement
  • Need For Page Replacement
  • Basic Page Replacement
  • Page Replacement Algorithms
  • FIFO Page Replacement
  • Optimal Algorithm
  • Optimal Page Replacement
  • LRU Page Replacement
  • LRU Algorithm (Cont.)
  • LRU Approximation Algorithm
  • Counting Algorithms
  • Allocation of Frames
  • Fixed Allocation
  • Priority Allocation
  • Global vs. Local Allocation
  • Working-Set Model
  • Working-set model
  • Page-Fault Frequency Scheme
  • Other Considerations
  • Increasing the Size of the TLB
  • Conclusion
  • Summary

OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 1

Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 2

Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 3

a program.Learning Objective Understand the purpose of the operating system Distinguish between a resource. by Parul Arora. 4 .. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

by Parul Arora. New Delhi-63. 5 .Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. • Operating system goals: Execute user programs and make solving user problems easier.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. • Use the computer hardware in an efficient manner.. 6 . Make the computer system convenient to use. New Delhi-63.

Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. 2. 7 . other computers). U1. Hardware – provides basic computing resources (CPU.Computer System Components 1. New Delhi-63. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. machines. memory. I/O devices). 4. business programs). video games. by Parul Arora. Users (people. 3. database systems..

U1.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 8 . by Parul Arora.

9 . • Kernel – the one program running at all times (all else being application programs). by Parul Arora. New Delhi-63.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Operating System Definitions • Resource allocator – manages and allocates resources. • Control program – controls the execution of user programs and operations of I/O devices .

New Delhi-63. 10 .. U1.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

First rudimentary operating system.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. 11 .. New Delhi-63. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

12 .Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. by Parul Arora. New Delhi-63.

New Delhi-63.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. 13 ..

14 .OS Features Needed for Multiprogramming • I/O routine supplied by the system. • CPU scheduling – the system must choose among several jobs ready to run. New Delhi-63. • Allocation of devices. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. • Memory management – the system must allocate the memory to several jobs. U1.

Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). . On-line communication between the user and the system is provided. when the operating system finishes the execution of one command. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. it seeks the next “control statement” from the user’s keyboard. A job swapped in and out of memory to the disk. by Parul Arora.. New Delhi-63. U1.

Desktop Systems • Personal computers – computer system dedicated to a single user. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features.. • I/O devices – keyboards. New Delhi-63. small printers. 16 . UNIX. by Parul Arora. • May run several different types of operating systems (Windows. U1. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • User convenience and responsiveness. display screens. mice. MacOS.

17 .. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. • Tightly coupled system – processors share memory and a clock. communication usually takes place through the shared memory.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. New Delhi-63.

Parallel Systems (Cont. U1. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.. New Delhi-63. by Parul Arora.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. Many processes can run at once without performance deterioration. master processor schedules and allocated work to slave processors. 18 . More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. New Delhi-63.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 19 . by Parul Arora.

Distributed Systems • Distribute the computation among several physical processors. such as high-speed buses or telephone lines. • Advantages of distributed systems.. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. processors communicate with one another through various communications lines. New Delhi-63. 20 . • Loosely coupled system – each processor has its own local memory. by Parul Arora. U1.

21 . New Delhi-63. by Parul Arora. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.Distributed Systems (cont) • Requires networking infrastructure. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

22 . U1.General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora.

• Asymmetric clustering: one server runs the application while other servers standby. 23 . • Symmetric clustering: all N hosts are running the application. by Parul Arora.Clustered Systems • Clustering allows two or more systems to share storage.. • Provides high reliability. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

medical imaging systems.. and some display systems. by Parul Arora. U1. • Real-Time systems may be either hard or soft real-time. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 24 . industrial control systems. New Delhi-63. • Well-defined fixed-time constraints.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments.

or read-only memory (ROM) Conflicts with time-sharing systems. U1.) • Hard real-time: Secondary storage limited or absent. .Real-Time Systems (Cont. data stored in short term memory. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. virtual reality) requiring advanced operating-system features. not supported by general-purpose operating systems. by Parul Arora. New Delhi-63. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.

New Delhi-63.Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. U1. by Parul Arora. 26 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. New Delhi-63. 27 . U1.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

New Delhi-63.. U1.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 28 .

by Parul arora U1. 29 . New Delhi-63.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management .

U1. 30 . by Parul Arora.strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.how memory is structured Memory management ..Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . New Delhi-63.

by Parul Arora. New Delhi-63. U1. 31 ..Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. 32 . New Delhi-63. • User programs go through several steps before being run.Background • Program must be brought into memory and placed within a process for it to be run.. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Load time: Must generate relocatable code if memory location is not known at compile time. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. by Parul Arora.g. New Delhi-63. absolute code can be generated.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.. must recompile code if starting location changes. 33 . base and limit registers). • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.

U1. New Delhi-63. by Parul Arora. 34 ..Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. Logical address – generated by the CPU. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. also referred to as virtual address. logical (virtual) and physical addresses differ in execution-time address-binding scheme.Logical vs. by Parul Arora. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes.. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. U1. 35 . Physical address – address seen by the memory unit.

by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • The user program deals with logical addresses.Memory-Management Unit • Hardware device that maps virtual to physical address. it never sees the real physical addresses. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. • In MMU scheme. 36 . U1..

37 .. New Delhi-63.Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

. unused routine is never loaded.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Useful when large amounts of code are needed to handle infrequently occurring cases. U1. New Delhi-63. • No special support from the operating system is required implemented through program design. by Parul Arora. 38 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.Dynamic Linking • Linking postponed until execution time. • Small piece of code. U1. • Dynamic linking is particularly useful for libraries. New Delhi-63. by Parul Arora. 39 .. • Stub replaces itself with the address of the routine. stub. • Operating system needed to check if routine is in processes’ memory address. and executes the routine. used to locate the appropriate memory-resident library routine.

U1. New Delhi-63. • Implemented by user. no special support needed from operating system. 40 .Overlays • Keep in memory only those instructions and data that are needed at any given time. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Needed when process is larger than amount of memory allocated to it. by Parul Arora..

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 41

Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 42

Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 43

. and from changing operating-system code and data. by Parul Arora. Relocation register contains value of smallest physical address. usually held in low memory with interrupt vector. User processes then held in high memory. limit register contains range of logical addresses – each logical address must be less than the limit register. 44 . • Single-partition allocation Relocation-register scheme used to protect user processes from each other. U1.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora..Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 45 .

by Parul Arora. U1. 46 .) Multiple-partition allocation Hole – block of available memory. it is allocated memory from a hole large enough to accommodate it..Contiguous Allocation (Cont. New Delhi-63. When a process arrives. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. holes of various size are scattered throughout memory.

. Produces the largest leftover hole. unless ordered by size. 47 . U1. must also search entire list. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. must search entire list.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. by Parul Arora. Best-fit: Allocate the smallest hole that is big enough. New Delhi-63.

U1. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. Do I/O only into OS buffers. Compaction is possible only if relocation is dynamic. but it is not contiguous.. and is done at execution time. by Parul Arora. but not being used. this size difference is memory internal to a partition. New Delhi-63. 48 . I/O problem Latch job in memory while it is involved in I/O.

Paging • Logical address space of a process can be noncontiguous. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • To run a program of size n pages. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. process is allocated physical memory whenever the latter is available. • Set up a page table to translate logical to physical addresses. • Divide logical memory into blocks of same size called pages. New Delhi-63. • Keep track of all free frames. between 512 bytes and 8192 bytes). need to find n free frames and load program. • Internal fragmentation. by Parul Arora.. U1. 49 .

New Delhi-63. 50 . by Parul Arora.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit..

by Parul Arora.. U1. 51 .Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

U1. New Delhi-63. by Parul Arora. 52 ..Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

53 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. New Delhi-63..

U1. New Delhi-63.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 54 . by Parul Arora..

U1. New Delhi-63. One for the page table and one for the data/instruction. by Parul Arora. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • In this scheme every data/instruction access requires two memory accesses.. • Page-table length register (PRLR) indicates size of the page table. 55 . • Page-table base register (PTBR) points to the page table.Implementation of Page Table • Page table is kept in main memory.

U1. 56 . A´´) If A´ is in associative register. by Parul Arora. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. get frame # out. New Delhi-63.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´.

New Delhi-63. 57 ..Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. New Delhi-63. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ration related to number of associative registers. U1. by Parul Arora.. 58 .

and is thus a legal page. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. “invalid” indicates that the page is not in the process’ logical address space. 59 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Memory Protection • Memory protection implemented by associating protection bit with each frame. by Parul Arora.. New Delhi-63.

New Delhi-63.. U1. 60 . by Parul Arora.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. U1.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 61 ..

Hierarchical Page Tables • Break up the logical address space into multiple page tables. • A simple technique is a two-level page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. New Delhi-63.. 62 .

a page offset consisting of 12 bits.. a 10-bit page offset. the page number is further divided into: Thus. 63 . U1. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. Since the page table is paged. by Parul Arora.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits.

64 .. by Parul Arora.Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

New Delhi-63. 65 .Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. by Parul Arora.

by Parul Arora.. • Virtual page numbers are compared in this chain searching for a match. This page table contains a chain of elements hashing to the same location.Hashed Page Tables • Common in address spaces > 32 bits. the corresponding physical frame is extracted. • The virtual page number is hashed into a page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. If a match is found. New Delhi-63. U1. 66 .

New Delhi-63. by Parul Arora.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 67 . U1..

New Delhi-63. U1. with information about the process that owns that page.Inverted Page Table • One entry for each real page of memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Decreases memory needed to store each page table.. • Entry consists of the virtual address of the page stored in that real memory location. • Use hash table to limit the search to one — or at most a few — page-table entries. 68 . but increases time needed to search the table when a page reference occurs. by Parul Arora.

New Delhi-63. 69 . by Parul Arora.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

Private code and data Each process keeps a separate copy of the code and data.. U1.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. compilers. New Delhi-63.. The pages for the private code and data can appear anywhere in the logical address space. by Parul Arora. text editors. Shared code must appear in same location in the logical address space of all processes. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. window systems). 70 .e.

71 .. New Delhi-63.Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

. method. symbol table. U1. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. procedure. object. common block. global variables. stack.Segmentation Memory-management scheme that supports user view of memory. A program is a collection of segments. A segment is a logical unit such as: main program. function. by Parul Arora. 72 . local variables.

U1.. by Parul Arora. New Delhi-63. 73 .User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. U1. by Parul Arora. 74 . New Delhi-63.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. offset>. 75 . Segment table – maps two-dimensional physical addresses. by Parul Arora. New Delhi-63. U1. each table entry has: base – contains the starting physical address where the segments reside in memory. limit – specifies the length of the segment. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. • • • Segment-table base register (STBR) points to the segment table’s location in memory. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR.

76 .) • Relocation. by Parul Arora.Segmentation Architecture (Cont. dynamic by segment table • Sharing.. New Delhi-63. shared segments same segment number • Allocation. U1. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Since segments vary in length. code sharing occurs at segment level. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. U1. New Delhi-63.Segmentation Architecture (Cont. by Parul Arora. 77 . • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. memory allocation is a dynamic storage-allocation problem.) • Protection.

Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 78 . by Parul Arora.. New Delhi-63.

Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 79 . New Delhi-63. by Parul Arora.

. New Delhi-63. 80 . by Parul Arora.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63.. 81 .Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but rather the base address of a page table for this segment. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment.

MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 82 .. New Delhi-63. U1.

83 . New Delhi-63.. U1.Segmentation with Paging – Intel 386 As shown in the following diagram. by Parul Arora. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.. 84 . by Parul Arora.

85 . by Parul arora U1.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. by Parul Arora. • Describe the reason for and use of cache memory. New Delhi-63. • Summarize the principles of virtual memory as applied to caching and paging. U1. cache memory. • Evaluate the trade-offs in terms of memory size (main memory.. 86 . auxiliary memory) and processor speed. • Discuss the concept of thrashing.

New Delhi-63. Allows address spaces to be shared by several processes. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Background • Virtual memory – separation of user logical memory from physical memory. . Allows for more efficient process creation.. Logical address space can therefore be much larger than physical address space. by Parul Arora. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. Only part of the program needs to be in memory for execution.

New Delhi-63. by Parul Arora..Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 88 .

U1. New Delhi-63.. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 89 . by Parul Arora.Demand Paging Bring a page into memory only when it is needed.

.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 90 . New Delhi-63. U1. by Parul Arora.

but valid-invalid bit 1 Example of a page table snapshot. U1. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. by Parul Arora.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. New Delhi-63. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 91 ..

Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 92 . New Delhi-63. U1..

93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. . Reset tables. Swap page into frame. New Delhi-63. Restart instruction: Least Recently Used block move U1. • • • • Get empty frame.Page Fault • If there is ever a reference to a page. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. by Parul Arora. Just not in memory. validation bit = 1.

New Delhi-63. by Parul Arora. U1.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 94 .

What happens if there is no free frame? • Page replacement – find some page in memory.. by Parul Arora. 95 . swap it out. algorithm performance – want an algorithm which will result in minimum number of page faults. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. but not really in use. New Delhi-63. • Same page may be brought into memory several times.

0 if p = 0 no page faults if p = 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. 96 . by Parul Arora.. U1.

U1. 97 .Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. New Delhi-63.. by Parul Arora. Swap Page Time = 10 msec = 10.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. U1. New Delhi-63.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 98 . by Parul Arora.

99 . • COW allows more efficient process creation as only modified pages are copied..If either process modifies a shared page. New Delhi-63. U1. • Free pages are allocated from a pool of zeroed-out pages. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. only then is the page copied.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory.

• A file is initially read using demand paging. . Subsequent reads/writes to/from the file are treated as ordinary memory accesses.. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. • Also allows several processes to map the same file allowing the pages in memory to be shared. A page-sized portion of the file is read from the file system into a physical page.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. U1.

New Delhi-63.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 101 . U1. by Parul Arora.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.. U1. 102 . by Parul Arora.

New Delhi-63.. 103 . by Parul Arora. U1.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

104 .If there is a free frame.Basic Page Replacement • Find the location of the desired page on disk. • Find a free frame: . New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Update the page and frame tables. by Parul Arora.If there is no free frame. use a page replacement algorithm to select a victim frame. U1. • Restart the process.. • Read the desired page into the (newly) free frame. use it. .

by Parul Arora.. 105 . U1.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

1. 3. 2. 3. 2. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. In all our examples. 106 . 1. 5. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5. 4. the reference string is 1. by Parul Arora.Page Replacement Algorithms Want lowest page-fault rate. U1.. 2. New Delhi-63.

New Delhi-63. U1. by Parul Arora..Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 107 .

2. 1. 5. 2. U1. 108 . 4. 1. 2..First-In-First-Out (FIFO) Algorithm Reference string: 1. by Parul Arora. 3. New Delhi-63. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 3. 4.

U1. New Delhi-63.. by Parul Arora.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 109 .

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

113 .Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.. U1.

2. 1. 3. New Delhi-63. 2. every time page is referenced through this entry.. look at the counters to determine which are to change. 1. When a page needs to be changed. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 114 . by Parul Arora.Least Recently Used (LRU) Algorithm Reference string: 1. 2. U1. 4. 4. 3. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. copy the clock into the counter. 5.

115 . New Delhi-63..LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

New Delhi-63. 116 . U1.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.LRU Algorithm (Cont. by Parul Arora..

New Delhi-63.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 117 . by Parul Arora. U1..

leave page in memory. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Second chance Need reference bit. We do not know the order. rules. New Delhi-63. replace next page (in clock order). initially = 0 When page is referenced bit set to 1. then: set reference bit 0. however. Clock replacement. If page to be replaced (in clock order) has reference bit = 1.. U1.LRU Approximation Algorithm Reference bit With each page associate a bit. Replace the one which is 0 (if one exists). by Parul Arora. 118 .

by Parul Arora. New Delhi-63. 119 .Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..

New Delhi-63. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. LFU Algorithm: replaces page with smallest count. by Parul Arora. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Counting Algorithms • Keep a counter of the number of references that have been made to each page. 120 . U1.

Allocation of Frames • Each process needs minimum number of pages. might span 2 pages. by Parul Arora. 121 . New Delhi-63. 2 pages to handle from. U1. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • Two major allocation schemes. 2 pages to handle to.

122 .g.. if 100 frames and 5 processes. • Proportional allocation – Allocate according to the size of process.Fixed Allocation • Equal allocation – e.. New Delhi-63. give each 20 pages. by Parul Arora. U1. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

select for replacement a frame from a process with lower priority number.. by Parul Arora. New Delhi-63. U1.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 123 . select for replacement one of its frames. • If process Pi generates a page fault.

one process can take a frame from another. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.. by Parul Arora. New Delhi-63.Global vs. U1. 124 . • Local replacement – each process selects from only its own set of allocated frames.

another process added to the system.Thrashing If a process does not have “enough” pages. Thrashing ≡ a process is busy swapping pages in and out. This leads to: low CPU utilization. by Parul Arora.. 125 . operating system thinks that it needs to increase the degree of multiprogramming. New Delhi-63. the page-fault rate is very high. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

by Parul Arora. Localities may overlap. U1. New Delhi-63.. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 126 .Thrashing Why does paging work? Locality model Process migrates from one locality to another.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

New Delhi-63. process loses frame. If actual rate too high. 130 . If actual rate too low.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. process gains frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1.

Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 131 . by Parul Arora. U1..

Otherwise there is a high degree of page faults. 132 .The amount of memory accessible from the TLB. TLB Reach = (TLB Size) X (Page Size) Ideally.) TLB Reach . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. the working set of each process is stored in the TLB. by Parul Arora. U1.Other Considerations (Cont. New Delhi-63.

Increasing the Size of the TLB • Increase the Page Size. • Provide Multiple Page Sizes. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. by Parul Arora.. U1. This may lead to an increase in fragmentation as not all applications require a large page size. New Delhi-63. 133 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

j < A.j] = 0. j < A. j++) for (i = 0. U1. i++) A[i. j++) A[i.Other Considerations (Cont.length.j] = 0..length. i < A.) Program structure int A[][] = new int[1024][1024].length. 1024 x 1024 page faults Program 2 for (i = 0. 134 . i < A.length. i++) for (j = 0. by Parul Arora. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Each row is stored in one page Program 1 for (j = 0. New Delhi-63.

and also allows degree of multiprogramming to be raised.. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Memory management algorithms differ in many concepts. New Delhi-63. Virtual memory frees application programers from worrying about memory availability U1. by Parul Arora. Virtual memory allows extremely large processes to be run. Multiprogramming increased the performance of computer system. .

and the operating system is responsible for managing them. Four major categories of operating systems are batch. Operating systems are a type of system software that allow applications to interface with computer hardware. . 136 Used. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. Second Chance. First In First Out.Summary • In the introduction. and Least Frequently U1. Resources are any objects that can be allocated within a system.. Policies for determining which pages to load and remove from memory include Random Replacement. personal computing and dedicated. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. timesharing. Least Recently Used. we saw that software can be roughly divided into two groups: application software and system software. New Delhi-63.

137 . U1. The Hardware mechanism that enables a device to notify the CPU is called __________. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Review Questions (OBJ) 1. a) Polling b) Interrupt c) System Call d) None of the above 2.. New Delhi-63.

U1.. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. Virtual memory is __________. 4. 138 . by Parul Arora. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 3. New Delhi-63.

The term " Operating System " means ________.Review Questions (OBJ) 5. by Parul Arora. New Delhi-63. 139 . a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. U1..

The main program is loaded into memory & is executed. All routines are kept on disk in a relocatable load format. by Parul Arora. The principle of locality of reference justifies the use of ________. ) Routine a) b) c) d) is not loaded until it is called. New Delhi-63.Review Questions (OBJ) 7.. U1. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 140 .

a) Program structure b) Program size c) Primary storage size d) None of the above U1. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. New Delhi-63.Review Questions (OBJ) 9. If all page frames are initially empty. 141 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ) The problem of thrashing is effected scientifically by ________. a) 10 b) 7 c) 8 d) 9 10.. the total number of page faults caused by the process will be __________. by Parul Arora.

Explain the difference between logical and physical addresses. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What is the main advantage of multiprogramming 2. List the four steps that are necessary to run a program on a completely dedicated machine 5.. How do MULTICS and UNIX differ? 7. What are the main differences between operating systems for mainframe computers and personal computers? 3. by Parul Arora. New Delhi-63. U1. Explain the difference between internal and external fragmentation 10.Review Questions (Short) 1. What are the three main purposes of an operating system? 4. 9. 142 . How does a real-time system differ from time-share? 8. How do I/O-bound and CPU-bound programs differ? 6.

When do page faults occur? 15. New Delhi-63. Describe the actions taken by the operating system when a page fault occurs. What is reentrant code? 14.. What is virtual memory? 17. What is meant by locality? 21. U1. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What is Belady’s anomaly? 19. by Parul Arora. 143 . Why is there a valid/invalid bit? Where is it kept? 18. What are overlays? 12. How was memory mapping used in extending the usefulness of minicomputers? 13.Review Questions (Short) 11. How do global and local allocation differ? 20. 16.

how would each of the First-?t. 200K. 7. to determine which page is victim. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 5. 5. if the entry is there. 4. and 600K (in order).Review Questions (Long) 1. 9. 5.. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 4. 8. 2. 3. 8. by Parul Arora. U1. Consider a paging system with the page table stored in memory. 9. 112K. 7. List ways to implement LRU. 1. 144 . for four page frames? 1. 4. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 500K. how long does a paged memory reference take? b. 8. Best-?t.)If we add associative registers. 4.) 3. a. Given memory partitions of 100K. and Worst-?t algorithms place processes of 212K. How many page faults occur for your algorithm for the following reference string. 417K.)If a memory reference takes 200 nanoseconds. and 75 percent of all pagetable references are found in the associative registers. 300K. 4. 3. 2. New Delhi-63. 6. 7.

Donovan J. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..6th Ed. 145 . “Operating System Concepts” Peason. U1. by Parul Arora. New Delhi-63. 2001 • "Operating Systems” Tannenbaum PHI...2001 • Madnick E..Recommended reading • Silbersachatz and Galvin. ”Operating System”: TMH. 4th Edition.

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