OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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. U1. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a program.Learning Objective Understand the purpose of the operating system Distinguish between a resource. New Delhi-63. by Parul Arora. 4 .

by Parul Arora.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. 5 .

6 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Make the computer system convenient to use. • Use the computer hardware in an efficient manner. New Delhi-63. by Parul Arora. • Operating system goals: Execute user programs and make solving user problems easier. U1.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware.

Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. by Parul Arora. Hardware – provides basic computing resources (CPU. video games. 3.. Users (people. business programs). New Delhi-63. 7 . U1. other computers). memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. machines. 2. database systems. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers.Computer System Components 1. I/O devices). 4.

by Parul Arora.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 8 . New Delhi-63.

.Operating System Definitions • Resource allocator – manages and allocates resources. U1. • Kernel – the one program running at all times (all else being application programs). by Parul Arora. 9 . • Control program – controls the execution of user programs and operations of I/O devices . New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. New Delhi-63.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 10 . U1..

First rudimentary operating system. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.. 11 .Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. U1.

by Parul Arora. 12 .Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1.

New Delhi-63. U1. by Parul Arora.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 13 ..

• Memory management – the system must allocate the memory to several jobs. • CPU scheduling – the system must choose among several jobs ready to run.OS Features Needed for Multiprogramming • I/O routine supplied by the system. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 14 . • Allocation of devices. New Delhi-63..

New Delhi-63. U1. A job swapped in and out of memory to the disk. On-line communication between the user and the system is provided. when the operating system finishes the execution of one command.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). by Parul Arora. .. it seeks the next “control statement” from the user’s keyboard. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

display screens.. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • User convenience and responsiveness. 16 . by Parul Arora.Desktop Systems • Personal computers – computer system dedicated to a single user. • May run several different types of operating systems (Windows. MacOS. mice. • I/O devices – keyboards. UNIX. U1. small printers.

• Tightly coupled system – processors share memory and a clock. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 17 . U1. communication usually takes place through the shared memory.Parallel Systems • Multiprocessor systems with more than on CPU in close communication..

18 . More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Parallel Systems (Cont. master processor schedules and allocated work to slave processors.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. by Parul Arora. Many processes can run at once without performance deterioration.. New Delhi-63. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.

. U1.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 19 . New Delhi-63.

Distributed Systems • Distribute the computation among several physical processors. 20 . U1. • Advantages of distributed systems. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • Loosely coupled system – each processor has its own local memory. processors communicate with one another through various communications lines. such as high-speed buses or telephone lines. by Parul Arora. New Delhi-63.

Distributed Systems (cont) • Requires networking infrastructure. 21 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.

22 .General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Asymmetric clustering: one server runs the application while other servers standby. 23 . by Parul Arora. • Symmetric clustering: all N hosts are running the application. New Delhi-63.Clustered Systems • Clustering allows two or more systems to share storage.. U1. • Provides high reliability.

U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. and some display systems. medical imaging systems. 24 . • Well-defined fixed-time constraints..Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. • Real-Time systems may be either hard or soft real-time. industrial control systems.

not supported by general-purpose operating systems. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.Real-Time Systems (Cont.. virtual reality) requiring advanced operating-system features. data stored in short term memory. New Delhi-63. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. . or read-only memory (ROM) Conflicts with time-sharing systems.) • Hard real-time: Secondary storage limited or absent.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 26 . New Delhi-63. by Parul Arora..Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens.

. 27 . by Parul Arora.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

U1. by Parul Arora. New Delhi-63. 28 ..Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

29 . New Delhi-63. by Parul arora U1.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management .

strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .how memory is structured Memory management . New Delhi-63. U1. 30 ..

New Delhi-63.. by Parul Arora.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 31 .

New Delhi-63.. by Parul Arora. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. 32 .Background • Program must be brought into memory and placed within a process for it to be run. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • User programs go through several steps before being run. U1.

. 33 . Need hardware support for address maps (e. • Load time: Must generate relocatable code if memory location is not known at compile time. by Parul Arora. must recompile code if starting location changes. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.g. absolute code can be generated.. base and limit registers).Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

. by Parul Arora. U1. 34 . New Delhi-63.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

35 . New Delhi-63. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.Logical vs.. also referred to as virtual address. U1. by Parul Arora. Logical address – generated by the CPU. logical (virtual) and physical addresses differ in execution-time address-binding scheme. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Physical address – address seen by the memory unit. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes.

• The user program deals with logical addresses. U1.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. 36 .Memory-Management Unit • Hardware device that maps virtual to physical address. • In MMU scheme. New Delhi-63. by Parul Arora. it never sees the real physical addresses.

by Parul Arora. U1. 37 .. New Delhi-63.Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.. New Delhi-63. by Parul Arora. • Useful when large amounts of code are needed to handle infrequently occurring cases. unused routine is never loaded. • No special support from the operating system is required implemented through program design.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 38 .

• Dynamic linking is particularly useful for libraries. New Delhi-63.Dynamic Linking • Linking postponed until execution time. • Small piece of code. stub. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Stub replaces itself with the address of the routine. used to locate the appropriate memory-resident library routine.. by Parul Arora. 39 . and executes the routine. U1. • Operating system needed to check if routine is in processes’ memory address.

by Parul Arora. 40 . programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. no special support needed from operating system. • Needed when process is larger than amount of memory allocated to it..Overlays • Keep in memory only those instructions and data that are needed at any given time. • Implemented by user. New Delhi-63.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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U1. by Parul Arora. usually held in low memory with interrupt vector. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. User processes then held in high memory. limit register contains range of logical addresses – each logical address must be less than the limit register.. Relocation register contains value of smallest physical address.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. New Delhi-63. 44 . and from changing operating-system code and data. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

45 . New Delhi-63.. by Parul Arora. U1.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.Contiguous Allocation (Cont. When a process arrives. by Parul Arora. New Delhi-63.. holes of various size are scattered throughout memory.) Multiple-partition allocation Hole – block of available memory. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 46 . it is allocated memory from a hole large enough to accommodate it.

Produces the largest leftover hole. unless ordered by size. New Delhi-63. by Parul Arora. must also search entire list. Worst-fit: Allocate the largest hole.. Best-fit: Allocate the smallest hole that is big enough. Produces the smallest leftover hole. 47 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. must search entire list.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. U1.

Fragmentation • External Fragmentation – total memory space exists to satisfy a request. but not being used. by Parul Arora. • Internal Fragmentation – allocated memory may be slightly larger than requested memory.. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. 48 . New Delhi-63. Compaction is possible only if relocation is dynamic. Do I/O only into OS buffers. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. I/O problem Latch job in memory while it is involved in I/O. this size difference is memory internal to a partition. U1. and is done at execution time. but it is not contiguous.

• Set up a page table to translate logical to physical addresses. by Parul Arora. between 512 bytes and 8192 bytes). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Keep track of all free frames. U1. 49 . • Internal fragmentation. • To run a program of size n pages. • Divide logical memory into blocks of same size called pages. process is allocated physical memory whenever the latter is available.Paging • Logical address space of a process can be noncontiguous.. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. need to find n free frames and load program. New Delhi-63.

New Delhi-63. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. 50 . by Parul Arora.. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 51 . New Delhi-63..

. U1.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 52 .

by Parul Arora. U1.. 53 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

U1. New Delhi-63. by Parul Arora. 54 ..Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• In this scheme every data/instruction access requires two memory accesses. New Delhi-63. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page-table length register (PRLR) indicates size of the page table. by Parul Arora. • Page-table base register (PTBR) points to the page table. 55 . One for the page table and one for the data/instruction. U1.Implementation of Page Table • Page table is kept in main memory..

A´´) If A´ is in associative register. 56 . get frame # out. by Parul Arora. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´.. U1.

. 57 . U1.Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

58 . New Delhi-63. U1. by Parul Arora. ration related to number of associative registers.. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.

“invalid” indicates that the page is not in the process’ logical address space.Memory Protection • Memory protection implemented by associating protection bit with each frame. U1. and is thus a legal page. New Delhi-63. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. 59 .. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. U1.. 60 .Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

by Parul Arora. New Delhi-63..Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 61 . U1.

U1. • A simple technique is a two-level page table. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 62 .Hierarchical Page Tables • Break up the logical address space into multiple page tables. by Parul Arora.

the page number is further divided into: Thus. by Parul Arora.. Since the page table is paged. New Delhi-63. 63 . a 10-bit page offset. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a page offset consisting of 12 bits. U1.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a logical address is as follows: pi p2 d 10 10 a 10-bit page number.

by Parul Arora. U1. 64 . New Delhi-63..Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 65 . by Parul Arora. New Delhi-63.

U1. the corresponding physical frame is extracted.Hashed Page Tables • Common in address spaces > 32 bits. by Parul Arora. 66 .. New Delhi-63. • Virtual page numbers are compared in this chain searching for a match. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This page table contains a chain of elements hashing to the same location. • The virtual page number is hashed into a page table. If a match is found.

. 67 .Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1.

by Parul Arora. with information about the process that owns that page. New Delhi-63. 68 . • Decreases memory needed to store each page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • Entry consists of the virtual address of the page stored in that real memory location. but increases time needed to search the table when a page reference occurs. U1. • Use hash table to limit the search to one — or at most a few — page-table entries.Inverted Page Table • One entry for each real page of memory.

New Delhi-63..Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 69 . U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. The pages for the private code and data can appear anywhere in the logical address space.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. Private code and data Each process keeps a separate copy of the code and data.. New Delhi-63. U1. window systems).. 70 . Shared code must appear in same location in the logical address space of all processes. compilers. text editors.e.

Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. by Parul Arora. 71 .

Segmentation Memory-management scheme that supports user view of memory. object. A segment is a logical unit such as: main program. common block. global variables.. symbol table. U1. local variables. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 72 . method. procedure. function. A program is a collection of segments. New Delhi-63. stack. by Parul Arora.

. by Parul Arora. 73 . U1.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 74 . New Delhi-63. by Parul Arora.. U1.

U1.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. offset>. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. 75 . • • • Segment-table base register (STBR) points to the segment table’s location in memory. Segment table – maps two-dimensional physical addresses.. New Delhi-63. limit – specifies the length of the segment. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. each table entry has: base – contains the starting physical address where the segments reside in memory.

. by Parul Arora. 76 . dynamic by segment table • Sharing. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Architecture (Cont. shared segments same segment number • Allocation. New Delhi-63. U1.) • Relocation.

• A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 77 .. • Since segments vary in length. memory allocation is a dynamic storage-allocation problem.) • Protection. New Delhi-63. code sharing occurs at segment level. U1. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.Segmentation Architecture (Cont. by Parul Arora.

U1.. by Parul Arora. New Delhi-63. 78 .Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 79 . New Delhi-63.. by Parul Arora.

by Parul Arora.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 80 . U1.. New Delhi-63.

by Parul Arora. 81 . • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment.. but rather the base address of a page table for this segment. New Delhi-63. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.

by Parul Arora. New Delhi-63. U1..MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 82 .

83 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63.Segmentation with Paging – Intel 386 As shown in the following diagram. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.

84 . by Parul Arora. U1.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

by Parul arora U1. New Delhi-63. 85 .Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management .

by Parul Arora. • Summarize the principles of virtual memory as applied to caching and paging. • Describe the reason for and use of cache memory. 86 .Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software.. • Evaluate the trade-offs in terms of memory size (main memory. • Discuss the concept of thrashing. New Delhi-63. cache memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. auxiliary memory) and processor speed. U1.

Allows for more efficient process creation. by Parul Arora. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. . Logical address space can therefore be much larger than physical address space. • Virtual memory can be implemented via: Demand paging Demand segmentation U1.Background • Virtual memory – separation of user logical memory from physical memory. Allows address spaces to be shared by several processes.. Only part of the program needs to be in memory for execution.

88 .Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1. New Delhi-63.

. 89 . by Parul Arora. New Delhi-63. U1. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Demand Paging Bring a page into memory only when it is needed.

90 . U1.. by Parul Arora.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.. by Parul Arora.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. 91 . U1. New Delhi-63. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but valid-invalid bit 1 Example of a page table snapshot.

U1.. 92 . New Delhi-63.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

. Restart instruction: Least Recently Used block move U1. by Parul Arora. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Reset tables. New Delhi-63.Page Fault • If there is ever a reference to a page. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort.. validation bit = 1. • • • • Get empty frame. Just not in memory. Swap page into frame.

by Parul Arora. 94 . New Delhi-63.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

New Delhi-63. 95 . by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. but not really in use. algorithm performance – want an algorithm which will result in minimum number of page faults.What happens if there is no free frame? • Page replacement – find some page in memory. swap it out.. • Same page may be brought into memory several times.

96 .Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.0 if p = 0 no page faults if p = 1. by Parul Arora.. U1. New Delhi-63.

. by Parul Arora.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. Swap Page Time = 10 msec = 10. New Delhi-63.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. 97 .

by Parul Arora. 98 .. New Delhi-63.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. by Parul Arora. • Free pages are allocated from a pool of zeroed-out pages. New Delhi-63. 99 . only then is the page copied. U1. • COW allows more efficient process creation as only modified pages are copied..If either process modifies a shared page. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

A page-sized portion of the file is read from the file system into a physical page. • A file is initially read using demand paging. U1. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. • Also allows several processes to map the same file allowing the pages in memory to be shared.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. Subsequent reads/writes to/from the file are treated as ordinary memory accesses.. New Delhi-63. .

by Parul Arora.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 101 .. U1.

• Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk.. by Parul Arora. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. 102 .

Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63. by Parul Arora. 103 .

use a page replacement algorithm to select a victim frame. 104 .If there is no free frame.Basic Page Replacement • Find the location of the desired page on disk. use it. • Read the desired page into the (newly) free frame. by Parul Arora. • Restart the process. • Find a free frame: . Update the page and frame tables. U1.If there is a free frame. . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 105 . New Delhi-63. by Parul Arora.

106 . 4. 4. by Parul Arora. the reference string is 1. 2. 2. 3. 3. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. In all our examples. 5. 5. 1. 2.Page Replacement Algorithms Want lowest page-fault rate. 1.. New Delhi-63.

107 .. by Parul Arora. U1.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

4. 1.. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 1. by Parul Arora. 5. 2. 3. 3. 4. 2. U1. 2.First-In-First-Out (FIFO) Algorithm Reference string: 1. 108 .

New Delhi-63. 109 . U1.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

by Parul Arora.Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.. 113 .

2. 114 . every time page is referenced through this entry. 4. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. copy the clock into the counter. 3. 2. 5. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 2. When a page needs to be changed. New Delhi-63.Least Recently Used (LRU) Algorithm Reference string: 1. 1. 4. 1. 3. by Parul Arora. look at the counters to determine which are to change..

LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 115 . U1.. by Parul Arora. New Delhi-63.

by Parul Arora.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.LRU Algorithm (Cont. 116 . U1.

117 .Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. by Parul Arora.

Replace the one which is 0 (if one exists).. replace next page (in clock order). initially = 0 When page is referenced bit set to 1. We do not know the order. Clock replacement. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. then: set reference bit 0. however. U1. rules. by Parul Arora. leave page in memory.LRU Approximation Algorithm Reference bit With each page associate a bit. Second chance Need reference bit. 118 . If page to be replaced (in clock order) has reference bit = 1.

New Delhi-63.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 119 . U1.

New Delhi-63.Counting Algorithms • Keep a counter of the number of references that have been made to each page. U1. 120 . by Parul Arora. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. LFU Algorithm: replaces page with smallest count.. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used.

. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2 pages to handle to. • Two major allocation schemes. 121 .Allocation of Frames • Each process needs minimum number of pages. New Delhi-63. U1. 2 pages to handle from. might span 2 pages. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. by Parul Arora.

Fixed Allocation • Equal allocation – e. 122 ...g. New Delhi-63. if 100 frames and 5 processes. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. give each 20 pages. • Proportional allocation – Allocate according to the size of process.

123 . • If process Pi generates a page fault. select for replacement a frame from a process with lower priority number. New Delhi-63. by Parul Arora. select for replacement one of its frames. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Priority Allocation • Use a proportional allocation scheme using priorities rather than size..

by Parul Arora. U1. 124 .. • Local replacement – each process selects from only its own set of allocated frames. New Delhi-63. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Global vs. one process can take a frame from another.

. operating system thinks that it needs to increase the degree of multiprogramming. the page-fault rate is very high. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This leads to: low CPU utilization. 125 . another process added to the system. Thrashing ≡ a process is busy swapping pages in and out. New Delhi-63. by Parul Arora.Thrashing If a process does not have “enough” pages.

. U1. New Delhi-63. by Parul Arora.Thrashing Why does paging work? Locality model Process migrates from one locality to another. 126 . Localities may overlap. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

. U1.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. process loses frame. If actual rate too low. If actual rate too high. by Parul Arora. New Delhi-63. process gains frame. 130 .

U1. 131 .Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63.

The amount of memory accessible from the TLB.) TLB Reach .Other Considerations (Cont.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. Otherwise there is a high degree of page faults. the working set of each process is stored in the TLB. U1. TLB Reach = (TLB Size) X (Page Size) Ideally. 132 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. This may lead to an increase in fragmentation as not all applications require a large page size. U1. • Provide Multiple Page Sizes. New Delhi-63.. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. by Parul Arora.Increasing the Size of the TLB • Increase the Page Size. 133 .

Each row is stored in one page Program 1 for (j = 0. New Delhi-63. j < A.length. by Parul Arora. i < A.j] = 0. j++) for (i = 0.. 134 . i++) for (j = 0. U1. j < A. i < A. i++) A[i. j++) A[i.Other Considerations (Cont.j] = 0.length. 1024 x 1024 page faults Program 2 for (i = 0. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) Program structure int A[][] = new int[1024][1024].length.length.

Virtual memory frees application programers from worrying about memory availability U1. by Parul Arora. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . Memory management algorithms differ in many concepts.. Multiprogramming increased the performance of computer system. Virtual memory allows extremely large processes to be run.and also allows degree of multiprogramming to be raised. New Delhi-63.Conclusion • • • • • Operating systems provide an environment for development and execution of programs.

. Second Chance. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. New Delhi-63. and the operating system is responsible for managing them. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. timesharing. Resources are any objects that can be allocated within a system. personal computing and dedicated. Policies for determining which pages to load and remove from memory include Random Replacement. we saw that software can be roughly divided into two groups: application software and system software. Four major categories of operating systems are batch. and Least Frequently U1. Least Recently Used. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . Operating systems are a type of system software that allow applications to interface with computer hardware. 136 Used. First In First Out.Summary • In the introduction.

New Delhi-63. The Hardware mechanism that enables a device to notify the CPU is called __________. by Parul Arora. a) Polling b) Interrupt c) System Call d) None of the above 2. U1.. 137 . Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 1.

by Parul Arora.Review Questions (OBJ) 3. 138 . U1. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. Virtual memory is __________. New Delhi-63.. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 4.

U1.. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. 139 .Review Questions (OBJ) 5. New Delhi-63. by Parul Arora. The term " Operating System " means ________. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. 140 . All routines are kept on disk in a relocatable load format.Review Questions (OBJ) 7. ) Routine a) b) c) d) is not loaded until it is called. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. The main program is loaded into memory & is executed. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. by Parul Arora. The principle of locality of reference justifies the use of ________..

Review Questions (OBJ) 9. 141 . and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. the total number of page faults caused by the process will be __________.. ) The problem of thrashing is effected scientifically by ________. If all page frames are initially empty. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a) Program structure b) Program size c) Primary storage size d) None of the above U1. a) 10 b) 7 c) 8 d) 9 10.

U1.. How does a real-time system differ from time-share? 8. 9. How do I/O-bound and CPU-bound programs differ? 6. What are the three main purposes of an operating system? 4. What are the main differences between operating systems for mainframe computers and personal computers? 3. by Parul Arora. New Delhi-63. What is the main advantage of multiprogramming 2. How do MULTICS and UNIX differ? 7. 142 . List the four steps that are necessary to run a program on a completely dedicated machine 5. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Explain the difference between internal and external fragmentation 10. Explain the difference between logical and physical addresses.Review Questions (Short) 1.

What is reentrant code? 14. How do global and local allocation differ? 20. U1.. Describe the actions taken by the operating system when a page fault occurs. 143 . New Delhi-63. When do page faults occur? 15. by Parul Arora.Review Questions (Short) 11. How was memory mapping used in extending the usefulness of minicomputers? 13. What are overlays? 12. What is meant by locality? 21. 16. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What is virtual memory? 17. What is Belady’s anomaly? 19. Why is there a valid/invalid bit? Where is it kept? 18.

5. 417K. how would each of the First-?t. 8. 5. 144 . 200K. 4.. 7. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. by Parul Arora. 4. List ways to implement LRU. 9. 3. 7. 2. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Best-?t. 7. 8. and 600K (in order). and 75 percent of all pagetable references are found in the associative registers. New Delhi-63. 3. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. to determine which page is victim. how long does a paged memory reference take? b. Consider a paging system with the page table stored in memory. 4. 1. How many page faults occur for your algorithm for the following reference string.) 3. 4. 4. a. Given memory partitions of 100K. 9. 2. 300K.)If a memory reference takes 200 nanoseconds. 500K. 5.)If we add associative registers. 8. if the entry is there.Review Questions (Long) 1. 112K. 6. and Worst-?t algorithms place processes of 212K. for four page frames? 1. U1.

Recommended reading • Silbersachatz and Galvin.. “Operating System Concepts” Peason. 145 . New Delhi-63..2001 • Madnick E.. 4th Edition. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.6th Ed.. 2001 • "Operating Systems” Tannenbaum PHI. Donovan J. U1. by Parul Arora. ”Operating System”: TMH.

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