OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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by Parul Arora. a program. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 4 .Learning Objective Understand the purpose of the operating system Distinguish between a resource. New Delhi-63.. U1.

. U1. New Delhi-63. 5 . by Parul Arora.Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Make the computer system convenient to use. U1.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. • Operating system goals: Execute user programs and make solving user problems easier.. • Use the computer hardware in an efficient manner. 6 . New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers.Computer System Components 1. Hardware – provides basic computing resources (CPU.. I/O devices). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 3. memory. 7 . 4. machines. database systems. Users (people. by Parul Arora. 2. video games. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. business programs). other computers). New Delhi-63.

New Delhi-63. 8 . U1..Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

Operating System Definitions • Resource allocator – manages and allocates resources. U1. by Parul Arora. • Kernel – the one program running at all times (all else being application programs). • Control program – controls the execution of user programs and operations of I/O devices . 9 . New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

by Parul Arora..Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 10 . New Delhi-63. U1.

• Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. First rudimentary operating system.. by Parul Arora. 11 .Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another.

by Parul Arora.. U1.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 12 .

13 .Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora. U1.

New Delhi-63.OS Features Needed for Multiprogramming • I/O routine supplied by the system. • Allocation of devices.. • CPU scheduling – the system must choose among several jobs ready to run. by Parul Arora. • Memory management – the system must allocate the memory to several jobs. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 14 . U1.

. by Parul Arora. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. On-line communication between the user and the system is provided. it seeks the next “control statement” from the user’s keyboard. when the operating system finishes the execution of one command. U1.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). A job swapped in and out of memory to the disk. . New Delhi-63.

New Delhi-63. small printers. display screens. UNIX. mice. U1..Desktop Systems • Personal computers – computer system dedicated to a single user. • I/O devices – keyboards. • User convenience and responsiveness. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. MacOS. 16 . • May run several different types of operating systems (Windows. by Parul Arora. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Parallel Systems • Multiprocessor systems with more than on CPU in close communication. communication usually takes place through the shared memory. by Parul Arora. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. 17 . • Tightly coupled system – processors share memory and a clock..

More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Parallel Systems (Cont. master processor schedules and allocated work to slave processors. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. New Delhi-63. 18 . Many processes can run at once without performance deterioration..) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. by Parul Arora. U1.

New Delhi-63.. U1.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 19 .

New Delhi-63. 20 . • Loosely coupled system – each processor has its own local memory. by Parul Arora. • Advantages of distributed systems.Distributed Systems • Distribute the computation among several physical processors. U1. processors communicate with one another through various communications lines. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. such as high-speed buses or telephone lines..

U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.. 21 .Distributed Systems (cont) • Requires networking infrastructure. New Delhi-63. by Parul Arora.

22 . U1. by Parul Arora..General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

New Delhi-63.. U1. • Symmetric clustering: all N hosts are running the application. • Provides high reliability.Clustered Systems • Clustering allows two or more systems to share storage. • Asymmetric clustering: one server runs the application while other servers standby. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 23 .

and some display systems. industrial control systems. • Well-defined fixed-time constraints.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. U1. by Parul Arora. • Real-Time systems may be either hard or soft real-time. medical imaging systems. New Delhi-63. 24 .

• Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. New Delhi-63. .) • Hard real-time: Secondary storage limited or absent. data stored in short term memory. or read-only memory (ROM) Conflicts with time-sharing systems. by Parul Arora. not supported by general-purpose operating systems. virtual reality) requiring advanced operating-system features. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Real-Time Systems (Cont. U1.

by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. New Delhi-63. 26 . U1.

. by Parul Arora. U1.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 27 .

by Parul Arora.. 28 .Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

by Parul arora U1. 29 .Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63.

30 .. New Delhi-63.strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . U1.how memory is structured Memory management . by Parul Arora.

by Parul Arora. U1.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 31 . New Delhi-63..

by Parul Arora. U1. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program.. New Delhi-63. • User programs go through several steps before being run. 32 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Background • Program must be brought into memory and placed within a process for it to be run.

• Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. U1. Need hardware support for address maps (e. must recompile code if starting location changes. 33 . by Parul Arora. absolute code can be generated. • Load time: Must generate relocatable code if memory location is not known at compile time..g.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. New Delhi-63. base and limit registers).. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. by Parul Arora. New Delhi-63. U1.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 34 .

U1. by Parul Arora. logical (virtual) and physical addresses differ in execution-time address-binding scheme.. also referred to as virtual address. New Delhi-63. Logical address – generated by the CPU. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 35 .Logical vs. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Physical address – address seen by the memory unit. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 36 .. • In MMU scheme. U1.Memory-Management Unit • Hardware device that maps virtual to physical address. it never sees the real physical addresses. by Parul Arora. New Delhi-63. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. • The user program deals with logical addresses.

U1.. 37 .Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

unused routine is never loaded.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. • Useful when large amounts of code are needed to handle infrequently occurring cases.. 38 . • No special support from the operating system is required implemented through program design. U1. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1. by Parul Arora. • Operating system needed to check if routine is in processes’ memory address. • Dynamic linking is particularly useful for libraries. stub. • Stub replaces itself with the address of the routine. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. used to locate the appropriate memory-resident library routine.. and executes the routine.Dynamic Linking • Linking postponed until execution time. 39 . • Small piece of code.

U1. • Implemented by user. 40 .Overlays • Keep in memory only those instructions and data that are needed at any given time. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Needed when process is larger than amount of memory allocated to it.. by Parul Arora. no special support needed from operating system. New Delhi-63.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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limit register contains range of logical addresses – each logical address must be less than the limit register.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. and from changing operating-system code and data. New Delhi-63. U1. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. User processes then held in high memory. usually held in low memory with interrupt vector. Relocation register contains value of smallest physical address. by Parul Arora. 44 .

45 .Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora. U1.

. it is allocated memory from a hole large enough to accommodate it. 46 .Contiguous Allocation (Cont. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.) Multiple-partition allocation Hole – block of available memory. holes of various size are scattered throughout memory. by Parul Arora. When a process arrives.

Produces the smallest leftover hole. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. must search entire list.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. U1. Worst-fit: Allocate the largest hole.. by Parul Arora. Produces the largest leftover hole. unless ordered by size. must also search entire list. New Delhi-63. Best-fit: Allocate the smallest hole that is big enough. 47 .

this size difference is memory internal to a partition. U1. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. and is done at execution time. New Delhi-63. Compaction is possible only if relocation is dynamic.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. 48 . I/O problem Latch job in memory while it is involved in I/O. • Internal Fragmentation – allocated memory may be slightly larger than requested memory.. but not being used. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Do I/O only into OS buffers. but it is not contiguous. by Parul Arora.

process is allocated physical memory whenever the latter is available. • To run a program of size n pages. • Internal fragmentation. 49 .Paging • Logical address space of a process can be noncontiguous. • Divide physical memory into fixed-sized blocks called frames (size is power of 2.. between 512 bytes and 8192 bytes). New Delhi-63. need to find n free frames and load program. • Divide logical memory into blocks of same size called pages. • Set up a page table to translate logical to physical addresses. by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Keep track of all free frames.

50 . New Delhi-63. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. by Parul Arora..

51 .. U1. New Delhi-63.Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

. New Delhi-63. 52 . U1. by Parul Arora.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. by Parul Arora. 53 .. U1.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. U1.Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 54 .

• In this scheme every data/instruction access requires two memory accesses. by Parul Arora.. New Delhi-63. 55 . U1. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page-table base register (PTBR) points to the page table. • Page-table length register (PRLR) indicates size of the page table. One for the page table and one for the data/instruction.Implementation of Page Table • Page table is kept in main memory.

A´´) If A´ is in associative register. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. get frame # out.. by Parul Arora. U1.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. 56 .

U1..Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 57 .

U1. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ration related to number of associative registers. New Delhi-63.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.. 58 . by Parul Arora.

“invalid” indicates that the page is not in the process’ logical address space. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Memory Protection • Memory protection implemented by associating protection bit with each frame. by Parul Arora. U1. and is thus a legal page.. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. 59 .

by Parul Arora. New Delhi-63.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 60 .

61 . by Parul Arora. U1..Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Hierarchical Page Tables • Break up the logical address space into multiple page tables. • A simple technique is a two-level page table. 62 . New Delhi-63. U1. by Parul Arora.

New Delhi-63. a page offset consisting of 12 bits. the page number is further divided into: Thus. U1. 63 . Since the page table is paged..Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a 10-bit page offset. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. a logical address is as follows: pi p2 d 10 10 a 10-bit page number.

New Delhi-63. 64 .Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1..

Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 65 . by Parul Arora. U1.

• The virtual page number is hashed into a page table. If a match is found. • Virtual page numbers are compared in this chain searching for a match. U1. by Parul Arora. the corresponding physical frame is extracted.. This page table contains a chain of elements hashing to the same location. 66 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Hashed Page Tables • Common in address spaces > 32 bits. New Delhi-63.

Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 67 . New Delhi-63. U1.

• Entry consists of the virtual address of the page stored in that real memory location. • Use hash table to limit the search to one — or at most a few — page-table entries.. 68 . U1.Inverted Page Table • One entry for each real page of memory. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. with information about the process that owns that page. but increases time needed to search the table when a page reference occurs. • Decreases memory needed to store each page table.

by Parul Arora. U1.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 69 . New Delhi-63..

Private code and data Each process keeps a separate copy of the code and data. Shared code must appear in same location in the logical address space of all processes. compilers.. text editors.e. U1. New Delhi-63.. The pages for the private code and data can appear anywhere in the logical address space. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 70 .Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. by Parul Arora. window systems).

71 . by Parul Arora. U1. New Delhi-63.Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

symbol table.Segmentation Memory-management scheme that supports user view of memory. global variables. function. method.. common block. A segment is a logical unit such as: main program. New Delhi-63. procedure. U1. stack. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. object. local variables. A program is a collection of segments. by Parul Arora. 72 .

U1.. New Delhi-63.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 73 . by Parul Arora.

by Parul Arora. 74 . New Delhi-63.. U1.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

75 . U1. limit – specifies the length of the segment. each table entry has: base – contains the starting physical address where the segments reside in memory. Segment table – maps two-dimensional physical addresses. offset>..Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. • • • Segment-table base register (STBR) points to the segment table’s location in memory.

U1. New Delhi-63.. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.) • Relocation. shared segments same segment number • Allocation.Segmentation Architecture (Cont. 76 . dynamic by segment table • Sharing. by Parul Arora.

. code sharing occurs at segment level. memory allocation is a dynamic storage-allocation problem. by Parul Arora.) • Protection.Segmentation Architecture (Cont. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Since segments vary in length. New Delhi-63. 77 . With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.

by Parul Arora.. 78 . New Delhi-63.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

by Parul Arora. 79 . U1. New Delhi-63.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

New Delhi-63. 80 .Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1.

Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. 81 . but rather the base address of a page table for this segment. New Delhi-63. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

. 82 . New Delhi-63.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.

the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. 83 .Segmentation with Paging – Intel 386 As shown in the following diagram. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. by Parul Arora.

by Parul Arora. New Delhi-63.. 84 .Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

by Parul arora U1.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 85 . New Delhi-63.

U1. 86 . by Parul Arora. auxiliary memory) and processor speed. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Discuss the concept of thrashing. • Evaluate the trade-offs in terms of memory size (main memory. cache memory. • Summarize the principles of virtual memory as applied to caching and paging. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. New Delhi-63. • Describe the reason for and use of cache memory..

• Virtual memory can be implemented via: Demand paging Demand segmentation U1. Logical address space can therefore be much larger than physical address space. . Allows for more efficient process creation. by Parul Arora. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. Only part of the program needs to be in memory for execution.Background • Virtual memory – separation of user logical memory from physical memory.. Allows address spaces to be shared by several processes.

U1.Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. 88 .

89 .. U1. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.Demand Paging Bring a page into memory only when it is needed.

New Delhi-63.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.. 90 .

.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. 91 . 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. but valid-invalid bit 1 Example of a page table snapshot.

by Parul Arora.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. 92 .

. New Delhi-63. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort. • • • • Get empty frame.Page Fault • If there is ever a reference to a page. by Parul Arora. . Reset tables. Swap page into frame. Just not in memory. validation bit = 1. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Restart instruction: Least Recently Used block move U1.

Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.. New Delhi-63. 94 .

by Parul Arora. New Delhi-63. but not really in use.. U1. 95 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Same page may be brought into memory several times.What happens if there is no free frame? • Page replacement – find some page in memory. swap it out. algorithm performance – want an algorithm which will result in minimum number of page faults.

.0 if p = 0 no page faults if p = 1. New Delhi-63. by Parul Arora. 96 . U1.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Swap Page Time = 10 msec = 10.Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. New Delhi-63.. U1. 97 .

Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 98 . New Delhi-63.. by Parul Arora. U1.

U1. • COW allows more efficient process creation as only modified pages are copied. by Parul Arora.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. New Delhi-63. only then is the page copied. • Free pages are allocated from a pool of zeroed-out pages.If either process modifies a shared page. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 99 ..

by Parul Arora. A page-sized portion of the file is read from the file system into a physical page. Subsequent reads/writes to/from the file are treated as ordinary memory accesses..Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . • Also allows several processes to map the same file allowing the pages in memory to be shared. U1. • A file is initially read using demand paging. New Delhi-63.

by Parul Arora.. New Delhi-63.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 101 .

102 .. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. by Parul Arora. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. New Delhi-63. U1. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.

New Delhi-63. U1. 103 .. by Parul Arora.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.If there is a free frame. 104 . .If there is no free frame. New Delhi-63. • Read the desired page into the (newly) free frame..Basic Page Replacement • Find the location of the desired page on disk. use it. • Restart the process. by Parul Arora. • Find a free frame: . use a page replacement algorithm to select a victim frame. Update the page and frame tables.

.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 105 . U1. New Delhi-63. by Parul Arora.

by Parul Arora.Page Replacement Algorithms Want lowest page-fault rate. 106 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the reference string is 1. 1. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. 4. 4. 5. 5. New Delhi-63. 2. 2. 2. 1. U1. 3.. 3. In all our examples.

U1. New Delhi-63..Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 107 . by Parul Arora.

. 108 . 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 3. 1. 2. 3. by Parul Arora. 2. 5. 1.First-In-First-Out (FIFO) Algorithm Reference string: 1. 4. New Delhi-63. U1. 4. 2.

by Parul Arora.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 109 ..

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 113 . U1. by Parul Arora..

Least Recently Used (LRU) Algorithm Reference string: 1. 5.. 1. 3. 4. by Parul Arora. 1. look at the counters to determine which are to change. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. When a page needs to be changed. 2. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. every time page is referenced through this entry. U1. 3. 2. 114 . 4. New Delhi-63. copy the clock into the counter.

115 . U1.LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora..

U1.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.LRU Algorithm (Cont. 116 . New Delhi-63.. by Parul Arora.

U1. by Parul Arora.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 117 .

. replace next page (in clock order). however. rules. If page to be replaced (in clock order) has reference bit = 1.LRU Approximation Algorithm Reference bit With each page associate a bit. New Delhi-63. leave page in memory. by Parul Arora. Second chance Need reference bit. initially = 0 When page is referenced bit set to 1. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. then: set reference bit 0. 118 . We do not know the order. Clock replacement. Replace the one which is 0 (if one exists).

U1. New Delhi-63. 119 . by Parul Arora.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

LFU Algorithm: replaces page with smallest count. New Delhi-63. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. by Parul Arora. U1. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Counting Algorithms • Keep a counter of the number of references that have been made to each page.. 120 .

2 pages to handle to.Allocation of Frames • Each process needs minimum number of pages. might span 2 pages. 121 .. New Delhi-63. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. by Parul Arora. U1. 2 pages to handle from. • Two major allocation schemes. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Proportional allocation – Allocate according to the size of process. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 122 . give each 20 pages..g. if 100 frames and 5 processes.. by Parul Arora.Fixed Allocation • Equal allocation – e.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. select for replacement one of its frames. New Delhi-63. select for replacement a frame from a process with lower priority number. 123 . • If process Pi generates a page fault. U1.Priority Allocation • Use a proportional allocation scheme using priorities rather than size..

. U1. • Local replacement – each process selects from only its own set of allocated frames. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 124 . Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.Global vs. one process can take a frame from another. New Delhi-63.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. Thrashing ≡ a process is busy swapping pages in and out. 125 .. U1. by Parul Arora. operating system thinks that it needs to increase the degree of multiprogramming. This leads to: low CPU utilization.Thrashing If a process does not have “enough” pages. the page-fault rate is very high. another process added to the system. New Delhi-63.

126 . by Parul Arora. U1. New Delhi-63. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Thrashing Why does paging work? Locality model Process migrates from one locality to another. Localities may overlap..

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

130 . U1. process loses frame. New Delhi-63. If actual rate too low.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. process gains frame. If actual rate too high.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. by Parul Arora.

131 . New Delhi-63.. U1. by Parul Arora.Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

TLB Reach = (TLB Size) X (Page Size) Ideally. © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Other Considerations (Cont. U1. by Parul Arora.) TLB Reach .The amount of memory accessible from the TLB. Otherwise there is a high degree of page faults. the working set of each process is stored in the TLB. New Delhi-63. 132 .

U1. This may lead to an increase in fragmentation as not all applications require a large page size. New Delhi-63.Increasing the Size of the TLB • Increase the Page Size. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. • Provide Multiple Page Sizes.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 133 .

length.length.. i < A.length.length. by Parul Arora. j < A. j < A.j] = 0. New Delhi-63. 1024 x 1024 page faults Program 2 for (i = 0. U1. j++) for (i = 0.) Program structure int A[][] = new int[1024][1024]. i++) for (j = 0. i < A. j++) A[i. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Each row is stored in one page Program 1 for (j = 0.j] = 0. 134 .Other Considerations (Cont. i++) A[i.

. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Virtual memory frees application programers from worrying about memory availability U1. Multiprogramming increased the performance of computer system. Virtual memory allows extremely large processes to be run..and also allows degree of multiprogramming to be raised. Memory management algorithms differ in many concepts.

Policies for determining which pages to load and remove from memory include Random Replacement. . Operating systems are a type of system software that allow applications to interface with computer hardware. Four major categories of operating systems are batch. and the operating system is responsible for managing them.Summary • In the introduction. 136 Used. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. timesharing. we saw that software can be roughly divided into two groups: application software and system software. Second Chance. personal computing and dedicated. Resources are any objects that can be allocated within a system. by Parul Arora. New Delhi-63. First In First Out. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. and Least Frequently U1. Least Recently Used.

by Parul Arora.. The Hardware mechanism that enables a device to notify the CPU is called __________. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 137 . a) Polling b) Interrupt c) System Call d) None of the above 2.Review Questions (OBJ) 1. New Delhi-63. U1.

a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. by Parul Arora. U1. 4. 138 .Review Questions (OBJ) 3. Virtual memory is __________. New Delhi-63. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Review Questions (OBJ) 5. U1. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. The term " Operating System " means ________. New Delhi-63. by Parul Arora. 139 ..

The principle of locality of reference justifies the use of ________. ) Routine a) b) c) d) is not loaded until it is called. by Parul Arora. U1. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. 140 . a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Review Questions (OBJ) 7.. All routines are kept on disk in a relocatable load format. The main program is loaded into memory & is executed.

and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. by Parul Arora.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. If all page frames are initially empty.Review Questions (OBJ) 9. a) 10 b) 7 c) 8 d) 9 10. 141 . ) The problem of thrashing is effected scientifically by ________. New Delhi-63. a) Program structure b) Program size c) Primary storage size d) None of the above U1. the total number of page faults caused by the process will be __________.

. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. What are the three main purposes of an operating system? 4. 9. U1. What are the main differences between operating systems for mainframe computers and personal computers? 3. List the four steps that are necessary to run a program on a completely dedicated machine 5. New Delhi-63.Review Questions (Short) 1. How do I/O-bound and CPU-bound programs differ? 6. by Parul Arora. How does a real-time system differ from time-share? 8. Explain the difference between logical and physical addresses. 142 . How do MULTICS and UNIX differ? 7. Explain the difference between internal and external fragmentation 10. What is the main advantage of multiprogramming 2.

by Parul Arora. U1. What are overlays? 12. When do page faults occur? 15. What is reentrant code? 14. New Delhi-63. 16.. What is meant by locality? 21. Why is there a valid/invalid bit? Where is it kept? 18. How do global and local allocation differ? 20. 143 . What is virtual memory? 17.Review Questions (Short) 11. What is Belady’s anomaly? 19. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How was memory mapping used in extending the usefulness of minicomputers? 13. Describe the actions taken by the operating system when a page fault occurs.

4. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 2. 7. Given memory partitions of 100K.)If we add associative registers. by Parul Arora. for four page frames? 1. Consider a paging system with the page table stored in memory. 4. and 75 percent of all pagetable references are found in the associative registers. 3. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 9. how long does a paged memory reference take? b. How many page faults occur for your algorithm for the following reference string.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. how would each of the First-?t. List ways to implement LRU. 200K. and Worst-?t algorithms place processes of 212K. 5. 2. 1. a. Best-?t. to determine which page is victim. 417K. 5. 4. 144 . 4. New Delhi-63.) 3. 8. 7. 4. and 600K (in order). 300K. 3. 8. 9.)If a memory reference takes 200 nanoseconds. 6. 8.Review Questions (Long) 1. 112K. 7. 5. if the entry is there. 500K. U1.

Donovan J.2001 • Madnick E. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2001 • "Operating Systems” Tannenbaum PHI... ”Operating System”: TMH. U1.Recommended reading • Silbersachatz and Galvin. New Delhi-63.6th Ed. “Operating System Concepts” Peason. by Parul Arora.. 4th Edition.. 145 .