OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. a program.Learning Objective Understand the purpose of the operating system Distinguish between a resource. 4 . by Parul Arora. New Delhi-63.

Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. by Parul Arora. 5 ..

. 6 . • Use the computer hardware in an efficient manner. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. • Operating system goals: Execute user programs and make solving user problems easier.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. New Delhi-63. Make the computer system convenient to use.

video games. database systems. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. I/O devices). New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. U1. 7 . other computers). 4. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. business programs).Computer System Components 1. Hardware – provides basic computing resources (CPU. machines. 3. memory. by Parul Arora.. Users (people.

New Delhi-63.. 8 . U1.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

• Control program – controls the execution of user programs and operations of I/O devices . • Kernel – the one program running at all times (all else being application programs). © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Operating System Definitions • Resource allocator – manages and allocates resources. U1.. New Delhi-63. by Parul Arora. 9 .

U1. 10 . by Parul Arora.. New Delhi-63.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. First rudimentary operating system. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. by Parul Arora.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. 11 .

by Parul Arora.. U1.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 12 .

13 .. New Delhi-63. U1.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

. • Memory management – the system must allocate the memory to several jobs. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.OS Features Needed for Multiprogramming • I/O routine supplied by the system. 14 . U1. New Delhi-63. • Allocation of devices. • CPU scheduling – the system must choose among several jobs ready to run.

by Parul Arora. New Delhi-63. . 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. when the operating system finishes the execution of one command. A job swapped in and out of memory to the disk.. it seeks the next “control statement” from the user’s keyboard.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). On-line communication between the user and the system is provided.

Desktop Systems • Personal computers – computer system dedicated to a single user. display screens. • User convenience and responsiveness. 16 .. small printers. MacOS. mice. U1. New Delhi-63. by Parul Arora. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. UNIX. • I/O devices – keyboards. • May run several different types of operating systems (Windows.

• Tightly coupled system – processors share memory and a clock.. U1.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. by Parul Arora. New Delhi-63. 17 . • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. communication usually takes place through the shared memory.

New Delhi-63. 18 . by Parul Arora. U1. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Many processes can run at once without performance deterioration. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task.Parallel Systems (Cont. master processor schedules and allocated work to slave processors..) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system.

Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 19 . New Delhi-63. U1. by Parul Arora.

such as high-speed buses or telephone lines. 20 . • Loosely coupled system – each processor has its own local memory. New Delhi-63.Distributed Systems • Distribute the computation among several physical processors. by Parul Arora. processors communicate with one another through various communications lines. U1. • Advantages of distributed systems. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

• Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.Distributed Systems (cont) • Requires networking infrastructure. U1. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 21 .

New Delhi-63. by Parul Arora.General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. 22 .

New Delhi-63. • Provides high reliability. 23 . by Parul Arora. • Asymmetric clustering: one server runs the application while other servers standby. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • Symmetric clustering: all N hosts are running the application.Clustered Systems • Clustering allows two or more systems to share storage.

. • Real-Time systems may be either hard or soft real-time. 24 . by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. medical imaging systems. U1.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. • Well-defined fixed-time constraints. New Delhi-63. industrial control systems. and some display systems.

New Delhi-63. virtual reality) requiring advanced operating-system features.) • Hard real-time: Secondary storage limited or absent. U1. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. or read-only memory (ROM) Conflicts with time-sharing systems.Real-Time Systems (Cont.. not supported by general-purpose operating systems. . by Parul Arora. data stored in short term memory. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. 26 .

U1. New Delhi-63. 27 . by Parul Arora..Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 28 . New Delhi-63.. U1. by Parul Arora.

by Parul arora U1.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 29 . New Delhi-63.

strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 30 . New Delhi-63.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . U1. by Parul Arora.how memory is structured Memory management ..

. by Parul Arora. 31 . New Delhi-63. U1.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

.Background • Program must be brought into memory and placed within a process for it to be run. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. New Delhi-63. by Parul Arora. 32 . U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • User programs go through several steps before being run.

Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.g. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Load time: Must generate relocatable code if memory location is not known at compile time. by Parul Arora.. New Delhi-63. Need hardware support for address maps (e. must recompile code if starting location changes. base and limit registers).. 33 . absolute code can be generated. U1.

New Delhi-63. by Parul Arora.. 34 . U1.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Logical address – generated by the CPU. also referred to as virtual address. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Physical address – address seen by the memory unit. logical (virtual) and physical addresses differ in execution-time address-binding scheme. 35 . • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. New Delhi-63. U1..Logical vs. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• The user program deals with logical addresses.Memory-Management Unit • Hardware device that maps virtual to physical address. the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. 36 . • In MMU scheme. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. it never sees the real physical addresses. New Delhi-63..

U1. 37 . New Delhi-63. by Parul Arora..Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Useful when large amounts of code are needed to handle infrequently occurring cases. unused routine is never loaded. • No special support from the operating system is required implemented through program design.. New Delhi-63. by Parul Arora. 38 . U1.

stub. • Small piece of code. 39 . by Parul Arora. • Operating system needed to check if routine is in processes’ memory address.Dynamic Linking • Linking postponed until execution time. used to locate the appropriate memory-resident library routine. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. and executes the routine. U1. • Stub replaces itself with the address of the routine. New Delhi-63.. • Dynamic linking is particularly useful for libraries.

Overlays • Keep in memory only those instructions and data that are needed at any given time. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 40 . • Needed when process is larger than amount of memory allocated to it. by Parul Arora. U1. New Delhi-63.. • Implemented by user. no special support needed from operating system.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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limit register contains range of logical addresses – each logical address must be less than the limit register. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. 44 . • Single-partition allocation Relocation-register scheme used to protect user processes from each other.. Relocation register contains value of smallest physical address. usually held in low memory with interrupt vector. U1. User processes then held in high memory. by Parul Arora. and from changing operating-system code and data. New Delhi-63.

by Parul Arora. New Delhi-63. 45 .Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1.

Contiguous Allocation (Cont. U1. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. it is allocated memory from a hole large enough to accommodate it. 46 .) Multiple-partition allocation Hole – block of available memory.. by Parul Arora. When a process arrives. holes of various size are scattered throughout memory.

must search entire list. by Parul Arora. must also search entire list..Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. Worst-fit: Allocate the largest hole. Produces the largest leftover hole. Produces the smallest leftover hole. New Delhi-63. Best-fit: Allocate the smallest hole that is big enough. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 47 . unless ordered by size.

but it is not contiguous. New Delhi-63. by Parul Arora. and is done at execution time. Compaction is possible only if relocation is dynamic. • Internal Fragmentation – allocated memory may be slightly larger than requested memory.. this size difference is memory internal to a partition.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. U1. but not being used. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. Do I/O only into OS buffers. I/O problem Latch job in memory while it is involved in I/O. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 48 .

• Set up a page table to translate logical to physical addresses. • To run a program of size n pages. by Parul Arora..Paging • Logical address space of a process can be noncontiguous. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. U1. between 512 bytes and 8192 bytes). • Keep track of all free frames. process is allocated physical memory whenever the latter is available. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Internal fragmentation. 49 . • Divide logical memory into blocks of same size called pages. need to find n free frames and load program.

U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. New Delhi-63.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. 50 .. by Parul Arora.

Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. by Parul Arora. 51 .

U1. 52 . by Parul Arora. New Delhi-63.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

53 .Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63. by Parul Arora.

54 . by Parul Arora..Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1.

• Page-table length register (PRLR) indicates size of the page table.Implementation of Page Table • Page table is kept in main memory. • Page-table base register (PTBR) points to the page table. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 55 . • In this scheme every data/instruction access requires two memory accesses.. by Parul Arora. U1. One for the page table and one for the data/instruction. New Delhi-63.

. 56 .Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. by Parul Arora. U1. get frame # out. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A´´) If A´ is in associative register. New Delhi-63.

U1. by Parul Arora..Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 57 . New Delhi-63.

by Parul Arora. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 58 . U1.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers. ration related to number of associative registers.

by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. “invalid” indicates that the page is not in the process’ logical address space. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. 59 . U1. and is thus a legal page.. New Delhi-63.Memory Protection • Memory protection implemented by associating protection bit with each frame.

.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 60 . U1. New Delhi-63.

61 . New Delhi-63. U1. by Parul Arora..Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

62 . U1. • A simple technique is a two-level page table.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Hierarchical Page Tables • Break up the logical address space into multiple page tables. by Parul Arora.

number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a logical address is as follows: pi p2 d 10 10 a 10-bit page number.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a 10-bit page offset. by Parul Arora. Since the page table is paged. U1. New Delhi-63. a page offset consisting of 12 bits.. 63 . the page number is further divided into: Thus.

Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora. 64 . U1.

New Delhi-63. U1. by Parul Arora.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 65 .

Hashed Page Tables • Common in address spaces > 32 bits. 66 . the corresponding physical frame is extracted. • Virtual page numbers are compared in this chain searching for a match. • The virtual page number is hashed into a page table. New Delhi-63. This page table contains a chain of elements hashing to the same location.. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. If a match is found. U1.

. 67 . New Delhi-63. by Parul Arora.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

. U1. 68 . New Delhi-63. • Entry consists of the virtual address of the page stored in that real memory location. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. but increases time needed to search the table when a page reference occurs. • Use hash table to limit the search to one — or at most a few — page-table entries.Inverted Page Table • One entry for each real page of memory. • Decreases memory needed to store each page table. with information about the process that owns that page.

New Delhi-63. by Parul Arora. U1. 69 .Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Private code and data Each process keeps a separate copy of the code and data. The pages for the private code and data can appear anywhere in the logical address space.. text editors. U1.. by Parul Arora. 70 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. window systems).e. New Delhi-63. Shared code must appear in same location in the logical address space of all processes.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. compilers.

New Delhi-63. by Parul Arora. 71 . U1..Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

function. local variables. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Memory-management scheme that supports user view of memory. stack. procedure. object. 72 . common block. New Delhi-63. method. by Parul Arora. global variables.. A program is a collection of segments. U1. A segment is a logical unit such as: main program. symbol table.

U1. 73 . by Parul Arora.User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

U1. by Parul Arora. 74 .Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

75 .. • • • Segment-table base register (STBR) points to the segment table’s location in memory. Segment table – maps two-dimensional physical addresses. by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. each table entry has: base – contains the starting physical address where the segments reside in memory.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. limit – specifies the length of the segment. offset>. New Delhi-63.

. 76 .) • Relocation. dynamic by segment table • Sharing.Segmentation Architecture (Cont. New Delhi-63. by Parul Arora. shared segments same segment number • Allocation. U1. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Since segments vary in length..) • Protection. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. New Delhi-63. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. memory allocation is a dynamic storage-allocation problem. code sharing occurs at segment level. U1. 77 .Segmentation Architecture (Cont. by Parul Arora.

. New Delhi-63.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 78 . by Parul Arora. U1.

. New Delhi-63.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 79 . U1. by Parul Arora.

. by Parul Arora. New Delhi-63. U1. 80 .Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. but rather the base address of a page table for this segment.. U1. New Delhi-63. 81 . • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment.

MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63. 82 . U1.

. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. U1. 83 .Segmentation with Paging – Intel 386 As shown in the following diagram. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.

U1.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 84 . New Delhi-63. by Parul Arora.

by Parul arora U1. New Delhi-63. 85 .Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Describe the reason for and use of cache memory. by Parul Arora. • Discuss the concept of thrashing. U1.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software.. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. cache memory. 86 . New Delhi-63. • Evaluate the trade-offs in terms of memory size (main memory. auxiliary memory) and processor speed. • Summarize the principles of virtual memory as applied to caching and paging.

New Delhi-63.. . by Parul Arora. Only part of the program needs to be in memory for execution. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. Allows for more efficient process creation. Logical address space can therefore be much larger than physical address space. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Allows address spaces to be shared by several processes.Background • Virtual memory – separation of user logical memory from physical memory.

88 . U1.. by Parul Arora. New Delhi-63.Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

89 .Demand Paging Bring a page into memory only when it is needed. by Parul Arora. U1. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

U1. New Delhi-63.. 90 . by Parul Arora.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

91 .. New Delhi-63. U1. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. but valid-invalid bit 1 Example of a page table snapshot. by Parul Arora.

. 92 . U1. New Delhi-63.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

validation bit = 1. Reset tables. Restart instruction: Least Recently Used block move U1. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort.. . Swap page into frame. Just not in memory. by Parul Arora.Page Fault • If there is ever a reference to a page. • • • • Get empty frame.

94 . by Parul Arora.. U1. New Delhi-63.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

swap it out. New Delhi-63.What happens if there is no free frame? • Page replacement – find some page in memory. but not really in use.. U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Same page may be brought into memory several times. 95 . algorithm performance – want an algorithm which will result in minimum number of page faults.

0 if p = 0 no page faults if p = 1. U1. 96 . by Parul Arora..Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. New Delhi-63. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

97 . by Parul Arora. Swap Page Time = 10 msec = 10. U1. New Delhi-63..Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

. by Parul Arora. 98 . New Delhi-63.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

If either process modifies a shared page. only then is the page copied. New Delhi-63.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. 99 . by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • COW allows more efficient process creation as only modified pages are copied.. • Free pages are allocated from a pool of zeroed-out pages.

U1. by Parul Arora. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Simplifies file access by treating file I/O through memory rather than read() write() system calls.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. New Delhi-63.. . A page-sized portion of the file is read from the file system into a physical page. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. • Also allows several processes to map the same file allowing the pages in memory to be shared. • A file is initially read using demand paging.

Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. 101 . by Parul Arora. New Delhi-63.

New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 102 . • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. by Parul Arora..

103 . by Parul Arora. U1.. New Delhi-63.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Find a free frame: . use it. by Parul Arora. • Restart the process. U1. New Delhi-63.. Update the page and frame tables.If there is no free frame. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. use a page replacement algorithm to select a victim frame. • Read the desired page into the (newly) free frame. 104 .Basic Page Replacement • Find the location of the desired page on disk. .If there is a free frame.

U1.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 105 . New Delhi-63. by Parul Arora..

In all our examples. 3. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. 1. 5.. 2. 4. the reference string is 1.Page Replacement Algorithms Want lowest page-fault rate. 2. New Delhi-63. 106 . 3. 4. 5. 1. 2. by Parul Arora. U1.

New Delhi-63. U1.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 107 . by Parul Arora..

3. 2. U1. 108 . 2. 1. 2.First-In-First-Out (FIFO) Algorithm Reference string: 1. 4. 1. by Parul Arora. New Delhi-63.. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 3. 5. 4.

109 . New Delhi-63. by Parul Arora.First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

New Delhi-63.Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1.. 113 .

3. look at the counters to determine which are to change. 4. 4.. U1. New Delhi-63. 5. 1. 3. copy the clock into the counter. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2.Least Recently Used (LRU) Algorithm Reference string: 1. by Parul Arora. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. every time page is referenced through this entry. 114 . 1. 2. When a page needs to be changed. 2.

New Delhi-63.LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1. 115 .

LRU Algorithm (Cont.. by Parul Arora. U1. New Delhi-63.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 116 .

U1. 117 . New Delhi-63.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.

subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. however. then: set reference bit 0. initially = 0 When page is referenced bit set to 1. leave page in memory. New Delhi-63. Replace the one which is 0 (if one exists). Second chance Need reference bit. We do not know the order. 118 . U1.LRU Approximation Algorithm Reference bit With each page associate a bit. by Parul Arora.. replace next page (in clock order). Clock replacement. If page to be replaced (in clock order) has reference bit = 1. rules.

New Delhi-63..Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 119 . U1. by Parul Arora.

New Delhi-63. by Parul Arora. U1. 120 . • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used.. LFU Algorithm: replaces page with smallest count.Counting Algorithms • Keep a counter of the number of references that have been made to each page.

New Delhi-63. 2 pages to handle to. 121 .Allocation of Frames • Each process needs minimum number of pages. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. might span 2 pages. 2 pages to handle from. by Parul Arora. • Two major allocation schemes. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. U1.

Fixed Allocation • Equal allocation – e.. U1. 122 . give each 20 pages. • Proportional allocation – Allocate according to the size of process..g. si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. if 100 frames and 5 processes. New Delhi-63. by Parul Arora.

select for replacement one of its frames. 123 . select for replacement a frame from a process with lower priority number. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • If process Pi generates a page fault. New Delhi-63. by Parul Arora.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. U1.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Local replacement – each process selects from only its own set of allocated frames.Global vs. U1. by Parul Arora. 124 . New Delhi-63. one process can take a frame from another. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames..

This leads to: low CPU utilization. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Thrashing If a process does not have “enough” pages. by Parul Arora.. the page-fault rate is very high. another process added to the system. U1. Thrashing ≡ a process is busy swapping pages in and out. operating system thinks that it needs to increase the degree of multiprogramming. 125 . New Delhi-63.

U1.. New Delhi-63. Localities may overlap.Thrashing Why does paging work? Locality model Process migrates from one locality to another. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 126 .

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

130 .Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. process loses frame. by Parul Arora. U1. If actual rate too high. If actual rate too low. process gains frame..

New Delhi-63. 131 . U1..Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1. New Delhi-63. 132 ..Other Considerations (Cont. TLB Reach = (TLB Size) X (Page Size) Ideally. Otherwise there is a high degree of page faults. by Parul Arora.) TLB Reach . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the working set of each process is stored in the TLB.The amount of memory accessible from the TLB.

• Provide Multiple Page Sizes.Increasing the Size of the TLB • Increase the Page Size. 133 . This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation.. U1. by Parul Arora. This may lead to an increase in fragmentation as not all applications require a large page size. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

i++) A[i. by Parul Arora. U1.j] = 0. j++) for (i = 0.length. j < A. Each row is stored in one page Program 1 for (j = 0.length. New Delhi-63. j < A. i < A. 1024 x 1024 page faults Program 2 for (i = 0. i < A.length. j++) A[i.Other Considerations (Cont.) Program structure int A[][] = new int[1024][1024]. 134 . 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. i++) for (j = 0.j] = 0.length.

and also allows degree of multiprogramming to be raised. New Delhi-63. by Parul Arora.. Memory management algorithms differ in many concepts. Virtual memory allows extremely large processes to be run. Virtual memory frees application programers from worrying about memory availability U1. . 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Multiprogramming increased the performance of computer system.

Resources are any objects that can be allocated within a system. Least Recently Used. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. .Summary • In the introduction. and the operating system is responsible for managing them.. personal computing and dedicated. 136 Used. timesharing. by Parul Arora. Second Chance. and Least Frequently U1. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. Operating systems are a type of system software that allow applications to interface with computer hardware. Four major categories of operating systems are batch. New Delhi-63. First In First Out. Policies for determining which pages to load and remove from memory include Random Replacement. we saw that software can be roughly divided into two groups: application software and system software.

Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. The Hardware mechanism that enables a device to notify the CPU is called __________.Review Questions (OBJ) 1. 137 . a) Polling b) Interrupt c) System Call d) None of the above 2. New Delhi-63. U1..

. 138 . Virtual memory is __________. by Parul Arora.Review Questions (OBJ) 3. New Delhi-63. 4. U1. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. New Delhi-63. U1. 139 .Review Questions (OBJ) 5. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. The term " Operating System " means ________. by Parul Arora.

New Delhi-63.. by Parul Arora. 140 . The principle of locality of reference justifies the use of ________. All routines are kept on disk in a relocatable load format. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8.Review Questions (OBJ) 7. U1. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ) Routine a) b) c) d) is not loaded until it is called. The main program is loaded into memory & is executed.

Review Questions (OBJ) 9. by Parul Arora. the total number of page faults caused by the process will be __________. If all page frames are initially empty. a) 10 b) 7 c) 8 d) 9 10. New Delhi-63. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO.. 141 . a) Program structure b) Program size c) Primary storage size d) None of the above U1. ) The problem of thrashing is effected scientifically by ________. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

List the four steps that are necessary to run a program on a completely dedicated machine 5. How does a real-time system differ from time-share? 8. U1. Explain the difference between internal and external fragmentation 10. How do MULTICS and UNIX differ? 7. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (Short) 1. How do I/O-bound and CPU-bound programs differ? 6. 142 . Explain the difference between logical and physical addresses. 9. What are the three main purposes of an operating system? 4. What are the main differences between operating systems for mainframe computers and personal computers? 3. What is the main advantage of multiprogramming 2. by Parul Arora. New Delhi-63..

Review Questions (Short) 11. New Delhi-63. When do page faults occur? 15. How was memory mapping used in extending the usefulness of minicomputers? 13. by Parul Arora. U1. 143 . What are overlays? 12. Why is there a valid/invalid bit? Where is it kept? 18. What is Belady’s anomaly? 19. What is meant by locality? 21. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How do global and local allocation differ? 20. What is reentrant code? 14. Describe the actions taken by the operating system when a page fault occurs.. 16. What is virtual memory? 17.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 7. 4. 8. 3. List ways to implement LRU. 4. 8. 5. 5. how would each of the First-?t.. 4. if the entry is there.)If a memory reference takes 200 nanoseconds. 1. 7. 500K. 300K. 9. 4. and 75 percent of all pagetable references are found in the associative registers. 2. how long does a paged memory reference take? b. How many page faults occur for your algorithm for the following reference string.) 3. Consider a paging system with the page table stored in memory.Review Questions (Long) 1. 4. 9. Given memory partitions of 100K. 3. 5. by Parul Arora. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. to determine which page is victim. 417K.)If we add associative registers. 7. New Delhi-63. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. a. for four page frames? 1. 2. 8. Best-?t. 200K. and Worst-?t algorithms place processes of 212K. 6. U1. 144 . 112K. and 600K (in order).

New Delhi-63. by Parul Arora. 2001 • "Operating Systems” Tannenbaum PHI. “Operating System Concepts” Peason. Donovan J..2001 • Madnick E. ”Operating System”: TMH.Recommended reading • Silbersachatz and Galvin..6th Ed.. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 4th Edition. U1.. 145 .