OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

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New Delhi-63. by Parul Arora. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Learning Objective Understand the purpose of the operating system Distinguish between a resource.. a program. U1. 4 .

Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.. 5 . New Delhi-63.

6 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. • Use the computer hardware in an efficient manner. U1. Make the computer system convenient to use.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. • Operating system goals: Execute user programs and make solving user problems easier. by Parul Arora. New Delhi-63.

memory. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. New Delhi-63. database systems.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Computer System Components 1. Users (people. by Parul Arora. video games. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. Hardware – provides basic computing resources (CPU. 4. I/O devices). other computers). business programs). 7 . machines. 2. 3.

Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. 8 . U1. New Delhi-63.

. New Delhi-63. • Kernel – the one program running at all times (all else being application programs). © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Control program – controls the execution of user programs and operations of I/O devices . 9 . by Parul Arora. U1.Operating System Definitions • Resource allocator – manages and allocates resources.

U1. New Delhi-63.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. 10 .

. • Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. First rudimentary operating system. 11 .Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another. by Parul Arora.

12 . by Parul Arora.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1.

Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 13 . by Parul Arora. U1.. New Delhi-63.

New Delhi-63.. 14 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Memory management – the system must allocate the memory to several jobs. • CPU scheduling – the system must choose among several jobs ready to run. • Allocation of devices. by Parul Arora. U1.OS Features Needed for Multiprogramming • I/O routine supplied by the system.

. . On-line communication between the user and the system is provided. by Parul Arora.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). A job swapped in and out of memory to the disk. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. when the operating system finishes the execution of one command. New Delhi-63. U1. it seeks the next “control statement” from the user’s keyboard.

UNIX. display screens. • May run several different types of operating systems (Windows.. • User convenience and responsiveness. small printers. • I/O devices – keyboards. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. MacOS. mice.Desktop Systems • Personal computers – computer system dedicated to a single user. by Parul Arora. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features. New Delhi-63. 16 .

• Tightly coupled system – processors share memory and a clock. New Delhi-63.Parallel Systems • Multiprocessor systems with more than on CPU in close communication. by Parul Arora. U1. communication usually takes place through the shared memory. • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 17 .

) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system. U1.Parallel Systems (Cont. master processor schedules and allocated work to slave processors. New Delhi-63. 18 .. by Parul Arora. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. Many processes can run at once without performance deterioration. More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 19 . by Parul Arora.. New Delhi-63. U1.

U1.Distributed Systems • Distribute the computation among several physical processors. 20 . processors communicate with one another through various communications lines. by Parul Arora.. Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. • Advantages of distributed systems. • Loosely coupled system – each processor has its own local memory. such as high-speed buses or telephone lines.

New Delhi-63. U1. 21 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems.. by Parul Arora.Distributed Systems (cont) • Requires networking infrastructure.

by Parul Arora. New Delhi-63. 22 .. U1.General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63.Clustered Systems • Clustering allows two or more systems to share storage. • Symmetric clustering: all N hosts are running the application.. • Provides high reliability. by Parul Arora. • Asymmetric clustering: one server runs the application while other servers standby. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 23 . U1.

by Parul Arora. • Well-defined fixed-time constraints. and some display systems. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. medical imaging systems. New Delhi-63. • Real-Time systems may be either hard or soft real-time. industrial control systems. U1.Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. 24 .

. New Delhi-63. not supported by general-purpose operating systems.) • Hard real-time: Secondary storage limited or absent.Real-Time Systems (Cont.. data stored in short term memory. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. virtual reality) requiring advanced operating-system features. by Parul Arora. or read-only memory (ROM) Conflicts with time-sharing systems. U1.

26 .Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63.

U1. 27 .Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63..

. U1.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 28 . by Parul Arora. New Delhi-63.

Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63. 29 . by Parul arora U1.

by Parul Arora.how memory is structured Memory management .strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 30 . New Delhi-63.. U1.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization .

by Parul Arora.. U1. New Delhi-63. 31 .Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. 32 . • User programs go through several steps before being run. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1..Background • Program must be brought into memory and placed within a process for it to be run. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program.

. New Delhi-63. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. 33 . absolute code can be generated. Need hardware support for address maps (e. by Parul Arora. must recompile code if starting location changes.. U1. • Load time: Must generate relocatable code if memory location is not known at compile time. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.g. base and limit registers).Binding of Instructions and Data to Memory • Compile time: If memory location known a priori.

. by Parul Arora.Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 34 .

Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.. Physical address – address seen by the memory unit. Logical address – generated by the CPU. 35 . • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. New Delhi-63.Logical vs. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. also referred to as virtual address. U1. logical (virtual) and physical addresses differ in execution-time address-binding scheme.

it never sees the real physical addresses. U1.. by Parul Arora. • In MMU scheme. • The user program deals with logical addresses. 36 . the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. New Delhi-63.Memory-Management Unit • Hardware device that maps virtual to physical address. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. U1. by Parul Arora. 37 .

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. • No special support from the operating system is required implemented through program design. New Delhi-63.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. 38 . unused routine is never loaded. • Useful when large amounts of code are needed to handle infrequently occurring cases.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Stub replaces itself with the address of the routine. • Operating system needed to check if routine is in processes’ memory address. 39 . • Small piece of code. and executes the routine. used to locate the appropriate memory-resident library routine. • Dynamic linking is particularly useful for libraries. New Delhi-63.Dynamic Linking • Linking postponed until execution time. by Parul Arora.. stub.

• Needed when process is larger than amount of memory allocated to it. U1. no special support needed from operating system. New Delhi-63. • Implemented by user. 40 .. by Parul Arora. programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Overlays • Keep in memory only those instructions and data that are needed at any given time.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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U1. usually held in low memory with interrupt vector. and from changing operating-system code and data. Relocation register contains value of smallest physical address.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. limit register contains range of logical addresses – each logical address must be less than the limit register. 44 . by Parul Arora.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. New Delhi-63. • Single-partition allocation Relocation-register scheme used to protect user processes from each other. User processes then held in high memory.

45 . by Parul Arora.. U1. New Delhi-63.Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

it is allocated memory from a hole large enough to accommodate it. U1. New Delhi-63. holes of various size are scattered throughout memory. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 46 .Contiguous Allocation (Cont. by Parul Arora.) Multiple-partition allocation Hole – block of available memory. When a process arrives.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. Produces the largest leftover hole. New Delhi-63. 47 . must search entire list. by Parul Arora. Best-fit: Allocate the smallest hole that is big enough.. must also search entire list.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. U1. Worst-fit: Allocate the largest hole. unless ordered by size. Produces the smallest leftover hole.

. this size difference is memory internal to a partition. but it is not contiguous. I/O problem Latch job in memory while it is involved in I/O. but not being used. and is done at execution time. Compaction is possible only if relocation is dynamic. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. New Delhi-63. U1. 48 . Do I/O only into OS buffers. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. by Parul Arora.

49 . process is allocated physical memory whenever the latter is available. between 512 bytes and 8192 bytes). • Divide logical memory into blocks of same size called pages. • To run a program of size n pages. • Keep track of all free frames. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • Divide physical memory into fixed-sized blocks called frames (size is power of 2. need to find n free frames and load program. • Set up a page table to translate logical to physical addresses.Paging • Logical address space of a process can be noncontiguous.. New Delhi-63. • Internal fragmentation.

50 .. U1. New Delhi-63. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

by Parul Arora. New Delhi-63. 51 . U1..Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. New Delhi-63.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 52 ..

. New Delhi-63. 53 . U1.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

. New Delhi-63. U1. 54 .Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

• In this scheme every data/instruction access requires two memory accesses. U1.Implementation of Page Table • Page table is kept in main memory.. New Delhi-63. 55 . • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page-table base register (PTBR) points to the page table. • Page-table length register (PRLR) indicates size of the page table. One for the page table and one for the data/instruction. by Parul Arora.

Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´. by Parul Arora. New Delhi-63. U1. Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A´´) If A´ is in associative register.. 56 . get frame # out.

Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 57 .. New Delhi-63.

Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. 58 .. ration related to number of associative registers. by Parul Arora.Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.

New Delhi-63. U1. “invalid” indicates that the page is not in the process’ logical address space. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 59 .. by Parul Arora.Memory Protection • Memory protection implemented by associating protection bit with each frame. and is thus a legal page.

by Parul Arora. New Delhi-63..Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 60 . U1.

New Delhi-63.. U1.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 61 .

• A simple technique is a two-level page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 62 .. U1.Hierarchical Page Tables • Break up the logical address space into multiple page tables. by Parul Arora.

. New Delhi-63.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. a page offset consisting of 12 bits. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Since the page table is paged. the page number is further divided into: Thus. by Parul Arora. 63 . U1. a 10-bit page offset.

Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. by Parul Arora.. 64 .

65 . by Parul Arora.Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1..

by Parul Arora. If a match is found. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the corresponding physical frame is extracted.Hashed Page Tables • Common in address spaces > 32 bits. U1. This page table contains a chain of elements hashing to the same location. 66 . New Delhi-63. • The virtual page number is hashed into a page table. • Virtual page numbers are compared in this chain searching for a match..

67 . U1. by Parul Arora.. New Delhi-63.Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

68 . but increases time needed to search the table when a page reference occurs. by Parul Arora. • Use hash table to limit the search to one — or at most a few — page-table entries..Inverted Page Table • One entry for each real page of memory. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Entry consists of the virtual address of the page stored in that real memory location. • Decreases memory needed to store each page table. with information about the process that owns that page. New Delhi-63.

. 69 . U1. New Delhi-63.Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1. Private code and data Each process keeps a separate copy of the code and data.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. compilers. Shared code must appear in same location in the logical address space of all processes. by Parul Arora.. New Delhi-63. text editors.. window systems). 70 .e. The pages for the private code and data can appear anywhere in the logical address space. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63.. 71 . U1.

arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A segment is a logical unit such as: main program. method. procedure.Segmentation Memory-management scheme that supports user view of memory. global variables. by Parul Arora. stack.. object. U1. A program is a collection of segments. 72 . function. symbol table. New Delhi-63. common block. local variables.

User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.. 73 . New Delhi-63.

U1.Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 74 . New Delhi-63. by Parul Arora.

New Delhi-63. Segment table – maps two-dimensional physical addresses. 75 .. offset>. each table entry has: base – contains the starting physical address where the segments reside in memory. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. • • • Segment-table base register (STBR) points to the segment table’s location in memory. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. limit – specifies the length of the segment.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number.

76 . shared segments same segment number • Allocation.. by Parul Arora.Segmentation Architecture (Cont. U1.) • Relocation. New Delhi-63. dynamic by segment table • Sharing. first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

code sharing occurs at segment level. memory allocation is a dynamic storage-allocation problem. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments. New Delhi-63. U1.Segmentation Architecture (Cont..) • Protection. • Since segments vary in length. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 77 . by Parul Arora.

U1. New Delhi-63.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 78 . by Parul Arora.

by Parul Arora. 79 . U1.Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

80 . New Delhi-63.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. U1.

81 . by Parul Arora. New Delhi-63.. but rather the base address of a page table for this segment. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment.Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63. 82 . by Parul Arora. U1.MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

. U1.Segmentation with Paging – Intel 386 As shown in the following diagram. by Parul Arora. New Delhi-63. 83 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.

by Parul Arora. U1.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 84 .. New Delhi-63.

New Delhi-63.Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . 85 . by Parul arora U1.

86 . • Summarize the principles of virtual memory as applied to caching and paging.. • Describe the reason for and use of cache memory. • Discuss the concept of thrashing. New Delhi-63. by Parul Arora. cache memory. • Evaluate the trade-offs in terms of memory size (main memory. auxiliary memory) and processor speed.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. U1.

. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Logical address space can therefore be much larger than physical address space. • Virtual memory can be implemented via: Demand paging Demand segmentation U1. Only part of the program needs to be in memory for execution. New Delhi-63. Allows for more efficient process creation. by Parul Arora. . Allows address spaces to be shared by several processes.Background • Virtual memory – separation of user logical memory from physical memory.

Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. New Delhi-63. 88 . U1.

. 89 . New Delhi-63. by Parul Arora. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Demand Paging Bring a page into memory only when it is needed. U1.

U1.. by Parul Arora.Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 90 .

U1. by Parul Arora.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. 0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries. 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 91 . but valid-invalid bit 1 Example of a page table snapshot..

New Delhi-63.. by Parul Arora. U1. 92 .Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Restart instruction: Least Recently Used block move U1. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • • • • Get empty frame. validation bit = 1. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort.Page Fault • If there is ever a reference to a page. by Parul Arora. . New Delhi-63. Just not in memory.. Swap page into frame. Reset tables.

U1. New Delhi-63. by Parul Arora.Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 94 .

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. algorithm performance – want an algorithm which will result in minimum number of page faults. New Delhi-63. • Same page may be brought into memory several times..What happens if there is no free frame? • Page replacement – find some page in memory. swap it out. 95 . but not really in use. U1. by Parul Arora.

by Parul Arora.0 if p = 0 no page faults if p = 1. New Delhi-63.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1. 96 .. every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

Swap Page Time = 10 msec = 10. 97 .Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out. by Parul Arora..000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.

. New Delhi-63. 98 . by Parul Arora. U1.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

• Free pages are allocated from a pool of zeroed-out pages. only then is the page copied.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.If either process modifies a shared page. New Delhi-63. by Parul Arora.. 99 . • COW allows more efficient process creation as only modified pages are copied.

• Simplifies file access by treating file I/O through memory rather than read() write() system calls.. New Delhi-63. • A file is initially read using demand paging. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Also allows several processes to map the same file allowing the pages in memory to be shared.Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. A page-sized portion of the file is read from the file system into a physical page. . Subsequent reads/writes to/from the file are treated as ordinary memory accesses. by Parul Arora. U1.

U1.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 101 . by Parul Arora.

• Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement.. New Delhi-63. U1. by Parul Arora. 102 .

by Parul Arora.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63.. 103 .

use it. . New Delhi-63.Basic Page Replacement • Find the location of the desired page on disk. use a page replacement algorithm to select a victim frame. • Find a free frame: . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. • Restart the process. Update the page and frame tables. 104 .If there is no free frame. • Read the desired page into the (newly) free frame..If there is a free frame.

. U1. by Parul Arora.Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 105 .

In all our examples. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 2. 1. 106 . by Parul Arora. 3. 5. 5. U1. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. 4..Page Replacement Algorithms Want lowest page-fault rate. the reference string is 1. 2. 3. 4. New Delhi-63. 1. 2.

New Delhi-63. by Parul Arora. U1.. 107 .Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.First-In-First-Out (FIFO) Algorithm Reference string: 1. 3. 108 .. 1. 3. 2. 4. U1. by Parul Arora. 1. 2. 2. 5. 4.

U1. New Delhi-63. by Parul Arora..First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 109 .

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

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Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

New Delhi-63.. 113 . by Parul Arora.Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

1. 2.Least Recently Used (LRU) Algorithm Reference string: 1. copy the clock into the counter. 3. 4. 2. 3. by Parul Arora. every time page is referenced through this entry. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. When a page needs to be changed.. look at the counters to determine which are to change. 1. U1. 4. 114 . New Delhi-63. 2. 5. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

115 ..LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. New Delhi-63. U1.

116 .) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. New Delhi-63..LRU Algorithm (Cont.

by Parul Arora. 117 . U1.Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

We do not know the order. then: set reference bit 0. replace next page (in clock order). Second chance Need reference bit. Replace the one which is 0 (if one exists).. U1. New Delhi-63. 118 . Clock replacement. initially = 0 When page is referenced bit set to 1. leave page in memory.LRU Approximation Algorithm Reference bit With each page associate a bit. If page to be replaced (in clock order) has reference bit = 1. however. rules. by Parul Arora. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora.. U1. New Delhi-63.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 119 .

LFU Algorithm: replaces page with smallest count. 120 .. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used.Counting Algorithms • Keep a counter of the number of references that have been made to each page. U1. by Parul Arora. New Delhi-63.

might span 2 pages. 2 pages to handle from. 2 pages to handle to. 121 . fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. • Two major allocation schemes.Allocation of Frames • Each process needs minimum number of pages. U1. New Delhi-63.

si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 122 . give each 20 pages.Fixed Allocation • Equal allocation – e. U1.. • Proportional allocation – Allocate according to the size of process. New Delhi-63. if 100 frames and 5 processes.. by Parul Arora.g.

by Parul Arora.. • If process Pi generates a page fault. New Delhi-63.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. 123 . select for replacement a frame from a process with lower priority number. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. select for replacement one of its frames.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. one process can take a frame from another. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.Global vs.. 124 . • Local replacement – each process selects from only its own set of allocated frames. by Parul Arora.

the page-fault rate is very high. another process added to the system. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 125 . operating system thinks that it needs to increase the degree of multiprogramming. New Delhi-63. U1.Thrashing If a process does not have “enough” pages. by Parul Arora. Thrashing ≡ a process is busy swapping pages in and out. This leads to: low CPU utilization..

. U1. Localities may overlap. 126 . by Parul Arora. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.Thrashing Why does paging work? Locality model Process migrates from one locality to another.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. If actual rate too high.. If actual rate too low. New Delhi-63. by Parul Arora. process gains frame. 130 . process loses frame.

by Parul Arora. 131 . New Delhi-63. U1..Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

U1.The amount of memory accessible from the TLB.) TLB Reach . 132 . the working set of each process is stored in the TLB. Otherwise there is a high degree of page faults.Other Considerations (Cont. TLB Reach = (TLB Size) X (Page Size) Ideally. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation. This may lead to an increase in fragmentation as not all applications require a large page size. by Parul Arora.. 133 . New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Increasing the Size of the TLB • Increase the Page Size. U1. • Provide Multiple Page Sizes.

j++) A[i. i++) A[i.length.j] = 0. j < A.. i < A.) Program structure int A[][] = new int[1024][1024]. i++) for (j = 0.length. U1. 1024 x 1024 page faults Program 2 for (i = 0.j] = 0. by Parul Arora. Each row is stored in one page Program 1 for (j = 0.length.length. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 134 .Other Considerations (Cont. New Delhi-63. j++) for (i = 0. i < A. j < A.

135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. . by Parul Arora. Multiprogramming increased the performance of computer system. Memory management algorithms differ in many concepts.Conclusion • • • • • Operating systems provide an environment for development and execution of programs. New Delhi-63.. Virtual memory allows extremely large processes to be run.and also allows degree of multiprogramming to be raised. Virtual memory frees application programers from worrying about memory availability U1.

and the operating system is responsible for managing them. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. ..Summary • In the introduction. New Delhi-63. Resources are any objects that can be allocated within a system. and Least Frequently U1. Policies for determining which pages to load and remove from memory include Random Replacement. Least Recently Used. timesharing. Second Chance. by Parul Arora. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. we saw that software can be roughly divided into two groups: application software and system software. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. Four major categories of operating systems are batch. personal computing and dedicated. 136 Used. Operating systems are a type of system software that allow applications to interface with computer hardware. First In First Out.

by Parul Arora. The Hardware mechanism that enables a device to notify the CPU is called __________. U1. 137 . a) Polling b) Interrupt c) System Call d) None of the above 2.Review Questions (OBJ) 1. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63.

by Parul Arora. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Review Questions (OBJ) 3. 4.. 138 . Virtual memory is __________. New Delhi-63. U1. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers.

Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6. New Delhi-63.Review Questions (OBJ) 5. by Parul Arora. 139 .. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. The term " Operating System " means ________. U1.

140 . This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. U1. All routines are kept on disk in a relocatable load format. a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management..Review Questions (OBJ) 7. by Parul Arora. New Delhi-63. The main program is loaded into memory & is executed. The principle of locality of reference justifies the use of ________. ) Routine a) b) c) d) is not loaded until it is called.

New Delhi-63.. the total number of page faults caused by the process will be __________. 141 . ) The problem of thrashing is effected scientifically by ________. a) 10 b) 7 c) 8 d) 9 10. If all page frames are initially empty.Review Questions (OBJ) 9. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. a) Program structure b) Program size c) Primary storage size d) None of the above U1.

. Explain the difference between internal and external fragmentation 10. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Explain the difference between logical and physical addresses. U1. List the four steps that are necessary to run a program on a completely dedicated machine 5. How do I/O-bound and CPU-bound programs differ? 6.Review Questions (Short) 1. What are the main differences between operating systems for mainframe computers and personal computers? 3. New Delhi-63. by Parul Arora. 9. What are the three main purposes of an operating system? 4. How do MULTICS and UNIX differ? 7. 142 . What is the main advantage of multiprogramming 2. How does a real-time system differ from time-share? 8.

What is meant by locality? 21. 143 . How do global and local allocation differ? 20. Describe the actions taken by the operating system when a page fault occurs. When do page faults occur? 15. 16. Why is there a valid/invalid bit? Where is it kept? 18. New Delhi-63. What is reentrant code? 14. How was memory mapping used in extending the usefulness of minicomputers? 13.. by Parul Arora. What is virtual memory? 17. What is Belady’s anomaly? 19. What are overlays? 12. Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Review Questions (Short) 11.

5. for four page frames? 1.)If a memory reference takes 200 nanoseconds. 4. 2. and 75 percent of all pagetable references are found in the associative registers. and Worst-?t algorithms place processes of 212K. by Parul Arora. how would each of the First-?t. 9. 4. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. how long does a paged memory reference take? b.)If we add associative registers. 7. 7. 4. 417K. Given memory partitions of 100K. a. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. 8. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. 9. 8. if the entry is there. 3. 300K. and 600K (in order). 3. List ways to implement LRU. 144 . 2.Review Questions (Long) 1. 5. Consider a paging system with the page table stored in memory. 1. Best-?t. U1.) 3. 112K.. to determine which page is victim. New Delhi-63. 8. 500K. 200K. 7. How many page faults occur for your algorithm for the following reference string. 4. 4. 6. 5.

U1.6th Ed. New Delhi-63. 4th Edition.2001 • Madnick E. Donovan J. “Operating System Concepts” Peason. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. ”Operating System”: TMH. 2001 • "Operating Systems” Tannenbaum PHI.... 145 .Recommended reading • Silbersachatz and Galvin..