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Sections

  • Introduction
  • What is an Operating System?
  • Computer System Components
  • Operating System Definitions
  • Operating System View
  • Mainframe Systems
  • Desktop Systems
  • Parallel Systems
  • Parallel Systems (Cont.)
  • Distributed Systems
  • Distributed Systems (cont)
  • Clustered Systems
  • Real-Time Systems
  • Real-Time Systems (Cont.)
  • Handheld Systems
  • Computing Environments
  • Learning Objective
  • Memory Management
  • Background
  • Dynamic Loading
  • Dynamic Linking
  • Overlays
  • Swapping
  • Schematic View of Swapping
  • Contiguous Allocation
  • Contiguous Allocation (Cont.)
  • Fragmentation
  • Paging
  • Address Translation Scheme
  • Free Frames
  • Implementation of Page Table
  • Associative Memory
  • Paging Hardware With TLB
  • Effective Access Time
  • Memory Protection
  • Page Table Structure
  • Hierarchical Page Tables
  • Two-Level Paging Example
  • Two-Level Page-Table Scheme
  • Address-Translation Scheme
  • Hashed Page Tables
  • Hashed Page Table
  • Inverted Page Table
  • Shared Pages
  • Shared Pages Example
  • Segmentation
  • User’s View of a Program
  • Logical View of Segmentation
  • Segmentation Architecture
  • Segmentation Hardware
  • Example of Segmentation
  • Sharing of Segments
  • Learning Objectives
  • Demand Paging
  • Valid-Invalid Bit
  • Page Fault
  • Steps in Handling a Page Fault
  • Performance of Demand Paging
  • Demand Paging Example
  • Process Creation
  • Copy-on-Write
  • Memory-Mapped Files
  • Memory Mapped Files
  • Page Replacement
  • Need For Page Replacement
  • Basic Page Replacement
  • Page Replacement Algorithms
  • FIFO Page Replacement
  • Optimal Algorithm
  • Optimal Page Replacement
  • LRU Page Replacement
  • LRU Algorithm (Cont.)
  • LRU Approximation Algorithm
  • Counting Algorithms
  • Allocation of Frames
  • Fixed Allocation
  • Priority Allocation
  • Global vs. Local Allocation
  • Working-Set Model
  • Working-set model
  • Page-Fault Frequency Scheme
  • Other Considerations
  • Increasing the Size of the TLB
  • Conclusion
  • Summary

OPERATING SYSTEMS UNIT 1

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 1

Learning Objective
Explain the objectives and functions of modern operating systems. Describe how operating systems have evolved over time from primitive batch systems to sophisticated multiuser systems. Analyze the tradeoffs inherent in operating system design. Describe the functions of a contemporary operating system with respect to convenience, efficiency, and the ability to evolve. Discuss networked, client-server, distributed operating systems and how they differ from single user operating systems.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 2

Introduction

© Bharati Vidyapeeth’s Institute of Computer Applications and Management , New Delhi-63, by Parul arora

U1. 3

4 . a program..Learning Objective Understand the purpose of the operating system Distinguish between a resource. by Parul Arora. New Delhi-63. and a process Recognize critical resources and explain the behavior of semaphores Describe various memory page replacement algorithms Describe how files are stored in secondary storage © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

U1. New Delhi-63. by Parul Arora. 5 ..Introduction • • • • • • • • • What is an Operating System? Features of Mainframe Systems Features of Desktop Systems Discuss Multiprocessor Systems Features of Distributed Systems Features of Clustered System Types of Real -Time Systems Features of Handheld Systems Features of Computing Environments © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora. New Delhi-63.What is an Operating System? • A program that acts as an intermediary between a user of a computer and the computer hardware. Make the computer system convenient to use. • Use the computer hardware in an efficient manner. • Operating system goals: Execute user programs and make solving user problems easier. U1. 6 .

4.Computer System Components 1. Users (people. Operating system – controls and coordinates the use of the hardware among the various application programs for the various users. Hardware – provides basic computing resources (CPU. New Delhi-63. video games. U1.. 2. I/O devices). 7 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. database systems. 3. by Parul Arora. other computers). machines. Applications programs – define the ways in which the system resources are used to solve the computing problems of the users (compilers. business programs). memory.

by Parul Arora. 8 .. U1.Abstract View of System Components © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

• Control program – controls the execution of user programs and operations of I/O devices . U1. by Parul Arora.. 9 .Operating System Definitions • Resource allocator – manages and allocates resources. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Kernel – the one program running at all times (all else being application programs). New Delhi-63.

U1. by Parul Arora.Operating System View • Users View Ease of use Resource utilization Individual usability no user view • System view Resource allocator Operation and control of I/O devices • System Goals Convenience for the user efficient © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 10 . New Delhi-63..

• Resident monitor initial control in monitor control transfers to job when job completes control transfers pack to monitor © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. First rudimentary operating system. 11 . U1. New Delhi-63.Mainframe Systems • Reduce setup time by batching similar jobs • Automatic job sequencing – automatically transfers control from one job to another.

12 .. New Delhi-63.Memory Layout for a Simple Batch System © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

. U1.Multiprogrammed Batch Systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 13 .

. • Memory management – the system must allocate the memory to several jobs. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 14 . • Allocation of devices. U1.OS Features Needed for Multiprogramming • I/O routine supplied by the system. New Delhi-63. by Parul Arora. • CPU scheduling – the system must choose among several jobs ready to run.

by Parul Arora. 15 • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A job swapped in and out of memory to the disk. when the operating system finishes the execution of one command.. On-line communication between the user and the system is provided. . New Delhi-63.Time-Sharing Systems–Interactive Computing • The CPU is multiplexed among several jobs that are kept in memory and on disk (the CPU is allocated to a job only if the job is in memory). U1. it seeks the next “control statement” from the user’s keyboard.

New Delhi-63. mice. small printers. • I/O devices – keyboards. Linux) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Can adopt technology developed for larger operating system’ often individuals have sole use of computer and do not need advanced CPU utilization of protection features.Desktop Systems • Personal computers – computer system dedicated to a single user.. 16 . • May run several different types of operating systems (Windows. U1. MacOS. display screens. • User convenience and responsiveness. by Parul Arora. UNIX.

. communication usually takes place through the shared memory. 17 . • Advantages of parallel system: Increased throughput Economical Increased reliability graceful degradation fail-soft systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. • Tightly coupled system – processors share memory and a clock. U1.Parallel Systems • Multiprocessor systems with more than on CPU in close communication.

Many processes can run at once without performance deterioration. 18 . More common in extremely large systems © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Parallel Systems (Cont.. U1. Most modern operating systems support SMP Asymmetric multiprocessing Each processor is assigned a specific task. master processor schedules and allocated work to slave processors. by Parul Arora. New Delhi-63.) Symmetric multiprocessing (SMP) Each processor runs and identical copy of the operating system.

by Parul Arora. New Delhi-63.Symmetric Multiprocessing Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 19 . U1..

processors communicate with one another through various communications lines. • Loosely coupled system – each processor has its own local memory. by Parul Arora. 20 . Resources Sharing Computation speed up – load sharing Reliability Communications © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. such as high-speed buses or telephone lines. • Advantages of distributed systems.Distributed Systems • Distribute the computation among several physical processors. U1.

21 .Distributed Systems (cont) • Requires networking infrastructure. by Parul Arora. • Local area networks (LAN) or Wide area networks (WAN) • May be either client-server or peer-to-peer systems. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. New Delhi-63.

General Structure of Client-Server © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 22 .. U1.

. • Asymmetric clustering: one server runs the application while other servers standby. New Delhi-63.Clustered Systems • Clustering allows two or more systems to share storage. 23 . • Provides high reliability. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Symmetric clustering: all N hosts are running the application. by Parul Arora.

• Well-defined fixed-time constraints. medical imaging systems.. 24 .Real-Time Systems • Often used as a control device in a dedicated application such as controlling scientific experiments. and some display systems. industrial control systems. U1. by Parul Arora. • Real-Time systems may be either hard or soft real-time. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

data stored in short term memory. 25 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. by Parul Arora. U1.) • Hard real-time: Secondary storage limited or absent. . virtual reality) requiring advanced operating-system features. or read-only memory (ROM) Conflicts with time-sharing systems. not supported by general-purpose operating systems. • Soft real-time Limited utility in industrial control of robotics Useful in applications (multimedia.Real-Time Systems (Cont.

U1. 26 .Handheld Systems • Personal Digital Assistants (PDAs) • Cellular telephones • Issues: Limited memory Slow processors Small display screens. by Parul Arora. New Delhi-63.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

.Migration of Operating-System Concepts and Features © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. New Delhi-63. by Parul Arora. 27 .

U1.Computing Environments • Traditional computing • Web-Based Computing • Embedded Computing © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 28 .. by Parul Arora.

New Delhi-63.Memory management © Bharati Vidyapeeth’s Institute of Computer Applications and Management . by Parul arora U1. 29 .

U1. New Delhi-63.Learning Objective • • Major responsibility of the operating system To discuss with both organizing and managing memory Real (main) memory first Virtual memory next Memory organization . by Parul Arora.how memory is structured Memory management .. 30 .strategies for optimizing performance • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63.Memory Management • • • • • • Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.. U1. 31 .

by Parul Arora. • User programs go through several steps before being run.Background • Program must be brought into memory and placed within a process for it to be run. New Delhi-63.. U1. 32 . • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

g. absolute code can be generated. New Delhi-63.. by Parul Arora. must recompile code if starting location changes.Binding of Instructions and Data to Memory • Compile time: If memory location known a priori. • Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. base and limit registers). Need hardware support for address maps (e. 33 . • Load time: Must generate relocatable code if memory location is not known at compile time. U1.

34 . U1. by Parul Arora..Multistep Processing of a User © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

. New Delhi-63. logical (virtual) and physical addresses differ in execution-time address-binding scheme. 35 .Logical vs. • Logical and physical addresses are the same in compiletime and load-time address-binding schemes. also referred to as virtual address. Physical Address Space • The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Logical address – generated by the CPU. by Parul Arora. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Physical address – address seen by the memory unit.

the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. • In MMU scheme.Memory-Management Unit • Hardware device that maps virtual to physical address. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. • The user program deals with logical addresses. 36 . it never sees the real physical addresses. New Delhi-63. by Parul Arora..

. by Parul Arora.Dynamic relocation using a relocation register © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 37 . U1. New Delhi-63.

unused routine is never loaded. 38 . U1.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization. • No special support from the operating system is required implemented through program design.. by Parul Arora. • Useful when large amounts of code are needed to handle infrequently occurring cases. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

and executes the routine.. • Operating system needed to check if routine is in processes’ memory address. • Dynamic linking is particularly useful for libraries. 39 . New Delhi-63. used to locate the appropriate memory-resident library routine. • Small piece of code. stub.Dynamic Linking • Linking postponed until execution time. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. • Stub replaces itself with the address of the routine. U1.

no special support needed from operating system. U1. New Delhi-63.Overlays • Keep in memory only those instructions and data that are needed at any given time. • Needed when process is larger than amount of memory allocated to it. 40 . programming design of overlay structure is complex © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Implemented by user.. by Parul Arora.

Overlays for a Two-Pass Assembler

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 41

Swapping
• • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

• •

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 42

Schematic View of Swapping

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 43

usually held in low memory with interrupt vector.. and from changing operating-system code and data.Contiguous Allocation • Main memory usually into two partitions: Resident operating system. limit register contains range of logical addresses – each logical address must be less than the limit register. Relocation register contains value of smallest physical address. User processes then held in high memory. 44 . • Single-partition allocation Relocation-register scheme used to protect user processes from each other. New Delhi-63. U1. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

45 . New Delhi-63..Hardware Support for Relocation and Limit Registers © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora.

When a process arrives. U1. New Delhi-63. holes of various size are scattered throughout memory. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 OS process 5 OS process 5 process 9 process 8 process 2 process 2 process 2 OS process 5 process 9 process 10 process 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. by Parul Arora.) Multiple-partition allocation Hole – block of available memory.Contiguous Allocation (Cont. it is allocated memory from a hole large enough to accommodate it. 46 .

47 . Worst-fit: Allocate the largest hole. New Delhi-63. Best-fit: Allocate the smallest hole that is big enough. Produces the largest leftover hole.Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. unless ordered by size. by Parul Arora. Produces the smallest leftover hole. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. must search entire list.. must also search entire list.

Do I/O only into OS buffers. 48 .. • Internal Fragmentation – allocated memory may be slightly larger than requested memory. New Delhi-63. this size difference is memory internal to a partition. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. and is done at execution time. but not being used. U1.Fragmentation • External Fragmentation – total memory space exists to satisfy a request. by Parul Arora. I/O problem Latch job in memory while it is involved in I/O. but it is not contiguous. Compaction is possible only if relocation is dynamic.

• Set up a page table to translate logical to physical addresses. between 512 bytes and 8192 bytes). New Delhi-63. 49 . • Keep track of all free frames. process is allocated physical memory whenever the latter is available.. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.Paging • Logical address space of a process can be noncontiguous. • Internal fragmentation. • Divide logical memory into blocks of same size called pages. by Parul Arora. need to find n free frames and load program. • To run a program of size n pages. • Divide physical memory into fixed-sized blocks called frames (size is power of 2.

Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory.. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. New Delhi-63. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 50 . by Parul Arora.

U1. 51 ..Address Translation Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 52 . by Parul Arora. New Delhi-63.. U1.

. New Delhi-63.Paging Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. 53 .

New Delhi-63. by Parul Arora. U1. 54 .Free Frames Before allocation After allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

by Parul Arora. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page-table length register (PRLR) indicates size of the page table.. • Page-table base register (PTBR) points to the page table. • In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. 55 .Implementation of Page Table • Page table is kept in main memory. New Delhi-63. U1.

Otherwise get frame # from page table in memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Associative Memory Associative memory – parallel search Page # Frame # Address translation (A´.. U1. get frame # out. New Delhi-63. by Parul Arora. A´´) If A´ is in associative register. 56 .

57 .. New Delhi-63. by Parul Arora.Paging Hardware With TLB © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

New Delhi-63. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 – α) =2+ε–α © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 58 .Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers.. ration related to number of associative registers. by Parul Arora.

and is thus a legal page. • Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space.. by Parul Arora. “invalid” indicates that the page is not in the process’ logical address space. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Memory Protection • Memory protection implemented by associating protection bit with each frame. New Delhi-63. 59 .

New Delhi-63. U1. by Parul Arora.Valid (v) or Invalid (i) Bit In A Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 60 ..

New Delhi-63.Page Table Structure • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 61 . by Parul Arora. U1.

by Parul Arora.. • A simple technique is a two-level page table. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Hierarchical Page Tables • Break up the logical address space into multiple page tables. New Delhi-63. U1. 62 .

a page offset consisting of 12 bits. U1. New Delhi-63. number page page offset 12 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a 10-bit page offset. a logical address is as follows: pi p2 d 10 10 a 10-bit page number. 63 . by Parul Arora.Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits.. Since the page table is paged. the page number is further divided into: Thus.

64 . by Parul Arora. U1.Two-Level Page-Table Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63..

Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 65 .. by Parul Arora. New Delhi-63.

. This page table contains a chain of elements hashing to the same location. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 66 . U1. • The virtual page number is hashed into a page table. New Delhi-63. by Parul Arora. If a match is found. • Virtual page numbers are compared in this chain searching for a match. the corresponding physical frame is extracted.Hashed Page Tables • Common in address spaces > 32 bits.

U1. 67 . New Delhi-63..Hashed Page Table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora.

U1.Inverted Page Table • One entry for each real page of memory. by Parul Arora. but increases time needed to search the table when a page reference occurs. 68 . • Use hash table to limit the search to one — or at most a few — page-table entries.. • Entry consists of the virtual address of the page stored in that real memory location. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Decreases memory needed to store each page table. with information about the process that owns that page.

Inverted Page Table Architecture © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. by Parul Arora. New Delhi-63. 69 ..

New Delhi-63. Shared code must appear in same location in the logical address space of all processes. text editors.e. window systems).. Private code and data Each process keeps a separate copy of the code and data. 70 . The pages for the private code and data can appear anywhere in the logical address space. by Parul Arora.. compilers. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i. U1.

New Delhi-63.. by Parul Arora. 71 . U1.Shared Pages Example © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

stack. object. 72 . global variables.. by Parul Arora. symbol table. A segment is a logical unit such as: main program. common block. function. method. New Delhi-63. local variables.Segmentation Memory-management scheme that supports user view of memory. arrays © Bharati Vidyapeeth’s Institute of Computer Applications and Management. A program is a collection of segments. U1. procedure.

User’s View of a Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. 73 . U1. by Parul Arora.

74 ..Logical View of Segmentation 1 1 2 3 4 4 2 3 user space physical memory space © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1. New Delhi-63.

offset>. limit – specifies the length of the segment. each table entry has: base – contains the starting physical address where the segments reside in memory.Segmentation Architecture • • • Logical address consists of a two tuple: <segment-number. U1. 75 .. New Delhi-63. Segment-table length register (STLR) indicates number of segments used by a program segment number s is legal if s < STLR. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • • • Segment-table base register (STBR) points to the segment table’s location in memory. by Parul Arora. Segment table – maps two-dimensional physical addresses.

first fit/best fit external fragmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1..Segmentation Architecture (Cont. by Parul Arora. 76 .) • Relocation. shared segments same segment number • Allocation. dynamic by segment table • Sharing. New Delhi-63.

U1.) • Protection. • A segmentation example is shown in the following diagram © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Segmentation Architecture (Cont. 77 . New Delhi-63. by Parul Arora. memory allocation is a dynamic storage-allocation problem.. code sharing occurs at segment level. • Since segments vary in length. With each entry in segment table associate: validation bit = 0 ⇒ illegal segment read/write/execute privileges • Protection bits associated with segments.

U1. New Delhi-63. by Parul Arora.Segmentation Hardware © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 78 ..

by Parul Arora. 79 .Example of Segmentation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1.

by Parul Arora. 80 .. New Delhi-63.Sharing of Segments © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.

. • Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment. but rather the base address of a page table for this segment.Segmentation with Paging – MULTICS • The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments. by Parul Arora. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 81 . U1. New Delhi-63.

MULTICS Address Translation Scheme © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 82 . by Parul Arora. New Delhi-63.. U1.

. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 83 . U1. the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. New Delhi-63. by Parul Arora.Segmentation with Paging – Intel 386 As shown in the following diagram.

84 . New Delhi-63.Intel 30386 Address Translation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. U1..

85 .Virtual memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management . New Delhi-63. by Parul arora U1.

• Describe the reason for and use of cache memory. • Evaluate the trade-offs in terms of memory size (main memory. cache memory. • Summarize the principles of virtual memory as applied to caching and paging. 86 . • Discuss the concept of thrashing. by Parul Arora.Learning Objectives • Explain the concept of virtual memory and how it is realized in hardware and software.. New Delhi-63. both in terms of the reasons it occurs and the techniques used to recognize and manage the problem. auxiliary memory) and processor speed. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

Only part of the program needs to be in memory for execution. by Parul Arora. . Allows for more efficient process creation.. Allows address spaces to be shared by several processes. New Delhi-63. Logical address space can therefore be much larger than physical address space. 87 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Virtual memory can be implemented via: Demand paging Demand segmentation U1.Background • Virtual memory – separation of user logical memory from physical memory.

88 .Virtual Memory That is Larger Than Physical Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1.. New Delhi-63. by Parul Arora.

Demand Paging Bring a page into memory only when it is needed. New Delhi-63. U1. Less I/O needed Less memory needed Faster response More users Page is needed ⇒ reference to it invalid reference ⇒ abort not-in-memory ⇒ bring to memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 89 . by Parul Arora.

Transfer of a Paged Memory to Contiguous Disk Space © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. 90 . by Parul Arora. U1.

0 ⇒ not-in-memory) Initially valid–invalid Frame #is set to 0 on all entries.Valid-Invalid Bit With each page table entry a valid–invalid bit is associated (1 ⇒ in-memory. by Parul Arora.. but valid-invalid bit 1 Example of a page table snapshot. U1. 91 . 1 1 1 0 Μ 0 0 page table © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.

New Delhi-63. 92 .. U1. by Parul Arora.Page Table When Some Pages Are Not in Main Memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. Restart instruction: Least Recently Used block move U1. Swap page into frame. New Delhi-63. Reset tables. 93 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Just not in memory.Page Fault • If there is ever a reference to a page. . • • • • Get empty frame. validation bit = 1. first reference will trap to OS ⇒ page fault • OS looks at another table to decide: Invalid reference ⇒ abort..

U1. 94 .Steps in Handling a Page Fault © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. New Delhi-63. by Parul Arora.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management. 95 . but not really in use. by Parul Arora.. U1. algorithm performance – want an algorithm which will result in minimum number of page faults. • Same page may be brought into memory several times.What happens if there is no free frame? • Page replacement – find some page in memory. swap it out. New Delhi-63.

every reference is a fault Effective Access Time (EAT) EAT = (1 – p) x memory access + p (page fault overhead + [swap page out ] + swap page in + restart overhead) © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63.. U1. 96 . by Parul Arora.Performance of Demand Paging Page Fault Rate 0 ≤ p ≤ 1.0 if p = 0 no page faults if p = 1.

U1. Swap Page Time = 10 msec = 10. 97 . by Parul Arora. New Delhi-63..Demand Paging Example Memory access time = 1 microsecond 50% of the time the page that is being replaced has been modified and therefore needs to be swapped out.000 msec EAT = (1 – p) x 1 + p (15000) 1 + 15000P (in msec) © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

98 .. U1.Process Creation • Virtual memory allows other benefits during process creation: • Copy-on-Write • Memory-Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora.

. • Free pages are allocated from a pool of zeroed-out pages. • COW allows more efficient process creation as only modified pages are copied. 99 .If either process modifies a shared page. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. only then is the page copied. New Delhi-63. by Parul Arora.Copy-on-Write • Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory.

New Delhi-63. .Memory-Mapped Files • Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory. U1.. A page-sized portion of the file is read from the file system into a physical page. • A file is initially read using demand paging. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. • Simplifies file access by treating file I/O through memory rather than read() write() system calls. by Parul Arora. • Also allows several processes to map the same file allowing the pages in memory to be shared. 100 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

New Delhi-63. 101 . U1. by Parul Arora.Memory Mapped Files © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

U1. by Parul Arora.Page Replacement • Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. • Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk. New Delhi-63.. 102 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. • Page replacement completes separation between logical memory and physical memory – large virtual memory can be provided on a smaller physical memory.

.Need For Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. by Parul Arora. 103 . U1.

use it. • Restart the process. 104 . use a page replacement algorithm to select a victim frame.If there is a free frame. by Parul Arora. U1. New Delhi-63. • Read the desired page into the (newly) free frame.Basic Page Replacement • Find the location of the desired page on disk.. . • Find a free frame: . © Bharati Vidyapeeth’s Institute of Computer Applications and Management.If there is no free frame. Update the page and frame tables.

U1. by Parul Arora. 105 . New Delhi-63..Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

4. 106 .. 2. In all our examples. by Parul Arora. 2. the reference string is 1. 3. 1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 4. New Delhi-63. 5. 5. 2. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string.Page Replacement Algorithms Want lowest page-fault rate. 3. U1. 1.

U1.Graph of Page Faults Versus The Number of Frames © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 107 . by Parul Arora.. New Delhi-63.

. 2. 1. 2. 4. 3. 3. by Parul Arora. New Delhi-63. 108 . 4. 2. 5. 5 3 frames 1 2 3 1 1 2 3 1 2 3 4 4 1 2 5 1 2 3 5 3 4 4 5 10 page faults 9 page faults 4 frames 2 3 4 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 1.First-In-First-Out (FIFO) Algorithm Reference string: 1.

. 109 .First-In-First-Out (FIFO) Algorithm FIFO Replacement – Belady’s Anomaly more frames ⇒ less page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. U1. by Parul Arora.

FIFO Page Replacement

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 110

FIFO Illustrating Belady’s Anamoly

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 111

Optimal Algorithm
Replace page that will not be used for longest period of time. 4 frames example 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 2 3 4 5 4 6 page faults

How do you know this? Used for measuring how well your algorithm performs.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora. U1. 112

113 .Optimal Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. U1. by Parul Arora. New Delhi-63.

114 . New Delhi-63. 4. 5 1 2 3 4 5 3 4 5 Counter implementation Every page entry has a counter. 5. look at the counters to determine which are to change. copy the clock into the counter. 1. 2. 4. 1. every time page is referenced through this entry. 2.. 3. 2. by Parul Arora. U1.Least Recently Used (LRU) Algorithm Reference string: 1. 3. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. When a page needs to be changed.

U1. by Parul Arora. 115 . New Delhi-63.LRU Page Replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

. New Delhi-63.LRU Algorithm (Cont. U1.) Stack implementation – keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 116 .

Use Of A Stack to Record The Most Recent Page References © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. 117 . New Delhi-63.. by Parul Arora.

LRU Approximation Algorithm Reference bit With each page associate a bit. New Delhi-63. Clock replacement. then: set reference bit 0. We do not know the order. replace next page (in clock order). 118 . leave page in memory. however. subject to same © Bharati Vidyapeeth’s Institute of Computer Applications and Management. initially = 0 When page is referenced bit set to 1.. U1. by Parul Arora. rules. Second chance Need reference bit. Replace the one which is 0 (if one exists). If page to be replaced (in clock order) has reference bit = 1.

119 . New Delhi-63. U1.. by Parul Arora.Second-Chance (clock) Page-Replacement Algorithm © Bharati Vidyapeeth’s Institute of Computer Applications and Management.

by Parul Arora. LFU Algorithm: replaces page with smallest count.Counting Algorithms • Keep a counter of the number of references that have been made to each page. New Delhi-63. U1. • • © Bharati Vidyapeeth’s Institute of Computer Applications and Management.. 120 . MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used.

U1.. 2 pages to handle from. • Two major allocation schemes. fixed allocation priority allocation © Bharati Vidyapeeth’s Institute of Computer Applications and Management. might span 2 pages. 121 . New Delhi-63. by Parul Arora.Allocation of Frames • Each process needs minimum number of pages. • Example: IBM 370 – 6 pages to handle SS MOVE instruction: instruction is 6 bytes. 2 pages to handle to.

by Parul Arora. • Proportional allocation – Allocate according to the size of process... si = size of process pi S = ∑ si m = total number of frames s ai = allocation for pi = i × m S m = 64 si = 10 s2 = 127 10 × 64 ≈ 5 137 127 a2 = × 64 ≈ 59 137 a1 = © Bharati Vidyapeeth’s Institute of Computer Applications and Management. give each 20 pages.Fixed Allocation • Equal allocation – e. New Delhi-63. if 100 frames and 5 processes. U1. 122 .g.

select for replacement a frame from a process with lower priority number.. select for replacement one of its frames.Priority Allocation • Use a proportional allocation scheme using priorities rather than size. • If process Pi generates a page fault. U1. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 123 . New Delhi-63. by Parul Arora.

Global vs. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. 124 . U1. one process can take a frame from another. by Parul Arora. Local Allocation • Global replacement – process selects a replacement frame from the set of all frames.. • Local replacement – each process selects from only its own set of allocated frames.

. U1. This leads to: low CPU utilization.Thrashing If a process does not have “enough” pages. Thrashing ≡ a process is busy swapping pages in and out. operating system thinks that it needs to increase the degree of multiprogramming. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora. 125 . the page-fault rate is very high. another process added to the system. New Delhi-63.

by Parul Arora. Localities may overlap. 126 .. Why does thrashing occur? Σ size of locality > total memory size © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Thrashing Why does paging work? Locality model Process migrates from one locality to another. U1. New Delhi-63.

Working-Set Model
∆ ≡ working-set window ≡ a fixed number of page references Example: 10,000 instruction WSSi (working set of Process Pi) = total number of pages referenced in the most recent ∆ (varies in time)
if ∆ too small will not encompass entire locality. if ∆ too large will encompass several localities. if ∆ = ∞ ⇒ will encompass entire program.

D = Σ WSSi ≡ total demand frames if D > m ⇒ Thrashing Policy if D > m, then suspend one of the processes.
© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 127

Working-set model

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 128

Keeping Track of the Working Set
• Approximate with interval timer + a reference bit • Example: ∆ = 10,000
Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 ⇒ page in working set.

• Why is this not completely accurate? • Improvement = 10 bits and interrupt every 1000 time units.

© Bharati Vidyapeeth’s Institute of Computer Applications and Management,, New Delhi-63, by Parul Arora.

U1. 129

If actual rate too low. If actual rate too high. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 130 . process gains frame. by Parul Arora.. process loses frame.Page-Fault Frequency Scheme Establish “acceptable” page-fault rate. U1. New Delhi-63.

131 . New Delhi-63. U1.Other Considerations Prepaging Page size selection fragmentation table size I/O overhead locality © Bharati Vidyapeeth’s Institute of Computer Applications and Management. by Parul Arora..

the working set of each process is stored in the TLB.The amount of memory accessible from the TLB. by Parul Arora. New Delhi-63. U1.) TLB Reach . 132 . © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Otherwise there is a high degree of page faults. TLB Reach = (TLB Size) X (Page Size) Ideally..Other Considerations (Cont.

by Parul Arora.Increasing the Size of the TLB • Increase the Page Size. This may lead to an increase in fragmentation as not all applications require a large page size. • Provide Multiple Page Sizes. 133 .. New Delhi-63. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. U1. This allows applications that require larger page sizes the opportunity to use them without an increase in fragmentation.

i++) A[i. New Delhi-63. i++) for (j = 0. 1024 page faults © Bharati Vidyapeeth’s Institute of Computer Applications and Management.Other Considerations (Cont.length. j++) for (i = 0. U1..j] = 0. j < A.length.length. j++) A[i. j < A. 134 . Each row is stored in one page Program 1 for (j = 0. i < A.) Program structure int A[][] = new int[1024][1024].length. i < A. by Parul Arora. 1024 x 1024 page faults Program 2 for (i = 0.j] = 0.

by Parul Arora. 135 © Bharati Vidyapeeth’s Institute of Computer Applications and Management.and also allows degree of multiprogramming to be raised. Memory management algorithms differ in many concepts. Virtual memory frees application programers from worrying about memory availability U1. New Delhi-63. Multiprogramming increased the performance of computer system. ..Conclusion • • • • • Operating systems provide an environment for development and execution of programs. Virtual memory allows extremely large processes to be run.

Four major categories of operating systems are batch. Policies for determining which pages to load and remove from memory include Random Replacement.Summary • In the introduction. . 136 Used. First In First Out. personal computing and dedicated. Resources are any objects that can be allocated within a system. Least Recently Used. New Delhi-63. by Parul Arora. timesharing. Some resources such as primary memory can be space-multiplexed while other resources such as the CPU must be time-multiplexed. we saw that software can be roughly divided into two groups: application software and system software. and Least Frequently U1. Second Chance. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. Operating systems are a type of system software that allow applications to interface with computer hardware. • • Virtual Memory allows systems to execute programs which exceed the size of primary memory by dividing programs into sections called pages which can be loaded into sections of memory called page frames. and the operating system is responsible for managing them..

The Hardware mechanism that enables a device to notify the CPU is called __________. U1. a) Polling b) Interrupt c) System Call d) None of the above 2. by Parul Arora. New Delhi-63. 137 .Review Questions (OBJ) 1. Who is called a supervisor of computer acitvity ? a) CPU b) Operating system c) Control unit d) Application Program © Bharati Vidyapeeth’s Institute of Computer Applications and Management..

Review Questions (OBJ) 3. New Delhi-63. U1. by Parul Arora.. _________ is a high speed cache used to hold recently referenced page table entries a part of paged virtual memory a) Translation Lookaside buffer b) Inverse page table c) Segmented page table d) All the above © Bharati Vidyapeeth’s Institute of Computer Applications and Management. a) An extremely large main memory b) An extremely large secondary memory c) An illusion of extremely large main memory d) A type of memory used in super computers. 138 . 4. Virtual memory is __________.

139 .Review Questions (OBJ) 5. U1. by Parul Arora. a) A set of programs which controls computer working b) The way a computer operator works c) Conversion of high-level language in to machine level language d) The way a floppy disk drive operates © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. The term " Operating System " means ________.. Which of the following statement is not true? a) Multiprogramming implies multitasking b) Multi-user does not imply multiprocessing c) Multitasking does not imply multiprocessing d) Multithreading implies multi-user 6.

a) Virtual Memory b) Interrupts c) Main memory d) Cache memory © Bharati Vidyapeeth’s Institute of Computer Applications and Management. This type of loading is called _________ Static loading Dynamic loading Dynamic linking Overlays 8. by Parul Arora. U1. ) Routine a) b) c) d) is not loaded until it is called. New Delhi-63.. All routines are kept on disk in a relocatable load format. 140 . The main program is loaded into memory & is executed.Review Questions (OBJ) 7. The principle of locality of reference justifies the use of ________.

Review Questions (OBJ) 9. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. New Delhi-63. and a process is allocated 3 page frames in real memory and references its pages in the order 1 2 3 2 4 5 2 3 2 4 1 and the page replacement is FIFO. a) 10 b) 7 c) 8 d) 9 10.. 141 . by Parul Arora. ) The problem of thrashing is effected scientifically by ________. If all page frames are initially empty. the total number of page faults caused by the process will be __________. a) Program structure b) Program size c) Primary storage size d) None of the above U1.

9. What are the three main purposes of an operating system? 4. U1. What are the main differences between operating systems for mainframe computers and personal computers? 3. What is the main advantage of multiprogramming 2. Explain the difference between logical and physical addresses. Explain the difference between internal and external fragmentation 10.. How do MULTICS and UNIX differ? 7. How do I/O-bound and CPU-bound programs differ? 6. Why are page sizes always powers of 2 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. 142 . New Delhi-63. by Parul Arora. List the four steps that are necessary to run a program on a completely dedicated machine 5.Review Questions (Short) 1. How does a real-time system differ from time-share? 8.

Why are segmentation and paging sometimes combined into one scheme? © Bharati Vidyapeeth’s Institute of Computer Applications and Management. How do global and local allocation differ? 20. Describe the actions taken by the operating system when a page fault occurs.. What is meant by locality? 21. What is virtual memory? 17. by Parul Arora. 16. Why is there a valid/invalid bit? Where is it kept? 18. 143 . U1. When do page faults occur? 15.Review Questions (Short) 11. What is Belady’s anomaly? 19. How was memory mapping used in extending the usefulness of minicomputers? 13. New Delhi-63. What are overlays? 12. What is reentrant code? 14.

4. for four page frames? 1. New Delhi-63. Best-?t. 200K. 4. 2. to determine which page is victim. 112K. 4. 7. How many page faults occur for your algorithm for the following reference string. by Parul Arora. 5.)If a memory reference takes 200 nanoseconds. 8. and 426K (in order)? Which algorithm makes the most ef?cient use of memory? 2. how long does a paged memory reference take? b. 6. U1. List ways to implement LRU. what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time. how would each of the First-?t. 8.) 3.)If we add associative registers. 1. 3. 8. if the entry is there. 9. 7. 5. 9. © Bharati Vidyapeeth’s Institute of Computer Applications and Management. and 600K (in order). 417K. 4. Given memory partitions of 100K. 2. 144 . and 75 percent of all pagetable references are found in the associative registers. 7. 300K.. 5. 3. a.Review Questions (Long) 1. 500K. and Worst-?t algorithms place processes of 212K. 4. Consider a paging system with the page table stored in memory.

4th Edition. New Delhi-63. 2001 • "Operating Systems” Tannenbaum PHI.2001 • Madnick E.. 2000 © Bharati Vidyapeeth’s Institute of Computer Applications and Management. “Operating System Concepts” Peason. ”Operating System”: TMH..6th Ed. by Parul Arora..Recommended reading • Silbersachatz and Galvin.. Donovan J. 145 . U1.

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