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Combinational Logic Functions Decoder Encoder Multiplexer Demultiplexer Magnitude Comparator Parity Generator and Checker

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**Time Division Multiplexing (TDM)
**

Each user has a specific time slot in a TDM data frame. Each frame has 24 users. TDM requires a time-dependent (counter) source to synchronize the select lines. Each user’s time slot repeats on the next frame for more data. The links are called T-Carriers (such as a T1 Line).

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**TDM Data Streams
**

Two methods in which data is transmitted:

Bit Multiplexing: One bit is sent at a time from the channel during the channel’s assigned time slot Word Multiplexing: One byte is sent at a time from the channel during the channel’s assigned time slot

4

TDM Data Streams

TDM Data Streams

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1

9 10 Demultiplexer Basics – 4 Demultiplexer Basics – 5 11 12 2 .TDM Data Streams Demultiplexer Basics – 1 Demultiplexer: A digital circuit that uses a decoder to direct a single input (from a MUX) to one of several outputs. Demultiplexer Basics – 3 They are similar to a MUX and can be designed using CASE Statements. 1-to-4 DEMUX Equations: Y( 0 ) = D0 S1 S0 . 7 8 Demultiplexer Basics – 2 Designated as a 1-to-n DEMUX that requires m select inputs such that n outputs = 2m select inputs. Y( 3 ) = D0 S1 S0. The selected output is chosen by the Select Inputs (as in a MUX). A DEMUX performs the reverse operation of a MUX. Y( 1) = D0 S1 S0 . Y( 2 ) = D0 S1 S0 .

BEGIN inputs <= d & s. END dmux8. “10111111” WHEN “0001”.Demultiplexer VHDL Entity ENTITY dmux8 IS PORT( s : IN STD_LOGIC_VECTOR (2 downto 0). y : OUT STD_LOGIC_VECTOR (0 to 7)). d : IN STD_LOGIC. 13 14 Demultiplexer VHDL Architecture Analog MUX/DEMUX Uses a CMOS Switch or Transmission Gate that will allow a signal to Pass in two directions for + and – Voltages. 15 16 Analog MUX/DEMUX Analog MUX/DEMUX 17 18 3 . • • • • • • “11111111” WHEN others. Demultiplexer VHDL Architecture ARCHITECTURE a OF dmux8 IS SIGNAL inputs : STD_LOGIC_VECTOR (3 downto 0). WITH inputs select Y <= “01111111” WHEN “0000”. Multiplexes 4 CMOS Switches to a single output (Y) for analog multiplexing. Some commercial types such as a CD4066 or 74HC4066. END a.

2 ) …. END IF. A very simple One-Bit Magnitude Comparator is the Two-Input XNOR Gate: When both inputs are equal. BEGIN PROCESS (a. it is a 0. VHDL 4-Bit Magnitude Comparator – 2 ARCHITECTURE a OF compare4 IS SIGNAL compare :STD_LOGIC_VECTOR (2 downto 0). if they are not. agtb. start with the MSB: If An–1 > Bn–1. 24 4 . 19 Magnitude Comparators – 2 Multiple Bit Comparisons AEQB = ( An-1 ⊕ Bn-1 ) • ( An.2 ⊕ Bn. b RANGE 0 to 15. then try the next most significant bit. For A > B. ELSE compare <= “111”. Also adds A > B (AGTB) and A < B (ALTB) Outputs. aeqb <= compare(1). END PROCESS END a. b) BEGIN IF a<b THEN compare <= “110”. altb <= compare(0). Even Parity: A parity system that requires the binary number and the parity bit to have an even # of 1s. the output is a 1. then AGTB = 1 If not. 23 Parity Basics – 1 Parity: A digital system that checks for errors in a n-Bit Binary Number or Code.Magnitude Comparators – 1 Magnitude Comparator: A digital circuit that compares two n-Bit Binary Numbers and indicates if they are equal or which is greater. aeqb. Odd Parity: A parity system that requires the binary number and the parity bit to have an Odd # of 1s. agtb <= compare(2). ELSIF a = b THEN compare <= “101”. 20 VHDL 4-Bit Magnitude Comparator – 1 ENTITY compare4 IS PORT( a. 21 22 : IN INTEGER : OUT STD_LOGIC). altb END compare4. VHDL 4-Bit Magnitude Comparator – 3 ELSIF a > b THEN compare <= “011”.

If Parity is EVEN.Parity Basics – 2 Parity Bit: A bit appended on the end of a binary number or code to make the # of 1s odd or even depending on the type of parity in the system. that are on the COM Port. If there are no errors. the syndrome output (Perr) is 0. the two bits (P1 and P2) will not be equal. When the two inputs are 01 or 10. 25 Parity Basics – 3 26 Parity Calculation N1 = 0110110: It has four 1s (an even number). the output is a 0. the receiver (RX) just generates a new Parity Bit (P1) based on the received parallel data and then compares it to the parity bit transmitted (P2). When the two inputs are 00 or 11. To check for a Parity error. Parity is not a foolproof system. Parity is used in transmitting and receiving data by devices in a PC called UARTs. Parity Generator HW – 3 If there is an error. Peven = 1. Podd = 0. For a parity generator of n bits. Parity Generation HW – 1 A basic two-bit parity generator can be constructed from a XOR Gate. add more gates. 27 28 N2 = 1000000: Parity Generator HW – 2 Cascading a long chain of XOR gates could cause excessive propagation delays. and we can use a two-bit magnitude comparator to check this (an XOR gate). the Parity Bit = 0 to keep it an even number (4). 29 30 5 . the Parity Bit = 1 to make it an odd number (5). One 1 in the data. the output is a 1 (so this is even parity). the error is not detected. If Parity is ODD. This check is called syndrome. If two bits are in error.

USE ieee. 33 34 Summary Decoder Encoder Multiplexer Demultiplexer Magnitude Comparator Parity Generator and Checker Homework Chapter 6 35 42 45 51 52 (Demultiplexer) (Magnitude Comparator) (Parity) a (Parity Generator) a (Parity Checker) 35 36 6 . pe <= p(3). 31 32 4-Bit Parity VHDL Code – 1 LIBRARY ieee. ENTITY parity4_gen IS PORT( d : IN STD_LOGIC_VECTOR (0 to 3).std_logic1164. parity_generate: FOR i IN 2 to 3 GENERATE p(i) <= p(i-1) xor d(i). BEGIN p(1) <= d(0) xor d(1).ALL. END parity4_gen. OUT STD_LOGIC). END parity. pe . END GENERATE. END GENERATE. 4-Bit Parity VHDL Code – 2 ARCHITECTURE parity OF parity4_gen IS SIGNAL p : STD_LOGIC_VECTOR (1 to 3). __statement.Parity Generator HW – 4 VHDL GENERATE Statement __generate_label: FOR __index_variable IN __range GENERATE __statement.

ACLU 37 7 .

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