**ELECTRONIC DEVICES AND CIRCUIT THEORY
**

ROBERT BOYLESTAD LOUIS NASHELSKY

PRENTICE HALL

Upper Saddle River, New Jersey Columbus, Ohio

8 1.Contents PREFACE ACKNOWLEDGMENTS xiii xvii 1 1.10 1.12 1.1 1.14 1.7 1.3 DIODE APPLICATIONS Introduction 51 Load-Line Analysis 52 Diode Approximations 57 51 v .5 1.2 1.4 1.and p-Type 7 Semiconductor Diode 10 Resistance Levels 17 Diode Equivalent Circuits 24 Diode Specification Sheets 27 Transition and Diffusion Capacitance 31 Reverse Recovery Time 32 Semiconductor Diode Notation 32 Diode Testing 33 Zener Diodes 35 Light-Emitting Diodes (LEDs) 38 Diode Arrays—Integrated Circuits 42 PSpice Windows 43 1 2 2.11 1.16 1.3 1.9 1.2 2.17 SEMICONDUCTOR DIODES Introduction 1 Ideal Diode 1 Semiconductor Materials 3 Energy Levels 6 Extrinsic Materials—n.13 1.15 1.6 1.1 2.

8 2.7 3.2 4.9 2.13 DC BIASING—BJTS Introduction 143 Operating Point 144 Fixed-Bias Circuit 146 Emitter-Stabilized Bias Circuit 153 Voltage-Divider Bias 157 DC Bias with Voltage Feedback 165 Miscellaneous Bias Configurations 168 Design Operations 174 Transistor Switching Networks 180 Troubleshooting Techniques 185 PNP Transistors 188 Bias Stabilization 190 PSpice Windows 199 143 5 5.10 3.10 2.1 4.4 3.11 2.1 3.3 vi Contents FIELD-EFFECT TRANSISTORS Introduction 211 Construction and Characteristics of JFETs 212 Transfer Characteristics 219 211 .13 Series Diode Configurations with DC Inputs 59 Parallel and Series-Parallel Configurations 64 AND/OR Gates 67 Sinusoidal Inputs.3 4.9 4.4 4.12 2.11 3.8 4.7 4.2 3.1 5.6 3.8 3.11 4.3 3.6 2.12 4.2 5. Half-Wave Rectification 69 Full-Wave Rectification 72 Clippers 76 Clampers 83 Zener Diodes 87 Voltage-Multiplier Circuits 94 PSpice Windows 97 3 3.10 4.2.12 BIPOLAR JUNCTION TRANSISTORS Introduction 112 Transistor Construction 113 Transistor Operation 113 Common-Base Configuration 115 Transistor Amplifying Action 119 Common-Emitter Configuration 120 Common-Collector Configuration 127 Limits of Operation 128 Transistor Specification Sheet 130 Transistor Testing 134 Transistor Casing and Terminal Identification 136 PSpice Windows 138 112 4 4.9 3.5 2.5 3.7 2.5 4.6 4.4 2.

3 8.4 5.5 5.2 7.9 6.5.13 FET BIASING Introduction 253 Fixed-Bias Configuration 254 Self-Bias Configuration 258 Voltage-Divider Biasing 264 Depletion-Type MOSFETs 270 Enhancement-Type MOSFETs 274 Summary Table 280 Combination Networks 282 Design 285 Troubleshooting 287 P-Channel FETs 288 Universal JFET Bias Curve 291 PSpice Windows 294 253 7 7.8 6.6 7.13 Specification Sheets (JFETs) 223 Instrumentation 226 Important Relationships 227 Depletion-Type MOSFET 228 Enhancement-Type MOSFET 234 MOSFET Handling 242 VMOS 243 CMOS 244 Summary Table 246 PSpice Windows 247 6 6.3 8.2 6. Av.3 6.7 5.8 5.12 5.10 5.1 7.1 6.7 7.6 5.4 8.3 7.4 7.7 6.8 BJT TRANSISTOR MODELING Introduction 305 Amplification in the AC Domain 305 BJT Transistor Modeling 306 The Important Parameters: Zi.10 6.6 6.12 6.3 8.9 5.11 5. Zo.1 8.5 7. Ai 308 The re Transistor Model 314 The Hybrid Equivalent Model 321 Graphical Determination of the h-parameters 327 Variations of Transistor Parameters 331 305 8 8.11 6.6 BJT SMALL-SIGNAL ANALYSIS Introduction 338 Common-Emitter Fixed-Bias Configuration 338 Voltage-Divider Bias 342 CE Emitter-Bias Configuration 345 Emitter-Follower Configuration 352 Common-Base Configuration 358 338 Contents vii .5 6.4 6.

12 SYSTEMS APPROACH— EFFECTS OF Rs AND RL Introduction 452 Two-Port Systems 452 Effect of a Load Impedance (RL) 454 Effect of a Source Impedance (Rs) 459 Combined Effect of Rs and RL 461 BJT CE Networks 463 BJT Emitter-Follower Networks 468 BJT CB Networks 471 FET Networks 473 Summary Table 476 Cascaded Systems 480 PSpice Windows 481 452 11 11.13 9.11 10.10 9.7 9.3 10.4 10.4 9.2 9.9 9.5 9.14 9.6 10.11 9.13 Collector Feedback Configuration 360 Collector DC Feedback Configuration 366 Approximate Hybrid Equivalent Circuit 369 Complete Hybrid Equivalent Model 375 Summary Table 382 Troubleshooting 382 PSpice Windows 385 9 9.10 8.15 FET SMALL-SIGNAL ANALYSIS Introduction 401 FET Small-Signal Model 402 JFET Fixed-Bias Configuration 410 JFET Self-Bias Configuration 412 JFET Voltage-Divider Configuration 418 JFET Source-Follower (Common-Drain) Configuration 419 JFET Common-Gate Configuration 422 Depletion-Type MOSFETs 426 Enhancement-Type MOSFETs 428 E-MOSFET Drain-Feedback Configuration 429 E-MOSFET Voltage-Divider Configuration 432 Designing FET Amplifier Networks 433 Summary Table 436 Troubleshooting 439 PSpice Windows 439 401 10 10.12 8.8 9.9 8.8 10.1 11.6 9.3 viii Contents BJT AND JFET FREQUENCY RESPONSE Introduction 493 Logarithms 493 Decibels 497 493 .10 10.1 10.2 10.12 9.11 8.8.7 8.5 10.2 11.9 10.8 8.3 9.1 9.7 10.

5 11.3 13.7 13.5 12.2 14.9 DISCRETE AND IC MANUFACTURING TECHNIQUES Introduction 588 Semiconductor Materials.10 11.1 14.13 General Frequency Considerations 500 Low-Frequency Analysis—Bode Plot 503 Low-Frequency Response—BJT Amplifier 508 Low-Frequency Response—FET Amplifier 516 Miller Effect Capacitance 520 High-Frequency Response—BJT Amplifier 523 High-Frequency Response—FET Amplifier 530 Multistage Frequency Effects 534 Square-Wave Testing 536 PSpice Windows 538 12 12.4 11.9 11.8 13.1 12.11 11.4 14.2 12.5 14.1 13.4 12.9 12. and CMOS Differential Amplifier Circuits 574 PSpice Windows 575 544 13 13.7 11. Ge.2 13.3 12.8 11.3 14.6 11.6 14.12 11.10 12.6 13.8 OPERATIONAL AMPLIFIERS Introduction 609 Differential and Common-Mode Operation 611 Op-Amp Basics 615 Practical Op-Amp Circuits 619 Op-Amp Specifications—DC Offset Parameters 625 Op-Amp Specifications—Frequency Parameters 628 Op-Amp Unit Specifications 632 PSpice Windows 638 609 Contents ix .8 12. BIMOS.11.5 13.11 COMPOUND CONFIGURATIONS Introduction 544 Cascade Connection 544 Cascode Connection 549 Darlington Connection 550 Feedback Pair 555 CMOS Circuit 559 Current Source Circuits 561 Current Mirror Circuits 563 Differential Amplifier Circuit 566 BIFET. Si. and GaAs 588 Discrete Diodes 590 Transistor Fabrication 592 Integrated Circuits 593 Monolithic Integrated Circuit 595 The Production Cycle 597 Thin-Film and Thick-Film Integrated Circuits 607 Hybrid Integrated Circuits 608 588 14 14.7 14.4 13.6 12.7 12.

5 17.2 17.6 15.5 15.9 POWER AMPLIFIERS Introduction—Definitions and Amplifier Types 679 Series-Fed Class A Amplifier 681 Transformer-Coupled Class A Amplifier 686 Class B Amplifier Operation 693 Class B Amplifier Circuits 697 Amplifier Distortion 704 Power Transistor Heat Sinking 708 Class C and Class D Amplifiers 712 PSpice Windows 714 679 17 17.5 18.3 16.7 17.7 16.4 16.1 16.7 18.5 16.15 15.3 17.3 18.9 18.8 LINEAR-DIGITAL ICs Introduction 721 Comparator Unit Operation 721 Digital-Analog Converters 728 Timer IC Unit Operation 732 Voltage-Controlled Oscillator 735 Phase-Locked Loop 738 Interfacing Circuitry 742 PSpice Windows 745 721 18 18.2 18.6 16.2 15.4 17.6 17.3 15.1 18.10 x Contents FEEDBACK AND OSCILLATOR CIRCUITS Feedback Concepts 751 Feedback Connection Types 752 Practical Feedback Circuits 758 Feedback Amplifier—Phase and Frequency Considerations 765 Oscillator Operation 767 Phase-Shift Oscillator 769 Wien Bridge Oscillator 772 Tuned Oscillator Circuit 773 Crystal Oscillator 776 Unijunction Oscillator 780 751 .1 15.4 18.2 16.8 18.6 18.1 17.7 OP-AMP APPLICATIONS Constant-Gain Multiplier 648 Voltage Summing 652 Voltage Buffer 655 Controller Sources 656 Instrumentation Circuits 658 Active Filters 662 PSpice Windows 666 648 16 16.8 16.4 15.

5 21.10 20.15 21.12 21.3 20.7 POWER SUPPLIES (VOLTAGE REGULATORS) Introduction 783 General Filter Considerations 783 Capacitor Filter 786 RC Filter 789 Discrete Transistor Voltage Regulation 792 IC Voltage Regulators 799 PSpice Windows 804 783 20 20.1 20.2 21.7 21.3 19.2 20.5 20.9 21.6 20.4 21.11 OTHER TWO-TERMINAL DEVICES Introduction 810 Schottky Barrier (Hot-Carrier) Diodes 810 Varactor (Varicap) Diodes 814 Power Diodes 818 Tunnel Diodes 819 Photodiodes 824 Photoconductive Cells 827 IR Emitters 829 Liquid-Crystal Displays 831 Solar Cells 833 Thermistors 837 810 21 21.13 21.16 pnpn AND OTHER DEVICES Introduction 842 Silicon-Controlled Rectifier 842 Basic Silicon-Controlled Rectifier Operation 842 SCR Characteristics and Ratings 845 SCR Construction and Terminal Identification 847 SCR Applications 848 Silicon-Controlled Switch 852 Gate Turn-Off Switch 854 Light-Activated SCR 855 Shockley Diode 858 DIAC 858 TRIAC 860 Unijunction Transistor 861 Phototransistors 871 Opto-Isolators 873 Programmable Unijunction Transistor 875 842 Contents xi .14 21.1 21.19 19.6 19.9 20.5 19.3 21.7 20.6 21.4 19.1 19.8 21.2 19.4 20.11 21.8 20.10 21.

22 22.4 22.6 22.5 22.1 22.3 22.9 OSCILLOSCOPE AND OTHER MEASURING INSTRUMENTS Introduction 884 Cathode Ray Tube—Theory and Construction 884 Cathode Ray Oscilloscope Operation 885 Voltage Sweep Operation 886 Synchronization and Triggering 889 Multitrace Operation 893 Measurement Using Calibrated CRO Scales 893 Special CRO Features 898 Signal Generators 899 884 APPENDIX A: HYBRID PARAMETERS— CONVERSION EQUATIONS (EXACT AND APPROXIMATE) APPENDIX B: RIPPLE FACTOR AND VOLTAGE CALCULATIONS APPENDIX C: CHARTS AND TABLES APPENDIX D: SOLUTIONS TO SELECTED ODD-NUMBERED PROBLEMS INDEX 902 904 911 913 919 xii Contents .8 22.7 22.2 22.

for keeping together the many detailed aspects of production. CANADA xvii . Calgary. Fuller . Stephen Evanson George Fredericks F D. Austin. CANADA Metropolitan State College. Bocksch Jeffrey Bowe Alfred D. Blountville. Napa. TX The Perkin-Elmer Corporation Charles S. Duane Bailey Joe Baker Jerrold Barrosse Ambrose Barry Arthur Birch Scott Bisland Edward Bloch Gary C. Hartford. CT SEMATECH. Caputi Robert Casiano Alan H. South Bend. We also want to thank Rex Davidson. Napa College. Ontario. Flint. Rockville. CANADA University of Southern California. Muskegon. Ontario. CA Penn State–Ogontz University of North Carolina–Charlotte Hartford State Technical College. Alberta. MI EG&G VACTEC Inc. Los Angeles. Anderson Al Anthony A. WI MicroSim Corporation Hofstra University International Rectifier Corporation Montgomery College. CO Indiana Vocational Technical College. Buerosse Lila Caggiano Mauro J. The comments from these individuals have enabled us to present Electronic Devices and Circuit Theory in this Seventh Edition: Ernest Lee Abbott Phillip D. Editor. MI Bunker Hill Community College. and suggestions. and Linda Ludewig. corrections. Charlestown. Denver.Acknowledgments Our sincerest appreciation must be extended to the instructors who have used the text and sent in comments. MA Waukesha County Technical College. Mott Community College. Production Editor at Prentice Hall. TN Humber College. MD ITT Technical Institute Humber College. UK Northeast State Technical Community College. CA Muskegon Community College. IN Bradford University. Day Mike Durren Dr. Senior Editor. We wish to thank those individuals who have shared their suggestions and evaluations of this text throughout its many editions. Czarapata Mohammad Dabbas John Darlington Lucius B. Pewaukee. at Prentice Hall for their editorial support of the Seventh Edition of this text. Southern Alberta Institute of Technology. Our sincerest thanks to Dave Garza.

WA ITT Technical Institute San Diego Mesa College. McMillan Thomas E. Robert A. DeKalb Technical Institute. Tacoma. Szymanski Parker M. MN L. UT xviii Acknowledgments . OH Greenville Technical College. Kent Donald E. VA DeVry Technical Institute. GA Tektronix Inc. IN Nashville State Technical Institute Hudson Valley Community College University of Western Ontario. GA Motorola Inc. H. Troy. Owens Technical College. Powell E. South Bend. Toledo. NJ PSE&G Nuclear Southern College of Technology. Tabor Peter Tampas Chuck Tinney Katherine L. UK Oakland Community College Southern-Alberta Institute of Technology. OH APPLIED MATERIALS. Beaconside. MI University of Utah Mohawk College of Applied Art & Technology. Bellingham. Clarkston. Marietta. Yunghans Ulrich E. ITT Technical Institute. Greenville. Robert Payne Dr. Walters Larry J. King Charles Lewis Donna Liverman William Mack Robert Martin George T. Saeed A. Texas Instruments Inc. Youngstown. INC. WA Salt Lake Community College. San Diego. Ontario. Salt Lake City. Wales. TX Hartford State Technical College. Usik Domingo Uy Richard J. Hamilton. CT Western Washington University. GA ITT Technical Institute. WA Bismarck State College University of Glamorgan. MI Western Washington University. Ontario. Woodbridge. Ickstadt Jeng-Nan Juang Karen Karger Kenneth E. Macon. Noel Shammas Ken Simpson Eric Sung Donald P. Newman Byron Paul Dr. Irving. Zeisler DeVry Institute of Technology. Houghton. Bellingham. Hartfold. F Rockafellow . Mason William Maxwell Abraham Michelen John MacDougall Donald E. London. Bates Vocational-Technical Institute. FL School of Engineering. UK Stark State College of Technology Computronics Technology Inc. CANADA Southwest State University. Shaikh Dr. Wheeler Julian Wilson Syd R. Alberta. CANADA Miami-Dade Community College. Marshall. SC Michigan Technological University. Wilson Jean Younes Charles E. CANADA Hampton University. CA Mercer University. Hampton. Miami. Calgary. Harrisburg Area Community College Northern Virginia Community College Indiana Vocational Technical College. Grady William Hill Albert L.Phil Golden Joseph Grabinski Thomas K.

In addition to the details of its construction and characteristics. Miniaturization appears to be limited by three factors (each of which will be addressed in this text): the quality of the semiconductor material itself. respectively. It is the simplest of semiconductor devices but plays a very vital role in electronic systems. The ideal diode is a two-terminal device having the symbol and characteristics shown in Figs. The engineer becomes more and more limited in his or her knowledge of the broad range of advances— it is difficult enough simply to stay abreast of the changes in one area of research or development. New designs and systems surface weekly. and the limits of the manufacturing and processing equipment. It no longer seems valid to mention tubes at all or to compare the advantages of one over the other—we are firmly in the solid-state era. it still seems like a few short years ago.1 INTRODUCTION It is now some 50 years since the first transistor was introduced on December 23.1 Ideal diode: (a) symbol. For those of us who experienced the change from glass envelope tubes to the solid-state era. It provides a basis for comparison.p n CHAPTER Semiconductor Diodes 1. having characteristics that closely match those of a simple switch. (b) characteristics. We have also reached a point at which the primary purpose of the container is simply to provide some means of handling the device or system and to provide a mechanism for attachment to the remainder of the network. and it reveals where improvements can still be made. extending from the simple to the very complex. the network design technique.1a and b. It refers to any device or system that has ideal characteristics—perfect in every way. 1947. Complete systems now appear on wafers thousands of times smaller than the single element of earlier networks. It will appear in a range of applications. 1 1. 1 . 1. The term ideal will be used frequently in this text as new devices are introduced. with succeeding editions involving the important decision of how much coverage should be dedicated to tubes and how much to semiconductor devices. Figure 1. The first edition of this text contained heavy coverage of tubes. the very important data and graphs to be found on specification sheets will also be covered to ensure an understanding of the terminology employed and to demonstrate the wealth of information typically available from manufacturers.2 IDEAL DIODE The first electronic device to be introduced is called the diode. The miniaturization that has resulted leaves us to wonder about its limits.

20. 1. Consider the region of negatively applied potential (third quadrant) of Fig. For the majority of the device characteristics that appear in this book.1a. it is relatively simple to determine whether a diode is in the region of conduction or nonconduction simply by noting the direction of the current ID established by an applied voltage. 1.2 are applicable.1a. if the resultant diode current has the same direction as the arrowhead of the diode symbol. therefore. 1. is an open circuit in the region of nonconduction. 1. + VD – Short circuit ID I D (limited by circuit) (a) 0 VD – VD + Open circuit ID = 0 (b) Figure 1. a diode will conduct current in the direction defined by the arrow in the symbol and act like an open circuit to any attempt to establish current in the opposite direction.2 (a) Conduction and (b) nonconduction states of the ideal diode as determined by the applied bias.p n Ideally. RF. as defined by Ohm’s law is RF VF IF 0V 2. the characteristics to the left are pertinent. In review. voltage polarities. One of the important parameters for the diode is the resistance at the point or region of operation. 1. and current directions be defined. . therefore. In essence: The characteristics of an ideal diode are those of a switch that can conduct current in only one direction. is a short circuit for the region of conduction.1b is to the right of the vertical axis. In general. while a reversal in direction would require the use of the characteristics below the axis. RR VR IR 5. while the abscissa (or “x” axis) will be the voltage axis. the conditions depicted in Fig. The ideal diode. 1. If we consider the conduction region defined by the direction of ID and polarity of VD in Fig. we will find that the value of the forward resistance. . If the polarity of the applied voltage is consistent with that shown in Fig.1b. the ordinate (or “y” axis) will be the current axis. the portion of the characteristics to be considered is above the horizontal axis.1b). 1. The ideal diode. 1. mA. the portion of the characteristics to be considered in Fig. . 3. or any positive value 0 (short circuit) where VF is the forward voltage across the diode and IF is the forward current through the diode.3a. For conventional flow (opposite to that of electron flow). If a reverse voltage is applied. If the current through the diode has the direction indicated in Fig. the diode is operating in the conducting region as depicted in Fig. it is critical that the various letter symbols. or any reverse-bias potential 0 mA (open-circuit) where VR is reverse voltage across the diode and IR is reverse current in the diode. If 2 Chapter 1 Semiconductor Diodes . In the description of the elements to follow. .1a (upper-right quadrant of Fig.

1) In fact. the higher the conductivity level.p n the resulting current has the opposite direction. the term resistivity ( . An insulator is a material that offers a very low level of conductivity under pressure from an applied voltage source. the resistivity of a material is measured in -cm or -m. the magnitude of the resistance of the cube of Fig.3b. The prefix semiis normally applied to a range of levels midway between two limits. As we progress through the next few sections. In metric units. therefore. Inversely related to the conductivity of a material is its resistance to the flow of charge. A semiconductor.3 Semiconductor Materials 3 . ID (a) ID ID (b) ID = 0 Figure 1. the primary purpose of this section is to introduce the characteristics of an ideal device for comparison with the characteristics of the commercial variety. That is. 1.3 (a) Conduction and (b) nonconduction states of the ideal diode as determined by the direction of conventional current established by the network.4 is 1 cm2 and the length 1 cm. The term conductor is applied to any material that will support a generous flow of charge when a voltage source of limited magnitude is applied across its terminals. is a material that has a conductivity level somewhere between the extremes of an insulator and a conductor. typical resistivity values are provided for three broad categories of materials. This fact will be helpful to remember as we compare resistivity levels in the discussions to follow. 1. Greek letter rho) is often used when comparing the resistance levels of materials. In Table 1.level? Is the reverse-bias resistance sufficiently large to permit an open-circuit approximation? 1. 1.1. keep the following questions in mind: How close will the forward or “on” resistance of a practical diode compare with the desired 0. the opencircuit equivalent is appropriate.4 into the following equation (derived from the l/A): basic resistance equation R RA l ( )(cm2) ⇒ cm -cm (1. As indicated earlier. as shown in Fig. the lower the resistance level. 1.4 is equal to the magnitude of the resistivity of the material as demonstrated below: R l A (1 cm) (1 cm2) ohms Figure 1. or current. if the area of Fig. In tables. The units of -cm are derived from the substitution of the units for each quantity of Fig. Although you may be familiar with the electrical properties of copper and 1.3 SEMICONDUCTOR MATERIALS The label semiconductor itself provides a hint as to its characteristics.4 Defining the metric units of resistivity.

the periodicity of the structure does not change significantly with the addition of impurities in the doping process.1 the extreme range between the conductor and insulating materials for the 1-cm length (1-cm2 area) of the material. As you are aware. continually repeats itself). is called covalent bonding.e. One complete pattern is called a crystal and the periodic arrangement of the atoms a lattice.000. but germanium is still in modest production. For Ge and Si the crystal has the three-dimensional diamond structure of Fig.5.p n TABLE 1. as shown in Fig. One very important consideration is the fact that they can be manufactured to a very high purity level. Some of the unique qualities of Ge and Si noted above are due to their atomic structure.000). In each case. For semiconductor materials of practical application in the electronics field. A bonding of atoms. they are certainly not the only two semiconductor materials. They are. 1. however. The ability to change the characteristics of the material significantly through this process.000. Further reasons include the fact that their characteristics can be altered significantly through the application of heat or light—an important consideration in the development of heat. strengthened by the sharing of electrons. the proton. Any material composed solely of repeating crystal structures of the same kind is called a single-crystal structure. the neutrons and protons form the nucleus. the germanium atom has 32 orbiting electrons. this singlecrystal feature exists.1 Typical Resistivity Values Conductor 10 6 -cm (copper) Semiconductor 50 -cm (germanium) 50 103 -cm (silicon) Insulator 1012 -cm (mica) Figure 1. Note in Table 1. recent advances have reduced impurity levels in the pure material to 1 part in 10 billion (1 10. 1. mica from your past studies.7 for silicon. Eighteen places separate the placement of the decimal point for one number from the other. As indicated by Fig. 1. are shown in Fig. while silicon has 14 orbiting electrons.” is yet another reason why Ge and Si have received such wide attention. there are 4 electrons in the outermost (valence) shell. In fact. known as “doping. Let us now examine the structure of the atom itself and note how it might affect the electrical characteristics of the material. Both Ge and Si are referred to as tetravalent atoms because they each have four valence electrons.and light-sensitive devices. In the atomic lattice. In a pure germanium or silicon crystal these 4 valence electrons are bonded to 4 adjoining atoms. One might ask if these low impurity levels are really necessary. the atom is composed of three basic particles: the electron. Chapter 1 Semiconductor Diodes 4 . As you will find in the chapters to follow. the two materials that have received the broadest range of interest in the development of semiconductor devices. and the neutron. 1. We are obviously dealing with a whole new spectrum of comparison levels when we deal with the semiconductor medium. the characteristics of the semiconductor materials of germanium (Ge) and silicon (Si) may be relatively new.5 Ge and Si single-crystal structure. The atoms of both materials form a very definite pattern that is periodic in nature (i. Ge and Si have received the attention they have for a number of reasons.6. In recent years the shift has been steadily toward silicon and away from germanium. They certainly are if you consider that the addition of one part impurity (of the proper type) per million in a wafer of silicon material can change that material from a relatively poor conductor to a good conductor of electricity. in addition. germanium and silicon. The potential (ionization potential) required to remove any one of these 4 valence electrons is lower than that required for any other electron in the structure.6a. while the electrons revolve around the nucleus in a fixed orbit. and. The Bohr models of the two most commonly used semiconductors..

1 that the resistivity also differs by a ratio of about 1000 1. As the temperature rises from absolute zero (0 K). The ratio of the number of carriers in germanium to that of silicon is greater than 103 and would indicate that germanium is a better conductor at room temperature. This should be the case.7 atom. of course. since resistivity and conductivity are inversely related. These natural causes include effects such as light energy in the form of photons and thermal energy from the surrounding medium. An increase in temperature of a semiconductor can result in a substantial increase in the number of free electrons in the material.6 Atomic structure: (a) germanium. This may be true. You will probably recall that the resistance of most conductors will increase with temperature. Covalent bonding of the silicon Although the covalent bond will result in a stronger bond between the valence electrons and their parent atom. Semiconductor materials such as Ge and Si that show a reduction in resistance with increase in temperature are said to have a negative temperature coefficient. The free electrons in the material due only to natural causes are referred to as intrinsic carriers.5 1013 free carriers per cubic centimeter. an increasing number of valence electrons absorb sufficient thermal energy to break the covalent bond and contribute to the number of free carriers as described above.3 Semiconductor Materials 5 . it is still possible for the valence electrons to absorb sufficient kinetic energy from natural causes to break the covalent bond and assume the “free” state. Intrinsic materials are those semiconductors that have been carefully refined to reduce the impurities to a very low level—essentially as pure as can be made available through modern technology.5 1010 free carriers in a cubic centimeter of intrinsic silicon material. At room temperature there are approximately 1. with silicon having the larger value. Figure 1. intrinsic germanium material will have approximately 2. This increased number of carriers will increase the conductivity index and result in a lower resistance level. At the same temperature. but both are still considered poor conductors in the intrinsic state. This is due to the fact that the numbers of carriers in a conductor will 1. (b) silicon.p n Figure 1. Note in Table 1. The term free reveals that their motion is quite sensitive to applied electric fields such as established by voltage sources or any difference in potential.

but their vibration pattern about a relatively fixed location will make it increasingly difficult for electrons to pass through. and any electron that has left its parent atom has a higher energy state than any electron in the atomic structure. the higher the energy state. and conductor.) etc.4 ENERGY LEVELS In the isolated atomic structure there are discrete (individual) energy levels associated with each orbiting electron. there is an interaction between atoms that will result in the electrons in a particular orbit of one atom having slightly different energy levels from electrons in the same orbit of an adjoining atom. 1. 1.8b. as shown in Fig. Nucleus (a) Energy Conduction band Energy Conduction band The bands overlap Conduction band Energy Electrons "free" to establish conduction E g > 5 eV Valence electrons bound to the atomic stucture Eg Valence band Valence band Valence band Figure 1.1 eV (Si) E g = 0. Note that there are boundary levels and maximum energy states in which any electron in the atomic lattice can find itself. Each material will.p n not increase significantly with temperature. Recall 6 Chapter 1 Semiconductor Diodes . The more distant the electron from the nucleus. have its own set of permissible energy levels for the electrons in its atomic structure. (b) conduction and valence bands of an insulator. Energy Valance Level (outermost shell) Energy gap Second Level (next inner shell) Energy gap Third Level (etc. As the atoms of a material are brought closer together to form the crystal lattice structure. An increase in temperature therefore results in an increased resistance level and a positive temperature coefficient. 1.67 eV (Ge) E g = 1.41 eV (GaAs) Semiconductor (b) Conductor Between the discrete energy levels are gaps in which no electrons in the isolated atomic structure can appear.8 Energy levels: (a) discrete levels in isolated atomic structures. The net result is an expansion of the discrete levels of possible energy states for the valence electrons to that of bands as shown in Fig. in fact. and there remains a forbidden region between the valence band and the ionization level. semiconductor.8a. Insulator E g = 1.

2) will result in an energy level referred to as one electron volt. 25°C) a large number of valence electrons have acquired sufficient energy to leave the valence band.8b and enter the conduction band. Note for the insulator that the energy gap is typically 5 eV or more. and phosphorus.6 10 10 19 C)(1 V) J (1. at room temperature there are more than enough free carriers to sustain a heavy flow of charge. The charge Q is the charge associated with a single electron. or current. Each will be described in some detail in the following paragraphs. The n-type is created by introducing those impurity elements that have five valence electrons (pentavalent). cross the energy gap defined by Eg in Fig. These impurities.15°C). although only added to perhaps 1 part in 10 million. (1.8b. which severely limits the number of electrons that can enter the conduction band at room temperature. The effect of such impurity elements is indicated in 1. The obviously lower Eg for germanium accounts for the increased number of carriers in that material as compared to silicon at room temperature.1 eV. for germanium 0. A semiconductor material that has been subjected to the doping process is called an extrinsic material. therefore.and p-type materials are formed by adding a predetermined number of impurity atoms into a germanium or silicon base. The unit of measure is appropriate. 1. such as antimony. n-Type Material Both the n. all the valence electrons of semiconductor materials find themselves locked in their outermost shell of the atom with energy levels associated with the valence band of Fig.5 Extrinsic Materials—n. increased carrier density in the conduction band at room temperature! 1. energy states in the forbidden bands will occur which will cause a net reduction in Eg for both semiconductor materials—consequently. The conductor has electrons in the conduction band even at 0 K. and for gallium arsenide 1. There are two extrinsic materials of immeasurable importance to semiconductor device fabrication: n-type and p-type. 1.41 eV.2) as derived from the defining equation for voltage V W/Q. You will note that the energy associated with each electron is measured in electron volts (eV).6 10 19 coulomb.6 1. Substituting the charge of an electron and a potential difference of 1 volt into Eq.67 eV.and p-Type 7 . We will find in Section 1.5 that if certain impurities are added to the intrinsic semiconductor materials.5 EXTRINSIC MATERIALS— n.3) 19 At 0 K or absolute zero ( 273. For silicon Eg is 1. Since energy is also measured in joules and the charge of one electron 1. since W QV eV (1. W and QV 1 eV (1. at room temperature (300 K. However. can alter the band structure sufficiently to totally change the electrical properties of the material.p n that ionization is the mechanism whereby an electron can absorb sufficient energy to break away from the atomic structure and enter the conduction band. Quite obviously.AND p-TYPE The characteristics of semiconductor materials can be altered significantly by the addition of certain impurity atoms into the relatively pure semiconductor material. arsenic.

the ratio (1012/107 105) would indicate that the carrier concentration has increased by a ratio of 100.9 Antimony impurity in n-type material.p n – – Si – – – Si – – – Si – – – – Si – – – – Sb – – – – – Si – Fifth valence electron of antimony – – – – – – Si – – – – Si Antimony (Sb) impurity – – Si – Figure 1. 0. This remaining electron. At room temperature in an intrinsic Si material there is about one free electron for every 1012 atoms (1 to 109 for Ge).000 1. which is unassociated with any particular covalent bond.05 eV (Si). 1. there are a large number of carriers (electrons) in the conduction level and the conductivity of the material increases significantly. – – Fig. 8 Chapter 1 Semiconductor Diodes . an additional fifth electron due to the impurity atom. is relatively free to move within the newly formed n-type material.9 (using antimony as the impurity in a silicon base). Note that a discrete energy level (called the donor level) appears in the forbidden band with an Eg significantly less than that of the intrinsic material.01 eV (Ge) E g as before Valence band Donor energy level Figure 1. It is important to realize that even though a large number of “free” carriers have been established in the n-type material. Since the inserted impurity atom has donated a relatively “free” electron to the structure: Diffused impurities with five valence electrons are called donor atoms. Note that the four covalent bonds are still present. loosely bound to its parent (antimony) atom.10. The effect of this doping process on the relative conductivity can best be described through the use of the energy-band diagram of Fig. however. it is still electrically neutral since ideally the number of positively charged protons in the nuclei is still equal to the number of “free” and orbiting negatively charged electrons in the structure. There is. The result is that at room temperature. 1.10 Effect of donor impurities on the energy band structure. Energy Conduction band E g = 0. Those “free” electrons due to the added impurity sit at this energy level and have less difficulty absorbing a sufficient measure of thermal energy to move into the conduction band at room temperature. If our dosage level were 1 in 10 million (107).

p n p-Type Material The p-type material is formed by doping a pure germanium or silicon crystal with impurity atoms having three valence electrons. Note that there is now an insufficient number of electrons to complete the covalent bonds of the newly formed lattice. Electron versus Hole Flow The effect of the hole on conduction is shown in Fig. There is. a transfer of holes to the left and electrons to the right. Figure 1. The direction to be used in this text is that of conventional flow. 1. therefore. on a base of silicon is indicated in Fig. then a vacancy. The effect of one of these elements. as shown in Fig.12. boron. The elements most frequently used for this purpose are boron. which is indicated by the direction of hole flow. 1. If a valence electron acquires sufficient kinetic energy to break its covalent bond and fills the void created by a hole. 1.11 Boron impurity in p-type material. for the same reasons described for the n-type material.12. Since the resulting vacancy will readily accept a “free” electron: The diffused impurities with three valence electrons are called acceptor atoms.12 Electron versus hole flow. The resulting p-type material is electrically neutral. gallium. will be created in the covalent bond that released the electron.11. and indium. Figure 1. The resulting vacancy is called a hole and is represented by a small circle or positive sign due to the absence of a negative charge. 1.and p-Type 9 .5 Extrinsic Materials—n. or hole.

When the fifth electron of a donor atom leaves the parent atom. The vacancies left behind in the covalent bonding structure represent our very limited supply of holes. the number of free electrons in Ge or Si is due only to those few electrons in the valence band that have acquired sufficient energy from thermal or light sources to break the covalent bond or to the few impurities that could not be removed. The n. therefore. the application of a voltage across its terminals leaves three possibilities: no bias (VD 0 V).and p-type materials were introduced. resulting in a lack of carriers in the region near the junction.13b. The semiconductor diode is formed by simply bringing these materials together (constructed from the same base—Ge or Si).6 SEMICONDUCTOR DIODE In Section 1. For the p-type material the number of holes far outweighs the number of electrons. We will find in the next section that the “joining” of a single n-type material with a p-type material will result in a semiconductor element of considerable importance in electronic systems. 1. (b) p-type material.13a) the electron is called the majority carrier and the hole the minority carrier. 1. For this reason: In an n-type material (Fig. 1. Donor ions Acceptor ions Majority carriers + –– – + – + + – – + + – + – + + – + – – + – + + – – + n-type (a) Minority carrier Majority carriers + – + – – + +– – + + – –+ + + – + + – – + + – + – + – p-type (b) Minority carrier Figure 1. Therefore: In a p-type material the hole is the majority carrier and the electron is the minority carrier. forward bias (VD 0 V). the number of holes has not changed significantly from this intrinsic level. as shown in Fig. 10 Chapter 1 Semiconductor Diodes . Since the diode is a two-terminal device.14.and p-type materials represent the basic building blocks of semiconductor devices. In an n-type material. as shown in Fig. the atom remaining acquires a net positive charge: hence the positive sign in the donor-ion representation. 1. Each is a condition that will result in a response that the user must clearly understand if the device is to be applied effectively. The net result. At the instant the two materials are “joined” the electrons and holes in the region of the junction will combine.13 (a) n-type material.p n Majority and Minority Carriers In the intrinsic state.5 both the n. and reverse bias (VD 0 V). the negative sign appears in the acceptor ion. This region of uncovered positive and negative ions is called the depletion region due to the depletion of carriers in this region. using techniques to be described in Chapter 20. is that the number of electrons far outweighs the number of holes. For similar reasons.

the same type of discussion can be applied to the majority carriers (holes) of the p-type material. In summary. For the purposes of future discussions we shall assume that all the minority carriers of the n-type material that find themselves in the depletion region due to their random motion will pass directly into the p-type material.6 Semiconductor Diode 11 . 1. This carrier flow has been indicated in Fig. No Applied Bias (VD 0 V) Under no-bias (no applied voltage) conditions. The closer the minority carrier is to the junction. Again.14 p-n junction with no external bias. The length of the vector representing hole flow has been drawn longer than that for electron flow to demonstrate that the magnitude of each need not be the same for cancellation and that the doping levels for each material may result in an unequal carrier flow of holes and electrons.14 for the minority carriers of each material. Similar discussion can be applied to the minority carriers (electrons) of the p-type material. This cancellation of vectors has been indicated by crossed lines.14. the number of majority carriers is so large in the n-type material that there will invariably be a small number of majority carriers with sufficient kinetic energy to pass through the depletion region into the p-type material. any minority carriers (holes) in the n-type material that find themselves within the depletion region will pass directly into the p-type material. 1. 1. therefore: In the absence of an applied bias voltage. 1. The resulting flow due to the majority carriers is also shown in Fig.14 will reveal that the relative magnitudes of the flow vectors are such that the net flow in either direction is zero.p n Figure 1. However. the net flow of charge in any one direction for a semiconductor diode is zero. the greater the attraction for the layer of negative ions and the less the opposition of the positive ions in the depletion region of the n-type material. A close examination of Fig. The majority carriers (electrons) of the n-type material must overcome the attractive forces of the layer of positive ions in the n-type material and the shield of negative ions in the p-type material to migrate into the area beyond the depletion region of the p-type material.

that find themselves entering the depletion region will not change. As indicated.16. For future reference.and p-type regions. Figure 1.18.14 with no applied voltage. in particular. The number of minority carriers. This widening of the depletion region will establish too great a barrier for the majority carriers to overcome.17 for the diode symbol and p-n junction. 0 V) If an external potential of V volts is applied across the p-n junction such that the positive terminal is connected to the n-type material and the negative terminal is connected to the p-type material as shown in Fig. that the direction of Is is against the arrow of the symbol. is a widening of the depletion region. the current in any direction is 0 mA. The net effect.p n The symbol for a diode is repeated in Fig. 1. The term saturation comes from the fact that it reaches its maximum level quickly and does not change significantly with increase in the reverse-bias potential. 1. In fact. 1.15 with the associated n. resulting in minority-carrier flow vectors of the same magnitude indicated in Fig. therefore: A semiconductor diode is forward-biased when the association p-type and positive and n-type and negative has been established. 1. for VD 0 V. Forward-Bias Condition (VD 0 V) A forward-bias or “on” condition is established by applying the positive potential to the p-type material and the negative potential to the n-type material as shown in Fig.15 No-bias conditions for a semiconductor diode. in recent years its level is typically in the nanoampere range for silicon devices and in the low-microampere range for germanium. as shown on the diode characteristics of Fig. Note. effectively reducing the majority carrier flow to zero as shown in Fig. 12 Chapter 1 Semiconductor Diodes .16 Reverse-biased p-n junction. Note that the arrow is associated with the p-type component and the bar with the n-type region. however. The reverse-biased conditions are depicted in Fig. For similar reasons. The reverse saturation current is seldom more than a few microamperes except for high-power devices. 1. Note also that the negative potential is connected to the p-type material and the positive potential to the n-type material—the difference in underlined letters for each region revealing a reverse-bias condition. the number of uncovered positive ions in the depletion region of the n-type material will increase due to the large number of “free” electrons drawn to the positive potential of the applied voltage. the number of uncovered negative ions will increase in the p-type material.17 Reverse-bias conditions for a semiconductor diode. The current that exists under reverse-bias conditions is called the reverse saturation current and is represented by Is. 1.16. Reverse-Bias Condition (VD Figure 1. 1. Figure 1. therefore.19 for VD 0 V.

1 µ uA – 0.2 µ uA – 0.18. An electron of the n-type material now “sees” a reduced barrier at the junction due to the reduced depletion region and a strong attraction for the positive potential applied to the p-type material. 1. The resulting minority-carrier flow of electrons from the p-type material to the n-type material (and of holes from the n-type material to the p-type material) has not changed in magnitude (since the conduction level is controlled primarily by the limited number of impurities in the material). reID (mA) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Defined polarity and direction for graph VD ID Forward-bias region (V > 0 V.3 – 0. The application of a forward-bias potential VD will “pressure” electrons in the n-type material and holes in the p-type material to recombine with the ions near the boundary and reduce the width of the depletion region as shown in Fig. (1.3 µ uA – 0. but the reduction in the width of the depletion region has resulted in a heavy majority flow across the junction.5 0. 1.19 Silicon semiconductor diode characteristics.7 1 V D (V) Reverse-bias region (VD < 0 V.6 Semiconductor Diode 13 . I D > 0 mA) VD I Eq.4) Actual commercially available unit + – Is –40 –30 –20 –10 1 0 0.4 µ uA 0. ID = 0 mA) Figure 1. ID = –Is ) No-bias (VD = 0 V.p n Figure 1. As the applied bias increases in magnitude the depletion region will continue to decrease in width until a flood of electrons can pass through the junction.18 Forward-biased p-n junction.

this difference will decrease and the actual characteristics approach those of Eq.4) is provided in Fig. For VD the scale for positive values is in tenths of volts and for negative values the scale is in tens of volts. there is a point where the application of too negative a voltage will result in a sharp change Chapter 1 Semiconductor Diodes 14 . therefore.and reverse-bias regions: ID where Is k Is(ekVD/TK 1) (1. (1.19. Eq.19 that the commercially available unit has characteristics that are shifted to the right by a few tenths of a volt.19 can easily be described: ID IsekVD/TK Is For positive values of VD the first term of the equation above will grow very quickly and overpower the effect of the second term. The result is that for positive values of VD.19. Note in Fig. 1. If we expand Eq. 1.19 is in tens of volts in the negative region. Initially. Eq. Fortunately.19. 1. It is important to note the change in scale for the vertical and horizontal axes. (1. In time.20. 1.19 is measured in milliamperes (although some semiconductor diodes will have a vertical scale measured in amperes) and the horizontal scale in the forward-bias region has a maximum of 1 V. which is simply the horizontal line of Fig. 1. Note also. (1. At VD 0 V. Before leaving the subject of the forward-bias state the conditions for conduction (the “on” state) are repeated in Fig. This is due to the internal “body” resistance and external “contact” resistance of a diode. 1. Typically. 1.20 Plot of e x.21 Forward-bias conditions for a semiconductor diode. however.4).p n sulting in an exponential rise in current as shown in the forward-bias region of the characteristics of Fig.4) does appear somewhat complex and may develop an unwarranted fear that it will be applied for all the diode applications to follow. 1. how quickly the current rises beyond the knee of the curve. resulting in ID break in the characteristics at VD 0 V is simply due to the dramatic change in scale from mA to A. Each contributes to an additional voltage at the same current level as determined by Ohm’s law (V IR).21 with the required biasing polarities and the resulting direction of majority-carrier flow. (1.4) into the following form. the contributing component for each region of Fig. 1. a number of approximations will be made in a later section that will negate the need to apply Eq. (1.4) and provide a solution with a minimum of mathematical difficulty. For positive values of ID the scale is in milliamperes and the current scale below the axis is in microamperes (or possibly nanoamperes).600/ with 1 for Ge of diode current (at or below the knee of the curve) and and Si for higher levels of diode current (in the rapidly increasing section of the curve) TC 273° A plot of Eq. Zener Region Figure 1. For negative values of VD the first term will quickly drop off beIs. Note that the vertical scale of Fig. Even though the scale of Fig. Figure 1. ID will be positive and grow as the function y ex appearing in Fig. The low Is.4) becomes ID Is(e0 1) Is(1 1) 0 mA as appearing in Fig. It can be demonstrated through the use of solid-state physics that the general characteristics of a semiconductor diode can be defined by the following equation for the forward. (1. as production methods improve.4) TK reverse saturation current 1 for Ge and 2 for Si for relatively low levels 11. Note in particular how the direction of conduction matches the arrow in the symbol (as revealed for the ideal diode). the voltage across a forward-biased diode will be less than 1 V.19. 1.

Silicon can be used for applications in which the temperature may rise to about 200°C (400°F). called Zener breakdown. The maximum reverse-bias potential that can be applied before entering the Zener region is called the peak inverse voltage (referred to simply as the PIV rating) or the peak reverse voltage (denoted by PRV rating). is the higher 1. their velocity and associated kinetic energy (WK 1 mv2) will be 2 sufficient to release additional carriers through collisions with otherwise stable atomic structures. however. as compared to germanium. 1. as indicated in Fig. The avalanche region (VZ) can be brought closer to the vertical axis by increasing the doping levels in the p.22. 1. Diodes are also connected in parallel to increase the current-carrying capacity. However. in general. PIV ratings for silicon can be in the neighborhood of 1000 V. whereas the maximum value for germanium is closer to 400 V. It occurs because there is a strong electric field in the region of the junction that can disrupt the bonding forces within the atom and “generate” carriers. a number of diodes of the same characteristics can be connected in series. They are described in detail in Section 1. in the characteristics. such as 5 V. As the voltage across the diode increases in the reverse-bias region.and n-type materials.23. higher PIV and current rating and wider temperature ranges than germanium diodes. the velocity of the minority carriers responsible for the reverse saturation current Is will also increase. The current increases at a very rapid rate in a direction opposite to that of the positive voltage region. this sharp change in the characteristic at any level is called the Zener region and diodes employing this unique portion of the characteristic of a p-n junction are called Zener diodes. an ionization process will result whereby valence electrons absorb sufficient energy to leave the parent atom. another mechanism. Although the Zener breakdown mechanism is a significant contributor only at lower levels of VZ. as shown in Fig. as VZ decreases to very low levels. If an application requires a PIV rating greater than that of a single unit.22 Zener region. The Zener region of the semiconductor diode described must be avoided if the response of a system is not to be completely altered by the sharp change in characteristics in this reverse-voltage region. That is.6 Semiconductor Diode 15 .p n Figure 1. The reverse-bias potential that results in this dramatic change in characteristics is called the Zener potential and is given the symbol VZ. Silicon versus Germanium Silicon diodes have. These additional carriers can then aid the ionization process to the point where a high avalanche current is established and the avalanche breakdown region determined. Eventually.14. whereas germanium has a much lower maximum rating (100°C). will contribute to the sharp change in the characteristic. The disadvantage of silicon.

24. The potential at which this rise occurs is commonly referred to as the offset.” In review: VT VT 0.3 (Ge) Obviously. such as output voltage (Vo) and forward voltage (VF). the closer the upward swing is to the vertical axis.3 V for germanium diodes when rounded off to the nearest tenths.7 (Si) 0. This factor plays a part in determining the shape of the curve only at very low current levels. However. This is evidenced by the similarities in the curves once the offset potential is reached. Once the curve starts its vertical rise.p n Figure 1. 1. to ensure a minimum of confusion with other terms. It has been found experimentally that: The reverse saturation current Is will just about double in magnitude for every 10°C increase in temperature. 16 Chapter 1 Semiconductor Diodes . The increased offset for silicon is due primarily to the factor in Eq. (1. the other characteristics of silicon as compared to germanium still make it the choice in the majority of commercially available units. Temperature Effects Temperature can have a marked effect on the characteristics of a silicon semiconductor diode as witnessed by a typical silicon diode in Fig.7 V for commercially available silicon diodes and 0. the more “ideal” the device. the first letter of a term that describes a particular quantity is used in the notation for that quantity. threshold. or firing potential.23 Comparison of Si and Ge semiconductor diodes. the factor drops to 1 (the continuous value for germanium).4). from the word “threshold. the notation VT has been adopted for this book. Frequently. forward-bias voltage required to reach the region of upward swing. However. It is typically of the order of magnitude of 0.

It is therefore paramount that their determination be clearly understood. Fundamentally. Typical values of Is for silicon are much lower than that of germanium for similar power and current levels as shown in Fig. Simply increase the level of Is in Eq.7 Resistance Levels 17 . The increasing levels of Is with temperature account for the lower levels of threshold voltage.24.7 RESISTANCE LEVELS As the operating point of a diode moves from one region to another the resistance of the diode will also change due to the nonlinear shape of the characteristic curve. Current levels of this magnitude in the reverse-bias region would certainly question our desired open-circuit condition in the reverse-bias region.23. the level of TK also will be increasing in the same equation.1 mA at a temperature of 100°C. the open-circuit equivalent in the reversebias region is better realized at any temperature with silicon than with germanium. 1. as shown in Fig. The result is that even at high temperatures the levels of Is for silicon diodes do not reach the same high levels obtained for germanium—a very important reason that silicon devices enjoy a significantly higher level of development and utilization in design.” but we will find when we review the specifications sheets that temperatures beyond the normal operating range can have a very detrimental effect on the diode’s maximum power and current levels. but the increasing level of Is will overpower the smaller percent change in TK. In the reverse-bias region the breakdown voltage is increasing with temperature. As the temperature increases the forward characteristics are actually becoming more “ideal.24 Variation in diode characteristics with temperature change. 1.4) and note the earlier rise in diode current. 1. It will be demonstrated in the next few paragraphs that the type of applied voltage or signal will define the resistance level of interest. but note the undesirable increase in reverse saturation current.p n Figure 1. Of course. 1. Three different levels will be introduced in this section that will appear again as we examine other devices. (1. It is not uncommon for a germanium diode with an Is in the order of 1 or 2 A at 25°C to have a leakage current of 100 A 0.

5) The dc resistance levels at the knee and below will be greater than the resistance levels obtained for the vertical rise section of the characteristics.25 and applying the following equation: RD VD ID (1. In general.5 V 2 mA 250 . therefore. The resistance of the diode at the operating point can be found simply by finding the corresponding levels of VD and ID as shown in Fig. Since ohmmeters typically employ a relatively constant-current source. EXAMPLE 1. the lower the current through a diode the higher the dc resistance level.26 Example 1. Figure 1.p n DC or Static Resistance The application of a dc voltage to a circuit containing a semiconductor diode will result in an operating point on the characteristic curve that will not change with time. the resistance determined will be at a preset current level (typically.5 V (from the curve) and RD 18 Chapter 1 Semiconductor Diodes VD ID 0. 1. VD 0. a few milliamperes). The resistance levels in the reverse-bias region will naturally be quite high.1 Determine the dc resistance levels for the diode of Fig.1 Solution (a) At ID 2 mA.25 Determining the dc resistance of a diode at a particular operating point.26 at (a) ID 2 mA (b) ID 20 mA 10 V (c) VD Figure 1. 1.

7 Resistance Levels Figure 1. 1. the point of operation would be the Q-point appearing on Fig. (1. 1. 19 . VD 0. 1. therefore.27. which means “still or unvarying.28 Determining the ac resistance at a Q-point. If a sinusoidal rather than dc input is applied. The ac resistance in the vertical-rise region of the characteristic is therefore quite small.5 and Example 1.8 V 20 mA 40 (c) At VD 10 V. The varying input will move the instantaneous operating point up and down a region of the characteristics and thus defines a specific change in current and voltage as shown in Fig. the lower the Q-point of operation (smaller current or lower voltage) the higher the ac resistance.6) The steeper the slope. The designation Q-point is derived from the word quiescent.27 Defining the dynamic or ac resistance. the less the value of Vd for the same change in Id and the less the resistance.1 that the dc resistance of a diode is independent of the shape of the characteristic in the region surrounding the point of interest.8 V (from the curve) and RD VD ID VD ID 0. With no applied varying signal. In general. 1. the situation will change completely. In equation form.p n (b) At ID 20 mA.28 will define a particular change in voltage and current that can be used to determine the ac or dynamic resistance for this region of the diode characteristics. 1. AC or Dynamic Resistance It is obvious from Eq. A straight line drawn tangent to the curve through the Q-point as shown in Fig. ID Is RD 1 A (from the curve) and 10 V 1 A 10 M clearly supporting some of the earlier comments regarding the dc resistance levels of a diode. while the ac resistance is much higher at low current levels.27 determined by the applied dc levels. An effort should be made to keep the change in voltage and current as small as possible and equidistant to either side of the Q-point. rd Vd Id where signifies a finite change in the quantity.” Figure 1.

6 0.11 V (b) For ID 25 mA.78 V 10 mA 0.p n EXAMPLE 1.76 V 0 mA 0.1 0. I D (mA) 30 25 ∆ Id 20 ∆Vd 15 10 5 4 2 0 ∆ Id 0. the tangent line at ID 25 mA was drawn as shown on the figure and a swing of 5 mA above and below the specified diode current was chosen.4 0. VD 0.76 V.5 0.8 V.65 V 4 mA 0. the tangent line at ID 2 mA was drawn as shown in the figure and a swing of 2 mA above and below the specified diode current was chosen. and at ID 0 mA. 1. The resulting changes in current and voltage are Id and and the ac resistance: rd Vd Id 0. At ID 4 mA. and at ID 20 mA.3 0. (b) Determine the ac resistance at ID 25 mA.7 0.2 For the characteristics of Fig.02 V Vd 0.2 Solution (a) For ID 2 mA.8 V Vd Id 20 mA 0.02 V 10 mA 2 .11 V 4 mA 27.29 Example 1.9 ∆Vd 1 VD (V) Figure 1.29: (a) Determine the ac resistance at ID 2 mA. VD 0. At ID 30 mA. (c) Compare the results of parts (a) and (b) to the dc resistances at each current level. VD 0. VD 0.2 0.8 0.5 Vd 4 mA 0.65 V.78 V. The resulting changes in current and voltage are Id and and the ac resistance is rd 20 Chapter 1 Semiconductor Diodes 30 mA 0.

but there is a basic definition in differential calculus which states: The derivative of a function at a point is equal to the slope of the tangent line drawn at that point. we will have an equation for the dynamic or ac resistance in that region.Si 1. VD 0. taking the derivative of Eq. VD ID 0.7 Resistance Levels 21 . 1.79 V 25 mA 31. Equation (1. as defined by Fig. we 11. ID vertical slope section of the characteristics and dID dVD Substituting obtain k ID TK 1 for Ge and Si in the vertical-rise section of the characteristics. VD 0.7 V and RD VD ID 0.79 V and RD which far exceeds the rd of 2 . For ID 25 mA. TK so that and k TK dID dVD 11. That is.4) with respect to the applied bias will result in d (ID) dVD and dID dVD d [Is(ekVD /TK dV k (ID TK Is) Is in the 1)] following a few basic maneuvers of differential calculus. In general.600 298 38. (1.p n (c) For ID 2 mA. If we find the derivative of the general equation (1.5 .93 k and at room temperature.026 ID V/I) gives us 26 mV ID (1.600 11. essentially finding the derivative of the function at the Q-point of operation.7 V 2 mA 350 which far exceeds the rd of 27. therefore.7) Ge.93ID Flipping the result to define a resistance ratio (R dVD dID or rd 0.6).600 TC 273° 273° 298° 11.62 We have found the dynamic resistance graphically.600 1 25° 38.4) for the semiconductor diode with respect to the applied forward bias and then invert the result. is.28.

The resistance r d.2 the ac resistance at 25 mA was calculated to be 2 . In reality.7) becomes inappropriate. (1. For Example 1. These additional resistance levels can be included in Eq. (1. general-purpose diodes. however.7) but multiplying by a factor of 2 for this region (in the knee of the curve 2). tained must be multiplied by a factor of 2.7) is accurate only for values of ID in the vertical-rise 2 (silicon) and the value of rd obsection of the curve.6) is sufficiently high to permit the open-circuit approximation. At high levels of current the level of rB may approach that of rd.7 and the resistance rB just introduced. There is no need to have the characteristics available or to worry about sketching tangent lines as defined by Eq.8) The factor rB can range from typically 0. For Example 1. we have rd 26 mV ID 26 mV 25 mA 1. All the resistance levels determined thus far have been defined by the p-n junction and do not include the resistance of the semiconductor material itself (called body resistance) and the resistance introduced by the connection between the semiconductor material and the external metallic conductor (called contact resistance).04 The difference of about 1 could be treated as the contribution of rB.7) by adding resistance denoted by rB as appearing in Eq. Eq. Using Eq.7) must be clearly understood.2 the ac resistance at 2 mA was calculated to be 27. the resistance associated with the device for this region is called the average ac resistance.6). rd 2 26 mV ID 2 26 mV 2 mA 2(13 ) 26 The difference of 1. Average AC Resistance If the input signal is sufficiently large to produce a broad swing such as indicated in Fig.p n The significance of Eq.5 could be treated as the contribution due to rB. but since there will frequently be other resistive elements of a much larger magnitude in series with the diode we will assume in this book that the ac resistance is determined solely by rd and the impact of rB will be ignored unless otherwise noted. 1. At low levels of diode current the factor rB is normally small enough compared to rd to permit ignoring its impact on the ac diode resistance. includes the dynamic resistance defined by Eq. therefore. the resistance deter22 Chapter 1 Semiconductor Diodes .7).1 for high-power devices to 2 for some low-power. (1. by definition. Technological improvements of recent years suggest that the level of rB will continue to decrease in magnitude and eventually become a factor that can certainly be ignored in comparison to rd. (1.8). It implies that the dynamic resistance can be found simply by substituting the quiescent value of the diode current into the equation. (1. In the reverse-bias region we will assume that the change in current along the Is line is nil from 0 V to the Zener region and the resulting ac resistance using Eq. It is important to keep in mind. Using Eq. 1. determining rd to a high degree of accuracy from a characteristic curve using Eq. (1.30. For lesser values of ID.5 . The discussion above has centered solely on the forward-bias region. (1. (1. (1. For small values of ID below the knee of the curve. that Eq. The average ac resistance is. rd 26 mV ID rB ohms (1. (1.6) is a difficult process at best and the results have to be treated with a grain of salt.

3 0.30).30.65 V 0. The fact that one resistance level can be used for such a wide range of the characteristics will prove quite useful in the definition of equivalent circuits for a diode in a later section. If the ac resistance (rd) were determined at ID 2 mA its value would be more than 5 .075 V 5 Vd Id (1. Equation (1. and if determined at 17 mA it would be less.7 Resistance Levels 23 . the lower the level of currents used to determine the average resistance the higher the resistance level. to pt.4 0.9) pt. mined by a straight line drawn between the two intersections established by the maximum and minimum values of input voltage. 1.30 Determining the average ac resistance between indicated limits.725 V Vd Id 2 mA 0. the content of this section is the foundation for a number of resistance calculations to be performed in later sections and chapters. As indicated earlier.p n I D (mA) 20 15 ∆ Id 10 5 0 0. Id and with Vd rav 17 mA 0.9 ∆Vd 1 VD (V) Figure 1. 1. As with the dc and ac resistance levels. 1.075 V 15 mA 15 mA 0.2 0.7 0.2 was developed to reinforce the important conclusions of the last few pages and to emphasize the differences among the various resistance levels. Summary Table Table 1.9) has defined a value that is considered the average of the ac values from 2 to 17 mA.8 0. rav For the situation indicated by Fig. In equation form (note Fig.5 0.1 0.6 0. In between the ac resistance would make the transition from the high value at 2 mA to the lower value at 17 mA.

7 is the resistance level appearing in the equivalent circuit of Fig. as shown in Fig. In essence. 1. and a reverse-bias condition will re24 Chapter 1 Semiconductor Diodes . the device symbol can be removed from a schematic and the equivalent circuit inserted in its place without severely affecting the actual behavior of the system.8 DIODE EQUIVALENT CIRCUITS An equivalent circuit is a combination of elements properly chosen to best represent the actual terminal characteristics of a device.p n TABLE 1. or such in a particular operating region. 1. system. Defined by a straight line between limits of operation 1. to pt. It should be obvious from Fig. the resulting segments are sufficiently close to the actual curve to establish an equivalent circuit that will provide an excellent first approximation to the actual behavior of the device. In other words.31 that the straight-line segments do not result in an exact duplication of the actual characteristics. 1.2 Resistance Levels Type Equation Special Characteristics Graphical Determination DC or static RD VD ID Defined as a point on the characteristics AC or dynamic rd Vd Id 26 mV ID Defined by a tangent line at the Q-point Average ac rav Vd Id pt. Piecewise-Linear Equivalent Circuit One technique for obtaining an equivalent circuit for a diode is to approximate the characteristics of the device by straight-line segments. it defines the resistance level of the device when it is in the “on” state. especially in the knee region.32 next to the actual device. However. once the equivalent circuit is defined. The result is often a network that can be solved using traditional circuit analysis techniques. For the sloping section of the equivalence the average ac resistance as introduced in Section 1. The resulting equivalent circuit is naturally called the piecewise-linear equivalent circuit.31. The ideal diode is included to establish that there is only one direction of conduction through the device.

Keep in mind. to pt. For instance. however. Since a silicon semiconductor diode does not reach the conduction state until VD reaches 0. a battery VT opposing the conduction direction must appear in the equivalent circuit as shown in Fig. The battery simply specifies that the voltage across the device must be greater than the threshold battery voltage before conduction through the device in the direction dictated by the ideal diode can be established. sult in the open-circuit state for the device.1 V 10 mA 10 as obtained for Fig.8 V. if IF 10 mA (a forward conduction current for the diode) at VD 0. + + ID VD VD VT 0. 1.7 V 0 mA 0.31). If a voltmeter is placed across an isolated diode on the top of a lab bench.8 V 10 mA 0.32. a reading of 0.7 V is required before the characteristics rise and rav Vd Id pt. 1.9). that VT in the equivalent circuit is not an independent voltage source.30.31 Defining the piecewise-linear equivalent circuit using straight-line segments to approximate the characteristic curve. The removal of rav from the equivalent 1.32 Components of the piecewise-linear equivalent circuit.p n Figure 1. The approximate level of rav can usually be determined from a specified operating point on the specification sheet (to be discussed in Section 1.7 V r av 10 Ω – Ideal diode – ID Figure 1.7 V with a forward bias (as shown in Fig. The battery simply represents the horizontal offset of the characteristics that must be exceeded to establish conduction. for a silicon semiconductor diode.8 Diode Equivalent Circut 25 . Simplified Equivalent Circuit For most applications. When conduction is established the resistance of the diode will be the specified value of rav. the resistance rav is sufficiently small to be ignored in comparison to the other elements of the network.7 V will not be obtained. 1. we know for silicon that a shift of 0. 0.

The reduced equivalent circuit appears in the same figure. 1. In fact. system. In industry a popular substitution for the phrase “diode equivalent circuit” is diode model—a model by definition being a representation of an existing device.7 V V D VD VT = 0. 1. In Chapter 2 we will see that this approximation is often made without a serious loss in accuracy.33 Simplified equivalent circuit for the silicon semiconductor diode. It states that a forward-biased silicon diode in an electronic system under dc conditions has a drop of 0.7 V across it in the conduction state at any level of diode current (within rated values. Ideal Equivalent Circuit Now that rav has been removed from the equivalent circuit let us take it a step further and establish that a 0.7-V level can often be ignored in comparison to the applied voltage level. Figure 1. Indeed. In this case the equivalent circuit will be reduced to that of an ideal diode as shown in Fig. the diode models employed for the range of circuit parameters and applications are provided in Table 1. this approximation is frequently employed in semiconductor circuit analysis as demonstrated in Chapter 2. 26 Chapter 1 Semiconductor Diodes .33. circuit is the same as implying that the characteristics of the diode appear as shown in Fig. of course).p n ID + r av = 0 Ω ID 0 V T = 0.34 with its characteristics.7 V – Ideal diode Figure 1. Each will be investigated in greater detail in Chapter 2. and so on. There are always exceptions to the general rule.3 with their piecewise-linear characteristics. this substitute terminology will be used almost exclusively in the chapters to follow. object.34 Ideal diode and its characteristics. Summary Table For clarity. but it is fairly safe to say that the simplified equivalent model will be employed most frequently in the analysis of electronic systems while the ideal diode is frequently applied in the analysis of power supply systems where larger voltages are encountered.

and so on. switching time.9 DIODE SPECIFICATION SHEETS Data on specific semiconductor devices are normally provided by the manufacturer in one of two forms. tables. such as frequency range. it is a very brief description limited to perhaps one page.3 Diode Equivalent Circuits (Models) Type Conditions Model Characteristics Piecewise-linear model Simplified model Rnetwork rav Ideal device Rnetwork Enetwork rav VT 1. there are specific pieces of data that must be included for proper utilization of the device. Capacitance levels (as defined in Section 1. the significance of the data will usually be self-apparent. it is understood to be equal to the following product: PDmax VD ID (1. They include: 1. The reverse-voltage rating [PIV or PRV or V(BR). The maximum forward current IF (at a specified temperature) 3.10) 7. thermal resistance levels. 1. noise level. The reverse saturation current IR (at a specified voltage and temperature) 4.10) where ID and VD are the diode current and voltage at a particular point of operation.11) 8. Most frequently. Operating temperature range Depending on the type of diode being considered. In either case. The maximum power dissipation level at a particular temperature 6. additional data may also be provided. it is a thorough examination of the characteristics using graphs. and peak repetitive values.p n TABLE 1. For the application in mind. where BR comes from the term “breakdown” (at a specified temperature)] 5. If the maximum power or dissipation rating is also provided. The forward voltage VF (at a specified current and temperature) 2.9 Diode Specification Sheets 27 . Reverse recovery time trr (as defined in Section 1. Otherwise. artwork.

Pdissipated (0. low-leakage diode.35 Electrical characteristics of a high-voltage. That is. (1.p n If we apply the simplified model for a particular application (a common occurrence).7 V)ID (1. 28 Chapter 1 Semiconductor Diodes .11) Figure 1.7 V for a silicon diode in Eq.10) and determine the resulting power dissipation for comparison against the maximum power rating. we can substitute VD VT 0.

36 Terminal characteristics of a high-voltage diode. This example would represent the expanded list of data and characteristics.35 and 1.36.p n An exact copy of the data provided for a high-voltage/low-leakage diode appears in Figs.9 Diode Specification Sheets 29 . 1. Figure 1. The term rectifier is applied to a diode when it is frequently used in a rectification process to be described in Chapter 2. 1.

A half-wave-rectified signal (described in Section 2. The maximum power rating decreases at a rate of 3.7 V.36. C: Maximum power dissipation level PD VDID 500 mW. Average rectified current. 1.8) has an average value defined by Iav 0.33 mW per degree increase in temperature above room temperature (25°C). G: At VR 20 V and a typical operating temperature IR 500 nA 0. as clearly indicated by the power derating curve of Fig. This is the maximum instantaneous value of repetitive forward current. I: The reverse recovery time is 3 s for the list of operating conditions. 30 Chapter 1 Semiconductor Diodes . however. Note in this case how the upper limits surround 0. 2. D: Maximum continuous forward current IFmax 500 mA (note IF versus temperature in Fig. This rating defines the maximum value and the time interval for such surges in current level. E: Range of values of VF at IF 200 mA.5 A. B: Temperature characteristics as indicated. In the figure below we find that the reverse saturation current does change slightly with increasing levels of VR but remains at less than 1 nA at room temperature up to VR 125 V. The average rectified current. 3. F: Range of values of VF at IF 1. and peak forward surge current as they appear on the specification sheet are defined as follows: 1. The average current rating is lower than the continuous or peak repetitive forward currents because a half-wave current waveform will have instantaneous values much higher than the average value. peak repetitive forward current.7 V for both devices.36). 1. its level can be higher than the continuous level. there will be very high currents through the device for very brief intervals of time (that are not repetitive). Note the use of the Celsius scale and the wide range of utilization [recall that 32°F 0°C freezing (H2O) and 212°F 100°C boiling (H2O)]. malfunctions.p n Specific areas of the specification sheet have been highlighted in blue with a letter identification corresponding with the following description: A: The minimum reverse-bias voltage (PIVs) for a diode at a specified reverse saturation current.005 A. As noted in the adjoining figure. On occasion during turn-on. In the top right figure note how the capacitance decreases with increase in reversebias voltage.2 should help with the reading of the graphs.5 V to over 1 V as IF increased from 10 A to over 100 mA. while at a higher reverse voltage IR drops to 5 nA 0. A brief investigation of Section 11. note how quickly the reverse saturation current increases with increase in temperature (as forecasted earlier). H: The capacitance level between terminals is about 8 pF for the diode at VR VD 0 V (no-bias) and an applied frequency of 1 MHz.36 employ a log scale.318Ipeak. A number of the curves of Fig.0 mA. Note that since it is at this level for a brief period of time. Peak repetitive forward current. and in the figure below note that the ac resistance (rd) is only about 1 at 100 mA and increases to 100 at currents less than 1 mA (as expected from the discussion of earlier sections). Peak forward surge current. Note that it exceeds VT 0. and so on. Note in the top left figure how VF increased from about 0. 1.

In the p-n semiconductor diode. The fact that the capacitance is dependent on the applied reverse-bias potential has application in a number of electronic systems. and the resulting time constant ( is very important in high-speed applications. In fact.10 Transition and Diffusion Capacitance 31 . Most shunt capacitive effects that can be ignored at lower frequencies because the reactance XC 1/2 f C is very large (open-circuit equivalent). however.37 Transition and diffusion capacitance versus applied bias for a silicon diode. 1. does not become excessive. in Chapter 20 a diode will be introduced whose operation is wholly dependent on this phenomenon. as shown in Fig. increased levels of current result in reduced levels of associated reRC ). In the reverse-bias region we have the transition. Both types of capacitance are present in the forward. XC will become sufficiently small due to the high value of f to introduce a low-reactance “shorting” path. the “friendlier” they will become. Recall that the basic equation for the capacitance of a parallel-plate capacitor is A/d. 1. Since the depletion width (d) will increase with increased reverse-bias potential. it is overshadowed by a capacitance effect directly dependent on the rate at which charge is injected into the regions just outside the depletion region.5 Figure 1.or depletion-region capacitance (CT). However.37. This. the resulting transition capacitance will decrease. In the reverse-bias region there is a depletion region (free of carriers) that behaves essentially like an insulator between the layers of opposite charge. while in the forward-bias region we have the diffusion (CD ) or storage capacitance.10 TRANSITION AND DIFFUSION CAPACITANCE Electronic devices are inherently sensitive to very high frequencies. 1. especially when the impact of each parameter is clearly understood for the application under investigation. The result is that increased levels of current will result in increased levels of diffusion capacitance. Although the effect described above will also be present in the forward-bias region. where is the permittivity of the dielectric (insulator) between defined by C the plates of area A separated by a distance d.and reverse-bias regions. cannot be ignored at very high frequencies. but one so outweighs the other in each region that we consider the effects of only one in each region.25 0.p n The more one is exposed to specification sheets. there are two capacitive effects to be considered. C (pF) 15 10 C Reverse-bias (C T) 5 C Forward-bias (C D ) (V) –25 –20 –15 –10 –5 0 0. which sistance (to be demonstrated shortly).

as shown in Fig. One such quantity that has not been considered yet is the reverse recovery time.41. 1.p n The capacitive effects described above are represented by a capacitor in parallel with the ideal diode. For low. 1. 1. If the applied voltage should be reversed to establish a reverse-bias situation. A number of commercially available semiconductor diodes appear in Fig. The anode refers to the higher or positive potential. with a trr of only a few hundred picoseconds (10 12).39 and stay at this measurable level for the period of time ts (storage time) required for the minority carriers to return to their majority-carrier state in the opposite material. however. the capacitor is normally not included in the diode symbol. Eventually. The electrons in the p-type and holes progressing through the n-type material establish a large number of minority carriers in each material. however. Naturally.39 Defining the reverse recovery time. Some details of the actual construction of devices such as those appearing in Fig. appears at the cathode end.11 REVERSE RECOVERY TIME There are certain pieces of data that are normally provided on diode specification sheets provided by manufacturers. 1. This combination of bias levels will result in a forward-bias or “on” condition for the diode. 32 Chapter 1 Semiconductor Diodes . This second period of time is denoted by tt (transition interval). as shown in Fig. when this storage phase has passed.40. For most diodes any marking such as a dot or band. the diode current will simply reverse as shown in Fig.or mid-frequency applications (except in the power area). Figure 1. In essence. 1. However. and the cathode refers to the lower or negative terminal. 1.40.38 Including the effect of the transition or diffusion capacitance on the semiconductor diode. the current will reduce in level to that associated with the nonconduction state. denoted by trr . the diode will remain in the short-circuit state with a current Ireverse determined by the network parameters. ID I forward Change of state (on required at t = t 1 off) Desired response t1 t I reverse ts t rr tt Figure 1. In the forward-bias state it was shown earlier that there are a large number of electrons from the n-type material progressing through the p-type material and a large number of holes in the n-type—a requirement for conduction. Units are available.41 are provided in Chapters 12 and 20. 1. we would ideally like to see the diode change instantaneously from the conduction state to the nonconduction state. 1. Most commercially available switching diodes have a trr in the range of a few nanoseconds to 1 s.38.12 SEMICONDUCTOR DIODE NOTATION The notation most frequently used for semiconductor diodes is provided in Fig. because of the large number of minority carriers in each material. The reverse recovery time is the sum of these two intervals: trr ts tt. The terminology anode and cathode is a carryover from vacuumtube notation. it is an important consideration in highspeed switching applications.

p n Anode p n Cathode or •.43a reveals an open (defective) diode.40 Semiconductor diode notation. 1.42.43a. An OL indication with the hookup of Fig.13 Diode Testing 33 . etc. 1. 1. therefore. K. 1. 1. Figure 1. [(a) Courtesy of Motorola Inc.] 1. The meter has an internal constant current source (about 2 mA) that will define the voltage level as indicated in Fig. Figure 1. the diode should be in the “on” state and the display will provide an indication of the forward-bias voltage such as 0. In general. Diode Checking Function A digital display meter with a diode checking capability appears in Fig.41 Various types of junction diodes.13 DIODE TESTING The condition of a semiconductor diode can be determined quickly using (1) a digital display meter (DDM) with a diode checking function. (2) the ohmmeter section of a multimeter. and (b) and (c) Courtesy International Rectifier Corporation.. When set in this position and hooked up as shown in Fig.43b. an OL indication should result due to the expected open-circuit equivalence for the diode.67 V (for Si). Note the small diode symbol as the bottom option of the rotating dial. or (3) a curve tracer. an OL indication in both directions is an indication of an open or defective diode. If the leads are reversed.

43 Checking a diode in the forward-bias state. Ohmmeter Testing In Section 1.42 Digital display meter with diode checking capability. including the semiconductor diode.45 can display the characteristics of a host of devices. the display of Fig. while a very low resistance reading in both directions will probably indicate a shorted device. if we measure the resistance of a diode using the connections indicated in Fig.44b. 1.46 Chapter 1 Semiconductor Diodes 34 . Curve Tracer Figure 1. (Courtesy Computronics Technology.7 we found that the forward-bias resistance of a semiconductor diode is quite low compared to the reverse-bias level. 1. For the reverse-bias situation the reading should be quite high. Inc. as indicated in Fig.) Figure 1. By properly connecting the diode to the test panel at the bottom center of the unit and adjusting the controls. we can expect a relatively low level.p n Figure 1.44a. 1.5 V) of the ohmmeter circuit. the less the resistance level. Therefore. The curve tracer of Fig. A high resistance reading in both directions obviously indicates an open (defective device) condition. requiring a high resistance scale on the meter. 1. The higher the current. The resulting ohmmeter indication will be a function of the current established through the diode by the internal battery (often 1.44 Checking a diode with an ohmmeter.

resulting in the voltage levels indicated. the resulting voltage would be about 625 mV 0. 1.625 V. 1. The fact that the curve drops down and away from the horizontal axis rather than up and away for the positive VD region reveals that the current in the Zener region has a direction opposite to that of a forward-biased diode.14 ZENER DIODES The Zener region of Fig. For a 2-mA level as defined for a DDM. The characteristic drops in an almost vertical manner at a reverse-bias potential denoted VZ.45 Curve tracer.47 was discussed in some detail in Section 1.46 Curve tracer response to 1N4007 silicon diode. can be obtained. Note that the vertical scaling is 1 mA/div. resulting in the levels indicated. Although the instrument initially appears quite complex.6. 1. Inc. The same instrument will appear on more than one occasion in the chapters to follow as we investigate the characteristics of the variety of devices. 35 . For the horizontal axis the scaling is 100 mV/div. the instruction manual and a few moments of exposure will reveal that the desired results can usually be obtained without an excessive amount of effort and time.47 Reviewing the Zener region.14 Zener Diodes Figure 1.p n Figure 1. (Courtesy of Tektronix.) Figure 1.

Zener diodes are available having Zener potentials of 1. For the Zener diode the direction of conduction is opposite to that of the arrow in the symbol as pointed out in the introduction to this section. ZZT at IZT ( ) 8. however. IZM (mA) 32 Typical Temperature Coefficient (%/°C) 0. VR (V) 7.072 36 Chapter 1 Semiconductor Diodes . For all applications to follow.4 for a 10-V.50 to permit a description of the Zener nameplate data appearing in Table 1.p n Figure 1. A larger drawing of the Zener region is provided in Fig. (b) semiconductor diode.5 Maximum Knee Impedance.49 Zener equivalent circuit: (a) complete. 20% diode. Figure 1. ZZK at IZK ( ) (mA) 700 0. silicon is usually preferred in the manufacture of Zener diodes. TABLE 1.4 Electrical Characteristics (25°C Ambient Temperature Unless Otherwise Noted) Zener Voltage Nominal.49. For the semiconductor diode the “on” state will support a current in the direction of the arrow in the symbol. The term nominal associated with VZ indicates that it is a typical average value.50 Zener test characteristics. The location of the Zener region can be controlled by varying the doping levels. Because of its higher temperature 4 and current capability.48a. IR at VR ( A) 10 Test Voltage. Both the semiconductor diode and zener diode are presented side by side in Fig. The complete equivalent circuit of the Zener diode in the Zener region includes a small dynamic resistance and dc battery equal to the Zener potential.48 Conduction direction: (a) Zener diode.5 Max Dynamic Impedance. 500-mW. IZT (mA) 12. the Zener potential can be expected to vary as 10 V 20% Figure 1.25 Maximum Reverse Current.2 Maximum Regulator Current. as shown in Fig. which have the graphic symbol appearing in Fig. This region of unique characteristics is employed in the design of Zener diodes. 1. we shall assume as a first approximation that the external resistors are much larger in magnitude than the Zener-equivalent resistor and that the equivalent circuit is simply the one indicated in Fig. VZ (V) 10 Test Current. An increase in doping. 1.48 to ensure that the direction of conduction of each is clearly understood together with the required polarity of the applied voltage. producing an increase in the number of added impurities.8 to 200 V with power ratings from 1 to 50 W.49b. 1. (b) approximate. Since this is a 20% diode. will decrease the Zener potential. 1. 1. Note also that the polarity of VD and VZ are the same as would be obtained if each were a resistive element.

08 – 0. The maximum knee impedance occurs at the knee current of IZK.4 at a temperature of 100°C.5 1 2 Zener current.1 0.04 3.p n or from 8 to 12 V in its range of application. and IZM is the maximum current for the 20% unit. VZ TCVZ (T1 100 T0) 37 1. (1.51 Electrical characteristics for a 10-V. and 3. The temperature coefficient reflects the percent change in VZ with temperature. Also available are 10% and 5% diodes with the same specifications.6 V 24 V 6. 1. negative.08 +0. It is defined by the equation TC VZ VZ (T1 T0) 100% %/°C (1.8 V Dynamic impedance. while a negative value would result in a decrease in value with increase in temperature.8-V. IZ – (mA) (b) Figure 1.12.12).2 0.51a that the temperature coefficient can be positive. ZZ – ( Ω ) 1 kΩ 500 200 100 50 20 10 5 2 0.1 24 V 6.5 1 5 10 50 100 Dynamic impedence versus Zener current 3.8 V 5 10 20 50 100 1 0. Note in Fig. Example 1. and ZZT is the dynamic impedance at this current level. The 24-V. The reverse saturation current is provided at a particular potential level. EXAMPLE 1. 1.04 0 – 0. Determine the nominal voltage for the Zener diode of Table 1. 6.05 0.6 V – 0.6-V levels refer to three Zener diodes having these nominal values within the same family of Zeners.01 0.12 Temperature coefficient – TC (%/˚C) +0.12). The curve for the 10-V Zener would naturally lie between the curves of the 6.3 Solution From Eq. T0 is the temperature at which VZ is provided (normally room temperature—25°C).8-V and 24-V devices. or even zero for different Zener levels. and T1 is the new level. Temperature coefficient versus Zener current +0. IZ – (mA) (a) Zener current.12) where VZ is the resulting change in Zener potential due to the temperature variation.12 0. The test current IZT is the current defined by the 1 power 4 level. 500-mW Zener diode. A positive value would reflect an increase in VZ with an increase in temperature.3 will demonstrate the use of Eq.14 Zener Diodes . Returning to Eq. (1.

54 V The variation in dynamic impedance (fundamentally. Figure 1.15 LIGHT-EMITTING DIODES The increasing use of digital displays in calculators. The two types in common use today to perform this function are the light-emitting diode (LED) and the liquid-crystal display (LCD).47). is VZ VZ 0. the 10-V Zener appears between the 6.072)(10 V) (100°C 100 (0. Again.54 V and because of the positive temperature coefficient. the new Zener potential. A few areas of application for the Zener diode will be examined in Chapter 2. 25°C) Figure 1. 1.4 yield VZ (0. the less the resistance value.53 is an actual photograph of a variety of Zener devices. watches.52 Zener terminal identification and symbols. Note that the heavier the current (or the farther up the vertical rise you are in Fig. and all forms of instrumentation has contributed to the current extensive interest in structures that will emit light when properly biased. 1.52. Note that their appearance is very similar to the semiconductor diode. its series resistance) with current appears in Fig.0072)(75) 0. Since the LED falls within the family of p-n junction devices and will appear in some of 38 Chapter 1 Semiconductor Diodes . Also note that as you drop below the knee of the curve. (Courtesy Siemens Corporation.) 1. the resistance increases to significant levels. defined by VZ. Figure 1.53 Zener diodes. 1. The terminal identification and the casing for a variety of Zener diodes appear in Fig.p n Substitution values from Table 1.8-V and 24-V Zeners.54 V 10.51b.

are for a forward current of 10 mA. as shown in the figure. The relative efficiency is defined by 1. with 20 mA the typical average forward current. Even though this description may not provide a clear understanding of the candela as a unit of measure. 1.2 to 3 V. As the name implies. In other materials. it will be introduced in this chapter. such as gallium arsenide phosphide (GaAsP) or gallium phosphide (GaP). In any forward-biased p-n junction there is. 1. of course.5 V for good light emission. The test conditions listed in Fig.55b that the peak forward current is 60 mA.54 (a) Process of electroluminescence in the LED. Light intensity is measured in candela. Note in the figure that the recombination of the injected carriers due to the forward-biased junction results in emitted light at the site of recombination. the number of photons of light energy emitted is sufficient to create a very visible light source. be some absorption of the packages of photon energy in the structure itself. one can expect a typical operating current of about 10 mA at 2. but a very large percentage are able to leave. In silicon and germanium the greater percentage is given up in the form of heat and the emitted light is insignificant.55c. The process of giving off light by applying an electrical source of energy is called electroluminescence. Two quantities yet undefined appear under the heading Electrical/Optical Characteristics at TA 25°C. The level of VD under forward-bias conditions is listed as VF and extends from 2. 1. This recombination requires that the energy possessed by the unbound free electron be transferred to another state. In all semiconductor p-n junctions some of this energy will be given off as heat and some in the form of photons. Note in Fig. by definition. They are the axial luminous intensity (IV) and the luminous efficacy ( v). The term efficacy is. The appearance and characteristics of a subminiature high-efficiency solid-state lamp manufactured by Hewlett-Packard appears in Fig. to permit the emergence of the maximum number of photons of light energy. its level can certainly be compared between similar devices. the light-emitting diode (LED) is a diode that will give off visible light when it is energized.p n the networks in the next few chapters. however. For the LED this is the ratio of the number of lumens generated per applied watt of electrical energy. within the structure and primarily close to the junction. a measure of the ability of a device to produce a desired effect. One candela emits a light flux of 4 lumens and establishes an illumination of 1 footcandle on a 1-ft2 area 1 ft from the light source. the conducting surface connected to the p-material is much smaller. Figure 1. As shown in Fig.15 Light-Emitting Diodes 39 . The LCD display is described in Chapter 20. 1.55. In other words. (b) graphic symbol. There may.54 with its graphic symbol. a recombination of holes and electrons.

(Courtesy Hewlett-Packard Corporation. (d) relative intensity versus wavelength. 1. (f) relative luminous intensity versus forward current. 1.55i simply reveals that the intensity is greater at 0° (or head on) and the least at 90° (when you view the device from the side). (g) relative efficiency versus peak current. Figure 1.55e) similar to the diode response curves. as shown in Fig.55 Hewlett-Packard subminiature high-efficiency red solid-state lamp: (a) appearance.55h reveals that the longer the pulse duration at a particular frequency. Figure 1.55g. 1. (e) forward current versus forward voltage. Figure 1. the lower the permitted peak current (after you pass the break value of tp). The relative intensity of each color versus wavelength appears in Fig. Since the LED is a p-n junction device. Note the almost linear increase in relative luminous intensity with forward current (Fig. (c) electrical/optical characteristics. it will have a forward-biased characteristic (Fig.) 40 Chapter 1 Semiconductor Diodes . (h) maximum peak current versus pulse duration. (b) absolute maximum ratings. (i) relative luminous intensity versus angular displacement.p n the luminous intensity per unit current. 1.55d.55f).

4 1.6 0 10 20 30 40 50 60 IF – Forward current – mA (f) Ipeak – Peak current – mA (g) Ratio of maximum tolerable peak current to maximum tolerable dc current 6 5 4 3 T 100 k tp 20˚ 30˚ 40˚ 50˚ 10˚ 0˚ 0.5 2.5 TA = 25˚C 0 500 550 600 650 Wavelength–nm (d) 700 750 20 IF – Forward current – mA Relative luminous intensity (normalized at 10 mA) Relative efficiency (normalized at 10 mA dc) TA = 25˚C 15 3.8 0.p n 1.6 1.0 1.7 0.15 Light-Emitting Diodes 41 .0 Green Relative intensity Yellow GaAsP Red High efficiency Red 0.000 90˚ 20˚ 40˚ 60˚ 80˚ 100˚ (i) Figure 1.0 TA = 25˚C 2.3 1.5 1.0 10 1.0 VF – Forward voltage – V (e) 0 5 10 15 20 1.2 1.9 0.4 0.8 0.0 5 0 0 0 0.5 1.2 z 30 kH Hz z 3 kH z 10 kH Hz 100 Hz 300 z 1 kH Ipeak max – Idc max 1 1. 1.5 3.0 10 100 1000 tp – Pulse duration – µs (h) 10.1 1.6 2 60˚ 70˚ 80˚ 0.0 2.55 Continued.0 0.

1 to 1 in. However. yellow. LEDs operate at voltage levels from 1.59 (see page 44). Numbers can be created by segments such as shown in Fig. 1.56 Litronix segment display. The other numbers then follow in sequence. One possible array appears in Fig. internal to the integrated circuit are systems and discrete devices that were available long before the integrated circuit as we know it today became a reality. It is simply a packaging technique that permits a significant reduction in the size of electronic systems. 1. Their semiconductor construction adds a significant ruggedness factor. Another diode array appears in Fig.3 V. In general. The remaining diodes would be left hanging and not affect the network to which pins 1 and 2 are connected. Figure 1. Pin 1 is the pin directly above the small indentation as you look down on the device. 1. That is.56. and white with blue soon to be commercially available.000 hours. or vice versa. The lightemitting region is available in lengths from 0. any number from 0 to 9 can be displayed. They have a fast response time (nanoseconds) and offer good contrast ratios for visibility. in the container shown in Fig.7 to 3. we have reached a plateau in our introduction to electronic circuits that permits at least a surface examination of diode arrays in the integrated-circuit package. Note in the same figure that pin 1 can be determined as being to the left of the small projection in the case if we look from the bottom toward the case.57. 1. then only pins 1 and 2 (or any number from 3 to 9) would be used. which makes them completely compatible with solid-state circuits. You will find that the integrated circuit is not a unique device with characteristics totally different from those we examine in these introductory chapters. There are also two-lead LED lamps that contain two LEDs.58 there are diodes set in a single silicon wafer that have all the anodes connected to pin 1 and the cathodes of each to pins 2 through 9. In this case the package is different but the numbering sequence appears in the outline. In other words. LEDs are presently available in red. Note that eight diodes are internal to the diode array. and white.p n LED displays are available today in many different sizes and shapes. If only one diode is to be used. orange. 42 Chapter 1 Semiconductor Diodes .16 DIODE ARRAYS—INTEGRATED CIRCUITS The unique characteristics of integrated circuits will be introduced in Chapter 12. so that a reversal in biasing will change the color from green to red. 1. green. The power requirement is typically from 10 to 150 mW with a lifetime of 100. By applying a forward bias to the proper p-type material segment.

With this in mind the computer analysis of this book was designed to make the computer system more “friendly” by revealing the relative ease with which it can be applied to perform some very help1.16 Diode Arrays — Integrated Circuits 43 .17 PSPICE WINDOWS The computer has now become such an integral part of the electronics industry that the capabilities of this working “tool” must be introduced at the earliest possible opportunity. 1. For those students with no prior computer experience there is a common initial fear of this seemingly complicated powerful system.57 Monolithic diode array.p n Figure 1.

200" max. ful and special tasks in a minimum amount of time with a high degree of accuracy. The purpose here is solely to introduce some of the terminology. touch on some of its limitations. When a language is employed to analyze a system.310" Notes: Alloy 42 pins. It permits innovative “moves” by the user that can result in printouts of data in an informative and interesting manner. tin plated Gold plated pins available Hermetically sealed ceramic package 1 7 1 Figure 1. Fortran. Programs typically develop with time and application as more efficient paths toward a solution become obvious. to name a few. The important advantage of the language approach is that a program can be tailored to meet all the special needs of the user. or C. through its symbolic notation. one wrong step and the result obtained can be completely meaningless.785" Connection Diagrams FSA2500M 0. As with the longhand approach.59 Monolithic diode array. or Circuit Master. the chosen language was BASIC. In general. All dimensions are in inches. reveal the possibilities available. forms a bridge between the user and the computer that permits a dialogue between the two for establishing the operations to be performed. and demonstrate its versatility with a number of carefully chosen examples.p n Figure 1.58 Package outline TO-96 for a diode array. MicroCap II. Once established in its “best” form it can be cataloged for future use. All dimensions are in inches. A language.271" 2 10 0. In earlier editions of this text. or utilizing a software package such as PSpice. The content was written with the assumption that the reader has no prior computer experience or exposure to the terminology to be applied. There is also no suggestion that the content of this book is sufficient to permit a complete understanding of the “hows” and “whys” that will surface. A software package is a program written and tested over a 44 Chapter 1 Semiconductor Diodes . Breadboard. the computer analysis of electronic systems can take one of two approaches: using a language such as BASIC. a program is developed that sequentially defines the operations to be performed—in much the same order in which we perform the same analysis in longhand. primarily because it uses a number of familiar words and phrases from the English language that in themselves reveal the operation to be performed. Pascal. Seating plane 3 4 5 6 7 8 9 8 14 0. The alternative approach referred to above utilizes a software package to perform the desired investigation. discuss a few of its capabilities. TO-116-2 Outline 0.

In addition. If one is to depend on computer analysis on a continuing basis. A more sophisticated version referred to simply as SPICE is finding widespread application in industry. The choice of which language or software package to become familiar with is primarily a function of the area of investigation. therefore.0 CD-ROM version. the user must input information exactly as requested by the package or the data may be misinterpreted.) In total. When using PSpice Windows. The software package chosen for this book is PSpice. 1. This text will be using Version 8.17 PSpice Windows 45 . is to install PSpice into the hard-disk *PSpice is a registered trademark of the OrCAD-MicroSim Corporation.5 diskettes. Figure 1. the network is first drawn on the screen followed by an analysis dictated by the needs of the user. one may acquire the data needed for a particular analysis from a software package and then turn to a language to define the format of the output. Fortunately. (Courtesy of the OrCAD-MicroSim Corporation. A language permits an expanded level of flexibility but also fails to benefit from the extensive testing and research normally devoted to the development of a “trusted” package. of course. A user must adjust his or her desire for output information to the range of possibilities offered by the package. if a package exists for the desired analysis or synthesis. The first step. efficient program. it should be considered before turning to the many hours required to develop a reliable. The package itself cannot be altered by the user. knowledge of the use and limits of both languages and software packages is a necessity. In addition. A photograph of a complete Design Center package appears in Fig. The user must define which approach best fits the needs of the moment.p n period of time designed to perform a particular type of analysis or synthesis in an efficient manner with a high level of accuracy. a fluent knowledge of one language or a particular software package will usually help the user become familiar with other languages and software packages.0.0. the two approaches go hand in hand.60 PSpice Design package. 1. the latest available. The Windows version employed in this text is 8. the Windows version is the most popular today. though the differences between this and earlier Windows versions are so few and relatively minor for this level of application that one should not be concerned if using an earlier edition.* PSpice currently is available in two forms: DOS and Windows. There is a similarity in purpose and procedures that ease the transition from one approach to another. Although DOS format was the first introduced. however. Obviously. In many ways.60 with the 8. and its application is limited to the operations built into the system. a software package is “packaged” to perform a specific series of calculations and operations and to provide the results in a defined format. It is also available in 3.

Since we have just finished covering the diode in detail. move the diode to any location you prefer and. An Edit Model dialog box will appear with a choice of changing the model reference (D1N4148). click on it again and hold the clicker down on the mouse. the procedure for each element will be described following the discussion of the characteristics and analysis of each device. If the label or parameters of the diode are to be changed. Now that we know the D1N4148 diode exists. The result is that the diode will appear on the screen and can be put in place with a left click of the mouse. The diode will turn green and blue. When selected. Left click on the symbol and a Part Browser Basic dialog box will appear. you will simply have to remember whether the device is in the active state.p n memory of your computer following the directions provided by MicroSim. Next. it can be obtained directly once the Part Browser Basic dialog box appears. simply left click on it once. followed by Model. In this text. the Edit choice of the menu bar at the top of the screen also can be chosen. additional comments regarding use of the diode will be made in the chapters to follow. Once set. all available parts in this library will appear in the Part listing. but the most direct path is to click on the picture symbol with the binoculars on the top right of the schematics screen. There are several ways to proceed. simply click on the element once (to make it red) and choose Edit. The result is that the Part Name will appear above and the Description will indicate it is a diode. Once located. a Library Browser dialog box will appear and the EVAL. D2. Any of the diodes can be removed by simply clicking on them to make them red and pressing the Delete key. simply click on the Place & Close option. D3. For all the above and for the chapters to follow. and so on) and the other the name of the chosen diode (D1N4148). the Part Browser Basic dialog box will appear as before and the same procedure can be followed. The process can be ended by a single right click of the mouse. Next. the procedure for finding the diodes stored in the library will be introduced along with the method for placing them on the screen.slb library should be chosen. followed by using the Delete command. if you happen to have a monochromatic (black-andwhite) screen. The same diode can be placed in other places on the same screen by simply moving the pointer and left clicking the mouse. Once established. the elements for the network must be obtained and placed on the screen to build the network. Remember that anything in red can be operated on. lift up on the clicker. two labels will appear—one indicating how any diodes have been placed (D1. click OK and the Part Browser Basic dialog box will reappear with the full review of the chosen element. Another path for obtaining an element is to choose Draw on the menu bar. For the moment. until it turns red. a message Get New Part will be displayed. when set. If a diode has to be moved. As mentioned above. If time permits. By choosing Libraries. Simply type D1N4148 in the Part Name box. scroll the Part list and choose the D1N4148 diode. To place the device on the screen and close the dialog box. simply remove the pointer from the element and click it once. or the parameters that define the characteristics of the diode. indicating that its location and associated information is set in memory. Then. If preferred. followed by Get New Part. At the same time. 46 Chapter 1 Semiconductor Diodes . review the other elements available within the various libraries to prepare yourself for the work to follow. and the diode will appear on the screen. followed by Place & Close. To remove the red status. we are at least aware of how to find and place an element on the screen. As you bring the marker close to the box using the mouse. the Schematics screen must be obtained using a control mechanism such as Windows 95. The next chapter will introduce the procedure for analyzing a complete network with diodes using PSpice. the text associated with each parameter. Once chosen.

determine the charge involved. 14. In your own words. and covalent bonding. (a) Using Table 1. Repeat Problem 15 but insert an impurity of indium.4 Energy Levels 9.9. Describe the difference between n-type and p-type semiconductor materials. That is. Consult your reference library and determine the level of Eg for GaP and ZnS. and ohmic contact resistance. 8. 7. two semiconductor materials of practical value. 1. 11. 2. Using Eq. Sketch the atomic structure of copper and discuss why it is a good conductor and how its structure is different from germanium and silicon. describe why the short-circuit and open-circuit equivalents are appropriate. 5.and reverse-bias states of the p-n junction diode. a negative temperature coefficient. Describe in your own words the meaning of the word ideal as applied to a device or system. determine the resistance of a silicon sample having an area of 1 cm2 and a length of 3 cm. Using both descriptions.5 cm2.3 Semiconductor Materials 4. If 48 eV of energy is required to move a charge through a potential difference of 12 V. Describe how you will remember the forward.6 V. In addition. how you will remember which potential (positive or negative) is applied to which terminal? 20. 6.6 Semiconductor Diode 18. 17. § 1. Sketch the atomic structure of silicon and insert an impurity of arsenic as demonstrated for silicon in Fig. 3.2 Ideal Diode 1.p n § 1. § 1. Consult your reference library and list three materials that have a negative temperature coefficient and three that have a positive temperature coefficient. In your own words. Describe in your own words the characteristics of the ideal diode and how they determine the on and off states of the device. Describe in your own words the conditions established by forward.and p-Type 12. (c) Repeat part (a) if the length is 8 cm and the area 0. bulk resistance.1. define semiconductor. That is. Describe the difference between majority and minority carriers. What is the one important difference between the characteristics of a simple switch and those of an ideal diode? PROBLEMS § 1. determine the written name for each material. How much energy in joules is required to move a charge of 6 C through a difference in potential of 3 V? 10. 16. define an intrinsic material. determine the diode current at 20°C for a silicon diode with Is an applied forward bias of 0. 13. § 1. (d) Repeat part (a) for copper and compare the results. (b) Repeat part (a) if the length is 1 cm and the area 4 cm2. Describe the difference between donor and acceptor impurities. (1. describe in your own words the process of hole conduction. 50 nA and Problems 47 .4). 15.5 Extrinsic Materials—n. Consult your reference library and find another explanation of hole versus electron flow.and reverse-bias conditions on a p-n junction diode and how the resulting current is affected. 19. resistivity.

26. Use a straight line segment that intersects the horizontal axis at 0. 29. 1.19 at 0. Determine the ac resistance for the diode of Fig. 1. 1. 31. (c) Compare solutions of parts (a) and (b). (1. Give some details. 28. 1. 20°C). 100°C. § 1. determine the diode current at 20°C for a silicon diode with Is at a reverse-bias potential of 10 V. 1. Using Eq. 1.6 and 0. ex at x 0? 1 important in Eq. Determine the static or dc resistance of the commercially available diode of Fig. Calculate the dc and ac resistance for the diode of Fig. Compare to the solutions obtained in Problem 32. § 1.6). 48 Chapter 1 Semiconductor Diodes . 33. (b) Is the result expected? Why? 23. (1. 25°C. 35. Assume that Is has increased to 0.19 at a reverse voltage of 10 V.1 A (T Determine its approximate value if the temperature is increased 40°C. Modify the equation as necessary for low levels of diode current. Refer to a manufacturer’s listing and compare the characteristics of a germanium and a silicon diode of similar maximum ratings. 1. Determine the forward voltage drop across the diode whose characteristics appear in Fig.29 at a forward current of 10 mA using Eq. Repeat Problem 20 for T 5. Using Eq. Determine the static or dc resistance of the commercially available diode of Fig. 25.29.75 V and compare to the average ac resistance obtained in Problem 34.1 A 22. 100°C (boiling point of water). (1.7 V. (1. 1. Compare the characteristics of a silicon and a germanium diode and determine which you would prefer to use for most practical applications.19 at a forward current of 2 mA. Determine the average ac resistance for the diode of Fig. For each temperature. (1.29 at a forward current of 10 mA using Eq. why is the factor 24. Repeat Problem 36 for the diode of Fig. determine the level of saturation current.7).24 at temperatures of 75°C. Find the piecewise-linear equivalent circuit for the diode of Fig. Repeat Problem 26 at a forward current of 15 mA and compare results. 32.4).29 at a forward current of 10 mA and compare their magnitudes. (b) Determine the dynamic (ac) resistance of the diode of Fig. (a) Determine the dynamic (ac) resistance of the diode of Fig. 34. 1.p n 21.19. determine the ac resistance at a current of 1 mA and 15 mA for the diode of Fig. How does it compare to the value determined at a reverse voltage of 30 V? 30.4)? (b) What is the value of y (c) Based on the results of part (b). In the reverse-bias region the saturation current of a silicon diode is about 0.8 Diode Equivalent Circuits 36. determine the ac resistance at a current of 1 mA and 15 mA for the diode of Fig. (a) Plot the function y ex for x from 0 to 5. 1.19. 1.7).6). and 200°C and a current of 10 mA. 1.29. Compare the solutions and develop a general conclusion regarding the ac resistance and increasing levels of diode current.19 for the region between 0. (1.7 V and best approximates the curve for the region greater than 0. 37.0 A.7 Resistance Levels 27. (a) Using Eq.9 V. Compare the extremes of each and comment on the ratio of the two.

Compare levels and comment on whether the results support conclusions derived in earlier sections of this chapter. 1.10 Transition and Diffusion Capacitance * 45.36. Using the characteristics of Fig.50. 1.) Problems 49 . determine the diffusion capacitance at 0 and 0.61 if tt time is 9 ns. 43. 1. 47.61 Problem 49 § 1.11 Reverse Recovery Time 49. 1.7 V.4. and IZM 40 mA. 2ts and the total reverse recovery Figure 1. 1. 1.5. Assuming that VF remains fixed at 0. 25 1 V. how has the maximum level of IF changed between the two temperature levels? 44. determine the temperature at which the diode current will be 50% of its value at room temperature (25°C). The following characteristics are specified for a particular Zener diode: VZ 29 V. What is the ratio of the change in capacitance to the change in voltage? (b) Repeat part (a) for reverse-bias potentials of 10 and change in capacitance to the change in voltage.2 and 11.37 at a forward potential of 0. 1. 48. § 1. 1.50 have a nominal voltage of 10. 1. Is the change significant? Does the level just about double for every 10°C increase in temperature? 42. Does the reverse saturation current of the diode of Fig. IR 20 A.1.25 V.36 determine the maximum ac (dynamic) resistance at a forward current of 0. Determine the reactance offered by a diode described by the characteristics of Fig. 1. 39. For the diode of Fig. At what temperature will the 10-V Zener diode of Fig. Sketch the waveform for i of the network of Fig.36.14 Zener Diodes 50. (a) Referring to Fig.37.3). and 20 mA. Determine the ratio of the (c) How do the ratios determined in parts (a) and (b) compare? What does it tell you about which range may have more areas of practical application? 46.36 change significantly in magnitude for reverse-bias potentials in the range 25 to 100 V? * 41. For the diode of Fig.8 V.9 Diode Specification Sheets * 38. IZT 10 mA. determine the transition capacitance at reverse-bias potentials of and 10 V. 40. Describe in your own words how diffusion and transition capacitances differ.75 V? (Hint: Note the data in Table 1. determine the maximum power dissipation levels for the diode at room temperature (25°C) and 100°C. * 51. VR 16. Sketch the characteristic curve in the manner displayed in Fig. Referring to Fig.p n § 1. 1. 1.36.2 V and a reverse potential of 20 V if the applied frequency is 6 MHz. Note that the provided graph employs a log scale for the vertical axis (log scales are covered in sections 11. Plot IF versus VF using linear scales for the diode of Fig.36. § 1. 1. Using the characteristics of Fig.36 determine the level of IR at room temperature (25°C) and the boiling point of water (100°C). Comment on the change in capacitance level with increase in reverse-bias potential for the diode of Fig. 1.37.

1 mA. 50 Chapter 1 Semiconductor Diodes . 1. at what angle will it be 0. Using the information provided in Fig. 1. 1. (c) Compare the percent increase from parts (a) and (b). determine the forward voltage across the diode if the relative luminous intensity is 1.55. (Note the absolute maximum ratings. Compare the levels of dynamic impedance for the 24-V diode of Fig. 1. At what point on the curve would you say there is little gained by further increasing the peak current? * 59.51b. 1.55 if the peak current is increased from 5 to 10 mA? (b) Repeat part (a) for 30 to 35 mA (the same increase in current).8 V at a temperature of 100°C.75 mcd? (b) At what angle does the loss of luminous intensity drop below the 50% level? * 61.p n 52. 60. Sketch the current derating curve for the average forward current of the high-efficiency red LED of Fig. Assume a linear scale between nominal voltage levels and a current level of 0. what level of temperature coefficient would you expect for a 20-V diode? Repeat for a 5-V diode.2. and 10 mA. 1.55e. 1. the frequency is 300 Hz.51a. determine the maximum tolerable peak current if the period of the pulse duration is 1 ms. 53.0 mcd for the device of Fig. 1.55h. Determine the dynamic impedance for the 24-V diode at IZ it is a log scale.15 Light-Emitting Diodes 56. 1.5. (b) Repeat part (a) for a frequency of 100 Hz. Using the curves of Fig.) *Please Note: Asterisks indicate more difficult problems. (a) What is the percent increase in relative efficiency of the device of Fig. Referring to Fig.55. 1. (a) Referring to Fig. 54. * 58. and the maximum tolerable dc current is 20 mA. 10 mA for Fig.55 as determined by temperature. Note that * 55.51b at current levels of 0. How do the results relate to the shape of the characteristics in this region? § 1. Determine the temperature coefficient of a 5-V Zener diode (rated 25°C value) if the nominal voltage drops to 4. what would appear to be an appropriate value of VT for this device? How does it compare to the value of VT for silicon and germanium? 57. (a) If the luminous intensity at 0° angular displacement is 3.

In this book the emphasis is toward developing a working knowledge of a device through the use of appropriate approximations. the fundamental behavior pattern of diodes in dc and ac networks should be clearly understood. It is important that the role and response of various elements of an electronic system be understood without continually having to resort to lengthy mathematical procedures. Although the results obtained using the actual characteristics may be slightly different from those obtained using a series of approximations. By chapter’s end. diodes are frequently employed in the description of the basic construction of transistors and in the analysis of transistor networks in the dc and ac domains. characteristics. and models of semiconductor diodes were introduced in Chapter 1. The analysis will proceed from one that employs the actual diode characteristic to one that utilizes the approximate models almost exclusively. 2 51 . This is usually accomplished through the approximation process. yet the characteristics and models remain the same. The variation may be slight. to permit a detailed mathematical analysis if desired. Also consider the other elements of the network: Is the resistor labeled 100 exactly 100 ? Is the applied voltage exactly 10 V or perhaps 10. however. The concepts learned in this chapter will have significant carryover in the chapters to follow. In other words.1 INTRODUCTION The construction. keep in mind that the characteristics obtained from a specification sheet may in themselves be slightly different from the device in actual use. thereby avoiding an unnecessary level of mathematical complexity. which can develop into an art itself. its function and response in an infinite variety of configurations can be determined. but it will often be sufficient to validate the approximations employed in the analysis. The content of this chapter will reveal an interesting and very positive side of the study of a field such as electronic devices and systems—once the basic behavior of a device is understood. Sufficient detail will normally be provided. The primary goal of this chapter is to develop a working knowledge of the diode in a variety of configurations using models appropriate for the area of application. For instance. The range of applications is endless. the characteristics of a 1N4001 semiconductor diode may vary from one element to the next in the same lot.08 V? All these tolerances contribute to the general belief that a response determined through an appropriate set of approximations can often be “as accurate” as one that employs the full characteristics.CHAPTER Diode Applications 2.

(2.1) becomes E VD 0V and Figure 2.1a that the “pressure” established by the battery is to establish a current through the series circuit in the clockwise direction. This similarity permits a plotting of Eq. If we set ID 0 A in Eq. 2.1) and solve for VD. 2. 2. a line can be drawn on the characteristics of the device that represents the applied load. 2. A straight line drawn between the two points will define the load line as depicted in Fig. for obvious reasons. 2. (2.1a employing a diode having the characteristics of Fig.1b. 2. We now have a load line defined by the network and a characteristic curve defined by the device. called load-line analysis.1b.2.2. we have the magnitude of ID on the vertical axis.2 LOAD-LINE ANALYSIS The applied load will normally have an important impact on the point or region of operation of a device.1) The two variables of Eq.3) as shown in Fig. and this introduction offers the simplest application of the method. Eq.1) becomes E VD VD and VD ID R (0 A)R E ID =0 A (2. Such an analysis is. It also permits a validation of the approximate technique described throughout the remainder of this chapter. If we set VD 0 V in Eq. (2. we have the magnitude of VD on the horizontal axis.1a will result in E or E VD VD VR ID R 0 (2. 2. The fact that this current and the defined direction of conduction of the diode are a “match” reveals that the diode is in the “on” state and conduction has been established.1) on the same characteristics of Fig. The point of intersection between the two is the point of opera52 Chapter 2 Diode Applications . Therefore. (2. (2.1) (VD and ID) are the same as the diode axis variables of Fig. with ID 0 A. Change the level of R (the load) and the intersection on the vertical axis will change.2) ID E R VD=0 V as shown in Fig. the technique is one used quite frequently in subsequent chapters.1 Series diode configuration: (a) circuit. Consider the network of Fig. IDR IDR (2.1b will be the region of interest—the forward-bias region. 2. Therefore. Eq. Applying Kirchhoff’s voltage law to the series circuit of Fig. (2. Although the majority of the diode networks analyzed in this chapter do not employ the load-line approach. The resulting polarity across the diode will be as shown and the first quadrant (VD and ID positive) of Fig.1b. The intersections of the load line on the characteristics can easily be determined if one simply employs the fact that anywhere on the horizontal axis ID 0 A and anywhere on the vertical axis VD 0 V. 2. The intersection of the load line with the characteristics will determine the point of operation of the system. (b) characteristics. Note in Fig.2. The result will be a change in the slope of the load line and a different point of intersection between the load line and the device characteristics.1) and solve for ID. with VD 0 V. If the analysis is performed in a graphical manner.2. 2.

3 (a) Circuit. The point of operation is usually called the quiescent point (abbreviated “Q-pt. tion for this circuit. 2. (b) characteristics. (2. whereas a horizontal line from the point of intersection to the vertical axis will provide the level of IDQ.3).3a employing the diode characteristics of Fig.2 Load-line Analysis 53 . The current ID is actually the current through the entire series configuration of Fig.3b determine: (a) VDQ and IDQ. EXAMPLE 2.2) and (2.1) and (1. The next two examples will demonstrate the techniques introduced above and reveal the relative ease with which the load line can be drawn using Eqs. (2. 2.ID E R ID Q Characteristics (device) Q-point Load line (network) 0 V D Q E VD Figure 2.1 Figure 2. 2. The solution obtained at the intersection of the two curves is the same that would be obtained by a simultaneous mathematical solution of Eqs. The load-line analysis described above provides a solution with a minimum of effort and a “pictorial” description of why the levels of solution for VDQ and IDQ were obtained.1a. (b) VR. unmoving” qualities as defined by a dc network. Since the curve for a diode has nonlinear characteristics the mathematics involved would require the use of nonlinear techniques that are beyond the needs and scope of this book.2 Drawing the load line and finding the point of operation. 2.4) [ID Is(ekVD/TK 1)].”) to reflect its “still. By simply drawing a line down to the horizontal axis the diode voltage VDQ can be determined. For the series diode configuration of Fig.

(2. the results obtained either way should be the same. 54 Chapter 2 Diode Applications .3): VD E ID 0 A 10 V The resulting load line appears in Fig. Certainly. 2. A higher degree of accuracy would require a plot that would be much larger and perhaps unwieldy.2): ID VDQ IDQ 0.3 V The difference in levels is again due to the accuracy with which the graph can be read. The intersection between the load line and the characteristic curve defines the Q-point as VD ID Q 0. Solution E 10 V 5 mA R VD 0 V 2 k Eq. (2.2 Repeat the analysis of Example 2. and the accuracy of ID is limited by the chosen scale.22 V The difference in results is due to the accuracy with which the graph can be read.5.1 with R 2k .78 V 9. The resulting Q-point is defined by (a) Eq. (2. Note the reduced slope and levels of diode current for increasing loads.78 V 9.25 V or VR E VD 10 V 0.7 V 9.3): VD E ID 0 A 10 V The resulting load line appears in Fig.25 mA)(1 k ) 9.25 mA Q The level of VD is certainly an estimate.2): ID E 10 V 10 mA R VD 0 V 2 k Eq. Figure 2.7 V 4.Solution (a) Eq. however.1. the results provide an expected magnitude for the voltage VR.6 mA (b) VR IRR IDQR (4. (b) VR IRR IDQR (9. Ideally.4. 2.6 mA)(2 k ) 9.2 V with VR E VD 10 V 0. (2.4 Solution to Example 2. EXAMPLE 2.

As noted in the examples above.7 V Q 3 4 5 6 7 8 9 10 V (V) D (E) Figure 2.5 1 2 ~ VD = 0. 2. the load line will be exactly the same as obtained in the examples above.5 Solution to Example 2. the load line is determined solely by the applied network while the characteristics are defined by the chosen device.7 V Q 3 4 5 6 7 8 9 10 V (V) D Figure 2.3 Solution The load line is redrawn as shown in Fig. 2.1 and 2.6 with the same intersections as defined in Example 2.5 1 2 ~ VD = 0.I D (mA) 10 9 8 7 E R 6 I D ~ 4.6 Solution to Example 2. The resulting Q-point: VD ID Q 0. the next two examples repeat the analysis of Examples 2.6 mA 5 = Q 4 3 2 1 0 Q-point Load line (from Example 2. If we turn to our approximate model for the diode and do not disturb the network.1 using the approximate equivalent model for the silicon semiconductor diode.1 using the diode approximate model. The characteristics of the approximate equivalent circuit for the diode have also been sketched on the same graph.25 mA 9 = Q 8 7 6 5 4 3 2 1 0 Q-point ⇒ 0.7 V ID Load line 0.2 using the approximate model to permit a comparison of the results.2.1. In fact. Repeat Example 2.2 Load-line Analysis 55 . EXAMPLE 2.7 V 9.25 mA Q I D (mA) 10 I D ~ 9.1) 0.

6 mA ID Q ⇒ Q-point 0.1 using the ideal diode model.78 V from Example 2. It suggests.2 using the diode approximate model. The results will reveal the conditions that must be satisfied to apply the ideal equivalent properly.2 using the approximate equivalent model for the silicon semiconductor diode. The level of IDQ is exactly the same as obtained in Example 2.1 using a characteristic curve that is a great deal easier to draw than that appearing in Fig. that the use of appropriate approximations can result in solutions that are very close to the actual response with a reduced level of concern about properly reproducing the characteristics and choosing a large-enough scale. EXAMPLE 2.4 Repeat Example 2.2. The Q-point is therefore defined by VD Q 0V 10 mA ID 56 Chapter 2 Diode Applications Q .8 the load line continues to be the same.1 is of a different magnitude to the hundredths place. The resulting Q-point: VD I D (mA) 10 9 8 7 6 ~ 4.2. as will be applied in the sections to follow.7 V 4.The results obtained in Example 2.7 V versus 0. 2. but they are certainly in the same neighborhood if we compare their magnitudes to the magnitudes of the other voltages of the network. In the next example we go a step further and substitute the ideal model.7 with the same intersections defined in Example 2. EXAMPLE 2. but the ideal characteristics now intersect the load line on the vertical axis. Solution As shown in Fig.3 are quite interesting. 2. The level of VD 0.6 mA 5 ID = Q 4 3 2 1 0 Q 0. In Example 2.5 1 2 ~ 0.7 V VD = Q 3 4 5 6 7 8 9 10 V (V) D Figure 2. Solution The load line is redrawn as shown in Fig.4 the results obtained for both VDQ and IDQ are the same as those obtained using the full characteristics in Example 2. The examples above have demonstrated that the current and voltage levels obtained using the approximate model have been very close to those obtained using the full characteristics. The characteristics of the approximate equivalent circuit for the diode have also been sketched on the same graph.7 Solution to Example 2.4.4 Repeat Example 2.7 V ID Load line 0. 2.

Certainly.1 to cause some concern about their accuracy. Recall the following: The primary purpose of this book is to develop a general knowledge of the behavior. but the additional effort of simply including the 0.1 using the ideal diode model. temperature.1 was developed to review the important characteristics. it is the approach that will be employed in this book unless otherwise specified. The results are sufficiently different from the solutions of Example 2. they do provide some indication of the level of voltage and current to be expected relative to the other voltage levels of the network. capabilities. 2.Figure 2. to the response obtained using the full characteristics.3 DIODE APPROXIMATIONS In Section 2. one could certainly consider one solution to be “as accurate” as the other.8 Solution to Example 2. Table 2. In fact. and conditions of application for the approximate and ideal diode models. and possible areas of application of a device in a manner that will minimize the need for extensive mathematical developments. if one considers all the variations possible due to tolerances. In the next few sections the approximate model will be employed exclusively since the voltage levels obtained will be sensitive to variations that approach VT.2.3 is more appropriate. and so on. Although the silicon diode is used almost exclusively due to 2.7-V offset suggests that the approach of Example 2. In later sections the ideal model will be employed more frequently since the applied voltages will frequently be quite a bit larger than VT and the authors want to ensure that the role of the diode is correctly and clearly understood. If rav should be close in magnitude to the other series elements of the network. In preparation for the analysis to follow.2 we revealed that the results obtained using the approximate piecewiselinear equivalent model were quite close. Since the use of the approximate model normally results in a reduced expenditure of time and effort to obtain the desired results. if not equal. The complete piecewise-linear equivalent model introduced in Chapter 1 was not employed in the load-line analysis because rav is typically much less than the other series elements of the network. the complete equivalent model can be applied in much the same manner as described in Section 2.3 Diode Approximations 57 . Use of the ideal diode model therefore should be reserved for those occasions when the role of a diode is more important than voltage levels that differ by tenths of a volt and in those situations where the applied voltages are considerably larger than the threshold voltage VT. models.

TABLE 2. As with the silicon diode.3 V in the equivalent circuits are not independent sources of energy but are there simply to remind us that there is a “price to pay” to turn on a diode. the germanium diode is still employed and is therefore included in Table 2. An isolated diode on a laboratory table will not indicate 0.3 V.7 and 0.1 Approximate and Ideal Semiconductor Diode Models its temperature characteristics.7 or 0. Keep in mind that the 0.3 V if a voltmeter is placed across its terminals. 58 Chapter 2 Diode Applications . It will enter the “on” state when VD VT 0. The supplies specify the voltage drop across each when the device is “on” and specify that the diode voltage must be at least the indicated level before conduction can be established. a germanium diode is approximated by an open-circuit equivalent for voltages less than VT.1.

Which diodes are “on” and which are “off”? Once determined. the diode symbol will appear as shown in Fig. in fact. The procedure described can. one can either place a 0.10. Figure 2. and VD 0.10 Series diode configuration.7 V for silicon and VD 0. 2. conduction through the diode will occur and the device is in the “on” state. Initially.1.9 (a) Approximate model notation.10.11.10 described in some detail in Section 2. contingent on the supply having a voltage greater than the “turnon” voltage (VT) of each diode. a diode is in the “on” state if the current established by the applied sources is such that its direction matches that of the arrow in the diode symbol. mentally replace the diodes with resistive elements and note the resulting current direction as established by the applied voltages (“pressure”). the substitution method will be utilized to ensure that the proper voltage and current levels are determined. In time the preference will probably simply be to include the 0.4 Series Diode Configurations with DC Inputs 59 . 2.9b. 2. If the resulting direction is a “match” with the arrow in the diode symbol. be applied to networks with any number of diodes in a variety of configurations.5) (2. The network is then redrawn as shown in Fig.7-V drop across the element. For those situations where the approximate equivalent circuit will be employed. The content will establish a foundation in diode analysis that will carry over into the sections and chapters to follow.4 SERIES DIODE CONFIGURATIONS WITH DC INPUTS In this section the approximate model is utilized to investigate a number of series diode configurations with dc inputs. The series circuit of Fig. the appropriate equivalent as defined in Section 2.3 can be substituted and the remaining parameters of the network determined. For each configuration the state of each diode must first be determined.7-V drop across each “on” diode and draw a line through each diode in the “off” or open state.12 with the appropriate equivalent model for the forward-biased silicon diode. Note for future reference that the polarity of VD is the same as would result if in fact the diode were a resistive element.1 on the analysis of diode configurations. (b) ideal diode notation.11 Determining the state of the diode of Fig. Figure 2. If a diode is in the “on” state. 2. If conditions are such that the ideal diode model can be employed.3 V for germanium.2 will be used to demonstrate the approach described in the paragraphs above. 2. The description above is. 2. For each configuration.9a for the silicon and germanium diodes.4) (2. The resulting direction of I is a match with the arrow in the diode symbol. In general. 2. The resulting voltage and current levels are the following: VD VR ID E IR VT VT VR R (2. of course. 2. and since E VT the diode is in the “on” state.12 Substituting the equivalent model for the “on” diode of Fig. the diode symbol will appear as shown in Fig.6) Figure 2. The state of the diode is first determined by mentally replacing the diode with a resistive element as shown in Fig. however.In the next few sections we demonstrate the impact of the models of Table 2. + E I R + VR – – Figure 2. or the network can be redrawn with the VT equivalent circuit as defined in Table 2. 2.

Since VR IRR.14 will reveal that the resulting current direction does not match the arrow in the diode symbol.13. VR. ac instantaneous values.7. we find that the direction of I is opposite to the arrow in the diode symbol and the diode equivalent is the open circuit no matter which model is employed. 2. 2.2 k ID 3. determine VD.14 Determining the state of the diode of Fig.32 mA EXAMPLE 2. VD VR Figure 2.6 For the series diode configuration of Fig.16.17 Determining the unknown quantities for Example 2. pulses. The diode is in the “off” state. 2. and VD E 60 Chapter 2 Diode Applications . The result is the network of Fig. Mentally replacing the diode with a resistive element as shown in Fig. In Fig.10. 2. Solution Since the applied voltage establishes a current in the clockwise direction to match the arrow of the symbol and the diode is in the “on” state.17.15. Applying Kirchhoff’s voltage law around the closed loop yields E VD VR E VR 0 0 E 8V Figure 2. 0. Always keep in mind that under any circumstances—dc. and so on—Kirchhoff’s voltage law must be satisfied! EXAMPLE 2. Figure 2.2 kΩ VR – Removing the diode. resulting in the equivalent circuit of Fig. Figure 2.16 Circuit for Example 2. 2. the diode current is 0 A and the voltage across the resistor R is the following: VR I RR ID R (0 A)R 0V The fact that VR 0 V will establish E volts across the open circuit as defined by Kirchhoff’s voltage law. and ID.13 the diode of Fig.13. where ID 0 A due to the open circuit.7 V E IR VD VR R 8V 0. 2.13 Reversing the diode of Fig.Figure 2.15 Substituting the equivalent model for the “off” diode of Figure 2. 2.6. 2. Due to the open circuit. Solution + VD – IR = 0 A + E 8V R 2.3 V 7.6 with the diode reversed.7 V 7. VR (0)R 0 V.10 has been reversed.7 ID = 0 A Repeat Example 2.3 V 2.

In particular.” The point of operation on the characteristics is shown in Fig.20.19 Series diode circuit for Example 2.5 V. keep the following in mind for the analysis to follow: 1. The resulting voltage and current levels are therefore the following: ID VR and VD 0A IRR E ID R 0. It is a common industry notation and one with which the reader should become very familiar. the level of applied voltage is insufficient to turn the silicon diode “on. VR. but the voltage is significant. determine VD. The current is zero. establishing the opencircuit equivalent as the appropriate approximation. 2. 2. and ID. Such notation and other defined voltage levels are treated further in Chapter 4.18 will be employed for the applied voltage. Solution Although the “pressure” establishes a current with the same direction as the arrow symbol.19. In the next example the notation of Fig. 2.20 Operating point with E 0. For the series diode configuration of Fig. An open circuit can have any voltage across its terminals. 2.4 Series Diode Configurations with DC Inputs 61 .7 the high voltage across the diode even though it is an “off” state.5 V (0 A)1. A short circuit has a 0-V drop across its terminals. but the current is always 0 A. E = + 10 V +10 V E = –5 V –5 V E 10 V E 5V Figure 2. EXAMPLE 2.2 k 0V Figure 2. For review purposes.18 Source notation.8. but the current is limited only by the surrounding network.8 Figure 2. note in Example 2. 2.

6 kΩ Vo – Figure 2.3 V 1. 62 Chapter 2 Diode Applications . The resulting voltage Vo and E ID VT IR 1 VT VR R 2 12 V Vo R 0. as shown in Fig. 2. Note the redrawn supply of 12 V and the polarity of Vo across the 5.22 Determining the unknown quantities for Example 2. I E R + 5.24 Determining the state of the diodes of Figure 2. An attack similar to that applied in Example 2. Figure 2.7 V 11 V 5.10 Determine ID.3 V) 1 V.10.22 results because E 12 V (0. Removing the diodes and determining the direction of the resulting current I will result in the circuit of Fig.EXAMPLE 2. 2.25.9.23. and the network of Fig.9.6-k resistor.25 Substituting the equivalent state for the open diode.21. Solution Figure 2.6 kΩ Solution Figure 2.24. + Si +12 V ID VD 2 – IR Vo Si 5.96 mA 11 V Figure 2. and Vo for the circuit of Fig. The combination of a short circuit in series with an open circuit always results in an open circuit and ID 0 A.21 Circuit for Example 2.23. There is a match in current direction for the silicon diode but not for the germanium diode.7 V 0.6 will reveal that the resulting current has the same direction as the arrowheads of the symbols of both diodes. 2. EXAMPLE 2. 2.6 k 0. 2.23 Circuit for Example 2. VD2.9 Determine Vo and ID for the series circuit of Fig.

Note that the “on” state is noted simply by the additional VD 0.28 Determining the state of the diode for the network of Fig. 2. V1. Solution The sources are drawn and the current direction indicated as shown in Fig. simply recall for the actual practical diode that when ID 0 A.26. V2.29 Determining the unknown quantities for the network of Fig. 2.11. as described for the no-bias situation in Chapter 1.11 Figure 2. and Vo for the series dc configuration of Fig. The conditions described by ID 0 A and VD1 0 V are indicated in Fig. Figure 2.28.10. Figure 2. VD 0 V (and vice versa).27.The question remains as to what to substitute for the silicon diode. 2.4 Series Diode Configurations with DC Inputs 63 . For the analysis to follow in this and succeeding chapters. 2. 2.27.29 is included to indicate this state. Vo and VD 2 I RR IDR (0 A)R E 0V 12 V Vopen circuit E VD VD Vo Applying Kirchhoff’s voltage law in a clockwise direction gives us 1 2 Vo 12 V 0 0 0 and VD 2 E VD 1 12 V with Vo 0V Determine I.26 Determining the unknown quantities for the circuit of Example 2. 2.27. 2.7 V Figure 2.27 Circuit for Example 2. EXAMPLE 2. The diode is in the “on” state and the notation appearing in Fig.

In time the entire analysis will be performed simply by referring to the original network.7 V 4. As indicated in the introduction to this section.4 can be extended to the analysis of parallel and series–parallel configurations.7 k 2.9 k 2. ID1. 2.12 Determine Vo. For each area of application. 2. both diodes are in the “on” state. I1.2 k 14.30 Network for Example 2.30. The voltage across parallel elements is always the same and Vo 64 Chapter 2 Diode Applications 0.7 V.31. Figure 2. This eliminates the need to redraw the network and avoids any confusion that may result from the appearance of another source. I E1 R1 E2 R2 VD 10 V 5 V 0. 2.27.56 V Vo 0 5V 0. The resulting current through the circuit is. Since the resulting current direction matches that of the arrow in each diode symbol and the applied voltage is greater than 0.7 k ) (2.7 V . Recall that a reverse-biased diode can simply be indicated by a line through the device.3 V 6. simply match the sequential series of steps applied to series diode configurations. EXAMPLE 2. Solution For the applied voltage the “pressure” of the source is to establish a current through each diode in the same direction as shown in Fig.12.072 mA and the voltages are V1 V2 IR1 IR2 (2.74 V 4.on the figure.072 mA)(4.072 mA)(2. and ID2 for the parallel diode configuration of Fig.2 k ) 9.44 V The minus sign indicates that Vo has a polarity opposite to that appearing in Fig.56 V Applying Kirchhoff’s voltage law to the output section in the clockwise direction will result in E2 and Vo V2 E2 V2 4. this is probably the path and notation that one will take when a level of confidence has been established in the analysis of diode configurations.5 PARALLEL AND SERIES–PARALLEL CONFIGURATIONS The methods applied in Section 2. 2.

2.32.95 mA Figure 2. The resulting current I is then I E1 E2 R VD 20 V 4V 2.5 Parallel and Series–Parallel Configurations 65 . Solution Redrawing the network as shown in Fig. a current of 28. we have ID 1 ID 2 I1 2 28.09 mA with the same terminal voltage.7 V 0.Figure 2.30. 2. the current is limited to a safe value of 14.09 mA Example 2. 2.12.31 Determining the unknown quantities for the network of Example 2. 2. If the current rating of the diodes of Fig.2 k 0.30 is only 20 mA.18 mA would damage the device if it appeared alone in Fig.13.33 k 28. By placing two in parallel.13.32 Network for Example 2.18 mA 2 14.12 demonstrated one reason for placing diodes in parallel.18 mA Assuming diodes of similar characteristics. EXAMPLE 2.13 Figure 2.33 reveals that the resulting current direction is such as to turn on diode D1 and turn off diode D2.7 V 6.33 Determining the unknown quantities for the network of Example 2. Determine the current I for the network of Fig. The current I1 VR R E R VD 10 V 0. 2.

” However.3 V is established across the germanium diode it will turn “on” and maintain a level of 0. 2.14 12 V Determine the voltage Vo for the network of Fig.37 Determining the unknown quantities for Example 2.3 V 11. The resulting action can be explained simply by realizing that when the supply is turned on it will increase from 0 to 12 V over a period of time—although probably measurable in milliseconds.15. 2.37. as noted by the resulting current directions in the network of Fig.3 k 0. The result: Vo 12 V 0.EXAMPLE 2.” the 0. At the instant during the rise that 0.36 Network for Example 2. and ID2 for the network of Fig.35 Determining Vo for the network of Fig.34 ple 2. 2. Solution The applied voltage (pressure) is such as to turn both diodes on. I1 Figure 2.14.3 V.7 V 3. 2.34.2 kΩ Figure 2. Solution Initially. The silicon diode will never have the opportunity to capture its required 0.36. EXAMPLE 2.7-V drop across the silicon diode would not match the 0. VT R1 2 0.7 V Si Ge Vo 2. Network for Exam- Figure 2.7 V and therefore remains in its open-circuit state as shown in Fig.34. Note the use of the abbreviated notation for “on” diodes and that the solution is obtained through an application of techniques applied to dc series—parallel networks. 2.212 mA Figure 2.35.15 Determine the currents I1. I2. 66 Chapter 2 Diode Applications . if both were “on.15. it would appear that the applied voltage will turn both diodes “on.3 V across the germanium diode as required by the fact that the voltage across parallel elements must be the same.

6 And/Or Gates + D1 – E 10 V Vo D2 R 0V 1 kΩ Figure 2.38 is assigned a “1” for Boolean algebra while the 0-V input is assigned a “0.38.38 Positive logic OR gate. The next step is simply to check that there is no contradiction to our assumptions. 2. as shown in the redrawn network of Fig. and our initial analysis can be assumed to be correct. For D1 the “on” state establishes Vo at Vo E VD 10 V 0.7 V 9.16 is an OR gate for positive logic. Our assumptions seem confirmed by the resulting voltages and current. D2 is definitely in the “off” state. The output is therefore at a 1 level with only one input. Figure 2. ID2 and ID2 I2 I1 3. 2. The network to be analyzed in Example 2. 10 V at terminal 1. With 9.39 Redrawn network of Fig. EXAMPLE 2. In general.3 V at the cathode ( ) side of D2 and 0 V at the anode ( ) side. note that the polarity across D1 is such as to turn it on and the polarity across D2 is such as to turn it off.3 V for Ge) to switch to the “on” state.7 V positive for the silicon diode (0. Our analysis will be limited to determining the voltage levels and will not include a detailed discussion of Boolean algebra or positive and negative logic. Terminal 2 with a 0-V input is essentially at ground potential.108 mA V2 E VT 1 E 2 VT 1 VT 2 0 0.3 V.212 mA 3. the 10-V level of Fig. The output voltage level is not 10 V as defined for an input of 1. 2. That is. which suggests that 2.6 V 5.7 V 18.40. 2.39.Applying Kirchhoff’s voltage law around the indicated loop in the clockwise direction yields V2 and with At the bottom node (a). 67 . but the 9.6 k 0. The current direction and the resulting continuous path for conduction further confirm our assumption that D1 is conducting.7 V I2 V2 R2 3.6 AND/OR GATES The tools of analysis are now at our disposal. The analysis will then verify or negate your initial assumptions.3 V is sufficiently large to be considered a 1 level. Figure 2. the best approach is simply to establish a “gut” feeling for the state of the diodes by noting the direction and the “pressure” established by the applied potentials.32 mA I1 I2 0.” Assuming these states will result in the configuration of Fig. That is.39 “suggests” that D1 is probably in the “on” state due to the applied 10 V while D2 with its “positive” side at 0 V is probably “off.” An OR gate is such that the output voltage level will be a 1 if either or both inputs is a 1. The analysis of AND/OR gates is made measurably easier by using the approximate equivalent for a diode rather than the ideal because we can stipulate that the voltage across the diode must be 0.16 Solution First note that there is only one applied potential.6 V VT 20 V 18. Determine Vo for the network of Fig.38. 2.32 mA 2. and the opportunity to investigate a computer configuration is one that will demonstrate the range of applications of this relatively simple device. The output is a 0 if both inputs are at the 0 level.

2.42 the voltage at Vo is 0.7 V at the anode of D1 and 10 V at the cathode. D1 is definitely in the “off” state.7 V come from if the input and source voltages are at the same level and creating opposing “pressures”? D2 is assumed to be in the “on” state due to the low voltage at the cathode side and the availability of the 10-V source through the 1-k resistor.17 (1) E1 = 10 V Si 1 D1 Si 2 Vo D2 R 1 kΩ Determine the output level for the positive logic AND gate of Fig.41. 2. However. 2. 2.7V E 10 V Figure 2.41.38.3 mA (0) E2 = 0 V E 10 V Figure 2. Solution Note in this case that an independent source appears in the grounded leg of the network.40 Assumed diode states for Fig.7 V 1k 9. For reasons soon to become obvious it is chosen at the same level as the input logic level. 2. and the output will be a 0 due to the 0-V output level. recall that we mentioned in the introduction to this section that the use of the approximate model will be an aid to the analysis.7 V required to turn the diodes on. 68 Chapter 2 Diode Applications .7 V (0) 0.7 V due to the forward-biased diode D2. With 0. Positive logic AND – (1) E1 10 V (0) I VD + R 1 kΩ Vo = VD = 0. where will the 0.42 Substituting the assumed states for the diodes of Fig. For D1.40 the current level is determined by I E R VD 10 V 0. For the network of Fig.42 with our initial assumptions regarding the state of the diodes. The network is redrawn in Fig. the gate is an OR gate. 2.41 gate. A 0-V input at both inputs will not provide the 0. The current I will have the direction indicated in Fig.42 and a magnitude equal to I E R VD 10 V 0. For the network of Fig.7 V 1k 9. An analysis of the same network with two 10-V inputs will result in both diodes being in the “on” state and an output of 9.3 V.3 mA EXAMPLE 2.Figure 2. With 10 V at the cathode side of D1 it is assumed that D1 is in the “off” state even though there is a 10-V source connected to the anode of D1 through the resistor. 2.

The circuit of Fig. 2. the output voltage is sufficiently small to be considered a 0 level. such as computers and communication systems. Its power and current ratings are typically much higher than those of diodes employed in other applications.43 Half-wave rectifier. Substituting the short-circuit equivalence for the ideal diode will result in the equivalent circuit of Fig. therefore. use in the ac-to-dc conversion process. 2. The remaining states of the diodes for the possibilities of two inputs and no inputs will be examined in the problems at the end of the chapter. 2. When employed in the rectification process.7 SINUSOIDAL INPUTS. a single input will result in a 0-level output. For the AND gate. a diode is typically referred to as a rectifier.The state of the diodes is therefore confirmed and our earlier analysis was correct.43. 2. the average value (the algebraic sum of the areas above and below the axis) is zero. The simplest of networks to examine with a time-varying signal appears in Fig. 2. Over one full cycle. will generate a waveform vo that will have an average value of particular. but once a few fundamental maneuvers are understood. For the moment we will use the ideal model (note the absence of the Si or Ge label to denote ideal diode) to ensure that the approach is not clouded by additional mathematical complexity. Although not 0 V as earlier defined for the 0 level. Half-Wave Rectification 69 . There is no question that the degree of difficulty will increase.43. defined by the period T of Fig. where it is fairly obvious that the output signal is an exact replica of the applied signal. HALF-WAVE RECTIFICATION The diode analysis will now be expanded to include time-varying functions such as the sinusoidal waveform and the square wave. + + vi – + R vo + vi R + vo = vi vo Vm – Figure 2. called a half-wave rectifier.44 – – – 0 T 2 t Conduction region (0 → T/2). The two terminals defining the output voltage are connected directly to the applied signal via the short-circuit equivalence of the diode. 2. the analysis will be fairly direct and follow a common thread.44. 2. During the interval t 0 → T/2 in Fig.43 the polarity of the applied voltage vi is such as to establish “pressure” in the direction indicated and turn on the diode with the polarity appearing above the diode.43. vi Vm + + T t vi – + R vo 0 T 2 1 cycle – – vi = Vm sin ωt Figure 2.7 Sinusoidal Inputs.

which naturally reduces vi + Vm VT – + R vo 0 vo + VT = 0.7 V. When conducting. the polarity of the input vi is as shown in Fig.7 V 0 T 2 – – T 2 Offset due to VT Tt Figure 2. 2.For the period T/2 → T. The output signal vo now has a net positive area above the axis over a full period and an average value determined by Vdc 0.45 and the resulting polarity across the ideal diode produces an “off” state with an open-circuit equivalent. vi Vm Vdc = 0 V 0 t vo Vm Vdc = 0. The result is the absence of a path for charge to flow and vo iR (0)R 0 V for the period T/2 → T. the diode is still in an opencircuit state and vo 0 V as shown in the same figure. 2.7 V t T vi Vm – VT 0. 2.7 V is demonstrated in Fig.7) – – vi + + R vo – vi R + vo = 0 V vo vo = 0 V 0 T 2 T t + Figure 2. The net effect is a reduction in area above the axis.7 V before the diode can turn “on. The applied signal must now be at least 0. The effect of using a silicon diode with VT 0.46 signal.318Vm half-wave (2.318Vm 0 T t Figure 2.47 for the forward-bias region.47 Effect of VT on half-wave rectified signal. the difference between vo and vi is a fixed level of VT 0.7 V and vo vi VT . The input vi and the output vo were sketched together in Fig.” For levels of vi less than 0. Half-wave rectified The process of removing one-half the input signal to establish a dc level is aptly called half-wave rectification. as shown in the figure. 70 Chapter 2 Diode Applications .46 for comparison purposes.45 – + – Nonconduction region (T/2 → T).

2.49 Resulting vo for the circuit of Example 2.3 V) 63.318Vm 0.318(200 V 0. Eq.7 V) 0.18.49. (b) Using a silicon diode.8) In fact. 2. Half-Wave Rectification 71 . vi 20 V EXAMPLE 2.50 Effect of VT on output of Fig. 0 T 2 T t 20 V – 0.3 V) 6. Eq.36 V The negative sign indicates that the polarity of the output is opposite to the defined polarity of Fig.50 and Vdc 0. (c) Repeat parts (a) and (b) if Vm is increased to 200 V and compare solutions using Eqs.318(Vm VT) (2.14 V vo The resulting drop in dc level is 0.6 V (c) Eq. For part c the offset and drop in amplitude due to VT would not be discernible on a typical oscilloscope if the full pattern is displayed. 2.3 V Figure 2.8 can be applied to determine the average value with a relatively high level of accuracy. (2. 0.48 ple 2.49. (a) Sketch the output vo and determine the dc level of the output for the network of Fig. if Vm is sufficiently greater than VT. 2. the dc level is Vdc 0.318(200 V) 63. vi 20 – – T 20 t vi + + 2 kΩ vo 0 vo 0 T 2 + – T 2 T 20 V t Figure 2.18 + vi T t R 2 kΩ + vo 0 T 2 – – Figure 2.318(Vm VT) 0. Vdc 0.8): Vdc (0. Network for Exam- Solution (a) In this situation the diode will conduct during the negative part of the input as shown in Fig.318Vm 0. 2. and vo will appear as shown in the same figure.7 is often applied as a first approximation for Vdc.the resulting dc voltage level.7 Sinusoidal Inputs. (2. 2.7): Vdc 0.18.48. For the full period.38 V which is a difference that can certainly be ignored for most applications.7) and (2.318(20 V) 6.7 V) Eq.318)(199.7 V = 19.318(Vm 0. the output has the appearance of Fig.8).5%. For situations where Vm VT. (2.22 V or about 3.48. 2. 2. (b) Repeat part (a) if the ideal diode is replaced by a silicon diode.318(19.

51. Therefore. 2. PIV rating Vm half-wave rectifier (2.PIV (PRV) The peak inverse voltage (PIV) [or PRV (peak reverse voltage)] rating of the diode is of primary importance in the design of rectification systems.52 for the period 0 → T/2 of the input voltage vi.53 Network of Fig.54 Conduction path for the positive region of vi. The net result is the configuration of Fig. 2.8 FULL-WAVE RECTIFICATION Bridge Network The dc level obtained from a sinusoidal input can be improved 100% using a process called full-wave rectification. 2. 2. The required PIV rating for the half-wave rectifier can be determined from Fig.54.52 with its four diodes in a bridge configuration.9) – – Vm V (PIV) + – R Vo = IR = (0)R = 0 V I= 0 + + Figure 2. 2. 72 Chapter 2 Diode Applications . 2. 2. Recall that it is the voltage rating that must not be exceeded in the reverse-bias region or the diode will enter the Zener avalanche region. During the period t 0 to T/2 the polarity of the input is as shown in Fig.53 to reveal that D2 and D3 are conducting while D1 and D4 are in the “off” state. 2. with its indicated current and polarity across R. Figure 2.53. as shown in the same figure. The resulting polarities across the ideal diodes are also shown in Fig. The most familiar network for performing such a function appears in Fig.52 Full-wave bridge rectifier.51 Determining the required PIV rating for the halfwave rectifier. Applying Kirchhoff”s voltage law. vo Vm + – vo R + + "on" – + – "on" – + vi Vm + vi R – – "off " 0 T 2 t – – vo + 0 T 2 t Figure 2. which displays the reverse-biased diode of Fig. vi Vm vi + D1 D2 – vo R + 0 T 2 T t – + vi "off " D3 D4 Figure 2. Since the diodes are ideal the load voltage is vo vi.43 with maximum applied voltage. it is fairly obvious that the PIV rating of the diode must equal or exceed the peak value of the applied voltage.

636Vm 2(0.55 vi Vm Conduction path for the negative region of vi. 2.53.7 V 2VT) (2.For the negative region of the input the conducting diodes are D1 and D4. 2. establishing a second positive pulse. vi – vi t vo Vm – vo R + 0 T 2 T t 0 T 2 T Vm + Figure 2. 2. The important result is that the polarity across the load resistor R is the same as in Fig. (2. if Vm is sufficiently greater than 2VT. 2. 2. resulting in the configuration of Fig.57. Vdc 0.11) + vi + – + vo – Vm – 2VT 0 T 2 T t + Figure 2. as shown in Fig. then Eq.10) If silicon rather than ideal diodes are employed as shown in Fig. 2.10) is often applied as a first approximation for Vdc. Eq.636Vm 0 T 2 T t 0 T 2 T t Figure 2.11) can be applied for the average value with a relatively high level of accuracy. Over one full cycle the input and output voltages will appear as shown in Fig. the dc level has also been doubled and Vdc or Vdc 2(Eq. an application of Kirchhoff’s voltage law around the conduction path would result in vi and VT vo Vomax vo vi Vm VT 2VT 2VT 0 The peak value of the output voltage vo is therefore For situations where Vm 2VT.57 Determining Vomax for silicon diodes in the bridge configuration.318Vm) full-wave (2. R VT = 0.636(Vm vo VT = 0. (2.56 Input and output waveforms for a full-wave rectifier.55. vo Vm Vdc = 0. 2.56.55.7 V – – Then again.7) 0. Since the area above the axis for one full cycle is now twice that obtained for a half-wave system.8 Full-Wave Rectification 73 .

60. as determined by the secondary voltages and the resulting current directions.PIV The required PIV of each diode (ideal) can be determined from Fig. A second popular full-wave rectifier appears in Fig. 1:2 vi Vm D1 + vi + 0 t vi – CT R – + vi – vo + – D2 1:2 Figure 2. D1 assumes the short-circuit equivalent and D2 the open-circuit equivalent. 2.59 with only two diodes but requiring a center-tapped (CT) transformer to establish the input signal across each section of the secondary of the transformer. 74 Chapter 2 Diode Applications .12) Center-Tapped Transformer Figure 2. For the indicated loop the maximum voltage across R is Vm and the PIV rating is defined by PIV Vm full-wave bridge rectifier (2.58 Determining the required PIV for the bridge configuration. During the positive portion of vi applied to the primary of the transformer. 2.61.59 Center-tapped transformer full-wave rectifier. During the negative portion of the input the network appears as shown in Fig.58 obtained at the peak of the positive region of the input signal. The output voltage appears as shown in Fig.60.60 Network conditions for the positive region of vi. 2. 2. the network will appear as shown in Fig.61 Network conditions for the negative region of vi. vi Vm + + – CT vo Vm Vm 0 T 2 t vi – Vm vo R + 0 T 2 t – + – – + Figure 2. reversing the roles of the diodes but maintaining the same polarity for the voltvi – – + CT – + Vm R vo Vm 0 T 2 T Vm t vi + – – Vm vo + 0 T 2 T t + Figure 2. 2.

2. 2. 2.64. 2.62 Determining the PIV level for the diodes of the CT transformer full-wave rectifier.19. CT transformer.636(5 V) 3.58 is equal to the maximum voltage across R.63 Bridge network for Example 2. 2. vi 10 V + + – 2 kΩ vi vi t + 2 kΩ vo + vo 5V 2 kΩ 0 T 2 t – 2 kΩ 0 T 2 – 2 kΩ vo + 2 kΩ – Figure 2.19. vi 10 V vi 0 T 2 T t 2 kΩ EXAMPLE 2. The net effect is the same output as that appearing in Fig. 2. However.64 for the positive region of the input voltage.65. PIV The network of Fig.13) VR Figure 2. Redrawing the network will result in the configuration of Fig. Inserting the maximum voltage for the secondary voltage and Vm as established by the adjoining loop will result in PIV Vsecondary Vm and PIV 2Vm Vm (2.65 Redrawn network of Fig.66 Resulting output for Example 2.19 + – 2 kΩ vo + 2 kΩ – Solution Figure 2. For the negative 2 2 2 part of the input the roles of the diodes will be interchanged and vo will appear as shown in Fig.66. where vo 1 vi or Vomax 1 Vi max 1 (10 V) 5 V. full-wave rectifier Determine the output waveform for the network of Fig. 2. 2.63 and calculate the output dc level and the required PIV of each diode.56 with the same dc levels. 2. The network will appear as shown in Fig. the PIV as determined from Fig.age across the load resistor R. 2. 2. as shown in Fig. Network of Fig. which is 5 V or half of that required for a half-wave rectifier with the same input. – Figure 2.8 Full-Wave Rectification 75 .65. T 2 T t Figure 2.64 region of vi.18 V 0 vo 5V or that available from a half-wave rectifier with the same input.62 will help us determine the net PIV for each diode for this full-wave rectifier.63 for the positive The effect of removing two diodes from the bridge configuration was therefore to reduce the available dc level to the following: Vdc 0.

2. The dc supply further requires that the voltage vi be greater than V volts to turn the diode on.68 a dc supply. 1. There are two general categories of clippers: series and parallel. The negative region of the input signal is 76 Chapter 2 Diode Applications . The series configuration is defined as one where the diode is in series with the load. Depending on the orientation of the diode.67a to a variety of alternating waveforms is provided in Fig. there are no boundaries on the type of signals that can be applied to a clipper. with the effect of VT reserved for a concluding example.67 Series clipper. The addition of a dc supply such as shown in Fig. 2. For the network of Fig.68. 2. Series The response of the series configuration of Fig.7 is an example of the simplest form of diode clipper—one resistor and diode. Our initial discussion will be limited to ideal diodes. the direction of the diode suggests that the signal vi must be positive to turn it on.9 CLIPPERS There are a variety of diode networks called clippers that have the ability to “clip” off a portion of the input signal without distorting the remaining part of the alternating waveform. Series clipper with There is no general procedure for analyzing networks such as the type in Fig. Although first introduced as a half-wave rectifier (for sinusoidal waveforms). Make a mental sketch of the response of the network based on the direction of the diode and the applied voltage levels.2. 2. while the parallel variety has the diode in a branch parallel to the load. but there are a few thoughts to keep in mind as you work toward a solution. + vi R + vo – (a) – vi V V vo V vi V vo 0 –V t t –V (b) t t Figure 2. the positive or negative region of the input signal is “clipped” off. 2.68.68 can have a pronounced effect on the output of a clipper. Figure 2. The half-wave rectifier of Section 2.67b.

and the complete curve At vi V the diodes change state.14) V + vd = 0 V – id = 0 A + vi R + vo = iRR = id R = (0)R = 0 V – – Figure 2. the network to be analyzed appears in Fig. such as shown in Fig. Be continually aware of the defined terminals and polarity of vo. where it is recognized that the level of vi that will cause a transition in state is vi V (2. we can be quite sure that the diode is an open circuit (“off” state) for the negative region of the input signal.15) Figure 2. supported further by the dc supply. therefore. Figure 2.72. 2. 2.“pressuring” the diode into the “off” state. 2.69 Determining the transition level for the circuit of Fig. 2. Vm.68 will result in the configuration of Fig. In general. 3. For Vm V the diode is in the short-circuit state and vo Vm V. vo 0 V. For an input voltage greater than V volts the diode is in the short-circuit state. vi Vm V 0 T 2 T t 0 T 2 T t vo Vm – V Figure 2. 4. 2.69. at vi for vo can be sketched as shown in Fig. Applying the condition id 0 at vd 0 to the network of Fig. It can be helpful to sketch the input signal above the output and determine the output at instantaneous values of the input.73 Sketching vo. For instance. 2. When the diode is in the short-circuit state.72 Determining vo when vi Vm.68. 2. Determining vi = V (diodes change state) Figure 2.73. It is then possible that the output voltage can be sketched from the resulting data points of vo as demonstrated in Fig.70. For the ideal diode the transition between states will occur at the point on the characteristics where vd 0 V and id 0 A.9 Clippers 77 . Keep in mind that at an instantaneous value of vi the input can be treated as a dc supply of that value and the corresponding dc value (the instantaneous value) of the output determined. 2. 2.71 levels of vo. at vi Vm for the network of Fig.71. as shown in Fig. 2.68. the output voltage vo can be determined by applying Kirchhoff’s voltage law in the clockwise direction: vi and V vo vo 0 (CW direction) vi V (2.71. Determine the applied voltage (transition voltage) that will cause a change in state for the diode.70 Determining vo. 2. while for input voltages less than V volts it is in the open-circuit or “off” state.

76 Determining the transition level for the clipper of Fig.EXAMPLE 2. 2. 78 Chapter 2 Diode Applications .74. For vi more negative than 5 V the diode will enter its open-circuit state. the network can be analyzed as if it had two dc level inputs with the resulting output vo plotted in the proper time frame.20.75 and vo vi 5 V. 2. Solution Past experience suggests that the diode will be in the “on” state for the positive region of vi —especially when we note the aiding effect of V 5 V. 2. 2. the transition levels. while for voltages more positive than 5 V the diode is in the short-circuit state.20. Substituting id 0 at vd 0 for 5 V. The analysis of clipper networks with square-wave inputs is actually easier to analyze than with sinusoidal inputs because only two levels have to be considered.74. vi 20 5V –5V T 2 T t 0 T 2 T vo vi + 5 V = 20 V + 5 V = 25 V vo = 0 V + 5 V = 5 V t Transition voltage vo = –5 V + 5 V = 0 V Figure 2. The input and output voltages appear in Fig. – + + vi vd = 0 V 5 V id = 0 A R + vo = vR = iR R = id R = (0) R = 0 V – – Figure 2. we obtain the network of Fig.76 and vi Figure 2.77 Sketching vo for Example 2. In other words.75 vo with diode in the “on” state.20 Determine the output waveform for the network of Fig. The network will then appear as shown in Fig.77.74 Series clipper for Example 2. 2. Figure 2.

21 that the clipper not only clipped off 5 V from the total swing but raised the dc level of the signal by 5 V. + 20 V – 5V + R + vo – 10 V – + 5V R + vo = 0 V – Figure 2.79 vo at vi 20 V. + vi R + vo – vi V t t vo V – vi vo 0 –V 0 –V 0 –V t 0 –V t Figure 2. 2. – + Figure 2.82 is the simplest of parallel diode configurations with the output for the same inputs of Fig. For vi will result.80 vo at vi 10 V. 2. 2.9 Clippers 79 .79 will result.Repeat Example 2. as demonstrated in the next example. 2. Solution For vi 20 V (0 → T/ 2) the network of Fig. Parallel The network of Fig.81. Note in Example 2. 2. placing the diode in the “off” state and vo iRR (0)R 0 V.20 for the square-wave input of Fig.78 Applied signal for Example 2.82 Response to a parallel clipper.21.78.21 Figure 2. 2. – Figure 2. 2. The resulting output voltage appears in Fig.21.80 circuit state and vo 20 V 5 V 25 V.81 Sketching vo for Example 2. The analysis of parallel configurations is very similar to that applied to series configurations. The diode is in the short10 V the network of Fig. EXAMPLE 2.67.

85 Determining the transition level for Example 2.86.86 Determining vo for the open state of the diode. Figure 2.84 region of vi. Any input voltage less than 4 V will result in a short-circuited diode. the next example will specify a silicon diode rather than an ideal diode equivalent. 2. the input voltage must be greater than 4 V for the diode to be in the “off” state. 2. Figure 2. where the condition id 0 A at vd 0 V has been imposed. where the defined terminals for vo require that vo V 4 V. – vi R + vo = V = 4 V V 4V + – Figure 2.83 Example 2. Figure 2. Figure 2.22.2 Determine vo for the network of Fig.83.87. To examine the effects of VT on the output voltage. The result is vi (transition) V 4 V. Since the dc supply is obviously “pressuring” the diode to stay in the shortcircuit state. 80 Chapter 2 Diode Applications . Solution The polarity of the dc supply and the direction of the diode strongly suggest that the diode will be in the “on” state for the negative region of the input signal.87 Sketching vo for Example 2.EXAMPLE 2. 2. For the open-circuit state the network will appear as shown in Fig. where vo vi. 2. vo for the negative The transition state can be determined from Fig.22. 2.84. For this region the network will appear as shown in Fig. Completing the sketch of vo results in the waveform of Fig.85.22.

The resulting output waveform appears in Fig. Note that the only effect of VT was to drop the transition level to 3. note the response of the last configuration. including the effects of VT.3 V. There is no question that including the effects of VT will complicate the analysis somewhat. will not be that difficult.7 V 3. 2. but once the analysis is understood with the ideal diode. For input voltages of less than 3. For input voltages greater than 3.22 using a silicon diode with VT 0. we find that vi and vi V VT VT 4V V 0 0.3 V Figure 2.90 Sketching vo for Example 2. EXAMPLE 2. 2.9 Clippers 81 .89 results.88 Determining the transition level for the network of Fig. where vo 4V 0.90. the diode will be in the “on” state and the network of Fig. 2. Applying Kirchhoff’s voltage law around the output loop in the clockwise direction.7 V 3. Figure 2. with its ability to clip off a positive and a negative section as determined by the magnitude of the dc supplies.23.89 Determining vo for the diode of Fig.3 V. 2. 2.7 V.88.83.83 in the “on” state. the diode will be an open circuit and vo vi.91. Summary A variety of series and parallel clippers with the resulting output for the sinusoidal input are provided in Fig. the procedure.Repeat Example 2. 2.7 V and obtaining the network of Fig.3 V Figure 2. 2.3 from 4 V.23 Solution The transition voltage can first be determined by applying the condition id 0 A at vd VD 0. In particular.

91 Clipping circuits. 82 Chapter 2 Diode Applications .Figure 2.

Throughout the analysis we will assume that for all practical purposes the capacitor will fully charge or discharge in five time constants. it can also be drawn in the alternative position shown in Fig. The resulting RC time constant is so small (R determined by the inherent resistance of the network) that the capacitor will charge to V volts very quickly. Applying Kirchhoff’s voltage law around the input loop will result in V and vo V vo 2V 0 Figure 2. For a clamping network: The total swing of the output is equal to the total swing of the input signal.95 Sketching vo for the network of Fig. Figure 2. 2.2. Since vo is in parallel with the diode and resistor.92 will clamp the input signal to the zero level (for ideal diodes).10 CLAMPERS The clamping network is one that will “clamp” a signal to a different dc level. 2.” The negative sign resulting from the fact that the polarity of 2V is opposite to the polarity defined for vo. 2. the network will appear as shown in Fig. During this interval the output voltage is directly across the short circuit and vo 0 V. and a resistive element.95 with the input signal.93 Diode “on” and the capacitor charging to V volts. The resulting output waveform appears in Fig. Now that R is back in the network the time constant determined by the RC product is sufficiently large to establish a discharge period 5 much greater than the period T/2 → T. When the input switches to the V state. 83 . with the open-circuit equivalent for the diode determined by the applied signal and stored voltage across the capacitor—both “pressuring” current through the diode from cathode to anode. During the interval 0 → T/2 the network will appear as shown in Fig. This fact is an excellent checking tool for the result obtained.92 Clamper. a diode.94. but it can also employ an independent dc supply to introduce an additional shift. 2.94. 2. In general. 2. Start the analysis of clamping networks by considering that part of the input signal that will forward bias the diode. the following steps may be helpful when analyzing clamping networks: 1. The resistor R can be the load resistor or a parallel combination of the load resistor and a resistor designed to provide the desired level of R. with the diode in the “on” state effectively “shorting out” the effect of the resistor R. voltage (since V Q/C) during this period.92. therefore.10 Clampers Figure 2. 2. The magnitude of R and C must be chosen such that the time constant RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval the diode is nonconducting. The network must have a capacitor. C + V + V – R + vo – – Figure 2. The network of Fig.94 Determining vo with the diode “off. The output signal is clamped to 0 V for the interval 0 to T/2 but maintains the same total swing (2V) as the input.93. and it can be assumed on an approximate basis that the capacitor holds onto all its charge and.

4. Assume that during the period when the diode is in the “off” state the capacitor will hold on to its established voltage level.96 for the input indicated. The analysis will begin with the period t1 → t2 of the input signal since the diode is in its short-circuit state as recommended by comment 1. In this case the resistor R is not shorted out by the diode but a Thévenin equivalent circuit of that portion of the network which includes the battery and the resistor will result in RTh 0 with ETh V 5 V. but it is also directly across the 5-V battery if you follow the direct connection between the defined terminals for vo and the battery terminals. 2. The output is across R.98 Determining vo with the diode in the “off” state. 2.97 Determining vo and VC with the diode in the “on” state. but the analysis will not be extended by an unnecessary measure of investigation. For the period t2 → t3 the network will appear as shown in Fig.96 Applied signal and network for Example 2. 2. Applying Kirchhoff’s voltage law around the input loop will result in 20 V and VC VC 5V 0 Figure 2.5 ms between levels. Keep in mind the general rule that the total swing of the total output must match the swing of the input signal. 25 V The capacitor will therefore charge up to 25 V. Figure 2. 10 V and Chapter 2 Diode Applications 25 V vo 35 V vo 0 84 . The result is vo 5 V for this interval. 5. 3.24 Determine vo for the network of Fig.24. as stated in comment 2. 2. Solution Note that the frequency is 1000 Hz. The open-circuit equivalent for the diode will remove the 5-V battery from having any effect on vo. Throughout the analysis maintain a continual awareness of the location and reference polarity for vo to ensure that the proper levels for vo are obtained.The statement above may require skipping an interval of the input signal (as demonstrated in an example to follow). During the period that the diode is in the “on” state.98. and applying Kirchhoff’s voltage law around the outside loop of the network will result in Figure 2. assume that the capacitor will charge up instantaneously to a voltage level determined by the network. resulting in a period of 1 ms and an interval of 0. For this interval the network will appear as shown in Fig. EXAMPLE 2.97.

For the period t2 → t3 the network will now appear as in Fig.99 vi and vo for the clamper of Fig. 2.101.5 ms.7 V 0. 2. Note that the output swing of 30 V matches the input swing as noted in step 5.7 V. 2. 2.The time constant of the discharging network of Fig. Applying Kirchhoff’s voltage law yields 10 V and vo 24. 2. Repeat Example 2.98 is determined by the product RC and has the magnitude RC (100 k )(0.1 F) 0. EXAMPLE 2.7 V 5V 24.10 Clampers 85 .01 s 10 ms The total discharge time is therefore 5 5(10 ms) 50 ms.100 Determining vo and VC with the diode in the “on” state.7 V vo 0 4.25 Solution For the short-circuit state the network now takes on the appearance of Fig.3 V 34. The resulting output appears in Fig.3 V 0 Figure 2.3 V For the input section Kirchhoff’s voltage law will result in VC 25 V 0.99 with the input signal. 2. with the only change being the voltage across the capacitor. Figure 2.100 and vo can be determined by Kirchhoff’s voltage law in the output section.96. Since the interval t2 → t3 will only last for 0. 5V and vo 20 V and VC 5V 0.3 V vo 0 Figure 2.24 using a silicon diode with VT 0.7 V 0. it is certainly a good approximation that the capacitor will hold its voltage during the discharge period between pulses of the input signal.101 Determining vo with the diode in the open state.

2. 2. Figure 2. verifying the statement that the input and output swings are the same. The resulting output will then form an envelope for the sinusoidal response as shown in Fig. 86 Chapter 2 Diode Applications . In fact.102.102 Sketching vo for the clamper of Fig. 2.103 Clamping circuits with ideal diodes (5 5RC T/2).104 for a network appearing in the bottom right of Fig. 2. 2.96 with a silicon diode. A number of clamping circuits and their effect on the input signal are shown in Fig. one approach to the analysis of clamping networks with sinusoidal inputs is to replace the sinusoidal signal by a square wave of the same peak values.The resulting output appears in Fig. Figure 2.103.103.103 are square waves. Although all the waveforms appearing in Fig. clamping networks work equally well for sinusoidal signals. 2.

106.11 Zener Diodes Figure 2.105a can be substituted. the Zener diode is “on” and the equivalent model of Fig. Figure 2. 2.104 Clamping network with a sinusoidal input.11 ZENER DIODES The analysis of networks employing Zener diodes is quite similar to that applied to the analysis of semiconductor diodes in previous sections.106 will result in the network of Fig. V i and R Figure 2. 1. as is the load resistor.107 Determining the state of the Zener diode. The applied dc voltage is fixed. 2. The simplest of Zener diode networks appears in Fig.105b. 2.106 Basic Zener regulator.105 Zener diode equivalents for the (a) “on” and (b) “off” states. where an application of the voltage divider rule will result in V VL RLVi R RL (2. If V VZ. 87 .vo (V) vi 20 V +30 + t –20 V vi C + – 10 V R vo 0 –10 V t 0 – + – Figure 2. First the state of the diode must be determined followed by a substitution of the appropriate model and a determination of the other unknown quantities of the network. 2. the Zener equivalent is the open circuit that appears in the same figure. 2. The analysis can fundamentally be broken down into two steps. For the “off” state as defined by a voltage less than VZ but greater than 0 V with the polarity indicated in Fig. Unless otherwise specified. Applying step 1 to the network of Fig.105a. 2. Determine the state of the Zener diode by removing it from the network and calculating the voltage across the resulting open circuit.16) If V VZ. 2.107. the Zener model to be employed for the “on” state will be as shown in Fig. 2.105b is substituted. 2. the diode is “off” and the open-circuit equivalence of Fig.

17) The Zener diode current must be determined by an application of Kirchhoff’s current law.108 Substituting the Zener equivalent for the “on” situation.109 Zener diode regulator for Example 2. Figure 2. It will then “lock in” at this level and never reach the higher level of V volts. it will provide a level for comparison against other voltages.26. Figure 2. Before continuing. Since voltages across parallel elements must be the same. IZ.26 (a) For the Zener diode network of Fig. When the system is turned on. VR. we find that VL VZ (2.2 k 8.2. IR and where IL VL RL and IZ IZ IR IL IL (2. 2. Zener diodes are most frequently used in regulator networks or as a reference voltage.18) IR VR R Vi R VL The power dissipated by the Zener diode is determined by PZ VZ IZ (2. Figure 2. Solution (a) Following the suggested procedure the network is redrawn as shown in Fig. EXAMPLE 2. the Zener diode will turn “on” as soon as the voltage across the Zener diode is VZ volts. Substitute the appropriate equivalent circuit and solve for the desired unknowns.16) gives V 88 RLVi R RL 1.19) which must be less than the PZM specified for the device. For values of applied voltage greater than required to turn the Zener diode “on. 2. determine VL.73 V Chapter 2 Diode Applications . it is particularly important to realize that the first step was employed only to determine the state of the Zener diode. the voltage across the diode is not V volts.106. 2. That is. (b) Repeat part (a) with RL = 3 k .109.108.110. If the Zener diode is employed as a reference voltage. Applying Eq. For the network of Fig.106 is a simple regulator designed to maintain a fixed voltage across the load RL. If the Zener diode is in the “on” state.2 k (16 V) 1k 1.” the voltage across the load will be maintained at VZ volts. 2. and PZ. (2. the “on” state will result in the equivalent network of Fig.

Applying Eq. (2. Since V 8. Substituting the open-circuit equivalent will result in the same network as in Fig. 2.73 V 7.109.33 mA 6 mA IL [Eq.109 in the “on” state.73 V VL 16 V 8.16) will now result in V RLVi R RL 3 k (16 V) 1k 3k 12 V Since V 12 V is greater than VZ 10 V. 2. 26. the diode is in the “on” state and the network of Fig.33 mA which is less than the specified PZM Figure 2. the diode is in the “off” state as shown on the characteristics of Fig. 2. (2.112 will result. 2.18)] 3.67 mA) 30 mW. PZ VZIZ (10 V)(2. 2. (2.110 Determining V for the regulator of Fig. 2.67 mA The power dissipated.Figure 2.17) yields VL and with and so that VR IL IR IZ VZ Vi VL RL VR R IR 6 mA 2.11 Zener Diodes 89 .27 V (b) Applying Eq. 2. where we find that VL VR IZ and PZ V Vi 0A VZIZ VZ (0 A) 0W Figure 2.109. 8.112 Network of Fig.7 mW 10 V VL 16 V 10 V 6V 10 V 3k 6V 1k 3.110.111.73 V is less than VZ 10 V.111 Resulting operating point for the network of Fig.

22) The Zener current IZ IR IL (2.21) Once the diode is in the “on” state.23) Vi VZ (2.24) resulting in a minimum IZ when IL is a maximum and a maximum IZ when IL is a minimum value since IR is constant. the voltage across R remains fixed at VR and IR remains fixed at IR VR R (2. and the Zener device will be in the “off” state. 2. simply calculate the value of RL that will result in a load voltage VL VZ. there is a specific range of resistor values (and therefore load current) which will ensure that the Zener is in the “on” state. Since IZ is limited to IZM as provided on the data sheet. it does affect the range of RL and therefore IL. Variable RL Due to the offset voltage VZ.20) will ensure that the Zener diode is in the “on” state and the diode can be replaced by its VZ source equivalent.106 that will turn the Zener diode on. VL Solving for RL.20) establishes the minimum RL but in turn specifies the maximum IL as ILmax VL RL VZ RLmin (2. (2. (2. That is. To determine the minimum load resistance of Fig.Fixed Vi. Too small a load resistance RL will result in a voltage VL across the load resistor less than VZ .25) 90 Chapter 2 Diode Applications . Substituting IZM for IZ establishes the minimum IL as ILmin and the maximum load resistance as RLmax VZ ILmin (2. The condition defined by Eq. we have RLmin RVZ Vi VZ (2.26) IR IZM (2.20) VZ RLVi RL R Any load resistance value greater than the RL obtained from Eq.

25): ILmin IR 32 mA 8 mA with Eq. (b) Determine the maximum wattage rating of the diode.27. EXAMPLE 2. (2.20): RLmin RVZ Vi VZ VR Vi VZ VR R IZM VZ ILmin (1 k )(10 V) 50 V 10 V 50 V 10 V 10 k 40 40 V 250 The voltage across the resistor R is then determined by Eq.22): and Eq.23) provides the magnitude of IR: IR 40 V 1k 40 mA 40 mA The minimum level of IL is then determined by Eq. (2. apply Eq.113. (2.114 VL versus RL and IL for the regulator of Fig.11 Zener Diodes 91 .26) determining the maximum value of RL: RLmax 10 V 8 mA 1. 2.114a and for VL versus IL in Fig. 2.113 Voltage regulator for Example 2. 2.(a) For the network of Fig.27 Figure 2.114b. 2. 2. (b) Pmax VZ IZM (10 V)(32 mA) 320 mW Figure 2. determine the range of RL and IL that will result in VRL being maintained at 10 V. (2.113. (2.25 k A plot of VL versus RL appears in Fig. Solution (a) To determine the value of RL that will turn the Zener diode on.

(2. (2.Fixed RL.28) Since IL is fixed at VZ /RL and IZM is the maximum value of IZ. Solution Eq.115. IRmax IZM IL (2.106.27): Vimin IL Eq.87 V Figure 2. (2. R)VZ RL VZ RL IL VZ (1200 20 V 1.116.67 V 16.28 Determine the range of values of Vi that will maintain the Zener diode of Fig.67 mA 16.22 k ) 20 V 20 V A plot of VL versus Vi is provided in Fig. Since IR IL.28. the voltage Vi must be sufficiently large to turn the Zener diode on.2 k 60 mA 220 1200 )(20 V) 23.28): IRmax Eq. 2. Figure 2.115 Regulator for Example 2.29): Vimax (RL VL RL IZM IRmaxR 16.115 in the “on” state. 92 Chapter 2 Diode Applications . 2.29) EXAMPLE 2. the maximum Vi is defined by Vimax Vimax VRmax IRmaxR VZ VZ (2.67 mA 76. 2.27) IZM The maximum value of Vi is limited by the maximum Zener current IZM. The minimum turn-on voltage Vi Vimin is determined by VL and Vimin VZ (RL RLVi RL R R)VZ RL (2. Variable Vi For fixed values of RL in Fig.116 VL versus Vi for the regulator of Fig. 2.67 mA (76.87 V 36.67 mA)(0.

117 is obtained by filtering a half-wave. Z2 will then “turn on” (as a Zener diode). (b) circuit operation at vi 10 V. As long as Vi is greater than the sum of VZ1 and VZ2. the output voltage will remain fixed at 20 V for a range of input voltage that extends from 23.118 Establishing three reference voltage levels. the input could appear as shown in Fig. Note that Z1 is in a low-impedance region.118. + 5 kΩ Z1 + vo 0 vo 20 V 20 V 0 ωt – (a) – I 5 kΩ vi = 10 V + – + – (b) Z1 20 V 0 Z2 V Figure 2.116.119 Sinusoidal ac regulation: (a) 40-V peak-to-peak sinusoidal ac regulator. however. 2. The waveform appearing in Fig. 2. For the sinusoidal signal vi the circuit will appear as shown in Fig.115 with a fixed RL. is to establish a steady dc voltage (for a defined range of Vi) such as that shown in Fig. 2.87 V. as shown in Fig.119a. 2. The net effect. while the impedance of Z2 is quite large. Figure 2. Two or more reference levels can be established by placing Zener diodes in series as shown in Fig. corresponding with the open-circuit representation.119b at the instant vi 10 V. The result is that vo vi when vi 10 V. 2. 2. In fact. Two back-to-back Zeners can also be used as an ac regulator as shown in Fig.117 and the output would remain constant at 20 V.11 Zener Diodes 93 .The results of Example 2. The region of operation for each diode is indicated in the adjoining figure. 2.or full-wave-rectified output—a process described in detail in a later chapter.67 to 36. both diodes will be in the “on” state and the three reference voltages will be available. 2. 2.117 Waveform generated by a filtered rectified signal.28 reveal that for the network of Fig. The input and output will continue to duplicate each other until vi reaches 20 V.116 from a sinusoidal source with 0 average value. while Z1 will be in a vi 22 V ωt –22 V vi 20-V Zeners Z2 Figure 2.

2. 2. but its rms value is lower than that associated with a full 22-V peak signal. diode D1 is cut off and diode D2 conducts charging capacitor C2. and the input voltage charges capacitor C1 to Vm with the polarity shown in Fig. charging capacitor C1 up to the peak rectified voltage (Vm). 2. Since diode D2 acts as a short during the negative half-cycle (and diode D1 is open). secondary diode D1 conducts (and diode D2 is cut off).119a can be extended to that of a simple square-wave generator (due to the clipping action) if the signal vi is increased to perhaps a 50-V peak with 10-V Zeners as shown in Fig. The network of Fig. 2. Voltage Doubler The network of Figure 2. 94 Chapter 2 Diode Applications .120 with the resulting output waveform. The network is effectively limiting the rms value of the available voltage.122b): Vm Vm from which VC 2 2Vm V C1 Vm VC2 V C2 0 0 Figure 2. Diode D1 is ideally a short during this half-cycle.120 Simple square-wave generator. 2.122a. three. 2. we can sum the voltages around the outside loop (see Fig. vi 50 V + π 2π ω t vi 5 kΩ 10-V Zeners + Z1 + + Z2 vo 10 V –10 V vo – – 0 – – Figure 2. During the positive voltage half-cycle across the transformer. During the negative half-cycle of the secondary voltage.119(a). four.12 VOLTAGE-MULTIPLIER CIRCUITS Voltage-multiplier circuits are employed to maintain a relatively low transformer peak voltage while stepping up the peak output voltage to two.region of conduction with a resistance level sufficiently small compared to the series 5-k resistor to be considered a short circuit.121 is a half-wave voltage doubler. The resulting output for the full range of vi is provided in Fig. or more times the peak rectified voltage.121 Half-wave voltage doubler. Note that the waveform is not purely sinusoidal.

On the next positive half-cycle. both capacitors stay charged—C1 to Vm and C2 to 2Vm. D1 Conducting Nonconducting + C1 Vm – + – Vm Vm D1 C1 + – Vm – + C2 Vm + + C2 Vm – – D2 (a) Nonconducting (b) D2 Conducting Figure 2. If. The output waveform across capacitor C2 is that of a half-wave signal filtered by a capacitor filter.12 Voltage-Multiplier Circuits 95 . 2. Diode D2 is nonconducting at this time. (b) negative half cycle. the voltage across capacitor C2 drops during the positive half-cycle (at the input) and the capacitor is recharged up to 2Vm during the negative half-cycle. If no load is connected across capacitor C2. as would be expected. 2. Another doubler circuit is the full-wave doubler of Fig. During the positive half-cycle of transformer secondary voltage (see Fig.124 Alternate halfcycles of operation for full-wave voltage doubler.123 Full-wave voltage doubler.124a) diode D1 conducts charging capacitor C1 to a peak voltage Vm.122 Double operation. there is a load connected to the output of the voltage doubler. 2. diode D2 is nonconducting and capacitor C2 will discharge through the load. showing each half-cycle of operation: (a) positive half-cycle.Figure 2. The peak inverse voltage across each diode is 2Vm. Figure 2.123.

seven.125 shows an extension of the half-wave voltage doubler. 2. whereas measuring the output voltage from the bottom of the transformer will provide even multiples of the peak voltage. the voltage across capacitors C1 and C2 is the same as that across a capacitor fed by a full-wave rectifier circuit. the voltage across capacitors C1 and C2 is 2Vm. using many sections to step up the dc voltage. Vm. It should be obvious from the pattern of the circuit connection how additional diodes and capacitors may be connected so that the output voltage may also be five. diodes D2 and D4 conduct with capacitor C3. Voltage Tripler and Quadrupler Figure 2. and so on. which is less than the capacitance of either C1 or C2 alone. Measuring from the top of the transformer winding (Fig. during the negative half-cycle of the transformer secondary voltage. which develops three and four times the peak input voltage. Figure 2. During the positive half-cycle. If no load current is drawn from the circuit. 96 Chapter 2 Diode Applications . If the load is small and the capacitors have little leakage. and across C2 and C4 it is 4Vm. On the negative halfcycle. and each diode in the circuit must be rated at 2Vm PIV. times the basic peak voltage (Vm). In operation capacitor C1 charges through diode D1 to a peak voltage.124b) diode D2 conducts charging capacitor C2 while diode D1 is nonconducting. each capacitor will be charged to 2Vm. maximum. If additional sections of diode and capacitor are used. The transformer rating is only Vm. diode D3 conducts and the voltage across capacitor C2 charges capacitor C3 to the same 2Vm peak voltage. One difference is that the effective capacitance is that of C1 and C2 in series. If load current is drawn from the circuit. In summary. during the positive half-cycle of the transformer secondary voltage.During the negative half-cycle (see Fig. six. The peak inverse voltage across each diode is 2Vm .125 Voltage tripler and quadrupler. across C1 and C3 it is 3Vm. charging C4 to 2Vm. 2. The voltage across capacitor C2 is 2Vm. Vm. Capacitor C2 charges to twice the peak voltage 2Vm developed by the sum of the voltages across capacitor C1 and the transformer. The lower capacitor value will provide poorer filtering action than the singlecapacitor filter circuit.125) will provide odd multiples of Vm at the output. the half-wave or full-wave voltage-doubler circuits provide twice the peak voltage of the transformer secondary while requiring no center-tapped transformer and only 2Vm PIV rating for the diodes. extremely high dc voltages may be developed by this type of circuit. as it is for the filter capacitor circuit.

2. The 4.126 as we progress through the discussion. By clicking on the Get New Part icon (the icon in the top right area with the binoculars) followed by Libraries. we will choose Grid On.27 to permit a comparison with the hand-calculated solution.126). the application of PSpice Windows requires that the network first be constructed on the schematics screen. Once located. we can choose the Analog. Move the resistor to a logical location. It might be helpful to reference the completed network of Fig. The next few paragraphs will examine the basics of setting up the network on the screen. If you want to move the 4. Repeat the above for the value of the resistor R2. 2. 2. moving the 4. and click the left button of the mouse— the resistor R1 is in place. The Display Options dialog box will permit you to make all the choices necessary regarding the type of display desired. The resistor R2 can be rotated by pressing the keys Ctrl and R simultaneously or by choosing Edit on the menu bar. assuming no prior experience with the process. By simply moving the mouse to the right. As briefly described in Chapter 1. followed by Display Options. the second resistor will appear. and R2 can be placed in the proper location with a subsequent click of the mouse. This will ensure that all the connections are made between the elements. 2. The result of the above is two resistors with the right labels but the wrong values.slb library of basic elements. Stay on Grid.13 PSPICE WINDOWS Series Diode Configuration PSpice Windows will now be applied to the network of Fig. A Set Attribute Value dialog box will appear. and send the value to the screen with OK. and Grid Spacing of 0. an additional click anywhere on the screen will remove the boxes and end the process. simply click once on the value and the boxes will reappear. Clicking on R followed by OK will result in the Part Browser Basic dialog box reflecting our choice of a resistive element. Release the clicker.126 PSpice Windows analysis of a series diode configuration.2.1 in.7k will appear within a box that can be moved by simply clicking on the small box and. The resistor R2 must now be placed to the right of R1. The screen can be set up by first choosing Options at the heading of the schematics screen. The resistor will appear horizontal. which is perfect for the R1 of Fig. In general. Figure 2. Since the network only has two resistors.7k to the desired location.7k label will remain where placed. Note that it snaps to the grid structure. followed by Rotate.27 (note Fig. the depositing of resistors can be ended by a right click of the mouse. and the 4. while holding the clicker down. it is easier to draw the network if the grid is on the screen and the stipulation is made that all elements be on the grid. 2. R The resistor R will be the first to be positioned. For our purposes. To change a value. Choosing the Place & Close option will place the resistive element on the screen and close the dialog box.7k in the future. Type in the correct value.13 PSpice Windows 97 . We can then scroll the Part list until we find R. double click on the value of the screen (first R1).

When you have the correct position. Let us now take a look at the diode specs by clicking the diode symbol once. Clicking on either label will provide the boxes that permit movement of the labels. The pencil is now ready to draw. click it in place with a left click. To change the label to E1 simply click the V1 twice and an Edit Reference Designator dialog box will appear. a V1 label will appear. bring the marker to the Value box and change it to 10V. Then click Save Attr. and click the left side of the mouse. to be sure and save the new value. it is necessary to use the Ctrl-R sequence twice to rotate the symbol before finalizing its position. IPROBE is found in the SPECIAL. Clicking OK results in the source symbol appearing on the schematic. and an OK will result in E1 being changed to 10V. Set the value to 10V and click OK. note that Is 2.slb library of the Library Browser dialog box. For the moment.slb library of Library Browser and choosing VDC. When the symbol first appears. This symbol can be placed as required. we will leave the parameters as listed. By choosing DC 0V. it is 180° out of phase with the desired current. and end the operation with a right click of the mouse. As with the elements described above. E1 can now be set. after which a dialog box will appear labeled E1 PartName:VDC. Move the diode to the correct position. Choosing the D1N4148 diode followed by an OK and Close & Place will place the diode symbol on the screen. simply click the mouse once more and place E1 as desired. LINE The elements now need to be connected by choosing the icon with the thin line and pencil or by the sequence Draw-Wire. After clicking it in the appropriate place. simply click on it (to establish the red or active color). Since we are looking for a positive answer in this investigation. The line will appear in red.slb library and appears as a meter face on the screen. To set the value of E1. once it is in place a single click will place the meter and a right click will complete the insertion process. In particular. A pencil will appear that can draw the desired connections in the following manner: Move the pencil to the beginning of the line. IPROBE One or more currents of a network can be displayed by inserting an IPROBE in the desired path. Draw the desired line (connection). but be sure to turn it 180° with the appropriate operations. click the value twice and the Set Attribute Value will appear. IPROBE will respond with a positive answer if the current (conventional) enters the symbol at the end with the arc representing the scale. IPROBE should be installed as shown in Fig. The new value will appear on the schematic. 2. and click the left side again when the connection is complete. and then click the scissors icon or use the sequence Edit-Delete. Therefore. waiting for another random click of the mouse or 98 Chapter 2 Diode Applications .126. The labels D1 and D1N4148 will appear near the diode. and then E1 will appear on the screen within a box. DC and Value will appear in the designated areas at the top of the dialog box. E The voltage sources are set by going to the source.To remove (clip) an element. Using the mouse.682nA and the terminal capacitance (important when the applied frequency becomes a factor) is 4pF. Change the label to E1 and click OK. followed by the Edit-Model-Edit Instance Model sequence. The box can be moved in the same manner as the labels for resistors. The value can also be set by clicking the battery symbol itself twice. DIODE The diode is found in the EVAL.

For additional lines. the currents (2. Note also that the results are not an exact match with those obtained in Example 2.slb library.56 rather than the 454. By clicking it on and off. therefore.the insertion of another line. although only three are placed in Fig. Simply place the arrow of the VIEWPOINT symbol where you desire the voltage with respect to ground. 2. If taken to the tenths place.081 rather than the 2. 2. They will only appear where VIEWPOINTS have been inserted. as shown in Fig 2.126. In addition. For practice. VIEWPOINT Nodal voltages can be displayed on the diagram after the simulation using VIEWPOINTS.13 PSpice Windows 99 .2 mV obtained in Example 2.126 can be improved (in the sense that they will be a closer match to the hand-written solution) by clicking on the diode (to make it red) 2.slb library and can be placed in the same manner as the elements described above. click it on and off and note the effect on the schematic. By selecting Do not auto-run Probe you save intermediary steps that are inappropriate for this analysis. and the dc voltages will not automatically appear.64 V rather than the 0. The results obtained in Fig. If we now exit the box by clicking on the small x in the top right corner.7 V assumed for all silicon diodes. the voltage across the diode is 281. it should be noted that an analysis can also be initiated by simply clicking the Simulation icon having the yellow background and the two waveforms (square wave and sinusoidal). go to Analysis and choose Simulation. EGND The system must have a ground to serve as a reference point for the nodal voltages. For the future. it is expected that the results are only close to the actual response. ANALYSIS The network is now ready to be analyzed. Note that the program has automatically provided four dc voltages of the network (in addition to the VIEWPOINT voltages). The icon with the large capital I will permit all the dc currents of the network to be shown if desired. To expedite the process. simply click the right side of the mouse. you can control whether the dc levels of the network will appear.56 mV 0. Clicking it once will remove the selected dc voltage. Further. For future analysis we will want control over what is displayed so follow the path through Analysis-Display Results on Schematic and slide over to the adjoining Enable box. Clicking the Enable box will remove the check. It will then turn geen to indicate it is in memory. you will obtain the results appearing in Fig. then click the icon with the smaller capital V in the same grouping. Earth ground (EGND) is part of the PORT.1 mA) are an exact match. A more direct path toward controlling the appearance of the dc voltages is to use the icon on the menu bar with the large capital V. a PSpiceAD dialog box will appear and reveal that the bias (dc) points have been calculated.79 mV 421. If the network was installed properly. The VIEWPOINT voltage at the far right is 421. it is an option that will be discussed later in this chapter. click on Analysis and choose Probe Setup. The same can be done for selected currents with the remaining icon of the group. On the other hand. The network is now complete. which is found in the SPECIAL. After OK.11. This occurred because an option under analysis was enabled.126. This all results from our using a real diode with a long list of variables defining its operation.11 was an approximate one and. simply repeat the procedure. A VIEWPOINT can be placed at every node of the network if necessary. However. simply click the nodal voltage of interest. the current is 2.126. When done. the results obtained for the nodal voltage and current are quite close.11.066 mA obtained in the same example. 2. it is important to remember that the analysis of Example 2. If you want to remove selected dc voltages on the schematic.

Note that the voltage across the diode now is 260. The results will not always be perfect. while the other provides an almost exact match with the hand-written solution.5E-15A (a value determined by trial and error). The result is the long listing of Fig.701 V. In addition. Diode Characteristics The characteristics of the D1N4148 diode used in the above analysis will now be obtained using a few maneuvers somewhat more sophisticated than those employed previously. the network in Fig.Figure 2.1 mW. As the current through the diode changes. Finally. The same can be said for the odd-numbered exercises at the end of this chapter. 2.7 V. Scrolling down the output file. Next is the SMALL SIGNAL BIAS SOLUTION or dc solution with the voltages at the various nodes. The resistor R2 is connected from node 3 to 4. The results can also be viewed in tabulated form by returning to Analysis and choosing Examine Output. In either case.127. again. the other examples should be examined using the Windows approach since the results are provided for comparison. the current through the sources of the network is shown.17 mV 440.93 mV 0.701 V. but sufficient coverage has been provided to examine any of the networks covered in this chapter with a dc source. The analysis is now complete for the diode circuit of interest. The total power dissipation of the elements is 31.5E-15A. Then.128. Note also that the Bias Current Display was enabled to show that the current is indeed the same everywhere in the circuit. an almost perfect match with the hand-written solution of 0. The source E2 is from 0 to node 3. One cannot expect a perfect match for every diode network by simply setting Is to 3. First. However. we find the Diode MODEL PARAMETERS clearly showing that Is is set at 3. the OPERATING POINT INFORMATION reveals that the current through the diode is 2. the level of Is must also change if an exact match with the handwritten solution is to be obtained.93 V or. Choose Is 3. it is suggested that Is 3.129 is constructed using the procedures described 100 Chapter 2 Diode Applications . with the 10V source from node 0 to 5. and using the sequence Edit-Model-Edit Instance Model (Text) to obtain the Model Editor dialog box.44 V. For transistors in the chapters to follow. or almost exactly 0.5E-15A. but in most cases they will be closer than if the parameters of the diode are left at their default values. and delete all the other parameters for the device.5E15A and is the only parameter listed. For practice. The negative sign reveals that it is reflecting the direction of electron flow (into the positive terminal). The Schematics Netlist describes the network in terms of numbered nodes.07 mA and the voltage across the diode 0. follow with OK-Simulate icon to obtain the results of Fig. 2. and so on.127 The circuit of Figure 2.126 reexamined with Is set to 3. the results obtained are very close to the expected values. rather than worry about the current in each system. The 0 refers to ground level. One is more accurate as far as the actual device is concerned. The VIEWPOINT voltage is 440. it will be set to 2E-15A to obtain a suitable match with the hand-written solution.5E-15A be used as the standard value if the PSpice solution is desired to be a close match with the hand-written solution. 2. We have not touched on all the alternative paths available through PSpice Windows.

the End Value 10V.01V. we plan to sweep the source voltage from 0 to 10 V in 0. Within the Analysis-Setup dialog box the DC Sweep is enabled (the only one necessary for this exercise). 101 . the Sweep Type will be linear. and the Start Value 0V. so the Swept Var. however.13 PSpice Windows Figure 2. the Vd appearing above the diode D1. Next. The resulting voltage Vd is. Note.128 Output file for PSpice Windows analysis of the circuit of Figure 2.01-V increments. followed by a single click of the DC Sweep rectangle. Analysis Setup is chosen by either clicking on the Analysis Setup icon (at the top left edge of the schematic with the horizontal blue bar and the two small squares and rectangles) or by using the sequence Analysis-Setup. In this case.Figure 2. the Name E. in this case. with an OK followed by a Close of the 2. Type is Voltage Source.129 Network to obtain the characteristics of the D1N4148 diode. The DC Sweep dialog box will appear with various inquiries.127. Then. above. A point in the network (representing the voltage from anode to ground for the diode) has been identified as a particular voltage by double-clicking on the wire above the device and typing Vd in the Set Attribute Value as the LABEL. the voltage across the diode. and the Increment 0.

130 Characteristics of the D1N4148 diode. The vertical axis must now be set to ID by first choosing Trace (or the Trace icon. In other words. which is the red waveform with two sharp peaks and a set of axis) and then Add to obtain Add Traces. Choose User Defined.7 V and the PSpice solution closer to the hand-written approach.07 mA would have obtained.130.07 mA for the current). Choosing I(D1) and clicking OK will result in the plot of Fig. followed by an immediate appearance of the MicroSim Probe graph showing only a horizontal axis of the source voltage E running from 0 to 10 V. Since the plot we want is of ID versus VD. In the previous analysis. Figure 2. After OK. The range can be reduced or expanded by simply going to Plot-Y-Axis Setting and defining the range of interest.5E-15A and all other parameters removed from the diode listing. we return to the dialog box to set the horizontal scale.0 V. 2. then enter 0V to 1V since this is the range of interest for Vd with a Linear scale.64 V. the curve would have shifted to the right and an intersection of 0.01-V increments. The analysis to be performed will obtain a complete solution for the network for each value of E from 0 to 10 V in 0. Click OK and you will find that the horizontal axis is now V(Vd) with a range of 0 to 1. This is accomplished by selecting Plot and then X-Axis Settings to obtain the X Axis Settings dialog box. 102 Chapter 2 Diode Applications . Next. The analysis is performed by the sequence Analysis-Run Probe. corresponding to a current of about 2 mA on the graph (recall the solution of 2. In this case. If Is had been set to 3. we click Axis Variable and select V(Vd) from the listing.Analysis Setup box. the voltage across the diode would have been about 0. the resulting plot extended from 0 to 10 mA. the network will be analyzed 1000 times and the resulting data stored for the plot to be obtained. the voltage across the diode was 0.7 V and 2. If the resulting current had been closer to 6.5 mA. we have to change the horizontal (x-axis) to VD. we are set to obtain the solution.

determine ID. determine the level of VD. (a) Using the approximate characteristics for the Si diode.132 that will result in a diode current of 10 mA if E 7 V. 2. 2. (b) Perform the same analysis as part (a) using the ideal model for the diode. (b) Repeat part (a) using the approximate model for the diode and compare results. 3.132.131b. and VR for the circuit of Fig.§ 2.131a.132 Problems 2. (c) Do the results obtained in parts (a) and (b) suggest that the ideal model can provide a good approximation for the actual response under some conditions? Problems Figure 2. (a) Using the characteristics of Fig. 4.133 Problem 4 103 .18 k . 2. Repeat part (a) with R 0.131 Problems 1.7 V in each case? Figure 2.131b. 2 2. 2.133. 2. (a) (b) (c) (d) Using the characteristics of Fig. 2. VD. ID.2 Load-Line Analysis 1. Use the characteristics of Fig. 3 How do the resulting levels of ID compare? Comment accordingly.47 k . Determine the value of R for the circuit of Fig. Repeat part (a) with R 0. and VR for the circuit of Fig. Is the level of VD relatively close to 0. PROBLEMS Figure 2. (c) Repeat part (a) using the ideal model for the diode and compare results. 2. determine ID and VD for the circuit of Fig.131b for the diode.

49 * 7.4 Series Diode Configurations with DC Inputs 5. 2.136 Problem 7 * 8.134 using the approximate equivalent model for the diode. Figure 2. Figure 2. Figure 2. Determine Vo and ID for the networks of Fig.135 Problems 6. Determine Vo and ID for the networks of Fig.134 Problem 5 6. 2.137 Problem 8 104 Chapter 2 Diode Applications .135. 2.§ 2. Determine the level of Vo for each network of Fig.136.137. Determine the current I for each of the configurations of Fig. Figure 2. 2.

140 Problem 11 Problems 105 .* 9. Determine Vo and ID for the networks of Fig. 2.138 Problem 9 § 2. 2.139.138.140. Determine Vo and I for the networks of Fig. 2.139 Problems 10. Figure 2.5 Parallel and Series–Parallel Configurations 10. Determine Vo1 and Vo2 for the networks of Fig. Figure 2. Figure 2. 50 * 11.

Figure 2. 2.7 V). Vo2. load applied as shown in Fig. Determine Vo for the negative logic OR gate of Fig.143.143 Problem 18 21. 17. 25.141 Problem 12 Figure 2.6 AND/OR Gates 14. Determine Vo for the configuration of Fig. 2. 18. Repeat Problem 22 with a silicon diode (VT * 24.12. 16.144 Problem 19 Figure 2. 19.8-k 0. Determine Vo for the network of Fig.145 Problem 20 Figure 2. Repeat Problem 22 with a 6.146 Problem 21 § 2. and I for the network of Fig.144. Determine Vo for the network of Fig. 23. 2.41 with 0 V on both inputs. Determine Vo and ID for the network of Fig. Half-Wave Rectification 22. 2. Figure 2. * 13. 2. 2. Determine Vo for the network of Fig. vd.142 Problems 13.147 Problems 22. Determine Vo for the network of Fig. 51 § 2.38 with 0 V on both inputs.147.148. 20. Figure 2. sketch vo and determine Vdc.148 Problem 24 Figure 2. 2.7 Sinusoidal Inputs.142. 2. For the network of Fig.41 with 10 V on both inputs. 15. Determine the level of Vo for the gate of Fig.149 Problem 25 106 Chapter 2 Diode Applications . 24 Figure 2.145.141.146. Figure 2. Sketch vL and iL. 2. 2. Determine Vo1. 2. Determine Vo for the negative logic AND gate of Fig. Assuming an ideal diode.149. sketch vi. The input is a sinusoidal waveform with a frequency of 60 Hz * 23. 2. 2.38 with 10 V on both inputs. and id for the half-wave rectifier of Fig.

(a) If silicon diodes are employed.151.152 Problem 29 Problems 107 . 2. (c) Find the maximum current through each diode during conduction. (c) Determine the current through each diode at Vimax using the results of part (b). determine the diode current and compare it to the maximum rating. Figure 2.151 Problem 27 § 2. 2.152. (e) If only one diode were present. Determine vo and the required PIV rating of each diode for the configuration of Fig.* 26.8 Full-Wave Rectification 28. (a) Given Pmax 14 mW for each diode of Fig. Figure 2. (b) Determine Imax for Vimax 160 V. Figure 2.150. sketch vo and iR. what is the dc voltage available at the load? (b) Determine the required PIV rating of each diode.150 Problem 26 * 27. A full-wave bridge rectifier with a 120-V rms sinusoidal input has a load resistor of 1 k . For the network of Fig. (d) What is the required power rating of each diode? 29. determine the maximum current rating of each diode (using the approximate equivalent model). 2.

2. 2. 2.155 Problem 32 33.153 and determine the dc voltage available.154 Problem 31 § 2.154 and determine the dc voltage available. Figure 2.9 Clippers 32.155 for the input shown.156 Problem 33 108 Chapter 2 Diode Applications . Sketch vo for the network of Fig. Sketch vo for the network of Fig. Figure 2. Figure 2.156 for the input shown. Determine vo for each network of Fig. Determine vo for each network of Fig.153 Problem 30 * 31. Figure 2.* 30. 2.

Figure 2.* 34. 2. 2. Determine vo for each network of Fig. 2.160 Problem 37 Problems 109 . Figure 2.158 for the input shown.159 Problem 36 § 2. Sketch vo for each network of Fig.159 for the input shown. Sketch iR and vo for the network of Fig.157 for the input shown.157 Problem 34 * 35. 2. Figure 2. Determine vo for each network of Fig.10 Clampers 37.158 Problem 35 36.160 for the input shown. Figure 2.

Figure 2. Sketch vo.162 Problem 39 * 40. 2. Figure 2. 2.161 Problem 38 * 39. Sketch vo for each network of Fig. For the network of Fig. (b) Compare 5 to half the period of the applied signal. Figure 2. Design a clamper to perform the function indicated in Fig.164.38. Design a clamper to perform the function indicated in Fig. 2.163 Problem 40 * 41. 2.162: (a) (c) Calculate 5 .164 Problem 41 110 Chapter 2 Diode Applications .163. Would it be a good approximation to consider the diode to be ideal for both configurations? Why? Figure 2.161 for the input shown.

11 Zener Diodes * 42.13 PSpice Windows 49. determine the range of Vi that will maintain VL at 8 V and not exceed the maximum power rating of the Zener diode. Design a voltage regulator that will maintain an output voltage of 20 V across a 1-k load with an input that will vary between 30 and 50 V. * 44. 2. IZ.142 using PSpice Windows. 2.§ 2. (a) Determine VL. Perform a general analysis of the Zener network of Fig. 2. 48. determine Rs and VZ. For the network of Fig. 52. determine the proper value of Rs and the maximum current IZM.121 if the secondary voltage of the transformer is 120 V (rms). 2. IL. Perform an analysis of the network of Fig. (b) Determine PZmax for the Zener diode of part (a). 2. That is. Repeat for a 5-V square wave.167 Problems 44.166 to maintain VL at 12 V for a load variation (IL) from 0 to 200 mA. § 2.166 Problem 43 § 2. 2. Problems 111 . Perform an analysis of the network of Fig.120 if the input is a 50-V square wave. 2. Figure 2.12 Voltage-Multiplier Circuits 47. Figure 2. Determine the voltage available from the voltage doubler of Fig.167 using PSpice Windows. 52 * Please Note: Asterisks indicate more difficult problems. 2. 46. (c) Determine the value of RL that will establish maximum power conditions for the Zener diode. Determine the required PIV ratings of the diodes of Fig. (a) Design the network of Fig.165 Problem 42 * 43. 51. That is. (d) Determine the minimum value of RL to ensure that the Zener diode is in the “on” state.165 if RL 180 (b) Repeat part (a) if RL 470 .121 in terms of the peak secondary voltage Vm. Perform an analysis of the network of Fig. Figure 2.167. 50. 2. and IR for the network Fig. 45. 2.135 using PSpice Windows. Sketch the output of the network of Fig.139 using PSpice Windows.

Production rose from about 1 million tubes in 1922 to about 100 million in 1937. radio and television provided great stimulation to the tube industry. Dr. 1928 All shared the Nobel Prize in 1956 for this contribution. the industry became one of primary importance and rapid advances were made in design. In the early 1930s the four-element tetrode and five-element pentode gained prominence in the electron-tube industry. (Courtesy of AT&T Archives. On December 23. Walter H. William Shockley (seated). the electronics industry was to experience the advent of a completely new direction of interest and development. China. Figure 3. Lee De Forest added a third element. Brattain. Bardeen Born: Madison. the vacuum-tube diode was introduced by J. called the control grid.1 INTRODUCTION During the period 1904–1947. John Bardeen (left). In the following years. In the years to follow. manufacturing techniques. 1936 Dr. It was on the afternoon of this day that Walter H. in 1906. and miniaturization.CHAPTER 3 Bipolar Junction Transistors 3. the vacuum tube was undoubtedly the electronic device of interest and development. 1902 PhD University of Minnesota. 1910 PhD Harvard.) Dr. Brattain Born: Amoy. the triode. The advantages of this threeterminal solid-state device over the tube were immediately obvious: It was smaller Co-inventors of the first transistor at Bell Laboratories: Dr.) 112 . The original transistor (a point-contact transistor) is shown in Fig. 1936 Dr. A. Brattain and John Bardeen demonstrated the amplifying action of the first transistor at the Bell Telephone Laboratories. In 1904. 1908 PhD Princeton. resulting in the first amplifier.1. to the vacuum diode. England. 3.1 The first transistor. 1947. (Courtesy Bell Telephone Laboratories. however. high-power and high-frequency applications. Fleming. Shortly thereafter. Dr. Shockley Born: London. Wisconsin.

(b) npn. or power level) will have at least three terminals with one controlling the flow between two other terminals. 3. You will find that all amplifiers (devices that increase the voltage. 3. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically. Both are shown in Fig. The term bipolar reflects the fact that holes and electrons participate in the injection process into the oppositely polarized material. This lower doping level decreases the conductivity (increases the resistance) of this material by limiting the number of “free” carriers. and was more efficient since less power was absorbed by the device itself.or n-type material.001 150 1.3 TRANSISTOR OPERATION The basic operation of the transistor will now be described using the pnp transistor of Fig.and one n-type layers of material. C for collector.3 Transistor Operation 113 . 3. The outer layers have widths much greater than the sandwiched p. If only one carrier is employed (electron or hole). requiring no warm-up period. The operation of the npn transistor is exactly the same if the roles played by the electron and hole are interchanged.2 the terminals have been indicated by the capital letters E for emitter. An appreciation for this choice of notation will develop when we discuss the basic operation of the transistor. it was instantly available for use.150/0. 3. Figure 3. resulting in a heavy flow of majority carriers from the p. had rugged construction. We will find in Chapter 4 that the dc biasing is necessary to establish the proper region of operation for ac amplification. 3. is often applied to this threeterminal device. For the biasing shown in Fig.3 the pnp transistor has been redrawn without the base-to-collector bias.and lightweight. Note the similarities between this situation and that of the forward-biased diode in Chapter 1.to the n-type material. Figure 3.2a. it is considered a unipolar device. 3. Note in the discussion above that this chapter is our first discussion of devices with three or more terminals.2 TRANSISTOR CONSTRUCTION The transistor is a three-layer semiconductor device consisting of either two n.and one p-type layers of material or two p. and B for base. The emitter layer is heavily doped. the base lightly doped. The Schottky diode of Chapter 20 is such a device.2 the ratio of the total width to that of the center layer is 0. and lower operating voltages were possible.2 Types of transistors: (a) pnp. and the collector only lightly doped. current. 10 1 or less).2 with the proper dc biasing. In Fig. 3. while the latter is called a pnp transistor. The former is called an npn transistor. For the transistors shown in Fig. from bipolar junction transistor. The abbreviation BJT. had no heater requirement or heater loss.3 Forward-biased junction of a pnp transistor. The depletion region has been reduced in width due to the applied bias. 3.

3. Note in Fig.5.4. Since the sandwiched n-type material is very thin and has a low conductivity. Consider the similarities between this situation and that of the reverse-biased diode of Section 1.4. As indicated in Fig. indicating clearly which junction is forward-biased and which is reverse-biased. we obtain IE IC IB (3. In summary. 3. Combining this with the fact that all the minority carriers in the depletion region will cross the reverse-biased junction of a diode accounts for the flow indicated in Fig.and minority-carrier flow indicated. however. as indicated in Fig.5. therefore.5 the widths of the depletion regions.2) Bipolar Junction Transistors . a large number of majority carriers will diffuse across the forward-biased p-n junction into the n-type material. The magnitude of the base current is typically on the order of microamperes as compared to milliamperes for the emitter and collector currents. is comprised of two components—the majority and minority carriers as indicated in Fig. The reason for the relative ease with which the majority carriers can cross the reverse-biased junction is easily understood if we consider that for the reverse-biased diode the injected majority carriers will appear as minority carriers in the n-type material.5 Majority and minority carrier flow of a pnp transistor. there has been an injection of minority carriers into the n-type base region material. 3. Figure 3. The larger number of these majority carriers will diffuse across the reverse-biased junction into the p-type material connected to the collector terminal as indicated in Fig. 3. while the other is forward biased. Figure 3.5 both biasing potentials have been applied to a pnp transistor. therefore: One p-n junction of a transistor is reverse biased.5 as if it were a single node. The minority-current component is called the leakage current and is given the symbol ICO (IC current with emitter terminal Open). 3.2). 3.2a as shown in Fig.5. In Fig. The collector current. (3.4 Reverse-biased junction of a pnp transistor. The collector current. Applying Kirchhoff’s current law to the transistor of Fig. 3. Recall that the flow of majority carriers is zero.Let us now remove the base-to-emitter bias of the pnp transistor of Fig. a very small number of these carriers will take this path of high resistance to the base terminal. In other words. 3. resulting in only a minority-carrier flow. The question then is whether these carriers will contribute directly to the base current IB or pass directly into the p-type material.5. IC 114 Chapter 3 ICmajority ICOminority (3.1) and find that the emitter current is the sum of the collector and base currents.6. 3. is determined in total by Eq. with the resulting majority. 3.

3. or at.7 Input or driving point characteristics for a common-base silicon transistor amplifier. while ICO is measured in microamperes or nanoamperes. It can severely affect the stability of a system at high temperature if not considered properly. IC is measured in milliamperes. The output or collector set of characteristics has three basic regions of interest. Improvements in construction techniques have resulted in significantly lower levels of ICO. the base is usually the terminal closest to. 3.6 requires two sets of characteristics—one for the driving point or input parameters and the other for the output side. This choice was based primarily on the fact that the vast amount of literature available at educational and industrial institutions employs conventional flow and the arrows in all electronic symbols have a direction defined by this convention. like Is for a reverse-biased diode. Throughout this book all current directions will refer to conventional (hole) flow rather than electron flow. Recall that the arrow in the diode symbol defined the direction of conduction for conventional current. The output set will relate an output current (IC) to an output voltage (VCB) for various levels of input current (IE) as shown in Fig. Figure 3. For the transistor: The arrow in the graphic symbol defines the direction of emitter current (conventional flow) through the device.6 are the actual directions as defined by the choice of conventional flow. 3. as indicated in Fig. 3.8: the active. Figure 3.6 Notation and symbols used with the common-base configuration: (a) pnp transistor. That is. to the point where its effect can often be ignored. compare the direction of IE to the polarity or VEE for each configuration and the direction of IC to the polarity of VCC. (b) npn transistor. ground potential. ICO.For general-purpose transistors. is temperature sensitive and must be examined carefully when applications of wide temperature ranges are considered. The input set for the common-base amplifier as shown in Fig.8. Note also that the applied biasing (voltage sources) are such as to establish current in the direction indicated for each branch. In addition.6 for the common-base configuration with pnp and npn transistors.4 Common-Base Configuration 115 .4 COMMON-BASE CONFIGURATION The notation and symbols used in conjunction with the transistor in the majority of texts and manuals published today are indicated in Fig. 3. All the current directions appearing in Fig. 3. Note in each case that IE IC IB. To fully describe the behavior of a three-terminal device such as the commonbase amplifiers of Fig. 3.7 will relate an input current (IE) to an input voltage (VBE) for various levels of output voltage (VCB). 3. The common-base terminology is derived from the fact that the base is common to both the input and output sides of the configuration.

However. 3. as indicated in Fig. 3. As inferred by its name. as indicated in Fig. The circuit conditions that exist when IE 0 for the common-base configuration are shown in Fig. ICBO. the collector current increases to a magnitude essentially equal to that of the emitter current as determined by the basic transistor-current relations.8 Output or collector characteristics for a common-base transistor amplifier. the cutoff region is defined as that region where the collector current is 0 A. 116 Chapter 3 Bipolar Junction Transistors .9. At higher temperatures the effect of ICBO may become an important factor since it increases so rapidly with temperature.8.3) Figure 3.8.IC (mA) Active region (unshaded area) 7 6 5 4 3 2 1 0 −1 0 5 10 15 7 mA 6 mA 5 mA Saturation region 4 mA 3 mA 2 mA I E = 1 mA I E = 0 mA 20 V CB (V) Figure 3. The curves clearly indicate that a first approximation to the relationship between IE and IC in the active region is given by IC IE (3. keep in mind that ICBO. The active region is defined by the biasing arrangements of Fig. Cutoff region cutoff. for higher power units ICBO will still appear in the microampere range. Note also the almost negligible effect of VCB on the collector current for the active region. the collector current is simply that due to the reverse saturation current ICO. the level of ICBO for general-purpose transistors (especially silicon) in the low.9. and saturation regions. The current ICO is so small (microamperes) in magnitude compared to the vertical scale of IC (milliamperes) that it appears on virtually the same horizontal line as IC 0. 3. 3. In addition.9 Reverse saturation current. In particular: In the active region the collector-base junction is reverse-biased.6. 3. as revealed on Fig. for the diode (both reverse leakage currents) is temperature sensitive. 3.and midpower ranges is usually so low that its effect can be ignored. Note in Fig.8 that as the emitter current increases above zero. like Is. Because of improved construction techniques. In addition: In the cutoff region the collector-base and base-emitter junctions of a transistor are both reverse-biased. while the base-emitter junction is forward-biased. At the lower end of the active region the emitter current (IE) is zero. The active region is the region normally employed for linear (undistorted) amplifiers. The notation most frequently used for ICO on data and specification sheets is.

The input characteristics of Fig. 3.7 V 0. increasing levels of VCB have such a small effect on the characteristics that as a first approximation the change due to changes in VCB can be ignored and the characteristics drawn as shown in Fig. It is important to fully appreciate the statement made by the characteristics of Fig.7 V at any level of emitter current as controlled by the external network. the base-to-emitter voltage will be assumed to be the following: VBE 0.6 0. 3. In the saturation region the collector-base and base-emitter junctions are forward-biased.10c.8 (a) 1 VBE (V) 6 5 4 3 2 1 0 0. as the base-to-emitter voltage increases. For the analysis to follow in this book the equivalent model of Fig. the effect of variations due to VCB and the slope of the input characteristics will be ignored as we strive to analyze transistor networks in a manner that will provide a good approximation to the actual response without getting too involved with parameter variations of less importance.2 0.The saturation region is defined as that region of the characteristics to the left of VCB 0 V. In fact.6 0.7 reveal that for fixed values of collector voltage (VCB). the emitter current increases in a manner that closely resembles the diode characteristics. I E (mA) 8 7 Any V CB 6 5 4 3 2 1 0 0. 3.10c will be employed for all dc analysis of transistor networks. They specify that with the transistor in the “on” or active state the voltage from base to emitter will be 0. 3.4 0.8 (b) 0.10b will result.10c.7 V (3. That is. Taking it a step further and ignoring the slope of the curve and therefore the resistance associated with the forward-biased junction will result in the characteristics of Fig.10 Developing the equivalent model to be employed for the base-toemitter region of an amplifier in the dc mode.7 V 1 VBE (V) 6 5 4 3 2 1 0 0. 3.4 0. The horizontal scale in this region was expanded to clearly show the dramatic change in characteristics in this region.4 Common-Base Configuration 117 . at the first encounter of any transistor configuration in the dc mode. Note the exponential increase in collector current as the voltage VCB increases toward 0 V.4) In other words.6 0. In fact. 3. If we then apply the piecewise-linear approach.2 0. once a transistor is in the “on” state.4 0.8 (c) 1 VBE (V) 8 7 I E (mA) 8 7 I E (mA) Figure 3. the characteristics of Fig. 3. one can now immediately specify that the voltage from base to emitter is 0.10a.7 V if the device is in the active region—a very important conclusion for the dc analysis to follow.2 0.

recognize that Eq. determine VBE if IC 4 mA and VCB 20 V.8. Even though the 1. (b) Using the characteristics of Fig.1 (a) Using the characteristics of Fig. but as mentioned earlier. IE IC 4 mA. 3.10c. Since alpha is defined solely for the majority carriers.998. IC also appears to be 0 mA for the range of VCB values. 3.5) where IC and IE are the levels of current at the point of operation. 3.8. (b) The effect of changing VCB is negligible and IC continues to be 3 mA.7) will be demonstrated in Section 3.6) For the characteristics of Fig. an ac alpha is defined by ac IC IE VCB constant (3.7) The ac alpha is formally called the common-base.8. when IE 0 mA on Fig. (d) Again from Fig.8. For the moment.8 and 3. for reasons that will be more obvious when we examine transistor equivalent circuits in Chapter 7.6. 3. Alpha ( ) In the dc mode the levels of IC and IE due to the majority carriers are related by a quantity called alpha and defined by the following equation: dc IC IE (3. permitting the use of the magnitude of one for the other. (3. IE IC 4 mA. amplification factor.8 when IE 0 mA. 3. 3. (c) From Fig. 3. (3. for practical devices the level of characteristics of Fig. The use of an equation such as (3. 3.2) becomes IC IE ICBO (3. short-circuit.7 the resulting level of VBE is about 0. with most approaching the high end of the range.7 and 3.7 V for any level of emitter current. Solution (a) The characteristics clearly indicate that IC IE 3 mA. Biasing The proper biasing of the common-base configuration in the active region can be determined quickly using the approximation IC IE and assuming for the moment that 118 Chapter 3 Bipolar Junction Transistors . 3.8 would suggest that alpha typically extends from 0.8. For most situations the magnitudes of ac and dc are quite close. determine the resulting collector current if IE remains at 3 mA but VCB is reduced to 2 V. In other words. For ac situations where the point of operation moves on the characteristic curve.90 to 0.7) specifies that a relatively small change in collector current is divided by the corresponding change in IE with the collector-to-base voltage held constant. Eq. VBE is 0. on Fig. However. 3. the level of ICBO is usually so small that it is virtually undetectable on the graph of Fig.8. IC is therefore equal to ICBO. determine the resulting collector current if IE 3 mA and VCB 10 V.EXAMPLE 3.8.10c. 3.74 V. (d) Repeat part (c) using the characteristics of Figs. 3. (c) Using the characteristics of Figs. On Fig.

” For instance. 3. Some students feel that they can remember whether the arrow of the device symbol in pointing in or out by matching the letters of the transistor type with the appropriate letters of the phrases “pointing in” or “not pointing in.7 is quite small and typically varies from 10 to 100 .12). – 3. For the common-base configuration the ac input resistance determined by the characteristics of Fig.5 TRANSISTOR AMPLIFYING ACTION Now that the relationship between IC and IE has been established in Section 3. The dc biasing does not appear in the figure since our interest will be limited to the ac response. the basic amplifying action of the transistor can be introduced on a surface level using the network of Fig. 3. there is a match between the letters npn and the italic letters of not pointing in and the letters pnp with pointing in. The result is the configuration of Fig. 3. 3. The arrow of the symbol defines the direction of conventional flow for IE IC. The difference in resistance is due to the forward-biased junction at the input (base to emitter) and the reverse-biased junction at the output (base to collector).8 is quite high (the more horizontal the curves the higher the resistance) and typically varies from 50 k to 1 M (100 k for the transistor of Fig.12.11 for the pnp transistor. If we assume for the moment that IL and VL Ii 1 (Ic 10 mA ILR (10 mA)(5 k ) 50 V Ii pnp E B Ri C IL + V i = 200 mV 20 Ω + Ro 100 k Ω R 5 k Ω VL – Figure 3. For the npn transistor the polarities will be reversed. we find that Ii Vi Ri 200 mV 20 ac 10 mA Ie). The dc supplies are then inserted with a polarity that will support the resulting current direction. IB 0 A.4. The output resistance as determined by the curves of Fig.5 Transistor Amplifying Action 119 . 3.11 Establishing the proper biasing management for a common-base pnp transistor in the active region. Using a common value of 20 for the input resistance.Figure 3.12 Basic voltage amplification action of the common-base configuration. 3.

transfer resistor → transistor 3. collector. Even though the transistor configuration has changed.6 COMMON-EMITTER CONFIGURATION The most frequently encountered transistor configuration appears in Fig. Two sets of characteristics are again necessary to describe fully the behavior of the common-emitter configuration: one for the input or base-emitter circuit and one for the output or collector-emitter circuit. 120 Chapter 3 Bipolar Junction Transistors .13 Notation and symbols used with the common-emitter configuration: (a) npn transistor. (b) pnp transistor.14. 3. The basic amplifying action was produced by transferring a current I from a lowto a high-resistance circuit. IE. The combination of the two terms in italics results in the label transistor.The voltage amplification is Av VL Vi 50 V 200 mV 250 Typical values of voltage amplification for the common-base configuration vary from 50 to 300. that is. The emitter. The input characteristics are a plot of the input current (IB) versus the input voltage (VBE) for a range of values of output voltage (VCE). 3. Both are shown in Fig. the current relations developed earlier for the common-base configuration are still applicable.13 for the pnp and npn transistors. and base currents are shown in their actual conventional current direction. That is. The current amplification (IC/IE) is always less than 1 for the comIE mon-base configuration. IE IC IB and IC For the common-emitter configuration the output characteristics are a plot of the output current (IC) versus output voltage (VCE) for a range of values of input current (IB). It is called the common-emitter configuration since the emitter is common or reference to both the input and output terminals (in this case common to both the base and collector terminals). Figure 3. This latter characteristic should be obvious since IC and is always less than 1.

for all practical purposes. compared to milliamperes of IC. The region to the left of VCEsat is called the saturation region. or power amplification. 3. The cutoff region for the common-emitter configuration is not as well defined as for the common-base configuration. That is. The reason for this difference in collector characteristics can be derived through the proper manipulation of Eqs. The active region for the common-emitter configuration is that portion of the upper-right quadrant that has the greatest linearity.14a this region exists to the right of the vertical dashed line at VCEsat and above the curve for IB equal to zero. that is. You will recall that these were the same conditions that existed in the active region of the common-base configuration.6): Substitution gives Rearranging yields Eq. In Fig.0 VBE (V) I B (µA) VCE = 1 V VCE = 10 V VCE = 20 V Figure 3. while the base-emitter junction is forward-biased.8) 121 3. Eq. 3. For the common-base configuration.3) and (3. (3. 3. indicating that the collector-to-emitter voltage will influence the magnitude of the collector current.IC (mA) 8 7 6 (Saturation region) 5 4 30 µA 3 2 10 µA 1 I B = 0 µA 0 VCEsat 5 10 ~ I CEO = β I CBO (a) 15 (Cutoff region) (b) 20 VCE (V) (Active region) 20 µA 90 µA 80 µA 70 µA 60 µA 100 50 µA 40 µA 90 80 70 60 50 40 30 20 10 0 0. when the input current IE was equal to zero. (3. so that the curve IE 0 and the voltage axis were. Note that on the characteristics of Fig. the collector current was equal only to the reverse saturation current ICO. (3. Consider also that the curves of IB are not as horizontal as those obtained for IE in the common-base configuration. In the active region of a common-emitter amplifier the collector-base junction is reverse-biased. Note on the collector characteristics of Fig.6).6 0. one.2 0.14 that IC is not equal to zero when IB is zero. that region in which the curves for IB are nearly straight and equally spaced.4 0.3): IC IC IB 1 IC (IC IE ICBO IB) ICBO 1 ICBO (3.14 Characteristics of a silicon transistor in the common-emitter configuration: (a) collector characteristics.6 Common-Emitter Configuration . The active region of the common-emitter configuration can be employed for voltage. (b) base characteristics.14 the magnitude of IB is in microamperes.8 1. current.

16. 3. where IB 0 A. The result supports our earlier conclusion that for a transistor in the “on” or active region the base-toemitter voltage is 0. cutoff will exist for switching purposes when IB 0 A or IC ICEO for silicon transistors only.2 0. as reflected in the characteristics of Fig. For linear (least distortion) amplification purposes. I B (µA) 100 90 80 70 60 50 40 30 20 10 Figure 3. The cutoff condition should ideally be IC 0 mA for the chosen VCE voltage.996.25 mA. the collector current defined by the condition IB 0 A will be assigned the notation indicated by Eq. (3. resulting in the approximate equivalent of Fig.996 250ICBO If ICBO were 1 A. and substitute a typical value of such as 0. 3. the region below IB 0 A is to be avoided if an undistorted output signal is required.8 1 V BE (V) 0.4 0. 0 0. ICEO ICBO 1 (3. the resulting collector current with IB 0 A would be 250(1 A) 0. a transistor will have two points of operation of interest: one in the cutoff and one in the saturation region. In other words. For the common-emitter configuration the same approach can be taken.004 1 ICBO 0.9) IB 0 A In Fig.7 V Figure 3. For germanium transistors. 3. This condition can normally be obtained for germanium transistors by reverse-biasing the base-to-emitter junction a few tenths of a volt.7 V for any level of IE greater than 0 mA.14. 3. Since ICEO is typically low in magnitude for silicon materials. cutoff for switching purposes will be defined as those conditions that exist when IC ICBO.14b.6 0.9).7 V. In this case the voltage is fixed for any level of base current. the resulting collector current is the following: IC (0 A) 1 ICBO 0.15 Circuit conditions related to ICEO. however.15 the conditions surrounding this newly defined current are demonstrated with its assigned reference direction. Recall for the common-base configuration that the input set of characteristics was approximated by a straight-line equivalent that resulted in VBE 0. When employed as a switch in the logic circuitry of a computer. For future reference.16 Piecewise-linear equivalent for the diode characteristics of Fig.If we consider the case discussed above. cutoff for the commonemitter configuration will be defined by IC ICEO. 122 Chapter 3 Bipolar Junction Transistors .

4 mA. At any location on this vertical line the voltage VCE is 7.14. certainly reveals the relative magnitude of one current to the other. with most in the midrange.(a) Using the characteristics of Fig.5 V as indicated on Fig.14a we find that IC 2. Since the collector current is usually the output current for a common-emitter configuration and the base current the input current. determine IC at VBE 0.4.11) is similar in format to the equation for ac in Section 3.11) is best described by a numerical example using an actual set of characteristics such as appearing in Fig. The subscripts FE are derived from forward-current amplification and common-emitter configuration.14a and repeated in Fig. For ac situations an ac beta has been defined as follows: ac IC IB (3. dc hFE. the result can be used to find ac using an equation to be derived shortly.6 Common-Emitter Configuration 123 .17.14. On specification sheets ac is normally referred to as hfe. The restriction of VCE constant requires that a vertical line be drawn through the operating point at VCE 7. 3. 3. The lowercase letter h continues to refer to the hybrid equivalent circuit to be described in Chapter 7 and the fe to the forward current gain in the common-emitter configuration. respectively.14b. is one that can be described with some clarity. 3.17.5 mA at the intersection of IB 20 A and VCE 15 V. (b) Using the characteristics of Fig.5 V. however. amplification factor. (b) Using Fig. (3. From Fig. As for . determine IC at IB 30 A and VCE 10 V.7 V. Note that the only difference between the notation used for the dc beta.7 V and VCE 15 V. specifically. and in fact. The use of Eq. the term amplification is included in the nomenclature above. is the type of lettering for each subscript quantity. On specification sheets dc is usually included as hFE with the h derived from an ac hybrid equivalent circuit to be introduced in Chapter 7. 3. For practical devices the level of typically ranges from about 50 to over 400. the collector current is 200 times the magnitude of the base current.11) VCE constant The formal name for ac is common-emitter. The procedure for obtaining ac from the characteristic curves was not described because of the difficulty of actually measuring changes of IC and IE on the characteristics. IB 20 A at VBE 0. Let us determine ac for a region of the characteristics defined by an operating point of IB 25 A and VCE 7.10) where IC and IB are determined at a particular operating point on the characteristics. forward-current. Equation (3. 3. EXAMPLE 3.2 Solution (a) At the intersection of IB 30 A and VCE 10 V. a constant. 3.5 V. Equation (3. IC 3. 3. The change 3.11). Beta ( ) In the dc mode the levels of IC and IB are related by a quantity called beta and defined by the following equation: dc IC IB (3. For a device with a of 200.

I C (mA) 9 8 90 µA 80 µA 7 70 µA 60 µA 50 µA 6 5 40 µA 4 IC2 ∆ IC IC1 3 Q . the collector current will be about 100 times the magnitude of the base current. For this situation the IB 20 A and 30 A curves meet the requirement without extending too far from the Q-point. It should be mentioned that the best determination is usually made by keeping the chosen IB as small as possible. in IB ( IB) as appearing in Eq.2 mA 20 A 1 mA 10 A IC IB 2.17 Determining ac and dc from the collector characteristics.pt. the two levels of IC can be determined by drawing a horizontal line over to the vertical axis and reading the resulting values of IC. At the two intersections of IB and the vertical axis.11) is then defined by choosing two points on either side of the Q-point along the vertical axis of about equal distances to either side of the Q-point. If we determine the dc beta at the Q-point: dc 2.7 mA 25 A 108 124 Chapter 3 Bipolar Junction Transistors .2 mA 30 A 100 The solution above reveals that for an ac input at the base. They also define levels of IB that are easily defined rather than have to interpolate the level of IB between the curves. 2 IB1 10 µA 1 IB = 0 µA 0 5 VCE = 7.5 V 10 15 20 25 VCE (V) IB 2 25 µA 20 µA 30 µA Figure 3. The resulting ac for the region can then be determined by IC2 IC1 IC ac IB VCE constant IB2 IB1 3. (3.

3. the levels of ac and dc are usually reasonably close and are often used interchangeably. the smaller the level of ICEO. the value of ac will vary somewhat from one transistor to the next even though each transistor has the same number code. note that ICEO 0 A.Although not exactly equal. 3. Figure 3. it is assumed to be about the same magnitude as dc. Calculating the ac at the Q-point indicated will result in ac IC IB VCE constant 9 mA 45 A 7 mA 35 A 2 mA 10 A 200 Determining the dc beta at the same Q-point will result in dc IC IB 8 mA 40 A 200 revealing that if the characteristics have the appearance of Fig. if ac is known. the magnitude of ac and dc will be the same at every point on the characteristics. Since the trend is toward lower and lower levels of ICEO. it is certainly sufficient to validate the approximate approach above.6 Common-Emitter Configuration 125 .18. For the analysis to follow the subscript dc or ac will not be included with to avoid cluttering the expressions with unnecessary labels. Note that the step in IB is fixed at 10 A and the vertical spacing between curves is the same at every point in the characteristics—namely. In particular. Although a true set of transistor characteristics will never have the exact appearance of Fig. and vice versa. it will normally be used for both the dc and ac calculations. For dc situations it will simply be recognized as dc and for any ac analysis as ac. it does provide a set of characteristics for comparison with those obtained from a curve tracer (to be described shortly). the validity of the foregoing approximation is further substantiated. 3. the level of ac would be the same in every region of the characteristics. 3. If the characteristics had the appearance of those appearing in Fig.18. If a value of is specified for a particular transistor configuration. the closer the magnitude of the two betas. That is.18 Characteristics in which ac is the same everywhere and ac dc. Generally. 2 mA. The variation may not be significant but for the majority of applications.18. Keep in mind that in the same lot.

That is. and from IC/IE we have introduced thus far. 3. we find that ICEO or ICEO ( 1 (3.15) (31. 3.4) Both of the equations above play a major role in the analysis in Chapter 4. Biasing The proper biasing of a common-emitter amplifier can be determined in a manner similar to that introduced for the common-base configuration. Beta is a particularly important parameter because it provides a direct link between current levels of the input and output circuits for a common-emitter configuration.12b) ICBO 1 1 1)ICBO ICBO (3. Next. The first step is to indicate the direction of IE as established by the arrow in the transistor symbol as shown in Fig. Let us assume that we are presented with an npn transistor such as shown in Fig.19b. 3. Using IE IC/ . IC and since IE IC IB we have IE ( IB IB IB 1)IB (3.13) as indicated on Fig. recall that ICEO but using an equivalence of 1 1 derived from the above. the other currents are introduced as 126 Chapter 3 Bipolar Junction Transistors . Substituting into IE we have IC IC IC IB IC and dividing both sides of the equation by IC will result in 1 or so that 1 1 ( 1 1) (3.A relationship can be developed between and using the basic relationships IC/IB we have IB IC/ .14a.19a and asked to apply the proper biasing to place the device in the active region.12a) or In addition.

3. 3. all the currents and polarities of Fig. If the transistor of Fig.19c to complete the picture. shown. shown in Fig. opposite to that of the common-base and common-emitter configurations.Figure 3. 3.20 with the proper current directions and voltage notation. 3.19 Determining the proper biasing arrangement for a commonemitter npn transistor configuration.19c would be reversed.7 COMMON-COLLECTOR CONFIGURATION The third and final transistor configuration is the common-collector configuration. (b) npn transistor. the supplies are introduced with polarities that will support the resulting directions of IB and IC as shown in Fig.19 was a pnp transistor.20 Notation and symbols used with the common-collector configuration: (a) pnp transistor. The same approach can be applied to pnp transistors. keeping in mind the Kirchhoff’s current law relationship: IC IB IE.7 Common-Collector Configuration 127 . The common-collector configuration is used primarily for impedance-matching purposes since it has a high input impedance and low output impedance. 3. 3. Finally. IE E IB B V BB C IC IE IB V EE V BB C B E p n p n p n IC V EE IE E IB B IC C (a) B IB IE E IC C (b) Figure 3.

21 with the load resistor connected from emitter to ground.8 LIMITS OF OPERATION For each transistor there is a region of operation on the characteristics which will ensure that the maximum ratings are not being exceeded and the output signal exhibits minimum distortion. All of the limits of operation are defined on a typical transistor specification sheet described in Section 3.21. The horizontal voltage axis for the common-collector configuration is obtained by simply changing the sign of the collector-to-emitter voltage of the common-emitter characteristics.22.6.22 Defining the linear (undistorted) region of operation for a transistor. For the common-collector configuration the output characteristics are a plot of IE versus VEC for a range of values of IB. 3. 128 Chapter 3 Bipolar Junction Transistors . the output characteristics of the common-collector configuration are the same as for the common-emitter configuration. is the same for both the common-emitter and commoncollector characteristics. 3. From a design viewpoint. Such a region has been defined for the transistor characteristics of Fig. It can be designed using the common-emitter characteristics of Section 3. A common-collector circuit configuration is provided in Fig. The vertical line on the characteristics defined as VCEsat specifies Figure 3. For all practical purposes.9. For the input circuit of the IE for the common-collector characteristics (since common-collector configuration the common-emitter base characteristics are sufficient for obtaining the required information. Note that the collector is tied to ground even though the transistor is connected in a manner similar to the common-emitter configuration. Finally. therefore. such as maximum collector current (normally referred to on the specification sheet as continuous collector current) and maximum collector-to-emitter voltage (often abbreviated as VCEO or V(BR)CEO on the specification sheet). Some of the limits of operation are self-explanatory.21 Common-collector configuration used for impedance-matching purposes.22. there is an almost unnoticeable change in the vertical scale of IC of the common-emitter characteristics if IC is replaced by 1). 3. For the transistor of Fig. 3. The input current. 3. ICmax was specified as 50 mA and VCEO as 20 V. there is no need for a set of commoncollector characteristics to choose the parameters of the circuit of Fig.C B E R Figure 3.

the more accurate the curve. The level of VCEsat is typically in the neighborhood of the 0. but a rough estimate is normally all that is required. 3. If we choose IC to be the maximum value of 50 mA and substitute into the relationship above. A rough estimate of the actual curve can usually be drawn using the three points defined above. One must then use the equation ICEO tablish some idea of the cutoff level if the characteristic curves are unavailable. the more points you have. 3. and solve for the resulting level of VCE.17). 3. the collector power dissipation was specified as 300 mW. (3. the level of IC is the following: (20 V)IC IC 300 mW 300 mW 20 V 15 mA defining a second point on the power curve. one must simply be sure that IC. The cutoff region is defined as that region below IC ICEO. and their product VCEIC fall into the range appearing in Eq. If the characteristic curves are unavailable or do not appear on the specification sheet (as is often the case). Operation in the resulting region of Fig. The question then arises of how to plot the collector power dissipation curve specified by the fact that PCmax or VCEIC VCEIC 300 mW 300 mW At any point on the characteristics the product of VCE and IC must be equal to 300 mW. we obtain VCEIC VCE (50 mA) VCE 300 mW 300 mW 300 mW 50 mA 6V As a result we find that if IC 50 mA. VCE. If we now choose VCE to be its maximum value of 20 V.22 will ensure minimum distortion of the output signal and current and voltage levels that will not damage the device.22.the minimum VCE that can be applied without falling into the nonlinear region labeled the saturation region. If we now choose a level of IC in the midrange such as 25 mA. 3.8 Limits of Operation 129 . 3.22.16) For the device of Fig. Of course. On some specification ICBO to essheets only ICBO is provided. we obtain VCE(25 mA) and VCE 300 mW 300 mW 25 mA 12 V as also indicated on Fig. then VCE 6 V on the power dissipation curve as indicated in Fig. This region must also be avoided if the output signal is to have minimum distortion. The maximum dissipation level is defined by the following equation: PCmax VCEIC (3.22.3 V specified for this transistor.

” “off. The maximum collector dissipation PCmax PD 625 mW. Although all the parameters have not been introduced.23j the effect of temperature and collector current on the level of hFE ( ac) is demonstrated. Certainly.15 mA. if we have a transistor with dc hFE 50 at room temperature. The 2N4123 is a general-purpose npn transistor with the casing and terminal identification appearing in the top-right corner of Fig.17) For the common-base characteristics the maximum power curve is defined by the following product of output quantities: PCmax VCBIC (3. and electrical characteristics.9 TRANSISTOR SPECIFICATION SHEET Since the specification sheet is the communication link between the manufacturer and user. Limits of Operation 7.18) 3. 3. At IC 50 mA it has dropped to 50/2 25. Since this is a normalized curve.17) using hFE 150 (the upper limit) and ICEO (150)(50 nA) 7. The derating factor under the maximum rating specifies that the maximum rating must be decreased 5 mW for every 1° rise in temperature above 25°C. 3. Most specification sheets are broken down into maximum ratings.23 is taken directly from the Small-Signal Transistors. the maximum value at 8 mA is 50.5 A.0075 mA can be considered to be 0 mA on an approximate basis.3 V.5 mA IC 200 mA 0.” and small-signal characteristics. FETs. Reference will then be made to this specification sheet to review the manner in which the parameter is presented. It also drops to this level if IC decreases to the low level of 0. for many applications the 7. The level of hFE has a range of 50 to 150 at IC 2 mA and VCE 1 V and a minimum value of 25 at a higher current of 50 mA at the same voltage. 3. while the smallsignal characteristics include the parameters of importance to ac operation. As IC increased beyond this level. Note in the maximum rating list that VCEmax VCEO 30 V with ICmax 200 mA. In Fig. thermal characteristics. At room temperature (25°C). The limits of operation have now been defined for the device and are repeated beICBO low in the format of Eq. In other words. In the “off” characteristics ICBO is specified as 50 nA and in the “on” characteristics VCEsat 0.5 A 0. and Diodes publication prepared by Motorola Inc. The “on” and “off” characteristics refer to dc limits. hFE drops off to one-half the value with IC equal to 50 mA.3 V VCE VCEIC 30 V 650 mW In the small-signal characteristics the level of hfe ( ac) is provided along with a plot of how it varies with collector current in Fig.ICEO VCEsat VCEIC IC VCE ICmax VCEmax PCmax (3.23a. note that hFE ( dc) is a maximum value of 1 in the neighborhood of about 8 mA. The electrical characteristics are further broken down into “on. it is particularly important that the information provided be recognized and correctly understood. a broad number will now be familiar.23f. The remaining parameters will be introduced in the chapters that follow. (3. normalizing reveals that the actual level of hFE 130 Chapter 3 Bipolar Junction Transistors . The information provided as Fig. 3.

3.23j is a log scale. You may want to look back at the plots of this section when you find time to review the first few sections of Chapter 11.9 Transistor Specification Sheet 131 .at any level of IC has been divided by the maximum value of hFE at that temperature and IC 8 mA. Note also that the horizontal scale of Fig.23 Transistor specification sheet. Log scales are examined in depth in Chapter 11. Figure 3. 3.

temperature. take note of the fact that the actual collector characteristics are not provided.0 5. In fact.5 mA IC = 50 µ A Figure 4 – Source Resistance IC = 100 µ A Source resistance = 500 Ω IC = 100 µ A 0.2 0.0 3.0 2.0 3.0 0.2 0.Before leaving this description of the characteristics.0 Hz Figure 3 – Frequency Variations 12 10 MF.5 mA Source resistance = 1 k Ω IC = 50 µ A 14 f = 1 kHz 12 10 8 6 4 2 0 0. The specification sheet can be a very valuable tool in the design or analysis mode.0 2.1 0. 3. and so on. Collector current (mA) (c) 100 200 td tr tf Figure 2 – Switching Times 3. As noted in the introduction to this section. Frequency (kHz) (d) 20 40 100 0.0 VCC = 3 V IC / IB = 10 VEB (off) = 0.7 1. Source Resistance (kΩ ) (e) 40 100 Figure 3. Figure 1 – Capacitance 10 7. TA = 25°C) Bandwidth = 1. all the parameters of the specification sheet have not been defined in the preceding sections or chapters. most specification sheets as provided by the range of manufacturers fail to provide the full characteristics.0 4.0 Cobo AUDIO SMALL SIGNAL CHARACTERISTICS NOISE FIGURE (VCE = 5 Vdc.1 Source resistance = 200 Ω IC = 1 mA MF.0 1. Noise figure (dB) Source resistance = 200 Ω IC = 0.0 7.0 1.5 0.3 0.0 10 20 30 50 I C .4 1 2 4 10 f.0 7.0 10 20 R S .2 0. Noise figure (dB) 8 6 4 2 0 0.4 1.23 Continued.0 10 Reverse bias voltage (V) (b) 20 30 40 5.1 IC = 1 mA IC = 0.0 5. the specification sheet provided in Fig.0 Capacitance (pF) 5.0 2.23 will be referenced continually in the chapters to follow as parameters are introduced. 132 Chapter 3 Bipolar Junction Transistors .5 V 2.0 C ibo Time (ns) 200 ts 100 70 50 30 20 10. and every effort should be made to be aware of the importance of each parameter and how it may vary with changing levels of current. It is expected that the data provided are sufficient to use the device effectively in the design process. However.

0 h FE DC Current gain (normalized) TJ = +125° C +25° C VCE = 1 V 1.2 0.0 0.5 1.0 10 0.7 1.0 5.5 0.2 0.0 I C . Collector current (mA) (f) 5.0 0.1 0. Collector current (mA) (g) 5. Collector current (mA) (h) 5.0 I C .0 1.5 0.0 3.0 2. Collector current (mA) (j) 20 30 50 70 100 200 Figure 3.0 10 STATIC CHARACTERISTICS (h) STATIC CHARACTERISTICS Figure 9 – DC Current Gain (i) 2.5 0.9 Transistor Specification Sheet 133 .0 5.0 2.0 0.1 0.0 0.0 2.0 3.0 2.0 I C .h PARAMETERS VCE = 10 V.7 0.3 0.2 0.0 10 I C . TA = 25°C Figure 5 – Current Gain 300 200 100 Figure 6 – Output Admittance h oe Output admittance (µ mhos) 50 20 10 5.1 7.7 0.1 0. f = 1 kHz.0 2.1 0.5 1.0 7.2 0.5 0.5 1.3 0.5 1.0 2.2 0.0 10 Figure 7 – Input Impedance 20 10 Figure 8 – Voltage Feedback Ratio h re Voltage feedback ratio (× 10−4 ) h ie Input impedance (kΩ) 10 5.0 10 h fe Current gain 100 70 50 30 0.0 I C . 3.1 –55°C 0.2 0.0 2.23 Continued.0 2.0 1.2 0. Collector current (mA) (i) 5.0 1.

Curve Tracer The curve tracer of Fig.25. resulting in the scale shown below the characteristics.3. let us determine ac at a Q-point of IC 7 mA and VCE 5 V. as indicated on Fig. VCE = 5 V) IB 1 = 30 µ A VCE = 5 V 134 Chapter 3 Bipolar Junction Transistors . The last scale factor provided can be used to quickly determine the ac for any region of the characteristics. In this region of the display. digital meter. The smaller displays to the right reveal the scaling to be applied to the characteristics.24 at IC 7 mA and VCE 5 V. the distance between IB curves is 190 of a division.2 mA IB 2 = 40 µ A ∆ IC 9 ≅ 10 div Figure 3. 0 mA 0V 1V 2V 3V 4V 5V 6V 7V 8V 0 µA 9V 10 V IC = 8 mA IC 2 = 8. The horizontal sensitivity is 1 V/div. Using the factor specified. there are three routes one can take to check a transistor: curve tracer. and ohmmeter. 1. 3. resulting in the scale shown to the left of the monitor’s display. The vertical sensitivity is 2 mA/div. For instance.24 Curve tracer response to 2N3904 npn transistor. we find that ac 9 200 div 10 div 180 20 mA 18 mA 80 µ A 16 mA 70 µA 14 mA 60 µA 12 mA 50 µA 10 mA 40 µA 8 mA 30 µA 6 mA 20 µA 4 mA 10 µA 2 mA B or gm per div 200 Per Step 10 µ A Horizontal per div 1V Vertical per div 2 mA Figure 3.24 once all the controls have been properly set.4 mA IC = 6 mA Q-point ( IC = 7 m A. 3.10 TRANSISTOR TESTING As with diodes. 3.25 Determining ac for the transistor characteristics of Fig. starting at 0 A for the bottom curve.45 will provide the display of Fig. IC 1 = 6. The step function reveals that the curves are separated by a difference of 10 A. Simply multiply the displayed factor by the number of divisions between IB curves in the region of interest.

It can measure capacitance and frequency in addition to the normal functions of voltage.Using Eq. collector and emitter) of a transistor it is assumed that this determination can be made by simply looking at the orientation of the leads on the casing. Note that this versatile instrument can also check a diode.26 Transistor tester. the forward.11) gives us ac IC IB VCE constant IC2 IB2 IC1 IB1 8.) Ohmmeter An ohmmeter or the resistance scales of a DMM can be used to check the state of a transistor.7 V with the red (positive) lead connected to the base and the black (negative) lead connected to the emitter. A reversal of the leads should result in an OL indication to represent the reverse-biased junction.28 Checking the reverse-biased base-to-collector junction of an npn transistor. (Courtesy Computronics Technology.4 mA 30 A 1. 3. Figure 3. Similarly. which is also provided on the digital display. For a pnp transistor the leads are reversed for each junction. Recall that for a transistor in the active region the base-to-emitter junction is forward-biased and the base-to-collector junction is reverse-biased. Advanced Digital Meters Advanced digital meters such as that shown in Fig. If both junctions of a transistor result in the expected readings the type of transistor can also be determined by simply noting the polarity of the leads as applied to the base-emitter junction. For an npn transistor. 3. a large or small resistance in both directions (reversing the leads) for either junction of an npn or pnp transistor indicates a faulty device. the forward-biased junction (biased by the internal supply in the resistance mode) from base to emitter should be checked as shown in Fig.27 Checking the forward-biased base-to-emitter junction of an npn transistor. Inc. Essentially. (3. A high resistance reading would indicate a pnp transistor. the forward-biased junction should register a relatively low resistance while the reverse-biased junction shows a much higher resistance. With the collector open the base-to-emitter junction should result in a low voltage of about 0. The reverse-biased baseto-collector junction (again reverse-biased by the internal supply) should be checked as shown in Fig. with the emitter open. current. Note the choice of pnp or npn and the availability of two emitter connections to handle the sequence of leads as connected to the casing. Although an ohmmeter can also be used to determine the leads (base.2 mA 40 A 6.26 are now available that can provide the level of hFE using the lead sockets appearing at the bottom left of the dial. In fact. 3.and reverse-bias states of the base-to-collector junction can be checked. High R Ω + – C B E Figure 3. 135 .27 and result in a reading that will typically fall in the range of 100 to a few kilohms.10 Transistor Testing Low R Open Ω + – B E Figure 3.28 with a reading typically exceeding 100 k .8 mA 10 A 180 verifying the determination above. and resistance measurements. in the diode testing mode it can be used to check the p-n junctions of a transistor. If the positive ( ) lead is connected to the base and the negative lead ( ) to the emitter a low resistance reading would indicate an npn transistor. The level of hFE is determined at a collector current of 2 mA for the Testmate 175A. Obviously. therefore. 3.

Whenever possible.to medium-power devices. while those with the small can (top hat) or plastic body are low. 136 Chapter 3 Bipolar Junction Transistors .11 TRANSISTOR CASING AND TERMINAL IDENTIFICATION After the transistor has been manufactured using one of the techniques described in Chapter 12. a copper frame. 3. gold. leads of. 3. A few of the methods commonly used are indicated in Fig. and an epoxy encapsulation.32b. or nickel are then attached and the entire structure is encapsulated in a container such as that shown in Fig. (d) Courtesy International Rectifier Corporation.30 Transistor terminal identification.31. Figure 3.29. typically. (b) and (c) Courtesy of Motorola Inc. Note the very small size of the actual semiconductor device. Those with the heavy duty construction are high-power devices.30. 3. As with the diode IC package. aluminum. the indentation in the top surface reveals the number 1 and 14 pins. There are gold bond wires.32a. The internal pin connections appear in Fig. Four (quad) individual pnp silicon transistors can be housed in the 14-pin plastic dual-in-line package appearing in Fig. Figure 3. collector.. The internal construction of a TO-92 package in the Fairchild line appears in Fig. or base of a transistor.3. the transistor casing will have some marking to indicate which leads are connected to the emitter.29 Various types of transistors: (a) Courtesy General Electric Company. 3. 3.

31 Internal construction of a Fairchild transistor in a TO-92 package. (b) pin connections.32 Type Q2T2905 Texas Instruments quad pnp silicon transistors: (a) appearance. (Courtesy Texas Instruments Incorporated.) 3. (Courtesy Fairchild Camera and Instrument Corporation.Figure 3.) (Top View) C 14 B 13 E 12 NC 11 E 10 B 9 C 8 1 C (a) 2 B 3 E 4 NC (b) 5 E 6 B 7 C NC – No internal connection Figure 3.11 Transistor Casing and Terminal Identification 137 .

be sure to enable the nested sweep. When chosen. and the name is inserted as VBB.12 PSPICE WINDOWS Since the transistor characteristics were introduced in this chapter it seems appropriate that a procedure for obtaining those characteristics using PSpice Windows should be examined. corresponding with a current of 100 A. Use an Increment of 0.slb library and start with the letter Q. if you placed a resistor a few elements ago. corresponding with a change in base current of 20 A between IB levels. Click the location once. however.3. choose OK. followed by selecting Automatically run Probe after simulation. First. Again. followed by a clicking of the Simulation icon (recall that it was the 138 Chapter 3 Bipolar Junction Transistors . Before leaving the dialog box. choose the Analysis Setup icon and enable the DC Sweep. since only one curve would result.01 V to ensure a continuous. a DC Nested Sweep dialog box will appear and ask us to repeat the choices just made for the voltage VBB. and the resistor will appear on the screen.7 V to correspond with an initial current of 20 A as determined by IB VBB RB VBE 2. This option allows you to retrieve elements that have been used in the past. For instance. This is unnecessary for the diode. Type in the Name VCC with a Start Value of 0 V and an End Value of 10 V. detailed plot.7 V 100 k 20 A The Increment will be 2V. The fact that there are a series of curves defined by the levels of IB will require that a sweep of IB values (a nested sweep) occur within a sweep of collector-to-emitter voltages. Then.7 V. Figure 3. Voltage Source and Linear are chosen. The library includes two npn transistors and two pnp transistors. 3. simply return to the scroll bar and scroll until the resistor R appears. followed by a closing of the Analysis Setup. The voltage VCC will establish our main sweep while the voltage VBB will determine the nested sweep. For future reference. the network in Fig. This time we will automatically Run Probe after the analysis by choosing AnalysisProbe Setup. this time we have to choose the Nested Sweep at the bottom left of the dialog box. The Start Value will now be 2.7 V 0. The final value will be 10. Next. and choose Voltage Source and Linear. Rather than click OK. After choosing OK. note the panel at the top right of the menu bar with the scroll control when building networks.33 is established using the same procedure defined in Chapter 2. and we are ready for the analysis. Click on DC Sweep. The transistors are listed in the EVAL.33 Network employed to obtain the collector characteristics of the Q2N2222 transistor.

click OK. since VCC is the collector-to-emitter voltage. you will find that its value is about 190—even though Bf in the list of specifications is 255. and a dialog box appears asking for the text material. however. the OrCAD MicroSim Probe screen will automatically appear. An adjustment of the range of the y-axis to 0–30 mA using the Y-Axis Settings will result in the characteristic curves of Fig.9 (don’t forget the close parentheses at the end of the listing) and follow with an OK and a Simulation. By choosing User Defined. the equal spacing of the curves throughout reveals that beta is the same everywhere (as specified by our new device characteristics). If the ac beta is determined in the middle of the graph. Using the ABC icon on the menu bar.9. since it appears as the horizontal axis of the Probe response. In fact. the other parameters of the element have a noticeable effect on the total operation. Enter the desired text. For the vertical axis. there is no need to label the voltage at the collector. Unfortunately. like the diode. Using a difference of 5 mA between any two curves and dividing by the difference in IB of 20 A will result in a of 250. there is no need to touch the X-Axis Settings at all if we recognize that VCC is the collector-to-emitter voltage. Choose OK again. the range can be set from 0 to 20 mA with a Linear scale.33. they extend from 10 to 20 mA on the vertical axis. we turn to Trace-Add and obtain the Add Traces dialog box. However. It can then be placed in the desired location.34 result.icon with the yellow background and two waveforms). the various levels of IB can be inserted along with the axis labels VCE and IC. Simply click on the icon.12 PSpice Windows 139 .35. if we return to the diode specifications through Edit-Model-Edit Instance Model (Text) and remove all parameters of the device except Bf 255. This time. which is essentially the same as that specified for the device.34 Collector characteristics for the transistor of Figure 3. 3. Note first that the curves are all horizontal. This can be corrected by choosing Plot and then Y-Axis Settings to obtain the Y-Axis Settings dialog box. a new set of curves will result. and it will appear on the screen. Figure 3. 3. Again. we obtain the transistor characteristics. In addition. meaning that the element is void of any resistive elements. 3. and the characteristics of Fig. Choosing IC(Q1) and OK.

35 Ideal collector characteristics for the transistor of Figure 3. 11. What names are applied to the two types of BJT transistors? Sketch the basic construction of each and label the various minority and majority carriers in each. 6.33.10c a valid one [based on the results of part (a)]? 140 Chapter 3 Bipolar Junction Transistors . 8. 3. 10. Describe the resulting carrier motion. From memory.FIGURE 3.4 Common-Base Configuration 10. Sketch a figure similar to Fig.4 for the reverse-biased junction of an npn transistor. (b) For networks in which the magnitude of the resistive elements is typically in kilohms.3 for the forward-biased junction of an npn transistor. Is it reasonable to assume on an approximate basis that VCB has only a slight effect on the relationship between VBE and IE? 12.10b. 3. (a) Determine the average ac resistance for the characteristics of Fig. 3. 3. Draw the graphic symbol next to each. 3. and then insert the conventional flow direction for each current. How must the two transistor junctions be biased for proper transistor amplifier operation? 4. PROBLEMS § 3. What is the source of the leakage current in a transistor? 5. Sketch a figure similar to Fig. is the approximation of Fig. 3. 7. Sketch a figure similar to Fig. Which of the transistor currents is always the largest? Which is always the smallest? Which two currents are relatively close in magnitude? 9. What is the major difference between a bipolar and a unipolar device? § 3. sketch the transistor symbol for a pnp and an npn transistor. Describe the resulting carrier motion. Is any of this information altered by changing from a silicon to a germanium base? 2. determine the levels of IC and IB.5 for the majority. Using the characteristics of Fig.and minority-carrier flow of an npn transistor.2 Transistor Construction 1. Describe the resulting carrier motion.3 Transistor Operation 3. If the emitter current of a transistor is 8 mA and IB is 1/100 of IC. determine VBE at IE 5 mA for VCB 1.7. and 20 V. § 3.

(a) Using the characteristics of Figs. does the value of ac change from point to point on the characteristics? Where are the high values located? Can you develop any general conclusions about the value of ac on a set of collector characteristics? (e) The chosen points in this exercise are the same as those employed in Problem 23. Repeat part (a) at IB 5 A and VCE 15 V. find the dc beta at an operating point 8 V and IC 2 mA. (c) How have the changes in VCB affected the resulting level of IC? (d) On an approximate basis. 3. 3. 3. Repeat part (a) at IB 30 A and VCE 10 V. 3.12 if the source has an internal resistance of 100 in series with Vi. calculate ICBO.998. (a) For the common-emitter characteristics of Fig. determine dc at IB 80 A and VCE 5 V. * 21. (The other circuit values remain the same.98. 30 A. (a) Given an dc of 0. 3. (c) At VCE 8 V. * 22.12 if Vi R 1 k .14.14a. does the value of dc change from point to point on the characteristics? Where were the higher values found? Can you develop any general conclusions about the value of dc on a set of characteristics such as those provided in Fig.14a.6 Common-Emitter Configuration 19. and memory only. (a) Using the characteristics of Fig.5 mA 14. and (d). 3. (b) Determine dc if IE 2. Repeat part (a) at IB 30 A and VCE 10 V.10b. (c) Find IE if IB 40 A and dc is 0. determine IC if IE 4 mA. Reviewing the results of parts (a) through (c). determine ac at IB 80 A and VCE 5 V. (a) (b) (c) (d) Using the characteristics of Fig. Calculate the voltage gain (Av VL/Vi) for the network of Fig.5 Transistor Amplifying Action 17. (b) Determine VBE if IC 5 mA and VCB 10 V. Define ICBO and ICEO. Reviewing the results of parts (a) through (c). (d) Repeat part (b) using the characteristics of Fig. Calculate the voltage gain (Av VL/Vi) for the network of Fig. (c) Using the dc determined in part (b). of VCE (b) Find the value of corresponding to this operating point. (e) Compare the solutions for VBE for parts (b). (a) Using the characteristics of Fig. How are they different? How are they related? Are they typically close in magnitude? 20.14a? * 24. Problems 141 . From memory. 16.14a.7 and 3. determine IC if VCB 10 V and VBE 800 mV.8.8.13. (c) Repeat part (b) using the characteristics of Fig. 3. (b) Repeat part (a) for IE 4. (a) (b) (c) (d) 10 V. (d) Calculate the approximate value of ICBO using the dc beta value obtained in part (a).14: (a) Find the value of IC corresponding to VBE 750 mV and VCE (b) Find the value of VCE and VBE corresponding to IC 3 mA and IB 5 V. If Problem 23 was performed. Repeat part (a) at IB 5 A and VCE 15 V.10c. how are IE and IC related based on the results above? 4. determine ICEO at VCE (b) Determine dc at IB 10 A and VCE 10 V. § 3. (c). Can the difference be ignored if voltage levels greater than a few volts are typically encountered? 15. Using the characteristics of Fig. find the corresponding value of ICEO.) 500 mV and 18. 3.5 mA and VCB 16 V. determine the resulting collector current if IE and VCB 4 V. 23. Using the characteristics of Fig. 3. sketch the common-base BJT transistor configuration (for npn and pnp) and indicate the polarity of the applied bias and resulting current directions. 3.8 mA and IB 20 A. 3. 3. compare the levels of dc and ac for each point and comment on the trend in magnitude for each quantity. § 3.

Note that the vertical scale is a log scale that may require reference to Section 11. and PCmax 30 mW. § 3.14 if ICmax 7 mA. 3.14. 3. 3. Then calculate dc and the resulting level of IE. (a) (b) (c) (d) (e) (f) Using the characteristics of Fig. Using the characteristics of Fig. what is the expected value of ICEO using the average value of dc? 35. Can you explain why? * 37. Is the change significant for the specified temperature range? Is it an element to be concerned about in the design process? § 3. How does the range of hFE (Fig.8 if ICmax 6 mA.23b. 3.23j. determine dc at IB 25 A and VCE 10 V. and IE. 3. An input voltage of 2 V rms (measured from base to ground) is applied to the circuit of Fig.23(j).1 V.10 Transistor Testing 39. 3.24. 27.2. determine the level of dc at IC 10 mA at the three levels of temperature appearing in the figure. VCEmax.9 Transistor Specification Sheet 32. determine ac at IC 14 mA and VCE Determine dc at IC 1 mA and VCE 8 V. sketch the boundaries of operation for the device. Determine the region of operation for a transistor having the characteristics of Fig. dc dc. (Use the level of IC determined by IC dcIB. 3. sketch the common-emitter configuration (for npn and pnp) and insert the proper biasing arrangement with the resulting current directions for IB. 34. Determine ac at IC 14 mA and VCE 3 V.23(f)) for the range of IC from 0. and PCmax 40 mW. Referring to Fig. Is the change one that should be considered in a design situation? * 38. VCEmax 17 V. For a transistor having the characteristics of Fig. IC. How does the level of ac and dc compare in each region? Is the approximation dc ac a valid one for this set of characteristics? 3 V. determine whether the input capacitance in the common-base configuration increases or decreases with increasing levels of reverse-bias potential. normalized from hFE of hfe (Fig. 3. Using the characteristics of Fig. Using the characteristics of Fig. Determine the region of operation for a transistor having the characteristics of Fig. From memory.7 Common-Collector Configuration 28. determine how much the level of hfe has changed from its value at 1 mA to its value at 10 mA.23. and memory only. 3.23f. ICmax and VCEsat. *Please Note: Asterisks indicate more difficult problems. 180 and IC 2. Using the characteristics of Fig.0 mA. calculate the circuit voltage amplification (Av Vo /Vi ) and emitter current for RE 1 k . VCBmax 15 V. 29. Assuming that the emitter voltage follows the base voltage exactly and that Vbe (rms) 0. 3. Based on the data of Fig. determine the corresponding value of . (a) Given that (b) Given dc (c) Given that dc 0.987. § 3. 3. 3. find IE and IB. 33. 31. 142 Chapter 3 Bipolar Junction Transistors .) 26.25. 3. Determine dc at IC 1 mA and VCE 8 V.8 Limits of Operation 30.21. determine the temperature range for the device in degrees Fahrenheit. determine the corresponding value of 120. § 3.23 regarding PDmax.23. Using the information provided in Fig. sketch the input and output characteristics of the common-collector configuration.1 to 10 mA? 100) compare with the range 36.14a. 3.

one must keep in mind that during the design or synthesis stage the choice of parameters for the required dc levels will affect the ac response. Each design will also determine the stability of the system. In actuality. In Section 4.3) 4 In fact. Too often it is assumed that the transistor is a magical device that can raise the level of the applied ac input without the assistance of an external energy source. that is. In most instances the base current IB is the first quantity to be determined. The dc level of operation of a transistor is controlled by a number of factors.1) (4. However. the superposition theorem is applicable and the investigation of the dc conditions can be totally separated from the ac response. Once the desired dc current and voltage levels have been defined. Although a number of networks are analyzed in this chapter. and vice versa.3) can be applied to find the remaining quantities of interest. a network must be constructed that will establish the desired operating point—a number of these networks are analyzed in this chapter.1) through (4. the path toward the solution of the networks to follow will begin to become quite apparent. including the range of possible operating points on the device characteristics. there is an underlying similarity between the analysis of each configuration due to the recurring use of the following important basic relationships for a transistor: VBE IE ( IC 0. how sensitive the system is to temperature variations—another topic to be investigated in a later section of this chapter.7 V 1)IB IB IC (4. Fortunately. the improved output ac power level is the result of a transfer of energy from the applied dc supplies.2 we specify the range for the BJT amplifier. The equations for IB are so similar for a num- 143 . the relationships of Eqs. once the analysis of the first few networks is clearly understood. Once IB is known.CHAPTER DC Biasing—BJTs 4. (4.2) (4. The similarities in analysis will be immediately obvious as we progress through the chapter.1 INTRODUCTION The analysis or design of a transistor amplifier requires a knowledge of both the dc and ac response of the system. The analysis or design of any electronic amplifier therefore has two components: the dc portion and the ac portion.

The maximum power constraint is defined by the curve PCmax in the same figure. defined by VCE VCEsat. By definition. defined by IB . The biasing circuit can be designed to set the device operation at any of these points or others within the active region. we can consider some differences among the IC (mA) 80 µA 70 µA IC max 25 60 µA 20 PC max 15 30 µA Saturation 10 D B 20 µA 50 µA 40 µA 5 10 µA C I B = 0 µA A 0 VCE sat 5 10 Cutoff 15 20 VCE max VCE (V) Figure 4. Confining ourselves to the active region. 144 Chapter 4 DC Biasing—BJTs . Still. The chosen Q-point often depends on the intended use of the circuit. Figure 4. Since the operating point is a fixed point on the characteristics. 4.ber of configurations that one equation can be derived from another simply by dropping or adding a term or two. one can select many different operating areas or points.2 OPERATING POINT The term biasing appearing in the title of this chapter is an all-inclusive term for the application of dc voltages to establish a fixed level of current and voltage. At the lower end of the scales are the cutoff region. The primary function of this chapter is to develop a level of familiarity with the BJT transistor that would permit a dc analysis of any system that might employ the BJT amplifier. The maximum ratings are indicated on the characteristics of Fig.1 by a horizontal line for the maximum collector current ICmax and a vertical line at the maximum collector-to-emitter voltage VCEmax.1 Various operating points within the limits of operation of a transistor.1 shows a general output device characteristic with four operating points indicated. it is also called the quiescent point (abbreviated Q-point). still. 4. but the result of such operation would be either a considerable shortening of the lifetime of the device or destruction of the device. and the saturation region. quiescent means quiet. 0 The BJT device could be biased to operate outside these maximum limits. For transistor amplifiers the resulting dc current and voltage establish an operating point on the characteristics that define the region that will be employed for amplification of the applied signal. inactive.

resulting in a Q-point at A—namely. Temperature causes the device parameters such as the transistor current gain ( ac) and the transistor leakage current (ICEO) to change.6 to 0. The base–emitter junction must be forward-biased (p-region voltage more positive). Having selected and biased the BJT at a desired operating point. This is usually the desired condition for small-signal amplifiers (Chapter 8) but not the case necessarily for power amplifiers. the device would initially be completely off. A highly stable circuit is desirable. point A would not be suitable. For the BJT to be biased in its linear or active operating region the following must be true: 1. we will be concentrating primarily on biasing the transistor for small-signal amplification operation. and the stability of a few basic bias circuits will be compared. 4. If the input signal is properly chosen. and linear regions of the BJT characteristic are provided as follows: 1. If no bias were used. 4. but the peakto-peak value would be limited by the proximity of VCE 0V/IC 0 mA. the effect of temperature must also be taken into account. This maintenance of the operating point can be specified by a stability factor. saturation.] Operation in the cutoff. as shown in Fig. zero current through the device (and zero voltage across it). Point D sets the device operating point near the maximum voltage and power level.various points shown in Fig. The base–collector junction must be reverse-biased (n-region more positive). the bias circuit.1 to present some basic ideas about the operating point and. Linear-region operation: Base–emitter junction forward biased Base–collector junction reverse biased 4. Point B therefore seems the best operating point in terms of linear gain and largest possible voltage and current swing. the voltage and current of the device will vary but not enough to drive the device into cutoff or saturation.1. [Note that for forward bias the voltage across the p-n junction is p-positive. the device will vary in current and voltage from operating point. while for reverse bias it is opposite (reverse) with n-positive. 2.2 Operating Point 145 . Point C would allow some positive and negative variation of the output signal. In general. One other very important biasing factor must be considered. This emphasis on the initial letter should provide a means of helping memorize the necessary voltage polarity. For point B. Higher temperatures result in increased leakage currents in the device. it is preferable to operate where the gain of the device is fairly constant (or linear) to ensure that the amplification over the entire swing of input signal is the same. Operating at point C also raises some concern about the nonlinearities introduced by the fact that the spacing between IB curves is rapidly changing in this region. with the reverse-bias voltage being any value within the maximum limits of the device. Since it is necessary to bias a device so that it can respond to the entire range of an input signal. S. if a signal is applied to the circuit. with a resulting forward-bias voltage of about 0. thereby changing the operating condition set by the biasing network. The output voltage swing in the positive direction is thus limited if the maximum voltage is not to be exceeded. which indicates the degree of change in operating point due to a temperature variation. In this discussion. thereby. Point B is a region of more linear spacing and therefore more linear operation. allowing the device to react to (and possibly amplify) both the positive and negative excursions of the input signal.7 V. The result is that the network design must also provide a degree of temperature stability so that temperature changes result in minimum changes in the operating point. which will be considered in Chapter 16.

4. and the voltages are defined by the standard double-subscript notation. The separation is certainly valid.2.4. the dc supply VCC can be separated into two supplies (for analysis purposes only) as shown in Fig. The current directions of Fig.2 provides a relatively straightforward and simple introduction to transistor dc bias analysis. Chapter 4 DC Biasing—BJTs 146 .3 FIXED-BIAS CIRCUIT The fixed-bias circuit of Fig.3 dc equivalent of Fig.2 are the actual current directions. VCC RC RB C ac input signal IB C1 B IC ac output signal + VCE C2 + VBE – – E Figure 4. 4. 4. Figure 4. Cutoff-region operation: Base–emitter junction reverse biased 3. Solving the equation for the current IB will result in the following: IB VCC RB VBE (4.3 that VCC is connected directly to RB and RC just as in Fig. 4.4 Base–emitter loop.4) Figure 4. the equations and calculations apply equally well to a pnp transistor configuration merely by changing all current directions and voltage polarities. we obtain VCC IBRB VBE 0 Note the polarity of the voltage drop across RB as established by the indicated direction of IB. It also reduces the linkage between the two to the base current IB. Equation (4. as we note in Fig. The voltage across RB is the applied voltage VCC at one end less the drop across the base-to-emitter junction (VBE).4) is certainly not a difficult one to remember if one simply keeps in mind that the base current is the current through RB and by Ohm’s law that current is the voltage across RB divided by the resistance RB. For the dc analysis the network can be isolated from the indicated ac levels by replacing the capacitors with an opencircuit equivalent. Even though the network employs an npn transistor. Forward Bias of Base–Emitter Consider first the base–emitter circuit loop of Fig.3 to permit a separation of input and output circuits.2.2. In addition. Writing Kirchhoff’s voltage equation in the clockwise direction for the loop. Saturation-region operation: Base–emitter junction forward biased Base–collector junction forward biased 4. 4. 4.2 Fixed-bias circuit. 4.

The magnitude of the collector current is related directly to IB through IC IB (4. but in the networks to follow the two can be quite different. However. (d) VBC.6. (b) VCEQ.5 will result in the following: VCE and VCE ICRC VCC VCC ICRC 0 (4. Collector–Emitter Loop The collector–emitter section of the network appears in Fig. VC (4. 4. we have VCE In addition.6 Measuring VCE and VC.3 Fixed-Bias Circuit EXAMPLE 4. Clearly understanding the difference between the two measurements can prove to be quite important in the troubleshooting of transistor networks. 4. In this case the two readings are identical. the selection of a base resistor. (c) VB and VC. 4. the magnitude of IC is not a function of the resistance RC. since the supply voltage VCC and the base–emitter voltage VBE are constants.and double-subscript notation recall that VCE VC VE (4. But in this case. Determine the following for the fixed-bias configuration of Fig. sets the level of base current for the operating point. which is an important parameter. Applying Kirchhoff’s voltage law in the clockwise direction around the indicated closed loop of Fig. then VBE VB (4. RB.7) where VCE is the voltage from collector to emitter and VC and VE are the voltages from collector and emitter to ground respectively. the level of RC will determine the magnitude of VCE. since VBE and VE 0 V.8) VB VE (4. It is interesting to note that since the base current is controlled by the level of RB and IC is related to IB by a constant .10) Figure 4.6) which states in words that the voltage across the collector–emitter region of a transistor in the fixed-bias configuration is the supply voltage less the drop across RC. 4.In addition. 4. (a) IBQ and ICQ.5 Collector–emitter loop.5) Figure 4.9) Keep in mind that voltage levels such as VCE are determined by placing the red (positive) lead of the voltmeter at the collector terminal with the black (negative) lead at the emitter terminal as shown in Fig. As a brief review of single. as we shall see.1 147 . since VE 0 V. VC is the voltage from collector to ground and is measured as shown in the same figure. Change RC to any level and it will not affect the level of IB or IC as long as we remain in the active region of the device.7.5 with the indicated direction of current IC and the resulting polarity across RC.

Note that it is in a region where the characteristic curves join and the collector-to-emitter voltage is at or below VCEsat. 4.08 A) 2. A saturated sponge is one that cannot hold another drop of liquid.7 V 47. Of course.8a by those appearing in Fig. the current is a maximum value for the particular design.13 V 0. Transistor Saturation The term saturation is applied to any system where levels have reached their maximum values. 4. Saturation conditions are normally avoided because the base–collector junction is no longer reverse-biased and the output amplified signal will be distorted.83 V with the negative sign revealing that the junction is reversed-biased. a quick.6): VCEQ VCC 12 V 0.7 V 6.1.83 V RB VBE A (c) VB VBE 0. Change the design and the corresponding saturation level may rise or drop.8b. (4.08 240 k IBQ (50)(47. If we approximate the curves of Fig. For a transistor operating in the saturation region. In addition. Solution (a) Eq. (4. Applying Ohm’s law the resistance between collector and emitter terminals can be determined as follows: 0V VCE 0 RCE ICsat IC 148 Chapter 4 DC Biasing—BJTs .35 mA)(2. 4.2 k ) 6. the highest saturation level is defined by the maximum collector current as provided by the specification sheet.5): ICQ (b) Eq.8a. direct method for determining the saturation level becomes apparent. An operating point in the saturation region is depicted in Fig.4): IBQ Eq.35 mA VCC ICRC 12 V (2. In Fig.83 V (d) Using double-subscript notation yields VBC VB VC 6.7 V VC VCE 6. (4. the collector current is relatively high on the characteristics. the current is relatively high and the voltage VCE is assumed to be zero volts.8b.Figure 4. 4. as it should be for linear amplification.7 dc fixed-bias circuit for Example 4.

4. Figure 4.2 k 5.10.3 Fixed-Bias Circuit 149 . Once ICsat is known.2 Solution ICsat VCC RC 12 V 2.10 Determining ICsat for the fixed-bias configuration.8 Saturation regions: (a) actual. causing the voltage across RC to be the applied voltage VCC.9 Determining ICsat. the short circuit has been applied. For the fixed-bias configuration of Fig. The resulting saturation current for the fixed-bias configuration is ICsat VCC RC (4. For the future. In short. set VCE 0 V.11) Figure 4. EXAMPLE 4. Determine the saturation level for the network of Fig. simply insert a short-circuit equivalent between collector and emitter of the transistor and calculate the resulting collector current.45 mA 4.7. we have some idea of the maximum possible collector current for the chosen design and the level to stay below if we expect linear amplification. Applying the results to the network schematic would result in the configuration of Fig. 4. 4. therefore.IC I C sat – Q-point IC I C sat – Q-point 0 VCE sat (a) VCE 0 (b) VCE Figure 4. (b) approximate. if there were an immediate need to know the approximate maximum collector current (saturation level) for a particular design.9.

11a establishes an output equation that relates the variables IC and VCE in the following manner: VCE VCC ICRC (4. we are specifying the horizontal axis as the line on which one point is located. In other words. The most direct method of plotting Eq.1 resulted in ICQ 2. 4. (b) the device characteristics. The network of Fig. 4.13) defining one point for the straight line as shown in Fig. we have a network equation and a set of characteristics that employ the same variables.11 Load-line analysis: (a) the network. this is similar to finding the solution of two simultaneous equations: one established by the network and the other by the device characteristics.11b. IC (mA) 8 7 6 5 V CC IC RC 4 3 2 VCE IB 1 10 µA I B = 0 µA 5 ICEO (a) (b) 10 15 VCE (V) 30 µA 50 µA 40 µA + RB 20 µA – + – 0 Figure 4. By substituting IC 0 mA into Eq. In essence. therefore. 4.12). (4.11b. If we choose IC to be 0 mA. 4. which is far from the saturation level and about one-half the maximum value for the design.The design of Example 4.12) on the output characteristics is to use the fact that a straight line is defined by two points.12. we find that VCE and VCE VCC VCC (0)RC IC 0 mA (4. 150 Chapter 4 DC Biasing—BJTs . The device characteristics of IC versus VCE are provided in Fig. We will now investigate how the network parameters define the possible range of Q-points and how the actual Q-point is determined. (4.12) on the characteristics.35 mA. Load-Line Analysis The analysis thus far has been performed using a level of corresponding with the resulting Q-point.12) The output characteristics of the transistor also relate the same two variables IC and VCE as shown in Fig. We must now superimpose the straight line defined by Eq. (4. The common solution of the two occurs where the constraints established by each are satisfied simultaneously.

If RC is fixed and VCC varied. the load line shifts as shown in Fig. If VCC is held fixed and RC changed.IC VCC RC Q-point VCE = 0 V IB Q Load line 0 IC = 0 mA VCC VCE Figure 4. the straight line established by Eq.12. 4.12) can be drawn. we find that IC is determined by the following equation: 0 and IC VCC VCC RC ICRC (4. If IB is held fixed.14 Effect of increasing levels of RC on the load line and Q-point.3 Fixed-Bias Circuit 151 . the actual Q-point can be established as shown in Fig.13.13 Movement of Q-point with increasing levels of IB. By joining the two points defined by Eqs. 4. Figure 4. Figure 4. (4.12. 4. 4.14). 4. which establishes the vertical axis as the line on which the second point will be defined. the Q-point will move as shown in the same figure.12 Fixed-bias load line. The resulting line on the graph of Fig. If we now choose VCE to be 0 V. (4.13) and (4.14) VCE 0V as appearing on Fig. the load line will shift as shown in Fig.15. If the level of IB is changed by varying the value of RB the Q-point moves up or down the load line as shown in Fig. 4.12 is called the load line since it is defined by the load resistor RC. By solving for the resulting level of IB.14. 4.

RC.16.16 Example 4.16 and the defined Q-point.3 Solution From Fig.15 Effect of lower values of VCC on the load line and Q-point. determine the required values of VCC. 4. 4. and RB for a fixed-bias configuration. EXAMPLE 4. I C (mA) 60 µA 12 10 8 30 µA 6 4 10 µA 2 I B = 0 µA 5 10 15 20 VCE Q-point 20 µA 50 µA 40 µA 0 Figure 4. VCE IC and RC IB and RB VCC 20 V at IC 0V 2k 0 mA VCC at VCE RC VCC IC VCC RB VCC IB VBE 20 V 10 m A VBE 20 V 0.7 V 25 A 772 k 152 Chapter 4 DC Biasing—BJTs .3 Given the load line of Fig.Figure 4.

18 Base–emitter loop.18. 4. fixed-bias configuration is the term ( There is an interesting result that can be derived from Eq. The analysis will be performed by first examining the base–emitter loop and then using the results to investigate the collector–emitter loop. Base–Emitter Loop The base–emitter loop of the network of Fig.17 contains an emitter resistor to improve the stability level over that of the fixed-bias configuration. 153 . 4.15) Substituting for IE in Eq.17) if the equation is used to sketch a series network that would result in the same equation.17 BJT bias circuit with emitter resistor.17 can be redrawn as shown in Fig. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in the following equation: VCC Recall from Chapter 3 that IE VCC IB(RB IBRB ( ( 1)IB ( I)IBRE VCC VBE 0 (4.16) IBRB VBE IERE 0 (4.4 Emitter-Stabilized Bias Circuit Figure 4. (4. Such is 4.15) will result in VBE 1)RE) Grouping terms will then provide the following: 0 Multiplying through by ( 1) we have with IB(RB ( IB(RB ( 1)RE) VCC VBE 0 1)RE) VCC VBE and solving for IB gives IB VCC RB ( VBE 1)RE (4. The improved stability will be demonstrated through a numerical example later in the section.4 EMITTER-STABILIZED BIAS CIRCUIT The dc bias network of Fig. Figure 4. 4.4. (4.17) Note that the only difference between this equation for IB and that obtained for the 1)RE.

23) (4. In other resistor RE is reflected back to the input base circuit by a factor ( words. (4. RB plus RE reflected by ( Collector–Emitter Loop The collector–emitter loop is redrawn in Fig. In fact. Since is typically 50 or more. the emitter resistor. 4. Using Ohm’s law.20 Reflected impedance level of RE. The result is Eq. (4.21 Collector–emitter loop. Figure 4. 4.19) The single-subscript voltage VE is the voltage from emitter to ground and is determined by VE Figure 4. we know that the current through a system is the voltage divided by the resistance of the circuit. IERE (4.18) Equation (4. it provides a fairly easy way to remember Eq.17). Writing Kirchhoff’s voltage law for the indicated loop in the clockwise direction will result in IERE Substituting IE VCE and VCE VCE VCC VCC ICRC IC (RC IC (RC VCC RE) RE) 0 IC and grouping terms gives 0 (4. In general.Figure 4. Ri ( 1)RE (4.20) while the voltage from collector to ground can be determined from VCE and or VC VC VC VCE VCC VE VE ICRC (4. Note that aside from the base-to-emitter voltage VBE. the 1). the emitter resistor appears to be a great deal larger in the base circuit. the case for the network of Fig.17). The resistance levels are 1).17). “appears as” ( 1)RE in the base–emitter loop.19 Network derived from Eq.18) is one that will prove useful in the analysis to follow. for the configuration of Fig. For the base–emitter circuit the net voltage is VCC VBE. (4. 4.22) The voltage at the base with respect to ground can be determined from VB or 154 VB DC Biasing—BJTs VCC VBE IBRB VE (4.21.24) Chapter 4 .20.21) (4. Solving for the current IB will result in the same equation obtained above.19. therefore. which is part of the collector–emitter loop.

01 mA)(2 k ) 20 V 4.For the emitter bias network of Fig. EXAMPLE 4. (c) VCE.22.7 V 2. (g) VBC.4 Emitter-Stabilized Bias Circuit 155 . (e) VE.98 V 13.01 mA)(2 k 1k ) 13.01 mA Eq.97 V 2.98 V VE VC VCE 15.27 V (reverse-biased as required) 20 V 6. (4.19): VCE VCC IC (RC RE) 20 V (2. (f) VB.17): IB VCC RB ( 19.02 V 15.97 V VC VCC ICRC 20 V (2.1 A) 2.1 A 20 V 0. 4. Solution (a) Eq.71 V 15.71 V VBC VB VC 2. (d) VC.98 V 13.01 V VE IERE ICRE (2. (b) IC. (4.3 V 481 k VBE 1)RE 40.01 V VB VBE VE 0.03 V 4.4.01 V 2.4 Figure 4.7 V 430 k (51)(1 k ) (b) IC (c) (d) (e) or (f) (g) IB (50)(40.01 mA)(1 k ) 2. determine: (a) IB.22 Emitter-stabilized bias circuit for Example 4.

1 36.5.23 and calculate the resulting collector current.83 1. change.71 VCE (V) 6.22 is therefore more stable than that of Fig.64 The BJT collector current is seen to change by 100% due to the 100% change in the value of . Solution Using the results calculated in Example 4.Improved Bias Stability The addition of the emitter resistor to the dc bias of the BJT provides improved stability. we have the following: IB ( A) 50 100 40. IB is the same and VCE decreased by 76%. the dc bias currents and voltages remain closer to where they were set by the circuit when outside conditions.97 9. 4. and transistor beta. Chapter 4 DC Biasing—BJTs 156 . some comparison of the improvement can be obtained as demonstrated by Example 4.35 4. Comand Fig. helping maintain the value of IC —or at least reducing the overall change in IC due to the change in .23 Determining ICsat for the emitter-stabilized bias circuit. For Fig.7 50 and for a new value of 100. Using the results calculated in Example 4. VCC RC RE (4.1 and then repeating for a value of yields the following: 100 IB ( A) 50 100 47.08 IC (mA) 2. that is. The network of Fig. such as temperature.7 for the same change in . Notice that IB decreased. 4.01 3.23: ICsat Figure 4.22 for the given value of pare the changes in IC and VCE for the same increase in . Saturation Level The collector saturation level or maximum collector current for an emitter-bias design can be determined using the same approach applied to the fixed-bias configuration: Apply a short circuit between the collector–emitter terminals as shown in Fig.63 VCE (V) 13.4 and then repeating for a value of 100. EXAMPLE 4.25) The addition of the emitter resistor reduces the collector saturation level below that obtained with a fixed-bias configuration using the same collector resistor. 4.3 IC (mA) 2. 4. The change in VCE has dropped to about 35%. While a mathematical analysis is provided in Section 4. 4.12.11 Now the BJT collector current increases by about 81% due to the 100% increase in . 4.08 47.5 Prepare a table and compare the bias voltage and currents of the circuits of Figs.

17) defines the level of IB on the characteristics of Fig. However.24 (denoted IBQ). 4. especially for silicon transistors. and the actual value of beta is usually not well defined.Determine the saturation current for the network of Example 4.5 VOLTAGE-DIVIDER BIAS In the previous bias configurations the bias current ICQ and voltage VCEQ were a function of the current gain ( ) of the transistor. it would be desirable to develop a bias circuit that is less dependent. 4.27) as obtained for the fixed-bias configuration.67 mA 20 V 3k which is about twice the level of ICQ for Example 4. 4. EXAMPLE 4.6 Solution ICsat VCC RC RE 20 V 2k 1k 6. Different levels of IBQ will.24.4. The level of IB as determined by Eq. The collector–emitter loop equation that defines the load line is the following: VCE Choosing IC 0 mA gives VCE VCCIC 0 mA VCC IC (RC RE) (4. or in 4.24 Load line for the emitter-bias configuration. Choosing VCE IC VCC RC RE VCE 0 V as shown in Fig.4. Figure 4. (4. of course. move the Q-point up or down the load line. Load-Line Analysis The load-line analysis of the emitter-bias network is only slightly different from that encountered for the fixed-bias configuration.26) 0 V gives (4. since is temperature sensitive.5 Voltage-Divider Bias 157 .

27 for the dc analysis. 158 Chapter 4 DC Biasing—BJTs . Figure 4. All in all. 4.26 Defining the Q-point for the voltage-divider bias configuration. 4. The approximate approach permits a more direct analysis with a savings in time and energy. The Thévenin equivalent network for the network to the left of the base terminal can then be found in the following manner: B R1 VCC R2 RE Thévenin Figure 4. The reason for the choice of names for this configuration will become obvious in the analysis to follow.25. It is also particularly helpful in the design mode to be described in a later section.26. 4. fact. 4. 4. The voltage-divider bias configuration of Fig. The first to be demonstrated is the exact method that can be applied to any voltage-divider configuration. but the operating point on the characteristics defined by ICQ and VCEQ can remain fixed if the proper circuit parameters are employed.Figure 4. there are two methods that can be applied to analyze the voltagedivider configuration. independent of the transistor beta. Exact Analysis The input side of the network of Fig. If the circuit parameters are properly chosen. As noted above.25 can be redrawn as shown in Fig. the approximate approach can be applied to the majority of situations and therefore should be examined with the same interest as the exact method. The second is referred to as the approximate method and can be applied only if specific conditions are satisfied. If analyzed on an exact basis the sensitivity to changes in beta is quite small.27 Redrawing the input side of the network of Fig. The level of IBQ will change with the change in beta.25 Voltage-divider bias configuration.25 is such a network. the resulting levels of ICQ and VCEQ can be almost totally independent of beta. Recall from previous discussions that a Q-point is defined by a fixed level of ICQ and VCEQ as shown in Fig.

VCE VCC IC (RC RE) (4. the remaining quantities of the network can be found in the same manner as developed for the emitter-bias configuration.30.19).29 determined as follows: Applying the voltage-divider rule: ETh VR2 R2VCC R1 R2 (4. R1 + R2 2 + – The Thévenin network is then redrawn as shown in Fig. 4.30) initially appears different from those developed earlier. EXAMPLE 4.7. and VB are also the same as obtained for the emitter-bias configuration. 4.31 Beta-stabilized circuit for Example 4. That is. 4. note that the numerator is again a difference of two voltage levels and the denominator is 1)—certainly very simthe base resistance plus the emitter resistor reflected by ( ilar to Eq. and IBQ can be determined by first applying Kirchhoff’s voltage law in the clockwise direction for the loop indicated: ETh Substituting IE ( IBRTh VBE IERE 0 VCC VR E Th – 1)IB and solving for IB yields IB ETh VBE RTh ( 1)RE (4.RTh: The voltage source is replaced by a short-circuit equivalent as shown in Fig. The remaining equations for VE. Although Eq. Determine the dc bias voltage VCE and the current IC for the voltage-divider configuration of Fig.28) R1 R2 R Th ETh: The voltage source VCC is returned to the network and the open-circuit Thévenin voltage of Fig.31. Once IB is known.5 Voltage-Divider Bias 159 . Figure 4. (4.28 Determining RTh.7 Figure 4.28. VC. RTh R1 R2 (4.17). 4.30) Figure 4.29) Figure 4.31) RTh IB ETh B + VBE – RE E which is exactly the same as Eq.30 Inserting the Thévenin equivalent circuit.29 Determining ETh. 4. (4. (4.

55 k 6. (4.7 V (141)(1.9 k ) 39 k 3.55 k Eq.78 V RE) 1.05 A) 0. (4. The resistance Ri is the equivalent resistance between base and ground for the transistor with an emitter resistor RE.9 k ETh VBE RTh ( 1)RE 2V 3.32. If Ri is much larger than the resistance R2.3 V 3.85 mA)(10 k Approximate Analysis The input section of the voltage-divider configuration can be represented by the network of Fig.22 V IC (RC 9.5 k ) 2V 3.5 k ) 1.28): RTh R1 R2 (39 k )(3.30): IB 0.9 k )(22 V) 39 k 3.5 k (0.31): VCE VCC 22 V 22 V 12. (4. (4. then I1 I2 and R1 and R2 can be considered series ele- Figure 4.85 mA Eq. Recall from Section 4.55 k 211.29): ETh R2VCC R1 R2 (3. (4. 4.05 A IC IB (140)(6. the current IB will be much ( smaller than I2 (current always seeks the path of least resistance) and I2 will be approximately equal to I1.32 Partial-bias circuit for calculating the approximate base voltage VB.18)] that the reflected resistance between base and emitter is defined by Ri 1)RE.4 [Eq. If we accept the approximation that IB is essentially zero amperes compared to I1 or I2.Solution Eq. 160 Chapter 4 DC Biasing—BJTs .9 k Eq.

That is. and compare solutions for ICQ and VCEQ. (4.37) that does not appear and IB was not calculated.35) (4. Once VB is determined.5 k ) 210 k Eq.33) through Eq. which is actually the base voltage.9 k 2V 4.31 using the approximate technique. VCEQ VCC IC (RC RE) (4. Repeat the analysis of Fig.5 Voltage-Divider Bias 161 . can be determined using the voltage-divider rule (hence the name for the configuration).33) In other words. The Q-point (as determined by ICQ and VCEQ) is therefore independent of the value of . if times the value of RE is at least 10 times the value of R2. the level of VE can be calculated from VE VB VBE (4.34) and the emitter current can be determined from IE and ICQ VE RE IE (4. EXAMPLE 4.32) 1)RE RE the condition that will define whether the approxiSince Ri ( mate approach can be applied will be the following: RE 10R2 (4.37) VCC ICRC IERE Note in the sequence of calculations from Eq.9 k )(22 V) 39 k 3.8 Solution Testing: RE (140)(1.36) The collector-to-emitter voltage is determined by VCE but since IE IC. 4. The voltage across R2.32): 10R2 10(3. the approximate approach can be applied with a high degree of accuracy. (4.ments. VB R2VCC R1 R2 (4.9 k ) 39 k VB (satisfied) R2VCC R1 R2 (3. (4.

(4.10 will compare solutions at a level well below the condition established by Eq.867 mA)(10 kV EXAMPLE 4.7 if tions for ICQ and VCEQ. and compare solu- Solution This example is not a comparison of exact versus approximate methods but a testing of how much the Q-point will move if the level of is cut in half.55 k (71)(1. the closer the approximate to the exact solution.7. VCEQ VCC 22 V 22 V 12.5 k ) (0. the primary difference between the exact and approximate techniques is the effect of RTh in the exact analysis that separates ETh and VB. therefore.34): VE VB 2V 1. ETh RTh ETh 2V VBE ( 1)RE 3. (4.867 mA VBE 0.97 V 1.7.5 k ) 11.7 V compared to 0.85 mA with the exact analysis.03 V versus 12.83 mA)(10 k .22 V obtained in Example 4. Essentially.55 k .3 V 1. The larger the level of Ri compared to R2. Eq. and considering the actual variation in parameter values one can certainly be considered as accurate as the other. Finally.Note that the level of VB is the same as ETh determined in Example 4. Example 4. The results for ICQ and VCEQ are certainly close.3 V ICQ IE VE RE IC(RC 9.81 A ICQ IB (70)(11.5 k ) (0. is reduced to 70.9 Repeat the exact analysis of Example 4.83 mA VCEQ VCC 22 V 12.46 V 162 Chapter 4 DC Biasing—BJTs IC(RC RE) 1. RE) 1. RTh and ETh are the same: RTh IB 3.81 A) 0.5 k 0.5 k 2 V 0.55 k 1.33).3 V 106.7 V 3.

2 k ) RTh ETh IB R1 R2 R2VCC R1 R2 ETh RTh IB VCC 18 V 4.83 VCEQ (V) 12. (4.6 k 4. the conditions of Eq.98 mA (1.33) will not be satisfied but the results will reveal the difference in solution if the criterion of Eq. 4.33): RE 60 k 10R2 10(22 k ) 220 k 22 k (not satisfied) 17. Solution Exact Analysis Eq.10.11 V 78.2 k ) 39.7 V 17.85 0.55 k (50)(1.22 12.5 Voltage-Divider Bias 163 . In this case. Determine the levels of ICQ and VCEQ for the voltage-divider configuration of Fig.35 k 3. Even though is drastically cut in half.33 using the exact and approximate techniques and compare solutions.46 The results clearly show the relative insensitivity of the circuit to the change in .33 Voltage-divider configuration for Example 4. (4.81 V 0.35 k (51)(1.10 Figure 4.6 A) IC(RC RE) 1.6 A ICQ VCEQ (50)(39. (4. EXAMPLE 4.54 V 82 k 22 k (18 V) 82 k 22 k VBE ( 1)RE 3.Tabulating the results.33) is ignored. we have: ICQ (mA) 140 70 0. from 140 to 70.81 V 3.2 k ) 1. the levels of ICQ and VCEQ are essentially the same.98 mA)(5.

11 V 1.88 The results reveal the difference between exact and approximate solutions.59 mA)(5.40) The level of IB is of course determined by a different equation for the voltage-divider bias and the emitter-bias configurations. but even though RE is only about three times larger than R2.88 V 3.98 2.38) Load-Line Analysis The similarities with the output circuit of the emitter-biased configuration result in the same intersections for the load line of the voltage-divider configuration. our analysis will be dictated by Eq. For the future. The results are notably different in magnitude. That is. with IC and VCC RC RE VCE 0 V VCE VCC IC 0 mA (4.33) to ensure a close similarity between exact and approximate solutions.39) (4.7 V 2.59 mA 3. 164 Chapter 4 DC Biasing—BJTs .24. while VCEQ is about 10% less. however. Transistor Saturation The output collector–emitter circuit for the voltage-divider configuration has the same appearance as the emitter-biased circuit analyzed in Section 4. 4. the results are still relatively close to each other. ICsat ICmax VCC RC RE (4.81 V 3. we have: ICQ (mA) Exact Approximate 1.4.Approximate Analysis VB VE ICQ VCEQ ETh VB IE VCC 18 V 3.2 k ) 0.11 V IC (RC (2. ICQ is about 30% greater with the approximate solution.54 3.6 k Tabulating the results.59 VCEQ (V) 4.81 V VBE VE RE 3. The load line will therefore have the same appearance as that of Fig. The resulting equation for the saturation current (when VCE is set to zero volts on the schematic) is therefore the same as obtained for the emitter-biased configuration. (4.2 k RE) 1.

6 DC Bias with Voltage Feedback 165 .34. Base–Emitter Loop Figure 4. 4. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in VCC I CRC IBRB VCC RC IC ' vo RB IB vi C1 RE IC C2 VBE IERE 0 + – RB VCC IB +– RC IC ' IC + VCE – IE + VBE – + – IE RE Figure 4. Figure 4.4. The numerator is again the difference of available voltage levels. much like the reflection of RE. the sensitivity to changes in beta or temperature variations is normally less than encountered for the fixed-bias or emitter-biased configurations. therefore. Although the Q-point is not totally independent of beta (even under approximate conditions). The analysis will again be performed by first analyzing the base–emitter loop with the results applied to the collector–emitter loop. 4. while the denominator is the base resistance plus the collector and emitter resistors reflected by beta. In general. we have VCC and solving for IB yields IB VCC RB VBE (RC RE) (4. the feedback path results in a reflection of the resistance RC back to the input circuit.35 shows the base–emitter loop for the voltage feedback configuration. the equation for IB has had the following format: IB V RB R 4.6 DC BIAS WITH VOLTAGE FEEDBACK An improved level of stability can also be obtained by introducing a feedback path from collector to base as shown in Fig.34 dc bias circuit with voltage feedback. Substituting I C IC will result in VCC Gathering terms.34.35 Base–emitter loop for the network of Fig.41) VBE IB(RC RE) IBRB 0 IBRC IBRB VBE IBRE 0 The result is quite interesting in that the format is very similar to equations for IB obtained for earlier configurations. However. In general. It is important to note that the current through RC is not IC but I C (where I C IC IB). the level of IC and IC far exceeds the usual level of IB and the apIB and IE IC proximation I C IC is normally employed.

R is zero ohms for the fixed-bias configuration and is therefore quite sensitive to variations in beta.11 Solution Eq. 4. 4. the sensitivity to variations in beta is less.37 Network for Example 4. Determine the quiescent levels of ICQ and VCEQ for the network of Fig.7 V (90)(4.36 Collector–emitter loop for the network of Fig. IB.11.3 V 781 k 11. and R RC RE for the collector-feedback arrangement.34. Since IC ICQ V RB R In general. R RE for the emitter-bias 1) ). we have 0 (4. then tions in beta.34 is provided in Fig. Applying Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in IERE Since I C IC and IE IC (RC and VCE VCE RE) VCC I CRC VCE IC (RC VCC VCC RE) 0 + – + RE VCE VCC IE IC.36.37. – IC Collector–Emitter Loop The collector–emitter loop for the network of Fig.2 kΩ (1. Of course. Since R is typically larger for the voltagefeedback configuration than for the emitter-bias configuration.3 V 531 k 9. setup (with ( The voltage V is the difference between two voltage levels. the less the sensitivity of ICQ to variaRB and RB R R . 3.42) – Figure 4.2 k ) 4. if R ICQ V RB R V R V R I' C + RC and ICQ is independent of the value of beta.31 V RE) 1.07 mA IC (RC 6. 4.41): 10 V IB VCC RB 250 k 250 k VBE (RC RE) 10 V 0. which is exactly as obtained for the emitter-bias and voltage-divider bias configurations.with the absence of R for the fixed-bias configuration. (4.69 V DC Biasing—BJTs 166 Chapter 4 .91 A ICQ VCEQ IB VCC 10 V 10 V (90)(11.07 mA)(4.7 k Figure 4.2 k ) 1.7 kΩ 250 kΩ 10 µF vi 10 µF vo 9. the larger R is compared to RB.7 k 1. EXAMPLE 4. Obviously. 4.91 A) β = 90 1.

2 k ) (1.11).89 A) 1.11 using a beta of 135 (50% more than Example 4.Repeat Example 4. that once the second term is relatively large compared to the first. Solving for IB gives IB VCC RB VBE (RC RE) 1.9%.3 V 1046. a 50% increase in would have resulted in a 50% increase in ICQ and a dramatic change in the location of the Q-point. however. In this example the level of beta is increased by 50%. the sensitivity to changes in beta is significantly less.3 V 796.11 that the second term in the denominator of the equation is larger than the first.13.12 Solution It is important to note in the solution for IB in Example 4.5 k 250 k 8. If the network were a fixed-bias design.6 DC Bias with Voltage Feedback 167 .38. which will increase the magnitude of this second term even more compared to the first.08 V RE) 1. EXAMPLE 4. 4. the less the sensitivity to changes in beta.92 V Even though the level of increased 50%.7 k EXAMPLE 4.13 91 kΩ R1 10 µF vi 110 kΩ R2 10 µF 3.2 k ) 9.38 Network for Example 4. 4.7 k 9.89 A and ICQ IB (135)(8. Recall in a recent discussion that the larger this second term is compared to the first.2 mA and VCEQ VCC 10 V 10 V 2. 18 V IC (RC 7.2 mA)(4.5 k 250 k 10 V 0. Determine the dc level of IB and VC for the network of Fig. It is more important to note in these examples.7 V (135)(4.3 kΩ 10 µF vo β = 75 510 Ω 50 µF Figure 4.1% while the level of VCEQ decreased about 20. the level of ICQ only increased 12.

43) Load-Line Analysis Continuing with the approximation I C IC will result in the same load line defined for the voltage-divider and emitter-biased configurations. The level of IBQ will be defined by the chosen bias configuration. Once the base current is known.66 mA VC VCC 18 V 18 V 9.5 A) 2.3 k 17.78 V VCC ICRC VBE (RC RE) 18 V 0.75 k A 17.3 k ) Saturation Conditions Using the approximation I C IC .66 mA)(3.75 k 0. For each configuration discussed thus far. the primary purpose here is to emphasize those characteristics of the device that permit a dc analysis of the configuration and to establish a general procedure toward the desired solution. the first step has been the derivation of an expression for the base current.51 k ) (2. the capacitor assumes the open-circuit equivalence and RB R1 R2. the collector current and voltage levels of the output circuit can be determined quite di168 Chapter 4 DC Biasing—BJTs . there are variations in design that would require many more pages than is possible in a book of this type. In fact. For the dc mode. ICsat ICmax VCC RC RE (4.7 MISCELLANEOUS BIAS CONFIGURATIONS There are a number of BJT bias configurations that do not match the basic mold of those analyzed in the previous sections. 4. Solving for IB gives IB VCC RB (91 k 201 k 35.3 V 486. However. That is.7 V 110 k ) (75)(3.Solution In this case.5 IC IB (75)(35. the equation for the saturation current is the same as obtained for the voltage-divider and emitter-bias configurations.22 V I CRC 8. the base resistance for the dc analysis is composed of two resistors with a capacitor connected from their junction to ground.3 V 285.

The analysis is quite similar but does require dropping RE from the applied equation.51 A) 1.56 V 11.34. 4.rectly. (b) Find VB. but it does suggest a possible route to follow if a new configuration is encountered. For the network of Fig.244 M 20 V 0. it appears somewhat unorthodox and quite different from those encountered thus far.14 Figure 4. VE. EXAMPLE 4.7 V 680 k (120)(4.39: (a) Determine ICQ and VCEQ. 4. and VBC.7 V VCE 11. 4.7 V 10.7 k ) 11. Solution (a) The absence of RE reduces the reflection of resistive levels to simply that of RC and the equation for IB reduces to IB VCC RB VBE RC 19.86 mA)(4.26 V 0V VB VC 0. This is not to imply that all solutions will take this path.7 k ) 15. The first example is simply one where the emitter resistor has been dropped from the voltage-feedback configuration of Fig.39 Collector feedback with RE 0 .51 A ICQ VCEQ IB VCC 20 V VB VC VE VBC (120)(15.86 mA ICRC (1. but one application of Kirchhoff’s voltage law to the base circuit will result in the desired base current.7 Miscellaneous Bias Configurations 169 . Initially.26 V VBE 0.3 V 1.26 V In the next example. the applied voltage is connected to the emitter leg and RC is connected directly to ground. VC.

When the same network is analyzed on an ac basis. For the dc analysis the collector is grounded and the applied voltage is in the emitter leg.3 V The next example employs a network referred to as an emitter-follower configuration.3 V 100 k 83 A IC IB (45)(83 A) 3.15 Determine VC and VB for the network of Fig.15 Solution Applying Kirchhoff’s voltage law in the clockwise direction for the base–emitter loop will result in IBRB and Substitution yields IB 9 V 0.40 Example 4.735 mA)(1.40.735 mA VC ICRC (3.7 V 100 k 8. we will find that the output and input signals are in phase (one following the other) and the output voltage is slightly less than the applied signal.48 V VB IBRB (83 A)(100 k ) 8.EXAMPLE 4. 4.2 k ) 4. Figure 4. 170 Chapter 4 DC Biasing—BJTs VBE VEE RB VEE VBE 0 IB .

4.3 V 182 k 19.Determine VCEQ and IE for the network of Fig.41 Common-collector (emitter-follower) configuration.7 Miscellaneous Bias Configurations 171 .73 A) 4.3 V 422 k VEE VBE IB VBE IE ( ( IERE 1)IB 0 VEE 0 1)IBRE IBRB VEE VBE RB ( 1)RE 45.16 Figure 4.41.73 A IC IB (90)(45.7 V 240 k (91)(2 k ) 240 k 19. EXAMPLE 4.12 mA Applying Kirchhoff’s voltage law to the output circuit.73 A)(2 k ) VCE 0 4.68 V IE 4. Solution Applying Kirchhoff’s voltage law to the input circuit will result in IBRB but and with Substituting values yields IB 20 V 0. we have VEE but and IE VCEQ ( VEE 20 V 11.16 mA IERE 1)IB ( 1)IBRE (91)(45.

4 k ) Example 4.2 k 2. we obtain IE 4 V 0. Figure 4.75 mA)(2.17 Determine the voltage VCB and the current IB for the common-base configuration of Fig. Solution Applying Kirchhoff’s voltage law to the input circuit yields VEE and Substituting values. 4. In the next example we investigate the common-base configuration.75 mA IE IERE VEE RE VBE VBE 0 Applying Kirchhoff’s voltage law to the output circuit gives VCB and VCB VCC 10 V 3. The collector current is then available to perform an analysis of the output circuit.4 V IB IC 2.All of the examples thus far have employed a common-emitter or commoncollector configuration.42. 172 Chapter 4 DC Biasing—BJTs . EXAMPLE 4.42 Common-base configuration.7 V 1.8 A ICRC VCC 0 IE ICRC with IC (2. In this situation the input circuit will be employed to determine IE rather than IB.18 employs a split supply and will require the application of Thévenin’s theorem to determine the desired unknowns.75 mA 60 45.

VCC = + 20 V EXAMPLE 4.2 kΩ R2 2.7 kΩ C C2 vo 10 µF B β = 120 E R2 2. 4.18 RC R1 C1 vi 10 µF 8. RTh: RTh ETh: 8.85 mA)(2.4 k 3.2 k 2.45 Determining ETh.8 kΩ VEE = – 20 V Figure 4.53 V 20 V The network can then be redrawn as shown in Fig.85 mA ETh (3. Figure 4.Determine VC and VB for the network of Fig. 4.2 kΩ RTh VCC 20 V VEE I R1 R2 + 2.45. 4.43.46.2 k ) 11.2 kΩ R1 B 8.2 kΩ + B – – + 20 V ETh – Figure 4.2 kΩ 2.2 k 1.2 k 40 V 10. 8.18 Solution The Thévenin resistance and voltage are determined for the network to the left of the base terminal as shown in Figs.2 k 20 V 2.7 Miscellaneous Bias Configurations .44 Determining RTh.44 and 4.73 k I VCC R1 IR2 VEE R2 VEE 20 V 8. where the application of Kirchhoff’s voltage law will result in ETh IBRTh VBE IERE VEE 0 173 4.2 kΩ RE 1.43 Example 4.

7 k ) (11. Kirchhoff’s voltage law.25 mA VC VCC 20 V 8.8 DESIGN OPERATIONS Discussions thus far have focused on the analysis of existing networks.8 kΩ VEE = –20 V Figure 4.53 V VB ETh IBRTh (35. The path toward a solution is less defined and in fact may require a number of basic assumptions that do not have to be made when simply analyzing a network. All the elements are in place and it is simply a matter of solving for the current and voltage levels of the configuration. This synthesis process requires a clear understanding of the characteristics of the device.8 k ) 7.53 k 35. such as Ohm’s law.59 V 4.77 V 219.53 V 0.53 V + – 1.39 A IC IB (120)(35.+ IB E Th R Th – VB 1.46 Substituting the Thévenin equivalent circuit.73 kΩ + VBE β = 120 – RE E 11. In most situations the thinking process is challenged to a higher degree in the design process than in the analysis sequence. The design process is one where a current and/or voltage may be specified and the elements required to establish the designated levels must be determined.39 A)(1.53 V) 11.7 V 1. Substituting IE ( VEE 1)IB gives ETh IB VBE VEE RTh ( 1)IBRE IBRTh 0 ETh VBE ( 1)RE and 20 V 11.73 k (121)(1.39 A) 4. and so on. the basic equations for the network.25 mA)(2.73 k ) ICRC (4. 174 Chapter 4 DC Biasing—BJTs . and a firm understanding of the basic laws of circuit analysis.

Eq.44) can then be used to calculate the required resistance level. If the transistor and supplies are specified.47b.44) In a particular design the voltage across a resistor can often be determined from specified levels. This is certainly a valid approximation considering the tolerances normally associated with resistive elements and the transistor parameters.5 k 19. EXAMPLE 4.47a. The first few examples will demonstrate how particular elements can be determined from specified levels.19 Solution From the load line VCC IC and RC IB with RB 20 V VCC RC VCC IC VCC RB VCC IB 20 V 0. RB.47 Example 4. If additional specifications define the current level.19 Figure 4. determine VCC.7 V 40 A 482. 4. the design process will simply determine the required resistors for a particular design. (4. Once the theoretical values of the resistors are determined. the nearest standard commercial values are normally chosen and any variations due to not using the exact resistance values are accepted as part of the design.3 V 40 A 175 . A complete design procedure will then be introduced for two popular configurations. and RC for the fixedbias configuration of Fig. one of the most powerful equations is simply Ohm’s law in the following form: Runk VR IR (4. If resistive values are to be determined.5 k 4. 4. Given the device characteristics of Fig.The design sequence is obviously sensitive to the components that are already specified and the elements to be determined.8 Design Operations VCE 0V 20 V 8 mA VBE VBE 2.

1 VCC IC VE 10 V 2.20 Given that ICQ Fig.8 k The nearest standard commercial values to R1 are 82 and 91 k .1 V 3.2 k 268.44): RC VC RC VRC IC VCE with and 18 V 12.4 V 12. using the series combination of standard values of 82 k and 4.7 V 3.4 V VC 86.1 V VE 0.4V 2mA 2.1 V 3.7 k 86.7 k would result in a value very close to the design level. 2 mA and VCEQ 10 V.4 V 2.Standard resistor values: RC RB Using standard resistor values gives IB 41. 4.48.48 Example 4. EXAMPLE 4.4 V 3. determine R1 and RC for the network of Figure 4. (4.2 k 3.20 Solution VE VB VB and IERE VBE ICRE 2.1R1 R1 Eq.4 k 470 k which is well within 5% of the value specified.1 A 2. 176 Chapter 4 DC Biasing—BJTs .8 k (2 mA)(1.2 k ) R2VCC R1 R2 (18 k )(18 V) R1 18 k 324 k 3.1R1 268.52 k 55. However.

5 k 3.36 A 639. and 110. and RB. 2 ICsat.5 k 4 mA ICsat and RC RE RE VCC RC RE VCC ICsat 3.5 k 1k IBQ IBQ and with RB RB ( ICQ 4 mA 110 36.8 k 111 k 4.5 k VCC RB ( 1)RE VBE 1)RE VCC VBE IBQ ( 1)RE (111)(1 k ) VCC VBE IBQ 28 V 0.7 V 36.The emitter-bias configuration of Fig.49 Example 4.21 Figure 4.5 k 3. VC 18 V.36 A 28 V 8 mA RC 2. RE.8 Design Operations 177 .3 V 36. ICsat EXAMPLE 4.36 A 27.49 has the following specifications: ICQ 1 8 mA.21 Solution ICQ RC 1 2 Csat I 4 mA VCC VC ICQ VRC ICQ 28 V 18 V = 2. 4. Determine RC.

The selection of collector and emitter resistors cannot proceed directly from the information just specified.50 Emitter-stabilized bias circuit for design consideration.For standard values: RC RE RB 2. The discussion will be limited to the emitter-bias and voltage-divider bias configurations. At this point some engineering judgment must be made. The emitter resistor cannot be unreasonably large because the voltage across it limits the range of voltage swing of the voltage from collector to emitter (to be noted when the ac re178 Chapter 4 DC Biasing—BJTs . however. Recall that the need for including a resistor from emitter to ground was to provide a means of dc bias stabilization so that the change of collector current due to leakage currents in the transistor and the transistor beta would not cause a large shift in the operating point. In actual practice. such as the level of the emitter voltage compared to the applied supply voltage. and so on. 4. Figure 4. In addition. Design of a Bias Circuit with an Emitter Feedback Resistor Consider first the design of the dc bias components of an amplifier circuit having emitter-resistor bias stabilization as shown in Fig. although the same procedure can be applied to a variety of other transistor circuits. other system components connected to the given amplifier stage may also define the current swing. voltage swing.50. The supply voltage and operating point were selected from the manufacturer’s information on the transistor used in the amplifier. value of common supply voltage. many other factors may have to be considered that may affect the selection of the desired operating point. For the moment we shall concentrate. The equation that relates the voltages around the collector–emitter loop has two unknown quantities present—the resistors RC and RE. on determining the component values to obtain a specified operating point.4 k 1k 620 k The discussion to follow will introduce one technique for designing an entire circuit to operate at a specified bias point. Often the manufacturer’s specification (spec) sheets provide information on a suggested operating point (or operating region) for a particular transistor. for the design.

49 using the criteria just introduced for the emitter voltage.51 Current-gainstabilized circuit for design considerations.8 Design Operations 179 . as in the previous design consideration.51 provides stabilization both for leakage and current gain (beta) changes. 4. The design steps are all demonstrated in the next example. VE.33 A Design of a Current-Gain-Stabilized (Beta-Independent) Circuit The circuit of Fig. Figure 4. Engineering judgment in selecting a value of emitter voltage. In the next example we perform a complete design of the network of Fig. 4. leads to a direct straightforward solution for all the resistor values. The examples examined in this chapter reveal that the voltage from emitter to ground is typically around one-fourth to one-tenth of the supply voltage.3 M 2 mA 150 VCC 13.sponse is discussed).50 for the indicated operating point and supply voltage.33 A VBE IB VE 20 V 0.7 V 2 V 13. The four resistor values shown must be obtained for the specified operating point. 4. 4. Selecting the conservative case of one-tenth will permit calculating the emitter resistor RE and the resistor RC in a manner similar to the examples just completed. Determine the resistor values for the network of Fig. EXAMPLE 4.22 Solution VE RE RC 1 10 VCC 1 10 (20 V) 2V 2 mA VCE IC 2V 1k VE 20 V 10 V 2 mA 2V 8V 2 mA VE IE VRC IC 4k VE IC VCC IB RB IC VRB IB 1.

6 k VB and 2. That is. 4. In addition.7R1 R1 32 k 27.7 V The equations for the calculation of the base resistors R1 and R2 will require a little thought. 180 Chapter 4 DC Biasing—BJTs . RE. note the absence of a dc supply connected to the base circuit.23 Determine the levels of RC. The network of Fig. Solution VE RE RC 1 10 VCC 1 10 (20 V) 2V 10 mA VCE IC 0. An additional equation can be obtained from an understanding of the operation of these two resistors in providing the necessary base voltage.7 V (1. R2 and Substitution yields R2 1 10 1 10 RE R2 R2 VCC VB R1 (80)(0.6 k 4. Using the value of base voltage calculated above and the value of the supply voltage will provide one equation—but there are two unknowns. R1 and R2.51 for the operating point indicated. Through proper design it can be used as a switch for computer and control applications. R1. it is assumed that the current through R1 and R2 should be approximately equal and much larger than the base current (at least 10 1). For the circuit to operate efficiently.EXAMPLE 4. Note that the output voltage VC is opposite to that applied to the base or input terminal.52a can be employed as an inverter in computer logic circuitry.2 k ) 1.9 TRANSISTOR SWITCHING NETWORKS The application of transistors is not limited solely to the amplification of signals.32 k 2. and R2 for the network of Fig. The only dc source is connected to the collector or output side and for computer applications is typically equal to the magnitude of the “high” side of the applied signal—in this case 5 V.25 k (use 10 k ) 2.7 V 2V 200 VE 20 V 8V 2V 10 mA 10 V 10 mA VE IE VRC IC 1k VBE VE IC VCC VB VE 2V 2.6 k )(20 V) R1 1.7R1 4. This fact and the voltagedivider equation for the base voltage provide the two relationships necessary to determine the base resistors.68 k 10. 4.

In Fig. 4. this requires that IB 50 A. Proper design for the inversion process requires that the operating point switch from cutoff to saturation along the load line depicted in Fig. we will assume that VCE VCEsat 0 V rather than the typical 0. When Vi 5 V.45) 4.52b. For our purposes we will assume that IC ICEO 0 mA when IB 0 A (an excellent approximation in light of improving construction techniques). as shown in Fig.to 0.9 Transistor Switching Networks 181 .1 mA 6 5 4 3 2 1 0 1 ~ VCE sat = 0 V 2 3 ~ I CEO = 0 mA (b) 4 10 µA I B = 0 µA 5 VCC = 5 V VCE 50 µA 40 µA 30 µA 20 µA Figure 4.3-V level. 4.82 kΩ VC h FE = 125 VC 5V 0V t 68 kΩ 0V t (a) I C (mA) 60 µA 7 I C sat = 6.52 Transistor inverter. In addition.52b.52a is defined by ICsat VCC RC (4. The saturation level for the collector current for the circuit of Fig.52b.1.VCC = 5 V Vi 5V RB RC 0. the transistor will be “on” and the design must ensure that the network is heavily saturated by a level of IB greater than that associated with the IB curve appearing near the saturation level. 4. 4.

Using a typical average value of VCEsat such as 0.1 mA 24.7 V 63 A IB 68 k RB and ICsat VCC RC 5V 0. 4. resulting in VC for the response indicated in Fig.46) gives IB 63 A ICsat dc 6.6 which is a relatively low value and kilohm range. (4.8 A which is satisfied.52a.52b. the resulting level of IB is the following: 5 V 0. 182 Chapter 4 DC Biasing—BJTs when placed in series with resistors in the . the current IC is quite high and the voltage VCE very low.1 mA Testing Eq. 4.53 Saturation conditions and the resulting terminal resistance. For Vi 0 V.1 mA 125 48.7 V Vi 0.15 V 6.The level of IB in the active region just before saturation results can be approximated by the following equation: ICsat IBmax dc For the saturation level we must therefore ensure that the following condition is satisfied: IC IB sat (4. C I Csat + – E VCE sat C R ≅ 0Ω E Figure 4. the transistor can also be employed as a switch using the same extremities of the load line. the 5V voltage drop across RC as determined by VRC ICRC 0 V.53. any level of IB greater than 60 A will pass through a Q-point on the load line that is very close to the vertical axis. At saturation. and since we are assuming that IC ICEO 0 mA. IB 0 A.82 k 6. The result is a resistance level between the two terminals determined by VCEsat Rsat ICsat and depicted in Fig. when Vi 5 V.15 V gives Rsat VCEsat ICsat 0 0. 4. In addition to its contribution to computer logic.46) dc For the network of Fig. Certainly.

4.54.55 if ICsat 10 mA.9 Transistor Switching Networks 183 . Determine RB and RC for the transistor inverter of Fig. the 5V VCC 500 k 10 A ICEO which certainly approaches an open-circuit equivalence for many situations.24. Solution At saturation: ICsat and so that At saturation: IB Choosing IB IC sat dc VCC RC 10 V RC 1k 10 mA RC 10 V 10 mA 10 mA 250 40 A 60 A to ensure saturation and using IB Vi 0.7 V RB 4.55 Inverter for Example 4.Figure 4.24 VCC = 10 V Vi 10 V VC RB Vi 0V 0V t h FE = 250 0V t VC 10 V 10 V RC Figure 4. EXAMPLE 4.54 Cutoff conditions and the resulting terminal resistance. For a typical value of ICEO magnitude of the cutoff resistance is Rcutoff 10 A. the cutoff condition will result in a resistance level of the following magnitude: VCC 5V Rcutoff ICEO 0 mA resulting in the open-circuit equivalence. For Vi 0 V. 4. as shown in Fig.

56 Defining the time intervals of a pulse waveform.7 V 10 V 0. tr. 184 Chapter 4 DC Biasing—BJTs . The total time required for the transistor to switch from the “off” to the “on” state is designated as ton and defined by ton tr td (4. There are transistors that are referred to as switching transistors due to the speed with which they can switch from one voltage level to the other.48) where ts is the storage time and tf the fall time from 90% to 10% of the initial value.7 V 150 k RB ICsat 62 A 40 A dc Vi 62 A and Therefore. and tf are provided versus collector current. use RB IB 150 k and RC 1k . which is a standard value. Their impact on the speed of response of the collector output is defined by the collector current response of Fig.we obtain Choose RB RB Vi 0. The time element tr is the rise time from 10% to 90% of the final value.7 V 60 A 155 k 150 k . Then IB 0.7 V IB 10 V 0. td. In Fig.23c the periods of time defined as ts. 4.56.47) with td the delay time between the changing state of the input and the beginning of a response at the output. 3. The total time required for a transistor to switch from the “on” to the “off” state is referred to as toff and is defined by toff ts tf (4. Transistor "on" Transistor "off" IC 100% 90% 10% 0 td tr t on t off ts tf t Figure 4.

57. such as 0. For a pnp transistor. the first step in being able to troubleshoot a network is to fully understand the behavior of the network and to have some idea of the expected voltage and current levels. Any reading totally different from the expected level of about 0. we find that 12 ns tr ts td tf 13 ns 120 ns 25 ns 12 ns 38 ns 132 ns Comparing the values above with the following parameters of a BSV52L switching transistor reveals one of the reasons for choosing a switching transistor when the need arises. 4. Figure 4. a reading of VCE of 1 to 2 V or 18 to 20 V as measured in Fig. the most important measurable dc level is the base-to-emitter voltage.7 V. If VCE 20 V (with VCC 20 V) at least two possibilities exist—either the device (BJT) is damaged and has the Figure 4.58 is certainly an uncommon result. A voltage level of equal importance is the collector-to-emitter voltage. For the transistor in the active region. or 12 V.10 Troubleshooting Techniques 185 . Note that the positive (red) lead is connected to the base terminal for an npn transistor and the negative (black) lead to the emitter terminal. 4. However. The proper connections for measuring VBE appear in Fig. 4. or negative in value would be suspect and the device or network connections should be checked. For an “on” transistor.57 Checking the dc level of VBE.For the general-purpose transistor of Fig. ton 12 ns and toff 18 ns 4. the voltage VBE should be in the neighborhood of 0. Quite obviously. However: For the typical transistor amplifier in the active region. the same connections can be used but a negative reading should be expected.3 V suggest a saturated device—a condition that should not exist unless being employed in a switching mode. 3.23c at IC ts td tr and so that and tf ton toff 120 ns 25 ns 13 ns 10 mA.10 TROUBLESHOOTING TECHNIQUES The art of troubleshooting is such a broad topic that a full range of possibilities and techniques cannot be covered in a few sections of a book.58 Checking the dc level of VCE. Recall from the general characteristics of a BJT that levels of VCE in the neighborhood of 0. VCE is usually about 25% to 75% of VCC.7 V. the practitioner should be aware of a few basic maneuvers and measurements that can isolate the problem area and possibly identify a solution. For VCC 20 V. 4. and unless knowingly designed for this response the design and operation should be investigated.

rather than the desired 28.7 V 680 28. Could it be that the internal connection between the wire and the end connection of a lead is faulty? How often has simply touching a lead at the proper point created a “make or break” situation between connections? Perhaps the supply was turned on and set at the proper voltage but the current-limiting knob was left in the zero position.59. Obviously. For VCC 20 V and a fixed-bias configuration. All resistor levels seem correct. On large schematics. one must simply be aware of typical levels within the system as defined by the applied potential and general operation of the network. If VRC and VRE are reasonable values but VCE is 0 V. Chapter 4 DC Biasing—BJTs 186 . Current levels are usually calculated from the voltage levels across resistors rather than “breaking” the network to insert the milliammeter section of a multimeter. the resulting base current would be IB Figure 4. the connections appear solid. Since actual resistor values are often different from the nominal color-code value (recall the common tolerance levels for resistive elements).resistor for RB rather than the design value of 680 k . Imagine the impact of using a 680. 20 V 0. If the meter is connected to the collector terminal of the BJT. for the networks covered in this chapter. It should be somewhat obvious from the discussion above that the voltmeter section of the VOM or DMM is quite important in the troubleshooting process.4 mA Figure 4. The failure of any of these points to register what would appear to be a reasonable level may be sufficient in itself to define the faulty connection or element. preventing the proper level of current as demanded by the network design. the reading will be 0 V since VCC is blocked from the active device by the open circuit. There are times when frustration will develop. it is time well spent to measure a resistor before inserting it in the network. it should read VCC volts since the network has one common ground for the supply and network parameters. one of the most effective methods of checking the operation of a network is to check various voltage levels with respect to ground by hooking up the black (negative) lead of a voltmeter to ground and “touching” the important terminals with the red (positive) lead. In any case. the network may be in saturation with a device that may or may not be defective. 4. the broader the range of possibilities. the possibility exists that the BJT is damaged and displays a short-circuit equivalence between collector and emitter terminals. 4. The result is actual values closer to theoretical levels and some insurance that the correct resistance value is being employed. In Fig.60. if the red lead is connected directly to VCC. the black lead of the voltmeter is connected to the common ground of the supply and the red lead to the bottom terminal of the resistor. establishing IC at 0 mA and VRC 0 V.characteristics of an open circuit between collector and emitter terminals or a connection in the collector–emitter or base–emitter circuit loop is open as shown in Fig.60 Checking voltage levels with respect to ground. and the proper supply voltage has been applied—what next? Now the troubleshooter must strive to attain a higher level of sophistication. At VC the reading should be less. the more sophisticated the system.59. 4. As noted earlier. The absence of a collector current and a resulting drop across RC will result in a reading of 20 V. as determined by the drop across RC and VE should be less than VC by the collector–emitter voltage VCE. specific voltage levels are provided with respect to ground for easy checking and identification of possible problem areas. One of the most common errors in the laboratory experience is the use of the wrong resistance value for a given design. You have checked the device on a curve tracer or other BJT testing instrumentation and it looks good.4 mA would certainly place the design in a saturation region and possibly damage the device. In Fig.3 V as defined by VCE VC VE (the difference of the two levels as measured above). if VCE registers a level of about 0. Of course.59 Effect of a poor connection or damaged device.4 A—a significant difference! A base current of 28.

61 Network for Example 4. the base current should be IB VCC RB ( VBE 1)RE 20 V 0. The level of VRB 19. therefore. and that will come only with continued exposure to practical circuits. Solution The 20 V at the collector immediately reveals that IC 0 mA. In fact.61.85 V 250 k 79. if not.25. with a short-circuit condition between base and emitter. if we assume a short circuit condition from base to emitter. Based on the readings appearing in Fig. determine whether the network is operating properly and. Based on the readings provided in Fig. 4. the probable cause. due to an open circuit or a nonoperating transistor. determine whether the transistor is “on” and the network is operating properly. the troubleshooting process is a true test of your clear understanding of the proper behavior of a network and the ability to isolate problem areas using a few basic measurements with the appropriate instruments.85 V also reveals that the transistor is “off ” since the difference of VCC VRB 0. we obtain the following current through RB: IRB VCC RB RE VRB RB 20 V 252 k 79. 4.7 V 250 k (101)(2 k ) 19.25 Figure 4.4 A which matches that obtained from IRB 19.10 Troubleshooting Techniques EXAMPLE 4.4 A If the network were operating properly.26 187 . 4.7 A The result. EXAMPLE 4. Experience is the key.3 V 452 k 42.15 V is less than that required to turn “on” the transistor and provide some voltage for VE. is that the transistor is in a damaged state.All in all.62.

Using the defined polarities of Fig. 4.3 V at the emitter results in a 0. Applying Kirchhoff’s voltage law to the base–emitter loop will result in the following equation for the network of Fig.62 Network for Example 4.50) VCE ICRC VCC 0 The resulting equation has the same format as Eq. However. In fact. the only difference between the resulting equations for a network in which an npn transistor has been replaced by a pnp transistor is the sign associated with particular quantities. and if okay. Fortunately.63 pnp transistor in an emitter-stabilized configuration. The current directions. First. have been reversed to reflect the actual conduction directions. although the connection to the supply must be “solid” or the 20 V would not appear at the collector of the device. Since VCC will be larger than the magnitude of the succeeding term. the voltage VCE will have a negative sign. As noted in Fig.Solution Based on the resistor values of R1 and R2 and the magnitude of VCC. both VBE and VCE will be negative quantities.7 V and the substitution of values will result in the same ever. in this case VBE sign for each term of Eq.49) as Eq.49) Figure 4. The level of IB is first determined. as noted in an earlier paragraph. (4.7-V drop across the base-to-emitter junction of the transistor. but the sign in front of each term on the right of the equal sign has changed.11 PNP TRANSISTORS The analysis thus far has been limited totally to npn transistors to ensure that the initial analysis of the basic configurations was as clear as possible and uncomplicated by switching between types of transistors. 4. (4.63. 4. resulting in the following equation: IERE Substituting IE IC gives VCE VCC IC(RC RE) (4. the 20 V at the collector reveals that IC 0 mA. check the continuity at the collector junction using an ohmmeter. the double-subscript notation continues as normally defined.17).63: IERE Substituting IE ( VBE IBRB VCC 0 1)IB and solving for IB yields IB VCC RB VBE 1)RE (4. 188 Chapter 4 DC Biasing—BJTs . followed by the application of the appropriate transistor relationships to determine the list of unknown quantities. For VCE Kirchhoff’s voltage law is applied to the collector–emitter loop.19). (4. Keep in mind that the direction of IB is now defined opposite of that for a pnp transistor as shown in Fig.26. Figure 4. How0. (4.17) except for the sign for VBE. Two possibilities exist—there can be a poor connection between RC and the collector terminal of the transistor or the transistor has an open base-tocollector junction.63. The resulting equation is the same as Eq.63. however. the analysis of pnp transistors follows the same pattern established for npn transistors. 4. the voltage VB 4 V seems appropriate (and in fact it is). the transistor should be checked using one of the methods described in Chapter 3. 4. The 3. suggesting an “on” transistor.

Applying Kirchhoff’s voltage law around the base–emitter loop yields VB and Substituting values.64.Determine VCE for the voltage-divider bias configuration of Fig. we have VB R2VCC R1 R2 (10 k )( 18 V) 47 k 10 k 3. For an npn transistor the equation VE VB VBE would be exactly the same.11 PNP Transistors VBE VB VE VBE 0 VE ( 0.46 V Note in the equation above that the standard single.and double-subscript notation is employed.46 V 1. 4.7 V VE RE 2. we have 189 .1 kΩ Figure 4.64 pnp transistor in a voltage-divider bias configuration. –18 V 2. The only difference surfaces when the values are substituted.1 k ) 132 k Solving for VB.27 47 kΩ 10 µF vi + VCE β = 120 – E 10 kΩ 1.16 V 10R2 10(10 k ) 100 k (satisfied) Note the similarity in format of the equation with the resulting negative voltage for VB.4 kΩ 10 µF C B vo EXAMPLE 4. The current IE For the collector–emitter loop: IERE Substituting IE VCE VCE VCC ICRC IC(RC VCC RE) 4.1 k 2.16 V 2.16 V 3.7 V) 0. we obtain VE 3. Solution Testing the condition RE results in (120)(1.24 mA 0 IC and gathering terms.

An arbitrary point is marked in Fig.Substituting values gives VCE 18 V 18 V 10.1 nA.65b. In any amplifier employing a transistor the collector current IC is sensitive to each of the following parameters: : increases with increase in temperature VBE : decreases about 7.48 V. For the same temperature variation.84 V 1.85 0. In the extreme. neither of which is affected by temperature or the change in leakage current or beta. 4. the same base current magnitude will exist at high temperatures as indicated on the graph of Fig.12 BIAS STABILIZATION The stability of a system is a measure of the sensitivity of a network to variations in its parameters. especially for levels beyond the threshold value.30 The effect of changes in leakage current (ICO) and current gain ( ) on the dc bias point is demonstrated by the common-emitter collector characteristics of Fig.65 to 0. TABLE 4.65a and b.5 mV per degree Celsius (°C) increase in temperature ICO (reverse saturation current): doubles in value for every 10°C increase in temperature Any or all of these factors can cause the bias point to drift from the designed point of operation. Note that the significant increase in leakage current not only causes the curves to rise but also an increase in beta. 4. the new operating point may not 190 Chapter 4 DC Biasing—BJTs . 4. this will result in the dc bias point’s shifting to a higher collector current and a lower collector–emitter voltage operating point.48 0.1 reveals how the level of ICO and VBE changed with increase in temperature for a particular transistor. In any case.16 V (2. while at 100°C (boiling point of water) ICO is about 200 times larger at 20 nA.4 k 7. increased from 50 to 80 and VBE dropped from 0.65 shows how the transistor collector characteristics change from a temperature of 25°C to a temperature of 100°C.65a at IB 30 A.65 0.2 10 3 0. An operating point may be specified by drawing the circuit dc load line on the graph of the collector characteristic and noting the intersection of the load line and the dc base current set by the input circuit.24 mA)(2.1 20 3. Table 4. At room temperature (about 25°C) ICO 0. Figure 4. as revealed by the larger spacing between curves. As the figure shows.3 103 20 50 80 120 VBE(V) 0. Since the fixed-bias circuit provides a base current whose value depends approximately on the supply voltage and base resistor. Recall that IB is quite sensitive to the level of VBE.1 Variation of Silicon Transistor Parameters with Temperature T (°C) 65 25 100 175 ICO (nA) 0.1 k ) 4. the transistor could be driven into saturation.

is defined for each of the parameters affecting bias stability as listed below: S(ICO) IC ICO IC VBE IC (4. S. A better bias circuit is one that will stabilize or maintain the dc bias initially set.12 Bias Stabilization 191 .51–4. (b) 100°C.53) to be sensitivity factors because: 4.51) S(VBE) (4. For a particular configuration. the delta symbol ( ) signifies change in that quantity. In some ways it would seem more appropriate to consider the quantities defined by Eqs. The numerator of each equation is the change in collector current as established by the change in the quantity in the denominator.65 Shift in dc bias point (Q-point) due to change in temperature: (a) 25°C. In other words: Networks that are quite stable and relatively insensitive to temperature variations have low stability factors. so that the amplifier can be used in a changing-temperature environment. and S( ) A stability factor. (4. if a change in ICO fails to IC/ ICO produce a significant change in IC. Stability Factors. be at all satisfactory.52) S( ) (4.Figure 4. S(VBE). and considerable distortion may result because of the bias-point shift.53) In each case. the stability factor defined by S(ICO) will be quite small. S(ICO).

(4. It is interesting to note in Fig. however.66 Variation of stability factor S(ICO) with the resistor ratio RB /RE for the emitter-bias configuration. Our purpose here. that good bias control normally requires that RB be greater than RE.54) will approach the following level (as shown in Fig.66. For RB/RE 4. (4. Eq. however.55) as shown on the graph of S(ICO) versus RB/RE in Fig. the more sensitive the network to variations in that parameter. and if time permits. a trade-off must occur that will satisfy both the stability and bias specifications.54) 1).57) 192 Chapter 4 DC Biasing—BJTs . The result therefore is a situation where the best stability levels are associated with poor design criteria. Keep in mind. 1 S(ICO) ( 1) ( 1) →1 (4. 4. an analysis of the network will result in 1 S(ICO) For RB/RE ( ( 1) ( RB/RE 1) RB/RE (4.54) will reduce to the following: S(ICO) 1 (4. The study of stability factors requires the knowledge of differential calculus.The higher the stability factor.66 that the lowest value of S(ICO) is 1. revealing that IC will always increase at a rate equal to or greater than ICO. you are encouraged to read more on the subject. A great deal of literature is available on this subject. the stability factor will For the range where RB/RE ranges between 1 and ( be determined by S(ICO) RB RE (4.56) revealing that the stability factor will approach its lowest level as RE becomes sufficiently large. 1). Obviously. is to review the results of the mathematical analysis and to form an overall assessment of the stability factors for a few of the most popular bias configurations. 4. Eq. S(ICO): EMITTER-BIAS CONFIGURATION For the emitter-bias configuration. Figure 4.66): 1.

9 nA) RB/RE RB/RE 11 51 61 (9.28 Solution (a) S(ICO) 1 1 250 51 51 250 42.01 1.01 51 51 0. (a) RB/RE 250 (RB 250RE) (b) RB/RE 10 (RB 10RE).66. 4.12 Bias Stabilization 193 .1 nA 1.53.53)(19.085 mA in the worst case.1 for the following emitter-bias arrangements. [S(ICO)]( ICO) 0. Even though the change in IC is considerably different in a circuit having ideal stability (S 1) from one having a stability factor of 42.2 IC [S(ICO)]( ICO) 0.01 (RE 100RB). say.9 nA) Example 4.9 nA) RB/RE RB/RE 1.01 51 51.53 which begins to approach the level defined by IC (42.28 reveals how lower and lower levels of ICO for the modern-day BJT transistor have improved the stability level of the basic bias configurations.54) by RE and then plug in RE 0 .85 A 1 1) (b) S(ICO) ( 1 1 10 51 51 10 9. For example. ( 1) 1 RB/RE RB/RE 251 51 301 1 51.01 1.18 A 1 (c) S(ICO) ( 1) 1 1 0. FIXED-BIAS CONFIGURATION For the fixed-bias configuration. which is obviously small enough to be ignored for most applications. (4. 2 mA.2)(19.01(19. the following equation will result: S(ICO) 1 (4. EXAMPLE 4.as shown in Fig. if we multiply the top and bottom of Eq.58) 4. (c) RB/RE 0. Some power transistors exhibit larger leakage currents.01 which is certainly very close to the level of 1 forecast if RB/RE IC [S(ICO)]( ICO) 20. would be from 2 to 2. the amount of change in IC from a dc bias current set at. ratio approaches ( Calculate the stability factor and the change in IC from 25°C to 100°C for the transistor defined by Table 4. but for most amplifier circuits the lower levels of ICO have had a very positive impact on the stability question. the change in IC is not that significant. The results reveal that the emitter-bias configuration is quite stable when the ratio RB/RE is as small as possible and the least stable when the same 1).

67. with IB maintaining a fairly constant value—a very unstable situation. RTh can be much less than the corresponding RB of the emitter-bias configuration and still have an effective design. The result is a drop in the level of IB as determined by the following equation: 194 Chapter 4 DC Biasing—BJTs . We are now aware of the relative levels of stability and how the choice of parameters can affect the sensitivity of the network. 4. The next few paragraphs attempt to fill this void through the use of some of the very basic relationships associated with each configuration. the equation for the base current is the following: IB VCC RB VBE with the collector current determined by IC IB ( 1)ICO (4. the equation for S(ICO) is the following: S(ICO) ( 1) 1 ( RTh/RE 1) RTh/RE (4. 4. the same conclusions regarding the ratio RB/RC can be applied here also.Note that the resulting equation matches the maximum value for the emitter-bias configuration.5 the development of the Thévenin equivalent network appearing in Fig.68a.67 Equivalent circuit for the voltage-divider configuration.59). Voltage-Divider Bias Configuration Recall from Section 4. for the voltage-divider bias configuration. (4. For the emitter-bias configuration of Fig. For the voltage-divider bias configuration. The result is a configuration with a poor stability factor and a high sensitivity to variations in ICO. the corresponding condition is RE RTh or RTh/RE should be as small as possible. however. where it was determined that S(ICO) had its lowest level and the network had its greatest stability when RE RB. 4. S(ICO) ( 1) 1 ( ) RB/RC 1) RB/RC (4. (4. (4. an increase in IC due to an increase in ICO will cause the voltage VE IERE ICRE to increase.59) Figure 4. In other words. 4. there is nothing in the equation for IB that would attempt to offset this undesirable increase in current level (assuming VBE remains constant). For the network of Fig.54).61) should increase due to an increase in ICO. the level of IC would continue to rise with temperature. but without the equations it may be difficult for us to explain in words why one network is more stable than another. For the fixed-bias configuration of Fig.60) Since the equation is similar in format to that obtained for the emitter-bias and voltage-divider bias configurations. Feedback-Bias Configuration (RE 5 0 In this case.61) If IC as defined by Eq.67.68b. Physical Impact Equations of the type developed above often fail to provide a physical sense for why the networks perform as they do. For Eq. Note the similarities with Eq.

In total. The feedback configuration of Fig. If IC should increase.12 Bias Stabilization 195 . S(VBE) The stability factor defined by S(VBE) IC VBE will result in the following equation for the emitter-bias configuration: S(VBE) Substituting RE 0 RB ( 1)RE (4.68d. VE will increase as described above.Figure 4. If the condition RE 10R2 is satisfied.64) as occurs for the fixed-bias configuration will result in S(VBE) (4. the level of VRC will increase in the following equation: VCC VBE VRC ↑ (4. The base-to-emitter voltage of the configuration is determined by VBE VB VE. the configuration is such that there is a reaction to an increase in IC that will tend to oppose the change in bias conditions.62) A drop in IB will have the effect of reducing the level of IC through transistor action and thereby offset the tendency of IC to increase due to an increase in temperature. IB ↓ VCC VBE RB VE ↑ (4.63) IB ↓ RB and the level of IB will decrease. 4.68c operates in much the same way as the emitter-bias configuration when it comes to levels of stability. and for a constant VB the voltage VBE will drop. In other words.68 Review of biasing managements and the stability factor S(ICO). The result is a stabilizing effect as described for the emitter-bias configuration. One must be aware that the action described above does not happen in a step-by-step sequence. it is a simultaneous action to maintain the established bias conditions. which will try to offset the increased level of IC.65) RB 4. 4. therefore. the very instant IC begins to rise the network will sense the change and the balancing effect described above will take place. The most stable of the configurations is the voltage-divider bias network of Fig. the voltage VB will remain fairly constant for changing levels of IC. If IC should increase due to an increase in temperature. A drop in VBE will establish a lower level of IB. Rather.

417 and IC ( 0.7 k .29 Determine the stability factor S(VBE) and the change in IC from 25°C to 100°C for the transistor defined by Table 4. (4.417 70.64): S(VBE) RB 240 k 0. (c) Emitter-bias with RB 47 k . (4. (4.67) revealing that the larger the resistance RE.1 for the following bias arrangements. RE 1 k . 100. negating the use of Eq. the lower the stability factor and the more stable the system.64) can be written in the following form: S(VBE) Substituting the condition ( for S(VBE): S(VBE) 1) /RE 1 RB/RE /RE ( 1) (4.7 k 10 (satisfied) 196 Chapter 4 DC Biasing—BJTs .67) and requiring the use of Eq.293 10 3)( 0.66) RB/RE will result in the following equation /RE 1 RE (4.Equation (4. IC [S(VBE)]( VBE) ( 0.293 ( 1)RE 100 (101)1 k 10 3 100 341 k 1)RE which is about 30% less than the fixed-bias value due to the additional ( term in the denominator of the S(VBE) equation.48 V 10 3)( 0. The condition ( 1) RB/RE is (b) In this case. ( not satisfied. (a) Fixed-bias with RB 240 k and 100. and Solution (a) Eq.64).9 A 10 3 [S(VBE)]( VBE) 10 3)(0. (b) Emitter-bias with RB 240 k . EXAMPLE 4.17 V) 50 A (c) In this case.417 ( 0.65): S(VBE) RB 100 240 k 0.65 V) 1) 101 and RB/RE 240. (4.17 V) 0. ( 1) 101 RB RE 47 k 4. and 100. Eq. RE 4.

the increase of 70. For the voltage-divider configuration.5% increase.04 A 10 3)( 0.9 A 2. or a change in transistors. (4.Eq.29. Determine ICQ at a temperature of 100°C if ICQ 2 mA at 25°C.0709 mA a 3. Use the transistor described by Table 4. where 1 50 and 2 80.68) The notation IC1 and 1 is used to define their values under one set of network conditions.7 k 0.64) (as defined by Fig.67): S(VBE) 1 RE 1 4.17 V) In Example 4. The resulting equation for S(VBE) for the feedback network will be similar to that of Eq. 4.212 36. In Example 4.30 Solution Eq.12 Bias Stabilization 197 . The mathematical development is more complex than that encountered for S(ICO) and S(VBE).64) with RE replaced by RC.67). (4. (4.1. For a situation where ICQ 2 mA. variation in for the same transistor. the resulting collector current will increase to ICQ 2 mA 70.32 10 ] 10 6)(30) 6 and IC [S( )][ (8.212 10 3 and IC [S(VBE)]( VBE) ( 0.29. the level of RB will be changed to RTh in Eq. as suggested by the following equation for the emitter-bias configuration: S( ) IC IC1(1 1(1 2 RB/RE) RB/RE) (4.25 mA 4.9 A will have some impact on the level of ICQ. EXAMPLE 4. while the notation 2 is used to define the new value of beta as established by such causes as temperature change. However. and a resistance ratio RB/RE of 20.32 0. RTh for the voltage-divider configuration can be this level or lower and still maintain good design characteristics. S( ) The last stability factor to be investigated is that of S( ). (4. the use of RB 47 k is a questionable design.68): S( ) IC1(1 1(1 2 3 RB/RE) 42 10 5050 3 RB/RE) (2 10 )(1 20) (50)(1 80 20) 8.

representing a change of 12. the IC to be determined is simply the change in IC from the level at room temperature. In addition. but take note that each component is simply a stability factor for the configuration multiplied by the resulting change in a parameter between the temperature limits of interest.42 A 50 ( 0.71) IC ( RB 1 after substituting the stability factors as derived in this section.In conclusion therefore the collector current changed from 2 mA at room temperature to 2.2 10 3.077 mA 10 3( 0. (4. the resulting change in IC due to an increase in temperature of 75°C is the following: IC (50 1)(19.4 A 10 6(30) 198 Chapter 4 DC Biasing—BJTs . The fixed-bias configuration is defined by S( ) IC1/ be replaced by RTh for the voltage-divider configuration.7 k .68) can .01 A 1. (4. the total effect on the collector current can be determined using the following equation: IC S(ICO) ICO S(VBE) VBE S( ) (4.2 0.17 V) 240 k 1200 A 2 mA (30) 50 1.25 mA at 100°C. then S(ICO) and IC 2. If the more stable voltage-divider configuration were employed with a ratio RTh/RE 2 and RE 4. The collector current has increased from 2 to 3.5%.51 nA 0. Eq.236 mA—but this was expected in the sense that we recognize from the content of this section that the fixed-bias configuration is the least stable. For this range the table reveals that ICO VBE and 20 nA 0.1 nA 0.236 mA which is a significant change due primarily to the change in .65 V 30 19.89. For instance.48 V 80 50 0. S( ) 1.445 1.17 V (note the sign) Starting with a collector current of 2 mA with an RB of 240 k .69) Summary Now that the three stability factors of importance have been introduced.89)(19.17 V) 43.9 nA) 57. if we examine the fixed-bias configuration.445 10 6 (2.9 nA 0.70) becomes the following: IC1 1) ICO VBE (4. (4.9 nA) 35.70) The equation may initially appear quite complex. S(VBE) 34 A 0.1 to find the change in collector current for a temperature change from 25°C (room temperature) to 100°C (the boiling point of water). Let us now use Table 4. For the collector feedback configuration with RE 0 S( ) IC1(RB RC) RC(1 1(RB 2)) 1 and RB of Eq.

including the ac response.1 mA. It should also be mentioned that for a particular transistor the variation in levels of ICBO and VBE from one transistor to another in a lot is almost negligible compared to the variation in beta. The capacitor will also appear in the ANALOG. at higher temperatures. This is accom- Figure 4.The resulting collector current is 2. Using methods described in previous chapters.13 PSPICE WINDOWS Voltage-Divider Configuration The results of Example 4.1. The network is obviously a great deal more stable than the fixedbias configuration. Recall that a positive result is obtained for IPROBE if the direction of conventional current enters that side of the symbol with the internal curve representing the scale of the meter.69 as obtained from the SPECIAL. In addition.slb. We are now more aware of how the dc response of the design can vary with the parameter variations of a transistor. Recall that the transistor can be found in the EVAL.slb library. and the resistor under ANALOG. the effects of S(ICO) and S(VBE) will be greater than S( ) for the device of Table 4. 4.077 mA.13 PSpice Windows 199 .slb.0 mA at 25°C. 4. Although the analysis above may have been clouded by some of the complex equations for some of the sensitivities.7 will now be verified using PSpice Windows. as mentioned in earlier discussions. the network of Fig. The effect of S(ICO) in the design process is becoming a lesser concern because of improved manufacturing techniques that continue to lower the level of ICO ICBO.slb library. IC will decrease with increasingly negative temperature levels. In fact.slb library. S( ) did not override the other two factors and the effects of S(VBE) and S(ICO) were equally important. compared to the 2.69 Applying PSpice Windows to the voltage-divider configuration of Example 4. 4. In this case. Three VIEWPOINTS appear in Fig.7.slb library. The analysis of the earlier sections was for idealized situations with nonvarying parameter values. also appearing in the SPECIAL. 4. or essentially 2. the purpose here was to develop a higher level of awareness of the factors that go into a good design and to be more intimate with the transistor parameters and their impact on the network’s performance. the dc source under SOURCE.69 can be constructed. We will want to set the value of beta for the transistor to match that of the example. The collector current will be sensed by the IPROBE option. the results of the analysis above support the fact that for a good stabilized design: The ratio RB/RE or RTh/RE should be as small as possible with due consideration to all aspects of the design. For temperatures below 25°C.

266 V 12. 4. Fixed-Bias Configuration The fixed-bias configuration of Fig. 4.7.70. which are very close to those of Fig. Since the voltage-divider network is one that is to have a low sensitivity to changes in beta. Then Bf is changed to 140 to match the value of Example 4.69.42 V.22 V of Example 4. In addition.76 V 1. let us return to the transistor and replace the beta of 140 with the default value of 225.69. Figure 4.85 mA.plished by clicking on the transistor symbol (to obtain the red outline) followed by Edit-Model-Edit Instance Model (text) to obtain the Model Editor. versus 0.85 mA.7. Any differences are due to the fact that we are using an actual transistor with a host of parameters not considered in our analysis. and let us proceed with the same type of analysis for the fixed-bias configuration and compare notes.71 is from Example 4. 4. It will save us from having to deal with the Probe response before viewing the output file or screen. that the voltage-divider configuration demonstrates a low sensitivity to changes in beta.1 to permit a comparison of results.824 mA. versus 12.70 Response obtained after changing from 140 to 255. Beta was set to 50 using the procedure described above. The sequence Analysis-Simulate will result in the dc levels appearing in Fig.259 V 12. 0. In this case. however. that the fixed-bias configuration was very sensitive to changes in beta. The collector current is actually closer to the hand-calculated level.9 and examine the results. which is very close to that obtained with a much lower beta. Recall the difference in beta from the specification value and the value obtained from the plot of the previous chapter. we will use a VIEWPOINT to read the collector-to-emitter voltage and enable the display of bias currents (using the icon with the large capital I). the Probe Setup under Analysis should enable Do not auto-run Probe. 200 Chapter 4 DC Biasing—BJTs .9 for the network of Figure 4. 4.832 mA versus 0. There is no question. In this case. which closely match those of Example 4. since we are only interested in the dc response.69. The final touch is to move some of the currents displayed to clean up the presentation. Click OK. therefore. The analysis will result in the dc levels appearing in Fig. Recall. The collector-to-emitter voltage is 13. and the collector current is 0. The collector-to-emitter voltage is 13.5 V.69 V 1. and the network is set up for the analysis.7. we will inhibit the display of some bias currents using the icon with the smaller capital I and the diode symbol.

Note the dramatic drop in VC to 0.08 A. The fixed-bias configuration is obviously very beta-sensitive.35 mA.4 mA versus the solution of 2.72 Network of Figure 4. with the collector voltage at 6.71.274 mA versus 2. the collector current at 2.23 A versus 47.13 PSpice Windows 201 .113 V compared to 6. These are a close match with the hand-written solution. The results appear in Fig.9. 4. Figure 4. and the base current at 47.71 Fixed-bias configuration with a of 50.83 V and the significant rise in ID to 5. Let us now test the sensitivity to changes in beta by changing to the default value of 255. 4.9.35 mA.72.Figure 4.998 V versus 6.71 with a of 255. 4. A PSpice analysis of the network will result in the levels appearing in Fig.83 V.

53 12 V IC RC RB 2.73. * 5. 11. (c) RB. 4. Find the saturation current (ICsat) for the fixed-bias configuration of Fig. VC = 6 V + I B = 40 µA VCE β = 80 – 3. Figure 4. 4. Given the BJT transistor characteristics of Fig. VB. (h) What is the dc power dissipated by the device at the operating point? (i) What is the power supplied by VCC? (j) Determine the power dissipated by the resistive elements by taking the difference between the results of parts (h) and (i). 4. (c) . 51. (c) What are the resulting values of ICQ and VCEQ? (d) What is the value of at the operating point? (e) What is the value of defined by the operating point? (f) What is the saturation (ICsat) current for the design? (g) Sketch the resulting fixed-bias configuration. ICQ. 4. (d) RB. determine: IBQ.76: (a) Draw a load line on the characteristics determined by E 21 V and RC 3 k for a fixedbias configuration. 47. VCEQ. Given the information appearing in Fig.75. Figure 4.3 Fixed-Bias Circuit 1.74 Problem 2 Figure 4. determine: (a) IC. 4.PROBLEMS § 4. (b) VCC. Determine the value of RB to establish the resulting operating point. 52.74. (b) Choose an operating point midway between cutoff and saturation.73 Problems 1. VC. 4. For (a) (b) (c) (d) (e) (f) the fixed-bias configuration of Fig. (b) RC. (d) VCE. 202 Chapter 4 DC Biasing—BJTs .75 Problem 3 4.73. VE. determine: (a) IC. Given the information appearing in Fig.

77. determine the following for an emitter-bias configuration if a Q-point is defined at ICQ 4 mA and VCEQ 10 V. VCEQ. (e) VB.76. 51. * 10.79. determine: (a) .4 Emitter-Stabilized Bias Circuit 6. (c) RB. determine: IBQ. VC.2 k .77 Problems 6. 9. (c) RB. 54 Figure 4. Problems Figure 4. (d) Power dissipated by the transistor.79 Problem 8 203 . 11. 10. 4. (c) RB. 20. (e) Power dissipated by the resistor RC.77. (a) RC if VCC 24 V and RE 1. (d) VCE. (b) VCC.76 Problems 5. Given the information provided in Fig. 36 § 4. Figure 4. VB. 4.78. For (a) (b) (c) (d) (e) (f) the emitter-stabilized bias circuit of Fig. 4. ICQ. determine: (a) RC. 24. 4.78 Problem 7 7. Using the characteristics of Fig.Figure 4. 35. Determine the saturation current (ICsat) for the network of Fig. VE. 4. Given the information provided in Fig. 48. 8. (b) at the operating point. (b) RE. 9. 19.

Figure 4. (c) VCC.77. (a) Determine IC and VCE for the network of Fig. 4. 4. § 4. (d) VCE. VCEQ. 20. 13. 18. (c) Determine the magnitude of the percent change in IC and VCE using the following equations: % IC IC(part b) IC(part a) IC(part a) 100%. 55 Figure 4.81.80.5 Voltage-Divider Bias 12. Compare the percent change in IC and VCE for each configuration.73. determine: IBQ. ICQ. For (a) (b) (c) (d) (e) (f) the voltage-divider bias configuration of Fig. 4. 4. VB. 4. 14.82. 24. (c) VB.73. 4. (d) R1. determine: (a) IC. (b) VE. 4. (e) Change to 150 and determine the new value of IC and VCE for the network of Fig.77. determine: (a) IC. 15. VC.82 Problem 14 204 Chapter 4 DC Biasing—BJTs .* 11. 49.81 Problem 13 Figure 4. Given the information provided in Fig. 51. % VCE VCE(part e) VCE(part d) VCE(part d) 100% (g) In each of the above. the magnitude of was increased 50%. % VCE VCE(part b) VCE(part a) VCE(part a) 100% (d) Determine IC and VCE for the network of Fig. Given the information appearing in Fig. VE. (e) VB.80 Problems 12. (f) Determine the magnitude of the percent change in IC and VCE using the following equations: % IC IC(part e) IC(part d) IC(part d) 100%. (b) VE. (b) Change to 135 and determine the new value of IC and VCE for the network of Fig. and comment on which seems to be less sensitive to changes in . (f) R1. 52.

the voltage feedback network of Fig. 50. (d) VE. VCEQ. 4. is the approximate approach a valid analysis technique if Eq. (b) VCE. (c) Determine VB. (a) Determine IC and VCE for the network of Fig.6 DC Bias with Voltage Feedback 22. 4. 56 Figure 4. (d) Find R2 if R1 24 k assuming that RE 10R2. * 19.33) is not satisfied. (b) Determine ICQ.33) is satisfied? 18.15. 4. 21 (d) Compare the solution to part (c) with the solutions obtained for parts (c) and (f ) of Problem 11. Repeat Problem 16 using the exact (Thévenin) approach and compare solutions. Based on the results. * 16. and note whether the assumption of part (d) is correct.84 Problems 22. 4. note the solutions provided in Appendix E. VC. (a) Determine ICQ. (b) Find VE. 4. and determine the new values of IC and VCE for the network of Fig. (4. (c) IB.80. Determine the following for the voltage-divider configuration of Fig. (4. (c) Determine the magnitude of the percent change in IC and VCE using the following equations: % IC IC(part b) IC(part a) IC(part a) 100%. determine: IB.76. determine: IC. * 20. % VCE VCE(part b) VCE(part a) VCE(part a) 100% Figure 4. (4. VC. which configuration is least sensitive to variations in ? * 21.84. VCEQ.83 using the approximate approach if the condition established by Eq. (a) IC. (b) Change to 120 (50% increase). (f) Test Eq. (a) Repeat parts (a) through (e) of Problem 20 for the network of Fig. Determine the saturation current (ICsat) for the network of Fig. (b) What general conclusions can be made about networks in which the condition RE 10R2 is satisfied and the quantities IC and VCE are to be determined in response to a change in ? § 4.33). (a) Using the characteristics of Fig. VE. Figure 4.83 Problems 16.83. (e) Based on the results of part (d). (4.85 Problem 23 Problems 205 . For (a) (b) (c) 23. 4. and IBQ for the network of Problem 12 (Fig. 4. and IBQ using the exact approach. 4. (c) Compare solutions and comment on whether the difference is sufficiently large to require standing by Eq. (e) VB. Use VCC 24 V and RC 3RE. IC. Change to 180 in part (b).33) when determining which approach to employ.80) using the approximate approach even though the condition established by Eq.80. * 17. 17. (e) Calculate at the Q-point. (4.85. If not performed. determine RC and RE for a voltage-divider network having a Q-point of ICQ 5 mA and VCEQ 8 V.80. 4.33) is satisfied. For (a) (b) (c) (d) the collector feedback configuration of Fig. VCE.

Given VB (a) VE. * 26.87 using the 1-M tentiometer.88 Problem 26 § 4. % VCE VCE(part b) VCE(part a) VCE(part a) 100% (d) Compare the results of part (c) with those of Problems 11(c). IC. and 20(c).* 24. and calculate the new levels of IC and VCE. Figure 4. (d) VCE. 4. 4. 11(f ). (c) . Figure 4.90. Given VC (a) IB. 4. For (a) (b) (c) (d) 8 V for the network of Fig. determine: po- (f) . VC.88. 4 V for the network of Fig. (b) Change to 135 (50% increase).86. (c) VC.86 Problem 24 Figure 4. (b) IC. Determine the range of possible values for VC for the network of Fig. (b) IC. (e) IB. (d) VCE. 4.89 Problem 27 Figure 4. determine: the network of Fig.7 Miscellaneous Bias Configurations 27. determine: IB. How does the collector-feedback network stack up against the other configurations in sensitivity to changes in ? 25. 4.90 Problem 28 206 Chapter 4 DC Biasing—BJTs . VCE. (a) Determine the level of IC and VCE for the network of Fig. * 28.89.87 Problem 25 Figure 4. (c) Determine the magnitude of the percent change in IC and VCE using the following equations: % IC IC(part b) IC(part a) IC(part a) 100%.

The available supply is 28 V. determine: IB. determine the appearance of the output waveform for the network of Fig. § 4. determine: (a) IE. IBmax. (4. Determine RC and RB for a fixed-bias configuration if VCC with VCEQ 6 V. Design an emitter-stabilized network at ICQ 2 ICsat and VCEQ 10 mA.91.5 mA VCC.33) should also be met to provide a high stability factor.* 29. and determine IB. 4. Determine the collector-to-emitter resistance at saturation and cutoff. 4. * 31. Using the characteristics of Fig.93 Problem 31 § 4.76. and RC 4RE. 4.95 Problem 37 Problems 207 .8 Design Operations 32. 1 33. design a voltage-divider configuration to have a saturation level of 10 mA and a Q-point one-half the distance between cutoff and saturation. Use standard values. VE. The condition established by Eq. VCE.4 kΩ Vo 5V RB Vi 5V RC Vo β = 100 Figure 4.94. and an operating point of ICQ 4 mA and VCEQ 8 V.92. Determine the level of VE and IE for the network of Fig. * 37. Choose VE 1 VCC. and ICsat when Vi 10 V. * 35. Use standard val8 ues. (c) VCE. 4.76. 12 V. Use standard values.9 Transistor Switching Networks * 36. ICsat 34.93.2 kΩ – IE VCE + VC 1. 10 V Vi 10 V Vi Vi 0V t 0V t 180 kΩ 2. Design the transistor inverter of Fig. Using the characteristics of Fig.92 Problem 30 Figure 4. Use standard values.8 kΩ 10 V Figure 4. 120. Use a level of IB equal to 120% of IBmax and standard resistor values. 4. (b) VC. 4. IC. For (a) (b) (c) (d) the network of Fig. * 30. Design a voltage-divider bias network using a supply of 24 V. and VE is to be one-fifth of VCC. For the network of Fig. Use VCC 20 V. 4.95 to operate with a saturation current of 8 mA using a transistor with a beta of 100. 1 2 80. Include the effects of VCEsat.94 Problem 36 Figure 4. and ICQ 2. – 8V 2. a transistor with a beta of 110.91 Problem 29 Figure 4.

determine ton and toff at a current of 2 mA.38. the levels obtained reflect a very specific problem in each case.56 and compare results. The measurements appearing in Fig. 4.23c.2 kΩ (a) (b) Figure 4. The measurements of Fig. 3.96 all reveal that the network is not functioning correctly.64 V β = 100 4V 18 kΩ 1.10 Troubleshooting Techniques * 39.4 V 3. 4.98: Does VC increase or decrease if RB is increased? Does IC increase or decrease if is reduced? What happens to the saturation current if is increased? Does the collector current increase or decrease if VCC is reduced? What happens to VCE if the transistor is replaced by one with smaller ? DC Biasing—BJTs 208 Chapter 4 . 16 V 16 V 91 kΩ VB = 9.98 Problem 41 41. List as many reasons as you can for the measurements obtained. (a) Using the characteristics of Fig. For (a) (b) (c) (d) (e) the circuit of Fig.96 Problem 39 * 40.2. Figure 4. How have ton and toff changed with increase in collector current? (c) For parts (a) and (b). (b) Repeat part (a) at a current of 10 mA.6 kΩ β = 100 2. 4.97 reveal that the networks are not operating properly. Be specific in describing why the levels obtained reflect a problem with the expected network behavior. In other words.6 kΩ 91 kΩ 3.2 kΩ 18 kΩ 1. sketch the pulse waveform of Fig. Note the use of log scales and the possible need to refer to Section 11. § 4.97 Problem 40 Figure 4. 4.

Answer the following questions about the circuit of Fig.99 Problem 42 * 43. 4. Answer the following questions about the circuit of Fig. 4.11 PNP Transistors 44.102 Problem 45 Figure 4. Determine VC. (a) What happens to the voltage VC if the resistor RB is open? (b) What should happen to VCE if increases due to temperature? (c) How will VE be affected when replacing the collector resistor with one whose resistance is at the lower end of the tolerance range? (d) If the transistor collector connection becomes open. VCE.101.42. Determine IE and VC for the network of Fig.101 Problem 44 Figure 4.103. 45.100. and IC for the network of Fig.99. 46. 4. 4. Determine VC and IB for the network of Fig. 4. (a) What happens to the voltage VC if the transistor is replaced by one having a larger value of ? (b) What happens to the voltage VCE if the ground leg of resistor RB2 opens (does not connect to ground)? (c) What happens to IC if the supply voltage is low? (d) What voltage VCE would occur if the transistor base–emitter junction fails by becoming open? (e) What voltage VCE would result if the transistor base–emitter junction fails by becoming a short? Figure 4. what will happen to VE? (e) What might cause VCE to become nearly 18 V? Figure 4.102. Figure 4.100 Problem 43 § 4.103 Problem 46 Problems 209 .

S(VBE). *Please Note: Asterisks indicate more difficult problems. VBE drops from 0. (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0.12 Bias Stabilization 47. S(VBE). (c) Which factors of parts (a) and (b) seem to have the most influence on the stability of the system. For (a) (b) (c) the network of Fig.7 to 0. 4. VBE drops from 0. 4. the network of Fig.13 PSpice Windows 53.5 V. (c) S( ) using T1 as the temperature at which the parameter values are specified and (T2) as 25% more than (T1). determine: S(ICO). (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0. * 49.2 to 10 A.84. 55. Repeat Problem 53 for the network of Fig.80. The results for Exercises 47 and 49 can be found in Appendix E. and increases 25%.§ 4. VCE. (a) Compare the levels of stability for the fixed-bias configuration of Problem 47. S( ) using T1 as the temperature at which the parameter values are specified and (T2) as 25% more than (T1). Repeat Problem 53 for the network of Fig.5 V. 4. For (a) (b) (c) * 50. band IB. (a) S(ICO).5 V.7 to 0. For (a) (b) (c) * 51. S( ) using T1 as the temperature at which the parameter values are specified and (T2) as 25% more than (T1). 54. (b) S(VBE).73. VBE drops from 0. Can any general conclusions be derived from the results? * 52. or is there no general pattern to the results? § 4. and increases 25%.5 V.2 to 10 A. the network of Fig.7 to 0. S( ) using T1 as the temperature at which the parameter values are specified and (T2) as 25% more than (T1). Compare the relative values of stability for Problems 47 through 50. (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0. 4. (d) Determine the net change in IC if a change in operating conditions results in ICO increasing from 0. 4.2 to 10 A. determine: S(ICO). 4.89. and increases 25%. and increases 25%. (b) Compare the levels of stability for the voltage-divider configuration of Problem 49. VBE drops from 0. 56. Repeat Problem 53 for the network of Fig. 4. determine IC. determine: S(ICO).2 to 10 A.73. That is.77.77. 210 Chapter 4 DC Biasing—BJTs .80. Determine the following for the network of Fig. * 48.7 to 0. S(VBE). Perform a PSpice analysis of the network of Fig. 4.

the current IC in Fig.1a is a direct function of the level of IB. it is important to keep in mind that the BJT transistor is a bipolar device—the prefix bi. to a large extent. those of the BJT transistor described in Chapters 3 and 4. However. there are also many similarities that will be pointed out in the sections to follow. For the FET the current I will be a function of the voltage VGS applied to the input circuit as shown in Fig. The primary difference between the two types of transistors is the fact that the BJT transistor is a current-controlled device as depicted in Fig. 5. while the JFET transistor is a voltage-controlled device as shown in Fig.1a. 5. electrons and holes. 5. For the FET an electric field is established by the charges present that will control the conduction path of the output 211 . We are all familiar with the ability of a permanent magnet to draw metal filings to the magnet without the need for actual contact.CHAPTER Field-Effect Transistors 5. In other words. Just as there are npn and pnp bipolar transistors.1 (a) Current-controlled and (b) voltage-controlled amplifiers.1 INTRODUCTION The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match. The FET is a unipolar device depending solely on either electron (n-channel) or hole (p-channel) conduction. 5.revealing that the conduction level is a function of two charge carriers. there are n-channel and p-channel field-effect transistors. The magnetic field of the permanent magnet has enveloped the filings and attracted them to the magnet through an effort on the part of the magnetic flux lines to be as short as possible.1b.1b. Although there are important differences between the two types of devices. In each case the current of the output circuit is being controlled by a parameter of the input circuit—in one case a current level and in the other an applied voltage. 5 Figure 5. The term field-effect in the chosen name deserves some explanation.

Once the FET construction and characteristics have been introduced. Ian Munro Ross (front) and G. However. Its thermal stability and other general characteristics make it extremely popular in computer circuit design. In other words. On the other hand. For the JFET transistor the n-channel device will appear as the prominent device. the JFET is a three-terminal device with one terminal capable of controlling the current between the other two. The result is a depletion region at each junction as shown in Fig. Chapter 5 Field-Effect Transistors 212 .2 CONSTRUCTION AND CHARACTERISTICS OF JFETs As indicated earlier. The two p-type materials are connected together and to the gate (G) terminal. Dacey jointly developed an experimental procedure for measuring the characteristics of a field-effect transistor in 1955. the BJT transistor has a much higher sensitivity to changes in the applied signal. There is a natural tendency when introducing a second device with a range of applications similar to one already introduced to compare some of the general characteristics of one versus the other.Drs. The MOSFET category is further broken down into depletion and enhancement types. The basic construction of the n-channel JFET is shown in Fig. In the absence of any applied potentials the JFET has two p-n junctions under no-bias conditions. 5. making them particularly useful in integrated-circuit (IC) chips. (Courtesy of AT&T Archives. therefore. the variation in output current is typically a great deal more for BJTs than FETs for the same change in applied voltage. it must be handled with care (to be discussed in a later section). In our discussion of the BJT transistor the npn transistor was employed through the major part of the analysis and design sections. At a level of 1 to several hundred megohms it far exceeds the typical input resistance levels of the BJT transistor configurations—a very important characteristic in the design of linear ac amplifier systems. can make them more sensitive to handling than BJTs. Illinois PhD California Institute of Technology Director of Solid-State Electronics Research at Bell Labs Vice President. FETs are more temperature stable than BJTs. Dacey Born: Chicago. Cambridge University President emeritus of AT&T Bell Labs Fellow—IEEE. The top of the n-type channel is connected through an ohmic contact to a terminal referred to as the drain (D). 5. In general. while the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S). The MOSFET transistor has become one of the most important devices used in the design and construction of integrated circuits for digital computers. and FETs are usually smaller in construction than BJTs. the drain and source are connected to the ends of the n-type channel and the gate to the two layers of p-type material. Ross Born: Southport. as a discrete element in a typical top-hat container. the biasing arrangements will be covered in Chapter 6. typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. which are both described. however. Note that the major part of the structure is the n-type material that forms the channel between the embedded layers of p-type material. The construction characteristics of some FETs. One of the most important characteristics of the FET is its high input impedance. Member of the National Science Board Chairman—National Advisory Committee on Semiconductors Dr. Eta Kappa Nu circuit without the need for direct contact between the controlling and controlled quantities. with paragraphs and sections devoted to the impact of using a p-channel JFET. C. with a section devoted to the impact of using a pnp transistor. England PhD Gonville and Caius College. Tau Beta Pi.2. Research at Sandia Corporation Member IRE.2 that resembles the same region of a diode under no-bias conditions. The analysis performed in Chapter 4 using BJT transistors will prove helpful in the derivation of the important equations and understanding the results obtained for FET circuits. 5. In essence. For this reason. Recall also that a depletion region is that region void of free carriers and therefore unable to support conduction through the region. Two types of FETs will be introduced in this chapter: the junction field-effect transistor (JFET) and the metal-oxide-semiconductor field-effect transistor (MOSFET).) Dr.

5.2 Construction and Characteristics of JFETs 213 . The “gate. 5. The instant the voltage VDD ( VDS) is applied. but the water analogy of Fig. 5.” through an applied signal (potential).4. VGS 0 V.4. controls the flow of water (charge) to the “drain. 5.4 JFET in the VGS 0 V and VDS 0 V. The path of charge flow clearly reveals that the drain and source currents are equivalent (ID IS). 5.” The drain and source terminals are at opposite ends of the n-channel as introduced in Fig. The source of water pressure can be likened to the applied voltage from drain to source that will establish a flow of water (electrons) from the spigot (source). the electrons will be drawn to the drain terminal. the flow of charge is relatively uninhibited and limited solely by the resistance of the n-channel between drain and source.2 Junction field-effect transistor (JFET). a positive voltage VDS has been applied across the channel and the gate has been connected directly to the source to establish the condition VGS 0 V.2 because the terminology is defined for electron flow. In Fig. establishing the conventional current ID with the defined direction of Fig. The result is a gate and source terminal at the same potential and a depletion region in the low end of each p-material similar to the distribution of the no-bias conditions of Fig. VDS Some Positive Value Figure 5. Under the conditions appearing in Fig.3 does provide a sense for the JFET control at the gate terminal and the appropriateness of the terminology applied to the terminals of the device. Analogies are seldom perfect and at times can be misleading.2.Figure 5. 5.4.3 Water analogy for the JFET control mechanism. ID D Depletion region e e G + n-channel p n e e p VDS VDD + VG S = 0 V – S IS – Figure 5. 5.

The fact that ID does not drop off at pinch-off and maintains the saturation level indicated in Fig. The reason for the change in width of the region is best described through the help of Fig. this is hardly the case — ID maintains a saturation level defined as IDSS in Fig. As shown in Fig.5 V.5 Varying reverse-bias potentials across the p-n junction of an n-channel JFET. the wider the depletion region—hence the distribution of the depletion region as shown in Fig. causing a noticeable reduction in the channel width. 5. 5. 5. 5. Figure 5.Figure 5. the higher the resistance. The current ID will establish the voltage levels through the channel as indicated on the same figure. suggesting that the resistance is approaching “infinite” ohms in the horizontal region. 5. It is important to note that the depletion region is wider near the top of both ptype materials. the current will increase as determined by Ohm’s law and the plot of ID versus VDS will appear as shown in Fig.4 will widen. Figure 5. with a current of very high density.5.6.6 ID versus VDS for VGS 0 V. The reduced path of conduction causes the resistance to increase and the curve in the graph of Fig.6 to occur. 5. Recall from the discussion of the diode operation that the greater the applied reverse bias. In actuality. As the voltage VDS is increased from 0 to a few volts. a condition referred to as pinch-off will result. however. Assuming a uniform resistance in the n-channel.6 is verified by the following fact: The absence of a drain current would remove the possibility of different potential levels through the n-channel material to establish the varying levels of reverse bias along the p-n junction. the depletion regions of Fig. 5. The result is that the upper region of the p-type material will be reversebiased by about 1. 214 Chapter 5 Field-Effect Transistors .5 V.6. VDS VP).6. the term pinch-off is a misnomer in that it suggests the current ID is pinched off and drops to 0 A.7.7 Pinch-off (VGS 0 V. As VDS increases and approaches a level referred to as VP in Fig. 5. 5.6.5.5. 5. The more horizontal the curve. The relative straightness of the plot reveals that for the region of low values of VDS. 5. If VDS is increased to a level where it appears that the two depletion regions would “touch” as shown in Fig. with the lower region only reverse-biased by 0. 5.6. The fact that the p-n junction is reverse-biased for the length of the channel results in a gate current of zero amperes as shown in the same figure. the resistance is essentially constant. The level of VDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP as shown in Fig. the resistance of the channel can be broken down to the divisions appearing in Fig. In reality a very small channel still exists. The fact that IG 0 A is an important characteristic of the JFET. The result would be a loss of the depletion region distribution that caused pinch-off in the first place.

Note in Fig. VGS 0V Figure 5. 5. The choice of notation IDSS is derived from the fact that it is the Drain-to-Source current with a Short-circuit connection from gate to source.8. In Fig. Just as various curves for IC versus VCE were established for different levels of IB for the BJT transistor.2 Construction and Characteristics of JFETs 215 . For the n-channel device the controlling voltage VGS is made more and more negative from its VGS 0 V level.10 how the pinchoff voltage continues to drop in a parabolic manner as VGS becomes more and more VP will be sufficiently negative to establish negative. the current is fixed at ID IDSS. once VDS VP the JFET has the characteristics of a current source.6 are affected by changes in the level of VGS.9 Application of a negative voltage to the gate of a JFET. The effect of the applied negative-bias VGS is to establish depletion regions similar to those obtained with VGS 0 V but at lower levels of VDS.As VDS is increased beyond VP.8 Current source equivalent for VGS 0 V. the region of close encounter between the two depletion regions will increase in length along the channel. therefore. 5. 5. the result of applying a negative bias to the gate is to reach 1 V. 5. In essence. 5. The next few paragraphs will describe how the characteristics of Fig. 5. but the voltage VDS (for levels VP) is determined by the applied load.” In summary: ID D + G IG = 0 A p n 1V p VDS > 0V + VG S = –1 V – + S IS – – Figure 5. denoted VGS. As we continue to investigate the characteristics of the device we will find that: IDSS is the maximum drain current for a JFET and is defined by the conditions VGS 0 V and VDS |VP|.9 a negative voltage of 1 V has been applied between the gate and source terminals for a low level of VDS.6 that VGS 0 V for the entire length of the curve. VDS VP. As shown in Fig. 5. is the controlling voltage of the JFET. the gate terminal will be set at lower and lower potential levels as compared to the source. Note also on Fig. but the level of ID remains essentially the same. the saturation level at a lower level of VDS as shown in Fig. The voltage from gate to source. and for all practical purposes the device has been “turned off. Eventually. Therefore. VGS when VGS a saturation level that is essentially 0 mA.10 for VGS The resulting saturation level for ID has been reduced and in fact will continue to decrease as VGS is made more and more negative. In other words. curves of ID versus VDS for various levels of VGS can be developed for the JFET.

and n-type materials as shown in Fig. In this region the JFET can actually be employed as a variable resistor (possibly for an automatic gain control system) whose resistance is controlled by the applied gate-to-source voltage. Voltage-Controlled Resistor The region to the left of the pinch-off locus of Fig. but with a reversal of the p.ID (mA) Ohmic Region IDSS 8 7 6 5 4 3 2 1 0 Locus of pinch-off values Saturation Region VGS = 0 V VGS = –1 V VGS = –2 V VGS = –3 V VGS = – 4 V = VP 10 5 VP (for VGS = 0 V) 15 20 25 VDS (V) Figure 5. On most specification sheets the pinch-off voltage is specified as VGS(off) rather than VP. The following equation will provide a good first approximation to the resistance level in terms of the applied voltage VGS.10 is referred to as the ohmic or voltage-controlled resistance region. or linear amplification region.10 n-Channel JFET characteristics with IDSS 8 mA and VP 4 V. with VP being a negative voltage for n-channel devices and a positive voltage for p-channel JFETs. 216 Chapter 5 Field-Effect Transistors .11. As VGS becomes more and more negative.2. The region to the right of the pinch-off locus of Fig. (5. 5.1) For an n-channel JFET with ro equal to 10 k (VGS 0 V. VP 3 V. 6 V). 5. 5. 5.10 that the slope of each curve and therefore the resistance of the device between drain and source for VDS VP is a function of the applied voltage VGS. Eq. 5. rd (1 ro VGS/VP)2 (5. the slope of each curve becomes more and more horizontal. will result in 40 k at VGS p-Channel Devices The p-channel JFET is constructed in exactly the same manner as the n-channel device of Fig. saturation. corresponding with an increasing resistance level. A specification sheet will be reviewed later in the chapter when the primary elements of concern have been introduced. Note in Fig.10 is the region typically employed in linear amplifiers (amplifiers with minimum distortion of the applied signal) and is commonly referred to as the constant-current. The level of VGS that results in ID 0 mA is defined by VGS VP.1) where ro is the resistance with VGS 0 V and rd the resistance at a particular level of VGS.

For the p-channel device.12 p-Channel JFET characteristics with IDSS 6 mA and VP Note at high levels of VDS that the curves suddenly rise to levels that seem unbounded. 5. as are the actual polarities for the voltages VGS and VDS. they do occur for the n-channel device if sufficient voltage is applied. Figure 5.11 p-Channel JFET.2 Construction and Characteristics of JFETs + – Figure 5. Although not appearing in Fig. The vertical rise is an indication that breakdown has occurred and the current through the channel (in the same direction as normally encountered) is now limited solely by the external circuit. Do not let the minus has an IDSS of 6 mA and a pinch-off voltage of VGS signs for VDS confuse you.12. 5. + – 217 . This region can be avoided if the level of VDSmax is noted on the specification sheet and the design is such that the actual level of VDS is less than this value for all values of VGS. They simply indicate that the source is at a higher potential than the drain.D + + G IG = 0 A + ID + n + VGG p + n VDS VDD + VG S = + VGG – S IS – The defined current directions are reversed. 6 V. which 6 V. the channel will be constricted by increasing positive voltages from gate to source and the double-subscript notation for VDS will result in negative voltages for VDS on the characteristics of Fig. 5.10 for the n-channel device.

Note that the arrow is pointing in for the n-channel device of Fig.13. ID IDSS. 5.13a to represent the direction in which IG would flow if the p-n junction were forward-biased. 5.14c.14 (a) VGS 0 V. Figure 5. as reviewed by Fig.14b. For p-channel JFETs a similar list can be developed. 5. (c) ID exists between 0 A and IDSS for VGS less than or equal to 0 V and greater than the pinch-off level.Symbols The graphic symbols for the n-channel and p-channel JFETs are provided in Fig. (b) p-channel. 5. Summary A number of important parameters and relationships were introduced in this section. For the p-channel device (Fig.13b) the only difference in the symbol is the direction of the arrow.14a. A few that will surface frequently in the analysis to follow in this chapter and the next for n-channel JFETs include the following: The maximum current is defined as IDSS and occurs when VGS 0 V and VDS |VP| as shown in Fig. the drain current is 0 A (ID 0 A) as appearing in Fig. . respectively. 5. D G VDD ≥ VP VG S = – VGG G D VG S = 0 V VG S – S (a) VP ≥ VG G G ≥ 0V – VG G + VG S + – 218 Chapter 5 Field-Effect Transistors – D 0 mA ≥ ID > IDSS ID S (c) + ID = IDSS + – + VG S VG G – + VG G ID = 0 A VDD S ≥ VP (b) VDD Figure 5.13 JFET symbols: (a) n-channel. For all levels of VGS between 0 V and the pinch-off level. 5. For gate-to-source voltages VGS less than (more negative than) the pinch-off level. (b) cutoff (ID 0 A) VGS less than the pinch-off level. the current ID will range between IDSS and 0 A.

5. (Courtesy of AT&T Archives. therefore: The transfer characteristics defined by Shockley’s equation are unaffected by the network in which the device is employed. producing a curve that grows exponentially with decreasing magnitudes of VGS. control variable ↓ IB (5. 1936 Head. The transfer curve can be obtained using Shockley’s equation or from the output characteristics of Fig. this linear relationship does not exist between the output and input quantities of a JFET. a graphical rather than mathematical approach will in general be more direct and easier to apply.2) a linear relationship exists between IC and IB. 5.15 two graphs are provided. VGS = VP Figure 5. with the vertical ID (mA) 10 10 9 9 IDSS 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 VGS (V) – 4 –3 –2 –1 0 0 5 10 15 20 25 VGS = –2 V VGS = –3 V VGS = – 4 V VDS VGS = –1 V IDSS VGS = 0 V ID (mA) William Bradford Shockley (1910–1989). co-inventor of the first transistor and formulator of the “field-effect” theory employed in the development of the transistor and FET. 5.3 TRANSFER CHARACTERISTICS Derivation For the BJT transistor the output current IC and input controlling current IB were related by beta. but the transfer curve defined by Eq. For the dc analysis to be performed in Chapter 6. (5. will require a plot of Eq. however.3) to represent the device and a plot of the network equation relating the same variables. The graphical approach. The network equation may change along with the intersection between the two curves. which was considered constant for the analysis to be performed. England PhD Harvard.3 Transfer Characteristics 219 . Shockley Transistor Corp. Double the level of IB and IC will increase by a factor of two also. It is important to keep in mind when applying the graphical approach that the device characteristics will be unaffected by the network in which the device is employed. Brattain and Bardeen ID = 0 mA.3) is unaffected.15 Obtaining the transfer curve from the drain characteristics.) Born: London. The relationship between ID and VGS is defined by Shockley’s equation: control variable ↓ 2 VGS (5. The solution is defined by the point of intersection of the two curves. In equation form. Unfortunately. Poniatoff Professor of Engineering Science at Stanford University Nobel Prize in physics in 1956 with Drs.10.2) IC f(IB) ↑ constant In Eq.5. Transistor Physics Department–Bell Laboratories President.3) ID IDSS 1 VP ↑ ↑ constants The squared term of the equation will result in a nonlinear relationship between ID and VGS. In Fig. (5. In general. (5.

When VGS VP 4 V. The levels of IDSS and VP define the limits of the curve on both axes and leave only the necessity of finding a few intermediate plot points.3) given simply the values of IDSS and VP. while the other is ID versus VGS. another point on the transfer curve can be located.15. (5.3): ID IDSS 1 IDSS 1 and 220 ID Field-Effect Transistors VGS VP 0 VP 0V 2 2 IDSS(1 0)2 (5. the ployed and the ohmic region ignored. There is therefore a direct “transfer” from input to output variables when employing the curve to the left of Fig. In review: When VGS 0 V. The point of intersection on the ID versus VGS curve will be as shown since the vertical axis is defined as VGS 0 V.15 is best demonstrated by examining a few specific levels of one variable and finding the resulting level of the other as follows: Substituting VGS 0 V gives Eq. If the relationship were linear. The next few paragraphs will introduce a quick. Note 1 V on the bottom axis of the transfer curve with ID 4.scaling in milliamperes for each graph. That is: When VGS VP. 5. it is important to realize that the drain characteristics relate one output (or drain) quantity to another output (or drain) quantity—both axes are defined by variables in the same region of the device characteristics. Compare the spacing between VGS 0 V and VGS 3 V and pinch-off.15 decreases noticeably as VGS becomes more and more neg1 V to that between ative. Applying Shockley’s Equation The transfer curve of Fig. 5. The validity of Eq. 5.3) as a source of the transfer curve of Fig. a parabolic curve will result because the vertical spacing between steps of VGS on the drain characteristics of Fig. One is a plot of ID versus VDS. The transfer characteristics are a plot of an output (or drain) current versus an input-controlling quantity. Before continuing. Using the drain characteristics on the right of the “y” axis. Continuing with VGS transfer curve can be completed. The change in VGS is the same. ID 0 mA. The resulting current level for both graphs is IDSS. 5.15. the plot of ID versus VGS would result in a straight line between IDSS and VP. but the resulting change VGS in ID is quite different. efficient method of plotting ID versus VGS given only the levels of IDSS and VP and Shockley’s equation. the drain current is zero milliamperes. 1 V curve to the ID axis and then If a horizontal line is drawn from the VGS extended to the other axis.5 mA.15 can also be obtained directly from Shockley’s equation (5. 5. Note in that VGS the definition of ID at VGS 0 V and 1 V that the saturation levels of ID are em2 V and 3 V. However. It is the transfer curve of ID versus VGS that will receive extended use in the analysis of Chapter 6 and not the drain characteristics of Fig. defining another point on the transfer curve. ID IDSS. a horizontal line can be drawn from the saturation region of the curve denoted VGS 0 V to the ID axis. (5.4) IDSS | VGS Chapter 5 .

as determined by Shockley’s equation: ID IDSS 1 IDSS 1 VGS VP VP/2 VP 2 2 IDSS 1 1 2 2 IDSS(0.75)2 as shown in Fig.25) 1V as substituted in the above calculation and verified by Fig.6) Let us test Eq.15. The format of Eq. (5. 5. 5. most efficient manner while maintaining an acceptable degree of accuracy.5 mA 8 mA 0.6) by finding the level of VGS that will result in a drain current of 4.15.3 Transfer Characteristics 221 . it would be quite advantageous to have a shorthand method for plotting the curve in the quickest. Note the care taken with the negative signs for VGS and VP in the calculations above. the resulting level of ID will be the following.25) 5. if we substitute VGS ID IDSS 1 8 mA 1 VGS VP 2 1V 4V 8 mA(0. The derivation is quite straight forward and will result in VGS VP 1 ID IDSS (5.5 mA for the device with the characteristics of Fig. by using basic algebra we can obtain [from Eq. VGS 4V 1 4 V(1 4 V(0.75) Shorthand Method Since the transfer curve must be plotted so frequently.5625) 4 V(1 0. If we specify VGS to be one-half the pinch-off value VP. (5. Conversely.5625) 4. 5.5) 1 V. 5.5)2 IDSS (0. 4. It should be obvious from the above that given IDSS and VP (as is normally provided on specification sheets) the level of ID can be found for any level of VGS.3)] an equation for the resulting level of VGS for a given level of ID.Substituting VGS VP yields ID IDSS 1 IDSS(1 ID 0 A VGS VP VP 1)2 VP 2 IDSS (0) (5. For the drain characteristics of Fig.5 mA 2 8 mA 1 1 4 2 8 mA(0. (5. The loss of one sign would result in a totally erroneous result.15.3) is such that specific levels of VGS will result in levels of ID that can be memorized to provide the plot points needed to sketch the transfer curve.15.

6). 5. It is a general equation for any level of VP as long as VGS VP/2.293) VP 1 and 0. (5.and ID IDSS 4 VGS VP/2 (5.7) is not for a particular level of VP. (5. At ID IDSS /2 12 mA/2 6 mA the gate-to-source 1.8) Additional points can be determined. Solution Two plot points are defined by IDSS and ID 12 mA 0 mA and and VGS VGS 0V VP At VGS VP /2 6 V/2 3 V the drain current will be determined by ID IDSS /4 12 mA/4 3 mA. All four plot points voltage is determined by VGS 0.15.5 VP VP ID IDSS IDSS/2 IDSS/4 0 mA EXAMPLE 5. we find that VGS VP 1 ID IDSS IDSS/2 IDSS VGS VP (1 0.3VP|ID IDSS /2 (5.3 VP 0.1 Sketch the transfer curve defined by IDSS 12 mA and VP 6 V. 222 Chapter 5 Field-Effect Transistors .3VP 0.3( 6 V) are well defined on Fig.8 V. a maximum of four plot points are used to sketch the transfer curves. VGS VP/2 If we choose ID IDSS/2 and substitute into Eq. On most occasions using just the plot point defined by VGS VP /2 and the axis intersections at IDSS and VP will provide a curve accurate enough for most calculations. TABLE 5. 5.16 with the complete transfer curve.1 VGS versus ID Using Shockley’s Equation VGS 0 0. The result specifies that the drain current will always be one-fourth of the saturation level IDSS as long as the gate-to-source voltage is one-half the pinch-off value.1.5) VP (0. Note the level of ID for 4 V/2 2 V in Fig.7) Now it is important to realize that Eq. In fact. in the analysis of Chapter 6. but the transfer curve can be sketched to a satisfactory level of accuracy simply using the four plot points defined above and reviewed in Table 5.

Sketch the transfer curve for a p-channel device with IDSS 4 mA and VP 3 V.Figure 5. both VP and VGS will be positive and the curve will be the mirror image of the transfer curve obtained with an n-channel and the same limiting values.3VP 0.3(3 V) 0. EXAMPLE 5.2 Solution At VGS VP /2 3 V/2 1.17 along with the points defined by IDSS and VP. there are a few fundamental parameters that will be provided by all manufacturers. At ID IDSS/2 4 mA/2 2 mA.16 Transfer curve for Example 5. 5. The specification sheet for the 2N5457 n-channel JFET as provided by Motorola is provided as Fig. For p-channel devices Shockley’s equation (5. Figure 5. A few of the most important are discussed in the following paragraphs.18.3) can still be applied exactly as it appears. 5.2. 5. Both plot points appear in Fig. In this case.1.4 SPECIFICATION SHEETS ( JFETs) Although the general content of specification sheets may vary from the absolute minimum to an extensive display of graphs and charts.5 V. ID IDSS /4 4 mA/4 1 mA. 5. VGS 0.9 V.17 Transfer curve for the p-channel device of Example 5.4 Specification Sheets (JFETs) 223 .

The specified maximum levels for VDS and VDG must not be exceeded at any point in the design operation of the device. The applied source VDD can exceed these levels. Any good design will 224 Chapter 5 Field-Effect Transistors . but the actual level of voltage between these terminals must never exceed the level specified.18 2N5457 Motorola n-channel JFET.Figure 5. with the maximum voltages between specific terminals. and the maximum power dissipation level of the device. maximum current levels. Maximum Ratings The maximum rating list usually appears at the beginning of the specification sheet.

5. The derating factor is discussed in detail in Chapter 3. The fact that both will vary from device to device with the same nameplate identification must be considered in the design process. The total device dissipation at 25°C (room temperature) is the maximum power the device can dissipate under normal operating conditions and is defined by PD VDSID (5.4 Specification Sheets (JFETs) 225 .82 mW for each increase in temperature of 1°C above 25°C. In this case VP VGS(off) has a range from 0. The terminal identification is also provided directly under the figure.19 with its terminal identification. as shown in Fig. and VDSmax specifies the maximum value for this paFigure 5.18. 5.9) Note the similarity in format with the maximum power dissipation equation for the BJT transistor. Operating Region The specification sheet and the curve defined by the pinch-off levels at each level of VGS define the region of operation for linear amplification on the drain characteristics as shown in Fig.20 Normal operating region for linear amplifier design.0 V and IDSS from 1 to 5 mA.82 mW/°C rating reveals that the dissipation rating decreases by 2.5 to 6. Electrical Characteristics The electrical characteristics include the level of VP in the OFF CHARACTERISTICS and IDSS in the ON CHARACTERISTICS. The small-signal characteristics are discussed in Chapter 9. but for the moment recognize that the 2. Although normally designed to operate with IG 0 mA. The term reverse in VGSR defines the maximum voltage with the source positive with respect to the gate (as normally biased for an n-channel device) before breakdown will occur. The ohmic region defines the minimum permissible values of VDS at each level of VGS. if forced to accept a gate current it could withstand 10 mA before damage would occur. 5. Case Construction and Terminal Identification This particular JFET has the appearance provided on the specification sheet of Fig. The other quantities are defined under conditions appearing in parentheses. On some specification sheets it is referred to as BVDSS —the Breakdown Voltage with the Drain-Source Shorted (VDS 0 V).19 Top-hat container and terminal identification for a p-channel JFET.try to avoid these levels by a good margin of safety. 5. Figure 5.20. JFETs are also available in top-hat containers.

VGS = –1. The resulting shaded region is the normal operating region for amplifier design. 5.5 V gm 2m per div. However. 5.5 V.9 V) 500 mV per step. The level of VP can be estimated by noting the VGS value of the bottom curve and taking into account the shrinking distance between curves as VGS becomes more and more negative.5 V. It as they approach the cutoff condition. However. and finally 2 V.5 INSTRUMENTATION Recall from Chapter 3 that hand-held instruments are available to measure the level of dc for the BJT transistor.5 V/step). and perhaps VP VGS = 0 V I DSS ≅ 9 mA Vertical Sens.5 V Horizontal Sens. revealing that the top curve is defined by VGS 0 V and the next curve down 0. 1V per div. VGS = –1 V I DSS = 4. The step voltage is 500 mV/step (0. The saturation current IDSS is the maximum drain current. In this case. 226 Chapter 5 Field-Effect Transistors . and the maximum power dissipation level defines the curve drawn in the same manner as described for BJT transistors. The vertical scale (in milliamperes) and the horizontal scale (in volts) have been set to provide a full display of the characteristics.5 V for the n-channel device. Using the same step voltage the next curve is 1 V. each vertical division (in centimeters) reflects a 1-mA change in IC while each horizontal division has a value of 1 V. 1 mA div VGS = –2 V VP ≅ − 3 V 1V div Figure 5. By drawing a line from the top curve over to the ID axis. 5. the curve tracer introduced for the BJT transistor can also display the drain characteristics of the JFET transistor through a proper setting of the various controls.21.5 mA 2 (VGS = – 0.21 Drain characteristics for a 2N4416 JFET transistor as displayed on a curve tracer.21. For the JFET of Fig. 1 mA per div. as shown in Fig. keep in mind that the VGS curves contract very quickly 3 V is a better choice. VP is certainly more negative than 2 V and perhaps VP is close to 2. the level of IDSS can be estimated to be about 9 mA.rameter. Similar instrumentation is not available to measure the levels of IDSS and VP. VGS = –0. then 1.

which will be our choice for this device. 5. That is. The JFET equations are defined for the configuration of Fig. JFET ID ID IG IDSS 1 IS 0A VGS VP 2 BJT ⇔ ⇔ ⇔ IC IC VBE IB IE 0. the level of VP can be estimated to a reasonable degree of accuracy simply by applying a condition appearing in Table 5.3VP. that VP VGS /0. Fortunately.21. and 2 V.25 V curve would reveal how quickly between each step of Fig. Shockley’s equation will result in ID 0.5 mA. 5. while the BJT equations relate to Fig. they are repeated below next to a corresponding equation for the BJT transistor. 1. Using this value we find that at VGS ID IDSS 1 9 mA 1 1 mA as supported by Fig. then VGS 0.25 V and the 2. and as visible from Fig. 5.3 3 V. Using this information we find 0. 1. The VGS the curves are closing in on each other for the same step voltage.5. 5. 5.22a. The importance of the parameter gm and how it is determined from the characteristics of Fig.should also be noted that the step control is set for a 5-step display.22 (a) JFET versus (b) BJT. 5.5 V. JFET D ID IG = 0 A G 2 BJT C IC IB B + VGS ID = IDSS 1 – ( VGS VP ( + IC = β IB IS VBE = 0. In an effort to isolate and emphasize their importance.7 V IE E – S (a) – (b) Figure 5. ID IDSS /2 9 mA/2 4.5. the voltage per step could be reduced to 250 mV 0.6 IMPORTANT RELATIONSHIPS A number of important equations and operating characteristics have been introduced in the last few sections that are of particular importance for the analysis to follow for the dc and ac configurations.21 the corresponding level of VGS is about 0. with VP At VGS 3 V clearly revealing how quickly the curves contract near VP. VGS VP 2 2V 3V 2 5.21 are described in Chapter 8 when small-signal ac conditions are examined.9 V.21.1. 0. when ID IDSS /2.7 V 227 (5. For the characteristics of Fig. 5.25 mA.25 V would have been included as well as an additional curve curve for VGS 2. 2. limiting the displayed curves to VGS 0.10) 5.21.9 V/0.3 2 V.6 Important Relationships .22b. If the step control had been increased to 10.

In some cases the substrate is internally connected to the source terminal. However. In this section we examine the depletion-type MOSFET. while the label MOSFET stands for metal-oxide-semiconductor-field-effect transistor. Recall that VBE 0. For the BJT configuration. Basic Construction The basic construction of the n-channel depletion-type MOSFET is provided in Fig. 5. IB is normally the first parameter to be determined. A slab of p-type material is formed from a silicon base and is referred to as the substrate.7 V was often the key to initiating an analysis of a BJT configuration. 5. which happens to have characteristics similar to those of a JFET between cutoff and saturation at IDSS but then has the added feature of characteristics that extend into the region of opposite polarity for VGS. 228 Chapter 5 Field-Effect Transistors . SiO2 is a particular type of insulator referred to as a dielectric that sets up opposing (as revealed by Figure 5. it is normally VGS. For the JFET.23 n-Channel depletion-type MOSFET. It is the foundation upon which the device will be constructed. The terms depletion and enhancement define their basic mode of operation. Since there are differences in the characteristics and operation of each type of MOSFET.23. there are two types of FETs: JFETs and MOSFETs. resulting in a four-terminal device.A clear understanding of the impact of each of the equations above is sufficient background to approach the most complex of dc configurations.7 DEPLETION-TYPE MOSFET As noted in the chapter introduction. The gate is also connected to a metal contact surface but remains insulated from the n-channel by a very thin silicon dioxide (SiO2) layer. such as that appearing in Fig. MOSFETs are further broken down into depletion type and enhancement type. Similarly. the condition IG 0 A is often the starting point for the analysis of a JFET configuration. many discrete devices provide an additional terminal labeled SS. 5. The source and drain terminals are connected through metallic contacts to n-doped regions linked by an n-channel as shown in the figure. they are covered in separate sections. The number of similarities between the analysis of BJT and JFET dc configurations will become quite apparent in Chapter 6.23.

and a voltage VDS is applied across the drain-to-source terminals.and p-type regions are diffused. even though the input impedance of most JFETs is sufficiently high for most applications. as shown in Fig. In addition: It is the insulating layer of SiO2 in the MOSFET construction that accounts for the very desirable high input impedance of the device. The reason for the label metal-oxide-semiconductor FET is now fairly obvious: metal for the drain. The fact that the SiO2 layer is an insulating layer reveals the following fact: There is no direct electrical connection between the gate terminal and the channel of a MOSFET.24 n-Channel depletion-type MOSFET with VGS voltage VDD. the gate terminal and the control to be offered by the surface area of the contact.24 the gate-to-source voltage is set to zero volts by the direct connection from one terminal to the other.25. the resulting current with VGS 0 V continues to be labeled IDSS. and gate connections to the proper surface—in particular. source.7 Depletion-Type MOSFET 229 . The insulating layer between the gate and channel has resulted in another name for the device: insulatedgate FET or IGFET. In fact. 5. the oxide for the silicon dioxide insulating layer. Figure 5. although this label is used less and less in current literature. and the semiconductor for the basic structure on which the n.the prefix di-) electric fields within the dielectric when exposed to an externally applied field. The very high input impedance continues to fully support the fact that the gate current (IG) is essentially zero amperes for dc-biased configurations. 5. 0 V and an applied 5. The result is an attraction for the positive potential at the drain by the free electrons of the n-channel and a current similar to that established through the channel of the JFET. In fact. the input resistance of a MOSFET is often that of the typical JFET. Basic Operation and Characteristics In Fig.

5. to the pinch-off level of 6 V.25 reveals that the drain current will increase at a rapid rate for the reasons listed above. a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n-channel available for conduction. In Fig.26. For positive values of VGS . As the gate-to-source voltage continues to increase in the positive direction. 5. The more negative the bias. and so on. 5.ID (mA) 10. The resulting levfor VGS els of drain current and the plotting of the transfer curve proceeds exactly as described for the JFET. Depending on the magnitude of the negative bias established by VGS.25 1 V. the positive gate will draw additional electrons (free carriers) from the p-type substrate due to the reverse leakage current and establish new carriers through the collisions resulting between accelerating particles. the higher the rate of recombination. The resulting level of drain current is therefore reduced with increasing negative bias for VGS as shown in Fig. The 230 Chapter 5 Field-Effect Transistors . The negative potential at the gate will tend to pressure electrons toward the p-type substrate (like charges repel) and attract holes from the p-type substrate (opposite charges attract) as shown in Fig. VGS has been set at a negative voltage such as 1 V. Figure 5.9 Enhancement mode I DSS ID VGS = + 1 V Depletion mode 8 VGS = 0 V VGS = –1 V 4 2 I DSS 2 IDSS 4 1 VGS 0 VGS = VP = – 6 V VGS = – 2 V VGS = VP = – 3 V 2 –4 V –5 V VDS – 6 – 5 – 4 – 3 – 2 –1 0 VP 0.25 Drain and transfer characteristics for an n-channel depletion-type MOSFET. Fig. 2 V.26.26 Reduction in free carriers in channel due to a negative potential at the gate terminal.3V VP P 2 Figure 5. 5.

28a. 5.25 is a clear indication of how much the current has increased for the 1-V change in VGS. be conservative with the choice of values to be substituted into Shockley’s equation. 5.2 V all of which appear in Fig. 5. The drain characteristics would appear exactly as in Fig. with the region between cutoff and the saturation level of IDSS referred to as the depletion region. As revealed above. Before plotting the positive region of VGS. Due to the rapid rise.2 mA. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region.5 mA 0. In other words. the application of a positive gate-to-source voltage has “enhanced” the level of free carriers in the channel compared to that encountered with VGS 0 V. 4V 2 0. 5.vertical spacing between the VGS 0 V and VGS 1 V curves of Fig.7 Depletion-Type MOSFET Figure 5. 2 0 V. In this case. That is.27 Transfer characteristics for an n-channel depletiontype MOSFET with IDSS 10 mA 4 V. we will try 1 V as follows: ID IDSS 1 10 mA 1 15.3 Solution At VGS VGS VGS and at ID IDSS . but all the voltage polarities and the current directions are reversed.25 but with VDS having negative val5. Sketch the transfer characteristics for an n-channel depletion-type MOSFET with 4 V. and VP 231 . there is now an n-type substrate and a p-type channel. That is. it is simply necessary that the proper sign be included with VGS in the equation and the sign be carefully monitored in the mathematical operations.3( 4 V) 1. as shown in the same figure.3VP IDSS ID 2 V. VGS VP 2 1V 4V 2 10 mA(1 0. as shown in Fig.25. the application of a voltage VGS which could possibly exceed the maximum rating (current or power) for the device. The terminals remain as identified. 5. keep in mind that ID increases very rapidly with increasing positive values of VGS.23. 4 V would result in a drain current of 22. For both regions. VP VP 2 VGS ID 4 V.5625) p-Channel Depletion-Type MOSFET The construction of a p-channel depletion-type MOSFET is exactly the reverse of that appearing in Fig.27.25)2 10 mA(1.63 mA which is sufficiently high to finish the plot. the user must be aware of the maximum drain current rating since it could be exceeded with a positive gate voltage. for the device of Fig. It is particularly interesting and helpful that Shockley’s equation will continue to be applicable for the depletion-type MOSFET characteristics in both the depletion and enhancement regions. 5. IDSS 10 mA and VP EXAMPLE 5. 10 mA 0 mA ID IDSS 4 10 mA 4 2.

The lack of a direct connection (due to the gate insulation) between the gate and channel is represented by a space between the gate and the other terminals of the symbol.28 p-Channel depletion-type MOSFET with IDSS 6 mA and VP 6 V.and p-channel depletion-type MOSFET are provided in Fig. the drain current will increase from cutoff at VGS VP in the positive VGS region to IDSS and then continue to increase for increasingly negative values of VGS. 5. Specification Sheets. The reversal in VGS will result in a mirror image (about the ID axis) for the transfer characteristics as shown in Fig. Shockley’s equation is still applicable and requires simply placing the correct sign for both VGS and VP in the equation.29 Graphic symbols for (a) n-channel depletion-type MOSFETs and (b) p-channel depletion-type MOSFETs. and VGS having the opposite polarities as shown in Fig.ID (mA) 9 8 D ID 7 6 IDSS 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 VP (b) VGS 0 ID (mA) VGS = –1 V VGS = 0 V VGS = +1 V VGS = +2 V VGS = +3 V VGS = +4 V VGS = +5 V VGS = VP = +6 V (c) VDS p G 5 4 + p p n SS 3 2 1 –1 0 V GS – S (a) Figure 5. For most of the analysis to follow in Chapter 6. Figure 5. 5. In other words.29.28c. and Case Construction The graphic symbols for an n. ues. Symbols. Two symbols are provided for each type of channel to reflect the fact that in some cases the substrate is externally available while in others it is not. 232 Chapter 5 Field-Effect Transistors . Note how the symbols chosen try to reflect the actual construction of the device.28b. 5. the substrate and source will be connected and the lower symbols will be employed. The vertical line representing the channel is connected between the drain and source and is “supported” by the substrate. ID having positive values as indicated (since the defined direction is now reversed).

with the terminal identification appearing in the same figure.30 2N3797 Motorola n-channel depletion-type MOSFET.The device appearing in Fig.30 has three terminals.7 Depletion-Type MOSFET 233 . The levels of VP and IDSS are provided along with a list of maximum values and typical “on” and “off” characteristics. The specification sheet for a depletion-type MOSFET is similar to that of a JFET. In addition. 5. how- Figure 5. 5.

5. and the drain current is now cut off until the gate-to-source voltage reaches a specific magnitude.31 n-Channel enhancement-type MOSFET. but note in Fig. another point is normally provided that reflects a typical value of ID for some positive voltage (for an n-channel device). Basic Construction The basic construction of the n-channel enhancement-type MOSFET is provided in Fig. The source and drain terminals are again connected through metallic contacts to n-doped regions. The SiO2 layer is still present to isolate the gate metallic platform from the region between the drain and source. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs—the absence of a channel as a constructed component of the device.30.ever. In summary. 5. 234 Chapter 5 Field-Effect Transistors . therefore. The transfer curve is not defined by Shockley’s equation. ID is specified as ID(on) 9 mA dc. the substrate is sometimes internally connected to the source terminal. but now it is simply separated from a section of the p-type material.31. with VDS 10 V and VGS 3.5 V. the construction of an enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET.31 the absence of a channel between the two n-doped regions. As with the depletion-type MOSFET. the characteristics of the enhancement-type MOSFET are quite different from anything obtained thus far. 5. since ID can extend beyond the IDSS level. For the unit of Fig. 5. A slab of p-type material is formed from a silicon base and is again referred to as the substrate. In particular. current control in an n-channel device is now effected by a positive gate-to-source voltage rather than the range of negative voltages encountered for n-channel JFETs and n-channel depletion-type MOSFETs. Figure 5. while in other cases a fourth lead is made available for external control of its potential level. except for the absence of a channel between the drain and source terminals.8 ENHANCEMENT-TYPE MOSFET Although there are some similarities in construction and mode of operation between depletion-type and enhancement-type MOSFETs.

32 Channel formation in the n-channel enhancementtype MOSFET. there are in fact two reverse-biased p-n junctions between the n-doped regions and the p-substrate to oppose any significant flow between drain and source.and enhancement-type MOSFETs have enhancement-type regions.32 both VDS and VGS have been set at some positive voltage greater than 0 V. The result is a depletion region near the SiO2 insulating layer void of holes. As VGS increases in magnitude. Since the channel is nonexistent with VGS 0 V and “enhanced” by the application of a positive gate-to-source voltage. but the label was applied to the latter since it is its only mode of operation. 5. the electrons in the p-substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer. 5. establishing the drain and gate at a positive potential with respect to the source. VGS at 0 V. With VDS some positive voltage. and terminal SS directly connected to the source. the concentration of electrons near the SiO2 surface increases until eventually the induced n-type region can support a measurable flow between drain and source. Electrons attracted to positive gate (induced n-channel) Region depleted of p-type carriers (holes) ID D n IG = 0 A G + VGS + + + + + + – S e e e e e e e e + + + + + + + n SS + VDS p – IS = ID Insulating layer Holes repelled by positive gate Figure 5. The positive potential at the gate will pressure the holes (since like charges repel) in the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p-substrate.31. In Fig. although VT is less unwieldy and will be used in the analysis to follow. The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal.8 Enhancement-Type MOSFET 235 . 5. Both depletion. the absence of an n-channel (with its generous number of free carriers) will result in a current of effectively zero amperes—quite different from the depletion-type MOSFET and JFET where ID IDSS.Basic Operation and Characteristics If VGS is set at 0 V and a voltage applied between the drain and source of the device of Fig. However. It is not sufficient to have a large accumulation of carriers (electrons) at the drain and source (due to the n-doped regions) if a path fails to exist between the two. The level of VGS that results in the significant increase in drain current is called the threshold voltage and is given the symbol VT. this type of MOSFET is called an enhancement-type MOSFET. as shown in the figure. On specification sheets it is referred to as VGS(Th).

33 with VGS 8 V.33 by the locus of saturation levels.33. causing a reduction in the effective channel width. saturation occurred at a level of VDS 6 V. Applying Kirchhoff’s voltage law to the terminal voltages of the MOSFET of Fig. the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. then the higher the level of VGS. Eventually.34 reveal that for the device of Fig. In fact.11)] will drop from 6 to 3 V and the gate will become less and less positive with respect to the drain.As VGS is increased beyond the threshold level. the density of free carriers in the induced channel will increase. If VGS is held fixed at some value such as 8 V and VDS is increased from 2 to 5 V. In other words. 236 Chapter 5 Field-Effect Transistors . (5. 5. the voltage VDG [by Eq.12) Obviously. The leveling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel as shown in Fig. The drain characteristics of Fig. as shown in Fig.33 Change in channel and depletion region with increasing level of VDS for a fixed value of VGS. the more the saturation level for VDS. 5. This reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons) in this region of the induced channel.33. if we hold VGS constant and increase the level of VDS.11) Figure 5. we find that VDG VDS VGS (5. 5. for a fixed value of VT. 5. resulting in an increased level of drain current. therefore. 5. the channel will be reduced to the point of pinch-off and a saturation condition will be established as described earlier for the JFET and depletion-type MOSFET. the saturation level for VDS is related to the level of applied VGS by VDSsat VGS VT (5. However. any further increase in VDS at the fixed value of VGS will not affect the saturation level of ID until breakdown conditions are encountered.

278 10 3(VGS 2 V)2 5. For levels of VGS VT. resulting in ever-increasing increments in drain current. Figure 5. 10 mA 36 V2 10 mA (6 V)2 A/V2 and a general equation for ID for the characteristics of Fig. the drain current is related to the applied gate-to-source voltage by the following nonlinear relationship: ID k(VGS VT)2 (5.278 10 3 8 V from the characteristics of Fig.278 10 3 A/V2. For the characteristics of Fig.34 yields k ID(on) (VGS(on) VT)2 (5.14) 10 mA when VGS(on) 10 mA (8 V 2 V)2 0.33 the level of VT is 2 V. the drain current of an enhancement-type MOSFET is 0 mA.ID (mA) 11 10 9 8 7 6 5 4 3 2 1 0 5V 6V 10 V Locus of VDSsat VGS = +8 V VGS = +7 V VGS = +6 V VGS = +5 V VGS = +4 V VGS = +3 V 15 V 20 V 25 V VGS = V T = 2 V VDS Figure 5. therefore: For values of VGS less than the threshold level.34 results in: ID 0. 5. k Substituting ID(on) 5.34 Drain characteristics of an n-channel enhancement-type MOSFET with VT 2 V and k 0. (5. The value of k can be determined from the following equation [derived from Eq.34 clearly reveals that as the level of VGS increased from VT to 8 V. the resulting saturation level for ID also increased from a level of 0 to 10 mA. In addition. The k term is a constant that is a function of the construction of the device. 5. In general.13)] where ID(on) and VGS(on) are the values for each at a particular point on the characteristics of the device. it is quite noticeable that the spacing between the levels of VGS increased as the magnitude of VGS increased.13) Again. as revealed by the fact that the drain current has dropped to 0 mA.8 Enhancement-Type MOSFET 237 . it is the squared term that results in the nonlinear (curved) relationship between ID and VGS.

35 Sketching the transfer characteristics for an n-channel enhancementtype MOSFET from the drain characteristics. however. Next. 5.13). the transfer characteristics will again be the characteristics to be employed in the graphical solution. For the dc analysis of enhancement-type MOSFETs to appear in Chapter 6. (5.Substituting VGS ID 4 V. a level of VGS greater than VT such as 5 V is chosen and substituted into Eq. ID (mA) 10 9 8 7 6 5 4 3 2 1 0 1 2 VT 3 4 5 6 7 8 VGS 10 9 8 7 6 5 4 3 2 1 0 ID (mA) VGS = +8 V VGS = +7 V VGS = +6 V VGS = +5 V VGS = +4 V VGS = +3 V 5 10 15 20 25 VDS VGS = V T = 2 V Figure 5. For an n-channel (induced) device.36a.5 10 3(VGS 4 V)2 First.34.12). In this case. 5. Essentially. (5. the squared term is 0 and ID 0 mA. a horizontal line is drawn at ID 0 mA from VGS 0 V to VGS 4 V as shown in Fig.5 10 3(1)2 0.11 mA 0.13) to determine the resulting level of ID as follows: ID 0. we find that 0. The transfer curve of Fig. (5. 5.5 10 3(VGS 10 3(5 V 4 V)2 4 V)2 0.5 0. At this point a measurable current will result for ID and will increase as defined by Eq.278 10 3(2)2 as verified by Fig. it is now totally in the positive VGS region and does not rise until VGS VT. In Fig. 5.278 10 3(4 V 10 3(4) 2 V)2 1. it proceeds as introduced earlier for the JFET and depletion-type MOSFETs. At VGS VT .35 is certainly quite different from those obtained earlier.278 0.35 the drain and transfer characteristics have been set side by side to describe the transfer process from one to the other.5 mA 238 Chapter 5 Field-Effect Transistors . thereby limiting the region of operation to levels of VDS greater than the saturation levels as defined by Eq. Note that in defining the points on the transfer characteristics from the drain characteristics. only the saturation levels are employed. The question now surfaces as to how to plot the transfer characteristics given the levels of k and VT as included below for a particular MOSFET: ID 0. it must be remembered that the drain current is 0 mA for VGS VT.

5.8 Enhancement-Type MOSFET 239 .31. with increasing levels of current resulting from increasingly negative values of VGS. 5. p-Channel Enhancement-Type MOSFETs The construction of a p-channel enhancement-type MOSFET is exactly the reverse of that appearing in Fig. additional levels of VGS are chosen and the resulting levels of ID obtained. 5. the level of ID is 2.37c. 5.37a.36c. The drain characteristics will appear as shown in Fig.5 10 3 A/V2 and VT 4 V.14) are equally applicable to p-channel devices.5. 7. 5. at VGS 6. 5. as shown in Fig. 5.Figure 5. there is now an n-type substrate and p-doped regions under the drain and source connections. and 8 V. but all the voltage polarities and the current directions are reversed.11) through (5. In particular. 5. respectively. with ID increasing with increasingly negative values of VGS beyond VT. The terminals remain as identified.36b.36 Plotting the transfer characteristics of an n-channel enhancementtype MOSFET with k 0. Equations (5. The transfer characteristics will be the mirror image (about the ID axis) of the transfer curve of Fig. 4.37b.35. and a point on the plot is obtained as shown in Fig. as shown in Fig. Finally. and 8 mA. That is. as shown on the resulting plot of Fig.

The case construction and terminal identification are provided next to the maximum ratings.5 10 3 A/V2. The specification sheet for a Motorola n-channel enhancement-type MOSFET is provided as Fig.37 p-Channel enhancement-type MOSFET with VT 2 V and k 0. 5. Again note how the symbols try to reflect the actual construction of the device. It is. which is now simply 10 nA dc (at VDS 10 V and VGS 0 V) compared to the milliampere range for the JFET and depletion-type MOSFET. Symbols.ID (mA) 8 D ID 7 6 8 7 6 5 4 3 2 1 VGS 0 ID (mA) VGS = –6 V p G 5 4 VGS = –5 V – p n SS 3 2 1 –6 –5 –4 –3 –2 –1 VT 0 VGS = –4 V VGS = –3 V VGS = VT = –2 V (c) VDS + D (a) (b) Figure 5. Figure 5.38 Symbols for (a) n-channel enhancement-type MOSFETs and (b) p-channel enhancement-type MOSFETs. and Case Construction The graphic symbols for the n. 5.38. in fact.and p-channel enhancement-type MOSFETs are provided as Fig.39. The dashed line between drain and source was chosen to reflect the fact that a channel does not exist between the two under no-bias conditions. The threshold voltage is specified 240 Chapter 5 Field-Effect Transistors . the only difference between the symbols for the depletion-type and enhancement-type MOSFETs. The specification sheet provides the level of IDSS under “off” conditions. Specification Sheets. which now include a maximum drain current of 30 mA dc.

depending on the unit employed. (5.8 Enhancement-Type MOSFET 241 . Rather than provide a range of k in Eq. a typical level of ID(on) (3 mA in this case) is specified at a particular level of VGS(on) (10 V for the specified ID level).39 2N4351 Motorola n-channel enhancement-type MOSFET. The given levels of VGS(Th). as VGS(Th) and has a range of 1 to 5 V dc.9. (5. 5.14) and a writing of the general equation for the transfer characteristics. In other words. The handling requirements of MOSFETs are reviewed in Section 5. when VGS 10 V. and VGS(on) permit a determination of k from Eq.Figure 5. ID 3 mA.13). ID(on).

061 10 3(VGS 3 V)2 0. it introduces a concern for its handling that was not present for the BJT or JFET transistors.4 Using the data provided on the specification sheet of Fig.40 Solution to Example 5. It is therefore imperative that we leave the shorting (or conduction) shipping foil (or ring) 242 Chapter 5 Field-Effect Transistors .4.EXAMPLE 5. (5. 10.39 and an average threshold voltage of VGS(Th) 3 V.525. and 7. ID will be 1. and 14 V. The transfer characteristics are sketched in Fig. respectively.94. There is often sufficient accumulation of static charge (that we pick up from our surroundings) to establish a potential difference across the thin layer that can break down the layer and establish conduction through it. 12.40. 4. Figure 5. but because of its extremely thin layer.244 mA For VGS 8. 5. 5. Solution (a) Eq.061 10 A/V k(VGS VT)2 0.061 10 3(5 V 10 3(4) 3 V)2 0. ID 10 3(2)2 0.9 MOSFET HANDLING The thin SiO2 layer between the gate and channel of MOSFETs has the positive effect of providing a high-input-impedance characteristic for the device.14): k ID(on) (VGS(on) VGS(Th) )2 3 10 3 mA 3 mA 2 2 (10 V 3 V) (7 V) 49 3 2 0. 3 (as defined).38 mA. (5.061 0. determine: (a) The resulting value of k for the MOSFET. 5.061 3 A/V2 (b) Eq. (b) The transfer characteristics.13): ID For VGS 5 V.

41 Zener-protected MOSFET. The maximum gate-to-source voltage is normally provided in the list of maximum ratings of the device.connecting the leads of the device together until the device is to be inserted in the system. So many of the discrete devices now have the Zener protection that some of the concerns listed above are not as troublesome. less than 1 W) compared to BJT transistors. At the very least always touch ground to permit discharge of the accumulated static charge before handling the device. Figure 5. it is still best to be somewhat cautious when handling discrete MOSFET devices. All the elements of the planar MOSFET are present in the vertical metal-oxide-silicon FET (VMOS)—the metallic surface connection to the terminals of the device—the SiO2 layer between the gate and the p-type region between the drain and source for the growth of the induced n-channel (enhancement- Figure 5.42 VMOS construction. The Zeners are back to back to ensure protection for either polarity. but even so it is still high enough for most applications. One disadvantage introduced by the Zener protection is that the off resistance of a Zener diode is less than the input impedance established by the SiO2 layer. The result is a maximum of 30 V for the gate-to-source voltage. 5. If both are 30-V Zeners and a positive transient of 40 V appears. With the ring the potential difference between any two terminals is maintained at 0 V. There are often transients (sharp changes in voltage or current) in a network when elements are removed or inserted if the power is on.23 to one with a vertical structure as shown in Fig. 5. The result is a reduction in input resistance.10 VMOS One of the disadvantages of the typical MOSFET is the reduced power-handling levels (typically. This shortfall for a device with so many positive characteristics can be softened by changing the construction mode from one of a planar nature such as shown in Fig.41.42. 5.10 VMOS 243 . 5. the lower Zener will “fire” at 30 V and the upper will turn on with a 0-V drop (ideally—for the positive “on” region of a semiconductor diode) across the other diode. The transient levels can often be more than the device can handle. as shown in Fig. 5. and therefore the power should always be off when network changes are made. However. and always pick up the transistor by the casing. The shorting ring prevents the possibility of applying a potential across any two terminals of the device. One method of ensuring that this voltage is not exceeded (perhaps by transient effects) for either polarity is to introduce two Zener diodes.

42 is somewhat simplistic in nature. the power dissipation level of the device (power lost in the form of heat) at operating current levels will be reduced.42 also has the appearance of a “V” cut in the semiconductor base. The construction of Fig. but it does permit a description of the most important facets of its operation.and n-channel devices. 5.11 CMOS A very effective logic circuit can be established by constructing a p-channel and an n-channel MOSFET on the same substrate as shown in Fig. VMOS FETs have reduced channel resistance levels and higher current and power ratings. An additional important characteristic of the vertical construction is: VMOS FETs have a positive temperature coefficient that will combat the possibility of thermal runaway. Another positive characteristic of the VMOS configuration is: The reduced charge storage levels result in faster switching times for VMOS construction compared to those for conventional planar construction. There is also the existence of two conduction paths between drain and source. contributing to a further decrease in the resistance level and an increased area for current between the doping layers. to further contribute to a higher current rating. as shown in Fig. 244 Chapter 5 Field-Effect Transistors . 5. Diffusion layers (such as the p-region of Fig. The length of the channel is now defined by the vertical height of the p-region. The configuration is referred to as a complementary MOSFET arrangement (CMOS) that has extensive applications in computer logic design. In fact. However.42 will result in the induced n-channel in the narrow p-type region of the device. The application of a positive voltage to the drain and a negative voltage to the source with the gate at 0 V or some typical positive “on” level as shown in Fig. which can be made significantly less than that of a channel using planar construction. The relatively high input impedance. fast switching speeds. the contact area between the channel and the n region is greatly increased by the vertical mode construction. On a horizontal plane the length of the channel is limited to 1 to 2 m (1 m 10 6 m).mode operation).42) can be controlled to small fractions of a micrometer. The term vertical is due primarily to the fact that the channel is now formed in the vertical direction rather than the horizontal direction for the planar device. Negative temperature coefficients result in decreased levels of resistance with increases in temperature that fuel the growing current levels and result in further temperature instability and thermal runaway. If the temperature of a device should increase due to the surrounding medium or currents of the device. Note the induced p-channel on the left and the induced n-channel on the right for the p. which often stands out as a characteristic for mental memorization of the name of the device. 5. respectively. The net result is a device with drain currents that can reach the ampere levels with power levels exceeding 10 W. 5. leaving out some of the transition levels of doping. 5. In general: Compared with commercially available planar MOSFETs. Since decreasing channel lengths result in reduced resistance levels. VMOS devices typically have switching times less than one-half that encountered for the typical BJT transistor.43. In addition.42. the resistance levels will increase. 5. 5. the channel of Fig. and lower operating power levels of the CMOS configuration have resulted in a whole new discipline referred to as CMOS logic design. causing a reduction in drain current rather than an increase as encountered for a conventional device.

The result is that Q2 will present a small resistance level.44 CMOS inverter. VSS 5V Ileakage R2 (high) Vo = R1VSS R1 + R2 ≅ 0 V (0-state) Q2 off Q1 on R1 (low) Figure 5. Since the drain current that flows for either case is limited by the “off” transistor to the leakage value. 5. establishing the desired inversion process. Q1 a high resistance. as shown in Fig. which is less than the required VT for the device. 5. 5. while the source of the n-channel MOSFET (Q1) is connected to ground. A simple application of the voltage-divider rule will reveal that Vo is very close to 0 V or the 0-state.Vi Vo VSS S2 G2 D2 D1 G1 S1 SiO2 n+ p+ p When "on" p-channel MOSFET n-type substrate p+ n+ n When "on" n-channel MOSFET n+ p p+ Figure 5.43 CMOS with the connections indicated in Fig. As introduced for switching transistors. 5.45. Additional comment on the application of CMOS logic is presented in Chapter 17. an inverter is a logic element that “inverts” the applied signal.44. The source of the p-channel MOSFET (Q2) is connected directly to the applied voltage VSS. turning on the p-channel MOSFET. resulting in an “off” state. One very effective use of the complementary arrangement is as an inverter. VGS2 0 V. an input level of 0 V will result in an output level of 5 V.” resulting in a relatively low resistance between drain and source as shown in Fig. 5.45 Relative resistance levels for Vi 5 V (1-state).44. Figure 5. That is. VGS1 Vi and Q1 is “on. and vice versa. the power dissipated by the device in either state is very low.45. and Vo VSS 5 V (the 1-state). 5. For an applied voltage Vi of 0 V (0-state). the application of 5 V at the input should result in approximately 0 V at the output. VGS1 0 V and Q1 will be off with VSS2 5 V. if the logic levels of operation are 0 V (0-state) and 5 V (1-state).44 that both gates are connected to the applied signal and both drain to the output Vo. Note in Fig.11 CMOS 245 . Since Vi and VSS are at 5 V. For the logic levels defined above. as shown in Fig. The resulting resistance level between drain and source is quite high for Q2. With 5 V at Vi (with respect to ground).

and then establish a basis for comparison of the levels of the important parameters of Ri and Ci for each device.5.12 SUMMARY TABLE Since the transfer curves and some important characteristics vary from one type of FET to another. TABLE 5.2 was developed to clearly display the differences from one device to the next.2 Field Effect Transistors Type JFET (n-channel) -SymbolBasic Relationships Transfer Curve Input Resistance and Capacitance Ri 100 M Ci: (1 10) pF MOSFET depletion-type (n-channel) Ri 1010 Ci: (1 10) pF MOSFET enhancement-type (n-channel) Ri 1010 Ci: (1 10) pF 246 Chapter 5 Field-Effect Transistors . Take a moment to ensure that each curve is recognizable and its derivation understood. A clear understanding of all the curves and parameters of the table will provide a sufficient background for the dc and ac analyses to follow in Chapters 6 and 8. Table 5.

Finally. the Nested Sweep is chosen. For the junction-fieldeffect transistor Beta is defined by IDSS Beta Vp 2 (5. 5. Choosing the Setup Analysis icon (recall that it has the horizontal blue line at the top). Figure 5. the DC Sweep is first enabled and then activated to produce the DC Sweep dialog box. The series of curves for various levels of V will require a nested sweep under the main sweep for the drain-to-source voltage.13 PSpice Windows 247 . 5.46. There is no need to call up the X-Axis Settings because the horizontal axis has the correct range and the voltage VDD is actually the drain-to-source voltage. the End Value of 5 V is entered.46 Network employed to obtain the characteristics of the n-channel J2N3819 JFET. ID(J1) is chosen.47. clicking on the analysis icon will result in the OrCAD-MicroSim Probe screen. and Increment of 0. and the Increment is set at 1 V. The parameter Vto 3 defines VGS VP 3 V as the pinch-off voltage— something to check when we obtain our characteristics. followed by OK. The result is the set of characteristics appearing in Fig. the Start Value of 0 V is chosen. and Voltage and Linear are chosen once more. Select Voltage SourceLinear. be sure to Enable Nested Sweep before clicking on OK and closing. the Name: VGG is entered.13 PSPICE WINDOWS The characteristics of an n-channel JFET can be found in much the same manner as employed for the bipolar transistor. Note the absence of any resistors since the input impedance is assumed to be infinite. Then. By choosing the Trace icon. the Start Value of 0 V. The remaining labels were added using the ABC icon.5. the Add Traces dialog box will appear. With the Automatically run Probe after Simulation enabled. End Value of 10 V. The configuration required appears in Fig. Then.15) Figure 5. resulting in IG 0 A.47 Drain characteristics for the n-channel J2N3819 JFET of Figure 5. Calling up the device specifications through Edit-Model-Edit Instance Model (Text) will result in a display having at the head of the listing a parameter Beta. 5.01 V.46. The value of IDSS is very close to 12 mA. as expected by the Vto parameter. and insert the Name: VDD. Note that the pinch-off voltage is 3 V.

48. 5. the End will be VGG. since the result will only be one curve. This time. and the Increment 0. Choose OK and we’re back to the X-Axis Settings dialog box to choose the User Defined range of 3 V to 0 V (which already appears because of our sweep settings). The DC Sweep is again enabled. After an OK followed by a Close. Figure 5. the Simulation icon can be chosen.01 V to get a good continuous plot. 248 Chapter 5 Field-Effect Transistors . Choose OK again and the Trace ID(J1) can be chosen to result in the transfer characteristics of Fig. a nested operation will not be performed. the Start Value 3 V (since we now know that VP Value 0 V. and the DC Sweep is chosen. Once the Probe screen appears. the Name 3 V).46. choose Plot-X-Axis Settings-Axis Variable and choose V(J1:g) for the gateto-source voltage. After choosing Voltage Source and Linear.The transfer characteristics can be obtained by returning to the network configuration and choosing the Analysis-Setup icon.48 Transfer characteristics for the n-channel J2N3819 JFET of Figure 5.

Are there any major differences? Problems 249 . Using the characteristics of Fig. 5. Given the characteristics of Fig. In general. 5. 5. (a) Draw the basic construction of a p-channel JFET. calculate the resistance of the JFET for the region ID 0 to 6 mA for VGS 0 V. 5.8 V.§ 5.5 mA for VGS 2 V. and compare the results with part (f). (b) Why is the input impedance to a JFET so high? (c) Why is the terminology field effect appropriate for this important three-terminal device? 7. (e) Determine VDS for VGS 2 V and ID 1. (e) VGS 4 V. 5. (c) Repeat part (a) between VGS 2 and 3 V. (g) Defining the result of part (b) as ro.10. 3. 5. (d) Using the results of part (c). (f) Using the results of part (e). (c) Determine VDS for VGS 1 V and ID 3 mA. (5. What are the major differences between the collector characteristics of a BJT transistor and the drain characteristics of a JFET transistor? Compare the units of each axis and the controlling variable. calculate the resistance of the JFET for the region ID 0 to 3 mA for VGS 1 V. (a) VGS 0 V. (a) Determine VDS for VGS 0 V and ID 6 mA using the characteristics of Fig. 5. (b) Repeat part (a) between VGS 1 and 2 V. (b) Using Fig. (d) VGS 1. (b) Using the results of part (a). (d) Repeat part (a) between VGS 3 and 4 V.10: (a) Determine the difference in drain current (for VDS VP) between VGS 0 V and VGS 1 V. How does IC react to increasing levels of IB versus changes in ID to increasingly negative values of VGS? How does the spacing between steps of IB compare to the spacing between steps of VGS? Compare VCsat to VP in defining the nonlinear region at low levels of output voltage. 2.5 mA. 8. Using the characteristics of Fig. sketch the transfer characteristics using Shockley’s equation.49 to establish the values of IDSS and VP.1) appear to be a valid approximation? 4. determine ID for the following levels of VGS (with VDS VP). (f) VGS 6 V.5 V. sketch a probable distribution of characteristic curves for the JFET (similar to Fig. (a) Describe in your own words why IG is effectively zero amperes for a JFET transistor. (b) VGS 1 V. (h) Repeat part (g) for VGS 2 V using the same equation.2 Construction and Characteristics of JFETs 1. does Eq.3 Transfer Characteristics 9. (c) VGS 1. calculate the resistance of the JFET for the region ID 0 to 1. (b) Apply the proper biasing between drain and source and sketch the depletion region for VGS 0 V.49: (a) Sketch the transfer characteristics directly from the drain characteristics. PROBLEMS § 5. Given IDSS 12 mA and VP 6 V. (i) Based on the results of parts (g) and (h). (e) Is there a marked change in the difference in current levels as VGS becomes increasingly negative? (f) Is the relationship between the change in VGS and the resulting change in ID linear or nonlinear? Explain. (5.1) and compare with the results of part (d). determine the resistance for VGS 1 V using Eq. 6.10. comment on the polarity of the various voltages and direction of the currents for an n-channel JFET versus a p-channel JFET.10). (c) Compare the characteristics of parts (a) and (b).

250 Chapter 5 Field-Effect Transistors .4 Specification Sheets (JFETs) 16. 5.5 mA and VP 4 V.5 V. 4. Determine VP for the characteristics of Fig.21. is the locus of pinch-off values defined by the region of VDS 20.5 mA. Given IDSS 6 mA and VP (a) Determine ID at VGS 2 and 3. 11. 13. (a) Given IDSS 12 mA and VP 4 V. sketch the transfer curve defined by the maximum IDSS and VP and the transfer curve for the minimum IDSS and VP. 15. That is. 3. 7. Given a Q-point of IDQ 3 mA and VGS 3 V.7 V and VDS 10 V. (b) Sketch the drain characteristics for the device of part (a).21 using IDSS and ID at some value of VGS.5 Instrumentation 18.5. Sketch the transfer § 5.Figure 5. VP 3 V? 19. (b) Determine VGS at ID 3 and 5. 5. (d) VGS 5 V. Then. (b) VGS 2 V. determine ID when: 5 V. Using the characteristics of Fig. determine ID at VGS 0. 5. 17 10. Referring to Fig. 5.1.49 Problems 9. § 5. Repeat the above for VGS 1 V. . sketch the transfer characteristics using the data points 12. Compare the result to the assumed value of 3 V from the characteristics. and compare it to the value determined using Shockley’s equation. Define the region of operation for the 2N5457 JFET of Fig. determine IDSS if VP 6 V. A p-channel JFET has device parameters of IDSS characteristics. That is.5 V.6 V.49 if VDSmax 25 V and PDmax 120 mW. simply substitute into Shockley’s equation and solve for VP.21.5 V: 14. sketch the transfer characteristics for the JFET transistor. Given IDSS 16 mA and VP of Table 5. (c) VGS 3.18 using the range of IDSS and VP provided. shade in the resulting area between the two curves. Define the region of operation for the JFET of Fig. Given IDSS 9 mA and VP (a) VGS 0 V. Determine the value of ID at VGS 3 V from the curve. 17.

the direction of electron flow. briefly describe the basic operation of an enhancement-type MOSFET. 5. (5. Explain in your own words why the application of a positive voltage to the gate of an n-channel depletion-type MOSFET will result in a drain current exceeding IDSS. (5. does the drain current increase at a significantly higher rate than for negative values? Does the ID curve become more and more vertical with increasing positive values of VGS? Is there a linear or a nonlinear relationship between ID and VGS? Explain. determine the level of VGS that will result in a maximum drain current of 20 mA if VP 5 V. determine the drain cur26. determine k and write the general expression for ID in the format of Eq. § 5. determine VT. (c) Determine ID for the device of part (a) at VGS 2. Problems 251 .1) to determine rd and compare to the result of part (b).30 is 8 mA. 24. 36. (a) Given VGS(Th) 4 V and ID(on) 4 mA at VGS(on) 6 V. Using IDSS 9 mA and VP 3 V for the characteristics of Fig.21. Given ID FET. 29. The maximum drain current for the 2N4351 n-channel enhancement-type MOSFET is 30 mA. Given a depletion-type MOSFET with IDSS 6 mA and VP rent at VGS 1.30.4 10 3 A/V2 and ID(on) 3 mA with VGS(on) 4 V. and the resulting depletion region. use Eq. determine VP if IDSS 2 V.50. 5. 30.5 V but k is increased by 100% to 0.7 Depletion-Type MOSFET 23.13). determine VT and k and write the general equation for ID. (a) Calculate the resistance associated with the JFET of Fig.5 V and k 0.5 V from ID 0 to 3 mA. (b) Repeat part (a) for the transfer characteristics if VT is maintained at 3.8 Enhancement-Type MOSFET 32. 5.21. (b) Apply the proper drain-to-source voltage and sketch the flow of electrons for VGS 0 V. 5. (a) What is the significant difference between the construction of an enhancement-type MOSFET and a depletion-type MOSFET? (b) Sketch a p-channel enhancement-type MOSFET with the proper biasing applied (VDS 0 V. 33. 1. In the positive VGS region. Using an average value of 2. 5.5 mA for a depletion-type MOS5 V. 34. (c) Assigning the label ro to the result of part (a) and rd to that of part (b). 31. 5. (c) In your own words. Given k 0.06 10 3 A/V2 and VT is the maximum value.21. and 10 V. 27. (a) Sketch the basic construction of a p-channel depletion-type MOSFET. (b) Repeat part (a) for VGS 0. VGS VT) and indicate the channel. and 2 V. In what ways is the construction of a depletion-type MOSFET similar to that of a JFET? In what ways is it different? 25. 3 V. Given ID 14 mA and VGS 4 mA at VGS 1 V. 0. Compare the difference in current levels between 1 and 0 V with the difference between 1 and 2 V. 35.21 for VGS 0 V from ID 0 to 4 mA. 37. IDSS 12 mA and VP 28. Given the transfer characteristics of Fig. what is the maximum permissible value of VDS utilizing the maximum power rating? § 5. (a) Sketch the transfer and drain characteristics of an n-channel enhancement-type MOSFET if VT 3. determine IDSS if VP 9. (b) Sketch the transfer characteristics for the device of part (a). If the drain current for the 2N3797 MOSFET of Fig.8 10 3 A/V2.9 mA for the IDSS of the 2N3797 MOSFET of Fig.4 10 3 A/V2. 5. calculate ID at VGS 1 V using Shockley’s equation and compare to the level appearing in Fig. 22. Sketch the transfer and drain characteristics of an n-channel depletion-type MOSFET with 8 V for a range of VGS VP to VGS 1 V. Determine VGS at this current level if k 0.

11 CMOS * 42.44 with Vi 0 V. Research CMOS logic at your local or college library. (a) Describe in your own words why the VMOS FET can withstand a higher current and power rating than the standard construction technique.45 10 3 A/V2. calculate dID /dVGS and compare its magnitude. Sketch the transfer characteristics of a p-channel enhancement-type MOSFET if VT and k 0. *Please Note: Asterisks indicate more difficult problems. and describe the range of applications and basic advantages of the approach.5 10 3(VGS 4)2 for VGS from 0 to GS 10 V. 252 Chapter 5 Field-Effect Transistors .Figure 5.10 VMOS 41. (b) Why do VMOS FETs have reduced channel resistance levels? (c) Why is a positive temperature coefficient desirable? § 5. and if your mathematics background includes differential calculus.1 V. Does VT 4 V have a significant impact on the level of ID for this region? § 5.44 (with Vi 0 V) has a drain current of 4 mA with VDS 0. 39.5 10 3(V 2 ) and ID 0. Does the current of an enhancement-type MOSFET increase at about the same rate as a depletion-type MOSFET for the conduction region? Carefully review the general format of the equations. (a) Describe in your own words the operation of the network of Fig. 5. what is the approximate resistance of the device? Do the resulting resistance levels suggest that the desired output voltage level will result? 43.5 A for the “off” transistor. 5. (b) If the “on” MOSFET of Fig.50 Problem 35 38. what is the approximate resistance level of the device? If ID 0. Sketch the curve of ID 0. 5V 40.

Another distinct difference between the analysis of BJT and FET transistors is that the input controlling variable for a BJT transistor is a current level. IC linkage between input and output variables is provided by .3) 253 . however. For the field-effect transistor. and so on. Doubling the value of IB will double the level of IC.1) 6 For JFETS and depletion-type MOSFETs. Linear relationships result in straight lines when plotted on a graph of one variable versus the other. In both cases.2) (6. which is assumed to be fixed in magnitude for the analysis to be performed.1 INTRODUCTION In Chapter 5 we found that the biasing levels for a silicon transistor configuration can IB. but it is a quicker method for most FET amplifiers. The general relationships that can be applied to the dc analysis of all FET amplifiers are IG ≅ 0 A and ID IS (6. A graphical approach may limit solutions to tenths-place accuracy. Since the graphical approach is in general the most popular. the relationship between input and output quantities is nonlinear due to the squared term in Shockley’s equation. The fact that beta is a constant establishes a linear relationship between IC and IB.7 V. the controlled variable on the output side is a current level that also defines the important voltage levels of the output circuit. while for the FET a voltage is the controlling variable. The nonlinear relationship between ID and VGS can complicate the mathematical approach to the dc analysis of FET configurations. Shockley’s equation is applied to relate the input and output quantities: ID IDSS 1 VGS VP 2 (6. the analysis of this chapter will have a graphical orientation rather than direct mathematical techniques. while nonlinear functions result in curves as obtained for the transfer characteristics of a JFET.CHAPTER FET Biasing 6. The be obtained using the characteristic equations VBE 0. and IC ≅ IE.

254 Chapter 6 FET Biasing .1 Fixed-bias configuration. For the dc analysis. The depletion-type MOSFET will then be examined with its increased range of operating points.4) It is particularly important to realize that all of the equations above are for the device only! They do not change with each network configuration so long as the device is in the active region. IG ≅ 0 A and VRG IGRG (0 A)RG 0V The zero-volt drop across RG permits replacing RG by a short-circuit equivalent. followed by the enhancement-type MOSFET.2 specifically redrawn for the dc analysis. 6. Both methods are included in this section to demonstrate the difference between the two philosophies and also to establish the fact that the same solution can be obtained using either method. it is one of the few FET configurations that can be solved just as directly using either a mathematical or graphical approach.2 Network for dc analysis. Figure 6. 6.1 includes the ac levels Vi and Vo and the coupling capacitors (C1 and C2). the graphical approach is the most popular for FET networks and is employed in this book. The solution can be determined using a mathematical or graphical approach—a fact to be demonstrated by the first few networks to be analyzed. as noted earlier. 6. The configuration of Fig. the dc solution of BJT and FET networks is the solution of simultaneous equations established by the device and network. The first few sections of this chapter are limited to JFETs and the graphical approach to analysis. Referred to as the fixed-bias configuration. However. Figure 6. The resistor RG is present to ensure that Vi appears at the input to the FET amplifier for the ac analysis (Chapter 9).For enhancement-type MOSFETs. Recall that the coupling capacitors are “open circuits” for the dc analysis and low impedances (essentially short circuits) for the ac analysis. The network simply defines the level of current and voltage associated with the operating point through its own set of equations. the following equation is applicable: ID k(VGS VT)2 (6. Finally.1. In reality. 6.2 FIXED-BIAS CONFIGURATION The simplest of biasing arrangements for the n-channel JFET appears in Fig. problems of a design nature are investigated to fully test the concepts and procedures introduced in the chapter. as appearing in the network of Fig.

The point where the two curves ID (mA) Device Network Q-point (solution) IDSS ID Q VP VGSQ = –VGG 0 VGS Figure 6. resulting in the notation “fixed-bias configuration. its magnitude and sign can simply be substituted into Shockley’s equation and the resulting level of ID calculated. 6.3 equation. For the analysis of this chapter. ID (mA) IDSS IDSS 4 VP VP 2 0 VGS Figure 6. Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop of Fig.3. At any point on the vertical line.4. the voltage VGS is fixed in magnitude. Plotting Shockley’s In Fig.The fact that the negative terminal of the battery is connected directly to the defined positive potential of VGS clearly reveals that the polarity of VGS is directly opposite to that of VGG.5) Since VGG is a fixed dc supply. This is one of the few instances in which a mathematical solution to a FET configuration is quite direct. 6. the fixed level of VGS has been superimposed as a vertical line at VGG. VP. the level of VGS is VGG —the level VGS of ID must simply be determined on this vertical line. and the intersection just described will be sufficient for plotting the curve.2 Fixed-Bias Configuration 255 . the three points defined by IDSS. Recall that choosing VGS VP/2 will result in a drain current of IDSS/4 when plotting the equation. 6.” The resulting level of drain current ID is now controlled by Shockley’s equation: ID IDSS 1 VGS VP 2 Since VGS is a fixed quantity for this configuration. A graphical analysis would require a plot of Shockley’s equation as shown in Fig.4 Finding the solution for the fixed-bias configuration.2 will result in VGG and VGS VGS VGG 0 (6. 6.

6. 6.5 are the quiescent values defined by Fig. Figure 6.4. the dc levels of ID and VGS that will be measured by the meters of Fig. 6. VS Using double-subscript notation: VDS or and In addition. its use is limited and will not be included in the forthcoming list of the most common FET configurations.7) The fact that VD VDS and VG VGS is fairly obvious from the fact that VS 0 V.4 that the quiescent level of ID is determined by drawing a horizontal line from the Q-point to the vertical ID axis as shown in Fig. or and VGS VG VG VGS VG VD VD VDS VD VS VS VGS VGS 0V (6. 6. Note in Fig.8) 0V (6. The subscript Q will be applied to drain current and gate-to-source voltage to identify their levels at the Q-point.1 is constructed and operating.5 Measuring the quiescent values of ID and VGS. For the configuration of Fig. 6. The drain-to-source voltage of the output section can be determined by applying Kirchhoff’s voltage law as follows: VDS and VDS ID RD VDD VDD IDRD 0 (6. but the derivations above were included to emphasize the relationship that exists between double-subscript and single-subscript notation.intersect is the common solution to the configuration—commonly referred to as the quiescent or operating point. It is important to realize that once the network of Fig. Since the configuration requires two dc supplies.6) Recall that single-subscript voltages refer to the voltage at a point with respect to ground.9) VS VS VDS VDS 0V (6. 256 Chapter 6 FET Biasing . 6.4.2.

6.6 Example 6. D G I DSS = 10 mA VP = –8 V VGS EXAMPLE 6.5 mA 4 I D = 5.625 mA)(2 k ) 16 V 11. 6.Determine the following for the network of Fig. Solution Mathematical Approach: (a) VGSQ (b) IDQ (c) VDS (d) VD (e) VG (f) VS 2V VGS 2 2V 2 IDSS 1 10 mA 1 VP 8V 2 10 mA(1 0. 2 kΩ (e) VG.25 V 4.25) 10 mA(0.2 Fixed-Bias Configuration 257 .6 mA Q Figure 6.75 V VGS 2V 0V VGG Graphical Approach: The resulting Shockley curve and the vertical line at VGS 2 V are provided in Fig.1 + 1 MΩ – S – + 2V Figure 6.7. (a) VGSQ. 16 V (b) IDQ.6. 6. It is certainly difficult to read beyond the second place without significantly inID (mA) IDSS = 10 mA 9 8 7 Q-point 6 5 4 3 2 1 –8 –7 – 6 – 5 – 4 – 3 –2 –1 0 VGS VP = –8 V VP VGSQ = –VGG = –2 V = –4 V 2 IDSS = 2.625 mA VDD IDRD 16 V (5.5625) 5.75 V VDS 4. (f) VS.7 Graphical solution for the network of Fig. (c) VDS. (d) VD. 6.1.6.75)2 10 mA(0.

JFET self-bias con- For the dc analysis.3 SELF-BIAS CONFIGURATION The self-bias configuration eliminates the need for two dc supplies. the capacitors can again be replaced by “open circuits” and the resistor RG replaced by a short-circuit equivalent since IG 0 A.6 mA VDD IDRD 16 V (5. Chapter 6 FET Biasing 258 . The current through RS is the source current IS. Therefore. for part (a).2 V 4. we find that VGS VGS Note in this case that VGS is a function of the output current ID and not fixed in magnitude as occurred for the fixed-bias configuration. 6. 6. but a solution of 5. The result is the network of Fig. 6. but IS ID and VRS VGS and or Figure 6.10) 0 For the indicated closed loop of Fig.8 figuration.8 V (d) VD VDS 4. Figure 6.9 DC analysis of the self-bias configuration.7 is quite acceptable. VGSQ (b) IDQ (c) VDS VGG 2V 5. 6.8 V 2V (e) VG VGS (f) VS 0 V The results clearly confirm the fact that the mathematical and graphical approaches generate solutions that are quite close.creasing the size of the figure.9 for the important dc analysis.6 mA)(2 k ) 16 V 11.9.6 mA from the graph of Fig. The controlling gate-to-source voltage is now determined by the voltage across a resistor RS introduced in the source leg of the configuration as shown in Fig.8. IDRS VRS VRS IDRS (6. 6.

10 Defining a point on the self-bias line. The graphical approach requires that we first establish the device transfer characteristics as shown in Fig. The straight line as defined by Eq. (6. That is. one point on the straight VGS line is defined by ID 0 A and VGS 0 V. The resulting levels of ID and VGS will then define another point on the straight line and permit an actual drawing of the straight line. an equation of the following form can be obtained: 2 ID K1ID K2 0 The quadratic equation can then be solved for the appropriate solution for ID. Suppose. (6. as appearing on Fig. therefore. (6. Since Eq. (6. The most obvious condition to apply is ID 0 A since it results in IDRS (0 A)RS 0 V. (6.Equation (6. and Shockley’s equation relates the input and output quantities of the device. Figure 6.11. 6.10) defines a straight line on the same graph.10. permitting either a mathematical or graphical solution. For Eq. The second point for Eq.10) into Shockley’s equation as shown below: ID IDSS 1 IDSS 1 or ID IDSS 1 VGS VP 2 IDRS VP IDRS VP 2 2 By performing the squaring process indicated and rearranging terms.10) is then drawn and the quiescent point obtained at the in6. 6. 6.10). let us now identify two points on the graph that are on the line and simply draw a straight line between the two points.10) requires that a level of VGS or ID be chosen and the corresponding level of the other quantity be determined using Eq.10) is defined by the network configuration.10).10. Both equations relate the same two variables. The sequence above defines the mathematical approach. for example.3 Self-Bias Configuration 259 . (6. that we choose a level of ID equal to one-half the saturation level. A mathematical solution could be obtained simply by substituting Eq. ID then VGS IDRS IDSS 2 IDSSRS 2 The result is a second point for the straight-line plot as shown in Fig.

(c) VDS. tersection of the straight-line plot and the device characteristic curve. 260 Chapter 6 FET Biasing .13) (6.11) VDS VRS VRD VRD VDD VDD 0 ISRS IDRD EXAMPLE 6. (b) IDQ.12 Example 6.2.12.2 Determine the following for the network of Fig.12) (6.ID IDSS IDSS 2 Q-point ID Q VP VGSQ I R VGS = _ DSS S 2 0 VGS Figure 6. The quiescent values of ID and VGS can then be determined and used to find the other quantities of interest. (f ) VD.14) VDS ID VDD IS VDS VDD ID(RS RD) (6.11 Sketching the selfbias line. 6. (a) VGSQ. The level of VDS can be determined by applying Kirchhoff’s voltage law to the output circuit. with the result that VRS and but and In addition: VS VG and VD VDS VS IDRS 0V VDD VRD (6. (e) VG. (d) VS. Figure 6.

if we choose VGS VP/2 IDSS/4 8 mA/4 2 mA. 6. 3 V. 6. keep in mind that the value of VGS could be chosen and the value of ID calculated with the same resulting plot. 6.12.12. The resulting operating point results in a quiescent value of gate-to-source voltage of VGSQ 2. The solution is obtained by superimposing the network characteristics defined by Fig.13 on the device characteristics of Fig. In addition.3 Self-Bias Configuration 261 . the same straight line will result. the resulting value of VGS would be 8 V. (6. In either case.14 Sketching the device characteristics for the JFET of Fig. as shown on the same graph. 6. I = 0 mA GS D – 8 –7 – 6 – 5 – 4 – 3 –2 – 1 0 VGS (V) Figure 6. and the plot of Fig.6 mA Q Figure 6. If we happen to choose ID 8 mA. VGS = –8 V ID (mA) 8 7 ID = 4 mA. Figure 6. 6. we find that ID For Shockley’s equation.13 as defined by the network.14 and finding the point of intersection of the two as indicated on Fig. we obtain VGS (4 mA)(1 k ) 4V IDRS The result is the plot of Fig. VGS = – 4V Network 6 5 4 3 2 1 V = 0 V. 6. ID = 8 mA.10) is employed. 6. 6.15 Determining the Q-point for the network of Fig. 6.15. representing the characteristics of the device.Solution (a) The gate-to-source voltage is determined by VGS Choosing ID 4 mA.6 V ID (mA) 8 7 6 5 4 3 Q-point 2 1 – 6 – 5 – 4 – 3 –2 –1 VGSQ = – 2. clearly demonstrating that any appropriate value of ID can be chosen as long as the corresponding value of VGS as determined by Eq.12.13 Sketching the selfbias line for the network of Fig.6 V 0 VGS (V) I D = 2.14 will result.

4 mA Q-point – 6 – 5 – 4 – 3 –2 –1 VGSQ ≅ – 4. (6. (6. 262 Chapter 6 FET Biasing 0.14): or VG VD VD VDD ID(RS RD) 20 V (2.3 Find the quiescent point for the network of Fig.4 mA From Eq. VGSQ ≅ (b) With the VGS scale.6 V 4 3 2 1 0 VGS (V) I D ≅ 6.10).6 mA)(3. Solution Note Fig. ID (mA) 8 RS = 100 Ω I D = 4 mA.10). IDQ ≅ 6. (a) With the ID scale.16 Example 6.12 if: (a) RS 100 . (6.42 V EXAMPLE 6.6 mA)(1 k ) 2.6 V 11.18 V 8.12): VS (e) Eq.16.6 mA)(1 k 3. (6.3. 6. VGS = – 0.6 mA (d) Eq.13): (f) Eq. VGSQ ≅ From Eq. IDQ ≅ 0.82 V 2.46 mA In particular.(b) At the quiescent point: IDQ (c) Eq. (6.6 V 0V VDS VS 8. ID = 0.3 k ) 20 V 11.82 V IDRS (2.3 k ) 11.11): VDS 2.4 V 7 Q-point 6 5 RS = 10 kΩ VGS = –4 V.6 V . 6.4 mA Q Figure 6. (6. (b) RS 10 k . note how lower levels of RS bring the load line of the network closer to the ID axis while increasing levels of RS bring the load line closer to the VGS axis.64 V 4.42 V VDD IDRD 20 V (2.

(e) VS.17 Example 6.19. EXAMPLE 6. 6. (a) The transfer characteristics and load line appear in Fig. (f) VDS. The dc analysis can therefore proceed in the same manner as recent examples. That is. 6.6 V 0 I D ≅ 3. 6.3 Self-Bias Configuration 263 .18 Sketching the dc equivalent of the network of Fig.8. 6.17.9. the resulting dc network of Fig. The device transfer curve was sketched using IDSS 12 mA 3 mA ID 4 4 ID (mA) 12 I DSS 11 10 9 8 7 6 5 Q-point 4 3 2 1 –6 VP –5 –4 –3 –2 –1 VGSQ ≅ –2. 6.19 Determining the Q-point for the network of Fig. (a) VGSQ.17.Determine the following for the common-gate configuration of Fig. (d) VG. (b) IDQ. 6. 6. VGS IDRS (6 mA)(680 ) 4. Solution The grounded gate terminal and the location of the input establish strong similarities with the common-base BJT amplifier.17.8 mA Q Figure 6.08 V as shown in Fig. Figure 6.18 has the same basic structure as Fig. In this case.4 Figure 6. Although different in appearance from the basic structure of Fig.19. 6.4. the second point for the sketch of the load line was determined by choosing (arbitrarily) ID 6 mA and solving for VGS. 6. (c) VD.

20 Voltage-divider bias arrangement. 6.8 mA)(1.21 Redrawn network of Fig.6 V (d) VG (e) VS (f) VDS 6.7 V 2. Note that all the capacitors. 6. 264 Chapter 6 FET Biasing . the source VDD was separated into two equivVDD VDD VDD R1 R1 IG ≅ 0 A RD ID VG + + R2 VG VGS + R2 – + VRS IS – – RS – Figure 6.4 VOLTAGE-DIVIDER BIASING The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to FET amplifiers as demonstrated by Fig. 6. In addition.21 for the dc analysis.20.19. but the dc analysis of each is quite different.20 for dc analysis.58 V 3.5 k ) 6.3 V 2.3 V 0V IDRS (3.19. Recall that IB provided the link between input and output circuits for the BJT voltage-divider configuration while VGS will do the same for the FET configuration. The basic construction is exactly the same. but the magnitude of IB for common-emitter BJT amplifiers can affect the dc levels of current and voltage in both the input and output circuits. The network of Fig.and the associated value of VGS: VP 6V 3V 2 2 as shown on Fig.8 mA)(680 ) 2. 6.58 V VD VS 6. 6. including the bypass capacitor CS. IG 0 A for FET amplifiers. Using the resulting quiescent point of Fig. 6.19 results in VGS VGSQ ≅ (b) From Fig. 6.72 V 12 V 5.20 is redrawn as shown in Fig. IDQ ≅ 3. Figure 6.8 mA (c) VD VDD IDRD 12 V (3. have been replaced by an “open-circuit” equivalent.

if we choose ID 0 mA. The procedure for plotting Eq.15) Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop of Fig.16) and finding the resulting value of VGS as follows: VGS VG VG and VGS VGID IDRS (0 mA)RS 0 mA (6.21 will result in VG and Substituting VRS ISRS VGS VGS VG VRS VRS 0 ID RS. but the origin is no longer a point in the plotting of the line. (6. (6. The exact location can be determined simply by substituting ID 0 mA into Eq.16) is not a difficult one and will proceed as follows. we have VGS VG IDRS (6.22. Since IG 0 A. 6. let us first use the fact that anywhere on the horizontal axis of Fig. Equation (6.22 Sketching the network equation for the voltage-divider configuration.4 Voltage-Divider Biasing 265 . (6.22 the current ID 0 mA. Since any straight line requires two points to be defined.17) The result specifies that whenever we plot Eq. The voltage VG. 6. Figure 6.16).alent sources to permit a further separation of the input and output regions of the network. If we therefore select ID to be 0 mA. 6. Kirchhoff’s current law requires that IR1 IR2 and the series equivalent circuit appearing to the left of the figure can be used to find the level of VG. the value of VGS for the plot will be VG volts. equal to the voltage across R2. can be found using the voltagedivider rule as follows: VG R2VDD R1 R2 (6. we are in essence stating that we are somewhere on the horizontal axis.16) is still the equation for a straight line.16) The result is an equation that continues to include the same two variables appearing in Shockley’s equation: VGS and ID. The point just determined appears in Fig. The quantities VG and RS are fixed by the network construction. 6.

This intersection also appears on Fig. the level of ID is determined by Eq. Since the intersection on the vertical axis is determined by ID VG/RS and VG is fixed by the input network.20) (6. The intersection of the straight line with the transfer curve in the region to the left of the vertical axis will define the operating point and the corresponding levels of ID and VGS.23 that: Increasing values of RS result in lower quiescent values of ID and more negative values of VGS.21) (6. Once the quiescent values of IDQ and VGSQ are determined. 6.For the other point. That is. (6.19) (6. let us now employ the fact that at any point on the vertical axis VGS 0 V and solve for the resulting value of ID: VGS 0V and ID VG VG VG RS IDRS IDRS VGS 0V (6. 6.18). the remaining network analysis can be performed in the usual manner.22) IDRS VDD R1 R2 266 Chapter 6 FET Biasing . 6. VDS VD VDD VDD VS IR1 IR2 ID(RD IDRD RS) (6. It is fairly obvious from Fig. (6.22. if VGS 0 V.23 Effect of RS on the resulting Q-point. increasing values of RS will reduce the level of the ID intersection as shown in Fig.18) The result specifies that whenever we plot Eq. (6.16). Figure 6.23. The two points defined above permit the drawing of a straight line to represent Eq.16).

EXAMPLE 6.82 V ( I D = 0 mA ) (VP) Figure 6. 6. The network equation is defined by VG R2VDD R1 R2 (270 k )(16 V) 2. (a) IDQ and VGSQ. (b) VD. then VGS 4 V/2 2 V.24 Example 6.82 V I D =1.25 Determining the Q-point for the network of Fig.24. (e) VDG.4 mA Q VG IDRS ID(1. if ID IDSS/4 8 mA/4 2 mA.5 k ) 1.1 M 0.82 V When ID 1.8 V I D = 2.4 Voltage-Divider Biasing 267 .5. The resulting curve representing Shockley’s equation apVP/2 pears in Fig. Solution (a) For the transfer characteristics. 6.Determine the following for the network of Fig. (d) VDS.27 M 1.24. (c) VS. 6.25.82 V and VGS 0 mA: VGS ID (mA) 8 (IDSS ) 7 6 5 4 3 Q-point 2 1 –4 –3 –2 –1 0 VGSQ = –1. 6.21 mA ( VGS = 0 V) 1 2 3 VG = 1.5 Figure 6.

42 V Although the basic construction of the network in the next example is quite different from the voltage-divider bias arrangement.5 kΩ VSS = –10 V Figure 6.24 V 3.When VGS 0 V: ID 1.4 k 1. Note that the network employs a supply at the drain and source. 268 Chapter 6 FET Biasing .26 Example 6. R D = 1.6 V 6.26. ID (d) VS. 6.4 mA)(1.21 mA The resulting bias line appears on Fig.82 V 1.82 V 10.4 k ) 10. (b) VDS. the resulting equations require a solution very similar to that just described. (a) IDQ and VGSQ.8 V 1.4 mA 1.24 V 8. EXAMPLE 6. VDD = 20 V (c) VD.24 V IDRS (2.6 Determine the following for the network of Fig. 6.64 V VD VS 10.5 k ) 3.4 mA)(2.6 V VDD ID(RD RS) 16 V (2.25 with quiescent values of IDQ and (b) VD VDD IDRD 16 V (2.8 k Ω I DSS = 9 mA VP = –3 V RS = 1.6.5 k 2.4 mA)(2.64 V VGSQ (c) VS (d) VDS or VDS (e) Although seldom requested. the voltage VDG can easily be determined using VDG VD VG 1.5 k ) 6.

The resulting operating point establishes the following quiescent levels: IDQ VGSQ 6. VGS or but and VGS VGS ISRS VSS IS VSS ID IDRS (6.23) VSS ISRS 0 The result is an equation very similar in format to Eq. 6.16) that can be superimposed on the transfer characteristics using the procedure described for Eq.5 k ) Figure 6. That is.Solution (a) An equation for VGS in terms of ID is obtained by applying Kirchhoff’s voltage law to the input section of the network as redrawn in Fig. 0 and ID 10 V 10 V 1.9 mA 0. (6.26. 6.67 mA VSS 10 V 10 V ID(1. 6.35 V (b) Applying Kirchhoff’s voltage law to the output side of Fig. Figure 6. The resulting plot points are identified on Fig.5 k ID(1.5 V and ID IDSS/4 9 mA/4 2. as also appearing VP/2 on Fig. VGS For ID For VGS 0 mA. for this example. 6.28 Determining the Q-point for the network of Fig. The transfer characteristics are sketched using the plot point established by VGS 3 V/2 1. (6.5 k ) 6.16). VGS 0 V.28.26 will result in VSS ISRS VDS IDRD VDD 6. 6.25 mA.27.28.27 Determining the network equation for the configuration of Fig. 6.26.4 0 Voltage-Divider Biasing 269 .

7. this required range will be fairly well defined by the MOSFET parameters and the resulting bias line of the network.Substituting IS ID and rearranging gives VDS VDD VSS ID(RD RS) (6.58 V 7. EXAMPLE 6.5 DEPLETION-TYPE MOSFETs The similarities in appearance between the transfer curves of JFETs and depletiontype MOSFETs permit a similar analysis of each in the dc domain.58 V VD VS VD VDS 7.77 V (6.5 k ) 20 V 12.9 mA)(1.9 mA)(1. Figure 6. (b) VDS.8 k ) 7. 270 .29 Example 6. the analysis is the same if the JFET is replaced by a depletion-type MOSFET.23 V (c) VD VDD IDRD 20 V (6. In fact.24) which for this example results in VDS 20 V 30 V 7.29. determine: (a) IDQ and VGSQ.7 For the n-channel depletion-type MOSFET of Fig. The primary difference between the two is the fact that depletion-type MOSFETs permit operating points with positive values of VGS and levels of ID that exceed IDSS.8 k 1. How far into the region of positive values of VGS and values of ID greater than IDSS does the transfer curve have to extend? For most situations.42 V (d) VDS or VS 6. A few examples will reveal the impact of the change in device on the resulting analysis.23 V 0. 6.35 V 10 V 22. for all the configurations discussed thus far. The only undefined part of the analysis is how to plot Shockley’s equation for positive values of VGS.

67 mA The resulting transfer curve appears in Fig.5 V 750 2 mA VG 1.5 V The plot points and resulting bias line appear in Fig.5 V 1.1 mA 0. Setting ID Setting VGS 0 mA results in VGS 0 V yields ID VG RS 1.5 V ID(750 ) VGS VP 2 1V 3V 2 6 mA 1 1 3 2 6 mA(1.5 mA and VGS VP/2 the fact that Shockley’s equation defines a curve that rises more rapidly as VGS becomes more positive.29.Solution (a) For the transfer characteristics.778) Figure 6. 6.8 V 6.5 V.30 Determining the Q-point for the network of Fig. (6.5 Depletion-Type MOSFETs 271 . a plot point is defined by ID IDSS/4 6 mA/4 3 V/2 1.16): VG VGS 10 M (18 V) 10 M 110 M VG IDRS 1. (6. 6.30. The resulting operating point: IDQ VGSQ 3. we have: Eq. Proceeding as described for JFETs. Substituting into Shockley’s equation yields ID IDSS 1 6 mA 1 10.15): Eq. 6.30. Considering the level of VP and 1. a plot point will be defined at VGS 1 V.

31.19): VDS VDD 18 V ≅ 10. (6. 6.8 k EXAMPLE 6. Solution (a) The plot points are the same for the transfer curve as shown in Fig. with a positive value for VGS.18 V 272 Chapter 6 FET Biasing 7. (6.8 Repeat Example 6.1 V ID(RD RS) 750 ) (3.8. Setting ID Setting VGS 0 mA results in VGS 0 V yields ID VG RS 1.35 V RS) 150 ) ID(RD (7. VGS VG IDRS 1.31. Note in this case that the quiescent point results in a drain current that exceeds IDSS.5 V The bias line is included on Fig.6 mA)(1. For the bias line.31 Example 6. The result: IDQ VGSQ (b) Eq.(b) Eq.6 mA 0.1 mA)(1.19): VDS VDD 18 V 3.5 V ID(150 ) Figure 6.5 V 150 10 mA 1.7 with RS 150 .8 k . 6.

Determine the following for the network of Fig.33.32. although it was done on this occasion to complete the transfer characteristics. There is therefore no requirement to plot the transfer curve for positive values of VGS. 6. Solution (a) The self-bias configuration results in VGS IDRS as obtained for the JFET configuration. we will choose 2 2 VGS VP 8 mA 1 2V 8V VGS RS 6V 2.4 k 1. 20 V EXAMPLE 6.7 mA)(6.5 mA 273 . (b) VD. at VGS 6 V gives 0 V. A plot point for the transfer characteristics for VGS 0 V is ID and and for VGS VGS 0 V. ID 0 mA.3 V 2.32 Example 6. establishing the fact that VGS must be less than zero volts.2 kΩ Vo Vi I DSS = 8 mA VP = – 8 V 1 MΩ 2.2 k ) 9.46 V 6. since VP VGS and ID 2V IDSS 1 12.5 mA The resulting transfer curve appears in Fig. 6.7 mA 4. 6. Choosing VGS ID The resulting Q-point: IDQ VGSQ (b) VD VDD IDRD 20 V (1.4 kΩ Figure 6. For the network bias line.9 (a) IDQ and VGSQ.9.5 Depletion-Type MOSFETs IDSS 4 VP 2 8 mA 4 8V 2 2 mA 4V 8 V.

the drain current must be IDSS (by definition).35. the drain current is zero for levels of gate-to-source voltage less than the threshold level VGS(Th). The example to follow employs a design that can also be applied to JFET transistors. For levels of VGS greater than VGS(Th).5 k ) 6.10 Determine VDS for the network of Fig. resulting in a graphical solution quite different from the preceding sections.10. the drain current is defined by 274 Chapter 6 FET Biasing . In other words.33 Determining the Qpoint for the network of Fig.32.34 Example 6. At first impression it appears rather simplistic. First and foremost. 6. 0V 10 mA There is therefore no need to draw the transfer curve and IDRD 15 V 20 V (10 mA)(1. but in fact it often causes some confusion when first analyzed due to the special point of operation. recall that for the n-channel enhancement-type MOSFET. VGSQ and IDQ VD VDD 20 V 5V Figure 6. Solution The direct connection between the gate and source terminals requires that VGS 0V Since VGS is fixed at 0 V. as shown in Fig.Figure 6. 6.6 ENHANCEMENT-TYPE MOSFETs The transfer characteristics of the enhancement-type MOSFET are quite different from those encountered for the JFET and depletion-type MOSFETs.34. EXAMPLE 6. 6.

(6. the constant k of Eq.36.27) 275 6. two points are defined immediately as shown in Fig.35). A direct connection now exists between drain and gate. other levels of ID can be determined for chosen values of VGS. 6. Feedback Biasing Arrangement A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig. a point between VGS(Th) and VGS(on) and one just greater than VGS(on) will provide a sufficient number of points to plot Eq.25) must be determined from the specification sheet data by substituting into Eq. the dc equivalent network appears as shown in Fig.35.ID (mA) ID2 ID = k (VGS – VGS(Th) )2 ID (on) ID1 VGS(Th) ID = 0 mA VGS1 VGS(on) VGS2 VGS Figure 6. 6.26) ID(on) (VGS(on) VGS(Th))2 Once k is defined. ID k(VGS VGS(Th))2 (6. (6.25) Since specification sheets typically provide the threshold voltage and a level of drain current (ID(on)) and its corresponding level of VGS(on). Typically.25) and solving for k as follows: ID ID(on) and k k(VGS k(VGS(on) VGS(Th))2 VGS(Th))2 (6. 6.6 Enhancement-Type MOSFETs . To complete the curve. (6.” Since IG 0 mA and VRG 0 V. 6. The resistor RG brings a suitably large voltage to the gate to drive the MOSFET “on.37.25) (note ID1 and ID2 on Fig. resulting in VD and VDS VG VGS (6.35 Transfer characteristics of an n-channel enhancementtype MOSFET.

(6.Figure 6. we have ID VDD RD (6. (6.28).29) 0 V into Eq. 276 Chapter 6 FET Biasing .30) VGS 0V The plots defined by Eqs.28) is that of a straight line.36.28) gives VGS Substituting VGS VDDID 0 mA (6. 6. Substituting ID 0 mA into Eq.28) appear in Fig. (6.28) The result is an equation that relates the same two variables as Eq. permitting the plot of each on the same set of axes.38 with the resulting operating point. Figure 6. Figure 6.36 Feedback biasing arrangement.37 DC equivalent of the network of Fig. (6. VDS VDD IDRD which becomes the following after substituting Eq.36. (6.38 Determining the Qpoint for the network of Fig.27): VGS VDD IDRD (6. For the output circuit. Since Eq. (6. 6.25). the same procedure described earlier can be employed to determine the two points that will define the plot on the graph.25) and (6. 6.

40.11.16 mA Figure 6.Determine IDQ and VDSQ for the enhancement-type MOSFET of Fig.6 Enhancement-Type MOSFETs 277 .24 10 3(6 V 3 V)2 0.39. EXAMPLE 6.26): k ID(on) (VGS(on) VGS(Th))2 6 mA (8 V 3 V)2 0.39.24 10 3(9) 10 3 6 10 25 3 A/v2 A/V2 2. 6. 6. Solving for k: Eq. Solution Plotting the Transfer Curve: Two points are defined immediately as shown in Fig.40 Plotting the transfer curve for the MOSFET of Fig.11 Figure 6.24 For VGS 6 V (between 3 and 8 V): ID 0.39 Example 6. 6. 6. (6.

40. (6. 6.24 10 3(49) 10 (10 V 11. At the operating point: IDQ and with ID = mA 2. For VGS ID 0.4 V 8 7 VGS Figure 6.42.41. VG R2VDD R1 R2 (6.76 mA as also appearing on Fig.24 3 10 V (slightly greater than VGS(Th)): 3 V)2 0.as shown on Fig. Voltage-Divider Biasing Arrangement A second popular biasing arrangement for the enhancement-type MOSFET appears in Fig.4 V VGSQ VDSQ 12 11 10 9 8 7 VDD 6 RD 5 4 I D = 2. 6. The four points are sufficient to plot the full curve for the range of interest as shown in Fig.75 mA 6.42 Voltage-divider biasing arrangement for an nchannel enhancement MOSFET. (6.30): VGS ID VDD 12 V VDD IDRD ID(2 k ) 0 mA 12 VID 12 V 2k VDD RD 6 mAVGS 0V The resulting bias line appears in Fig.4 V VGSQ 6.41 Determining the Q-point for the network of Fig.31) 278 Chapter 6 FET Biasing .75 mA Q 3 2 1 0 1 2 3 4 5 6 Q-point 9 10 11 12 (VDD) VGSQ = 6.40.29): Eq.40.39. 6. 6. 6. 6. The fact that IG 0 mA results in the following equation for VGG as derived from an application of the voltage-divider rule: Figure 6. For the Network Bias Line: VGS Eq.

43.44.82 k ) ID(0. Solution Network: Eq. VGSQ.6 Enhancement-Type MOSFETs 279 . all the remaining quantities of the network such as VDS. VGS VG VGS R2VDD R1 R2 VG IDRS (18 M )(40 V) 22 M 18 M 18 V 18 V ID(0.42 will result in VG and or For the output section: VRS and or VDS VDS VDS VDD VDD VRD VRS ID(RS VDD VRD RD) (6.12.12 Figure 6.33) 0 VGS VGS VGS VG VG VRS VRS IDRS (6. and VDS for the network of Fig.Applying Kirchhoff’s voltage law around the indicated loop of Fig.95 mA as appearing on Fig. and VS can be determined.82 k ) 0 V.82 k ) 18 V 18 V (0 mA)(0.31): Eq.32) relates the same two variables. (6. 6.32): When ID 0 mA. the two curves can be plotted on the same graph and a solution determined at their intersection. (6. Once IDQ and VGSQ are known.32) 0 Since the characteristics are a plot of ID versus VGS and Eq.82 k ) 21.44. EXAMPLE 6.82 k 6. Determine IDQ. 6. When VGS VGS 0 ID as appearing on Fig. ID(0. VD. 18 V 18 V 18 V 0. (6.43 Example 6. 6. 6.

k ID(on) 3 mA with VGS(on) 10 V Eq.0 k ) (6.5 V VG = 18 V 25 VGS Figure 6. IDQ ≅ 6.1 reviews the basic results and demonstrates the similarity in approach for a number of configurations.7 SUMMARY TABLE Now that the most popular biasing arrangements for the various FETs have been introduced.44).7 mA)(0.12 VGS(Th))2 10 3(VGS 5)2 which is plotted on the same graph (Fig. Device: VGS(Th) 5 V.95 RS 20 10 I D ≅ 6. Once the transfer characteristics are established. (6. the network self-bias line can be drawn and the Q-point determined at the intersection of the device transfer characteristic and the network bias curve.6 V RD) 3. 280 Chapter 6 FET Biasing . It also reveals that the general analysis of dc configurations for FETs is not overly complex.12 10 3 A/V2 and ID k(VGS 0.5 V VDD 40 V 40 V 14.26): ID(on) (VGS(on) VGS(Th))2 3 mA (10 V 5 V)2 0.12.44 Determining the Q-point for the network of Example 6. 6.ID (mA) 30 VG = 21. 6.7 mA VGSQ Eq.82 k 6. From Fig. The remaining analysis is simply an application of the basic laws of circuit analysis.44.33): VDS 12. Table 6.4 V ID(RS 25.7 mA Q Q-point 0 5 VGS (Th) 10 15 20 VGSQ = 12. (6.

1 FET Bias Configurations Type Configuration VDD RD RG Pertinent Equations Graphical Solution ID IDSS JFET Fixed-bias VGG – VGSQ VGG VDS VDD IDRS Q-point VP VGG 0 VGS ID IDSS + VDD RD RG JFET Self-bias VDS RS VDD VGS VDD IDRS ID(RD RS) Q-point VP V' 0 GS I'D VGS JFET Voltage-divider bias R1 R2 RD VG R2VDD R1 R2 Q-point VP ID IDSS VG RS 0 ID IDSS VG VGS RS VDD RD VDS VGS VG IDRS VDD ID(RD RS) JFET Common-gate RS –VSS VDD RD VDS VGS VDD VSS VSS IDRS ID(RD RS) Q-point VP Q-point 0 VSS RS VSS VGS ID IDSS VGS = 0 V Q JFET (VGSQ 0 V) VGSQ 0 V IDQ IDSS VP 0 VGS ID IDSS I'D VGS JFET (RD 0 ) RG VDD VGS VD VS VDS RS IDRS VDD IDRS VDD ISRS Q-point VP V'GS 0 Depletion-type MOSFET Fixed-bias VGG VDD RD ID Q-point RG VGSQ VGG VDS VDD IDRS VP VDD IDSS 0 VGG ID Q-point VGS Depletion-type MOSFET Voltage-divider bias R1 R2 RD VG R2VDD R1 R2 VG RS IDSS RS VDS VDD RD VGS VG ISRS VDD ID(RD RS) VDD RD VP ID 0 VG VGS Enhancement type MOSFET Feedback configuration RG VGS VDS VGS VDD IDRD ID(on) Q-point 0 VGS(Th) ID VGS(on) VDD VGS VDD Enhancementtype MOSFET Voltage-divider bias R1 R2 RD VG VGS R2VDD R1 R2 VG IDRS VG RS Q-point 0 VGS(Th) VG VGS RS 281 .TABLE 6.

These are usually particularly interesting problems due to the challenge of finding the opening and then using the results of the past few sections and Chapter 5 to find the important quantities for each device.8 COMBINATION NETWORKS Now that the dc analysis of a variety of BJT and FET configurations is established. The equations and relationships used are simply those we have now employed on more than one occasion—no need to develop any new methods of analysis. Fundamentally.45. Since VGS is a level for which an immediate solution is not obvious. The door is then usually open to calculate other quantities and concentrate on the remaining unknowns.92 V 282 Chapter 6 FET Biasing .62 V 3. The voltage-divider configuration is one where the approxi10R2 240 k ).45 Example 6. Solution From past experience we now realize that VGS is typically an important quantity to determine or write an equation for when analyzing JFET networks.7 V results in VE 0. EXAMPLE 6. the analysis simply requires that we first approach the device that will provide a terminal voltage or current level.6.6 k ) 288 k permitting a determination of VB using the voltage-divider rule on the input circuit.13 Determine the levels of VD and VC for the network of Fig. mate technique can be applied ( RE (180 1. the opportunity to analyze networks with both types of devices presents itself.13. let us turn our attention to the transistor configuration. Figure 6. For VB: VB Using the fact that VBE 24 k (16 V) 82 k 24 k VB VBE 3. 6.62 V 0.7 V 2.

7 k ) 16 V 4. The level of IDQ is then established by a horizontal line as shown in the same figure.7 k ) (1.825 mA)(2.825 mA 1. let us turn to the graphical approach and simply work in the reverse order employed in the preceding sections.7 V) 3.62 V ( 3. The two are related by Shockley’s equation: IDQ IDSS 1 VGS VP 2 Q and VGSQ could be found mathematically by solving for VGSQ and substituting numerical values.45.45 reveals that VC is linked to VB by VGS (assuming that VRG 0 V).07 V The question of how to determine VC is not as obvious. VC can be determined from VC VB VGS The question then arises as to how to find the level of VGSQ from the quiescent value of ID.7 V Figure 6. 6.7 V 7.8 Combination Networks 283 .92 V 1. The JFET transfer characteristics are first sketched as shown in Fig. we find for this configuration that IS IC ID(2. VGSQ is then determined by dropping a line down from the operating point to the horizontal axis.46. 6.32 V ID (mA) 12 I DSS 10 8 6 4 Q-point – 6 –5 VP –4 –3 Q 2 –2 –1 0 I D = 1.and with IE VRE RE VE RE IC ≅ IE ID 2. However.93 V and VD 16 V 16 V 11. Since we know VB if we can find VGS.6 k 1. A more careful examination of Fig.825 mA Q VGS ≅ – 3.825 mA Continuing. Both VCE and VDS are unknown quantities preventing us from establishing a link between VD and VC or from VE to VD.46 Determining the Q-point for the network of Fig. 6. 6. resulting in VGSQ The level of VC: VC VB VGSQ 3.

14.6 V 1 mA For the transistor.6 V Q 2. 6. an equation for VGS can be derived and the resulting quiescent point determined using graphical techniques. turning to the self-biased JFET.5 A IB(470 k ) (12. there is no obvious path to determine a voltage or current level for the transistor configuration.5 A)(470 k ) 16 V 5. VGS IDRS ID(2. IE ≅ IC and VB 16 V 16 V IB IC ID 1 mA 80 1 mA 12. That is.4 k ) resulting in the self-bias line appearing in Fig.47. Solution In this case.67 mA I D = 1 mA Q 10.875 V 1.7 V 10.48 Determining the Q-point for the network of Fig.47.125 V and VE VD VB 9.125 V Figure 6.47 Example 6.48 that establishes a quiescent point at VGSQ IDQ ID (mA) 8 IDSS 7 6 5 4 3 2 1 0 –4 –3 –2 –1 VP VGS = –2.EXAMPLE 6. Figure 6. 6. 284 Chapter 6 FET Biasing . 6.425 V VBE 0.14 Determine VD for the network of Fig. However.

For the network of Fig. it is good design practice for linear amplifiers to choose operating points that do not crowd the saturation level (IDSS) or cutoff (VP) regions. 6. 6. RS. if resistive levels are requested. it is just a matter of applying Ohm’s law in its appropriate form. requiring that the nearest commercial value be employed. However. VDD.9 Design 285 .5 mA Q EXAMPLE 6.15 RD VD = 12 V I DSS = 6 mA VP = – 3 V RS Figure 6. It appears logical that the device chosen should have a maximum VDS greater than the specified value by a safe margin.50 Example 6. Determine the required values of RD and RS. in every design procedure the maximum levels of ID and VDS as appearing on the specification sheet must not be considered as exceeded. In particular. The area of application. the value of RS and RD may not be standard commercial values. if the levels of VD and ID are specified for the network of Fig. In general. Of course. What are the closest standard commercial values? 20 V I D = 2.50. In some cases. In any case. However. and operating conditions are just a few of the conditions that enter into the total design process.49 Self-bias configuration to be designed. must be determined. It is possible that only VDD and RD are specified together with the level of VDS.49. For example. The above is only one possibility for the design phase involving the network of Fig. the level of RD can then be be determined from VGS calculated from RD (VDD VD)/ID. Levels of VGSQ close to VP/2 or IDQ near IDSS/2 are certainly reasonable starting points in the design. the result is often obtained simply by applying Ohm’s law in the following form: Runknown VR IR (6. Of course. with the tolerance (range of values) normally specified for the parameters of a network.49. The device to be employed may have to be specified along with the level of RS.6.34) Figure 6. the approach is in many ways the opposite of that described in previous sections. the slight variation due to the choice of standard values will seldom cause a real concern in the design process. the level of VGSQ can be determined from a plot of the transfer curve and RS can then IDRS. 6. The examples to follow have a design or synthesis orientation in that specific levels are provided and network parameters such as RD. we will first concentrate on establishing the chosen dc conditions. the levels of VDQ and IDQ are specified. level of amplification desired. and so on. where VR and IR are often parameters that can be found directly from the specified voltage and current levels.9 DESIGN The design process is one that is not limited solely to dc conditions. If VDD is specified. 6.15. signal strength.

5.4 k IDQ 2.5 mA 2 DQ 1 –3 –2 VP –1 Q 0 VGS VGS = – 1 V Figure 6.44 V (2.22 mA 3.16 For the voltage-divider bias configuration of Fig.22 mA)RS 7.52 Example 6. and applying VGS IDRS will establish the 2. The nearest standard commercial values are RD RS 3. RD and VRD IDQ VDD VDQ IDQ 8V 2.5 mA will result in VGSQ level of RS: (VGSQ ) ( 1 V) RS 0.22 mA The equation for VGS is then written and the known values substituted: VG IDRS (2.44 V 2. 6.5 mA Plotting the transfer curve in Fig. 6.5 mA 3.39 k 12 V and VGSQ EXAMPLE 6. Solution The level of VG is determined as follows: VG with ID 47 k (16 V) 47 k 91 k VDD VD RD 16 V 12 V 1. determine the value of RS.8 k VGS Figure 6.44 V 2.5 mA ID (mA) 6 IDSS 5 4 3 I = 2.50.2 k 0.3 k ⇒ 0. 6.4 k ⇒ 3. if VD 2 V. (6.35 k The nearest standard commercial value is 3.3 k .44 V and RS 5.22 mA)RS 2V 7. 286 Chapter 6 FET Biasing .34).2 k 20 V 12 V 2.51 Determining VGSQ for the network of Fig.52.51 and drawing a horizontal line at IDQ 1 V.16.Solution As defined by Eq.

What is the next step? Is it a bad connection? A misreading of the color code for a resistive element? An error in the construction process? The range of possibilities seems vast and often frustrating.34) yields RD and VRD ID VDD VDS ID(on) RD 6V 4 mA 1 VDD 2 VDD ID(on) ID(on) 4 mA and VGS VDS VGS(on) VGS 1 2 1 2 6 V. some idea of the expected voltage or current level must be known for the measurement to have any importance. the response is totally unexpected and fails to match the theoretical calculations. Seldom are current levels measured since such maneuvers require disturbing the network structure to insert the meter. Determine the level of VDD and RD. 6. therefore. The troubleshooting process first described in the analysis of BJT transistor configurations should narrow down the list of possibilities and isolate the problem area following a definite plan of attack. In general. In total. VDD 6V VDD VDD 12 V 1 2 VDD ID(on) 1. Solution Given ID and so that Applying Eq. Of course. In any case. This is usually followed by the checking of voltage levels between specific terminals and ground or between terminals of the network. (6.53.17.10 TROUBLESHOOTING How often has a network been carefully constructed only to find that when the power is applied. for this configuration. the process begins with a rechecking of the network construction and the terminal connections.17 VDD RD 10 MΩ VGS(on) = 6 V I D(on) = 4 mA VGS(Th) = 3 V Figure 6.10 Troubleshooting 287 .53 Example 6. once the voltage levels are obtained.5 k which is a standard commercial value. current levels can be calculated using Ohm’s law.The levels of VDS and ID are specified as VDS 1 VDD and ID 2 of Fig. the troubleshooting process can begin with some hope of success only if the basic operation of the network is understood along with some expected levels of voltage 6. 6. ID(on) for the network EXAMPLE 6.

it is possible that there is a poor ground connection between RS and ground that may not be obvious. Note for each configuration of Fig. of course. the continuity of the output circuit can easily be checked by grounding the negative lead of the voltmeter and measuring the voltage levels from VDD to ground using the positive lead.Figure 6. the device is not open between drain and source. and so on. If the level of VDS seems inappropriate. 6. times when the reasons for a strange response seem to disappear mysteriously when you check a network.54. there is obviously no drop across RD due to the lack of current through RD and the connections should be checked for continuity. The continuity of a network can also be checked simply by measuring the voltage across any resistor of the network (except for RG in the JFET configuration). An indication of 0 V immediately reveals the lack of current through the element due to an open circuit in the network. For p-channel FETs. VGSQ is limited to negative values in the range 0 V to VP. If VD VDD. the current through RD may be zero. Any other response should be considered suspicious and needs to be investigated. but it is also not “on. For the n-channel JFET amplifier. it is best not to breathe a sigh of relief and continue with the construction. The most sensitive element in the BJT and JFET configurations is the amplifier itself. note that the double-subscript notation for voltages continues as defined for the n-channel device: VGS. The application of excessive voltage during the construction or testing phase or the use of incorrect resistor values resulting in high current levels can destroy the device. If you question the condition of the amplifier. If VS VDD. The level of VDS is typically between 25% and 75% of VDD. with the positive lead (normally red) to the gate and the negative lead (usually black) to the source. such as a shorted device from drain to source. The internal connection between the wire of your lead and the terminal connector may have separated. In this case.55 that each supply voltage is now a negative voltage drawing current in the indicated direction. The cause for such a sensitive “make or break” situation should be found and corrected. 288 Chapter 6 FET Biasing . VGS is positive (positive or negative for the depletion-type MOSFET) and VDS negative. For the network of Fig. the resulting reading should have a negative sign and a magnitude of a few volts. the best test for the FET is the curve tracer since it not only reveals whether the device is operable but also its range of current and voltage levels. Some testers may reveal that the device is still fundamentally sound but do not reveal whether its range of operation has been severely reduced. it is clearly understood that the quiescent value of VGSQ is limited to 0 V or a negative voltage. or current. but the troubleshooter will simply have to narrow down the possible causes for the malfunction. The development of good troubleshooting techniques comes primarily from experience and a level of confidence in what to expect and why. 6. In such cases.11 P-CHANNEL FETS The analysis thus far has been limited solely to n-channel FETs. In this case. Other possibilities also exist. or it may reoccur at the most inopportune moment. however. 6. A reading of 0 V for VDS clearly indicates that either the output circuit has an “open” or the JFET is internally short-circuited between drain and source. but there is continuity between VD and VDD. There are. and the defined current directions are reversed as shown in Fig. 6.55 for the various types of FETs. VDS. In particular.54. however. If a meter is hooked up as shown in Fig.” The continuity through to VS is confirmed. If VD is VDD volts. a mirror image of the transfer curves is employed.54 Checking the dc operation of the JFET self-bias configuration. 6.

11 P-Channel FETs 289 . the next example will demonstrate that with the experience gained through the analysis of n-channel devices. However. 6.Figure 6. the magnitude of each quantity will be correct. the analysis of p-channel devices is quite straightforward. Due to the similarities between the analysis of n-channel and p-channel devices.55 p-channel configurations. one can actually assume an n-channel device and reverse the supply voltage and perform the entire analysis. although the current direction and voltage polarities will have to be reversed. When the results are obtained.

57. 290 Chapter 6 FET Biasing . VGSQ. 6. and VDS for the p-channel JFET of Fig. 6. 6.57 Determining the Q-point for the JFET configuration of Fig.56.56 Example 6.57.55 V Applying Kirchhoff’s voltage law gives 0 as also appearing in Fig.4 mA Q 3. Figure 6. we obtain ID VG RS 4.53 mA VG 4.4 mA 1.4 V 4 Q. Solution VG 20 k ( 20 V) 20 k 68 k VG and Choosing ID 0 mA yields VGS as appearing in Fig. Choosing VGS 0 V.56.55 V VGS VGS VG IDRS IDRS 4.4 V 3 VGS Figure 6.EXAMPLE 6.55 V 1. The resulting quiescent point from Fig. 6.8 k 2.18.point 2 1 – 5 – 4 –3 – 2 – 1 0 1 2 VGS Q 4 VP = 1.57: IDQ VGSQ ID (mA) 8 7 6 5 I D = 3. 6.18 Determine IDQ.

labeled M.8 0. Note also that the scale for ID/IDSS is on the left rather than on the right as encountered for ID in past exercises. a universal curve was developed that can be used for any level of IDSS and VP. The result is that when ID IDSS.6 2 2 0. The vertical scale labeled m can in itself be used to find the solution to fixed-bias configurations.4 3 0. is employed along with the m scale to find the solution ID I DSS 1. For the vertical axis. not its sign.8 – 0. The additional two scales on the right need an introduction.2 0 + VGS VP Figure 6. 6.3 V IDRD RS) 1. and when VGS VP.12 Universal JFET Bias Curve 291 . the ratio VGS /VPis 1. The universal curve for an n-channel JFET or depletion-type MOSFET (for negative values of VGSQ) is provided in Fig. the scale is also a normalized level of ID /IDSS.12 UNIVERSAL JFET BIAS CURVE Since the dc solution of a FET configuration requires drawing the transfer curve for each analysis.0 VG G VP 0.4 0.7 k 6.4 – 0.58.6 Normalized curve V of ID = I DSS 1 – GS VP 0. the VP indicating that only the magnitude of VP is to be employed.0 m= 5 VP RS IDSS M= m 1. the ratio is 1.8 4 0. Note that the horizontal axis is not that of VGS but of a normalized level defined by VGS /VP.2 0 –1 – 0.4 mA)(2.58 Universal JFET bias curve.2 1 0.7 V VDS ID(RD 15. 6. The other scale. Kirchhoff’s voltage law will result in IDRS and VDS VDD 20 V 20 V 4.6 – 0.For VDS.8 k ) VDD 0 (3.

(6.60. as shown in Fig. with VG as defind by Eq. Once the procedure is clearly understood.19 Determine the quiescent values of ID and VGS for the network of Fig. The resulting Q-point: VGS ID 0. we obtain m VP IDSSRS 3 V (6 mA)(1. Figure 6.35) M with VG (6. The use of the m and M axes is best described by examples employing the scales.31 The self-bias line defined by RS is plotted by drawing a straight line from the origin through a point defined by m 0.59.575 VP IDSS 292 Chapter 6 FET Biasing .6 k ) 0.36) R2VDD R1 R2 Keep in mind that the beauty of this approach is the elimination of the need to sketch the transfer curve for each analysis.19.18 and 0. The description to follow will not concentrate on why the m scale extends from 0.to voltage-divider configurations. The equations for m and M are the following. 6.2 and the M scale from 0 to 1 at VGS /VP 0 but rather 0 to 5 at VGS /VP on how to use the resulting scales to obtain a solution for the configurations. and that the calculations are fewer.31. m VP IDSSRS m VG VP (6. Solution Calculating the value of m. EXAMPLE 6. The scaling for m and M come from a mathematical development involving the network equations and normalized scaling just introduced. with a good measure of accuracy. that the superposition of the bias line is a great deal easier.59 Example 6. the analysis can be quite rapid. 6.15).

575(3 V) Determine the quiescent values of ID and VGS for the network of Fig. 293 .20.Figure 6.61.20 Figure 6. EXAMPLE 6. The quiescent values of ID and VGS can then be determined as follows: IDQ and VGSQ 0. 6.575VP 0.20.08 mA 1.18IDSS 0.60 Universal curve for Examples 6.18(6 mA) 1.61 Example 6.73 V 0.19 and 6.

5 V 6V 0. Then draw a horizontal line over to the m axis and.625 Now that m and M are known.53IDSS 0.53 and 0.625 3.5 V VP IDSSRS 6 V (8 mA)(1.56 V 0. add the magnitude of m as shown in the figure.60.62 is constructed using computer methods described in the previous chapters. draw the straight line to intersect with the transfer curve and define the Q-point: VGS ID 0. 294 Chapter 6 FET Biasing . 6. 6. The network of Fig.53(8 mA) 0. we have M m VG VP 0. The J2N3819 JFET is obtained from the EVAL. through Edit-Model-Edit Instance Model (Text).26(6 V) 4.26VP 6.2 k ) 0.Solution Calculating m gives m Determining VG yields VG Finding M. 6. at the point of intersection. Vto is set to 6V and Beta. Using the resulting point on the m axis and the M intersection. After an OK followed by clicking the Simulation icon (the yellow background with the two waveforms) and clearing the Message Viewer.20 will now be verified using PSpice Windows.24 mA 1.365 R2VDD R1 R2 (220 k )(18 V) 910 k 220 k 3. The resulting drain cur- Figure 6.222 mA/V2. the bias line can be drawn on Fig. PSpiceAD screens will result in Fig. 6.62 JFET voltage-divider configuration with PSpice Windows results for the dc levels.26 That is.60.62. In particular. VP IDSS and with IDQ VGSQ 0. the same universal curve can be employed. as defined by Beta IDSS/VP2 is set to 0.13 PSPICE WINDOWS JFET Voltage-Divider Configuration The results of Example 6.slb library and. note that even though the levels of IDSS and VP are different for the two networks. First find M on the M axis as shown in Fig.

and VGS is 3.rent is 4.64 Network employed to obtain the characteristics of the IRF150 enhancement-type n-channel MOSFET.333 mA/V2.077 V 1. Since only one curve will be obtained.13 with both a transistor and JFET will be verified.slb library. the device characteristics will be obtained by constructing the network of Fig. the Model must be altered to have a Bf(beta) of 180 to match the example. Clicking on the Setup Analysis icon (with the blue bar at the top in the left-hand corner of the screen).32 V. DC Sweep is chosen to obtain the DC Sweep dialog box. the analysis procedure of Section 6.13 using PSpice Windows.831 V). 6.13 PSpice Windows 295 .573 V versus the calculated value of 1. and Linear is chosen for the Sweep Type. Type. The results appearing in Fig. VC is 7.44 V compared to 11. Voltage Source is chosen as the Swept Var. which in 6. VD is 11. Vto must be set to 6V and Beta to 0. First. For the transistor.07 V.63 are again an excellent comparison with the handwritten solution.63 Verifying the hand-calculated solution of Example 6. there is no need for a Nested Sweep.758 V compared to 3.504 V 5.6 will be verified using the IRF150 enhancement-type n-channel MOSFET found in the EVAL. Enhancement MOSFET Next. Figure 6.231 mA compared to the calculated level of 4.56 V—both excellent comparisons. The voltage-drain voltage VDD will remain fixed at a value of 9 V (about three times the threshold value (Vto) of 2.64.138 V compared to 7.24 mA. and VGS is 3.7 V. while the gate-to-source voltage VGS. Figure 6. and for the JFET. 6. Combination Network Next. the results of Example 6.

6. and the characteristics will appear on the screen. 6. Next.64 with a load line defined by the network of Figure 6. The hand-drawn load line will be described in the paragraph to follow.this case is VGG. Click OK.4 Ω 50 A down to VGS VGG 20 V as shown in Fig. The network of Fig.65 Characteristics of the IRF500 MOSFET of Figure 6. The Name therefore is VGG and the Start Value 0V. revealing a rather high-current device. and the plot of Fig. the Add Traces dialog box can be obtained by clicking the Traces icon (red pointed pattern on an axis) and the ID(M1) chosen to obtain the drain current versus the gate-to-source voltage. simply choose Plot followed by XAxis Settings and set the User Defined range to 0 to 20 V. After another OK. 296 Chapter 6 FET Biasing . and C. with the horizontal axis appearing with VGG as the variable and range from 0 to 10 V.66 Feedback-biasing arrangement employing an IRF150 enhancement-type MOSFET. After an OK followed by a Close of the Analysis Setup. and the Increment 0. the End Value 10V. A simulation resulted in the levels shown. 6.66.65. Figure 6.01V. Figure 6.65. B. will be swept from 0 to 10 V. the OrCAD-MicroSim Probe screen will result.65 will result. 6. If Automatically run Probe after simulation is chosen under the Probe Setup Options of Analysis. which match the solution of Fig. the analysis can be performed through the Analysis icon.66 was then established to provide a load line extending from ID equal to 20 V/0. The labels ID and VGS were added using the Text Label icon with the letters A. To expand the scale of the resulting plot to 20 V.

68 Problem 2 3. (b) Superimpose the network equation on the same graph. PROBLEMS Figure 6.69.§ 6. 6.68. Compare with the solutions of part (c).2 Fixed-Bias Configuration 1.69 Problem 3 297 . determine: (a) IDQ and VGSQ using a purely mathematical approach. determine: (a) ID. Figure 6. (b) Repeat part (a) using a graphical approach and compare results. solve for IDQ and then find VDSQ. For the fixed-bias configuration of Fig. 35 2. (c) Find VDS. (b) VDS. (c) VGG.67: (a) Sketch the transfer characteristics of the device. 6.67 Problems 1. Figure 6. VD. For the fixed-bias configuration of Fig. (c) Determine IDQ and VDSQ. and VS using the results of part (a). 6. Given the measured value of VD in Fig. (d) Using Shockley’s equation. VG.

6. 6. 8. Figure 6.71 Problem 5 § 6.3 Self-Bias Configuration 6. Determine VD for the fixed-bias configuration of Fig. determine: 9.70. Determine IDQ for the network of Fig. (d) Calculate VDS. VD. 7. 36 * 7. establish a quadratic equation for ID and choose the solution compatible with the network characteristics. FET Biasing 1. That is.71. 5. and VS. 298 Chapter 6 . (e) VDS. (b) Superimpose the network equation on the same graph.73. 6. VD. Figure 6. VG. and VS. VG. Determine VD for the fixed-bias configuration of Fig. determine: (a) VGSQ and IDQ.70 Problem 4 Figure 6.74. 6. (b) VDS. (d) VD. Given the measurement VS (a) IDQ. 6.4. For the self-bias configuration of Fig. (c) IDSS. Compare to the solution obtained in Problem 6. 6.72 Problems 6.72: (a) Sketch the transfer curve for the device.72 using a purely mathematical approach.7 V for the network of Fig. (b) VGSQ. (c) Determine IDQ and VGSQ. For the network of Fig.

(b) VDS.76 Problem 11 § 6. Figure 6. 6. What is the effect of a smaller RS on IDQ and VGSQ? (b) What is the minimum possible value of RS for the network of Fig. 6.74 Problem 9 Figure 6. determine: (a) VG. 6.76.77. Figure 6. (d) VDSQ. Find VS for the network of Fig. (b) IDQ and VGSQ. 13 13.77? Problems 299 . (c) VD.75. determine: (a) ID.77 Problems 12. Figure 6. 6.51 k (about 50% of the value of 12). (c) VD and VS.4 Voltage-Divider Biasing 12. (a) Repeat Problem 12 with RS 0. (d) VS. For the network of Fig.73 Problem 8 Figure 6.75 Problem 10 * 11. For the network of Fig.* 10.

determine: (a) IDQ and VGSQ. Given VDS 4 V for the network of Fig. § 6. 6.78 Problem 14 Figure 6. 6. 6.81 Problem 17 Figure 6. Figure 6. For the network of Fig.68 kΩ Figure 6. 9 V. 6. For the network of Fig. Determine: 18 V ID 2 kΩ 750 kΩ VD = 9 V * 15.80. (b) VD and VS.82. (b) VDS and VD. determine: (a) IDQ and VGSQ.79.78.14. determine: (a) ID. VD (a) ID. * 18. (d) VP.79 Problems 15. determine: (a) IDQ and VGSQ. 37 * 16.5 Depletion-Type MOSFETs 17. (c) VG and VGS. For the network of Fig. (b) VDS and VS. (b) VDS and VS. + VG + VGS 91 kΩ VDS IDSS = 8 mA – VS – 0.81.82 Problem 18 300 Chapter 6 FET Biasing . (c) VGS. (b) VS and VDS. 6.80 Problem 16 Figure 6. For the self-bias configuration of Fig.

(b) VD and VS. (f) VC. (d) IB.83 Problem 19 Figure 6.85.8 MΩ VGS(Th) = 3 V I D(on) = 5 mA VGS(on) = 6 V VGS Q – 0.6 Enhancement-Type MOSFETs 19. 6. (e) VD.75 kΩ Figure 6. 6. For the network of Fig. determine: (a) VG. 20. (b) VGSQ and IDQ. determine: (a) IDQ and VGSQ. 24 V 2. For the network of Fig. 6.8 Combination Networks * 21.§ 6.84. (c) IE.83. (d) VDS. (b) VGSQ and VDSQ. Figure 6. (c) VD and VS. determine: (a) IDQ.2 kΩ 10 MΩ ID Q + 6.85 Problem 21 Problems 301 . For the voltage-divider configuration of Fig.84 Problem 20 § 6.

(c) IE. determine: (a) VB and VG.86 Problem 22 § 6. (f) VCE. 6. Figure 6.5RS with R1 22 M . Design a voltage-divider bias network using a depletion-type MOSFET with IDSS 10 mA and VP 4 V to have a Q-point at IDQ 2. For the combination network of Fig. Use standard values. Design a network such as appears in Fig. * 24. In addition. (d) IB. What do the readings for each configuration of Fig. (e) VC.86.87 suggest about the operation of the network? Figure 6. Design a self-bias network using a JFET transistor with IDSS 8 mA and VP 6 V to have a Q-point at IDQ 4 mA using a supply of 14 V. VS.9 Design * 23.87 Problem 26 302 Chapter 6 FET Biasing .39 using an enhancement-type MOSFET with VGS(Th) 4 V. Use a supply of 16 V and standard values. 6.10 Troubleshooting * 26. § 6. IC.* 22. Assume that RD 3RS and use standard values.5 10 3A/V2 to have a Q-point of IDQ 6 mA. and ID. (b) VE.5 mA using a supply of 24 V. and VD. 6. set VG 4 V and use RD 2. k 0. 25. (g) VDS.

90 Problem 29 Figure 6. Repeat Problem 12 using the universal JFET bias curve.12 Universal JFET Bias Curve 31. 6. (c) VD. 28. 6. (c) VD.88 Problem 27 Figure 6. 6.11 p-Channel FETs 29. 34.* 27.90.88 initially suggest that the network is behaving properly. For the network of Fig. Repeat Problem 1 using the universal JFET bias curve. determine: (a) IDQ and VGSQ. Although the readings of Fig. (b) VDS. 6. Figure 6. 30.89 Problem 28 § 6. Repeat Problem 6 using the universal JFET bias curve. Problems 303 . determine: (a) IDQ and VGSQ. 32. The network of Fig.89 is not operating properly. Repeat Problem 15 using the universal JFET bias curve. 33. For the network of Fig. (b) VDS. What is the specific cause for its failure? * Figure 6.91 Problem 30 § 6.91. determine a possible cause for the undesirable state of the network.

Perform a PSpice Windows analysis of the network of Problem 15.§ 6. 304 Chapter 6 FET Biasing . 37. Perform a PSpice Windows analysis of the network of Problem 6.13 PSpice Windows 35. *Please Note: Asterisks indicate more difficult problems. Perform a PSpice Windows analysis of the network of Problem 1. 36.

of a system Po /Pi cannot be greater than its power input. The dc biasing of the device was then examined in detail in Chapter 4. The factor missing from the discussion above that permits an ac power output greater than the input ac power is the applied dc power. Let us now insert a control mechanism Figure 7. Po. That is. 305 . Pi. It is a contributor to the total output power even though part of it is dissipated by the device and resistive elements. stated another way. There is no set dividing line between the two. and characteristics of the transistor were introduced in Chapter 3. Perhaps the role of the dc supply can best be described by first considering the simple dc network of Fig. and that the efficiency defined by cannot be greater than 1. The question then arises as to how the ac power output can be greater than the input ac power? Conservation of energy dictates that over time the total power output. The small-signal technique is introduced in this chapter. where Po(ac) is the ac power to the load and efficiency is defined by Pi(dc) is the dc power supplied. 7. 7 7. It will determine whether small-signal or largesignal techniques should be applied. This chapter not only introduces both models but defines the role of each and the relationship between the two. a conversion Po(ac)/Pi(dc). appearance. In fact. We now begin to examine the small-signal ac response of the BJT amplifier by reviewing the models most frequently used to represent the transistor in the sinusoidal ac domain. but the application––and the magnitude of the variables of interest relative to the scales of the device characteristics––will usually make it quite clear which method is appropriate. there is an “exchange” of dc power to the ac domain that permits establishing a higher output ac power.1 Steady current established by a dc supply. There are two models commonly used in the small-signal ac analysis of transistor networks: the re model and the hybrid equivalent model. In other words.2 AMPLIFICATION IN THE AC DOMAIN It was demonstrated in Chapter 3 that the transistor can be employed as an amplifying device. The resulting direction of flow is indicated in the figure with a plot of the current i versus time. and large-signal applications are examined in Chapter 16. One of our first concerns in the sinusoidal ac analysis of transistor networks is the magnitude of the input signal.1. the output sinusoidal signal is greater than the input signal or.re CHAPTER BJT Transistor Modeling 7.1 INTRODUCTION The basic construction. the output ac power is greater than the input ac power.

nodal analysis. properly chosen. There are two schools of thought in prominence today regarding the equivalent circuit to be substituted for the transistor. 7. 7. This is clearly demonstrated by Fig. Since both models are used extensively today.1. Since we are interested only in the ac response of the circuit.3. it is indeed fortunate that transistor small-signal amplifiers can be considered linear for most applications. the graphical symbol of the device can be replaced in the schematic by this circuit and the basic methods of ac circuit analysis (mesh analysis. The parameters of the other equivalent circuit can be determined for any region of operation within the active region and are not limited by the single set of parameters provided by the specification sheet. The hybrid-parameter equivalent circuit continues to be very popular. although it must now share the spotlight with an equivalent circuit derived directly from the operating conditions of the transistor—the re model. proper amplifier design requires that the dc and ac components be sensitive to each other’s requirements and limitations.2.3 BJT TRANSISTOR MODELING Figure 7. 7.2. all the dc supplies can be replaced by a zero-potential equivalent (short circuit) since they determine only the dc (quiescent level) of the output voltage and not the magnitude of the swing of the ac output. permitting the use of the superposition theorem to isolate the dc analysis from the ac analysis. the hybrid equivalent circuit suffers from being limited to a particular set of operating conditions if it is to be considered accurate. Let us assume for the moment that the small-signal ac equivalent circuit for the transistor has already been determined. However. For the system of Fig. the re model fails to account for the output impedance level of the device and the feedback effect from output to input. Once the ac equivalent circuit has been determined. Once determined. In an effort to demonstrate the effect that the ac equivalent circuit will have on the analysis to follow. that best approximates the actual behavior of a semiconductor device under specific operating conditions.re such as that shown in Fig. Manufacturers continue to specify the hybrid parameters for a particular operating region on their specification sheets. A model is the combination of circuit elements. Any attempt to exceed the limit set by the dc level will result in a “clipping” (flattening) of the peak region of the output signal. However. The control mechanism is such that the application of a relatively small signal to the control mechanism can result in a much larger oscillation in the output circuit. to show how closely related the two models are and how a proficiency with one leads to a natural proficiency with the other. the dc levels can be ignored in the ac analysis of the network. 7.4. 7. therefore. For many years the industrial and educational institutions relied heavily on the hybrid parameters (to be introduced shortly). consider the circuit of Fig. The dc levels were simply important for determining the proper Q-point of operation. The parameters (or components) of the re model can be derived directly from the hybrid parameters in this region. while in others the re model will be used exclusively. In some analysis and examples the hybrid model will be employed. In total. and Thévenin’s theorem) can be applied to determine the response of the circuit. the peak value of the oscillation is controlled by the established dc level. In turn.2 Effect of a control element on the steady-state flow of the electrical system of Fig. In addition. The key to transistor small-signal analysis is the use of equivalent circuits (models) to be introduced in this chapter. 7. The text will make every effort. they are both examined in detail in this text. however. the coupling capacitors C1 and C2 and bypass capacitor C3 were chosen to have a very small 306 Chapter 7 BJT Transistor Modeling . however.

Note that this will result in the “shorting out” of the dc biasing resistor RE. 7. 7. Therefore.4 The network of Fig.3 following removal of the dc supply and insertion of the short-circuit equivalent for the capacitors. R1 and R2 will be in parallel and RC will appear from collector to emitter as shown in Fig. 7. Figure 7. 7. reactance at the frequency of application. permitting an isolation between stages for the dc levels and quiescent conditions. 7. If we establish a common ground and rearrange the elements of Fig. they too may for all practical purposes be replaced by a low-resistance path or a short circuit. 7.5 employ familiar components such as resistors and independent controlled sources.4.3 Transistor circuit under examination in this introductory discussion.re Figure 7. Recall that capacitors assume an “open-circuit” equivalent under dc steady-state conditions. Figure 7.3 BJT Transistor Modeling 307 .5.5 Circuit of Fig.4 redrawn for small-signal ac analysis. Since the components of the transistor equivalent circuit appearing in Fig.

can be applied to determine the desired quantities.re analysis techniques such as superposition. For the two-port (two pairs of terminals) system of Fig. for most electrical and electronic systems. the re and hybrid equivalent circuits will be introduced to complete the ac analysis of the network of Fig. the ac equivalent of a network is obtained by: 1. Note in Fig. 7. the impedance between each pair of terminals under normal operating conditions is quite important. therefore.5.1) If the input signal Vi is changed. we would expect some indication of how the output voltage Vo is related to the input voltage Vi —the voltage gain. Input Impedance. the current Ii can be computed using the same level of input impedance. which define the current gain Ai Io/Ii. A great deal more will be offered about these parameters in the sections to follow. In summary. and so on. Let us further examine Fig. let us concentrate on those parameters of a two-port system that are of paramount importance from an analysis and design viewpoint. Figure 7. Redrawing the network in a more convenient and logical form In the sections to follow. For both sets of terminals. In fact. Since we know that the transistor is an amplifying device. Removing all elements bypassed by the short-circuit equivalents introduced by steps 1 and 2 4.5 for this configuration that Ii Ib and Io Ic. Av. Thévenin’s theorem. the input impedance Zi is defined by Ohm’s law as the following: Zi Vi Ii (7. the input side (the side to which the signal is normally applied) is to the left and the output side (where the load is connected) is to the right. Setting all dc sources to zero and replacing them by a short-circuit equivalent 2. 7. 7. The input impedance Zi and output impedance Zo will prove particularly important in the analysis to follow. Zo.4 THE IMPORTANT PARAMETERS: Zi. In other words: 308 Chapter 7 BJT Transistor Modeling . Zi For the input side. the general flow is usually from the left to the right.6. 7.6 Two-port system.5 and identify the important quantities to be determined for the system. Ai Before investigating the equivalent circuits for BJTs in some detail. Replacing all capacitors by a short-circuit equivalent 3. 7.

Ai 309 . The importance of the input impedance of a system can best be demonstrated by the network of Fig. If the source were ideal (Rs 0 ).2 k . or rms values. we will find in the sections to follow that the input impedance of a transistor can be approximately determined by the dc biasing conditions—conditions that do not change simply because the magnitude of the applied ac signal has changed.4 The Important Parameters: Zi.7 Determining Zi. Zo.8. It is particularly noteworthy that for frequencies in the low to mid-range (typically 100 kHz): The input impedance of a BJT transistor amplifier is purely resistive in nature and. depending on the manner in which the transistor is employed. once the input impedance has been determined the same numerical value can be used for changing levels of applied signal. For instance.2 kΩ Vi Amplifier – – Figure 7. An oscilloscope or sensitive digital multimeter (DMM) can be used to measure the voltage Vs and Vi. 7.8 Demonstrating the impact of Zi on an amplifier’s response.2) and (7. Both voltages can be the peak-to-peak. and the system (possibly a transistor amplifier) has an input resistance of 1. The signal source has an internal resistance of 600 . as long as both levels use the same standard.re For small-signal analysis. 7. Equation (7. In addition: An ohmmeter cannot be used to measure the small-signal ac input impedance since the ohmmeter operates in the dc mode. in Fig. can vary from a few ohms to megohms. the full 10 mV would be applied to the system. peak. 7. but Rsource + V s 600 Ω 10 mV + Zi = 1.3) + V s Ii Rsense Zi + Vi Two-port System – – Figure 7. In fact. Av. The input impedance is then determined in the following manner: Ii Vs Vi Rsense Zi Vi Ii (7.7 a sensing resistor has been added to the input side to permit a determination of Ii using Ohm’s law.1) is particularly useful in that it provides a method for measuring the input resistance in the ac domain.

The level of input impedance. then Vi 1 (10 mV) 5 mV or 50% of the available signal. 7. Vi will be 93. 7. is applied to the output terminals and the level of Vo is measured with an oscilloscope or sensitive DMM.9.2 mV 1k Vi Ii 1. the applied signal has been set to zero volts.8 mV 1k 1. common-emitter. In the sections and chapters to follow. That is: The output impedance is determined at the output terminals looking back into the system with the applied signal set to zero.re with a source impedance.8 A 0. To determine Zo. Of course.10.2 mV 0. In Fig.2 k 0. for example.6 k 6.5) 310 Chapter 7 BJT Transistor Modeling . can have a significant impact on the level of signal that reaches the system (or amplifier).2% of the applied signal. or common-collector configuration and on the placement of the resistive elements.1 For the system of Fig.8 A Output Impedance. if 2 Zi 8. determine the level of input impedance.2 k .7% of the full-input signal is available at the input. Rsense + V s 2 mV 1 kΩ Zi + Vi = 1. Zo The output impedance is naturally defined at the output set of terminals.67 mV Thus.2 mV – – Two-port System Figure 7.9 Example 7. Vs. it will be demonstrated that the ac input resistance is dependent on whether the transistor is in the common-base. a signal. the input voltage must be determined using the voltagedivider rule as follows: Vi Zi ZiVs Rsource (1. only 66.2 k )(10 mV) 1.5 k 0.4) and (7. therefore. EXAMPLE 7. If Zi were only 600 .1 Solution Ii and Vs Vi Rsense Zi 2 mV 1. The output impedance is then determined in the following manner: Io V Vo Rsense Zo Vo Io (7. but the manner in which it is defined is quite different from that of the input impedance.

11 Effect of Zo Ro on the load or output current IL.5 k 16 A Voltage Gain. depending on the configuration and the placement of the resistive elements. if Zo RL.2 + 20 kΩ Zo Vo = 680 mV + V= 1 V – – Figure 7. Zo. the level of Zo should be as large as possible.10 Determining Zo. can vary from a few ohms to a level that can exceed 2 M . Solution Io and V Vo Rsense Zo 1V Vo Io 680 mV 20 k 680 mV 16 A 320 mV 20 k 42. EXAMPLE 7. the majority of the amplifier output current will pass on to the load. for frequencies in the low to mid-range (typically 100 kHz): The output impedance of a BJT transistor amplifier is resistive in nature and.4 The Important Parameters: Zi.12. For amplifier configurations where significant gain in current is desired. Av One of the most important characteristics of an amplifier is the small-signal ac voltage gain as determined by Av Vo Vi (7. It will be demonstrated in the sections and chapters to follow that Zo is frequently so large compared to RL that it can be replaced by an open-circuit equivalent. 7. determine the level of output impedance.11. 7. For the system of Fig.2. Rsense Two-port System Vs = 0 V Figure 7. Zo.12 Example 7. As demonstrated by Fig. In addition: An ohmmeter cannot be used to measure the small-signal ac output impedance since the ohmmeter operates in the dc mode. Av. Ai 311 . – In particular.re Rsource Rsense + Vs = 0 V Two-port System Io Vo Zo + V – Figure 7.6) 7.

14. determine: (a) Vi. however. 7. Depending on the configuration. (7.13. EXAMPLE 7.13 having a source resistance Rs.6) is referred to as the no-load voltage gain. the level of Vi would first have to be determined using the voltage-divider rule before the gain Vo/Vs could be calculated. can have a voltage gain in the thousands. Chapter 7 BJT Transistor Modeling 312 . the no-load voltage gain is greater than the loaded voltage gain. the voltage gain Avs or AvNL can be determined simply by measuring the appropriate voltage levels with an oscilloscope or sensitive DMM and substituting into the appropriate equation. (c) Zi. a load has not been connected to the output terminals and the level of gain determined by Eq.8) Experimentally. That is. A multistage (multiunit) system. the magnitude of the voltage gain for a loaded single-stage transistor amplifier typically ranges from just less than 1 to a few hundred. (b) Ii. That is.3 For the BJT amplifier of Fig.7) RL (open circuit) Rsource + Vs Zi + Vi + AυNL V o – – – Figure 7. AvNL Vo Vi (7. 7.13 Determining the no-load voltage gain. (d) Avs. For the system of Fig.re For the system of Fig. 7. Vi with and so that Avs Avs Vi Vs Vo Vs Vo Vs Zi ZiVs Zi Rs Zi Zi Rs Vi Vs Zi Rs Vo Vi AvNL (7. In Chapter 9 it will be demonstrated that: For transistor amplifiers.

8 k 24 mV 13. Ai 313 . Vi and Ii Zi Io Vo RL Figure 7.3.33 A 40 mV 24 mV 1.68 V 320 24 mV 13. the current gain typically ranges from a level just less than 1 to a level that may exceed 100. Ai The last numerical characteristic to be discussed is the current gain defined by Ai Io Ii (7. For the loaded situation of Fig.2 k 1.14 Example 7.8 k 1. an important quantity that can have significant impact on the overall effectiveness of a design. 7. Solution (a) AvNL (b) Ii (c) Zi (d) Avs Vs Rs Vi Ii Zi Zi Rs Vo and Vi Vi Vi Vo AvNL 7. Zo.8 k 192 (320) Current Gain.re Figure 7. 7.9) Although typically the recipient of less attention than the voltage gain. Av. In general: For BJT amplifiers.15.33 A AvNL 1.2 k 1.15 Determining the loaded current gain. it is. however.4 The Important Parameters: Zi.

7.re with and Ai Io Ii Ai Vo /RL Vi /Zi Av Zi RL Vo Zi Vi RL (7.16a. the diode equivalence of Fig. Other factors. Fortunately.3. will affect some of these parameters. In the sections and chapters to follow. the input and output signals are either 180° out of phase or in phase. For the output side. In other words. As noted in Section 7. For the base-to-emitter junction of the transistor of Fig.16b between the same two terminals seems to be quite appropriate. the results obtained with the model in place should be relatively close to those obtained with the actual transistor.8 revealed that Ic Ie (as derived from Ic the range of values of VCE.16b establishes the fact that 314 Chapter 7 BJT Transistor Modeling . Common Base Configuration In Fig.16a. but this will be discussed in Chapter 11. and the resulting phase relationship. Phase Relationship The phase relationship between input and output sinusoidal signals is important for a variety of practical reasons. 7. such as the applied frequency at the low and high ends of the frequency spectrum. recall that Ie) for the horizontal curves of Fig. a common-base pnp transistor has been inserted within the two-port structure employed in our discussion of the last few sections. In fact. The reason for the either–or situation will become quite clear in the chapters to follow.16b. 3. The forward-biased junction will behave much like a diode (ignoring the effects of changing levels of VCE) as verified by the curves of Fig.10) allows the determination of the current gain from the voltage gain and the impedance levels. the output impedance Zo. 7.7. Summary The parameters of primary importance for an amplifier have now been introduced: the input impedance Zi. the model (equivalent circuit) is chosen in such a way as to approximate the behavior of the device it is replacing in the operating region of interest. 7. all the parameters will be determined for a variety of transistor networks to permit a comparison of the strengths and weaknesses for each configuration. the current gain Ai. In Fig. 7.10) Eq. The current source of Fig. the re model for the transistor has been placed between the same four terminals. Recall that a current-controlled current source is one where the parameters of the current source are controlled by a current elsewhere in the network. (7. in general: BJT transistor amplifiers are referred to as current-controlled devices. You will recall from Chapter 3 that one junction of an operating transistor is forward-biased while the other is reverse-biased. 3. 7.5 THE re TRANSISTOR MODEL The re model employs a diode and controlled current source to duplicate the behavior of a transistor in the region of interest. however: For the typical transistor amplifier at frequencies that permit ignoring the effects of the reactive elements. the voltage gain Av.

resulting in an open-circuit equivalence at the output terminals. This same equation can be used to find the ac resistance of the diode of Fig.17.16 (a) Common-base BJT transistor.12) For the common-base configuration. 7.re Figure 7.11) The subscript e of re was chosen to emphasize that it is the dc level of emitter current that determines the ac level of the resistance of the diode of Fig. Recall from Chapter 1 that the ac resistance of a diode can be determined by the equation rac 26 mV/ID. typical values of Zi range from a few ohms to a maximum of about 50 . Ic Ie. 7. 7. (b) re model for the configuration of Fig. Substituting the resulting value of re in Fig. 7. We have therefore established an equivalence at the input and output terminals with the current-controlled source.16b if we simply substitute the emitter current as follows: re 26 mV IE (7. The result is that for the model of Fig.16a. 7.16a. 7. Zo CB (7. For the output impedance. Due to the isolation that exists between input and output circuits of Fig. 7.16b is a valid model of the actual device. providing a link between the two—an initial review would suggest that the model of Fig. Zi re CB (7.16b. if we set the signal to zero.16b will result in the very useful model of Fig. That is. then Ie 0 A and Ic Ie (0 A) 0 A. 7. where ID is the dc current through the diode at the Q (quiescent) point. with the controlling current Ie appearing in the input side of the equivalent circuit as dictated by Fig.17.17.5 The re Transistor Model .13) 315 7. it should be fairly obvious that the input impedance Zi for the common-base configuration of a transistor is simply re.17 Common-base re equivalent circuit. 7. Figure 7.

18.re In actuality: For the common-base configuration.18 Defining Zo. Vo and so that and For the current gain.to 2-M would be obtained. 7.14) Ie Ie (7. (7. 7.19. for the common-base configuration the input impedance is relatively small and the output impedance quite high.15) Figure 7. The voltage gain will now be determined for the network of Fig. 316 Chapter 7 BJT Transistor Modeling . If care were taken to measure Zo graphically or experimentally. The output resistance of the common-base configuration is determined by the slope of the characteristic lines of the output characteristics as shown in Fig. Assuming the lines to be perfectly horizontal (an excellent approximation) would result in the conclusion of Eq.13). levels typically in the range 1. IC (mA) 4 Slope = 1 ro IE = 4 mA IE = 3 mA 3 IE = 2 mA 2 IE = 1 mA 1 IE = 0 mA 0 VCB Figure 7. Ai and Ai Io Ii Ic Ie 1 CB Io RL Vi Av Av Vo Vi RL re ( Ic)RL IeZi Iere IeRL Iere RL re CB IeRL (7. typical values of Zo are in the megohm range. In general.19 Defining Av Vo /Vi for the common-base configuration.

56 k ) 168.5 The re Transistor Model 317 . 7.98)(0.56 k is connected to the output terminals..19 (i. For an npn transistor in the common-base configuration.69 A Ic RL IeRL (0. For a common-base configuration of Fig.86 mV 84. (7.69 A)(0. 0. 7. Substituting the re equivalent circuit for the npn transistor will result in the configuration of Fig. but the output set is now the collector and emitter terminals.98.14).43 and Av Vi 2 mV or from Eq. and an ac signal of 2 mV applied between the base and emitter terminals: (a) Determine the input impedance. (c) Find the output impedance and current gain. Note that the controlled-current source is still connected between the collector and base terminals and the diode between the base and 7. Figure 7.re The fact that the polarity of the voltage Vo as determined by the current Ic is the same as defined by Fig. 7. In addition. the emitter terminal is now common between the input and output ports of the amplifier.43 0.86 mV Vo 168.21a.17 with IE 4 mA.5 6.21b.56 k ) 6.20 Approximate model for a common-base npn transistor configuration.5 307. Av (c) Zo Io Ai Ii RL re (0.5 84. EXAMPLE 7.98 as defined by Eq.98)(307. the equivalence would appear as shown in Fig.4 Solution (a) re (b) Ii Vo 26 mV IE Ie Vi Zi 26 mV 4 mA 2 mV 6. 7. (b) Calculate the voltage gain if a load of 0.15) Common Emitter Configuration For the common-emitter configuration of Fig. the input terminals are the base and emitter terminals. the negative side is at ground potential) reveals that Vo and Vi are in phase for the common-base configuration.e. 7. (7.20.

Using Ohm’s law gives Vi Vbe Iere Ibre Figure 7. the base current is the input current while the output current is still Ic. we will use the following approximation for the current analysis: Ie Ib (7.17) However. since the ac beta is typically much greater than 1.18) The input impedance is determined by the following ratio: Zi Vi Ii Vbe Ib The voltage Vbe is across the diode resistance as shown in Fig. 7.re Figure 7. 318 Chapter 7 BJT Transistor Modeling . (b) approximate model for the configuration of Fig. Recall from Chapter 3 that the base and collector currents are related by the following equation: Ic Ib (7.22 Determining Zi using the approximate model. emitter terminals.16) The current through the diode is therefore determined by Ie and Ic Ie Ib ( Ib 1)Ib Ib (7.21a.22.21 (a) Common-emitter BJT transistor. The level of re is still determined by the dc current IE. 7. In this configuration.

a resistive element in the emitter leg is reflected into the input circuit by a multiplying factor . the characteristics of interest are the output set of Fig. the current Ic is 0 A and the output impedance is Zo ro CE (7. The steeper the slope.re Substituting yields Zi and Zi Vbe Ib re CE Ibre Ib (7.24.21 does not include an output impedance. typical values of Zi defined by re range from a few hundred ohms to the kilohm range. the less the level of output impedance (Zo). Vo IoRL 7.19) states that the input impedance for a situation such as shown in Fig. Note that the slope of the curves increases with increase in collector current. The re model of Fig. (7.04 k Zi For the common-emitter configuration. 7. if the applied signal is set to zero. 7.25. 7.25.25 Including ro in the transistor equivalent circuit. For the model of Fig. if the contribution due to ro is ignored as in the re model.5 ) 1. pedance is defined by Zo The voltage gain for the common-emitter configuration will now be determined . 7. but if available from a graphical analysis or from data sheets. it can be included as shown in Fig.24 Defining ro for the common-emitter configuration. In other words.26 using the assumption that Zo including ro will be considered in Chapter 8. For the output impedance.4 and increased to a level of re (160)(6. the output im.5 The re Transistor Model 319 .19) In essence.23 is beta times the value of re.5 as in Example 7. For the defined direction of Io and polarity of Vo. 7. 50 µA 40 µA 30 µA ro2 > ro1 20 µA 10 µA I B = 0 µA Slope = 1 ro 2 8 6 4 Figure 7. 7. The effect of for the configuration of Fig. For instance.23 Impact of re on input impedance. For the common-emitter configuration. IC (mA) Slope = 10 1 ro 1 Figure 7. 160 (quite typical). with maximums of about 6–7 k . 2 0 10 20 VCE Figure 7. Eq.20) Of course. typical values of Zo are in the range of 40 to 50 k . the input impedance has if re 6.

For typical parameter values. and the output impedance is ro.26: Ai and Ai Io Ii Ic Ib CE. 320 .re Figure 7. the common-emitter configuration can be considered one that has a moderate level of input impedance.21) CE.5 Given 120 and IE 3. (b) Av if a load of 2 k is applied.ro IbRL The resulting minus sign for the voltage gain reveals that the output and input voltages are 180° out of phase.26 Determining the voltage and current gain for the common-emitter transistor amplifier.22) Using the facts that the input impedance is re. Continuing gives Vo and so that and IoRL Vi Av Av IiZi Vo Vi RL re IcRL Ib re IbRL Ib re (7.2 mA for a common-emitter configuration with ro determine: (a) Zi. Figure 7. a high voltage and current gain. (c) Ai with the 2 k load. 7. The current gain for the configuration of Fig. 7.27 can be an effective tool in the analysis to follow. the equivalent model of Fig. the collector current is Ib.27 re model for the common-emitter transistor configuration. and an output impedance that may have to be included in the network analysis. 7. EXAMPLE 7.26 would establish a voltage Vo with the opposite polarity. The minus sign simply reflects the fact that the direction of Io in Fig. Chapter 7 BJT Transistor Modeling .ro Ib Ib (7.

125 975 246.6 The Hybrid Equivalent Model 321 . 7. 7. the parameters are defined at an operating point that may or may not reflect the actual operating conditions of the amplifier. the re model is applied more frequently. the model defined for the common-emitter configuration of Fig.re Solution (a) re 26 mV IE re 26 mV 3.0 250 30 k 10 — 1 S 4 Figure 7.1 20 1. f = 1 kHz) 2N4400 Voltage feedback ratio (IC = 1 mA dc.28 Hybrid parameters for the 2N4400 transistor. however.21 is normally applied rather than defining a model for the common-collector configuration. f = 1 kHz) 2N4400 Output admittance (IC = 1 mA dc. but often with the hoe parameter of the hybrid equivalent model to provide Min.0 Max. This is due to the fact that specification sheets cannot provide parameters for an equivalent circuit at every possible operating point.15 and Zi (120)(8.5 that the re model for a transistor is sensitive to the dc level of operation of the amplifier. In addition. VCE = 10 V dc. VCE = 10 V dc. VCE = 10 V dc. The quantities hie. They must choose operating conditions that they believe reflect the general characteristics of the device.5 8.125 ) 2k 8. a number of commoncollector configurations will be investigated and the impact of using the same model will become quite apparent.21): Av (c) Ai Io Ii Common Collector Configuration For the common-collector configuration. Input impedance (IC = 1 mA dc. One obvious advantage of the specification sheet listing is the immediate knowledge of typical levels for the parameters of the device as compared to other transistors.6 THE HYBRID EQUIVALENT MODEL It was pointed out in Section 7.28 are called the hybrid parameters and are the components of a small-signal equivalent circuit to be described shortly. 7.28 are drawn from the specification sheet for the 2N4400 transistor described in Chapter 3. and hoe of Fig. The values are provided at a dc collector current of 1 mA and a collector-to-emitter voltage of 10 V. (7. a range of values is provided for each parameter for guidance in the initial design or analysis of a system.5 0. VCE = 10 V dc. For the hybrid equivalent model to be described in this section. For years.2 mA 8. The result is an input resistance that will vary with the dc operating point. 7. the hybrid model with all its parameters was the chosen model for the educational and industrial communities. 7. hre. 7. The hybrid parameters as shown in Fig. In subsequent chapters.125 RL re 120 (b) Eq. f = 1 kHz) Small-signal current gain (IC = 1 mA dc. f = 1 kHz) hie hre hfe hoe 0. hfe. Presently.

the parameters of the other model are immediately available. Once developed. The subscript 11 of h11 defines the fact that the parameter is determined by a ratio of quantities measured at the input terminals. it is quite important that the hybrid model be covered in some detail in this book. Figure 7. The following set of equations (7. once the components of one are defined for a particular operating point. and therefore is discussed in detail in this chapter. In fact. If Ii is set equal to zero by opening the input leads.23) is only one of a number of ways in which the four variables of Fig. the following will result: h11 Vi Ii ohms Vo 0 (7. Our description of the hybrid equivalent model will begin with the general twoport system of Fig.29 can be related. however.23a) (7. the following will result for h12: h12 Vi Vo unitless Ii 0 (7.24) The ratio indicates that the parameter h11 is an impedance parameter with the units of ohms. If we arbitrarily set Vo 0 (short circuit the output terminals) and solve for h11 in Eq. it is called the short-circuit input-impedance parameter. Vi Io h11Ii h21Ii h12Vo h22Vo (7. A clearer understanding of what the various h-parameters represent and how we can determine their magnitude can be developed by isolating each and examining the resulting relationship. (7. the similarities between the re and hybrid models will be quite apparent. is the ratio of the input voltage to the output voltage with the input current equal to zero.” The term hybrid was chosen because the mixture of variables (V and I ) in each equation results in a “hybrid” set of units of measurement for the h-parameters. therefore.29. 7.25) The parameter h12. Since specification sheets do provide the hybrid parameters and the hybrid model continues to receive a good measure of attention. The first integer of the subscript defines the 322 Chapter 7 BJT Transistor Modeling .re some measure for the output impedance. 7. It is the most frequently employed in transistor circuit analysis.29 Two-port system.23b) The parameters relating the four variables are called h-parameters from the word “hybrid.23a). It has no units since it is a ratio of voltage levels and is called the open-circuit reverse transfer voltage ratio parameter. Since it is the ratio of the input voltage to the input current with the output terminals shorted. The subscript 12 of h12 reveals that the parameter is a transfer quantity determined by a ratio of input to output measurements.

7.32 with a new set of subscripts for the h-parameters. The last parameter. can be found by again opening the input leads to set I1 0 and solving for h22 in Eq. (7. it is the output conductance parameter and is measured in siemens (S). like h12. The notation of Fig. The term reverse is included because the ratio is an input voltage over an output voltage rather than the reverse ratio typically of interest. This parameter.23b): h22 Io Vo siemens (7.27) Ii 0 Since it is the ratio of the output current to the output voltage. Figure 7. It is called the open-circuit output admittance parameter.23b) Vo is equal to zero by again shorting the output terminals. (7. Since the parameter h11 has the unit ohm. 7. The complete “ac” equivalent circuit for the basic three-terminal linear device is indicated in Fig. let us apply Kirchhoff’s voltage law “in reverse” to find a circuit that “fits” the equation. Performing this operation will result in the circuit of Fig.26) Note that we now have the ratio of an output quantity to an input quantity.32 Complete hybrid equivalent circuit.6 The Hybrid Equivalent Model 323 . Since each term of Eq. let us now apply Kirchhoff’s current law “in reverse” to obtain the circuit of Fig.23b) has the units of current. The subscript 21 again indicates that it is a transfer parameter with the output quantity in the numerator and the input quantity in the denominator. 7. It is formally called the short-circuit forward transfer current ratio parameter. The choice of letters is obvious from the following listing: h11 → input resistance → hi h12 → reverse transfer voltage ratio → hr Figure 7.23a) has the unit volt.32 is of a more practical nature since it relates the h-parameters to the resulting ratio obtained in the last few paragraphs.31. (7. 7. the second integer defines the source of the quantity to appear in the denominator.re measured quantity to appear in the numerator.30. Since each term of Eq. that the resistance in ohms of this resistor is equal to the reciprocal of conductance (1/h22). it is represented by the resistor symbol. 7. The quantity h12 is dimensionless and therefore simply appears as a multiplying factor of the “feedback” term in the input circuit. the following will result for h21: h21 Io Ii unitless Vo 0 (7. Figure 7. Since h22 has the units of admittance. however. If in Eq.31 Hybrid output equivalent circuit. (7. which for the transistor model is conductance. The subscript 22 reveals that it is determined by a ratio of output quantities. 7. it is represented by a resistor in Fig. Keep in mind. h22. The term forward will now be used rather than reverse as indicated for h12.30.30 Hybrid input equivalent circuit. The parameter h21 is the ratio of the output current to the input current with the output terminals shorted. has no units since it is the ratio of current levels.

The networks of Figs. the lowercase letter b was added. the transistor model is a three-terminal two-port system. they are all three-terminal configurations.34 Common-base configuration: (a) graphical symbol. the letters e and c were added. respectively. The hybrid equivalent network for the common-emitter configuration appears with the standard notation in Fig. however. The h-parameters. Figure 7.33 since the potential level is the same.33 Common-emitter configuration: (a) graphical symbol. therefore. Io Ic. therefore.32 is applicable to any linear three-terminal electronic device or system with no internal independent sources. the bottom of the input and output sections of the network of Fig. called the Figure 7. 324 Chapter 7 BJT Transistor Modeling . The input voltage is now Vbe. Two additional transistor equivalent circuits. with the output voltage Vce. 7.34.33 and 7.re h21 → forward transfer current ratio → hf h22 → output conductance → ho The circuit of Fig. For the common-base configuration of Fig. 7.32 can be connected as shown in Fig. while for the common-emitter and common-collector configurations. For the common-base configuration. (b) hybrid equivalent circuit.32 was further impetus for calling the resultant circuit a hybrid equivalent circuit. a second subscript has been added to the h-parameter notation. Ii Ie. will change with each configuration.33. In each case. (b) hybrid equivalent circuit. For the transistor. even though it has three basic configurations. and through an application of Kirchhoff’s current law. To distinguish which parameter has been used or which is available. 7. The fact that both a Thévenin and Norton circuit appear in the circuit of Fig. 7. Ie Ib Ic. 7. 7. Note that Ii Ib. so that the resulting equivalent circuit will have the same format as shown in Fig. 7. Essentially. not to be discussed in this text.34 are applicable for pnp or npn transistors. 7.32. Io Ic with Veb Vi and Vcb Vo.

35. 7. Since hr is normally a relatively small quantity. It should be reasonably clear from Fig.37 for comparison.7. The resistance determined by 1/ho is often large enough to be ignored in comparison to a parallel load. and Ai are only slightly affected if they (hr and ho) are not included in the model. in the same equivalent circuit. For the common-emitter and common-base configurations. In Section 7. the magnitude of hr and ho is often such that the results obtained for the important parameters such as Zi. the magnitudes of the various parameters will be found from the transistor characteristics in the region of operation resulting in the desired small-signal equivalent network for the transistor. 7. 7. Av.37a that Ii Io + Vi hi h f Ii + Vo – – Figure 7.35. (b) common-base configuration. In fact. but not both. The resulting equivalent of Fig. 7. the hybrid equivalent and the re models for each configuration have been repeated in Fig. as shown in Fig. use either the voltage source or the current source. its removal is approximated by hr 0 and hrVo 0. resulting in a short-circuit equivalent for the feedback element as shown in Fig.37 Hybrid versus re model: (a) common-emitter configuration. Zo. 7. Ib b Ic c b Ib Ic c h ie h fe Ib β re β Ib e e (a) Ie Ic c e e Ie e Ic c e hib h f b Ib re α Ie b b (b) b e Figure 7. Figure 7. permitting its replacement by an opencircuit equivalent for the CE and CB models. 7.36 Approximate hybrid equivalent model.36 is quite similar to the general structure of the common-base and common-emitter equivalent circuits obtained with the re model.6 The Hybrid Equivalent Model 325 .35 Effect of removing hre and hoe from the hybrid equivalent circuit.re z-parameter and y-parameter equivalent circuits.

0. hoe 20 S ( mho).6.6 Given IE 2. (b) The common-base re model.28) (7.5 mA IE re (140)(10.30) (7.31) hfe re ac (7. determine: Solution (a) re hie ro 26 mV 26 mV 10. 326 Chapter 7 BJT Transistor Modeling .456 kΩ 140 Ib 1 = 50 kΩ h oe c Figure 7. e e (b) re 10.38 Common-emitter hybrid equivalent circuit for the parameters of example 7. (7. hib and hfb re 1 (7.37b. b Ib h ie 1.5 S. 7.5 mA. Figure 7. 7. note that the minus sign in Eq. 7.re hie and From Fig.37b. 7. ro 1 hob 1 0.4 2.39 Common-base re model for the parameters of example 7. hfe 140.4 ) 1.4 1. and hob (a) The common-emitter hybrid equivalent circuit.6.5 S 2M Note Fig.456 k 1 1 50 k hoe 20 S Note Fig.29) In particular.38.39.31) accounts for the fact that the current source of the standard hybrid equivalent circuit is pointing down rather than in the actual direction as shown in the re model of Fig. EXAMPLE 7.

the h-parameters are determined in the region of operation for the applied signal so that the equivalent circuit will be the most accurate available.32) VCE constant hre IB constant (unitless) (7. vo. 7. The constant values of VCE and IB in each case refer to a condition that must be met when the various parameters are determined from the characteristics of the transistor. and io. For the greatest accuracy. *The partial derivative vi/ ii provides a measure of the instantaneous change in vi due to an instantaneous change in ii. In Section 7. In Eq.34) then requires that a small change in collector current be divided by the corresponding change in base current. that hfe re that will vary significantly with interest. In other words. Equation (7.35) In each case. (7.34) the condition VCE constant requires that the changes in base current and collector current be taken along a vertical straight line drawn through the Q-point representing a fixed collector-to-emitter voltage. Since hfe is usually the parameter of greatest interest. ii.7 GRAPHICAL DETERMINATION OF THE h-PARAMETERS Using partial derivatives (calculus). It is hie IC and should be determined at operating levels.re A series of equations relating the parameters of each configuration for the hybrid equivalent circuit is provided in Appendix A. while the parameters hfe and hoe are obtained from the output or collector characteristics. (7. 7. For the common-base and common-collector configurations. is a fairly good approximation.32) through (7. The parameters hie and hre are determined from the input or base characteristics.7 Graphical Determination of the h-Parameters 327 . Assuming. The first step in determining any of the four hybrid parameters is to find the quiescent point of operation as indicated in Fig.34) hoe ic vce IB constant (siemens) (7. therefore. for this parameter first. the symbol refers to a small change in that quantity around the quiescent point of operation.35).33) hfe VCE constant (unitless) (7. such as Eqs. since it can have a real impact on the gain levels of a transistor amplifier. these changes should be made as small as possible. we demonstrate that the hybrid parameter hfe ( ac) is the least sensitive of the hybrid parameters to a change is a constant for the range of in collector current. it can be shown that the magnitude of the hparameters for the small-signal transistor equivalent circuit in the region of operation for the common-emitter configuration can be found using the following equations:* hie vi ii vi vo io ii io vo vbe ib vbe vce ic ib ic vce ic ib vbe ib vbe vce (ohms) (7. we shall discuss the operations involved with equations.8.40. 7. the proper equation can be obtained by simply substituting the proper values of vi.

we get Figure 7. 7.41 hoe determination. Substituting into Eq.34).4 V 10 10 6 100 In Fig. That is.35) for hoe.7) mA 10) A VCE 3 constant VCE 8. a straight line is drawn tangent to the curve IB through the Q-point to establish a line IB constant as required by Eq. 7. All that remains is to substitute the resultant changes of ib and ic into Eq.40.41. hfe ic ib 10 (2. In Fig. (7.re Figure 7. 328 Chapter 7 BJT Transistor Modeling . (7. A change in vCE was then chosen and the corresponding change in iC determined by drawing the horizontal lines to the vertical axis at the intersections on the IB constant line. (7. the change in ib was chosen to extend from IB1 to IB2 along the perpendicular straight line at VCE. The corresponding change in ic is then found by drawing the horizontal lines from the intersections of IB1 and IB2 with VCE constant to the vertical axis.7 (20 1.35).40 hfe determination.

The natural choice then is to pick a change in vCE and find the resulting change in vBE as shown in Fig. (7.7 Graphical Determination of the h-Parameters 329 . 7. 7.5 k Figure 7.40 through 7.33).32). resulting in a corresponding change in ib. we get hie 15 10 vbe ib VCE constant 3 6 10 (733 (20 718) mV 10) A VCE 8. (7.42.1 (2.2 2. Substituting into Eq. a line is drawn tangent to the curve VCE 8. Substituting into Eq. we get vbe (733 725) mV 8 10 3 4 10 4 hre vce IB constant (20 0) V 20 For the transistor whose characteristics have appeared in Figs.re hoe ic vce 0.43. A small change in vbe was then chosen.32). (7. 7. 7.44.4 V 10 10 1. can be found by first drawing a horizontal line through the Q-point at IB 15 A. hre.42 hie determination. The last parameter.43. For hie. 7.1) mA (10 7) V IB constant 3 IB 15 A 33 A/V 33 10 6 S 33 S 3 To determine the parameters hie and hre the Q-point must first be found on the input or base characteristics as indicated in Fig.4 V through the Q-point to establish a line VCE constant as required by Eq. the resulting hybrid small-signal equivalent circuit is shown in Fig.

and CB Transistor Configurations Parameter hi hr hf ho 1/ho CE 01 k 02.43.98 00.re Figure 7. TABLE 7.43 hre determination. As mentioned earlier. CC. the other decreased in magnitude. Figure 7. The minus sign indicates that in Eq.5 A/V0 2M 330 Chapter 7 BJT Transistor Modeling .1 Typical Parameter Values for the CE.40 through 7. 7.1 lists typical parameter values in each of the three configurations for the broad range of transistors available today. the hybrid parameters for the common-base and commoncollector configurations can be found using the same basic equations with the proper variables and characteristics.44 Complete hybrid equivalent circuit for a transistor having the characteristics that appear in Figs. within the change chosen. (7.34) as one quantity increased in magnitude. Table 7.5 10 50 25 A/V 40 k 4 CC 01 k 1 50 25 A/V 40 k CB 20 03.0 10 4 0.

note that the input resistance is much higher than that of the common-base configuration and that the ratio of output to input resistance is about 40 1.0 mA. Transistors are available today with values of hfe that vary from 20 to 600. such as in Fig. while at 3 mA. if hfe 50 at IC 1.45.5(50) 25 to 1.8 VARIATIONS OF TRANSISTOR PARAMETERS There are a large number of curves that can be drawn to show the variations of the h-parameters with temperature.45 Hybrid parameter variations with collector current. the region of operation and conditions under which it is being used will have an effect on the various h-parameters. it is 1. hfe has changed from a value of 0. For the commonemitter and common-collector configurations. the effect of the collector current on the h-parameter has been indicated.5 or 150% of that value. Logarithmic scales will be examined in Chapter 11. At 0. these quantities are also indicated on the curves.5: Transistor Amplifying Action) that the input resistance of the common-base configuration is low.1 mA. 7.5(50) 75. In Fig. 7. the quiescent point is at the intersection of VCE 5. while the output resistance is high. The parameters have all been normalized to unity so that the relative change in magnitude with collector current can easily be determined. Take careful note of the logarithmic scale on the vertical and horizontal axes. hfe is about 0. frequency.0 mA. The effect of temperature and collector current and voltage on the h-parameters is discussed in Section 7. and current. For any transistor. Consider also for the common-emitter and common-base configurations that hr is very small in magnitude. On every set of curves.0 V and IC 1.8 Variations of Transistor Parameters 331 . Since the frequency and temperature of operation will also affect the h-parameters. with Figure 7.re Note in retrospect (Section 3. Consider also that the short-circuit current gain is very close to 1. In other words.5 or 50% of its value at 1.8. For this particular situation. voltage. 7.0 mA. the operating point at which the parameters were found is always indicated. 7. The most interesting and useful at this stage of the development include the h-parameter variations with junction temperature and collector voltage and current.46.

They are quite sensitive to collector current and collector-to-emitter voltage. but it does increase measurably for higher values. Consider. There would then be no justification in eliminating hoe from the equivalent circuit on an approximate basis. on an approximate and relative basis. a magnitude that may not permit eliminating this parameter from the equivalent circuit. The fact that hfe will change from 50% of its normalized value at 50°C to 150% of its normalized value at 150°C indicates clearly that the operating temperature must be carefully considered in the design of transistor circuits. the variation in h-parameters has been plotted for changes in junction temperature. however. It is therefore a quantity that should be determined as close to operating conditions as possible. The horizontal scale is a linear scale rather than a logarithmic scale as was employed for Figs. 332 Chapter 7 BJT Transistor Modeling . In other words.45 and 7. all the parameters increase in magnitude with temperature. is hoe.45 so that a comparison between the two sets of curves can be made. the point of operation at IC 50 mA. This set of curves was normalized at the same operating point of the transistor discussed in Fig. The magnitude of hre is now approximately 11 times that at the defined Q-point. 7. Note that hie and hfe are relatively steady in magnitude while hoe and hre are much larger to the left and right of the chosen operating point. 7.re Figure 7. a change of IC from 0. It is interesting to note from Figs.47. The normalization value is taken to be room temperature: T 25°C.46. can. be considered fairly constant for the range of collector current and voltage.46 that the value of hfe appears to change the least. 7. hre is fairly constant. In Fig. whether hfe or . while the input impedance hie changes at the greatest rate. hoe and hre are much more sensitive to changes in collector voltage than are hie and hfe. In Fig. In general.46 Hybrid parameter variations with collector–emitter potential.45 and 7. however. Therefore. 7. It is indeed fortunate that for most applications the magnitude of hre and hoe are such that they can usually be ignored. re does vary considerably with collector current as one might The value of hie expect due to the sensitivity of re to emitter (IE IC) current. This increase in hoe will decrease the magnitude of the output resistance of the transistor to a point where it may approach the magnitude of the load resistor. the variation in magnitude of the h-parameters on a normalized basis has been indicated with changes in collector voltage. For values below the specified VCE. The parameter hoe is approximately 35 times the normalized value.1 to 3 mA. the specific value of current gain. 7.46. The parameter least affected.

Can you think of an analogy that would explain the importance of the dc level on the resulting ac gain? PROBLEMS § 7. 7. (a) What is the expected amplification of a BJT transistor amplifier if the dc supply is set to zero volts? (b) What will happen to the output ac signal if the dc level is insufficient? Sketch the effect on the waveform.F capacitor at a frequency of 1 kHz? For networks in which the resistor levels are typically in the kilohm range.2 Amplification in the AC Domain 1.2-k load is 5 mA and the drain on the 18-V dc supply is 3. Figure 7.3 BJT Transistor Modeling 3. Given the common-base configuration of Fig.47 Hybrid parameter variations with temperature. § 7.8 mA? 2.5. (c) What is the conversion efficiency of an amplifier in which the effective value of the current through a 2.48 Problem 4 Problems 333 . sketch the ac equivalent using the notation for the transistor model appearing in Fig.48. 7. is it a good assumption to use the short-circuit equivalence for the conditions just described? How about at 100 kHz? 4. What is the reactance of a 10.re Figure 7.

Given the BJT configuration of Fig. list the conditions under which it should be applied. AvNL.50 Problem 9 – – 334 Chapter 7 BJT Transistor Modeling . (a) For the configuration of Fig. (b) For each model. Av.4 k . Zi. determine IL for the configuration of Fig.50. 7. and Io 10 A.5 k . 7.6 kΩ Zi + Vi BJT transistor amplifier Aυ NL + Vo = 3. Ii Io + Vs 12 mV 1 kΩ Zi + BJT transistor amplifier Aυ = –180 + Vo RL 0. (b) Using the results of part (a).11 if RL 2. Io. Ai using Eq.2 k and Iamplifier 6 mA. Avs. (a) For the network of Fig. Zi. (b) Using the Zo obtained in part (a).10.7.49. Rsense 0. § 7. Zo.51 kΩ Vi = 4 mV – Figure 7. 7. 7. determine: (a) (b) (c) (d) (e) (f) Ii. Vo. 7. 8.6 V – – – Figure 7. Rsense 10 k .4 The Important Parameters: Zi.10). For the BJT amplifier of Fig. (7. determine Zo if V 600 mV. determine Vi if the applied source is changed to 12 mV with an internal resistance of 0.re 5. determine: (a) (b) (c) (d) Vi. determine Zi if Vs 40 mV. 7. Ai using the results of parts (a) and (d). (a) Describe the differences between the re and hybrid equivalent models for a BJT transistor. Ai 6. and Ii 20 A.49 Problem 8 9. Ii = 10 µA + Vs 18 mV 0.

and RL 2.2 k . 7. Problems 335 . determine the following for a common-emitter amplifier if 80. (b) Ib if Vi 30 mV. (b) Zi. resulting in an emitter current of 0. (e) Av Vo/Vi. 15. Redraw the common-emitter network of Fig.2 k . sketch the: 16.7 k .2 k .2 k ro 50 k . 25 S.4 k . (d) Vo. The input impedance to a common-emitter transistor amplifier is 1. For the common-base configuration of Fig.980. § 7.17. (c) Common-base hybrid equivalent model. with 140. (d) Common-base re equivalent model. 12.27.2 mA and Determine the following if the applied voltage is 48 mV and the load is 2. 7. Given IE (dc) 1. (b) Common-emitter re equivalent model. and ro 40 k . (b) Vo if RL 1. 7. and ro 40 k . (c) Common-base hybrid equivalent model. Determine: (a) re. hfe 100.2 mA.2 k . (e) Ai Io /Ii.5 mA.17.3 for the ac response with the approximate hybrid equivalent model substituted between the appropriate terminals.re § 7. an ac signal of 10 mV is applied.6 The Hybrid Equivalent Model 14. (f) Ib. (a) re. hre 4 10 4. 120. IE (dc) 2 mA. (a) Zi. and hoe (a) Common-emitter hybrid equivalent model. 11. determine: (a) Zi. Using the model of Fig. (c) Ic. If 0. 13. (c) Ic. (d) Common-base re equivalent model. (c) Av Vo / Vi. is 0. (e) Av. (b) Common-emitter re equivalent model. sketch the: (a) Common-emitter hybrid equivalent model. (d) Ai Io/Ii IL/Ib. For the common-base configuration of Fig.5 The re Transistor Model 10. (b) Ib. (f) Ib. (d) Zo with ro .99. (d) Av if RL 1. (c) Ai Io / Ii IL /Ib if RL 1. the emitter current is 3. 7. Given hie 2.

52 Problem 18 19. Repeat Problem 20 for RL 3. § 7. hre uration of Fig. 7. is it a good approximation to ignore the effects of 1/hoe on the total load impedance? What is the percent difference in total loading on the transistor using the following equation? % difference in total load RL RL (1/hoe) RL 100% 180. 18.re 17. 21. Figure 7. 23. Include ro. 336 Chapter 7 BJT Transistor Modeling .28 with Av 22.53 Problems 19. Redraw the network of Fig. 7. 7.53: (a) Determine Vo in terms of Vi.7 Graphical Determination of the h-Parameters 6 mA and VCE 5 V. (b) Calculate Ib in terms of Vi. Given the typical values of hie 1 k .28.2 k and hoe 20 S. 7. 21 Ib(without hre) Ib(with hre) Ib(without hre) 100% (e) Is it a valid approach to ignore the effects of hreVo for the typical values employed in this example? 20. 7. determine hfe at IC (b) Repeat part (a) at IC 1 mA and VCE 15 V.40. Given the typical values of RL 2. Redraw the network of Fig. 2 10 4.51 Problem 17 Figure 7. Include ro. (c) Calculate Ib if hreVo is ignored.51 for the ac response with the re model inserted between the appropriate terminals.3 k and the average value of hoe in Fig. (a) Using the characteristics of Fig.52 for the ac response with the re model inserted between the appropriate terminals. 7. and Av 160 for the input config- (d) Determine the percent difference in Ib using the following equation: % difference in Ib Figure 7. Repeat Problem 19 using the average values of the parameters of Fig.

7.45. determine hie at IB (b) Repeat part (a) at IB 5 A and VCE 10 V.40 and 7. 25. Include ro. determine the approximate CE hybrid equivalent model at IB 25 A and VCE 12. Determine the CE re model at IB 7. (a) Using the characteristics of Fig. (a) If hoe 20 S at IC 1 mA on Fig. 20 V.re 24.2 mA) hfe(1 mA) hfe(0. which parameter changed the least for the full range of collector current? (b) Which parameter changed the most? (c) What are the maximum and minimum values of 1/hoe? Is the approximation 1/hoe RL RL more appropriate at high or low levels of collector current? (d) In which region of current spectrum is the approximation hreVce 0 the most appropriate? 36. determine the approximate value of hre at 0.2 mA to 1 mA using the equation % change hfe(0.40 through 7. 7. can hre be ignored as a good approximation if Av 210? * 35.45. 7.47. * 28. Repeat Problem 30 for hie (same changes in IC). Problems 337 . what is the approximate value of hoe at IC 0. 31. Is it a good approximation to ignore the effects of 1/hoe in this case? 33. use Figs. 7. 7. 26. 7.2 mA and compare to a resistive load of 6.8 k . sketch the re equivalent model for the transistor having the characteristics appearing in Figs.2 mA) 100% (b) Repeat part (a) for an IC change from 1 mA to 5 mA. determine hre at IB (b) Repeat part (a) at IB 30 A. determine the magnitude of the percent change in hfe for an IC change from 0. (a) If hoe 20 S at IC 1 mA on Fig.43.40 and 7. 7. (a) Reviewing the characteristics of Fig.45 through 7. (b) Using the value of hre determined in part (a). determine hoe at IC (b) Repeat part (a) at IC 1 mA and VCE 15 V. 25 A and VCE 12. (a) Using the characteristics of Fig.42.42.43.42. * 27. Using the results of Fig.2 mA? (b) Determine its resistive value at 0. 30. (e) In which temperature range do the parameters change the least? *Please Note: Asterisks indicate more difficult problems. 7. § 7.8 k . which parameter changed the most with increase in temperature? (b) Which changed the least? (c) What are the maximum and minimum values of hfe? Is the change in magnitude significant? Was it expected? (d) How does re vary with increase in temperature? Simply calculate its level at three or four points and compare their magnitudes. (a) Using the characteristics of Fig. * 29.1 mA. Using the characteristics of Figs. 6 mA and VCE 20 A and VCE 20 A. 5 V. (a) Using Fig. 7. 7. what is the approximate value of hoe at IC 10 mA? (b) Determine its resistive value at 10 mA and compare to a resistive load of 6.5 V.41. Is it a good approximation to ignore the effects of 1/hoe in this case? 34.5 V using the characteristics of Figs.45.45. (a) Reviewing the characteristics of Fig.47.44.45. 7. 7. 7. (a) If hre 2 10 4 at IC 1 mA on Fig.8 Variations of Transistor Parameters For Problems 30 through 34. 32.

2 COMMON-EMITTER FIXED-BIAS CONFIGURATION The first configuration to be analyzed in detail is the common-emitter fixed-bias network of Fig.2 will result in the network of Fig. while the output current Io is the collector current.3. 8.1 INTRODUCTION The transistor models introduced in Chapter 7 will now be used to perform a smallsignal ac analysis of a number of standard transistor network configurations. Substituting the re model for the common-emitter configuration of Fig. Zo. note the placement of the important network parameters Zi.CHAPTER 8 BJT Small-Signal Analysis 8. the effect of an output impedance is examined as provided by the hoe parameter of the hybrid equivalent model. The networks analyzed represent the majority of those appearing in practice today. 338 . In addition. 8. The computer analysis section includes a brief description of the transistor model employed in the PSpice software package.2 that the common ground of the dc supply and the transistor emitter terminal permits the relocation of RB and RC in parallel with the input and output sections of the transistor.2. Since the re model is sensitive to the actual point of operation. The small-signal ac analysis begins by removing the dc effects of VCC and replacing the dc blocking capacitors C1 and C2 by short-circuit equivalents. it will be our primary model for the analysis to be performed. and Io on the redrawn network. In addition. To demonstrate the similarities in analysis that exist between models. Note that the input signal Vi is applied to the base of the transistor while the output Vo is off the collector. 8. Ii. Modifications of the standard configurations will be relatively easy to examine once the content of this chapter is reviewed and understood. Note in Fig. 8. respectively. 8. The effect of both parameters is reserved for a systems approach in Chapter 10.1. For each configuration. however. It demonstrates the range and depth of the computer analysis systems available today and how relatively easy it is to enter a complex network and print out the desired results. resulting in the network of Fig. The analysis of this chapter does not include a load resistance RL or source resistance Rs. recognize that the input current Ii is not the base current but the source current. a section is devoted to the small-signal analysis of BJT networks using solely the hybrid equivalent model. 8.

8.1 Common-emitter fixed-bias configuration. For Fig.3) Zo ro RC RC is frequently applied and RC (8. Ii Ib b RB c Ic Io RC Zo +Z Vi i + Vo β re β Ib ro Figure 8. Zo If ro 10 RD. and the magnitude of ro is typically obtained from the specification sheet or characteristics.2 Common-Emitter Fixed-Bias Configuration 339 . and ro.4. resulting in an open-circuit equivalence for the current source. 8. Ii Ib 0. 8.3 Substituting the re model into the network of Fig. Zi: Figure 8. the approximation RC ro Zo RC ro ohms (8. The result is the configuration of Fig. re.2. – – The next step is to determine . 8. The magnitude of is typically obtained from a specification sheet or by direct measurement using a curve tracer or transistor testing instrument.VCC RC RB Ii Vi C1 Zi E B C C2 Vi Zo Zi RB E Io Vo Ii B C Io RC Zo Vo Figure 8. C1. 8.3.4) ro 10RC Figure 8. re. when Vi 0.2) Zo: Recall that the output impedance of any system is defined as the impedance Zo determined when Vi 0. and ro have been determined will result in the following equations for the important two-port characteristics of the system. and C 2.4 Determining Zo for the network of Fig.1 following the removal of the effects of VCC. The value of re must be determined from a dc analysis of the system. permitting the following approximation: Zi re RB 10 re ohms (8. Assuming that .3 clearly reveals that Zi RB re ohms (8.2 Network of Figure 8.1) For the majority of situations RB is greater than re by more than a factor of 10 (recall from the analysis of parallel elements that the total resistance of two parallel resistors is always less than the smallest and very close to the smallest if one is much larger than the other).3. Figure 8.

5) Av RC re (8. RB 10 re Io Ii RBro (ro)(RB) (8.6). (8.5. 8.10).8) The complexity of Eq. (7. as shown in Fig.5 and 8.Av: and but The resistors ro and RC are in parallel.9) Phase Relationship: The negative sign in the resulting equation for Av reveals that a 180° phase shift occurs between the input and output signals.7) suggests that we may want to return to an equation such as Eq. complex expression. although we recognize that must be utilized to determine re. (8. Av (8. That is.6) ro 10RC Note the explicit absence of in Eqs. Ai Av Zi RC (8. which is often the case. if ro 10RC and RB 10 re. Ai: The current gain is determined in the following manner: Applying the current-divider rule to the input and output circuits. which utilizes Ao and Zi. 340 Chapter 8 BJT Small-Signal Analysis . Ai and Ai ro 10RC. However. Io with The result is Ai Io Ii Ai Io Ib Io Ii Ib Ii ro ro RC RB RB re (8. Vo Ib Ib(RC ro) Vi rc Vi re so that Vo Vo Vi (RC ro) (RC ro) re and If ro 10RC.7) Ib (ro)( Ib) ro RC (RB)(Ii) RB re and or Io Ib Ib Ii ro ro RB RB re RC and (ro RBro RC)(RB re) which is certainly an unwieldy.

04 A 2.11 10.2 Common-Emitter Fixed-Bias Configuration 341 .VCC Vo RC RB Vi 0 t Vo Vi 0 t Figure 8.71 (e) Since RB 10 re(470 k 100 Ai (c) Zo 280.6: (a) Determine re.71 24. ). 12 V 3 kΩ 470 kΩ Ii Vi 10 µ F Zi Io EXAMPLE 8.71 k ) 8.6 Example 8.1.5 Demonstrating the 180° phase shift between input and output waveforms.069 k RC 3 k RC 3k (d) Av re 10.7 V 470 k (101)(24.071 k 10.071 k 1. (d) Determine Av (with ro ).428 mA (100)(10. 8. (e) Find Ai (with ro (f) Repeat parts (c) through (e) including ro results. Solution (a) DC analysis: IB IE re (b) re Zi VCC RB ( 1)IB 26 mV IE VBE 12 V 0.1 50 k in all calculations and compare Vo 10 µ F β = 100 ro = 50 kΩ Zo Figure 8.71 ) RB re 470 k 1. (b) Find Zi (with ro ). (c) Calculate Zo (with ro ).04 A) 26 mV 2. For the network of Fig.428 mA 1.

069 k ) 3k 94. 8. 8.7.24)(1. 8. 8.24 vs. 342 Chapter 8 BJT Small-Signal Analysis .7.16 which differs slightly only due to the accuracy carried through the calculations. 3 k 280.3 VOLTAGE-DIVIDER BIAS The next configuration to be analyzed is the voltage-divider bias network of Fig.11 264. (50 k (100)(470 k )(50 k ) 3 k )(470 k 1.13 vs.7 Voltage-divider bias configuration.(f) Zo Av Ai ro RC 50 k 3 k 2. That is.071 k ) 94.71 re RBro (ro RC)(RB re) 2. Recall that the name of the configuration is a result of the voltage-divider bias at the input side to determine the dc level of VB. at the frequency (or frequencies) of operation.8 Substituting the re equivalent circuit into the ac equivalent network of Fig.83 k ro RC 10. CE. the reactance of the capacitor is so small compared to RE that it is treated as a short circuit across RE. 100 As a check: Ai Av Zi RC ( 264. When Ii b Ib c Io Zi R1 R2 e R' + Vi + Vo Zo β re β Ib ro e RC – – Figure 8. Substituting the re equivalent circuit will result in the network of Fig. VCC Io RC R1 C Ii B Vi C1 Zi E R2 RE CE Zo C2 Vo Figure 8. Note the absence of RE due to the low-impedance shorting effect of the bypass capacitor.83 k vs.8.

8. Ai For ro 10RC. (8. The parallel combination of R1 and R2 is defined by R Zi: From Fig. Vo ( Ib)(RC ro) Ib Vo Vo Vi Vi re Vi (RC ro) re RC ro re (8. the equation for the current gain will have the same format as Eq. 8.17) and Ai 8.8. 8. For ro 10RC. (8.VCC is set to zero.8 is so similar to that of Fig.3 Voltage-Divider Bias 343 . Ai Io Ii Io Ii R ro ro(R R R re ro 10RC Io Ii (ro R ro RC)(R re) (8.10) Zo: From Fig. it places one end of R1 and RC at ground potential as shown in Fig. Zi R re 0 A and Ib (8. In addition. note that R1 and R2 remain part of the input circuit while RC is part of the output circuit. That is.12) R1 R2 R1R2 R1 R2 (8. 8.3 except for the fact that R R1 R2 RB.16) re) (8. Av Vo Vi RC re (8.13) ro 10RC Since RC and ro are in parallel. Zo Av : RC RC ro (8.8.7).14) and so that and Av which you will note is an exact duplicate of the equation obtained for the fixed-bias configuration.15) ro 10RC Ai: Since the network of Fig.11) 0 mA.8 with Vi set to 0 V resulting in Ib Zo If ro 10RC. 8.

Zi.2.81 V VBE 2.2 k )(22 V) 56 k 8. 8.8 kΩ 56 kΩ 10 µ F Vi Ii 8.5 k ) 135 k Using the approximate approach.9.7 V 2.2 kΩ Zi 1. determine: re. 22 V Io 6.18) ro 10RC. Ai Io Ii R R (8. Av Zi RC (8.81 V 2.And if R 10 re.5 kΩ 10 µF 1/hoe 50 k and compare re- Vo β = 90 Zo 20 µ F Figure 8. (8. R 10 re and As an option. Ai Io Ii Ai Phase relationship: between Vo and Vi. VB VE 344 Chapter 8 10(8. Solution (a) DC: Testing RE 10R2 (90)(1. Av (ro ). Zo (ro ).19) The negative sign of Eq.2 k 0. ).9 Example 8.11 V BJT Small-Signal Analysis .2 k ) 82 k (satisfied) R2 R1 VB R2 VCC (8.14) reveals a 180° phase shift EXAMPLE 8.2 For (a) (b) (c) (d) (e) (f) the network of Fig. Ai (ro The parameters of parts (b) through (e) if ro sults.

15 k (90)(18.41 mA R1 R2 (56 k ) (8. 6.8 k )(7. 10(6. The re equivalent model is substituted in Fig.4 CE EMITTER-BIAS CONFIGURATION The networks examined in this section include an emitter resistor that may or may not be bypassed in the ac domain. The effect of ro is to make the analysis a great deal more complicated.15 k 1.15 k ) 7. and considering the fact that in most situations its effect can be ignored.04 is not 1.98 k vs.76 73.6 k satisfied.04 There was a measurable difference in the results for Zo.11 will result in Vi or Vi Ib re Ib re Ie RE ( 1)IbRE 8.8 k 50 k RC ro 5.3 vs.66 k ) 64. 8.44 The condition ro 10RC (50 k 324. Therefore.15 k 10(1.5 k 1.35 k (c) Zo RC 6. However.15 k )(50 k ) 6. Therefore.8 k ) 68 k ) is not satisfied.2 k ) 7.98 k Av re 18.35 k RC ro 6. the effect of ro will be discussed later in this section. and Ai because the condition ro 10RC was not satisfied.11. 8.44 ) 7. 8.11 V 1.44 26 mV IE 26 mV 1. Av.15 k 1.44 re (e) The condition R 10 re (7.8 k 368.8 k 6. Ai (f) Zi Zo R R re (90)(7.66 k 1. Unbypassed The most fundamental of unbypassed configurations appears in Fig.3 vs. it will not be included in the current analysis.41 mA 18.IE re (b) R Zi VE RE 2.66 k ) 16. 8.4 CE Emitter-Bias Configuration 345 .76 (d) Av 18. Applying Kirchhoff’s voltage law to the input side of Fig.8 k RC 368.15 k 1. We will first consider the unbypassed situation and then modify the resulting equations for the bypassed configuration.66 k 5. 73.15 k R re 7. but note the absence of the resistance ro.10. Ai (ro R ro RC)(R re) (50 k (90)(7.

8.11.10 CE emitter-bias configuration.20) Zb RE is normally much greater than 1.24) Av : Ib and Vo Io RC Vi R Zb C with Av Vo Vi RC Zb (8. and the input impedance looking into the network to the right of RB is Zb re Vi Ib re ( 1)RE β The result as displayed in Fig.12 reveals that the input impedance of a transistor with an unbypassed resistor RE is determined by Zb Since re ( 1)RE (8.VCC Ii b Ib c + RC RB Ii Vi C1 Zo RE Zi RE Io Vo C2 Vi RB e Ie = ( β + 1)Ib Zi Zb RC + β re β Ib Io Zo Vo – – Figure 8.10.12 Defining the input impedance of a transistor with an unbypassed emitter resistor. (8. 8. Eq.11 Substituting the re equivalent circuit into the ac equivalent network of Fig.21) can be further reduced to Zb Zi: Returning to Fig. Ib alent. The result is RB Zb (8. the approximate equation is the following: Zb re (re RE RE) (8. 8.21) Figure 8. we have Zi Zo: With Vi set to zero. Figure 8.25) Vi Zb IbRC 346 Chapter 8 BJT Small-Signal Analysis .22) 0 and Ib can be replaced by an open-circuit equivZo RC (8.23) RE (8. and Zb Since RE is often much greater than re.

The equations were included to remove the nagging question of the effect of ro on the important parameters of a transistor configuration. Ai: The magnitude of RB is often too close to Zb to permit the approximation Ib Ii. Applying the current-divider rule to the input circuit will result in Ib and In addition. Zi: Zb re ( 1 1) (RC RC /ro RE)/ro RE (8.29) Phase relationship: The negative sign in Eq.Substituting Zb (re RE) gives Av Vo Vi RE.25) again reveals a 180° phase shift between Vo and Vi. Each equation can be derived through careful application of the basic laws of circuit analysis such as Kirchhoff’s voltage and current laws.30) 8. Note in each case.26) and for the approximation Zb Note again the absence of from the equation for Av. Effect of ro: The equations appearing below will clearly reveal the additional complexity resulting from including ro in the analysis.4 CE Emitter-Bias Configuration 347 . (8. source conversions. that when certain conditions are met.28) RBIi RB Zb RB RB Ib Zb or Zi RC (8. the equations return to the form just derived. The derivation of each equation is beyond the needs of this text and is left as an exercise for the reader. and so on. however. Thévenin’s theorem. Av Vo Vi RC RE (8. and so that Ai Ib Ii Io Io Ib Io Ii RB and Ai Io Ii Ai RB Av Io Ib Ib Ii RB Zb RB Zb (8.27) RC re RE (8.

1 . For RE 1 k : 1 1 and re RE 1 100 Zo 1 10 1000 RC 51ro 1 0. Therefore. Zo which was obtained earlier.20). re 10 . ro re. The 100.33) Any level of ro Av Vo Vi 348 Chapter 8 BJT Small-Signal Analysis . all the equations derived earlier will result.02 50 which is certainly simply RC. Zb re ( re ( 1 1). 1)RE (RC RE)/ro 1)RE which compares directly with Eq.31) Typically 1/ and re/RE are less than one with a sum usually less than one. (8. the following equation is an excellent one for most applications: Since Zb Zo: Zo RC ro (ro 1 However.34) RC (8. Av : RC 1 Zb 1 re ro RC ro RC ro (8.32) (re RE) ro 10(RC RE) (8. and Zo RC ro 1 1 which can be written as Zo RC ro 1 1 1 re RE re RE re) re RE (8. and result is a multiplying factor for ro greater than one.Since the ratio RC/ro is always much less than ( Zb For ro 10(RC RE). if ro 10(RC RE). In other words.

99 349 35. (b) Zi.89 A 8.56 k RB ( 1)RE ( 1)IB (121)(46.36) Bypassed If RE of Fig.4 CE Emitter-Bias Configuration . For the network of Fig. (d) Av. 8. (8. Av Vo Vi RC Zb (8. 20 V (c) Zo. Eqs.13.34 mA 26 mV IE 26 mV 4. 2.34 mA 5.3.35) ro 10RC as obtained earlier.56 kΩ CE 10 µ F Figure 8.10 is bypassed by an emitter capacitor CE. 8.7 V 470 k (121)0.1 through 8. without CE (unbypassed). the complete re equivalent model can be substituted resulting in the same equivalent network as Fig. ro = 40 kΩ Zi 0.13 Example 8.The ratio re ro 1 Vo Vi RC Zb 1 RC ro RC ro and Av For ro 10RC.9) are therefore applicable.2 kΩ 470 kΩ 10 µ F Vo C2 10 µ F Vi Ii C1 Zo EXAMPLE 8. Io (e) Ai. 8. Solution (a) DC: IB IE and re VCC VBE 20 V 0.3 β = 120. determine: (a) re.3. Av Zi RC (8.5 A) 4. Ai: The determination of Ai will be left to the equation Ai using the above equations.

28 (a significant increase) (120)(470 k ) 470 k 718. Zb and (c) Zo (d) ro Av Zi (re 10(RC 10(2.(b) Testing the condition ro 40 k 40 k Therefore.2 k 10RC is satisfied.34 k 67. (8. EXAMPLE 8.89) RC 2.89 RC Zb (120)(2.4 Repeat the analysis of Example 8.99 .2 k RE).2 k 5.99 (e) Ai RB RB Zb 367. 0.2 k ) 67. determine (using appropriate approximations): (a) re.14.92 compared to 104.2 k 104.99 67.5 For the network of Fig.8 119. and re 5. Zi (c) Zo (d) Av RC 2.92 k 560 ) RB Zb 470 k 59.82 RB Zb 470 k RB re 718. Solution (a) The dc analysis is the same.93 using Eq. Therefore.6 k (satisfied ) 10(2.92 k RC 2. (c) Zo.76 k ) RE) 120(5.27): Av Zi 59.3 with CE in place. (b) RE is “shorted out” by CE for the ac analysis.34 k ( 3.70 ) EXAMPLE 8. 8. Vo Vi 3.2 k RC re 2.92 k RC/RE.28): Ai RB/(RB Zb).56 k ) 27. (8. Therefore. (d) Av. compared to (e) Ai Av 3.8 470 k (120)(5.99 717. Chapter 8 BJT Small-Signal Analysis 350 . (b) Zi. (e) Ai.85 using Eq.

2 kΩ 90 kΩ Vi Ii Zi C1 10 kΩ 0.14 Example 8.2 kΩ 0.64 10(10 k ) (satisfied) (16 V) 0. The testing conditions of ro 10 (RC the appropriate approximations yields Zb Zi RE RB Zb 8.15.4 CE Emitter-Bias Configuration + – Figure 8.68 kΩ C2 β = 210.68 kΩ Vo R R1 R2 9k Zi Vi R' Figure 8.16 V Io 2.47 k RE) and ro 142.8 k 9k 142. ro = 50 kΩ Zo CE Vo Solution (a) Testing RE 10R2 (210)(0.6 V 10 k 0.8 k 8.8 k VB R2 R1 VE IE re R2 VB VE RE VCC VBE 100 k 10 k 90 k 1.9 V 0.9 V 1.6 V 0.15 The ac equivalent circuit of Fig.68 k 26 mV IE 26 mV 1.7 V 1.14. + Zo – – + 10RC are both satisfied.68 k ) 142.11 only by the fact that now RB Ii Io 10 kΩ 90 kΩ 2.324 mA 19. The resulting configuration is now different from Fig.324 mA (b) The ac equivalent circuit is provided in Fig. 8. Using 351 . 8. 8.5.

47 k Av ( 3.5 EMITTER-FOLLOWER CONFIGURATION When the output is taken from the emitter terminal of the transistor as shown in Fig. the network is referred to as an emitter-follower.17.2 k 144. but the ap352 Chapter 8 BJT Small-Signal Analysis . Solution (a) The dc analysis is the same. For the dc analysis.6 Repeat Example 8. while for the ac analysis. the resistor RE in the equations above is simply RE1 with RE2 bypassed by CE.24) RC 2.2 k RC 3.(c) Zo (d) Av (e) Ai RC 2.1 Another variation of an emitter-bias configuration appears in Fig. The output voltage is always slightly less than the input signal due to the drop from base to emitter. and re 19.83 k (e) Ai Av ( 112.02) RL 2.12 k 2. 8.2 k 12.2 k 112.24 0.83 k (c) Zo RC 2.16.2 k 2.02 (a significant increase) (d) Av re 19.68 k RE Zi 8. re (210)(19.47 EXAMPLE 8. VCC Io RC RB C1 Vi Ii RE Zi RE Zo 1 C2 Vo 2 CE Figure 8. 8.16 An emitter-bias configuration with a portion of the emitter-bias resistance bypassed in the ac domain. 8.2 k RC 2.5 with CE in place.64 .12 k (b) Zb Zi RB Zb 9 k 4. the emitter resistance is RE1 RE2.64 k Zi 2.64 ) 4.

8. proximation Av 1 is usually a good one. The effect of ro will be examined later in the section.37) (8. where a load is matched to the source impedance for maximum power transfer through the system. Other variations of Fig. 8. Ii b Ib c + β re Zi Vi RB e Zb RE Io Zo Ie = ( β + 1) Ib β Ib + Vo – – Figure 8. Zi: The input impedance is determined in the same manner as described in the preceding section: Zi with Zb re RB Zb ( 1)RE (8.5 Emitter-Follower Configuration . because the collector is grounded for ac analysis.38) 353 8. both Vo and Vi will attain their positive and negative peak values at the same time. In fact. 8. which is the direct opposite of the standard fixed-bias configuration. That is. Unlike the collector voltage.18. The fact that Vo “follows” the magnitude of Vi with an in-phase relationship accounts for the terminology emitterfollower.17 Emitter-follower configuration. The emitter-follower configuration is frequently used for impedance-matching purposes.18 Substituting the re equivalent circuit into the ac equivalent network of Fig.17 will result in the network of Fig. 8. Substituting the re equivalent circuit into the network of Fig.17. It presents a high impedance at the input and a low impedance at the output. the emitter voltage is in phase with the signal Vi.17 that draw the output off the emitter with Vo Vi will appear later in this section.17.VCC RB Ii Vi C1 E Zi B C C2 Vo Io RE Zo Figure 8. The resulting effect is much the same as that obtained with a transformer. it is actually a common-collector configuration. The most common emitter-follower configuration appears in Fig. 8.

41) RE Ie Vo Ie RE Zo + Vi If we now construct the network defined by Eq.19 Defining the output impedance for the emitter-follower configuration. That is.42) – Figure 8. the configuration of Fig.or and Zb Zb (re RE) RE (8.19 will result. Vi is set to zero and Zo RE re (8. (8.40) Zo: The output impedance is best described by first writing the equation for the current Ib: Ib and then multiplying by ( Ie Substituting for Zb gives Ie or but and so that re Vi Zb 1) to establish Ie. 8.39) (8. RE Av Vo Vi 354 Chapter 8 BJT Small-Signal Analysis .44) and Av Since RE is usually much greater than re. Since RE is typically much greater than re. ( 1)Ib ( 1) Vi Zb ( re [ re/( ( re 1 Ie 1)Vi ( 1)RE Vi 1)] 1) re Vi re RE re (8. the following approximation is often applied: Zo re (8.19 can be utilized to determine the voltage gain through an application of the voltage-divider rule: Vo Vo Vi REVi RE re RE RE re 1 re RE and (8.43) Av: Figure 8.41). To determine Zo.45) (8.

Zo RE re (8.46) RB RB Zb Zb ( 1) 1)Ib or and or so that Ai Ib Ii Io Io Ib and since ( Ai or Ai Av (8. Effect of ro: Zi: ( 1)RE re (8. 8.18.44) and earlier discussions of this section.47) Phase relationship: As revealed by Eq.5 Emitter-Follower Configuration 355 .Ai: From Fig. (8. Ib RBIi RB Zb RB RB Ie ( Io Ii Io Ib Ib Ii ( 1) 1) RB . Zo and since ro re.50) ro RE re 8. RB Zb Zi RE (8. Zb re ( 1)RE which matches earlier conclusions with Zb Zo: Zo Using 1 .51) Any ro (re RE) (8.48) Zb RE 1 ro If the condition ro 10RE is satisfied.49) ro 10RE ro RE re ( 1) (8. Vo and Vi are in phase for the emitter-follower configuration.

(c) Zo. (f) Repeat parts (b) through (e) with ro 25 k and compare results. 8.53) EXAMPLE 8.7 V 20.20 Example 8.42 A) 2.Av: Av ( 1)RE/Zb RE 1 ro 1 (8. (e) Ai. But so that and Zb Av Av RE (re RE) re RE RE ro 10RE (8.42 A 220 k (101)3. (d) Av. (b) Zi.52) If the condition ro 10RE is satisfied and we use the approximation Av RE Zb (re RE) .062 mA IE BJT Small-Signal Analysis IE re 356 Chapter 8 . Solution (a) IB VCC VBE RB ( 1)RE 12 V 0.3 kΩ Zo Figure 8.61 2. 12 V 220 kΩ 10 µ F Vi Ii β = 100. determine: (a) re.062 mA 26 mV 26 mV 12.7. ro = ∞ Ω 10 µ F Vo Io Zi 3.3 k ( 1)IB (101)(20.20.7 For the emitter-follower network of Fig.

67 versus Ai Av (0. the results for Zo and Av are the same.61 ) (101)(3.7 k RB Zb 220 k 295.996) 40.3 k )/295. In this case RB is again replaced by the parallel combination of R1 and R2.56 k 132.61 ) with Zi Zo Av 1.261 k 333.3 k RE 334.5 Emitter-Follower Configuration 357 .56 k RB Zb 220 k 334.3 k 25 k which is not satisfied.22 will also provide the input/output characteristics of an emitter-follower but includes a collector resistor RC.06 (f) Checking the condition ro 25 k ( 1 33 k (100 1 1)3.3 k 1 25 k matching the earlier result.43 k 295. Zb re 1)RE RE ro (100)(12. through (8.56 re 3. The network of Fig.72 k obtained earlier RE re 12.7 k 3.56 k RB Zb Zi RE 132.996 1 ( (100 1)(3.15 k vs.3 k 10RE.3 k 12.261 k 294.37) R1 R2. The results suggest that for most applications a good approximation for the actual results can be obtained by simply ignoring the effects of ro for this configuration. Therefore.61 Vi 0.72 k 3.996 1 (100)(220 k ) RB 220 k 334.21 is a variation of the network of Fig. Equations (8.(b) Zb Zi (c) Zo (d) Av (e) Ai re ( 1)RE (100)(12. In general. 8.61 12.3 k ) 1. we have 10(3.47) are changed only by replacing RB by R The network of Fig. 8.56 as obtained earlier 1)RE/Zb RE 1 ro 0. even though the condition ro 10RE was not satisfied. The input impedance Zi and output impedance Zo are unaffected by RC since it is not reflected into the base or emitter equiv8. with Zi only slightly less.3 k 3. which employs a voltage-divider input section to set the bias conditions. 8.72 k RE re 3. therefore.3 k ) 39.7 k 126.3 k Vo RE RE re 3.3 k 12. 132.17.

55) Io RC ( Ic )RC IeRC BJT Small-Signal Analysis . Zi: Zi Zo: Zo Av : Vo 358 Chapter 8 RE re (8. with the commonbase re equivalent model substituted in Fig. The standard configuration appears in Fig.22 Emitter-follower configuration with a collector resistor RC.6 COMMON-BASE CONFIGURATION The common-base configuration is characterized as having a relatively low input and a high output impedance and a current gain less than 1.VCC VCC R1 Ii Vi C1 Zi R2 C2 Vo Io RE Zo Zi Vi C1 R1 RC C2 Vo R2 Io RE Zo Figure 8. The transistor output impedance ro is not included for the common-base configuration because it is typically in the megohm range and can be ignored in parallel with the resistor RC. 8. The voltage gain. 8.23 Common-base configuration.24 Substituting the re equivalent circuit into the ac equivalent network of Fig. In fact. 8.23.24. Figure 8.54) RC (8. Figure 8. can be quite large. however. the only effect of RC will be to determine the Q-point of operation. alent networks.23. 8.21 Emitter-follower configuration with a voltagedivider biasing arrangement. Ii Ie E Zi RE B VEE VCC C Ic Io RC + Vi + Vo Zo e Ie Ic c Io + Vi Ii RE Zi re α Ie + Vo Zo RC – – – – Figure 8.

25 Example 8. Zo. 8.57) Phase relationship: The fact that Av is a positive number reveals that Vo and Vi are in phase for the common-base configuration.3 mA 26 mV 26 mV 20 IE 1.3 V 1k 1.98 1 8.61 re RC 5 k RC 5k 250 re 20 0.25. Effect of ro: For the common-base configuration. For (a) (b) (c) (d) (e) the network of Fig.3 mA RE re 1 k 20 19. – Solution (a) IE re (b) Zi (c) Zo (d) Av (e) Ai VEE RE VBE 2 V 0.8 + Vo Ii 1 kΩ Zi 2V + Vo α = 0. determine: re. 10 µ F Ie 10 µF Io 5 kΩ 8V Zo EXAMPLE 8.8. Zi. ro 1/hob is typically in the megohm range and sufficiently larger than the parallel resistance RC to permit the approximation ro RC RC. Ai.56) and Vo Vi re yields Ie Io Ai Io Ii Ie Ii Ii 1 (8.98 ro = 1 MΩ – Figure 8.6 Common-Base Configuration 359 .with so that Vo Av A i: and with Assuming that RE Ie Vi re Vi RC re RC re RC re (8. Av.7 V 1k 1.

Some of the steps to be performed below are the result of experience working with such configurations. Substituting the equivalent circuit and redrawing the network will result in the configuration of Fig.27 Substituting the re equivalent circuit into the ac equivalent network of Fig.26 employs a feedback path from collector to base to increase the stability of the system as discussed in Section 4. 8.12.26 Collector feedback configuration. The effects of a transistor output resistance ro will be discussed later in the section. VCC RC RF C Ii Vi C1 E Zi B Zo Io C2 Vo Figure 8. IbRC RC V re i 360 Chapter 8 BJT Small-Signal Analysis . 8. However. 8.26. It is not expected that a new student of the subject would choose the sequence of steps described below without taking a wrong step or two.27. the simple maneuver of connecting a resistor from base to collector rather than base to dc supply has a significant impact on the level of difficulty encountered when analyzing the network.7 COLLECTOR FEEDBACK CONFIGURATION The collector feedback network of Fig.8. Since Ib is normally much larger than I . B – Ib RF I' + C Ic Io + Vi Ii Zi + RC Zo V o β re β Ib – Zi: with and I Vo Io Io and but and Vo Ib Vo Ib ( Ib)RC Vi re Vi R re C Vo RF IoRC Ib I Vi – Figure 8.

59) RF Ib = 0 A Vi = 0 β re β Ib = 0 A RC Zo Figure 8. 8. the network will appear as shown in Fig.27. Av: At node C of Fig. Io RC ( Ib)RC Vi R re C Vo Vi RC re (8.28. 8.7 Collector Feedback Configuration 361 .58) so that or Zi Zo: If we set Vi to zero as required to define Zo. The effect of re is removed and RF appears in parallel with RC and Zo RC RF (8. Ib Substituting Ib I and Io Vo Vi/ re gives us Vo and Av 8. I The result is Vi Vi or Ib re Ii re Vi 1 Zi Vi Ii (Ii I ) re 1 RC 1 RF re re 1 RF RC re Ii re reVi Ii re I re Vo RF Vi Vo RF Vi RF RCVi reRF Vi RF 1 1 RF RC V re i and re RC re 1 1 r RF RC eRC but RC is usually much greater than re and 1 re re Zi 1 re RC RF re 1 RC RF (8.28 Defining Zo for the collector feedback configuration. Io Ib Ib.Therefore.60) I For typical values.

Ai and Ai Io Ii Io Ii RF RC RF RC (8. we have Ib re Ii)RF Ib re and Substituting Ib Ib RF RF Ii RF RC) IbRC IiRF 0 Ib( re Io/ from Io Io Ib yields ( re Io RF RC) RFIi RF IiRF and re RC Ignoring re compared to RF and RC gives us Ai For RC RF.63) Recognizing that 1/RF 0 and applying the condition ro RC 1 RF Zi 1 re RC RFre but typically RC/RF 1 and Zi 1 1 re RC RFre 362 Chapter 8 BJT Small-Signal Analysis .Ai: Applying Kirchhoff’s voltage law around the outside network loop yields Vi VRF (Ib Vo 0 IoRC 0 and Using Io Ib. (8. Effect of ro: Zi: A complete analysis without applying approximations will result in 1 Zi 1 re RC ro RF 1 RF RC ro RFre 10RC. (8.62) Io Ii RF RF RC (8.61) Phase relationship: The negative sign of Eq.60) reveals a 180° phase shift between Vo and Vi.

68) Since RF re.65) as obtained earlier. Zo RC RF (8. For (a) (b) (c) (d) (e) (f) the network of Fig. Av ro RC re ro RC 1 RF For ro 10RC.69) and since RC/RF is typically much less than one. 8.29. Zo: Including ro in parallel with RC in Fig.66) ro 10RC ro RC RF (8. 8. Ai.9 20 k and compare results.28 will result in Zo For ro 10RC.7 Collector Feedback Configuration 363 . Repeat parts (b) through (e) with ro RC re (8. Av as obtained earlier. RF RC EXAMPLE 8. RC re RC 1 RF ro 10RC Av (8. Zo. Av. 8. determine: re. Zi.or Zi re 1 RC RF ro 10RC (8.67) (8. RF RC RC. For the common condition of RF Zo Av : 1 RF Av 1 1 (r R ) re o C ro RC RF RC ro 10RC.64) as obtained earlier. (8.70) ro 10RC.

02 (c) Zo RC RF 2.5 above 364 Chapter 8 .21 50(11.7 k 180 k 0.35 k vs.21 ) 560.66 k above BJT Small-Signal Analysis vs.7 k 20 k 1 1 RF 180 k 1 1 RC ro Zi 1 1 02. ro = ∞ Ω Zo Figure 8.7 kΩ 180 kΩ Ii Vi 10 µF Zi Io Vo 10 µF β = 200.53 A) 2.66 k 27 k RC (d) Av 240. Therefore.7 k ) RF RC 50 (f) Zi: The condition ro 10RC is not satisfied. Solution (a) IB IE re (b) Zi 9 V 0.015 11.45 10 0.006 10 3 1.7 k 20 k 0 re RF RFre (200)(11.21 1 RC RF 1 200 2.7 k 180 k 2.9V 2.21) 180 k (180 k )(11.38 k 1 180 k 1 0.21 re 11.32 mA 26 mV 26 mV 11.9.32 mA IE 11.21 2.21 ) 2.86 11.7 k RF RC 11.7 Zo: Zo ro RC RF 20 k 2.29 Example 8. R C ro 2.7 k 180 k 2. 2.5 0.53 A ( 1)IB (201)(11.64 10 3 617.21 re (200)(180 k ) RF (e) Ai 180 k (200)(2.005 0.7 V VCC VBE 180 k (200)2.013 3 0. 560.18 10 3 1.

38 k 180 k (2.013 209. The derivations are left as an exercise at the end of the chapter.38 k ) 1 0.30 Collector feedback configuration with an emitter resistor RE. (8.72) (8. Eqs.56 1 (r R ) re o C ro RC RF 10 6 1 180 k 1 1 11.38 k ) 8.56) For the configuration of Fig.94 vs.21 2. 8.7 2.73) RC) (8.71) RC RF RC RE (8.71) through (8.86 above 617.30. Zi: Zi 1 RE (RE RF Zo: Zo Av : Av A i: Ai 1 1 (RE RF 8. Ai: Ai Av Zi RC 240.74) 365 .7 k 47.92 10 2](2.74) will determine the variables of interest.Av: 1 RF Av 1 [5. 50 above ( 209.7 Collector Feedback Configuration RC) (8.56 vs. VCC RC RF Ii Vi C1 Zi RE Zo Io Vo C2 Figure 8.

32 Substituting the re equivalent circuit into the ac equivalent network of Fig.31 has a dc feedback resistor for increased stability.31. yet the capacitor C3 will shift portions of the feedback resistance to the input and output sections of the network in the ac domain. the capacitor will assume a shortcircuit equivalent to ground due to its low impedance level compared to the other elements of the network. RF1 re (8. The small-signal ac equivalent circuit will then appear as shown in Fig.77) ro 10RC ro RF2 RC Ib R Vo . The portion of RF shifted to the input or output side will be determined by the desired ac input and output resistance levels. 8.76) RC RF2 (8.32. 8. At the frequency or frequencies of operation. Ii + Zi Vi RF 1 Ib Io + Vo Zo β re β Ib ro RF 2 RC – Zi: Zi Zo: Zo For ro 10RC.75) RC RF2 ro (8.8.8 COLLECTOR DC FEEDBACK CONFIGURATION The network of Fig. 8.31 Collector dc feedback configuration. Zo Av : R and 366 Chapter 8 BJT Small-Signal Analysis – Figure 8. VCC RC RF 1 RF 2 Io Vo C2 C3 C1 Vi Ii Zi Zo Figure 8.

but and so that Av For ro 10RC.8 Collector DC Feedback Configuration 367 . (8.82) Phase relationship: The negative sign in Eq. RF1 and Ai Io Ii Ai Io Ii re RF1(ro RF2) RF1(ro RF2 RC) (8. 8. Av Ai: For the input side. Ib RF1Ii RF1 re Vo Vi Vo Ib Vi re Vi R re Vo Vi ro RF2 RC re (8. Ai Io Ii ro RF2 or Io Ib R R RC R Ib R RC Io Ib R RC Ib Ii RF1 RF1 re RC) R ro R F 2 R and Ai Io Ii (RF1 RF1R re)(R (8.78) clearly reveals a 180° phase shift between input and output voltages.79) or Ib Ii RF1 RF1 re and for the output side using R Io The current gain.78) RF2 RC re ro 10RC (8.81) RF1 10 re so that 1 RC ro RF2 Zi RC or Ai Io Ii Av (8.80) RF1 Since RF1 is usually much larger than re.

EXAMPLE 8. we find 30 k 10(3 k ) 30 k which is satisfied through the equals sign in the condition.7 V (120 k 68 k ) (140)3 k 11. 8.39 k The ac equivalent network appears in Fig. Therefore.62 mA 26 mV 26 mV 9.62 mA (b) re (140)(9. ro = 30 kΩ Figure 8. Zi RF1 re 1.87 k 3k 68 k 368 Chapter 8 BJT Small-Signal Analysis . 120 kΩ 68 kΩ 0.92 ) 1. 3 kΩ Ai.6 A 608 k IE ( 1)IB (141)(18. 8. 8.37 k 120 k 1.39 k + Vi Ib Ii 120 kΩ Zi Io + Vo Zo β re 1. determine: re.395 kΩ β Ib 140 Ib ro 30 kΩ 68 kΩ 3 kΩ – – Figure 8. Solution (a) DC: IB VCC RF VBE RC 12 V 0. Zo RC RF2 2.01 µF Ii Vi 10 µF Zi Io Vo 10 µF Zo β = 140.33 Example 8. Zo.3V 18. Av.34. (c) Testing the condition ro 10RC.92 re IE 2.10 For (a) (b) (c) (d) (e) the network of Fig.33.33. 12 V Zi.6 A) 2.34 Substituting the re equivalent circuit into the ac equivalent network of Fig.10.

the dc analysis associated with use of the re model is not an integral part of the use of the hybrid parameters. hoe 1/ro.14 140 1. Fixed-Bias Configuration For the fixed-bias configuration of Fig. when the problem is presented. 140 3k 30 k 68 k 140 1 0. RF2 RC 68 k 3 k re 9. a brief overview of some of the most important will be included in this section to demonstrate the similarities in approach and the resulting equations. hfe lated by the following equations as discussed in detail in Chapter 7: hie . the small-signal ac equivalent network will appear as shown in Fig.35 Approximate common-emitter hybrid equivalent circuit. Since the various parameters of the hybrid model are specified by a data sheet or experimental analysis. that the hybrid parameters and components of the re model are rere. Although time and priorities do not permit a detailed analysis of all the configurations discussed thus far.(d) ro Av 10RC.92 2.8 8. 8.9 APPROXIMATE HYBRID EQUIVALENT CIRCUIT The analysis using the approximate hybrid equivalent circuit of Fig. Keep in mind.36 for the common-base configuration is very similar to that just performed using the re model.92 289.37.9 Approximate Hybrid Equivalent Circuit 369 .87 k 9. e Ie hib hfb Ie hob c b b Figure 8. 8. and hib re (note Appendix A). the parameters such as hie. and so on. hib. therefore.36 Approximate common-base hybrid equivalent circuit. 8. however.35 for the common-emitter configuration and of Fig. In other words.38 using the approximate common-emitter hybrid equiv8. hfe.3 re is satisfied. hfb . 8. b Ib hie e hfe Ib hoe e c Figure 8. are specified.14 (e) Since the condition RF1 Ai 1 RC ro RF2 1 122.

8.84) RB hie (8.38 Substituting the approximate hybrid equivalent circuit into the ac equivalent network of Fig. Vo Io R hfe Ib R and with Vo Av Vo Vi Ib Vi hie hfe Vi R hie (8.38. Zi: From Fig. Compare the similarities in appearance with Fig. and the results of one can be directly related to the other.VCC RC RB Ii Io C1 Zi hie hfe C2 Zo Vo Vi Ii Ic Ib RB hie hfe Ib hoe Io RC Zo Zi Vi Vo Figure 8. then Ib hie and 1/hoe Io Ii Ai hfe 370 Chapter 8 BJT Small-Signal Analysis + – + Figure 8. 8. Zi Zo: From Fig.38.83) so that Ai: Assuming that RB hfeIb hfe Ii with hfe(RC 1/hoe) hie 10RC. Zo Av : Using R 1/hoe RC.37. The similarities suggest that the analysis will be quite similar.85) Ii and Io Ic ICR RC 1/hoe (8. – + – + – (8. 8.37 Fixed-bias configuration.3 and the re model analysis. alent model.86) . 8.

38.39.175 k hie 1. Ai.88) 371 8.7 k 2.11.175 kΩ hoe = 20 µ A/V EXAMPLE 8. Zi R hie (8.38 with RB R.38.9 Approximate Hybrid Equivalent Circuit . determine: 8V Io 2. Zo.34 Voltage-Divider Configuration For the voltage-divider bias configuration of Fig. Zi: From Fig.39 Example 8. 8. the resulting small-signal ac equivalent network will have the same appearance as Fig.40 Voltage-divider bias configuration.171 k hie hfe 120 (b) ro Zo (c) Av (d) Ai 262. Solution (a) Zi RB hie 330 k 1.87) Zo: From Fig. Zo RC (8. Figure 8.56 k RC hoe C (120)(2.7 k 50 k ) hfe(RC 1/hoe) 1. 8.11 (a) (b) (c) (d) Zi. VCC Io RC R1 Ii Vi C1 R2 Zi RE CE Vo hie hfe C2 Zo Figure 8.171 k 1 1 50 k hoe 20 A/V 1 R 50 k 2. 8.7 kΩ 330 kΩ Vo Vi Ii Zi hfe = 120 Zo hie = 1.For the network of Fig. 8. with RB replaced by R R1 R2. 8.40. Av.

41.90) hfe(RC 1/hoe) hie (8.89) Unbypassed Emitter-Bias Configuration For the CE unbypassed emitter-bias configuration of Fig. The analysis will proceed in the same manner. with re replaced by hie and Ib by hfeIb.92) 372 Chapter 8 BJT Small-Signal Analysis . 8.Av: Av A i: Ai R hfeR hie (8. the small-signal ac model will be the same as Fig.95) hfe RC Zb Av RC RE hfeRC hfe RE (8.11.91) (8.94) RC (8.93) Zi hfe RE RB Zb (8. Zi: Zb and Zo: Zo Av : Av and A i: Ai hfeRB RB Zb (8. VCC Io RC RB Vo Vi Ii Zi RE hie hfe Zo Figure 8. 8.41 CE unbypassed emitter-bias configuration.

42.98) VCC RB Ii Vi Zi Io RE Zo hie hfe Vo Figure 8. 8.or Ai Av Zi RC (8. hfe. 8.43 as follows: Vo RE RE (Vi) hie/(1 hfe) 8. Zo: For Zo.18. with re hie and Zi: Zb Zi hfe RE RB Zb (8.99) RE hie 1 hfe Figure 8. The resulting equations will therefore be quite similar. 8.97) (8.42 Emitter-follower configuration.9 Approximate Hybrid Equivalent Circuit 373 . the voltage-divider rule can be applied to Fig.5 and Zo or since 1 hfe hfe. Av: For the voltage gain.43.96) Emitter-Follower Configuration For the emitter-follower of Fig. the output network defined by the resulting equations will appear as shown in Fig. the small-signal ac model will match Fig.43 Defining Zo for the emitter-follower configuration. 8. Zo RE hie hfe (8. Review the development of the equations in Section 8.

45 Substituting the approximate hybrid equivalent circuit into the ac equivalent network of Fig. hfb Ii Ic Io + Vi Zi RE VEE + Vo Zo RC VCC – Figure 8. From Fig. – Zi: Zi Zo: Zo Av : Vo 374 Chapter 8 BJT Small-Signal Analysis RE hib (8. 8.101) or Ai (8. which is very similar to Fig.103) RC (8. 8. 8.24.44 Common-base configuration.100) A i: Ai hfe RB RB Zb Av Zi RE (8.104) Io RC (hf b Ie)RC .44. 8. Av Vo Vi RE RE hie/hfe (8. Substituting the approximate common-base hybrid equivalent model will result in the network of Fig.44.45.45. 8. hib .but since 1 hfe hfe. – + Zi Vi Ii RE Ie hib hfb Ie Io RC + Vo Zo – Figure 8.102) Common-Base Configuration The last configuration to be examined with the approximate hybrid equivalent circuit will be the common-base amplifier of Fig.

2 kΩ hfb = − 0.with so that A i: Ie Vi hib Av and Vo Vi Vo hfb Vi R hib C (8.21 hib 1 1 2M hob 0. It is assumed that the analysis above clearly reveals the similarities in approach using the re or approximate hybrid equivalent models.99 hib = 14. – Solution (a) Zi (b) ro Zo (c) Av (d) Ai RE hib 2.46 Example 8. 8.5 µA/V Io 3.2 k 14.10 COMPLETE HYBRID EQUIVALENT MODEL The analysis of Section 8.105) hfb RC hib Ai Io Ii hfb 1 (8.106) For (a) (b) (c) (d) Ii the network of Fig.91 hib 14.99)(3.46.10 Complete Hybrid Equivalent Model 375 . Ai.5 A/V 1 R RC 3. EXAMPLE 8. Av. thereby removing any real difficulty with analyzing the remaining networks of the earlier sections.8 that were not analyzed in this section are left as an exercise in the problem section of this chapter.1 through 8. 8.9 was limited to the approximate hybrid equivalent circuit with some discussion about the output impedance.12 + Vi Zi 2. In this section.12.3 Ω hob = 0.21 hfb 1 The remaining configurations of Sections 8.3 k hob C hfb RC ( 0.3 14.3 kΩ + Vo Zo 4V 10 V – Figure 8. we employ the complete equivalent circuit to show the impact of hr and define in more specific terms the 8. determine: Zi.3 k ) 229. Zo.

Consider the general configuration of Fig. are employed. It is only necessary to insert the parameters defined for each configuration. 8. hr. and so on. common-emitter. and common-collector configurations. hie. the equations developed in this section can be applied to each configuration. the current gain Ai will be determined first since the equations developed will prove useful in the determination of the other parameters. Unlike the analysis of previous sections of this chapter. hfe. and ho. 8.48 using parameters that do not specify the type of configuration. That is. the solutions will be in terms of hi. and so on. Current Gain.impact of ho. hib. The complete hybrid equivalent model is then substituted in Fig. hfb.47 Two-port system. In other words. are utilized. Ii + Rs Ib hi hr Vo + hf Ib I 1/ho + Vo Zo Io + Vs Zi Vi RL – – – – Figure 8.47 with the two-port parameters of particular interest. we have ho RL Io ho RL) and 376 Chapter 8 Io(1 BJT Small-Signal Analysis . Io Ii + Vi Transistor + Vo Zo RL Rs + Vs Zi – – – Figure 8. for a common-base configuration.47.48 Substituting the complete hybrid equivalent circuit into the two-port system of Fig. Ai Io /Ii Vo 1/ho ho RL Io hf Ii hf Ii Applying Kirchhoff’s current law to the output circuit yields Io Substituting Vo hf Ib I hf Ii hf Ii hoVo Io RL gives us Io Io hf Ii Rewriting the equation above. 8. It is important to realize that since the hybrid equivalent model has the same appearance for the common-base. Recall that Appendix A permits a conversion from one set to the other if one set is provided and the other is required. while for a common-emitter configuration. hf.

Voltage Gain. (8. Zi Vi Ii 1 hi hf ho RL 1 h f hr RL ho RL (8.107) and Io (1 hoRL)hi Vo hf RL Vi Solving for the ratio Vo/Vi yields Av Vo Vi hrVo hi hf RL (hiho hf hr)RL (8. the familiar form of Av hf RL/hi will return if the factor (hiho hf hr)RL is sufficiently small compared to hi.10 Complete Hybrid Equivalent Model 377 .107) hf if the factor Note that the current gain will reduce to the familiar result of Ai hoRL is sufficiently small compared to 1.so that Ai Io Ii 1 hf hoRL (8. Zi For the input circuit. Input Impedance. we obtain Zi and substituting Ai yields The familiar form of Zi than the first.109) Vi Ii hi hr RL Ai hi will be obtained if the second factor is sufficiently smaller 8. Vi/Ii Vi hi Ii Io RL hi Ii Io Ii Ai Ii hiIi hr RL Ai Ii h r RL Io hrVo Substituting we have Since Vo Vi Ai Io so that the equation above becomes Vi Solving for the ratio Vi/Ii.108) In this case. Av Vo /Vi Vi Iihi hrVo Vo/RL from above re- Applying Kirchhoff’s voltage law to the input circuit results in Substituting Ii sults in (1 hoRL)Io/hf from Eq.

RL RC and Io is de378 Chapter 8 BJT Small-Signal Analysis . Solution Now that the basic equations for each quantity have been derived. 8. (b) Av. the order in which they are calculated is arbitrary. 8. A Thévenin equivalent circuit for the input section of Fig.13 For the network of Fig. Zo Vo /Io The output impedance of an amplifier is defined to be the ratio of the output voltage to the output current with the signal Vs set to zero. the output impedance will reduce to the familiar form Zo 1/ho for the transistor when the second factor in the denominator is sufficiently smaller than the first. Ii hrVo Rs hi Substituting this relationship into the following equation obtained from the output circuit yields Io hf Ii hoVo hoVo (8. Figure 8. The complete common-emitter hybrid equivalent circuit has been substituted and the network redrawn as shown in Fig. (a) Zi and Z i. the input impedance is often a useful quantity to know and therefore will be calculated first. (c) Ai Io /Ii and A i Io /I i. In this example. 8.13. 8. For the input circuit with Vs 0.110) hf hrVo Rs hi and Zo Vo Io ho 1 [hf hr /(hi Rs)] In this case.49.50. However.51 since ETh Vs and RTh Rs 1 k (a result of RB 470 k being much greater than Rs 1 k ). (d) Zo (within RC) and Z o (including RC).Output Impedance. EXAMPLE 8.50 will result in the input equivalent of Fig.49 Example 8. determine the following parameters using the complete hybrid equivalent model and compare to the results obtained using the approximate model.

and the equations derived above can be applied.108): Av Vo Vi 1.022)4.6 kΩ Z'o hre Vo 2 × 10− 4 Vo hfe Ib 110 Ib 1 hoe = 50 kΩ hoe = 20 µS Io + Vi Rs 1 kΩ Zi + Zo 4. The output impedance Zo as defined by Eq.Ii' Z'i Ii Ib Io 1.6 k 94. 8.48.032 0.7 k ) 1.51 k hfeRL (hiehoe hfehre)RL (110)(4.51 is then an exact duplicate of the defining network of Fig. It does not include the effects of RC. (8.6 k 47 313. (8. (a) Eq.51 k hie versus 1. (8.6 kΩ Zo 2 × 10− 4 Vo 110 Ib 50 kΩ 4.6 k using simply hie.7 k (b) Eq. Zi 470 k hie Zi Zi 1.10 Complete Hybrid Equivalent Model 379 .6 k 517 103 1. 8.50 with a Thévenin equivalent circuit. The resulting configuration of Fig.7 kΩ Vo + – + Vs – – – Figure 8.109): Zi Vi Ii h fe h re RL 1 hoe RL (110)(2 10 4)(4. Z o is simply the parallel combination of Zo and RL.9 8.6 k 1 (20 S)(4.52 1.7 k ) [(1.6 k )(20 S) (110)(2 517 103 (0. 8.6 k 10 4)]4. fined as the current through RC as in previous examples of this chapter. I'i Z'i Ii hie 1.7 k 1. 8.50 Substituting the complete hybrid equivalent circuit into the ac equivalent network of Fig.49.51 Replacing the input section of Fig.110) is for the output transistor terminals only.7 k ) 1.7 kΩ Z'o + Zi Vi 470 kΩ + Vo Rs 1 kΩ + – + Vs – – Thevenin – Figure 8.

20 S 1 Rs)] 1 [(110)(2 10 4)/(1. even Ai was off by less than 10%. (b) Ai and A i. EXAMPLE 8. The higher value of Zo only contributed to our earlier conclusion that Zo is often so high that it can be ignored compared to the applied load. 8.14.versus 323.7 k ) (c) Eq. the complete hybrid equivalent model must be used. However.2 kΩ Zi 6V Zo 12 V Z'o + Vo + Vs Z'i – – – Figure 8.46 k Note from the results above that the approximate solutions for Av and Zi were very close to those calculated with the complete equivalent model.6 k 1 k )] 20 S 8. determine the following parameters using the complete hybrid equivalent model and compare the results to those obtained using the approximate model.52. keep in mind that when there is a need to determine the impact of hre and hoe. (8. 380 Chapter 8 BJT Small-Signal Analysis .49 in a pnp common-base configuration to introduce the parameter conversion procedure and emphasize the fact that the hybrid equivalent model maintains the same layout. hie = 1. I i Ii and A i 100. 50 k .14 For the common-base amplifier of Fig.55 also.110): Zo Vo Io hoe 1 [hfehre/(hie Zi.7 k RC Zo 4. The specification sheet for a particular transistor typically provides the commonemitter parameters as noted in Fig.66 k using only RC. 7.7 k 86. Since 470 k (d) Eq. 8. 4.46 S 1 11. (8.107): Ai 110 100.66 k which is greater than the value determined from 1/hoe Zo versus 4. as described above. (a) Zi and Z i.094 versus 110 using simply hfe. In fact.54 S 86.55 1 0.6 kΩ hre = 2 × 10− 4 hfe = 110 hoe = 20 µS Io + Rs 1 kΩ Vi Ii' Ii 3 kΩ 2.125 using Av Io Ii 1 hfeRL/hie. hfe hoe RL 1 110 (20 S)(4.28.52 Example 8. The next example will employ the same transistor parameters appearing in Fig.

(8. Solution The common-base hybrid parameters are derived from the common-emitter parameters using the approximate equations of Appendix A: hib hie 1 hfe hie 1.41 Ω Substituting the common-base hybrid equivalent circuit into the network of Fig.2 kΩ + + Vo Rs 1 kΩ + 0.(c) Av.52 will then result in the small-signal equivalent network of Fig.991Ie hfb Ie hob = 0. Ii' Z'i c Zo − 0.10 Complete Hybrid Equivalent Model 381 .18 S)(2.18 S hoe 1 hfe Ii Zi 3 kΩ Vi e 20 S 1 110 hib Ie 14.883 10 4)(2.2 k ) 14.991)(0. (a) Eq. Zi (b) Eq.60 versus 14.52.2 k ) 14.53.19 14.991 0. The Thévenin network for the input circuit will result in RTh 3 k 1 k 0.75 k for Rs in the equation for Zo.60 hib hib.883 hfb hob 1 110 110 0.883 × 10−4 Vo hrb Vo + Vs – – b – Thévenin – b Figure 8.55 (1.41 1 (0. (d) Zo and Z o. 8. 8.41 0.6 k 110 hre 4 1.107): Ai Io Ii 1 3k hfb hob RL Zi Zi 14.109): Zi Vi Ii h f b h rb RL 1 hob RL ( 0.41 Note how closely the magnitude compares with the value determined from hib hrb re 14. (8.41 using Zi 8.18 µ S Io Z'o 2.6 k )(20 S) 1 110 2 10 4 hiehoe 1 hfe 10 1 hfe hfe 0. 8.53 Small-signal equivalent for the network of Fig.6 k 1 110 14.

If the input impedance of a common-base configuration is in the kilohm range.1 Since 3 k Zi.991)(0. (8. 0. RC Zo versus 2. there is good reason to recheck the analysis.110): Zo 1 hob [hf b hrb /(hib 0. and a voltage gain slightly less than 1.41 10 4)]2. The function of each component of a design will become increasingly familiar as general facts such as those above become part of your background. For the future.18 S)(2.3 using Av (d) Eq.295 S 3.41 )(0.199 k RC.991)(0. I i Vo Vi 0.56 M using Zo Zo using Z o 1/hob.18 S 1 0.991)(2.883 0. one should now be able to state with some assurance that the emitter-follower configuration typically has a high input impedance. One obvious advantage of being able to recall general facts like the above is an ability to check the results of a mathematical analysis.25 versus 151.2 k ) hfb Io/I i 1 also. It must be absolutely clear that the values listed are simply typical values to establish a basis for comparison. However.2 k 149. 8.39 M [( 0.39 M 2.2 k 8. 382 Chapter 8 BJT Small-Signal Analysis . Rs)] 1 10 4)/(14.11 SUMMARY TABLE Now that the most familiar configurations of the small-signal transistor amplifiers have been introduced. The levels obtained in an actual analysis will most likely be different.991 (0.1 is presented to review the general characteristics of each for immediate recall.2 k ) [(14. low output impedance.41 h fb RL hib (hib hob hfbhrb)RL ( 0.108): Av 14. on the other side of the coin.53: 2.18 S) ( 0. Being able to repeat most of the information in the table is an important first step in developing a general familiarity with the subject matter. a result of 22 suggests that the analysis may be correct.75 k )] versus 5. There should be no need to perform a variety of calculations to recall salient facts such as those above. For instance.2 k 3. it will permit the study of a network or system without becoming mathematically involved.991 Ii and A i (c) Eq.883 hfb RL/hib. (8. For Z o as defined by Fig. and certainly different from one configuration to another. Table 8.

12 Troubleshooting 383 .TABLE 8. and CC Transistor Amplifiers Configuration Fixed-bias: VCC RB RC Zi Medium (1 k ) RB re re (RB 10 re) (ro Zo Medium (2 k ) RC ro RC 10RC) (ro Av High ( 200) (RC ro) re RC re 10RC) Ai High (100) RBro RC)(RB (ro re) (ro RB 10RC . CB.1 Relative Levels for the Important Parameters of the CE. 10 re) Voltage-divider bias: R1 VCC RC Medium (1 k ) R1 R2 re Medium (2 k ) RC ro RC High ( 200) RC ro re RC re (ro 10RC) High (50) (R1 R2)ro RC)(R1 R2 (R1 R2) R1 R2 re (ro 10RC) (ro re) R2 (ro RE CE 10RC) Unbypassed emitter bias: RB VCC RC High (100 k ) RB Zb Zb (re RE) Medium (2 k ) RC (any level of ro) Low ( 5) RC RE RC RE (RE re) High (50) RB Zb re RB RB RE RE (RE re) Emitterfollower: RB VCC High (100 k ) RB Zb Zb (re RE) Low (20 RE re re ) Low ( 1) High ( 50) RB Zb RE RE re 1 RB RE (RE Commonbase: RE VEE RC VCC (RE Collector feedback: RF RB RE re) (RE re) Low (20 RE re re ) Medium (2 k ) RC High (200) RC re Low ( 1) 1 re) VCC RC Medium (1 k ) re 1 RC RE 10RC) Medium (2 k ) RC RF (ro 10RC) High ( 200) RC re (ro RF 10RC) RC) High (50) RF RF RF RC RC (ro 8.

the oscilloscope can also be used to compare dc levels simply by switching to the dc mode for each channel. In general. with time and experience. In most cases. Note that the black (gnd) lead of the oscilloscope is connected directly to ground and the red lead is moved from point to point in the network. both the dc and ac supplies are applied and the ac response at various points in the network is checked with an oscilloscope as shown in Fig. the network appears to be operating properly. 8. In general. VCE. there may be more than one problem area in the same system. 8. The fact that vo is measured in volts and vi in millivolts suggests a sizable gain for the amplifier. There is no ac VCC υ o (V) RC RB C2 C1 υo 0 υi υ i (mV) 0 t RE CE υe υe 0 t Oscilloscope t Rs + Vs – (AC-GND-DC switch on AC) Ground strap Figure 8. or isolating procedures require an understanding of what to expect at various points in the network in both the dc and ac domains. there is nothing mysterious about the general troubleshooting process. If you decide to follow the ac response. the probability of malfunctions in some areas can be predicted and an experienced person can isolate problem areas fairly quickly. In a typical laboratory setting. The vertical channels are set in the ac mode to remove any dc component associated with the voltage at a particular point. checking. it is important to realize that the same techniques can be applied to ensure that a system is operating properly.54. the dc mode of the multimeter could be used to check VBE and the levels of VB. a network operating correctly in the dc mode will also behave properly in the ac domain. Of course. however. the testing. Needless to say. In fact. providing the patterns appearing in Fig. a network providing the expected ac response is most likely biased as planned. it is good procedure to start with the applied 384 Chapter 8 BJT Small-Signal Analysis . and VE to review whether they lie in the expected range. In addition. a poor ac response can be due to a variety of reasons.54. Note the difference in vertical scales for the two voltages. If desired.8.12 TROUBLESHOOTING Although the terminology troubleshooting suggests that the procedures to be described are designed simply to isolate a malfunction. response at the emitter terminal due to the short-circuit characteristics of the capacitor at the applied frequency.54 Using the oscilloscope to measure and display various voltages of a BJT amplifier. In any case. Fortunately. The small ac signal applied to the base is amplified to the level appearing from collector to ground.

the current description will concentrate on the variations introduced by the ac analysis. experience are all factors that contribute to the development of an effective approach to the art of troubleshooting. and the gain of the system as revealed by vo is much lower. Once 8.9 (Example 8.55 The waveforms resulting from a malfunction in the emitter area. 8. Recall for this configuration that the gain is much greater if RE is bypassed. a familiarity with the instrumentation. 8. If the response for the network of Fig.2) is developed as shown in Fig. a prior knowledge of what to expect.13 PSPICE WINDOWS Voltage-Divider Configuration Using the Software Transistor Parameters Now that the basic maneuvers for developing the network on the schematics grid have been introduced. the network has a malfunction that is probably in the emitter area. a checking of the dc levels will probably not isolate the problem area since the capacitor has an “open-circuit” equivalent for dc. 8. 8. An unexpected response at some point suggests that the network is fine up to that area.13 PSpice Windows 385 . In general.Figure 8. The response obtained suggests that RE is not bypassed by the capacitor and the terminal connections of the capacitor and the capacitor itself should be checked. In this case. The waveform obtained on the oscilloscope will certainly help in defining the possible problems with the system. signal and progress through the system toward the load. and most important.56. checking critical points along the way. Note the ac source of 1 mV and the printer symbol at the output terminal of the network.54 is as appears in Fig. Using schematics.55. 8. thereby defining the region that must be investigated further. The sinusoidal ac source is listed in the SOURCE. An ac response across the emitter is unexpected. the network of Fig.slb library as VSIN.

simply click on Change Display after saving the attribute. Double-clicking on the printer symbol will result in a PRINT1 dialog box. After each entry. For instance. The printer symbol on the collector of the transistor is listed as VPRINT1 under the SPECIAL. AC 1mV. PHASE ok. When placed on the schematic. a Change Attribute dialog box would appear. Next. placed on the diagram.56 Using PSpice Windows to analyze the network of Figure 8. If you want to display the value of the ac signal. the beta (Bf) is set to 90 and Is is set to 2E-15A to result in a base-to-emitter voltage close to 0.out). and only the 1mV will be displayed after the sequence OK-OK. if AC 1mV was just saved and Change Display was chosen. VOFF 0 (no dc offset voltage for the sinusoidal signal).9 (Example 8. If done properly. After each entry. choose Value Only. be sure to Save Attr to save the entered attribute. one must first click on the transistor to put it in the active mode (red) and then choose Edit-Model-Edit Instance Model (Text). MAG ok. be sure to Save Attr or the computer will remind you.slb library.7 V. the following choices will be made: VAMPL 1mV (the peak value of the sinusoidal signal). The above choices can be listed next to the printer symbol on the schematic by simply clicking the Change Display option and choosing the Display Value and Name for each item. Since AC is the name and 1mV the value. it dictates that the ac voltage at that point will be printed in the output file (*. This value of I is the result of nu386 Chapter 8 BJT Small-Signal Analysis . within which the following choices should be made: AC ok. The cursor appears in the Value box. and the desired value can be entered. The transistor is obtained through the sequence Get New Part icon-LibrariesEVAL. the assigned value will appear in the listing. Each choice can be made by double-clicking the desired quantity. which will then appear in the Name and Value rectangles at the top of the box. double-clicking the symbol will result in the PartName: VSIN dialog box with a list of options. FREQ 10kHz (the frequency of interest). PHASE 0 (no initial phase angle for the sinusoidal signal). Since we will want the parameters of the transistor to match those of the example as closely as possible. For our analysis.Figure 8.slb-Q2N2222-OK-Place & Close.2).

In most cases. Clicking the Transient option will result in a Transient dialog box.7 V.7 V. reveals that even though beta of the BJT MODEL PARAMETERS listing was set at 90. the operating conditions of the network resulted in a dc beta of 48. Choosing the Setup Analysis icon will result in the Analysis Setup dialog box. in which the AC Sweep must be chosen because of the applied ac source. Since it has been used recently. if we follow this procedure without setting the horizontal scale. A plot of the output waveform can be obtained using the Probe option.1 mV versus the hand-written solution (with ro 50 k ) of 324. A closer result (within 7%) could be obtained by setting all the parameters of the device except IS and beta to zero. The Print Step option refers to the time interval between printing or plotting the results of the transient analysis. However. Note that ground is always defined as the 0 node and the assumed node of higher potential listed first. and the results will be accepted as sufficiently close to the hand-written levels. However. Specific headings are duplicated in Fig. VIEWPOINT can be found in the scroll listing at the top right of the menu bar rather than by returning to the library listing.3 and an ac beta of 55. Note also the listing of the frequency applied at the bottom of the dialog box. Under Schematics Netlist. The Final Time is the last instant the network’s response will be determined. and the dc results are excellent. the voltage-divider configuration is less sensitive to changes in beta in the dc mode. For our example. which compare directly with the VIEWPOINT values. In particular. we will simply end up with a plot point of 296 mV at a frequency of 10 kHz.57.1 ms 100 s. The sequence Analysis-Probe Setup-Automatically run Probe after simulation-OK will result in a MicroSim Probe screen when the Analysis icon is chosen. The results are certainly close. 8. it provides the desired results. Within this box. The No-Print Delay was chosen as 0 since all the capacitors are essentially short cir8. we should turn to Analysis-Probe Setup and choose Do not auto-run Probe to save time getting to the desired results. For the remainder of this text. the dc levels at the various nodes are revealed. Clicking the Analysis icon will result in a PSpiceAD dialog box that will indicate the AC Analysis is finished. we will obtain a lengthy listing of input and output data on the analyzed network. The transistor is listed in the order Collector-Base-Emitter. and End Freq: 10kHz. The period of the applied signal of 10 kHz is 0. However. however. Later in this chapter. the impact of the remaining parameters has been demonstrated. Therefore. The phase angle is 178° versus the ideal of 180°—a very close match. the drop in ac beta had an effect on the resulting level of Vo: 296. we will choose 1 s to provide 100 plot points per cycle. Fortunately. the defining parameters of the device are listed with the set values of IS 2E-15A and 90. The result will be an analysis at only one frequency. Start Freq: 10kHz. however. Clicking on AC Sweep will result in an AC Sweep and Noise Analysis dialog box. Under BJT MODEL PARAMETERS. in which a number of choices have to be made based on the waveform to be viewed. if we choose File followed by Examine Output. this chosen level of IS will remain the same. The horizontal scale is set by the sequence Analysis-Setup-Transient with the AC Sweep disabled.3 mV—a 9% difference. the nodes assigned to the network are revealed. an ac model for the transistor will be introduced with results that will be an exact match with the hand-written solution. Under SMALL-SIGNAL BIAS SOLUTION. OPERATING POINT INFORMATION. for the moment. The next listing. but probably not as close as one would like. in which Linear is chosen along with Total Pts: 1.5 ms to provide five full cycles of the waveform. VIEWPOINTs have been inserted to display the three dc voltages of interest. note that VBE is exactly 0.merous runs of the network to find that value of IS that provided a level of VBE closest to 0. Our initial interest will simply be in the magnitude of the quantities of interest and not their shape or appearance.13 PSpice Windows 387 . Our choice is 500 s or 0.

388 .56.Figure 8.57 Output file for the network of Figure 8.

choose 8.56.76 V 13. If a comparison is to be made between the input and output voltages on the same graph. The last choice of Step Ceiling sets a maximum time period between response calculations for the system. they will never be separated by a time period greater than that set by the Step Ceiling. a MicroSim Probe screen will appear showing only the horizontal scale from 0 to 500 s as specified in the Transient dialog box. Now one must choose the waveform to be displayed from the list of Simulation Output Variables.cuits at 10 kHz.58). or very close to the values displayed above. V(Q1:c)—an option under Alias names—will be chosen. The time between calculations will be adjusted internally by the software package to ensure sufficient data at times when the response may change faster than usual. If the Trace on the menu bar is chosen. 8. If you would like to see the data points (as shown in Fig.6 V 600 mV. and the data points will appear. simply turn to Tools-Options-Probe Options and choose Mark Data Points. Using the scale of the graph. and the Add Traces dialog box will appear. which we will set at 1 s. Using the icon results in the dialog box immediately. If we felt there was a transient phase between energizing the network and reaching a steady-state response. 8. However. the peak-to-peak value of the curve is approximately 13.13 PSpice Windows 389 . To obtain a waveform.45 V. with the waveform riding on the Figure 8. The range of the vertical axis was automatically chosen by the computer. After it is triggered. Click OK. dc level of 13. resulting in a peak value of 300 mV.58. followed by an OK. Since we want the collector-to-emitter voltage of the transistor.58 Voltage vc for the network of Figure 8. Five full cycles of the output waveform are displayed (as we expected) with 100 data points for each cycle. Since a 1-mV signal was applied. the gain is 300. After Simulation. the Add Y-Axis option under Plot can be chosen. the No-Print Delay could be used to effectively eliminate this period of time.16 V 0. one must follow with Add. The result is the waveform of Fig. one can either choose Trace on the menu bar or the Trace icon (red pattern on a black axis).

8. A Text Label dialog box will appear. 390 Chapter 8 BJT Small-Signal Analysis .Figure 8. Click OK. the Add Trace icon and select V(Vs: ). which can be used to draw the line with a left-click at the starting point and another click when the line is in place.56.59 using Tools-Label-Text. A pencil will appear. Each plot Figure 8. and it can be placed with the mouse in any location on the graph. The result is that both waveforms will appear on the same screen. Labels can be added to the waveforms as shown in Fig. in which the desired text can be entered.59 The voltages vc and vs for the network of Figure 8.56. each with their own vertical scale.60 Two separate plots of vc and vs in Figure 8. Lines can also be added with Tools-Label-Line.

the vertical and horizontal intersections will appear in the dialog box.592 V vertically and 50. Once the desired wave8. If moved to the first peak value. By clicking on the vertical line and holding it down. appears. The labels Vs and Vc were added using the Tools option. because the peak-to-peak value matches the 2 0. The last waveform of this section will demonstrate the use of the Cursor option that can be called up using the Tools menu choice or the Cursor Point icon (having a graph with an arrow drawn from the graph to the vertical axis). A1 will be at 13. By right-clicking on the mouse. which also has its location registered in the dialog box. The time interval is essentially 1/4 of the total period (200 s) of the waveform. the vertical line and corresponding horizontal line (on the graph) can be moved across the waveform.453 V. another graph will appear. If A2 is set at the bottom of the waveform as shown in Fig. The sequence ToolsCursor-Display will result in a line at the dc level of 13. If two separate graphs are preferred.35 s horizontally. At each point. Upon selection.17 s.61 Demonstrating the use of cursors to read specific points on a plot. it will read 13. The peak and minimum values for the graph of Fig.61. These intersecting lines are moved by holding down Figure 8. waiting for the next choice. The remaining information on the third line of the box is the difference between the two intersections on the two axis. the right side of the mouse. Left-clicking on the mouse once will result in a horizontal and vertical line intersecting at some point on the curve. as shown in the dialog box at the bottom right of the graph of Fig.754 V and 74.60.13 PSpice Windows 391 .825 s. we can choose the Plot option and select Add Plot after V has been displayed.can be printed with File-Print-Copies-OK.162 V at 125.61 can also be found using the icons appearing in the top right region of the menu bar. resulting in a difference between the two of 591. The labels A1 and A2 were added using the Tools-Label-Text sequence or the ABC text icon. 8.999 mV. This is as expected. 8.61.296 V 0. 8. a second intersection. If further operations are to be performed on either graph. The sequence Trace-Add-V(Vs: ) will then result in the graphs of Fig. the SEL defines the active plot. or 0.592 V obtained earlier. defined by A2. 8.

66 k .56. 8. This was demonstrated for the network of Fig. The current controlled current source (CCCS) is found in the ANALOG. it must be added in series with the controlling current indicated by the arrow on the Figure 8. If a solution is desired that is limited to the approximate model.56. 392 Chapter 8 BJT Small-Signal Analysis . Clicking on the icon with the intersection at the top will automatically place the A1 intersection at the top of the curve. When you click on F. then the transistor must be represented by a model such as appearing in Fig.63 Substituting the controlled source of Figure 8. Since re does not appear within the basic structure of the CCCS. For Example 8. Voltage-Divider Configuration—Controlled Source Substitution The results obtained for any analysis using the transistors provided in the software package will always be different from those obtained with an equivalent model that only includes the effect of beta and re.63. 8. The next icon will place the intersecGAIN = β F1 B Ib βre βIb C B βre Ib βIb C B βre Ib C βIb F E E E Figure 8. with re 1.form is obtained and the sequence Tools-Cursor-Display applied or the Toggle cursor icon (the icon in the center region of the menu bar with the black dashed axis and red curve passing through the origin) is chosen. the six icons to the right of the Toggle cursor icon will change to a color pattern indicating they are ready for use. the Description above will read Current-controlled current source.2. 8. is 90. After OKPlace & Close. the graphical symbol for the CCCS will appear on the screen as shown in Fig. tion at the steepest slope and the next at the minimum value (matching the trough value).62 for the transistor of Figure 8.slb library as Part F.56.62.62 Using a controlled source to represent the transistor of Figure 8. Clicking the next icon to the right will place the intersection at the bottom (trough) of the curve.

8. For (a) (b) (c) (d) the network of Fig. 8. IC.66: Calculate IB.65.65 Problem 2 * 3. 12 V PROBLEMS 220 kΩ 2.64: Determine Zi and Zo.2 kΩ Io Vo Vi Ii Zi Zo β = 60 ro = 40 kΩ Figure 8. Calculate Av and Ai.2 Common-Emitter Fixed-Bias Configuration 1. Determine Zi and Zo. Find Av and Ai.7 kΩ 1 MΩ Vo 200. Repeat part (a) with ro 20 k . 10 V 4.§ 8. determine VCC for a voltage gain of Av VCC 4. For the network of Fig. For (a) (b) (c) (d) the network of Fig.3 kΩ Io Vo Vi Ii Zi +10 V 390 kΩ Zo β = 100 ro = 60 kΩ Figure 8.64 Problems 1 and 21 2. 8. and re. Vi β = 90 ro = ∞ Ω Figure 8. Repeat part (b) with ro 20 k .66 Problem 3 Problems 393 . Determine the effect of ro 30 k on Av and Ai.

3 kΩ 82 kΩ Vo 25 k . Repeat parts (b) and (c) with ro BJT Small-Signal Analysis 20 k . Calculate VB and VC.68 if Av 6.70: Determine re. 8.2 kΩ 10 µF 1 kΩ CE 3.67 Problem 4 Figure 8. 8.9 kΩ Io 1 µF Vo Zo CC Vi CC 5.3 Voltage-Divider Bias 4. Figure 8.2 kΩ Io Vo 56 kΩ 2. Determine VCC for the network of Fig.68 Problem 5 5.70 Problems 7 and 9 394 Chapter 8 . 8.7 kΩ β = 100 ro = 50 kΩ β = 100 ro = ∞ Ω Figure 8.8 kΩ 220 kΩ VC CC Vo Vi CC Zi VB β = 180 ro = 50 kΩ 20 V 2.69 Problem 6 Vi β = 140 ro = 100 kΩ Ii Zi 1. Find Zi and Zo.4 CE Emitter-Bias Configuration 7.2 kΩ Zo § 8. 6.2 kΩ CE 390 kΩ Figure 8.69: Determine re.67: Determine re. For (a) (b) (c) (d) the network of Fig.6 kΩ 1. 39 kΩ 1 µF Vi Ii Zi 4. VCC = 20 V 160 and ro 100 k .§ 8. Determine Zi and Av Vo /Vi. 8. Find Av and Ai. For (a) (b) (c) (d) the network of Fig. Repeat parts (b) and (c) with ro VCC = 16 V VCC 3. For (a) (b) (c) the network of Fig. Calculate Zi and Zo. Calculate Av and Ai.

7 kΩ Vo Zi 390 kΩ Io 5.72: Determine re. * 10. 8.71.71 Problem 8 Figure 8.72 Problem 10 § 8. 16 V 12 V 270 kΩ Vi Ii Zi Io 2. 8.73: Determine re and re.6 kΩ Zo −8 V Zo Ii β = 110 ro = 50 kΩ Vi β = 120 ro = 40 kΩ Vo Figure 8. 9. For (a) (b) (c) the network of Fig. determine RE and RB if Av Zb RE. Compare results. Calculate Av and Ai.2 kΩ Vi CC 330 kΩ Io Vo CC β = 80 ro = 40 kΩ β = 120 ro = 80 kΩ 0.8. 10 and re 3. For (a) (b) (c) the network of Fig. For (a) (b) (c) * 12. 8.5 Emitter-Follower Configuration 11. Assume that 22 V 5. Find Zi and Av.74 Problem 12 Problems 395 .2 kΩ RB Vo Vi Zi 1. Find Zi and Zo.8 .6 kΩ 20 V Ii 8. For the network of Fig.74: Determine Zi and Zo.73 Problem 11 Figure 8. Repeat Problem 7 with RE bypassed. Calculate Vo if Vi 1 mV.47 kΩ CE RE Figure 8. Find Av. the network of Fig. Calculate Ai. 8.

Determine Zi and Zo.998 ro = 1 MΩ Zo Figure 8. For (a) (b) (c) (d) the network of Fig. For (a) (b) (c) the common-base configuration of Fig. For the network of Fig. +6 V −10 V 6.76: Determine re.6 Common-Base Configuration 14. 8.77.75 Problem 13 § 8. 8.7 kΩ Io Vo α = 0. 8V 3. Find Av and Ai. Find Zi and Zo. 8.8 kΩ Ii Vi Zi 4. Determine re.* 13.2 kΩ β = 200 ro = 40 kΩ Io 2 kΩ Vo Figure 8.75: Calculate IB and IC.6 kΩ Io Vo β = 75 ro = ∞ Ω Vi Ii 3. Calculate Av and Ai. determine Av and Ai.77 Problem 15 396 Chapter 8 BJT Small-Signal Analysis .76 Problem 14 * 15. VCC = 20 V 56 kΩ Vi Ii 8.9 kΩ −5 V Figure 8.

§ 8.78: Determine re.79 Problem 17 * 18. 8. § 8.78 Problem 16 * 17.80: (a) Determine Zi and Zo.7 Collector Feedback Configuration 16. RF.80 Problem 19 Problems 397 . RE 1. Find Zi and Zo.2 k .9 kΩ β = 120 ro = 40 kΩ Figure 8. 8. Av 160. and VCC. For (a) (b) (c) the collector FB configuration of Fig.8 Collector DC Feedback Configuration 19. and Zo using the equations of parts (a) through (c).30: Derive the approximate equation for Av.8 kΩ 39 kΩ 22 kΩ 10 µ F Ii Vi 1 µF Zi 1 µF Vo Zo β = 80 ro = 45 kΩ Figure 8.2 k . Ai. 90. Given re 10 . RF 120 k . RC. Zi. 200. For (a) (b) (c) (d) the network of Fig. Derive the approximate equations for Zi and Zo. For the network of Fig. 8. (b) Find Av and Ai. Derive the approximate equation for Ai. and Ai 19 for the network of Fig. determine VCC RC RF Vo re = 10 Ω Vi β = 200 ro = 80 kΩ Figure 8. and VCC 10 V. 8. 220 kΩ Vo Vi Ii Zi Zo 12 V Io 3. Given RC 2.79. Calculate Av and Ai. 9V Io 1. calculate the magnitudes of Av.

hfe 90.9 Approximate Hybrid Equivalent Circuit 20.7 kΩ Vo Zi 4V 12 V Zo 10 µF Ii + Vi + – Figure 8. Calculate Av and Ai. Find hfe and hie. (a) Given 120. and hoe 20 S.§ 8.82: Determine Zi and Zo. 21. Determine re and compare re to hie. Determine Av and Ai if hoe 50 S.75 kΩ hoe = 25 µS 12 kΩ Zi 1. and ro 40 k . (Note: The solutions are available in Appendix E if Problem 1 was not performed. For (a) (b) (c) (d) (e) (f) (g) 22.5 . Calculate Av and Ai. Determine . 8. hre 2 10 4. and ro.992 hib = 9.81: Determine Zi and Zo. Compare the solutions above with those of Problem 1. re 4. . Determine Zi and Zo if hoe 50 S.82 Problem 23 – 398 Chapter 8 BJT Small-Signal Analysis . (b) Given hie 1 k .45 Ω hob = 1 µ A/V 10 µ F 1.2 kΩ Io Ii 5 µF 5 µF Zo Vo hfe = 180 hie = 2. Calculate Av and Ai using the hybrid parameters.2 kΩ Io 2.81 Problems 22 and 24 * 23. For (a) (b) (c) the common-base network of Fig. sketch the approximate hybrid equivalent circuit. For (a) (b) (c) the network of Problem 1: Determine re. 18 V 68 kΩ 2.2 kΩ 10 µF Figure 8.) the network of Fig. sketch the re model. hfb = −0. Find Zi and Zo using the hybrid parameters. 8. re.

2 kΩ – Zi 10 µ F – Figure 8.83. 2. 20 V 2 10 4 and compare results.12 Troubleshooting * 27. For (a) (b) (c) (d) the common-base amplifier of Fig.83 Problem 25 * 26.10 Complete Hybrid Equivalent Model * 24. Repeat parts (a) and (b) of Problem 22 with hre * 25. (c) Ai Io/Ii. hib = 9. 8.2 kΩ 470 kΩ Ii 5 µF Io 5 µF Vo Zo hfe = 140 hie = 0.86 kΩ hre = 1. Av.§ 8. Problems 399 . For the network of Fig. determine: (a) Zi.5 µ A/V hrb = 1 × 10− 4 Io 5 µF 1.6 kΩ 5 µF Ii + Vi + + Vs Zi – – Figure 8.2 kΩ Zo 4V 14 V Vo 0.997 hob = 0. 8. (d) Zo. Given the network of Fig. (b) Determine the reason for the dc levels obtained and why the waveform for vo was obtained.2 kΩ 2.5 × 10− 4 hoe = 25 µS 1 kΩ + Vs + Vi 1. Ai. 8. Zo.84.85: (a) Determine if the system is operating properly based on the voltage-divider bias levels and expected waveforms for vo and vE. determine: Zi.84 Problem 26 – § 8. (b) Av.45 Ω hfb = −0.

29. Using PSpice Windows.85 Problem 27 § 8. 8.22 V 150 kΩ 2.7 V R2 39 kΩ RE β = 70 υe 0 10 µ F t – 1. Use Probe to display the input and output waveforms.6. determine the gain for the network of Fig.25.5 kΩ + Vs – Figure 8. 30. 8. 400 Chapter 8 BJT Small-Signal Analysis .13 PSpice Windows 28.13. Using PSpice Windows. determine the gain for the network of Fig. *Please Note: Asterisks indicate more difficult problems. 8. Use Probe to display the input and output waveforms. Using PSpice Windows. determine the gain for the network of Fig.2 kΩ 10 µ F vo C2 0 υo (V) t + VBE = 0. Use Probe to display the input and output waveforms.VCC = 14 V υi (mV) 0 10 µ F C1 Rs RC R1 t VB = 6.

the BJT is a current-controlled device and the FET is a voltage-controlled device. As with BJT amplifiers. While the voltage gain of an FET amplifier is generally less than that obtained using a BJT amplifier. The depletion MOSFET circuit. In fact. gm.gm CHAPTER FET Small-Signal Analysis 9. While the common-source configuration is the most popular providing an inverted. In both cases. and output impedance. Using PSpice. While the BJT had an amplification factor (beta). Due to the very high input impedance. FET ac amplifier networks can also be analyzed using computer software. Table 9. the enhancement MOSFET is quite popular in digital circuitry. the FET has a transconductance factor.1. one also finds common-drain (source-follower) circuits providing unity gain with no inversion and common-gate circuits providing gain with no inversion. the input current is generally assumed to be 0 A and the current gain is an undefined quantity. Output impedance values are comparable for both BJT and FET circuits. amplified signal. the important circuit features described in this chapter include voltage gain. however. The FET can be used as a linear amplifier or as a digital device in logic circuits. Because of the high input characteristic of FETs. the FET amplifier provides a much higher input impedance than that of a BJT configuration.1 INTRODUCTION Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a high input impedance. Using PSpice transistor models. While a BJT device controls a large output (collector) current by means of a relatively small input (base) current. provides a summary of FET small-signal amplifier circuits and related formulas. therefore. FET devices are also widely used in high-frequency applications and in buffering (interfacing) applications. the ac equivalent model is somewhat simpler than that employed for BJTs. They are also considered low-power consumption configurations with good frequency range and minimal size and weight. however. 9 401 . Both JFET and depletion MOSFET devices can be used to design amplifiers having similar voltage gains. the FET device controls an output (drain) current by means of a small input (gate-voltage) voltage. input impedance. especially in CMOS circuits that require very low power consumption. has a much higher input impedance than a similar JFET configuration. one can perform a dc analysis to obtain the circuit bias conditions and an ac analysis to determine the small-signal voltage gain. In general. note that the output current is the controlled variable. located at the end of the chapter.

we find that gm is actually the slope of the characteristics at the point of operation.2) Graphical Determination of gm If we now examine the transfer characteristics of Fig.1). gm m y x ID VGS (9.gm one can analyze the circuit using specific transistor models. (9.in the terminology applied to gm reveals that it establishes a relationship between an output and input quantity.2 FET SMALL-SIGNAL MODEL The ac analysis of an FET configuration requires that a small-signal ac model for the FET be developed. The gate-to-source voltage controls the drain-to-source (channel) current of an FET. That is. therefore.1 Definition of gm using transfer characteristic. we have: gm ID VGS (9. it is reasonably clear that the slope and.1) The prefix trans. 9. Or.1. 9. in other words. The root word conductance was chosen because gm is determined by a voltage-to-current ratio similar to the ratio that defines the conductance of a resistor G 1/R I/V. as VGS approaches 0 V. The change in collector current that will result from a change in gate-to-source voltage can be determined using the transconductance factor gm in the following manner: ID gm VGS (9. On the other hand. Recall from Chapter 6 that a dc gate-to-source voltage controlled the level of dc drain current through a relationship known as Shockley’s equation: ID IDSS(1 VGS/VP)2. A major component of the ac model will reflect the fact that an ac voltage applied to the input gate-to-source terminals will control the level of current from drain to source.3) Following the curvature of the transfer characteristics. Solving for gm in Eq. gm increase as we progress from VP to IDSS. the magnitude of gm increases. 402 Chapter 9 FET Small-Signal Analysis . ID IDSS gm ≡ ∆ID (= Slope at Q-point) ∆VGS Q-Point ∆ID ∆VGS VP 0 VGS Figure 9. one can develop a program using a language such as BASIC that can perform both the dc and ac analyses and provide the results in a very special format.

57 mS (b) gm 0.2) reveals that gm can be determined at any Q-point on the transfer characteristics by simply choosing a finite increment in VGS (or in ID) about the Q-point and then finding the corresponding change in ID (or VGS.2 using the procedure defined in Chapter 6. respectively).0 V VGS Note the decrease in gm as VGS approaches VP.1 m A ID (a) gm 3.5 V.5 V gm at −2.5 mS 0.8 mA 4 3 2 gm at −1. Mathematical Definition of gm The graphical procedure just described is limited by the accuracy of the transfer plot and the care with which the changes in each quantity can be determined.0 V Figure 9. (9. Each operating point is then identified and a tangent line is drawn at each point to best reflect the slope of the transfer curve in this region.5 V ID = 8 mA 1 − ( VGS −4 V ) 6 5 2.5 V 0.2) is then applied to determine gm.1 mA 2 0.5 V.2 FET Small-Signal Model 403 .2 Calculating gm at various bias points.5 mS (c) gm 1. (c) VGS 8 mA and VP 4 V at the EXAMPLE 9.7 V VGS 1.8 m A ID 2. The resulting changes in each quantity are then substituted in Eq.5 mA −2 −1 1 0 VGS (V) −4 VP −3 1. Naturally.2) to determine gm. but this can then become a cumbersome 9. the larger the graph the better the accuracy. (b) VGS 2. (a) VGS 1. Equation (9. ID (mA) 8 7 gm at − 0. 9.1 Solution The transfer characteristics are generated as Fig.6 V 1.5 m A ID 1.7 V 1.5 V. Determine the magnitude of gm for a JFET with IDSS following dc bias points: 0. 2. An appropriate increment is then chosen for VGS to reflect a variation to either side of each Q-point.6 V VGS 1.gm Equation (9.

It was mentioned earlier that the slope of the transfer curve is a maximum at VGS 0 V. dID dVGS VGS VP Q-pt.6) and compare with the graphical results. (9.5) 0 V.5 mS graphically) 404 Chapter 9 FET Small-Signal Analysis .1 using Eq. where it was stated that: The derivative of a function at a point is equal to the slope of the tangent line drawn at that point.5 V. 2 d IDSS 1 dVGS 2IDSS 1 VGS VP 2 d 1 dVGS VGS VP VGS d 1 VP dVGS 2IDSS 1 VGS VP VGS VP 0 1 VP (9.2 For the JFET having the transfer characteristics of Example 9. (9. If we therefore take the derivative of ID with respect to VGS (differential calculus) using Shockley’s equation. an equation for gm can be derived as follows: gm ID VGS IDSS Q-pt.gm problem.4) then becomes gm gm0 1 VGS VP (9.5 V 4V 3. An alternative approach to determining gm employs the approach used to find the ac resistance of a diode in Chapter 1. Plugging in VGS 0 V into Eq.4) 2IDSS 1 d (1) dVGS gm 1 dVGS VP dVGS 2IDSS 1 VP VGS VP and where VP denotes magnitude only to ensure a positive value for gm.6) EXAMPLE 9. (b) Find the value of gm at each operating point of Example 9.5 mS (versus 3.1: (a) Find the maximum value of gm.4) will result in the following equation for the maximum value of gm for a JFET in which IDSS and VP have been specified: gm 2IDSS 1 VP gm0 2IDSS VP 0 VP (9. and where the added subscript 0 reminds us that it is the value of gm when VGS Equation (9. VGS VP 4 mS (maximum possible value of gm) (b) At VGS gm gm0 1 4 mS 1 0. Solution (a) gm0 2IDSS VP 2(8 mA) 4V 0.

Figure 9.3 Solution Note Fig.gm At VGS gm At VGS gm 1. Plotting gm vs. In equation form. The f signifies forward transfer parameter. 9.5 V.5 V 4V 1.5 V 4V 2.4. gm gm0(1 1) 0.3.4) through (9. Plot gm vs.57 mS graphically) The results of Example 9.1 and 9. (9.18. gm will be one-half the maximum value. VGS VGS of Eq. VGS. 9.5 V.3 Plot of gm vs. Since the factor 1 gm (S) gm0 gm0 2 VP VP 2 0 VGS (V) Figure 9.2 are certainly sufficiently close to validate Eq. gm0 1 VGS VP 4 mS 1 2.3 also reveals that when VGS is one-half the pinch-off value.2 FET Small-Signal Model 405 . EXAMPLE 9. On specification sheets. and the s reveals that it is connected to the source terminal.6) is less than 1 for any value of VGS other than VP V 0 V.6) defines a straight line with a minimum value of 0 and a maximum value of gm as shown by the plot of Fig.5 mS (versus 1. VGS for the JFET of examples 9. At VGS VP. gm yfs (9. Equation (9. gm is provided as yfs where y indicates it is part of an admittance equivalent circuit. the magnitude of gm will decrease as VGS approaches VP and the ratio GS VP increases in magnitude.2.5 mS (versus 2. (9.7) For the JFET of Fig.6) for future use when gm is required. gm0 1 2. yfs ranges from 1000 to 5000 S or 1 to 5 mS. 9. 5.5 mS graphically) VGS VP 4 mS 1 1.

VP Impact of ID on gm A mathematical relationship between gm and the dc bias current ID can be derived by noting that Shockley’s equation can be written in the following form: 1 VGS VP ID IDSS (9. (9. gm gm0 IDSS/4 IDSS gm0 2 0. gm (b) If ID IDSS/2. 9. 406 Chapter 9 FET Small-Signal Analysis . the results are (a) If ID IDSS. ID for the JFET of Examples 9. VGS for a JFET with IDSS 8 mA and 4 V.6) will result in gm gm0 1 VGS VP gm0 ID IDSS (9. (9.8) into Eq.4 Plot of gm vs.gm gm (S) 4 mS 2 mS −4 V −2 V 0 VGS (V) Figure 9.8) Substituting Eq.9) to determine gm for a few specific values of ID.707gm0 gm0 IDSS IDSS gm0 EXAMPLE 9.5gm0 gm0 IDSS/2 IDSS 0.4 Plot gm vs.1 through 9.5. gm (c) If ID IDSS/4. (9.9) Using Eq. Solution See Fig.3.

In equation form. 5. (9.10) (1000 M ) is typical. For the JFET of Fig.4 clearly reveal that the highest values of gm are obtained when VGS approaches 0 V and ID its maximum value of IDSS. The plots of Examples 9. with the subscript o signifying an output network parameter and s the terminal (source) to which it is attached in the model. the ideal situation is on hand with the output impedance being infinite (an open circuit)—an often applied approximation.gm gm (S) 4 mS 4 3 2.2 FET Small-Signal Model 407 . yos has a range of 10 to 50 S or 20 k (R 1/G 1/50 S) to 100 k (R 1/G 1/10 S).18. The more horizontal the curve. In equation form.5 Plot of gm vs. the output impedance will typically appear as yos with the units of S.6 as the slope of the horizontal characteristic curve at the point of operation. The parameter yos is a component of an admittance equivalent circuit.12) VGS constant 9. while a value of 1012 FET Output Impedance Zo The output impedance of FETs is similar in magnitude to that of conventional BJTs.11) The output impedance is defined on the characteristics of Fig. On FET specification sheets. Zo (FET) rd 1 yos (9. 9. FET Input Impedance Zi The input impedance of all commercially available FETs is sufficiently large to assume that the input terminals approximate an open circuit. the greater the output impedance. If perfectly horizontal. In equation form. Zi (FET) For a JFET a practical value of 109 to 1015 is typical for MOSFETs.83 mS 2 2 mS 1 0 1 2 IDSS 4 3 4 IDSS 2 5 6 7 8 IDSS 9 10 ID (mA) Figure 9. rd VDS ID (9. ID for a JFET with IDSS 8 mA and VGS 4 V.3 and 9.

Substituting into Eq. (9.2 mA. resulting in a ID of 0. EXAMPLE 9.12).1 mA.5.6 Definition of rd using FET drain characteristics. resulting in a . ID (mA) 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ∆ VDS = 8 V VGS = −2 V ∆ ID = 0. 9.1 mA VGS = −3 V VGS = −4 V VDS (V) ∆VDS = 5 V VGS = 0 V ∆ ID = 0. This is accomplished by drawing a straight line approximating the VGS line at the point of operation.2 mA VGS = −1 V 0 V and VGS Figure 9. Note the requirement when applying Eq. a tangent line is drawn and VDS is chosen as 5 V.7 Drain characteristics used to calculate rd in Example 9. Substituting into Eq. A VDS or ID is then chosen and the other quantity measured off for use in the equation.2 mA 25 k VGS 0 V 2 V. Solution For VGS 0 V. (9.7 for VGS 2 V at VDS 8 V.gm ID (mA) VGS = 0 V ∆VDS ∆ID rd = VGS = constant at −1 V VGS Q-point ∆VDS −2 V −1 V ∆ ID 0 VDS (V) Figure 9. (9.12) that the voltage VGS remain constant when rd is determined.12). a tangent line is drawn and For VGS ID of 0. 408 Chapter 9 FET Small-Signal Analysis VDS is chosen as 8 V. rd VDS ID 5V 0.5 Determine the output impedance for the FET of Fig.

The input impedance is represented by the open circuit at the input terminals and the output impedance by the resistor rd from drain to source. with lower values typically occurring at lower levels of VGS (closer to 0 V). a model for the FET transistor in the ac domain can be constructed.1 mA 80 k revealing that rd does change from one operating region to another. take note of the fact that the source is common to both input and output circuits while the gate and drain terminals are only in “touch” through the controlled current source gmVgs. Given yfs 3. In addition.gm rd VDS ID VGS 2V 8V 0. 9. G + Vgs − 3. G + Vgs − gmVgs rd D S S Figure 9. sketch the FET ac equivalent model. FET AC Equivalent Circuit Now that the important parameters of an ac equivalent circuit have been introduced and discussed. EXAMPLE 9.8.2 FET Small-Signal Model 409 .8 FET ac equivalent circuit. Note that the gate to source voltage is now represented by Vgs (lower-case subscripts) to distinguish it from dc levels. The control of Id by Vgs is included as a current source gmVgs connected from drain to source as shown in Fig.9.6 Solution gm yfs 3. In situations where rd is ignored (assumed sufficiently large to other elements of the network to be approximated by an open circuit). The current source has its arrow pointing from drain to source to establish a 180° phase shift between output and input voltages as will occur in actual operation.6.8 mS and rd 1 yos 1 20 S 50 k resulting in the ac equivalent model of Fig. 9.8 mS and yos 20 S. 9. the equivalent circuit is simply a current source whose magnitude is controlled by the signal Vgs and parameter gm — clearly a voltage-controlled device.9 FET ac equivalent model for Example 9.8 × 10−3 Vgs 50 kΩ D S S Figure 9.

Zo. a number of fundamental FET small-signal configurations will be investigated.13) because of the open-circuit equivalence at the input terminals of the JFET. The fixed-bias configuration of Fig. The applied signal is represented by Vi and the output signal across RD by Vo. The approach will parallel the ac analysis of BJT amplifiers with a determination of the important parameters of Zi. +VDD RD D C1 Vi G C2 Vo RG Zi S Zo – + VGG Figure 9. they act as short-circuit equivalents for the ac analysis.10 JFET fixed-bias configuration.10.gm 9. or characteristics. 9. Once the level of gm and rd are determined from the dc biasing arrangement. 9. the ac equivalent model can be substituted between the appropriate terminals as shown in Fig. Note that both capacitors have the short-circuit equivalent because the reactance XC 1/(2 fC) is sufficiently small compared to other impedance levels of the network.3 JFET FIXED-BIAS CONFIGURATION Now that the FET equivalent circuit has been defined. the direction of the current source reverses. specification sheet. which defines the direction of gmVgs.11. and the dc batteries VGG and VDD are set to zero volts by a short-circuit equivalent. Zi: Figure 9. XC ≈ 0 Ω 1 XC ≈ 0 Ω 2 Vi G D Vo RD Zo Battery VDD replaced by short RG Zi Battery VGG replaced by short gmVgs rd S Figure 9.10 includes the coupling capacitors C1 and C2 that isolate the dc biasing arrangement from the applied signal and load. Note the defined polarity of Vgs. If Vgs is negative.11 is then carefully redrawn as shown in Fig.12 clearly reveals that Zi RG (9. 9. The network of Fig.12. and Av for each configuration.11 Substituting the JFET ac equivalent circuit unit into the network of Fig. 9. 410 Chapter 9 FET Small-Signal Analysis . 9.

3 JFET Fixed-Bias Configuration 411 . The result is gmVgs 0 mA.11. Zo: Setting Vi 0 V as required by the definition of Zo will establish Vgs as 0 V also.12 Redrawn network of Fig.12.16) (9. 9. Av: Solving for Vo in Fig. the approximation rd RD RD can often be applied and Zo RD rd 10RD (9. we find Vo but and so that Av If rd 10RD: Av Vo Vi gmRD rd 10RD gmVgs(rd RD) Vi gmVi(rd RD) Vgs Vo Vo Vi gm(rd RD) (9. and the current source can be replaced by an open-circuit equivalent as shown in Fig. 9.17) Phase Relationship: The negative sign in the resulting equation for Av clearly reveals a phase shift of 180° between input and output voltages.gm G D + Vi Zi RG + Vgs gmVgs rd RD Zo + Vo – – S – Figure 9. 9.13 Determining Zo.13. The output impedance is Zo RD rd (9.14) If the resistance rd is sufficiently large (at least 10 1) compared to RD. 9.15) D gmVgs = 0 mA rd RD Zo S Figure 9.

412 Chapter 9 FET Small-Signal Analysis .88 mS)(2 k ) 3. Solution (a) gm0 gm (b) rd 2IDSS VP gm0 1 2(10 mA) 8V VGSQ VP 2.1 had an operating point defined by VGSQ 2 V and IDQ 5.85 k (d) Zo RD rd 2 k 25 k gm(RD rd) (1. The self-bias configuration of Fig.5 mS 1 1 1 25 k yos 40 S (c) Zi RG 1 M 1.88 mS 2.5 mS ( 2 V) ( 8 V) 1.14 with an applied signal Vi.gm EXAMPLE 9. (b) Find rd.88 mS)(1. (c) Determine Zi. (f) Determine Av ignoring the effects of rd.14 JFET configuration for Example 9. The network is redrawn as Fig.7. (d) Calculate Zo.5 1 between rd and RD 9. (e) Determine the voltage gain Av. 9. a ratio of 25 k 2 k resulted in a difference of 8% in solution. 20 V 2 kΩ D C1 G C2 IDSS = 10 mA VP = −8 V S Zo 2V + + 1 MΩ Vi Zi Vo – – Figure 9. 12.48 gmRD (1.7 The fixed-bias configuration of Example 6. (a) Determine gm.15 requires only one dc supply to establish the desired operating point.85 k ) (e) Av 3. with IDSS 10 mA and VP 8 V. The value of yos is provided as 40 S.76 (f) Av As demonstrated in part (f).625 mA.4 JFET SELF-BIAS CONFIGURATION Bypassed RS The fixed-bias configuration has the distinct disadvantage of requiring two dc voltage sources. 9.

9.15 following the substitution of the JFET ac equivalent circuit. the resulting equations Zi. Zo. Since the resulting configuration is the same as appearing in Fig. and Av will be the same.16 Network of Fig.16 and carefully redrawn in Fig. 9.12.4 JFET Self-Bias Configuration . If left in the ac. 9.15 Self-bias JFET configuration. allowing RS to define the operating point.18) 413 9. gain will be reduced as will be shown in the paragraphs to follow. The JFET equivalent circuit is established in Fig. the capacitor assumes the short-circuit state and “short circuits” the effects of RS. 9. G D + Vi Zi RG + Vgs gmVgs rd RD Zo + Vo – – S – Figure 9.17 Redrawn network of Fig.gm RD D C1 Vi G S Zi RG RS CS Zo C2 Vo Figure 9. XC ≈ 0 Ω 1 XC ≈ 0 Ω 2 Vi G D Vo gmVgs RG S rd RD Zo Zi RS bypassed by X C S VDD Figure 9. Zi: Zi RG (9.16. The capacitor CS across the source resistance assumes its short-circuit equivalence for dc. 9. Under ac conditions.17.

20) gm(rd RD) (9. In this case. The voltage across RG is then 0 V.18 Self-bias JFET configuration including the effects of RS with rd Zi: Due to the open-circuit condition between the gate and output network.18 will result in the gate terminal being at ground potential (0 V).21) Phase relationship: The negative sign in the solutions for Av again indicates a phase shift of 180° between Vi and Vo. Zo Av : Av If rd 10RD. Figure 9.23) Vi 0 Setting Vi 0 V in Fig. 9. Av gmRD (9.18. the resistance rd will be left out of the analysis to form a basis for comparison. 9.22) rd 10RD rd RD (9. Initially. there is no obvious way to reduce the network to lower its level of complexity.15. the input remains the following: Zi Zo: The output impedance is defined by Zo Vo Io RG (9.gm Zo: Zo If rd 10RD. 414 Chapter 9 FET Small-Signal Analysis . Unbypassed RS If CS is removed from Fig 9. one must simply be very careful with notation and defined polarities and direction. the resistor RS will be part of the ac equivalent circuit as shown in Fig. and Av.19) RD rd 10RD (9. G D ID gmVgs Zo RD Vo + Zi Vi RG + Vgs + – S RS – Io – . In determining the levels of Zi. Zo. and RG has been effectively “shorted out” of the picture.

the equivalent will appear as shown in Fig.19 Including the effects of rd in the self-bias JFET configuration.4 JFET Self-Bias Configuration 415 . Since Zo Vo Io Vi 0V IDRD Io we should try to find an expression for Io in terms of ID. 9.19.gm Applying Kirchhoff’s current law will result in: Io with so that or and Since then and Vo Zo Vo Io Io ID Io ID Vgs gm (Io Io[1 gmRS] ID (Io ID)RS ID[1 gmVgS ID)RS gmIoRS gmRS] 0A gmIDRS (the controlled current source gmVgs for the applied conditions) Vo IDRD IoRD ( Io)RD RD rd (9. so that with the result that Io gm Io gm Io gmVgs Vrd gmVgs Vo Vo rd IDRD rd (ID Ird Vgs Vgs ID IDRD ID 1 Vgs rd Vgs ID using Vo Io) RS Io) RS RS rd RS rd RS rd IDRD rd ID 1 RD rd ID 1 (ID rd Io 1 ID 1 gmRs gmRS gmRS RS rd RD rd or Io 1 gmRS 9.24) ∝ If rd is included in the network. G + Zi Vi RG Vgs − + gmVgs S rd − RD a + I′ ID D Io Zo Vo + RS − Io + ID Io − Figure 9. Applying Kirchhoff’s current law: Io but and or Now.

9.25b) rd 10RD Av: For the network of Fig.26) IDRS] RD rd gmVi RD rd ( IDRD) (IDRS) rd RS gmVi gmRS gmRS RS 1 416 Chapter 9 FET Small-Signal Analysis . an application of Kirchhoff’s voltage law on the input circuit will result in Vi Vgs Vo and I Vgs Vi VRS ID RS 0 The voltage across rd using Kirchhoff’s voltage law is VRS Vo VRS rd so that an application of Kirchhoff’s current law will result in Vo VRS ID gmVgs rd Substituting for Vgs from above and substituting for Vo and VRS we have ID so that or gm[Vi ID 1 ID 1 The output voltage is then Vo IDRD 1 and Av Vo Vi gmRDVi RD gmRS gmRD RD gmRS RS rd RS rd (9.25a) For rd 1 10 RD.gm and Zo Vo Io IDRD ID 1 gmRs 1 1 and finally.19. 1 gmRS gmRS RD and 1 rd RS and rd Zo RD (9. Zo 1 RS rd gmRS RS rd Rs rd RD rd RS rd gmRS RS rd gmRS RD RD rd gmRS RS rd RD rd (9.

3 kΩ C2 Vo C1 Vi IDSS = 10 mA VP = −6 V Zo 1 MΩ 1 kΩ EXAMPLE 9.2 has an operating point defined by VGSQ 6 V. (e) Calculate Av with and without the effects of rd. with IDSS 8 mA and VP drawn as Fig. Av Vo Vi 1 gmRD gmRS rd 10(RD RS) (9.8 Zi Figure 9. (9.26) again reveals that a 180° phase shift will exist between Vi and Vo.3 k 33 k If rd Zo (e) With rd: Av 1 1.gm Again. The self-bias configuration of Example 6. if rd 10(RD RS). Compare the results.3 k 1k (1. (a) Determine gm.51 mS 1 yos (c) Zi RG (d) With rd: Therefore.6 mA.3 k 3.4 JFET Self-Bias Configuration gmRS gmRD RD rd RS 1 (1. The value of yos is given as 20 S.8.6 V and IDQ 2.3 k ) 3.20 with an applied signal Vi. The network is re2.67 mS 1 VP 50 k ( 2.51 mS)(1 k ) 50 k 417 . Solution (a) gm0 gm (b) rd 2IDSS VP gm0 1 2(8 mA) 2.92 9. 9.51 mS)(3.67 mS 6V VGSQ 2. (c) Find Zi.20 Network for Example 9.6 V) ( 6 V) 1. (b) Find rd. Compare the results. (d) Calculate Zo with and without the effects of rd. 20 V 3.27) Phase Relationship: The negative sign in Eq. 1 20 S 1M rd 50 k Zo RD RD 10 RD 3.

3 k ) 1 (1. however. R1 RD G D Vi R2 + Vgs gmVgs RD Vo Vi Zi + Zo R1 R2 Vgs gmVgs rd RD Vo Zi Zo – Figure 9.23. 9. Substituting the ac equivalent model for the JFET will result in the configuration of Fig.21.22. Since each network has a common ground.gm Without rd: Av gm RD 1 gmRS (1.22 Network of Fig. 9.51 mS)(1 k ) 1. which will have a very positive effect on the overall gain of a system.51 mS)(3.21 JFET voltage-divider configuration.98 As above. 9. that Zi is magnitudes greater than the typical Zi of a BJT.23 Redrawn network of Fig. – Figure 9. Note also that the typical gain of a JFET amplifier is less than that generally encountered for BJTs of similar configurations. RD can also be brought down to ground but in the output circuit across rd. The resulting ac equivalent network now has the basic format of some of the networks already analyzed. 418 Chapter 9 FET Small-Signal Analysis . 9. +VDD RD R1 C1 D G S Vi R2 Zo C2 Vo Zi RS CS Figure 9. R1 can be brought down in parallel with R2 as shown in Fig.21 under ac conditions. the effect of rd was minimal because the condition rd 10(RD RS) was satisfied.22. 9. Replacing the dc supply VDD by a short-circuit equivalent has grounded one end of R1 and RD.5 JFET VOLTAGE-DIVIDER CONFIGURATION The popular voltage-divider configuration for BJTs can also be applied to JFETs as demonstrated in Fig. Keep in mind. 9.

which is now sensitive to the parallel combination of R1 and R2. Note that the output is taken off the source terminal and. The only difference is the equation for Zi.32) Note that the equations for Zo and Av are the same as obtained for the fixed-bias and self-bias (with bypassed RS) configurations.30) rd 10RD Av : Vgs and so that and If rd 10RD.6 JFET SOURCE-FOLLOWER (COMMON-DRAIN) CONFIGURATION The JFET equivalent of the BJT emitter-follower configuration is the source-follower configuration of Fig. the drain is grounded (hence. when the dc supply is replaced by its short-circuit equivalent.gm Zi: R1 and R2 are in parallel with the open-circuit equivalence of the JFET resulting in Zi Zo: Setting Vi R1 R2 (9. 9. Av Vo Vi gmRD rd 10RD Vi gmVgs(rd RD) Vgs gm(rd RD) (9. 9. VDD D C1 Vi G S Zi RG RS Zo C2 Vo Figure 9.28) 0 V will set Vgs and gmVgs to zero and Zo rd RD (9.6 JFET Source-Follower (Common-Drain) Configuration 419 . 9.29) For rd 10RD.24. Zo RD (9.24 JFET source-follower configuration. the terminology common-drain).31) Vo Av Av Vo Vi Vo Vi gmVgs(rd RD) (9.

Vi G D + Zi RG Vgs gmVgs rd Io – S Vo Vi Zi RS Zo RG G S Vgs gmVgs D + – Zo rd RS + Vo – Figure 9. 9. 9.27 Determining Zo for the network of Fig.25 redrawn. Io gmVgs Ird Vo rd The result is Io Vo Vo Vo 1 rd 1 rd 1 rd 1 RS 1 RS 1 RS IRS Vo RS gmVgs gm[ Vo] gm 420 Chapter 9 FET Small-Signal Analysis . they can all be placed in parallel as shown in Fig. The current source reversed direction but Vgs is still defined between the gate and source terminals. 9. The controlled source and internal output impedance of the JFET are tied to ground at one end and RS on the other.25 Network of Fig. rd. Applying Kirchhoff’s current law at node s.24.27. with Vo across RS. and RS are connected to the same terminal and ground.25.gm Substituting the JFET equivalent circuit will result in the configuration of Fig.26 Network of Fig. 9. Zi: Figure 9. 9.26 clearly reveals that Zi is defined by Zi RG (9.26. Since gmVgs.24 following the substitution of the JFET ac equivalent model. Figure 9. The fact that Vgs and Vo are across the same parallel Vgs.33) Zo: Setting Vi 0 V will result in the gate terminal being connected directly to ground as shown in Fig. 9. network results in Vo S Io – Vgs gmVgs Zo rd RS + Vo + – Figure 9.

– 9.05 µ F Zi 1 MΩ 0. A dc analysis of the source-follower network of Fig. (d) Calculate Zo with and without rd.36) gmVi(rd RS) gm(rd RS) gm(rd RS) 10RS.86 V EXAMPLE 9.gm 1 1 1 1 1 1 1 gm gm rd RS rd RS 1/gm which has the same format as the total resistance of three parallel resistors. (a) Determining gm.6 JFET Source-Follower (Common-Drain) Configuration 421 . Compare results. Compare results.28 Network to be analyzed in Example 9. Phase Relationship: Since Av of Eq.36) is larger than the numerator by a factor of one. 2. Vo Vi 1 gmRS gmRS (9. Vo and Vi are in phase for the JFET source-follower configuration.28 will result in VGSQ and IDQ 4.9 +9 V IDSS = 16 mA VP = − 4 V yos = 25 µS + Vi 0. (c) Determine Zi. 9. (b) Find rd.9.56 mA. Therefore.26 will result in Vi and so that or and so that In the absence of rd or if rd Av Vo Vo[1 Av Vo Vgs gm(Vi gm(rd RS)] Vo Vi 1 Vgs Vi Vo Vo Vo)(rd RS) gmVo(rd RS) gmVi(rd RS) (9. and Zo Vo Io 1 Vo rd Zo For rd 10RS.35) Av: The output voltage Vo is determined by Vo gmVgs(rd RS) and applying Kirchhoff’s voltage law around the perimeter of the network of Fig.34) (9.05 µ F 2. (e) Determine Av with and without rd. (9.36) is a positive quantity. 9.2 kΩ Zo + Vo – Figure 9. Zo RS 1/gm rd 10RS Vo 1 RS rd RS 1/gm (9.37) rd 10RS Since the bottom of Eq. (9. the gain can never be equal to or greater than one (as encountered for the emitter-follower BJT network).

(e) With rd: Av (2.6 365.02 (2.83 1 (2.28 mS 438.2 k ) 1 (2.28 mS)(40 k 2.28 mS 1 yos (c) Zi RG (d) With rd: 1/2. Without rd: Zo RS 1/gm 2.28 mS)(40 k 2.30.83 revealing that rd usually has little impact on the gain of the configuration.09 k ) 4. In addition.2 k ) 1 gm(rd RS) (2.2 k ) gm(rd RS) 1 (2.7 JFET COMMON-GATE CONFIGURATION The last JFET configuration to be analyzed in detail is the common-gate configuration of Fig. Note the continuing requirement that the controlled source gmVgs be connected from drain to source with rd in parallel.6 revealing that Zo is often relatively small and determined primarily by 1/gm.69 revealing that rd typically has little impact on Zo. Without rd: Av gmRS 1 gmRS 5.29.77 0.77 which is less than 1 as predicted above.28 mS)(2.09 k ) 1 4. 422 Chapter 9 FET Small-Signal Analysis .2 k ) 0.02 1 5.28 mS)(2. 9. 9. Substituting the JFET equivalent circuit will result in Fig.28 mS)(2.gm Solution (a) gm0 gm (b) rd 2IDSS VP gm0 2(16 mA) 8 mS 4V VGSQ ( 2.52 2.2 k 438. Note also the location of the controlling voltage Vgs and the fact that it appears directly across the resistor RS. the resistor connected between input terminals is no longer RG but the resistor RS connected from source to ground.28 mS)(2. 9. which parallels the common-base configuration employed with BJT transistors.2 k 362.86 V) 1 8 mS 1 VP ( 4 V) 1 40 k 25 S 1M Zo rd RS 1/gm 40 k 2.2 k 40 k 2. The isolation between input and output circuits has obviously been lost since the gate terminal is now connected to the common ground of the network.

Figure 9.31 Determining Z i for the network of Fig.29.29.31.29 JFET common-gate configuration. Applying Kirchhoff’s voltage law around the output perimeter of the network will result in V and I' Vrd V VRD VRD V 0 I RD Vrd I' a Z'i gmVgs Vi Vgs Applying Kirchhoff’s current law at node a results in I and or so that I Ird I I 1 gmVgs V rd RD rd gmVgs (V I RD rd V 1 and Zi V I V I gm Ird I RD) rd gm[ V ] 1 rd RD rd 1 rd gm gmVgs or + – – I' + Ird + rd V r d – + RD VRD – Figure 9. 9.gm – C1 C1 S D C2 a S rd + D b C2 + Vi Zi RS Z'i G RD VDD Zo + + Vi Vo Zi RS – gmVgs Vgs Z'o RD Zo + Vo – – – +G – Figure 9. Let us therefore find the impedance Z i of Fig. which will simply be in parallel with RS when Zi is defined.29 following substitution of JFET ac equivalent model. 9. Zi: The resistor RS is directly across the terminals defining Zi.7 JFET Common-Gate Configuration 423 . The network of interest is redrawn as Fig.30 Network of Fig.38) Zi rd RD 1 gmrd 9. The voltage V Vgs. 9. (9. 9.

and rd will be in parallel with RD. Therefore.30 will “short-out” the effects of RS and set Vgs to 0 V. Eq.40) rd 10RD and Zi RS 1/gm Zo: Substituting Vi 0 V in Fig. The result is gmVgs 0.30 reveals that Vi and The voltage across rd is Vrd and Ird Vo Vo rd Vi Vi Vo Vgs IDRD RD rd 10RD RD rd (9.42) Applying Kirchhoff’s current law at node b in Fig.39) 1 and 10RD. 9.41) (9.30 results in Ird and ID Vo rd ID so that Vo IDRD ViRD rd and Vo 1 RD rd Vi rd Vi rd VoRD rd Vi RD rd Vo Vo ID gmVgs Ird Vi 0 gmVgs gm[ Vi] gmVi gmVi RD gm gmRD 424 Chapter 9 FET Small-Signal Analysis .gm and results in If rd 1/rd Zi Zi RS RS Z i rd RD 1 gmrd (9. (9. Zo Av: Figure 9. Zo For rd 10RD.38) permits the following approximation since RD /rd gm: 1 Zi gm RD rd 1 rd 1 gm (9. 9.

+12 V EXAMPLE 9.6 kΩ 10 µ F Vo IDSS = 10 mA VP = − 4 V yos = 50 µS 10 µ F 1.2 V and IDQ 2.1 k 0.32 Network for Example 9.43) For rd 10RD.1 kΩ + Vi = 40 mV – Figure 9.6 k (2.25 ms)(20 k ) 9.2 V) 5 mS 1 VP ( 4 V) 1 50 S 20 k 2.gm gmRD with Av Vo Vi 1 RD rd RD rd (9.32 may not initially appear to be of the common-gate variety. (c) Calculate Zi with and without rd.29. Solution (a) gm0 gm (b) rd 2IDSS VP gm0 1 2(10 mA) 5 mS 4V VGSQ ( 2.35 k 1 20 k 3. Although the network of Fig. Compare results. Compare results.7 JFET Common-Gate Configuration 425 . the factor RD /rd of Eq. 2.03 mA: If VGSQ (a) Determine gm.1 k 0.43) can be dropped as a good approximation and Av gmRD rd 10RD (9. (b) Find rd. 9.25 mS 1 yos (c) With rd: Zi rd RD 1 gmrd 1. 9.51 k RS 1. a close examination will reveal that it has all the characteristics of Fig. (d) Find Zo with and without rd.44) Phase Relationship: The fact that Av is a positive number will result in an inphase relationship between Vo and Vi for the common-gate configuration. (e) Determine Vo with and without rd. Compare results.10 3. (9.10.

In fact. In this case. both equations result in essentially the same level of impedance.25 mS)(3.gm Without rd: Zi RS 1/gm 0.02)(40 mV) In this case.1 0. 426 Chapter 9 FET Small-Signal Analysis .1)(40 mV) 8.1 324 mV Av Vo Vi ➤ Vo AvVi 7.8 DEPLETION-TYPE MOSFETs The fact that Shockley’s equation is also applicable to depletion-type MOSFETs results in the same equation for gm.31 k 1. rd 10RD 20 k 10(3. the difference is a little more noticeable but not dramatically so. (e) With rd: RD 3.1 k 1/2.18 and Without rd: Av with Vo gmRD AvVi (2.25 mS)(3.33. The only difference offered by D-MOSFETs is that VGSQ can be positive for n-channel devices and negative for p-channel units. 9. The result is that gm can be greater than gm0 as demonstrated by the example to follow. Example 9.10 demonstrates that even though the condition rd 10RD was not satisfied. 1/gm was the predominant factor. the results for the parameters given were not significantly different using the exact and approximate equations. The range of rd is very similar to that encountered for JFETs.44 k Even though the condition. In fact. the ac equivalent model for D-MOSFETs is exactly the same as that employed for JFETs as shown in Fig. (d) With rd: Zo Without rd: Zo RD 3.6 k gmRD (2. the approximate equations can be used to find a reasonable idea of particular levels with a reduced amount of effort.8 mV RD rd 3.25 ms 1. RD is certainly the predominant factor in this example.6 k Again the condition rd 10RD is not satisfied. but both results are reasonably close.02 280.6 k 20 k 3.6 k 1 1 rd 20 k 8.6 k ) rd 20 k Av RD 3. in most cases. 9.6 k ) 20 k 36 k is not satisfied.1 k 0.6 k ) (8.05 k (7.18 1 0.

18 V (e) Calculate Zo.33 D-MOSFET ac equivalent model. (a) Determine gm and compare to gm0.8.11 Vo C1 Vi Zi 10 MΩ 150 Ω IDSS = 6 mA VP = − 3 V yos = 10 µS Zo Figure 9.8 Depletion-Type MOSFETs 427 . G D + Vi Zi 10 MΩ 110 MΩ + Vgs 4. The network of Fig.117) 4. (b) Find rd. 9. 9. 9. (f) Find Av.47 mS 1 1 100 k yos 10 S (c) See Fig.6 mA.35 AC equivalent circuit for Fig. (d) Find Zi.34.35.8 kΩ 110 MΩ C2 0.47 × 10 −3 Vgs 100 kΩ 1.34.23. 9. 9. Equations (9. Solution (a) gm0 gm (b) rd 2IDSS VP gm0 1 2(6 mA) 4 mS 3V VGSQ 4 mS 1 VP ( 0. 9.11.35 V EXAMPLE 9. Note the similarities with the network of Fig.34 was analyzed as Example 6. 1.gm G D G S S + G D Vgs gmVgs rd – S Figure 9.35 V) ( 3 V) 4 mS(1 0.34 Network for Example 9.8 kΩ Zo + Vo – S – S – Figure 9.28) through (9. resulting in VGSQ and IDQ 7. (c) Sketch the ac equivalent network for Fig.32) are therefore applicable.

28): Zi R1 R2 10 M 110 M 9. (9. (9.36 Enhancement MOSFET ac small-signal model.8 k 18 k (f) rd 10RD → 100 k gmRD (4.9 ENHANCEMENT-TYPE MOSFETs The enhancement-type MOSFET can be either an n-channel (nMOS) or p-channel (pMOS) device. The device transconductance. 9.8 k 9. yfs.77 k RD (e) Eq.32): Av 1.45) Chapter 9 FET Small-Signal Analysis . an equation for gm was derived from Shockley’s equation.36. as shown in Fig.8 k ) 8.47 mS)(1. 9. is provided on specification sheets as the forward transfer admittance. There is an output impedance from drain to source rd. For E-MOSFETs.36. rd = 1 yos Figure 9. the relationship between output current and controlling voltage is defined by ID Since gm is still defined by gm ID VGS k(VGS VGS(Th))2 we can take the derivative of the transfer equation to determine gm as an operating point. gm. D G S pMOS G D gmVgs rd + Vgs D G S nMOS – S gm =yfs . In our analysis of JFETs.gm (d) Eq. The ac small-signal equivalent circuit of either device is shown in Fig.17 M 1.05 Eq. revealing an open-circuit between gate and drainsource channel and a current source from drain to source having a magnitude dependent on the gate-to-source voltage. gm dID dVGS d k(VGS dVGS 2k(VGS and 428 VGS(Th))2 k d (VGS dVGS VGS(Th)) VGS(Th)) VGS(Th))2 2k(VGS VGS(Th))(1 0) VGS(Th)) gm d (VGS dVGS 2k(VGSQ (9. That is.29): Zo rd RD 100 k 1. which is usually provided on specification sheets as an admittance yos. (9.

Otherwise.gm Recall that the constant k can be determined from a given typical operating point on a specification sheet. Zi: Applying Kirchhoff’s current law to the output circuit (at node D in Fig.10 E-MOSFET DRAIN-FEEDBACK CONFIGURATION The E-MOSFET drain-feedback configuration appears in Fig. 9. however. the input and output terminals would be connected directly and Vo Vi. 9.46) gm(rd RD)] Vi Ii RF 1 rd RD gm(rd RD) 9. VDD RD RF D C1 Vi Zi G S Zo C2 Vo Ii Ii G Zi D gmVgs rd RD RF + Vi + Vgs Vo Zo – – S Figure 9. Recall from dc calculations that RG could be replaced by a short-circuit equivalent since IG 0 A and therefore VRG 0 V. In every other respect. that the characteristics of an E-MOSFET are such that the biasing arrangements are somewhat limited. with and so that and finally.37 E-MOSFET drain-feedback configuration. Substituting the ac equivalent model for the device will result in the network of Fig.38 AC equivalent of the network of Fig. Ii Vi RF IiRF Vi[1 Zi Vi Vo Vo Ii Ii Vgs gmVi gmVi Vi Vo rd RD Vo rd RD gmVi) (rd RD)(Ii gmVi) Vi (rd RD)(Ii RF (rd RD)Ii (rd RD)gmVi Ii[RF rd RD] (9.37. 9.38) results in Vo Ii gmVgs rd RD and so that or Therefore. Be aware. the ac analysis is the same as that employed for JFETs or D-MOSFETs.37. However.10 E-MOSFET Drain-Feedback Configuration 429 . Note that RF is not within the shaded area defining the equivalent model of the device but does provide a direct connection between input and output circuits. 9. for ac situations it provides an important high impedance between Vo and Vi.38. 9. Figure 9.

RF is so much larger than rd RD that Zo and with rd 10RD.39.37.48) RF Vi = Vgs = 0 V gmVgs = 0 mA rd RD Zo Figure 9. RF rd RD. rd. 9. Normally. rd 10RD rd RD (9. Zo RD RF rd RD.38 will result in Ii but so that and so that Vo Vgs Vi RF Vi RF 1 rd RD Vo RF 1 RF gmVgs Vi and Ii Vo gmVi gmVi Vi Vo rd RD Vi RF Vo rd RD Vo rd RD 1 RF gm Vo and Av Vo Vi 1 gm RF 1 1 rd RD RF 430 Chapter 9 FET Small-Signal Analysis . rd 10RD 1 RF gm(rd RD) (9.gm Typically. Zi RF 1 gmRD RF rd RD.39 Determining Zo for the network of Fig.47) Zo: Substituting Vi 0 V will result in Vgs 0 V and gmVgs 0. and RD are then in parallel and Zo RF rd RD (9. so that Zi For rd 10RD. 9. 9.49) Av: Applying Kirchhoff’s current law at node D of Fig. with a shortcircuit path from gate to ground as shown in Fig. RF.

(b) Find rd.92 k 2. (c) Calculate Zi with and without rd.40 was analyzed in Example 6. Solution (a) gm 2k(VGSQ VGS(Th)) 2(0. (a) Determine gm.4 V 3 V) 10 M 50 k 2 k rd RD 1 (1. 9.24 1.10 E-MOSFET Drain-Feedback Configuration 431 .42 M 1 3. (d) Find Zo with and without rd.40 Drain-feedback amplifier from Example 6.63 mS 1 1 50 k (b) rd yos 20 S (c) With rd: Zi RF 10 3 A/V2)(6.4 V. Compare results. EXAMPLE 9. (9. VGSQ 6. Compare results.50) gm Av rd RD and if rd Av gmRD gm(RF rd RD) 10RD.11.11.75 mA.51) RF rd RD. with the result that k 0. (e) Find Av with and without rd. The E-MOSFET of Fig. Compare results.12 12 V 2 kΩ Vo 1 µF 10 MΩ Vi 1 µF Zi Zo ID ( on) = 6 mA VGS (on) = 8 V VGS (Th) = 3 V yos = 20 µS Figure 9. and IDQ 2.24 10 3 A/V2.63 mS)(50 k 2 k ) 1 gm(rd RD) 10 M 1.but and so that Since RF is usually 1 rd RD 1 RF gm 1 RF rd RD 1 RF (9.13 9. rd 10RD Phase Relationship: The negative sign for Av reveals that Vo and Vi are out of phase by 180°.

41.63 mS)(2 k ) 2.11 E-MOSFET VOLTAGE-DIVIDER CONFIGURATION The last E-MOSFET configuration to be examined in detail is the voltage-divider network of Fig.53 M 40 k is satisfied.21 RD 2k RF rd RD 1. Substituting the ac equivalent network for the E-MOSFET will result in the configuration of Fig. 9.92 k 10 M 50 k 2k 49.26 (1. Figure 9.32) are applicable as listed below for the E-MOSFET. 9.42 AC equivalent network for the configuration of Fig. The format is exactly the same as appearing in a number of earlier discussions.28) through (9. (e) With rd: Av gm(RF rd RD) (1. (d) With rd: Zo Without rd: Zo again providing very close results.gm Without rd: Zi 1 RF gmRD 1 10 M (1.75 k 2k 2k ) Without rd: Av gmRD 3. (9. RD R1 D C1 Vi S Zi R2 RS CS Vi Zi R1 R2 Vgs gmVgs rd RD Zo G D Vo VDD + G Vo Zo – S Figure 9.23. The result is that Eqs. 9.42. which is exactly the same as Fig.63 mS)(2 k ) which is very close to the above result.41.92 k ) 3.41 E-MOSFET voltage-divider configuration.63 mS)(10 M 50 k (1.63 mS)(1. the revealing that since the condition rd 10RD 50 k results for Zo with or without rd will be quite close. 9. 9. 432 Chapter 9 FET Small-Signal Analysis .

simply keep in mind that network parameters can affect the dc and ac levels in different ways. or output impedance. the approximate equations are often employed because some variation will occur when calculated resistors are replaced by standard values.53) (9. In most cases. Once the initial design is completed. 9.54) 9. a small RS will also contribute to a higher gain. the available dc supply voltage is known.12 Designing FET Amplifier Networks 433 . In the unbypassed RS network.gm Zi: Zi Zo: Zo For rd 10RD. In most situations.52) rd RD (9.55) RD rd 10RD R1 R2 (9. The next three examples will determine the required parameters for a specific gain. it presents an important high impedance path between Vo and Vi. In addition. but for the ac analysis. Throughout the design procedure be aware that although superposition permits a separate analysis and design of the network from a dc and an ac viewpoint. Often a balance must be made between a particular operating point and its impact on the ac response.56) Vo Vi gm(rD RD) (9. requiring that RS be relatively small. To avoid unnecessary complexity during the initial stages of the design. a parameter chosen in the dc environment will often play an important role in the ac response. but for the source-follower. It is then necessary to determine the resistive elements necessary to establish the desired gain or impedance level. In total. recall that gm is larger for operating points closer to the ID axis (VGS 0 V). the results can be tested and refinements made using the complete equations.12 DESIGNING FET AMPLIFIER NETWORKS Design problems at this stage are limited to obtaining a desired dc bias condition or ac voltage gain. recall that the resistance RG could be replaced by a short-circuit equivalent in the feedback configuration because IG 0 A for dc conditions. In particular. the various equations developed are used “in reverse” to define the parameters necessary to obtain the desired gain. the gain is reduced from its maximum value of 1. input impedance. and the capacitors to be employed at the chosen frequency are defined. Av Vo Vi gmRD (9. Zo Av : Av and if rd 10RD. the FET to be employed has been determined.

gm EXAMPLE 9.43 Circuit for desired voltage gain in Example 9. the level of gm is gm0. 9. we find RD rd and or with and RD 50RD RD 50 k 2k 2k 2RD 100 k 1 yos 20 1 10 6 S 50 k RD(50 k ) RD 50 k 2(RD 50 k ) 48RD 100 k 48 100 k 2. Solution Since VGSQ 0 V. That is. VDD (+30 V) RD Vo C1 Vi 0.08 k The closest standard value is 2 k (Appendix C). That is. The resulting level of VDSQ would then be determined as follows: VDSQ Zi Zo 434 Chapter 9 VDD IDQRD 30 V (10 mA)(2 k ) 10 V The levels of Zi and Zo are set by the levels of RG and RD.13.43 to have an ac gain of 10. FET Small-Signal Analysis . determine the value of RD.13 Design the fixed-bias network of Fig. respectively. which would be employed for this design. rd Substituting. RG 10 M RD rd 2 k 50 k 1.1 µF RG 10 MΩ IDSS = 10 mA VP = – 4 V yos = 20 µS Figure 9.92 k RD 2k . The gain is therefore determined by Av with The result is and gm0 gm(RD rd) 2IDSS VP 10 RD rd gm0(RD rd) 5 mS 2(10 mA) 4V 5 mS(RD rd) 10 5 mS 2k From the device specifications.

1 µF 0V 0. gm VGSQ VP ( 1 V) 5 mS 1 ( 4 V) gm0 1 3.75 mS 2.gm Choose the values of RD and RS for the network of Fig.14 RD C2 Vo C1 Vi 0. 4 VDD +20 V EXAMPLE 9. 9.13 k 2.75 mS The magnitude of the ac voltage gain is determined by Av Substituting known values will result in 8 so that RD rd (3.1 µF RL 10 MΩ IDSS = 10 mA VP = – 4 V yos = 20 µS gm 0 = 5 mS RG 10 MΩ RS CS 40 µF Figure 9.44 Network for desired voltage gain in Example 9.12 Designing FET Amplifier Networks 1 yos RD 50 k 1 20 S 50 k 2.2 k 435 .625 mA Determining gm. 9.75 mS)(RD rd) 8 3. Solution The operating point is defined by VGSQ and ID IDSS 1 VGSQ VP 1 VP 4 2 1 ( 4 V) 4 1V 2 10 mA 1 ( 1 V) ( 4 V) 5.44 that will result in a gain of 8 using a relatively high level of gm for this device defined at VGSQ 1 VP.14.13 k gm(RD rd) The level of rd is defined by rd and with the result that RD which is a standard value.

The exact and approximate equation for each important parameter are provided with a typical range of values for each. EXAMPLE 9.625 mA. and since the equation VGS IDRS has obtained in Examnot changed.13 SUMMARY TABLE In an effort to provide a quick comparison between configurations and offer a listing that can be helpful for a variety of reasons.6 k .75 mS)RD (3. We can now test the condition: rd 50 k and 50 k 10(RD 10(3.75 mS)RD 1 0.18 k ) 10(3. Using the full equation for Av at this stage of the design would simply complicate the process unnecessarily.14.78 k ) which is satisfied—the solution stands! 9. In this example. The gain of an unbypassed self-bias configuration is Av gmRD 1 gmRS For the moment it is assumed that rd 10(RD RS). In fact. Although all the possible configurations are not present.625 mA)RS 177. Table 9. 8 and so that 1 (3. RS is unbypassed and the design becomes a bit more complicated.8 1V 5. RS continues to equal the standard value of 180 ple 9.6 k 37.75 mS ) (3.75 mS)RD 3. 9. RS does not appear in the ac design because of the shorting effect of CS.75 mS)(180 8(1 RD 0.675) 13. the majority of the most frequently encountered are included.44 to establish a gain of 8 if the bypass capacitor CS is removed.675 (3. Solution VGSQ and IDQ are still 1 V and 5. Substituting (for the specified magnitude of 8 for the gain).8 k RS) 0.4 3.625 mA The closest standard value is 180 .15 Determine RD and RS for the network of Fig. any configuration not 436 Chapter 9 FET Small-Signal Analysis .gm The level of RS is determined by the dc operating conditions as follows: VGSQ 1V and RS IDRS (5.573 k with the closest standard value at 3. In the next example.1 was developed.

1 Zi.gm TABLE 9. and Av for various FET configurations Configuration Fixed-bias [JFET or D-MOSFET] +VDD Zi Zo Av Vo Vi D-MOSFET] RD C1 Vi Zi RG VGG Zo C2 Vo Medium (2 k ) High (10 M ) RG RD (rd 10 RD) Medium ( 10) gm(rd RD) RD rd gm RD (rd 10 RD) Self-bias bypassed Rs [JFET or D-MOSFET] +VDD S Medium (2 k ) C2 Vo Medium ( 10) gm(rd RD) -MOSFET] C1 Vi Zi RG RD High (10 M ) RD rd RG Zo RD (rd 10 RD) gm RD (rd 10 RD) RS CS Self-bias unbypassed RS [JFET or D-MOSFET] Low ( 2) +VDD d RS -MOSFET] C1 Vi Zi RG 1 C2 Vo gmRS gmRS RS RD rd RS rd RD rd 1 RD High (10 M ) RG Zo gmRD gmRs RD RS rd 1 RD RS rd 10 RD or rd gmRD 1 gmRS [rd 10(Rd RS)] Voltage-divider bias [JFET or D-MOSFET] vider bias -MOSFET] R1 C1 Vi Zi +VDD Medium (2 k ) RD C2 Vo Zo Medium ( 10) gm(rd RD) High (10 M ) R1 R2 RD r RD (rd 10 RD) gm RD (rd 10 RD) R2 RS CS 9.13 Summary Table 437 . Z0.

1 (Continued) Configuration Source-follower [JFET or D-MOSFET] Low ( 1) Zi Zo Av Vo Vi -MOSFET] C1 Vi Zi RG +VDD Low (100 k ) High (10 M ) C2 Vo rd RS 1/gm 1 gm(rd RS) gm(rd RS) RG RS RS 1/gm (rd 10 RS) Zo 1 gmRS gmRS (rd 10 R S) Common-gate [JFET or D-MOSFET] ate -MOSFET] C1 Vi Q1 +VDD RD Medium (2 k ) Low (1 k ) RD rd C2 Vo RS rd RD 1 gmrd RD (rd 10 RD) Medium ( 10) RD gmRD rd 1 RD rd Zi RS RG CS Zo 1 RS gm (rd 10 RD) gmRD (rd 10 R S) Drain-feedback bias E-MOSFET back bias T RF C1 Vi Zi +VDD RD C2 Vo Zo Medium (1 M ) Medium (2 k ) RF 1 rd RD gm(rd RD) RF rd RD Medium ( 10) gm(RF rd RD) 1 RF gmRD RD (rd 10 RD) (RF. rd 10 RD) Voltage-divider bias E-MOSFET ider bias T +VDD Medium (2 k ) RD R1 D Zo S C2 Vo Medium ( 10) gm(rd RD) Medium (1 M ) R1 R2 RD rd C1 Vi Zi G RD RS (Rd 10 RD) gmRD (rd 10 RD) R2 438 Chapter 9 FET Small-Signal Analysis .gm TABLE 9. rd 10 RD) gmRD (RF.

Apply a test ac signal: measure the ac voltages starting at the input and working along toward the output. which has a JFET with VP 10 mA. Look at the circuit board to see if any obvious problems can be seen: an area charred by excess heating of a component. Check Check Check Check if the supply voltage is present. The 10-M resistor was added to act as a path to ground for the capacitor 9. if the output voltage at VD is between 0 V and VDD. 4. 9. its polarity. a component that feels or seems too hot to touch.45. Even better.gm listed will probably be some variation of those appearing in the table. what appears to be a poor solder joint. any connection that appears to have come loose. the ac signal at various points should be checked using an oscilloscope to see the waveform. 3. 9. causing the nominal value to change. the ac voltage at each side of the coupling capacitor terminals. 2. A good troubleshooter has a “nose” for finding the trouble in a circuit—this ability to “see” what is happening being greatly developed through building. testing. amplitude. 9. For an FET small-signal amplifier. Use a dc meter: make some measurements as marked in a repair manual containing the circuit schematic diagram and a listing of test dc voltages. In particular. and frequency. Check the color code of resistor values to be sure that they are correct. troubleshooting a circuit is a combination of knowing the theory and having experience using meters and an oscilloscope to check the operation of the circuit. one could go about troubleshooting a circuit by performing a number of basic steps: 1. Possible Symptoms and Actions If there is no output ac voltage: 1. 2. Be sure that all ground connections are made common. If the problem is identified at a particular stage. 3. observe that the signal is present for the full signal cycle. When building and testing a FET amplifier circuit in the laboratory: 1. if there is any input ac signal at the gate terminal. the listing will provide some insight as to what expected levels should be and which path will probably generate the desired equations.15 PSpice Windows 439 . measure the resistor value as components used repeatedly may get overheated when used incorrectly. 4. 2.15 PSPICE WINDOWS JFET Fixed-Bias Configuration The first JFET configuration to be analyzed using PSpice Windows is the fixed-bias 4 V and IDSS configuration of Fig. Check that all dc voltages are present at the component terminals. so at the very least. 3. as well as any unusual waveform “glitches” that may be present. and repairing many different circuits. The format chosen was designed to permit a duplication of the entire table on the front and back of one 8 1 by 2 11 inch page.14 TROUBLESHOOTING As mentioned before. Measure the ac input signal to be sure the expected value is provided to the circuit.

440 Chapter 9 FET Small-Signal Analysis . The AC ANALYSIS at the end of the listing reveals that the voltage at the source (node 2) is 10 mV as set. and the ac voltage will be determined at four different points for comparison and review. VTO is 4 V and BETA is 625E-6 as entered.5 V. The choice of 0.2 mS. The Schematics Netlist reveals the nodes assigned to each parameter and defines the nodes for which the ac voltage is to be printed.46. but the voltage at the other end of the capacitor is 3 V less due to the impedance of the capacitor at 10 kHz—certainly a drop to be ignored.5 V. Vto must also be changed to 4 V.125 mS confirming our analysis. The constant Beta is determined by Beta IDSS Vp 2 10 mA 42 0. The output of 6. revealing that the larger the capacitor. The J2N3819 n-channel JFET from the EVAL. 9.gm but is essentially an open-circuit as a load. The OPERATING POINT INFORMATION reveals that ID is 4 mA and gm is 3. note that Vi is set at 10 mV at a frequency of 10kHz from node 2 to 0. The SMALLSIGNAL BIAS SOLUTION reveals that the voltage at both ends of RG is 1. In this case.625 mA/V2 and inserted as a Model Parameter using the sequence Edit-Model-Edit Instance Model (Text). The remaining elements of the network are set as described for the transistor in Chapter 8. Calculating the value of gm from: VGSQ 2IDSS gm 1 VP VP 2 (10 mA) ( 1.45 Fixed-bias JFET configuration with an ac source.slb library will be used. Figure 9.75 mV reflects a gain of 6. The voltages before and after the capacitor on the output side are exactly the same (to three places).5 V) 1 4V ( 4 V) 3. In the list of Junction FET MODEL PARAMETERS.275E-2 62.275. leavresulting in VGS ing a drop of 8 V across RD. An analysis of the network will result in the printout of Fig. the closer the characteristics to a short circuit. The voltage from drain to source (ground) is 12 V. 1.02 F for this frequency was obviously a good one.

45. 9.46 Output file for the network of Figure 9.15 PSpice Windows 441 .gm Figure 9.

68 V and 14. 9. The SMALL-SIGNAL BIAS SOLUTION reveals that VGS 1.63 mV at an angle of 180°.slb library as G.48 obtained. Recall that for the transistor. The Analysis is run and the results of Fig.94 mS compared to a hand-calculated level of 2. we need the voltage controlled current source (VCCS) found in the ANALOG.90 mS.7114 V and VD 14.49 V. The results for JFETs are a lot closer than those obtained for transistors when we used the provided elements because of the special feature of having essentially infinite input impedance so that the gate current is zero ampere.3 mV at an angle of 179. The nodes are identified in the Schematics Netlist and the parameters in the Junction FET MODEL PARAMETERS. Figure 9. Figure 9. When selected. the Description reads Voltage-controlled current source.3 mA and that gm is 2. 9. 442 Chapter 9 FET Small-Signal Analysis .25E-4.47 Self-bias configuration with an ac source.47 following substitution of a VCCS for the JFET in the ac domain.36 mA compared to a hand-calculated level of 3. resulting in a Vto of 4 and a Beta of 6. When placed on the schematic. VBE is a function of the operating conditions. The AC ANALYSIS provides an output level of 13.228 V—results that are very close to a hand-written solution of 1.gm JFET Self-Bias Configuration The self-bias configuration of Fig. which compares well with a handcalculated level of 13. We will now investigate the self-bias configuration using the approximate model as done for the transistor and see if there is an improvement in the results (compared to the hand-calculated levels).47 will be analyzed using the J2N3819 JFET from the library and then using an approximate equivalent circuit. it will appear as shown in Fig. The sensing voltage is between the plus and minus sign.49 Network in Figure 9. VP 4 V and IDSS 10 mA. It will be interesting to see if there are any major differences in solution.49. while the controlled current is between the other two external terminals. 9. In this case. The OPERATING POINT INFORMATION reveals that ID is 3. Again.9°.

15 PSpice Windows 443 .gm Figure 9. 9.47.48 Output file for the network of Figure 9.

49 is only valid for the ac gain since the only parameter defined is the ac transconductance factor. since we want the dc levels to be displayed. The result of an analysis is a gain of 13.8 mV. Choose Plot-Add Plot-Trace-Add-V(Vi:+). disable AC Sweep. return to Setup under Analysis. the dc levels are displayed and a plot of the output and input voltages will be obtained on the same screen. and the output waveform of Fig.18 V compared to the calculated level of 10.823 V 3. and under AC ANALYSIS that the output ac voltage is 125. Each must be saved and then the display changed to print the magnitude of the ac voltage and the applied frequency.50 JFET voltage-divider configuration with an ac source. choose V(J1:d). In addition.64 V. Then. Therefore. For the ac solution.5. the option Do not auto-run Probe was chosen. but if we examine the SMALL-SIGNAL BIAS SOLUTION. comparing very well with the 1.2 mS.8 V calculated in Example 6. After setting up the network. Finally. The No-Print Delay will be 0s and the Step Ceiling 2 s. and VDS is 10. 9.28. Then.62—almost an exact match with the handwritten gain. the period is 200 s. AC Sweep was chosen and the frequency of 5 kHz entered.2 mS)(2. Under Analysis-Probe Setup. and enable Transient. This approach is certainly valid for an ac analysis. comparing very well with the hand-calculated value of 2. click the Trace icon. with Vi at 24 mV and a frequency of 5 kHz. and both wave444 Chapter 9 FET Small-Signal Analysis . The ac waveform for the output can be obtained by first applying the sequence Analysis-Probe SetupAutomatically run Probe after simulation.50. and double-click Transient to obtain the Transient dialog box.812 V. A Print Step to 2 s would then give us 100 plot points for each cycle. we find that the results are meaningless.50 reveal that VGS is 1. Double-clicking on the schematic symbol will result in a PartName: G dialog box.8 mV/24 mV 5. the source Vi must be set to the indicated parameters by double-clicking on the source and then sequentially double-clicking on each parameter and typing in the correct values.635 V 1. the equivalent appearing in Fig. we can choose Examine Output under Analysis and find under OPERATING POINT INFORMATION that gm is 2. in which the GAIN(gm) can be set to the hand-calculated level of 2.24 V. Note that the parameters chosen are different from those employed in earlier examples. The resulting dc levels of Fig. BETA is of course calculated from IDSS/ VP 2.gm Figure 9. the JFET parameters were printed on the screen using the ABC icon.22 mS. VD is 10.51 will appear. 9.545 V compared to 6. 9. For the frequency of 5 kHz.635 V 6. and Enable Voltage Display is enabled. The hand-calculated level is gmRD (2.24. resulting in a gain of 125. 9.18 V 3. and under Setup.90 mS. JFET Voltage-Divider Configuration The last network to be analyzed in this PSpice Windows presentation is the voltagedivider configuration of Fig. The Final Time will be 5 200 s 1 ms to show five cycles. In this example.4 k ) 5. the Display Results on Schematic option is chosen under Analysis.

Figure 9. 7. and a horizontal line will appear at the dc level of the output voltage at 10. Click the Toggle cursor icon. Determine the value of gm for a JFET (IDSS yfs 4. and device ideal voltage gain. § 9. Shift SEL to the bottom waveform by simply bringing the pointer to the left of the lower waveform and left-clicking the mouse once. Av(FET). Calculate gm0 for a JFET having device parameters IDSS 2. what is the device cur3 V) at a bias point of VGS 2. 9.496 mV. and the intersection will automatically go to the peak value of the waveform (A1 in the dialog box).5 mS. Calculate the value of gm for a JFET (IDSS 1 V. For a JFET having specified values of yfs 4. What is the value of gm at that 5 V) when biased at VGSQ 25 S VP/4. 10 mS and IDSS PROBLEMS 3. A JFET (IDSS bias point? 6 mS at VGSQ 10 mA. Choose the Cursor Peak icon. (b) rd. comparing well with the printed value in the output file.5 mS and yos 25 S. A left click of the mouse and an intersecting set of lines will appear.2 FET Small-Signal Model 1. 5. For a JFET having device parameters gm0 rent at VGS 0 V? 4.5 V. what is the value of IDSS if VP 5 V) is biased at ID 8 mA. Problems 445 . Determine the pinch-off voltage of a JFET with gm0 3. Zo(FET).gm forms will appear as shown.184 V. For a JFET having gm 6. The difference is simply due to the number of points chosen for the plot. 12 mA.51 The ac drain and gate voltage for the voltage-divider JFET configuration of Figure 9. The difference appearing in the dialog box is 125. VP yos IDSS/4.50. VP 5 mS and VP 12 mA. VP 15 mA and VP 5 V. determine the device output impedance. determine: (a) gm.5 V? 1 V. an increased number of plot points would have brought the two levels closer together. 8. A specification sheet provides the following data (at a listed drain–source current) At the listed drain–source current.

what is the value of gm? 100 k has an ideal voltage gain of Av(FET) 11.gm 10. (e) What is the value of gm at VGSQ 2.5 V using Eq.5 V graphically. yos(maximum) 10 S): 14.52 JFET transfer characteristic for Problem 11 12.53 JFET drain characteristic for Problem 12 13.5 V. 446 Chapter 9 FET Small-Signal Analysis .6)? Compare with the solution to part (b). Using the drain characteristic of Fig. If a JFET having a specified value of rd 200. (a) Plot gm vs. VGS for an n-channel JFET with IDSS 8 mA and VP (b) Plot gm vs. ID for the same n-channel JFET as part (a). (9.5 V using Eq. 9. (9. Using the transfer characteristic of Fig.6)? Compare with the solution to part (d). ID (mA) 10 9 8 7 6 5 4 3 2 1 −5 −4 −3 −2 −1 0 VGS (V) Figure 9. (d) Graphically determine gm at VGS 2. (c) What is the value of gm at VGSQ 1.52: (a) What is the value of gm0? (b) Determine gm at VGS 1. 9.53: (a) What is the value of rd for VGS 0 V? (b) What is the value of gm0 at VDS 10 V? ID (mA) 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 −3 V 10 11 12 13 14 15 16 17 18 19 20 −4 V VDS (V −2 V −1 V VGS = 0 V Figure 9. 6 V. For a 2N4220 n-channel JFET (yfs(minimum) (a) What is the value of gm? (b) What is the value of rd? 750 S.

18. 22. Determine Zi.56 Self-bias configuration for Problems 20 and 47 Problems 447 .55 Problems 19. +12 V 20 V 2 kΩ Vo Vo Vi Zi 1 MΩ Zo 3. VP 4 V.54 Fixed-bias amplifier for Problems 17 and 18 § 9. 4 V. 9. Repeat Problem 19 if yos is 10 S.3 kΩ Vi Zo 10 MΩ 1. Sketch the ac equivalent model for a JFET if yfs 16. Compare the results to those of Problem 19.55 if yfs 20. 5. 3000 S and yos 6 mA. VP 50 s. 10 mA.6 mS and yos 10 mA. Determine Zi. and rd 6 V. Sketch the ac equivalent model for a JFET if IDSS yos 25 S. Zo. 6 V.F capacitor is removed and the parameters of the network are the same as in Problem 19. Determine Zi. 9.gm 15. and Av for the network of Fig. 9.54 if IDSS 40 S.8 kΩ Vo Vi Zo 1 MΩ Zi 1. 21. VP 15 S.4 JFET Self-Bias Configuration 19. Zo and Av for the network of Fig. and § 9. Zo. VP 12 mA.55 if the 20. Zo. and Av for the network of Fig. and yos 21. 9. Determine Zi.1 kΩ 20 µF Zi Figure 9. and Av for the network of Fig. Zo.56 if IDSS 40 S.5 V – + Figure 9. and yos +18 V 1. Compare results with those of Problem 19. Determine Zi. 9. and 46 Figure 9.3 JFET Fixed-Bias Configuration 17.54 if IDSS 40 k . VGSQ 2 V. and Av for the network of Fig.

58. Zo. and compare results. 9. 9.59 Problem 29 § 9. 25. Determine Zi.59. 448 Chapter 9 FET Small-Signal Analysis . 29.3 kΩ IDSS = 6 mA VP = −6 V rd = 30 kΩ Zi 10 MΩ 3.1 mV. 20 V +20 V IDSS = 9 mA VP = −4.58 Problems 27 and 28 Figure 9. Zo. Repeat Problem 24 if rd 20 k 20 k and compare results. Repeat Problem 30 if rd 25 k . 9. 20 mV and the capacitor CS is § 9.57 if Vi removed. 9. 9.57 Problems 23–26 and 48 24.gm § 9. Zo.5 JFET Voltage-Divider Configuration 23. Determine Zi. and Vo for the network of Fig.57 if Vi 20 mV. 33 k . and Av for the network of Fig. 32. +20 V 2 kΩ 82 MΩ Vo Vi Zi 11 MΩ RS 610 Ω CS Zo IDSS = 12 mA VP = − 3 V rd = 100 kΩ Figure 9. 9. Zo.5 V rd = 40 kΩ Zi 10 MΩ 2.60 if Vi 31. Determine Zi. and Av for the network of Fig. and Vo for the network of Fig. Zo. Determine Zi. and Vo for the network of Fig. Repeat Problem 27 if rd 20 k . and Av for the network of Fig. Determine Zi. 28.2 kΩ Vo Zo 3.61 if rd 0.7 JFET Common-Gate Configuration 30. Determine Zi. Zo.3 kΩ Vo Zo Vi Vi Figure 9. Repeat Problem 23 if rd 26.6 JFET Source-Follower Configuration 27.

and 49 Figure 9.8 Depletion-Type MOSFETs 33.62 Problem 33 34.8 kΩ Vo IDSS = 12 mA VP = − 3.8 V rd = 40 kΩ Vo Zo Zi 1 kΩ 11 MΩ +22 V 3.5 mA VP = − 4 V Figure 9.60 Problems 30. and 50 Problems 449 .gm +15 V 91 MΩ Vi Vi Zi 1. Determine Vo for the network of Fig.62 if yos 20 S.2 kΩ Vo Zo IDSS = 7. 9.3 kΩ 2. 9.1 kΩ Vo IDSS = 8 mA VP = − 3 V 10 MΩ + Vi = 2 mV – Figure 9. +22 V 1.61 Problem 32 § 9.63 Problems 34. +16 V 1. 35. and Av for the network of Fig. Determine Zi. 31.5 V Zo 10 MΩ 100 Ω Vi Zi Figure 9.63 if rd 60 k . Zo.5 kΩ IDSS = 8 mA VP = − 2.

67 if Vi 42.10 E-MOSFET Drain-Feedback Configuration 38.3 10 3.3 kΩ IDSS = 12 mA VP = −3 V rd = 45 kΩ Vo 15 MΩ 10 MΩ 1. 3 V and it is biased at VGSQ 0.1 kΩ Zo Vi Figure 9. +18 V +20 V 6. 9.65 Problem 37 § 9. and ID(on) 4 mA.3 × 10−3 yos = 30 µS Vi Figure 9. and Av for the network of Fig. Zo. 8 V.8 kΩ 91 MΩ yos = 35 µS yfs = 6000 µS Vo 91 MΩ Vi Zi 3. Repeat Problem 39 if k drops to 0. VGS(Th) 4 V. 40. 20 mV. 36.67 if Vi VGS(on) 7 V and yos 20 S. +20 V 10 kΩ 22 MΩ Vo VGS(Th) = 3.67 Problems 41 and 42 450 Chapter 9 FET Small-Signal Analysis .gm 35.64 if Vi 37. Determine Zi. and Av for the amplifier of Fig.66 if k +16 V 2.2 10 3.5 V k = 0. with 41. Determine Vo for the network of Fig.64 Problem 36 Figure 9. 9. Determine Vo for the network of Fig. 4 mV. Compare results. Determine Zi. Determine Vo for the network of Fig. 4 mV. Assume k 39. 9. Zo.65.66 Problems 39. Determine gm for a MOSFET if VGS(Th) 0. and 51 40.3 10 3.2 kΩ Vo 10 MΩ Vi Zi Zo VGS(Th) = 3 V rd = 100 kΩ Figure 9. Repeat Problem 34 if rd 25 k . 9. 9.

The device should be biased at VGSQ 1 VP. determine the voltage gain for the network of Fig. 48. Determine the output voltage for the network of Fig.8 mV and rd 40 k .5 V yos = 25 µS Vi 10 MΩ RS RD Vo IDSS = 12 mA VP = − 3 V rd = 40 kΩ Figure 9. 49. determine the voltage gain for the network of Fig. 30V 3.56. 50.69 Problem 44 Figure 9. determine the voltage gain for the network of Fig. Using PSpice Windows.57.12 Designing FET Amplifier Networks 44. Using PSpice Windows. 9.69 to have a gain of 8. Using PSpice Windows. Using PSpice Windows.gm § 9.60.66. 45. 51.11 E-MOSFET Voltage-Divider Configuration 43.68 if Vi 0. Design the fixed-bias network of Fig.70 Problem 45 § 9.68 Problem 43 § 9. Design the self-bias network of Fig. Using PSpice Windows. 47. determine the voltage gain for the network of Fig.4 × 10 −3 Vo + Vi 10 MΩ 1. 9.55. Problems 451 . determine the voltage gain for the network of Fig. 9. determine the voltage gain for the network of Fig. 9.2 kΩ – – Figure 9. 3 +VDD (+22 V) +VDD (+20 V) RD Vo Vi 10 MΩ IDSS = 8 mA VP = − 2. 9. 9. Using PSpice Windows.13 PSpice Windows 46.63. 9.3 kΩ 40 MΩ + VGS(Th) = 3 V k = 0.70 to have a gain of 10. 9. 9.

the important parameters of a two-port system have been identified.1. sophisticated designs that would be quite bulky if built with discrete (individual) components. 10. many of the results obtained in the last two chapters are utilized in the analysis to follow. 10.Rs /RL CHAPTER 10 Systems Approach— Effects of Rs and RL 10. we develop the systems approach in a slow deliberate manner that will include numerous examples to make each salient point. The emphasis in previous chapters on determining the two-port parameters for various configurations will be quite helpful in the analysis to follow. The techniques introduced will be used in the remaining chapters and broadened as the need arises. The small IC packages contain stable.1) Thévenin Figure 10. Fundamentally.1 INTRODUCTION In recent years. In the next few sections. The content of this chapter is a first step in developing some familiarity with this approach. For the moment recogVo nize that the impedance levels and the gains of Fig. 452 . reliable. The systems approach is not a difficult one to apply once the basic definitions of the various parameters are correctly understood and the manner in which they are utilized is clearly demonstrated.1 Two-port system. self-testing.2 TWO-PORT SYSTEMS Ii Io + Zi Vi AυNL AiNL Zo – The description to follow can be applied to any two-port system—not only those containing BJTs and FETs—although the emphasis in this chapter is on these active devices. The impact of these + important elements is considered in detail in a later section. In fact. a first plateau in the understanding of system analysis will be accomplished. – If we take a “Thévenin look” at the output terminals we find with Vi set to zero that ZTh Zo Ro (10. The trend to packaged systems is quite understandable when you consider the enormous advances in the design and manufacturing of integrated circuits (ICs). If the content of this chapter is clearly and correctly understood. Note in particular the absence of a load and a source resistance.1 are determined for no-load (absence of RL) and no-source resistance (Rs) conditions. this approach concentrates on the terminal characteristics of a package and treats each as a building block in the formation of the total package. the introduction of a wide variety of packaged networks and systems has generated an increasing interest in the systems approach to design and analysis. In Fig. 10.

1).2 Two-Port Systems 453 . Figure 10.2. The result is an output impedance equal to Ro as originally defined. 10. sketch the two-port equivalent of Fig. and the voltage drop across the impedance Ro will be 0 V. where RL is the defined load for the analysis of interest.2.2) Note the use of the additional subscript notation “NL” to identify a no-load voltage gain. 10.2 by finding Zo and AvNL in the usual manner. 10. Vi is set to zero. This is not to say that the quantity is seldom calculated. Substituting the Thévenin equivalent circuit between the output terminals will result in the output configuration of Fig. Before looking at an example. 10. To find Zo. Since our present interest is in BJT and FET amplifiers.3 Example 10. For the input circuit the parameters Vi and Ii are related by Zi Ri. permitting the use of Ri to represent the input circuit. AvNL and so that Vo ETh Vo Vi AvNLVi AvNLVi (10.1 Figure 10. However.3 (Example 8.2 and in fact is seldom part of the two-port system analysis of active devices. The absence of a load will result in Io 0. but it is most frequently calculated from the expression Ai Av(Zi/RL). The open-circuit output voltage is therefore AvNLVi. both Zo and Zi can be represented by resistive elements. For the fixed-bias transistor network of Fig. take note of the fact that Ai does not appear in the two-port model of Fig.2 Substituting the internal elements for the two-port system of Fig. Before continuing let us check the results of Fig.1. 10. as it should be. 10. 10. permitting a short-circuit equivalent for the source. resulting in AvNLVi 0.Rs /RL ETh is the open-circuit voltage between the output terminals identified as Vo.1. EXAMPLE 10.

1. revealing an opposite polarity for the controlled source than that indicated in the figure. 10. The only change is the general appearance of the model. 10. The model can be applied to any current.11 Using the information above.5. 10. Figure 10. 10.1. Zi Zo AvNL 1.069 kΩ + Ro = 3 kΩ −280. as defined earlier. the gain of the system without an applied load. Note in particular the negative sign associated with the controlled voltage source. RC 3 k was included in defining the no-load voltage gain. Ri and Ro are the input and output impedances of the amplifier as defined by the configuration. A second format for Fig. particularly popular with op-amps (operational amplifiers).Rs /RL Solution From Example 8. all the parameters of the model are unaffected by changing loads or 454 Chapter 10 Systems Approach—Effects of Rs and RL . the effect of an applied load is investigated using the two-port model of Fig. Although this need not be the case (RC could be defined as the load resistor in Chapter 8). AvNL is. the two-port equivalent of Fig.or voltage-controlled amplifier.11Vi + Vo – – – Figure 10. In Example 10.4 can be drawn. Ideally.1.2. 10. + Vi Ri 1. appears in Fig. the analysis of this chapter will assume that all biasing resistors are part of the no-load gain and that a loaded system requires an additional load RL connected to the output terminals.069 k 3k 280.3 EFFECT OF A LOAD IMPEDANCE (RL) In this section.4 Two-port equivalent for the parameters specified in Example 10.5 Operational amplifier (op-amp) notation. It also reveals a 180° phase-shift between the input and output voltages.2.

6.2 will result in the configuration of Fig. (10.3) through (10. 10. In any case. Ri. 10.3 Effect of a Load Impedance (RL) 455 . the current gain can be obtained from the voltage gain and impedance parameters Zi and RL. Although the level of Ri may change with the configuration. 10. 10.6 Applying a load to the two-port system of Fig. 10.6. The next example will demonstrate the usefulness and validity of Eqs. Note also that the formula for the voltage gain does not include the input impedance or current gain. Applying a load to the two-port system of Fig. Since the ratio RL/(RL Ro) will always be less than 1: The loaded voltage gain of an amplifier is always less than the no-load level. for some transistor amplifier configurations. once AvNL.6). the applied voltage and input current will always be related by Ii Vi Zi Vi Ri (10. while for others Ro can be sensitive to the source resistance.4) Defining the output current as the current through the load will result in Io Vo RL (10. Applying the voltage-divider rule to the output circuit will result in Vo and Av RLAvNL Vi RL Ro Vo Vi RL RL Ro AvNL (10.Rs /RL source resistances (as normally encountered for op-amps to be described in Chapter 14).5) with the minus sign occurring due to the defined direction for Io in Fig. In general. The current gain is then determined by Ai and Ai Av Zi RL (10. However.2.6) Io Ii Vo /RL Vi/Zi Vo Zi Vi RL for the unloaded situation.3) Figure 10. Ri can be quite sensitive to the applied load. the equations about to be derived can be employed. and Ro are defined for a particular configuration. therefore.

2 k 57.5) 1.11 RL (with re 10. (10.Rs /RL EXAMPLE 10.269 k 456 Chapter 10 Systems Approach—Effects of Rs and RL . 10.071 k 2.3) yields Av A Ro vNL 2.7. 10. 12 V 3 kΩ Io RC RB Ii CC 470 kΩ + β = 100 Zo RL 2. Note in particular that the applied load is in parallel with the collector resistor RC defining a net parallel resistance RL The output voltage Vo IBRL RC RL 3k 2.71 and 100) Applying Eq. Zi is unaffected by the applied load and Ai ( 118.2 k 3k (0.5 RL Zi RL For the current gain.423)( 280.11) 2. Solution (a) Recall from Example 10.2 k 1.2 In Fig.3).2 kΩ Vo + Vi Zi – – Figure 10. (a) Determine the voltage and current gain using the two-port systems approach defined by the model of Fig. a load has been applied to the fixed-bias transistor amplifier of Example 10.071 k 3k 280. 10.8.11) 118.7 Example 10.2.2 k ( 280.69 (b) Substituting the re model will result in the network of Fig. Ai Av In this case.1 that Zi Zo Av NL 1.1 (Fig.4. 10. (b) Determine the voltage and current gain using the re model and compare results.

3 Effect of a Load Impedance (RL) 457 . The advantages of the systems approach are similar to those associated with applying Thévenin’s theorem.5 as obtained above. by the current-divider rule. the effect of changing the load can be determined directly from Eq. and as with any trend.9977Ii Ii 0.2 demonstrated two techniques to solve the same problem. Although any network can be solved using the re model approach. Ib and Io (470 k )Ii 470 k 1. (10.5769 Ib Ii 0.7) so that Substituting values gives Av Av 1.5769 Ib so that Ai Io Ii 0.71 118.7 were presented for analysis without the unloaded parameters. Of course.071 k 3 k ( Ib) 3k 2. However. 10. the user must be aware of how to utilize the given data.8 Substituting the re model in the ac equivalent network of Fig.6).2 kΩ Vo β re β Ib RC 3 kΩ – R' L – Figure 10.Rs /RL Ii Ib Zi RB 470 kΩ Zo Io + Vi + RL 2. the advantage of the systems approach is that once the two-port parameters of a system are known. it would be a toss-up as to which approach would yield the desired results in the most direct. For the current gain. When you purchase a “system” the two-port parameters are provided.69 Example 10. efficient manner. 57. No need to go back to the ac equivalent model and analyze the entire network. 10.269 k 10. if the network of Fig. 10. with and Ib Vo Vo Vi Vi re Vi R re L RL re RC RL re (10.3).5769 Ii Ii 0. They permit concentrating on the effects of the load without having to re-examine the entire network. keep in mind that the “package” approach is the developing trend.7.2 k 0.5769(100) as obtained using Eq. (10.

9a.9 Demonstrating the differences between the dc and ac load lines. 10. 10. the application of a relatively small sinusoidal signal to the base of the transistor could cause the base current to swing from a level of IB2 to IB4 as shown in Fig.9b. 10. Note of particular importance that the ac and dc load lines pass through the same Q-point—a condition that must be satisfied to ensure a common solution for the network under dc and/or ac conditions. For the unloaded situation.9b. the coupling capacitors are replaced by a short-circuit equivalence that will place the load and collector resistors in a parallel arrangement defined by RL RC RL The effect on the load line is shown in Fig. 10. For the ac analysis. the dc load line was drawn on the output characteristics as shown in Fig. however. t (b) 458 Chapter 10 Systems Approach—Effects of Rs and RL .Rs /RL The AC Load Line For a system such as appearing in Fig. 10. The application of the same signal for a loaded situation would result in the same swing in the IB level. The resulting output voltage vce would then have the swing appearing in the same figure. of the steeper slope of the ac load line is a smaller output voltage VCEQ RL' ac load line IB 6 ICQ + IC et oV i Du IB t 5 VCEQ VCC RC RB CC iB R' L VCC RC IB 4 0 IB 3 + RL V o ICQ Q-point IB dc load line + Vi 2 CC Ib IB – (a) – 0 0 VCEQ ICQ R'L vce VCC 1 VCE VCEQ + ICQ R' L 0 vce Figure 10. The result.9b with the levels to determine the new axes intersections. The load resistance did not contribute to the dc load line since it was isolated from the biasing network by the coupling capacitor (CC).9b. as shown in Fig.

Figure 10. That is. 10. the smaller the level of RL. The fraction of the applied signal reaching the input terminals of the amplifier of Fig.10. the steeper the slope and the smaller the ac voltage gain. a source with an internal resistance has been applied to the basic two-port system. For the two-port system of Fig. the larger the internal resistance of a signal source the less the overall gain of the system.9) Vo Vs Rs NL 10. the lower the level of ac voltage gain. it should be fairly clear that: For a particular design. the less the voltage at the input terminals of the amplifier. Recall Eq.4 Effect of the Source Impedance (Rs) 459 . Vo and so that and Vi Vo Avs Av Vi NL RiVs Ri Rs Av Ri NL Ri Ri Rs Ri Vs Av (10. Since RL is smaller for reduced levels of RL.110) for the complete hybrid equivalent model.10. 10. In Fig. 10.8) clearly shows that the larger the magnitude of Rs. (8. The definitions of Zi and AvNL are such that: The parameters Zi and AvNL of a two-port system are unaffected by the internal resistance of the applied source. 10. In general.10 Including the effects of the source resistance Rs. Vi RiVs Ri Rs (10. It should be obvious from the intersection of the ac load line on the vertical axis that the smaller the level of RL.8) Equation (10.Rs /RL swing (vce) and a drop in the gain of the system as demonstrated in the numerical analysis above.4 EFFECT OF THE SOURCE IMPEDANCE (RS) Our attention will now turn to the input side of the two-port system and the effect of an internal source resistance on the gain of an amplifier.10 is determined by the voltage-divider rule. However: The output impedance may be affected by the magnitude of Rs. therefore: For a particular amplifier.

12 Substituting the two-port equivalent network for the fixed-bias transistor amplifier of Fig.071 k 0.10) EXAMPLE 10.12. (10.1 (Fig. a source with an internal resistance has been applied to the fixed-bias transistor amplifier of Example 10.9): Avs Vo Vs Ri Ri Rs AvNL 1.11Vi + Vo – – – Figure 10. 10.11. Rs Ro + Vs 0.3.11 Example 10. Eq.6817Vs or 68. 10.11) 190.3). The input current is also altered by the presence of a source resistance as follows: NL Ii Vs Rs Ri (10.11.8% was lost across the internal resistance of the source.5 kΩ + Vi Ri 1.5 k 0. Solution (a) The two-port equivalent for the network appears in Fig.071 k 0.071 k 1.2% of the available signal reached the amplifier and 31.6817)( 280. 10.5 k ( 280. (a) Determine the voltage gain Avs Vo /Vs.8): Vi RiVs Ri Rs (1. Using Eq.96 Eq.3 In Fig.071 kΩ + – 3 kΩ AυNLVi −280. if Rs 0 (ideal voltage source).Rs /RL The result clearly supports the statement above regarding the reduction in gain with increase in Rs. (10. 10. Figure 10. Avs Av . 460 Chapter 10 Systems Approach—Effects of Rs and RL .9). What percent of the applied signal appears at the input terminals of the amplifier? (b) Determine the voltage gain Avs Vo /Vs using the re model.11) (0. which is the maximum possible value. (10.071 k )Vs 1.

13 Substituting the re equivalent circuit for the fixed-bias transistor amplifier of Fig.3 that the same results were obtained with the systems approach and using the re model. but Rs remains a quantity associated only with the applied source. let us assume that Zi and Zo are unaffected by RL and Rs.14. Note again in Example 10. Throughout the analysis above. they should be applied. Of course. and Zo have been specified.11. 10. In Fig. The next natural question is how the presence of both factors in the same network will affect the total gain. If not.5 COMBINED EFFECT OF Rs AND RL The effects of Rs and RL have now been demonstrated on an individual basis. the resistance “seen” by the source is now Rs Zi. 10.5 Combined Effect of Rs and RL 461 . 10. Ii Rs 500 Ω RB 470 kΩ β re 1.571 k Vs 1.96 as above.571 k (100)(3 k ) 1. a source with an internal resistance Rs and a load RL have been applied to a two-port system for which the parameters Zi.071 kΩ Ib Ii Vs Rs re 3k Vs 1. 10. Solving for Vo gives Vo with and so that Zi (100Ib)3 k re and Ib Vo Avs 100 Vo Vs 190. Av .57 k + Vs + β Ib 100 Ib 3 kΩ Vo – – Figure 10. NL Is Ii Rs Io + Vs + Vi Ri + – Ro AυNLVi RL + Vo – – – Figure 10.13. Certainly. the approach to the solution is simply a matter of preference. respectively. 10. if the two-port parameters are available.Rs /RL (b) Substituting the re model will result in the equivalent circuit of Fig. For the moment.14 Considering the effects of Rs and RL on the gain of an amplifier. note that Rs was not included in the definition of Zi for the two-port system.

63 would still be respectable. the less the overall gain of an amplifier.9)(0. Ai or using Is Vs /(Rs Ri). For instance.9-level factors. the following mathematical steps can be performed: Avs Vo Vs Vo Vi Vi Vs (10. so Eqs. which is still quite high. which is close to the lower factor. In fact: The larger the source resistance and/or smaller the load resistance.13) and substituting Eqs. The two reduction factors of Eq.14) clearly reveals that both the source and the load resistance will reduce the overall gain of the system. Equation (10. (10. Ii Is.18.14) form a product that has to be carefully considered in any design procedure. therefore.2) 0. The effect of the excellent 0.15) and (10.8): Vi or and at the output side. for good overall gain the effect of both Rs and RL must be evaluated individually and as a product.9 and the second 0. the net result would be (0. the product of the two results in an overall reduction factor equal to (0.16) will generate the same result. if the first factor is 0.81. (10.12) will result in Avs and Avs Since Ii Vi /Ri.12) Vo /Vs.15) Vo Vs Ri Ri Rs RL RL Ro Av (10.9)(0.11) Vi Vs Ri RLAV RL Ro NL (10.14) RLAv Ri RL Ro Ri Rs NL NL However.9 level was completely wiped out by the significantly lower second multiplier. 462 Chapter 10 Systems Approach—Effects of Rs and RL . (10. (10. the net result of 0.9) 0.9 and the second factor is 0.16) Av Ri RL (10.2. It is not sufficient to ensure that Rs is relatively small if the impact of the magnitude of RL is ignored. as before. In general.11) and (10.14). Ais Avs Rs RL Ri (10. Vo or For the total gain Avs Av Vo Vi RLAv Vi RL Ro NL RiVs Ri Rs Ri Rs (10. Even if the first were 0. in Eq. If both were 0.7. (10.Rs /RL At the input side we find Eq.

(c) Ai.4768)( 280. and AvNL 12 V EXAMPLE 10.11.96 1.6 BJT CE NETWORKS The fixed-bias configuration has been employed throughout the analysis of the early sections of this chapter to clearly show the effects of Rs and RL. + – – Figure 10.11) Vo RLAvNL 4. The two-port parameters for the fixed-bias configuration are Zi 1.98) 4.4 3 kΩ 470 kΩ Rs 10 µF Vo 20 µF β = 100 Zo Vi Zi RL 4.6 BJT CE Networks 463 .6104)( 280.3 kΩ Solution (a) Eq.071 k 4. determine: (a) Avs. In this section.Rs /RL For the single-stage amplifier of Fig. (b) Av Vo /Vi.11) (0. various CE configurations are examined with a load and a source resistance.7 k )( 280.071 k 0.96 Vo Vs (b) Av (c) Ai or Ais as above.3 k 4.11) 133.57) 4.7 kΩ + Vs 0.4 ( 280. 3 k .11) 10. (10. A detailed analysis will not be performed for each configuration since they follow a very similar path to that demonstrated in the last few sections. Zo 280.15 Example 10.11) 170.7812)(0. with RL 4.7 k RL 38.98 1.071 k .7 k 1.7 k 3k Vi RL Ro (0.14): Avs Ri RL A Ri Rs RL Ro v NL 1.7 k and Rs 0. 10.071 k 0.3 k Rs Ri Avs ( 133.6104)( 280.7 k RL 38. 10.57 (4.3 k .071 k Ri Av ( 170.7 k 3k (0.15.

16. Rs + Vs Zi + Vi Zo β re β Ib RC RC RL For the voltage gain Avs of Fig. AvNL RC /re and Ro Vo RL( RC /re)Vi RL RC Vo Vi RL RC Av RLRC 1 RL RC re RLRC RL RC RL RC re (10.16.17 would result. the system model with a load and source resistance will appear as shown in Fig. + Vo RL Figure 10.16 Fixed-bias configuration with Rs and RL – – – – RC. 10. (8.17 Fixed-bias configuration with the substitution of the re model. Vi and with 464 Vi Vs Avs ZiVs Zi Rs Zi Zi Vo Vs Rs Vi Vo Vs Vi Chapter 10 Systems Approach—Effects of Rs and RL – – Figure 10. Vo RL RL Ro AvNLVi Rs Ro + Vs Zi + Vi Ri β re + – RC Aυ NL Vi + Vo Zo RL Substituting Eq. In general.17) and but and Av If the re model were substituted for the transistor in the fixed-bias configuration. clearly revealing that RC and RL are in parallel. .6).Rs /RL Fixed Bias For the fixed-bias configuration examined in detail in recent sections. 10. 10. the network of Fig.

6 BJT CE Networks 465 .18 Voltage-divider bias configuration with Rs and RL.18) Since the load is connected to the collector terminal of the common-emitter configuration. Zi remains independent of the applied load and Zi RB RE (10.19.Rs /RL so that Avs Zi Zi Rs Av (10. 10. 10.23) with Avs Av (10. the load is again connected to the collector terminal and Zi remains Zi R re (R R1 R2) (10.20) Voltage-Divider Bias For the loaded voltage-divider bias configuration of Fig.25) 10. Zi and as obtained earlier. – In the small-signal ac model.24) CE Unbypassed Emitter Bias For the common-emitter unbypassed emitter-bias configuration of Fig.18. Zo re RC (10.22) RC R1 Rs Ib C1 C2 + + Vi R2 RE CE Zo RL Vo + Vs – Zi – Figure 10. RC and RL will again be in parallel and Av RC RL re Zi Zi Rs (10.19) (10.21) and for the system’s output impedance Zo VCC RC (10.

the resistance RC will again drop down in parallel with RL and Av Vo Vi Vo Vs Io Ii Zi) RC RL RE Zi Zi Av Rs Zi RL (10.29) Vi/Zi. In the smallsignal ac model of the system.Rs /RL VCC RC RB Rs Ii C2 Io + C1 + Vs + Vi Zo RE RL Vo – Zi – – Figure 10. 466 Chapter 10 Systems Approach—Effects of Rs and RL . Collector Feedback To keep with our connection of the load to the collector terminal the next configuration to be examined is the collector feedback configuration of Fig. 10.27) with Avs Av (10. For the output impedance.26) For the voltage gain.20.19 CE unbypassed emitter-bias configuration with Rs and RL. Zo RC (10.28) and but keep in mind that Ii Is Ai Vs /(Rs (10. RC and RL will again drop down in parallel and VCC RC RF Rs Ii C1 Zi C2 Io RL + Vo + Vs + Vi Zo – – – Figure 10.20 Collector feedback configuration with Rs and RL.

553 k .94.30)] is a function of RL will alter the level of Zi from the no-load value.3 k 11.32) and Zi re (10.21 Example 10.33) The fact that Av [Eq.31) Zo RC RF RF Av (10. Using the systems approach.21 has the following no-load system pa238. with re rameters: AvNL 200.37 k ) 180 k 131. 9V 2.26 k 0.6 kΩ EXAMPLE 10. and Zi 0.66 k . (b) Avs.485 k 11. The collector feedback amplifier of Fig.5. Solution (a) For the two-port system: Av RC RL re 1. if the no-load model is available.7 k 3. 10.3 with Zi re RF Av 2.7 kΩ 180 kΩ Ii Io Vo 0.3 1. (10. determine: 11. Zo RC RF 2.6 BJT CE Networks 467 .30) with The output impedance Avs Av (10.3 kΩ – – Figure 10.42 (200)(11.3 131.853 k 10.42 2. Therefore.5 + Vs + Vi β = 200 3.3 . and (a) Av.Rs /RL Av RC RL re Zi Zi Rs (10. the level of Zi must be modified as demonstrated in the next example. (c) Ai.

23.3) (132. the resistance RB is neglected because it is usually so much larger than the source resistance that a Thévenin equivVCC RB Ii Rs C1 Zi Ib + Vi C2 RE Zo Io + Vs + RL Vo – – Figure 10.853 k 0.22 with the value of Zi as controlled by RL and the voltage gain. the small-signal ac model would appear as shown in Fig. 10.853 k 0.2 Rs RL ( 77.7): Av Ii RLAvNL RL Ro (3.67) 0.3 k 10. For the input section of Fig.3 kΩ – (b) Avs Zi Zi Rs 77. Now the two-port gain equation can be applied (slight difference in Av due to approximation Ib IRF in Section 8.94) 3.66 k 2.2 Zi RL Zi Av 0.94Vi Figure 10.6 k 3. 10.Rs /RL The system approach will result in the configuration of Fig.3)(0.23 Emitter-follower configuraton with Rs and RL.853 k 0.22 The ac equivalent circuit for the network of Fig.3 k )( 238.853 k 3. – 468 Chapter 10 Systems Approach—Effects of Rs and RL .21.7 BJT EMITTER-FOLLOWER NETWORKS The input and output impedance parameters of the two-port model for the emitterfollower network are sensitive to the applied load and source resistance. 10.24.853 k ) 3.24.3 k or Ai Avs 34.66 kΩ Io 132. 10.3 k ( 132. 10.3) (c) Ai ( 132.3 + Vs 0.6 k 0.3 k 2. – – – Vo 3.6 kΩ + Vi 0.853 kΩ + + −238.67 Av 34. For the emitter-follower configuration of Fig.

10. 10. Applying Kirchhoff’s voltage law to the input circuit of Fig. + Vs e + – – ' RE Vo – alent circuit for the configuration of Fig.23 following the substitution of the re equivalent circuit.7 BJT Emitter-Follower Networks .24. 10.25 would result in simply Rs and Vs as shown in Fig.24 Emitter-follower configuration of Fig. 10. Rs β + re Ie R' E Rs β + re Io Zo RE RL + Vs + Vo + Vs + Vo – (a) – – (b) – Figure 10. The voltage gain can then be obtained directly from Fig. 10. [(Rs Drawing the network to “fit” Eq.26b. 10. In Fig. RE and the load resistance RL have been separated to permit a definition of Zo and Io. we have Ie and Using 1 Ie yields Ie (Rs / Vs re) RE (10.34) will result in the configuration of Fig. 10. 10.26a using the voltage divider rule: REVs Vo RE (Rs / re) or Avs Vo Vs RE RE (Rs / re) 469 10.34) ( 1)Ib Rs Vs re)/( Figure 10.Rs /RL b c Ib + Rs Vi Ie = (β + 1) Ib β re β Ib ' where RE = RE RL Figure 10. the effect of RB must be included. 10.26 Networks resulting from the application of Kirchhoff’s voltage law to the input circuit of Fig.24. if current levels are to be determined such as Ii in the original diagram.26a.25 Determining the Thévenin equivalent circuit for the input circuit of Fig. (10.24 will result in Vs and so that Vs Ib IbRs Ib(Rs Rs re Ib re re Vs ( ( ( 1)IbRE 1)RE) 1)RE ( re 1)] 1)Vs ( 1)RE RE 0 0 Rs + Vs RB – Thévenin Establishing Ie.23. Of course.

560 kΩ Ii 0. 10.21 k 1.37): Zi RB (re 560 k 560 k 75. the gain equation is AvNL while for loaded conditions.3 k 2. Zb and or Zi Zi (re R E) RB Zb RE RL) (10.56 kΩ C1 + Vi β = 65 C2 Vo Io 3. 15 V (d) Ai Io /Ii.993 with re 21.2 kΩ + Vs – Figure 10.32 k 65(21.54 k 470 Chapter 10 RE RL) 87.38) RE RE re EXAMPLE 10.36) For the input impedance. respectively.74 and (a) The new values of Zi and Zo as determined by the load and Rs. Zo 21.54 k . and AvNL 65. (b) Av using the systems approach. (c) Avs using the systems approach.Rs /RL and Setting Vs Avs Vo Vs RE RL RE RL Rs/ re (10.46 k versus 157. Systems Approach—Effects of Rs and RL .35) 0 and solving for Zo will result in Zo RE Rs re (10.27 Example 10.6 For the loaded emitter-follower configuration of Fig.6.74 3. (10.6 .2 k ) (no-load).3 kΩ 2. determine: 0. Av Vo Vi RE RL RE RL re (10.37) RB (re For no-load conditions. Zi – Zo Solution Eq.27 with a source resistance and the no-load two-port parameters of Zi 157.

98)(0. 10.8 BJT CB Networks 471 .08 Vo Vi 0.2 k )(0. The isolation that exists between input and output circuits also maintains Zo at a fixed level even though the level of Rs may change.74 (2.Rs /RL Zo RE 3.56 k Avs Vo Vs Vo Vi Vi Vs 0.3 k 30.46 k 2. (b) Substituting the two-port equivalent network will result in the small-signal ac equivalent network of Fig.2 k (0.98) 33.29. (c) Vi so that (d) Ai ZiVs Zi Rs (75.993) 0.98 30.98Vi with Av Ii Rs re 0.36 21.993Vs (0.8 BJT CB NETWORKS A common-base amplifier with an applied load and source resistance appear in Fig.28 Small-signal ac equivalent circuit for the network of Fig. Vo RLAvNLVi RL Ro 0.3 k 3.61 10.993)Vi 2.56 kΩ Io + Vs + Vi 75. and Zi remains essentially the same for no-load or loaded conditions.2 k 30.2 kΩ – – – – Figure 10.28.27.46 k 0.08 versus 21.6 (no Rs). 10. The fact that the load is connected between the collector and base terminals isolates it from the input circuit.973 Io Ii Av Zi RL 75.993 Vi + Vo 2.46 k )Vs 75.56 k 65 30.08 Ω 0. 10. The voltage gain is now determined by 10.46 kΩ + 0.

10.2 k )(250)Vi RLAvNLVi 155.29 Common-base configuration with Rs and RL.40) EXAMPLE 10.39) 1 (10.30. and Zo 5 k .31.2 kΩ + Vo – Zi – – Figure 10. 472 Chapter 10 Systems Approach—Effects of Rs and RL .2 kΩ 10 µF + Vi + Vo – – – Figure 10. 10.3Vi Vo 8.30 Example 10. (8. Av and the current gain: Ai RC RL re (10. the no-load two-port parameters are (using 1) Zi re 20 . Ii Io 10 µF 1 kΩ 2V α≈1 = 5 kΩ 8V 8. AvNL 250. (c) Ai. determine: (a) Av.2 kΩ + Vs 0.7 For the common-base amplifier of Fig.2 k 5k RL Ro Ii Io + Vs 0. 10. Solution (a) The small-signal ac equivalent network appears in Fig.31 Small-signal ac equivalent circuit for the network of Fig.2 kΩ + Vi 1 kΩ 20 Ω + – 5 kΩ 250Vi 8. (b) Avs.30. Using the two-port equivalent model.Rs /RL Ii Rs C1 Zi + Vs + Vi RE VEE RC VCC C2 Io RL Zo + Vo – – – Figure 10.7.

41) VDD RD C2 + Vs Rsig C1 Zi Zo RG RS CS RL V o Vi Figure 10.3 5k 8.12 Vi Vo Vs Vi Av 20 20 200 (155. resulting in the following equation for the loaded gain: Av gm(RD RL) (10.3) 8.379 20 (155. + – 10.9 FET Networks + – – 473 .3) 155. the applied load will appear in parallel with RD in the small-signal model. therefore: The no-load two-port model of Fig. the isolation that exists between gate and drain or source of an FET amplifier ensures that changes in RL do not affect the level of Zi and changes in Rsig do not affect Ro. Bypassed Source Resistance For the FET amplifier of Fig.106 k 20 Note the relatively low gain due to a source impedance much larger than the input impedance of the amplifier. 10.2 k 20 3. 10. 10.9 FET NETWORKS As noted in Chapter 9.32.32 JFET amplifier with Rsig and RL.2 k which is significantly less than 1 due to the division of output current between RC and RL. In essence.2 for an FET amplifier is unaffected by an applied load or source resistance.3 (b) Avs Vo Vs Ri Ri Rs 14. (c) Ai Av Zi RL 0.Rs /RL and or Av Av Vo Vi RC RL re 155.

42) (10.45) (10.43) Unbypassed Source Resistance For the FET amplifier of Fig.34 Example 10.18. 10.34.1 MΩ 2. the load will again appear in parallel with RD and the loaded gain becomes Av with and VDD RD Vo Vi Zi Zo gm(RD RL) 1 gmRS RG RD (10. the no-load two-port parameters are AvNL 3. EXAMPLE 10. (a) Using the two-port parameters above.7 kΩ Vo .2 mS.33 JFET amplifier with unbypassed RS. and Zo 2.8.3 kΩ 2 1. with gm 2.4 k .44). calculate the loaded gain and compare to the result of part (a). (b) Using Eq. determine Av and Avs.2 kΩ CS = 20 µ F Figure 10. 10. (10.33.44) (10.46) Rsig C2 C1 Zi + RL Vo + Vs Figure 10. Zi R1 R2 239 k . VDD R1 Rsig 1 kΩ 10 µF RD 2.8 For the FET amplifier of Fig.4 kΩ 20 µ F + Vs Zi Vi R2 RS 270 kΩ RS 1 0.Rs /RL The impedance levels remain at Zi Zo RG RD (10. 474 Chapter 10 Systems Approach—Effects of Rs and RL – – + – + Vi RG Zo RS – – – + Zo RL 4.

4 k 4.105 as above 3.2 mS)(2. (10.44): Av gm(RD RL) 1 gmRS1 (2. (b) Eq.36 Source-follower configuration with Rsig and RL.18) 4.35.7 k )( 3.4 k 2.34. 10. and Av Vo Vi Vo Vs RLAvNL RL Ro Vi Vo Vs Vi (4.2 mS)(0.36. – 10.7 k 2.105 Avs Ri A Ri Rsig v (239 k )( 2.47) VCC Rsig C1 RG Zi C2 RS Zo RL + Vs + Vo – – Figure 10.35 Small-signal ac equivalent circuit for the network of Fig.7 k ) 1 (2.9 FET Networks – – 475 .105) 239 k 1k 2. the level of Zi is independent of the magnitude of RL and determined by Zi RG (10. 10.66 Source Follower For the source-follower configuration of Fig.Rs /RL Solution (a) The small-signal ac equivalent network appears in Fig.4 kΩ − 3.498 1. 10.096 1 kΩ Av + Vs + Zi Vi 239 kΩ + – 2.18Vi Zo + 4.3 k ) 2.7 kΩ Vo Figure 10.

the input and output circuits remain isolated and Zi RS 1 gmRS Zo The loaded voltage gain is given by Av gm(RD RL) (10. the phase relationship between the input and output voltages is also provided for quick reference.51) VDD RD C2 + Rsig + Vs C1 Zi + Vi RS Zo RL Vo – – Figure 10.49) revealing an insensitivity to the magnitude of the source resistance Rsig.50) (10. In each case. Av Vo Vi 1 gm(RS RL) gm(RS RL) (10.37 is somewhat different from those described above with regard to the placement of RL and Rsig. – 10. A review of 476 Chapter 10 Systems Approach—Effects of Rs and RL .52) RD (10.37 Common-gate configuration with Rsig and RL.1.48) The level of output impedance is as determined in Chapter 9: Zo RS 1 gm (10.10 SUMMARY TABLE Now that the loaded and unloaded (Chapters 8 and 9) BJT and JFET amplifiers have been examined in some detail. Although all the equations are for the loaded situation. Common Gate Even though the common-gate configuration of Fig. 10.Rs /RL The loaded voltage gain has the same format as the unloaded gain with RS replaced by the parallel combination of RS and RL. the removal of RL will result in the equations for the unloaded amplifier. a review of the equations developed is provided by Table 10. The same is true for the effect of Rs (for BJTs) and Rsig (for JFETs) on Zo.

TABLE 10. The linkage provided by Ib between input and output circuits of the BJT transistor amplifier adds a touch of complexity to some of the equations. Zo) Configuration Av Vo /Vi RL RC) re Zi RB re Zo RC hfe hie (RL RC) Including ro: (RL RC ro) re (RL RC) re RB hie RC RB re RC ro R1 R2 re RC hfe hie (RL RC) R1 R2 hie RC Including ro: (RL RC ro) re R1 R2 re RC ro RE 1 RL RE RE) Rs RE Rs R1 R2 Rs re R1 R2 (re Rs 1 R1 R2 (hie hfeRE) RE hfe hie Including ro: 1 R1 R2 (re RE) RE Rs re (RL RC) re hfb hib (RL RC) Including ro: (RL RC ro) re RE re RE hib RC RC RE re RC ro 10. Zi.10 Summary Table 477 .Rs /RL the equations will reveal that the isolation provided by the JFET between the gate and channel by the SiO2 layer results in a series of less complex equations than those encountered for the BJT configurations.1 Summary of Transistor Configurations (Av.

Rs /RL TABLE 10. Zi. Zo) (Continued) Configuration VCC Av Vo /Vi RL RC) RE Zi R1 R2 (re RE) Zo RC RC R1 Rs Vi Zo RL Zi R2 RE Vo (RL RC) RE R1 R2 (hie hfeRE) RC + Vs – Including ro: (RL RC) RE RL RC RE1 R1 R2 (re RE) RC VCC RB (re RE1) RC RC RB Rs Vi Zo Vo (RL RC) RE1 RL RB (hie hfeRE1) RC + Vs Zi RE1 – RE2 CE Including ro: RL RC RE1 (RL RC) re RB (re RE1) RF RC VCC RC RF Rs Vi Vo Zo Zi re Av RC hfe hie (RL RC) RF hie A v RC + Vs RL – Including ro: (RL RC ro) re (RL RC) RE RF re Av RF RE Av RC RF RC RF ro VCC RC RF Rs Vi Vo Zo RL Zi RL E (RL RC) RE RF hfeRE Av RC RF + Vs – Including ro: (RL RC) RE RF RE Av RC RF 478 Chapter 10 Systems Approach—Effects of Rs and RL .1 Summary of Transistor Configurations (Av.

10 Summary Table 479 .1 (Continued) Configuration VDD RD Vo Rsig Vi Zo RL Zi RG RS CS Av Vo /Vi Zi Zo gm(RD RL) RG RD + Vs – Including rd: gm(RD RL rd) RG RD rd VDD RD Vo Rsig Vi Zo RL Zi RG RS gm(RD RL) 1 gmRS RG 1 RD gmRS Including rd: gm(RD RL) RD RS gmRS rd RD gmRS + Vs 1 RG 1 – VDD RD R1 Rsig Vi Zo RL Zi R2 RS CS Vo gm(RD RL) R1 R2 RD + Vs Including rd: gm(RD RL rd) R1 R2 RD rd – VDD 1 RD Rsig Vi gm(RS RL) gm(RS RL) RG RS 1/gm + Vs – Zi RG RS Zo RL Vo Including rd: gmrd (RS RL) rd RD gmrd (RS RL) RG 1 RS gmrdRS rd RD Rsig Vi RD VDD Zo Vo RS RL gm(RD RL) Including rd: gm(RD RL) Zi 1 RS gmRS RD + Vs – Zi 1 RS gmrdRS rd RD RL RD rd 10.Rs /RL TABLE 10.

480 Chapter 10 Systems Approach—Effects of Rs and RL . 10. but Eq. 10. Av2. are the voltage gains of each stage under loaded conditions.38 Cascaded system. The total gain of the system is then determined by the product of the individual gains as follows: AvT and the total current gain by AiT AvT Zi1 RL (10. The loading of each succeeding stage must be considered. the application of a load to a two-port system will affect the voltage gain.11 CASCADED SYSTEMS The two-port systems approach is particularly useful for cascaded systems such as that appearing in Fig. the no-load values are provided for each system.53) No matter how perfect the system design. (b) The total gain for the system.38. determine: (a) The loaded gain for each stage.38. Av1 will determine the signal strength and source impedance at the input to Av2. 10. Figure 10. In Fig. 10. For Av2.53) requires the loaded values. 10.39. (10.39 Example 10.9 The two-stage system of Fig. there is no possibility of a situation where Av1. (d) The total gain for the system if the emitter-follower configuration were removed. Av3. (c) The total current gain for the system. Vo = Vi 1 2 Vo = Vi 2 3 + Vi + Aυ Zi = Zi 1 Zo Zi Aυ 2 Zo Zi Aυ 3 Zo A υn Z in Zon = Zo RL Vo – 1 1 2 2 3 3 – Figure 10. and so on. The no-load parameters can be used to determine the loaded gains of Fig. EXAMPLE 10. Av2.54) Av1 Av2 Av3 (10. where Av1. 10.39 employed a transistor emitter-follower configuration prior to a common-base configuration to ensure that the maximum percent of the applied signal appears at the input terminals of the common-base amplifier. which are the loaded values. That is. with the exception of Zi and Zo for the emitter-follower. Av and Avs.38 are simply the no-load values.Rs /RL 10.9. Therefore. of Fig. For the configuration of Fig. and so on.39. Av1 is determined with the input impedance to Av2 acting as the load on Av1.

re 18.2 k (26 26 with )Vs 1k Vo Vi Rs AvT (10 k )(101. Take note. however. that it was also important that the output impedance of the first stage was relatively close to the input impedance of the second stage or the signal would have been “lost” again by the voltage-divider action. respectively.20 Avs Zi1 Zi1 92 (c) AiT Zi1 RL 123.20) 8. the gain is about 25 times greater with the emitter-follower configuration to draw the signal to the amplifier stages.97Vi2 (d) ViCB and 0.2 k )(240)Vi2 8.684)(147. the results 10. 10. all the parameters listed under Model Editor were removed except Is and beta.40 employs the same unloaded configuration examined in the PSpice analysis of Chapter 8.025)(147. Vo2 and (b) AvT Av1Av2 (0.7 from above and Avs (0.97 3. 10.2 k 5. therefore.Rs /RL Solution (a) For the emitter-follower configuration.20) 10 k 1k AvL RLAvNLVi2 RL Ro2 Vo2 Vi2 147. The BJT network of Fig.1 k 147.025Vs 147. In this way.684Vi1 Vo1 26 12 Zi2 Zo1 and Av 1 Vo1 Vi1 0. which were set to 2E-15A and 90.97) 101. where the unloaded gain was 369 (Example 8. the loaded gain is (26 )(1)Vi1 Zi2 AvNLVi1 0. For the transistor.97) In total.684 For the common-base configuration.41 ZiCBVs ZiCB Rs AvT Vi Vs 0.2.12 PSpice Windows 481 .97 (8.025 Vi Vo Vs Vi 10 k (101.12 PSPICE WINDOWS Loaded Voltage-Divider BJT Transistor Configuration The computer analysis of this section includes a PSpice Windows evaluation of the response of a loaded BJT and FET amplifier with a source resistance.44 ).

Reviewing the output file following Analysis-Examine Output will result in the data listings of Fig.32 mA. revealing that the capacitor is an effective short circuit for ac.9.44 ) Chapter 10 Systems Approach—Effects of Rs and RL . the output voltage will rise to 243.40 Loaded voltage-divider BJT transistor configuration. The gain from the base of the transistor to the output is 144. note that VBE is essentially 0.7 V. and under Analysis Setup. which is quite close to the hand-calculated.35 k )Vs 1. Display Results on Schematic under Analysis was chosen and the Voltage Display enabled. Figure 10.44 R1 R2 re 56 k 1.69Vs 8. and the Operating Point Information reveals that beta (dc and ac) is 90.3 mV/0. The loaded gain from source to output is 144. If we return to the network and change RL to 10 M .Rs /RL will be as close to the hand-written solutions as possible without going to the controlled source equivalents.3 mV (30% loss in signal voltage) of the applied signal across Rsig.7 mV 207. 10. An Analysis resulted in the dc levels appearing in Fig.2 k (90)(18.40. and the BJT MODEL PARAMETERS reveal our choices for this run—although the last three are default values. re and Zi 18. the AC Sweep was set at a fixed frequency of 10 kHz.9.2 (using the approximate approach). The AC ANALYSIS reveals that the voltage on the other side of Rsig is about 0. resulting in a drop of about 0. that VBE is 0. For interest’s sake. 10.7 V and the dc levels of each terminal of the transistor are very close to those calculated in Example 8. The SMALL-SIGNAL BIAS SOLUTION simply confirms the levels printed on the schematic. let us now calculate the loaded voltage gain and compare to the PSpice solution of 144.6 k 0. The option Do not auto-run Probe was chosen.7 A (in addition to a host of other levels). resulting in a gain of 243.35 k Vi and 482 Vi Vs ZiVs Zi Rs 0. approximate level of 369.41. that IC is 1.3 mV. and that IB is 14. Both levels are certainly significantly less than the no-load level of 369.7 mV.35 k 0.9 mV/0.57. In addition.69 (1.7 mV 347. The nodes are defined in the Schematics Netlist. In particular. Note the placement of the VPRINT1 option to pick up the voltage lost across the source resistance and to note if there is any drop in gain across the capacitor. In addition. The remaining two ac levels are the same. note the zero volt levels at the left side of C1 and the right side of C2.

40.Rs /RL Figure 10.41 Output file for the network of Fig. 10. 483 .

62 The results obtained above have clearly substantiated the analysis and equations presented in this chapter for a loaded amplifier. 484 Chapter 10 Systems Approach—Effects of Rs and RL 3.69)( 208. Beta was 4V.4) 10 k 6. In addition. Note also that the drop across Rsig is negligible due to the high input impedance of the device. and the OPERATING POINT INFORMATION reveals that the drain current is 3. note the effectiveness of the capacitors to block the dc voltages.597mV resulting in a loaded gain of 5.3. The remaining parameters were left alone to perset to 0.3 k ) . vice is in reality not infinite (although for all practical purposes it is an excellent assumption. In the Model Editor dialog box. Using the value of gm hand-calculated earlier. note the small voltage at the gate.57 with Avs (0.90 mS)(4.42 is a loaded version of the network examined in Chapter 9. the equation for the loaded gain will result in a gain of 5.71 V.42 Loaded self-bias JFET transistor configuration. The sequence Analysis-Examine Output will result in the listing of Fig.625mA/V2 and Vto mit a close comparison with the Chapter 9 solution and because they have less effect on the response than for a BJT transistor. and the short-circuit equivalency can be assumed.3.57) which is an excellent comparison with the computer solution. which resulted in a no-load gain of 13.36 mA. indicating that the input impedance to the de- Figure 10.94 mS. the frequency was set to 10 kHz and an Analysis called for without the Probe option.8 k 208. The Schematics Netlist provides a listing of assigned nodes.62 as shown below—an excellent comparison with the computer solution.) Again. Again. 10. The output voltage is 5.43.7 k 5.597 compared to the unloaded gain of 13. 10.Rs /RL Av Vo Vi Vi Vo Vs Vi 144 RLAvNL RL Ro (10 k )( 350. and that gm is 2. Av gm(RD RL) (2. that VGS is 1. The AC ANALYSIS reveals that there is negligible drop across either capacitor at this frequency. Loaded JFET Self-Bias Transistor Configuration The network of Fig.

.42.43 Output file for the network of Fig. 10.Rs /RL Figure 10.

(a) Draw the dc and ac load lines for the network of Fig. For the fixed-bias configuration of Fig. (c) Calculate the gain Av using the model of part (b) and Eq. 10. and 3 * 2. 10. and Zo using the re model and compare with the solutions above.2 with the parameters determined in part (a) in place. Determine the voltage gain Av Vo/Vi and compare with the solution obtained in Problem 1. (b) Determine the peak-to-peak value of Ic and Vce from the graph if Vi has a peak value of 10 mV.44 Problems 1. 18 V 3.44: (a) Determine AvNL. (b) Sketch the two-port model of Fig. 10.3). (e) Determine Av. (d) Determine the current gain using Eq. (10. and Zo.44 on the characteristics of Fig.6).8 µF Vi Ii 1.8 µF Io Vo β = 100 Zo RL 4.Rs /RL PROBLEMS § 10.3 kΩ 680 kΩ 1.45. Zi.45 Problems 2 and 7 486 Chapter 10 Systems Approach—Effects of Rs and RL . 10.7 kΩ Zi Figure 10. Zi. 2. Figure 10. (10.3 Effect of a Load Impedance (RL) 1.

10.46: Determine AvNL.Rs /RL 3. and Zo. 2. For (a) (b) (c) (d) (e) (f) (g) (h) the network of Fig.6 k and Rs to 0. What is the effect of increasing levels of RL on the gain? (f) Change Rs to 0. (c) Determine Av and Avs.47: (a) Determine AvNL. Sketch the two-port model of Fig.44 for RL What is the effect of decreasing levels of RL on the voltage gain? (b) How will Zi.5 k (with RL at 2.7.5 k . How does Av change with the level of Rs? Change Rs to 1 k and determine Avs.5 Combined Effect of Rs and RL * 5.6 k and calculate Avs. 10. and AvNL change with decreasing values of RL? 4. Determine Av using the results of part (b). (e) Change RL to 5.2. Determine Avs. Zi. and 0. 10. (g) Change RL to 5. Zo. How are the impedance parameters affected by changing levels of RL and Rs? 24 V 4.7 kΩ + Vs – Zi Figure 10. How do they change with change in Rs? 12 V 3 kΩ 1 MΩ 1 µF Vo Vi Rs 1 µF β = 180 Zo + Vs 0.46 Problem 4 § 10. How does Avs change with the level of Rs? Change Rs to 1 k and determine AvNL.4 Effect of a Source Impedance (Rs) * 4. Zi. For the network of Fig. and Zo. Zi.6 kΩ Zi – Figure 10. Change Rs to 1 k and determine Av.5 k and determine the new levels of Zi and Zo. (a) Determine the voltage gain Av for the network of Fig. § 10. (d) Calculate Ai. (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place.2 with the parameters determined in part (a) in place.3 kΩ 560 kΩ Ii 10 µF 10 µ F Io Vo Vi Rs 1 kΩ β = 80 Zo RL 2. Determine Avs using the re model and compare the results to that obtained in part (d).7 k ) and comment on the effect of reducing Rs on Avs. and Zo. 10.47 Problems 5 and 17 Problems 487 .

Zi.49 Problem 9 488 Chapter 10 Systems Approach—Effects of Rs and RL . Zi.48: (a) Determine AvNL. and 8 * 7. Zi. (c) Calculate the gain Av using the model of part (b).6 BJT CE Networks 6. 8. Determine the voltage gain Av Vo /Vi and compare the solution with that obtained in Problem 6. What is the effect of increasing levels of Rs on Av and Avs? Figure 10. What is the effect on AvNL. and Zo. 10. and Zo.48 on the characteristics of Fig. 10.49: (a) Determine AvNL. 10. For the voltage-divider configuration of Fig. What is the effect of decreasing levels of RL on the voltage gain? (b) How will Zi.2 with the values determined in part (a). (b) Determine the peak-to-peak value of Ic and Vce from the graph if Vi has a peak value of 10 mV.Rs /RL § 10. (c) Determine Av and Avs. and Zo? (e) Change Rs to 1 k and determine Av and Avs. 7. (a) Determine the voltage gain Av for the network of Fig.45. Figure 10.2. 2. (b) Sketch the two-port model of Fig. 10.2 with the parameters determined in part (a) in place. and 0. 10. (a) Draw the dc and ac load lines for the network of Fig. (b) Sketch the two-port model of Fig. 10. and AvNL change with decreasing levels of RL? 4. For the emitter-stabilized network of Fig.7. 10. Zo.5 9. and Zo using the re model and compare solutions. (d) Determine the current gain Ai. Zi.48 with RL k . (d) Change Rs to 1 k . (e) Determine Av.48 Problems 6.

6 k . (d) Change Rs to 1 k and determine Av and Avs. What is the effect of changing levels of Rs and RL on the voltage gains? (f) Determine Zo if Rs changed to 0. 10.5 k with all other parameters as appearing in Fig.51: (a) Determine Zi. Zi. What is the effect of changing levels of RL on the input impedance? Figure 10. 10. and AvNL. and Zo. For the common-base network of Fig.6 k and determine Av and Avs. (c) Determine Av and Avs.51. What is the effect of increasing levels of Rs on the voltage gains? (e) Change Rs to 1 k and determine AvNL. What is the effect of increasing levels of RL on the voltage gains? Maintain Rs at its original level of 0.51 Problems 11 and 19 Problems 489 .2 k and calculate Av and Avs. Zo.2 with the parameters of part (a) in place. Figure 10.2 with the values determined in part (a). What is the effect of increasing levels of Rs on the parameters? (f) Change RL to 5. (d) Determine Av and Avs using the re model and compare with the results of part (c). 10.2 k . (c) Determine Av and Avs. (e) Change Rs to 0. and Zo.8 BJT CB Networks * 11. For the network of Fig.5 k and RL to 2. 10. (b) Sketch the two-port model of Fig.Rs /RL § 10.50: (a) Determine AvNL. Zi. (b) Sketch the two-port model of Fig.7 BJT Emitter-Follower Networks * 10.50 Problems 10 and 18 § 10. How is Zo affected by changing levels of Rs? (g) Determine Zi if RL is reduced to 2. 10.

(c) Determine Av and Avs.2 with the parameters determined in part (a) in place. and Zo.7 k and calculate Av and Avs. 10. 10. Zi.9 FET Networks 12. (b) Sketch the two-port model of Fig.6 kΩ 10 µF 1 MΩ 0.52: (a) Determine AvNL. What was the effect of increasing levels of RL on both voltage gains? (e) Change Rsig to 1 k (with RL at 2. 10.7 kΩ + Vs Figure 10.53 Problem 13 490 Chapter 10 – 12 V Rsig 0. (d) Change RL to 4.2 kΩ – Systems Approach—Effects of Rs and RL . (c) Determine Av and Avs. What was the effect of increasing levels of Rsig on both voltage gains? (f) Change RL to 4. (b) Sketch the two-port model of Fig.7 kΩ 10 µ F Vo Rsig 0. Zi.7 k and Rsig to 1 k and calculate Zi and Zo. determine Zi and Zo. 10.2 µF Vi IDSS = 6 mA VP = − 6 V Vo 8. What was the impact on both impedances? 12 V 2.8 k and Rsig to 1 k and calculate the new levels of Av and Avs. (d) Change RL to 6. How are the voltage gains affected by changes in Rsig and RL? (e) For the same changes as part (d).Rs /RL § 10.53: (a) Determine AvNL.2 k ) and calculate Av and Avs.5 kΩ 2 MΩ Zi 8.52 Problems 12 and 20 13. For the source-follower network of Fig. and Zo.2 µF 3. What was the effect on both parameters? + Vs Figure 10.3 kΩ Zo 2.2 with the parameters determined in part (a) in place. For the self-bias JFET network of Fig.51 kΩ 20 µF Vi IDSS = 10 mA VP = − 6 V Zo Zi RL 4.

55 with two identical stages.3 kΩ Aυ NL = – 420 Zi 2 Vo Zo RL 2.55 Problem 15 – – Rs 0. (f) How Zo is affected by the first stage and Rs. (c) The loaded current gain of each stage.6 µF Vo IDSS = 5 mA VP = − 4 V Rsig 5. 10. 10.7 kΩ Problems 491 .54: (a) Determine AvNL. (e) How Zi is affected by the second stage and RL. Av and Avs. Zi.7 kΩ + Vs 1 kΩ Zi 1. What was the effect on both parameters? 18 V 3. For the common-gate configuration of Fig.11 Cascaded Systems 1 µF V i CE amplifier Zi = 1 kΩ Zo = 3.3 kΩ Aυ NL = – 420 Zo 1 1 µF CE amplifier Zi = 1 kΩ Zo = 3. What was the effect of changing RL on the voltage gains? (e) Change Rsig to 0. + Vs Figure 10. For the cascaded system of Fig.6 kΩ Zi § 10.2 with the parameters determined in part (a) in place.2 k and Rsig to 0. (b) Sketch the two-port model of Fig. 10.7 k ) and calculate Av and Avs.Rs /RL * 14.3 kΩ 5.5 k and calculate Zi and Zo.5 k (with RL at 4. (c) Determine Av and Avs. (g) The phase relationship between Vo and Vi. determine: (a) The loaded voltage gain of each stage.6 µ F Vi Zo 4. and Zo. (d) The total current gain of the system.2 kΩ Figure 10. (b) The total gain of the system. What was the effect of changing Rsig on the voltage gains? (f) Change RL to 2.2 k and calculate Av and Avs.54 Problem 14 * 15. (d) Change RL to 2.

For the capacitive elements assume a frequency of 1 kHz. 10.52 and compare with the results of Problem 12.2 kΩ Figure 10. 492 Chapter 10 – Zi 2 § 10.Rs /RL * 16.2 kΩ Zo = 4.56 Problem 16 17. Repeat Problem 17 for the network of Fig. determine: (a) The loaded voltage gain of each stage. 10. (f) How Zo is affected by the first stage and Rs. Repeat Problem 17 for the network of Fig.51 and compare with the results of Problem 11. 10. determine the level of Vo for Vs 1 mV for the network of Fig. 20. 10. (e) How Zi is affected by the second stage and RL. (d) The total current gain of the system. 19.6 kΩ Aυ NL = – 640 Zo 1 Vo + Vs RL Zo 2.47. (b) The total gain of the system.56. (g) The phase relationship between Vo and Vi. 10. Av and Avs. 18.50 and compare the results with those of Problem 10. Rs Vi Emitter . *Please Note: Asterisks indicate more difficult problems. (c) The loaded current gain of each stage. Repeat Problem 17 for the network of Fig.follower 1 kΩ 10 µF Zi Zi = 50 kΩ Zo = 20 Ω Aυ ≅ 1 NL 10 µF CE amplifier Z i = 1. Using PSpice Windows. For the cascaded system of Fig.12 PSpice Windows Systems Approach—Effects of Rs and RL .

The similarities between the frequency response analyses of both BJTs and FETs permit a coverage of each in the same chapter.000 10x 493 . Since the analysis will extend through a wide frequency range.f CHAPTER BJT and JFET Frequency Response 11. and x are the same in each equation. it was a frequency that normally permitted ignoring the effects of the capacitive elements. For the amplifier. review. If a is determined by taking the base b to the x power.1) The variables a. In addition. if b 10 and x 2. x logb a (11. the logarithmic scale will be defined and used throughout the analysis. reducing the analysis to one that included only resistive elements and sources of the independent and controlled variety.1 INTRODUCTION The analysis thus far has been limited to a particular frequency. the same x will result if the log of a is taken to the base b. b.2 LOGARITHMS There is no escaping the need to become comfortable with the logarithmic function. As a first step in clarifying the relationship between the variables of a logarithmic function. For instance. consider the following mathematical equations: a bx. 11 11. and identifying levels of particular importance in the design. since industry typically uses a decibel scale on its frequency plots. and analysis procedures are all positive features of using the logarithmic function. if you were asked to find the power of a number that would result in a particular level such as shown below: 10. We will now investigate the frequency effects introduced by the larger capacitive elements of the network at low frequencies and the smaller capacitive elements of the active device at the high frequencies. The plotting of a variable between wide limits. a but x bx (10)2 100 2 logb a log10 100 In other words. the concept of the decibel is introduced in some detail. comparing levels without unwieldy numbers.

In summary: Common logarithm: x Natural logarithm: y The two are related by loge a 2. x log10 10.f the level of x could be determined using logarithms. In addition. Solution (a) 1. (b) loge 64. note that the logarithm of a number does not increase in the same linear fashion as the number.4). (b) loge e3. Solution (a) 6 (b) 3 (c) 2 (d) 1 The results in Example 11. Logarithms taken to the base 10 are referred to as common logarithms. (d) loge e 1.903 Note in parts (a) and (b) of Example 11.2) (11.1 clearly reveal that the logarithm of a number taken to a power is simply the power of the number if the number matches the base of the logarithm. 8000 is 125 times larger than 64.2 that the logarithms log10 a and loge a are indeed related as defined by Eq. EXAMPLE 11. (c) log10 1600. . (d) log10 8000.159 (c) 3. (c) log10 10 2.1 Using the calculator.71828. (11.16 times larger 494 Chapter 11 BJT and JFET Frequency Response . (a) log10 64. (a) log10 106. but the logarithm of 8000 is only about 2.3) On today’s scientific calculators. determine the logarithm of the following numbers to the base indicated. EXAMPLE 11. In the next example.000 4 For the electrical/electronics industry and in fact for the vast majority of scientific research.204 (d) 3. determine the logarithm of the following numbers.806 (b) 4.3 log10 a (11. That is.4) log10 a loge a (11. the base in the logarithmic equation is limited to 10 and the number e 2. the base and the variable x are not related by an integer power of the base. That is. the common logarithm is typically denoted by the key and the natural logarithm by the key. . .2 Using the calculator. while logarithms taken to the base e are referred to as natural logarithms.

determine the antilogarithm of the following expressions: (a) 1. In fact.5) 1 becomes log10 1 b log10 b (11.000. log10 ab log10 a log10 b (11. If the antilogarithm of a number is desired.3 Solution (a) a 101.f than the magnitude of the logarithm of 64.000 and so on 0 1 2 3 4 5 6 7 8 Using a calculator. the equations employing natural logarithms will have the same format.000 log10 100. log10 1 As clearly revealed by Table 11. TABLE 11. the 10x or ex calculator functions are employed. (b) 0. 11.04 loge a. log10 b (11.81 (b) a e0.000.6 Calculator keys: and a 39. since 100 log10 which for the special case of a a b log10 a 0 1.1 log10 100 log10 10 log10 100 log10 1.7) revealing that for any b greater than 1 the logarithm of a number less than 1 is always negative.6) (11. the same relationships hold true for logarithms to any base.000 log10 100. revealing a very nonlinear relationship. Table 11.1. In general.0408 Since the remaining analysis of this chapter employs the common logarithm.04 Calculator keys: and a 1.000 log10 10. EXAMPLE 11.8) In each case.000 log10 10. let us now review a few properties of logarithms using solely the common logarithm.6 log10 a. however.2 Logarithms 495 .000.000 log10 1.1 clearly shows how the logarithm of a number increases only as the exponent of the number.

Figure 11. The term semi (meaning one-half) indicates that only one of the two scales is a log scale.4 Using a calculator.1.6 30) log10 18 1. The spacing between the lines of the log plot is shown on the graph.477 1.6 30). Note that the vertical scale is a linear scale with equal divisions.398 1. whereas double-log indicates that both scales are log scales. Most graph paper available is of the semilog or double-log (log-log) variety.602 2.1 Semilog graph paper. 496 Chapter 11 BJT and JFET Frequency Response . Solution (a) 0. 250 (c) log10 (0.204 250 0.255 The use of log scales can significantly expand the range of variation of a particular variable on a graph. A semilog scale appears in Fig.2218 1. 11.204 4000 Check: log10 log10 16 1.255 (c) log10 0.3 (b) log10 4000 log10 250 3.6 log10 30 Check: log10 (0. 4000 (b) log10 .f EXAMPLE 11.5. determine the logarithm of the following numbers: (a) log10 0.

5. the relationship can be written as log4 64 3. since plots will typically only have the tic marks indicated in Fig. This is particularly true for some of the log-log plots that appear later in the book.5) Figure 11. Note that between any two digits the same compression of the lines appears as you progress from the left to the right. the bel (B) was defined by the following equation to relate power levels P1 and P2: G log10 P2 P1 bel (11. Since log10 5 0.3 Decibels 497 .7. an increase in power level. In logarithmic form. It is important to note the resulting numerical value and the spacing. whereas the next shorter bars have values of 0. 11. The term bel was derived from the surname of Alexander Graham Bell. That is.3. and 30 associated with them. 5.1 0. It will increase by a factor of 2 as derived from the power of 4 in the following manner: (4)2 16. The important point is that the results extracted at each level be correctly labeled by developing a familiarity with the spacing of Figs. 7.7 1 10 100 log almost three-fourths (0.1 and 11. and 50 and the shortest bars 0. For a change of 4 to 64 W. 3.2 due to a lack of space.3) (3) (5) (7) (30) (50) (70) 0. say 4 to 16 W. For standardization. it is marked off at a point 70% of the distance. The distance from 1 (log10 1 0) to 2 is therefore 30% of the span. 11. Be aware that plotting a function on a log scale can change the general appearance of the waveform as compared to a plot on a linear scale. about halfway (0. and a nonlinear plot on a linear scale can take on the appearance of a straight line on a log plot. A straight-line plot on a linear scale can develop a curve on a log scale. the audio level will increase by a factor of 3 since (4)3 64. 11.9) 11.2.4771 or almost 48% of the span (very close to one-half the distance between power of 10 increments on the log scale).3 DECIBELS The concept of the decibel (dB) and the associated calculations will become increasingly important in the remaining sections of this chapter. The log of 3 to the base 10 is 0. and 70. You must realize that the longer bars for this figure have the numerical values of 0.2 Identifying the numerical values of the tic marks on a log scale.3.7.f The log of 2 to the base 10 is approximately 0. The background surrounding the term decibel has its origin in the established fact that power and audio levels are related on a logarithmic basis. does not result in an audio level increase by a factor of 16/4 4.

that the decibel rating is a measure of the difference in magnitude between two power levels.12) Figure 11.3. The reference level is generally accepted to be 1 mW. If we substitute into 2 Eq. For a specified terminal (output) power (P2) there must be a reference power level (P1). The resistance to be associated with the 1-mW power level is 600 . then P2 V2/Ri. the decibel symbol frequently appears as dBm. For Vi equal to some value V1. It can be best described through the system of Fig. (11. however.10) to determine the resulting difference in decibels between the power levels. P1 2 V 1/Ri. Frequently.12) applied simply to establish a basis of comparison between levels—voltage or current. In equation form. chosen because it is the characteristic impedance of audio transmission lines.3. One of the advantages of the logarithmic relationship is the manner in which it can be applied to cascaded stages. microphones.f It was found.10) indicates clearly.3 Configuration employed in the discussion of Eq. Therefore. the 6-mW standard of earlier years is applied.11) There exists a second equation for decibels that is applied frequently. For situations of this type. Equation (11. 11. so the decibel (dB) was defined such that 10 decibels 1 bel. the magnitude of the overall voltage gain of a cascaded system is given by Av Av Av … Av (11.) is commonly rated in decibels. 11. GdB 10 log10 P2 P1 dB (11. GdB 10 log10 P2 P1 10 log10 V2 V1 V 2/Ri 2 2 V 1/Ri 10 log10 V2 V1 2 and GdB 20 log10 dB (11. that the bel was too large a unit of measurement for practical purposes. When the 1-mW level is employed as the reference level. If Vi should be increased (or decreased) to some other level. where Ri .13) Av T 1 2 3 n 498 Chapter 11 BJT and JFET Frequency Response .10) The terminal rating of electronic communication equipment (amplifiers. is the input resistance of the system of Fig. etc. the decibel gain should more correctly be referred to as the voltage or current gain in decibels to differentiate it from the common usage of decibel as applied to power levels. For example.12). (11. however. although on occasion. the effect of different impedances (R1 R2) is ignored and Eq. P2 1 mW GdBm 10 log10 600 dBm (11. (11. V2.

2 or 100 to 1000 results in the same 20-dB change in level.301) 13. a future calculation giving a decibel result in the neighborhood of 100 should be questioned immediately.3 Decibels 499 . EXAMPLE 11. Certainly.000 etc. When Vo Vi. Table 11. At a very high gain of 1000.f Applying the proper logarithmic relationship results in Gv 20 log10 AvT 20 log10 Av1 20 log10 Av2 20 log10 Avn (dB) (11. (c) Explain why parts (a) and (b) agree or disagree.000. the dB level is 80 dB.5 Solution By Eq. Table 11. while the output impedance is 20 . the dB level is 60. the equation states that the decibel gain of a cascaded system is simply the sum of the decibel gains of each stage. 20 log10 Av3 Vo /Vi 0.2 Voltage Gain.6 Solution (a) GdB Po 500 W 1 10 log10 10 log10 10 log10 20 Pi 10 kW 20 10(1.10). A change in Vo /Vi from 1 to 10. an increase of only 20 dB—a result of the logarithmic relationship.000 P1 This example clearly demonstrates the range of decibel values to be expected from practical devices. (11. Find the magnitude gain corresponding to a decibel gain of 100.000 W at a voltage of 1000 V.01 dB Vo PR (500 W)(20 ) 20 log10 20 log10 20 log10 Vi 1000 1000 V 10 log10 20 log10 (c) Ri Vi2 Pi 100 1000 (1 kV)2 10 kW 20 log10 106 104 1 10 20 log10 10 Ro 20 20 dB (b) Gv 100 11. The input power to a device is 10.707 1 2 10 40 100 1000 10. Vo /Vi 1 and the dB level is 0. The output power is 500 W.2 clearly reveals that voltage gains of 50 dB or higher should immediately be recognized as being quite high. that is.5 0.000. while at the much higher gain of 10.14) TABLE 11. Gv Gv1 Gv2 Gv3 Gvn dB (11.000. (b) Find the voltage gain in decibels. 10 to 100.2 was developed. (a) Find the power gain in decibels. 10 log10 P2 P1 100 dB → log10 P2 P1 10 EXAMPLE 11.15) In an effort to develop some association between dB levels and voltage gains. GdB so that P2 1010 10. First note that a gain of 2 results in a dB level of 6 dB while a drop to 1 results in a 6-dB level. dB Level 6 3 0 6 20 32 40 60 80 In words.

An increase in the number of stages of a cascaded system will also limit both the high. The magnitudes of the gain response curves of an RC-coupled. or CE. In addition. while its upper frequency limit is determined by either the parasitic capacitive elements of the network and frequency dependence of the gain of the active device.2 V 20 V 200 mV 40 40 W Pi Pi 40 W antilog (2. (11. 11.7 An amplifier rated at 40-W output is connected to a 10.to the high-frequency regions. The gain must obviously be zero at f 0 since at this point there is no longer a changing flux established through the core to induce a secondary or output voltage.4 GENERAL FREQUENCY CONSIDERATIONS The frequency of the applied signal can have a pronounced effect on the response of a single-stage or multistage network. a low-. and transformer-coupled amplifier system are provided in Fig.f EXAMPLE 11. (a) Calculate the input power required for full power output if the power gain is 25 dB. Cs.5) 40 W 3. The analysis thus far has been for the midfrequency spectrum. high-. The frequency-dependent parameters of the small-signal equivalent circuits and the stray capacitive elements associated with the active device and the network will limit the high-frequency response of the system. and mid-frequency region has been defined.5 mW 20 log10 Vo Vi 11. 11. As indicated in Fig. Solution (a) Eq.4. we shall find that the coupling and bypass capacitors can no longer be replaced by the short-circuit approximation because of the increase in reactance of these elements. For each plot. At low frequencies.and low-frequency responses. direct-coupled.16 102 126. Note that the horizontal scale is a logarithmic scale to permit a plot extending from the low.speaker. For the moment. the high-frequency response is controlled primarily by the stray capacitance between the turns of the primary and secondary wind500 Chapter 11 BJT and JFET Frequency Response . let us say that it is simply due to the “shorting effect” (across the input terminals of the transformer) of the magnetizing inductive reactance at low frequencies (XL 2 fL).10): 25 10 log10 40 W 316 (b) Gv Vo Vi Vo Vi 20 log10 antilog 2 PR Vo 100 Vo Vi 100 (40 W)(10 V) 20 V 100 0. the primary reasons for the drop in gain at low and high frequencies have also been indicated within the parentheses. (b) Calculate the input voltage for rated output if the amplifier voltage gain is 40 dB. An explanation of the drop in gain for the transformer-coupled system requires a basic understanding of “transformer action” and the transformer equivalent circuit.4. the drop at low frequencies is due to the increasing reactance of CC. For the RC-coupled amplifier.

at midfrequencies. break. or half-power frequencies. Pomid and at the half-power frequencies. ings. there are no coupling or bypass capacitors to cause a drop in gain at low frequencies. 11. band.4 General Frequency Considerations . The corresponding frequencies f1 and f2 are generally called the corner.707AvmidVi 2 Ro 0. PoHPF 0.f Figure 11.4. (b) transformercoupled amplifiers.707 was chosen because at this level the output power is half the midband power output. there is a band of frequencies in which the magnitude of the gain is either equal or relatively close to the midband value. The multiplier 0.707Avmid was chosen to be the gain at the cutoff levels. To fix the frequency boundaries of relatively high gain. For the direct-coupled amplifier. For each system of Fig. cutoff.4 Gain versus frequency: (a) RC-coupled amplifiers. it is a flat response to the upper cutoff frequency. that is.5 AvmidVi 2 Ro 501 V2o Ro AvmidVi 2 Ro 11. (c) direct-coupled amplifiers. which is determined by either the parasitic capacitances of the circuit or the frequency dependence of the gain of the active device. 0. As the figure indicates.

000 100.5 Normalized gain versus frequency plot.12) in the following manner: Av Avmid dB 20 log10 Av Avmid (11. Figure 11. At high frequencies.and high-frequency regions. 11.16) The bandwidth (or passband) of each system is determined by f1 and f2. This fact must now be expanded to indicate that this is the case only in the midband region. the more negative the decibel level. For the greater part of the discussion to follow. a decibel plot of the voltage gain versus frequency is more useful than that appearing in Fig.6 Decibel plot of the normalized gain versus frequency plot of Fig. Before obtaining the logarithmic plot. therefore. bandwidth (BW) f2 f1 (11. 20 log10 1/ 2 3 dB.4. 11. the resulting level is 0.5Pomid (11.6. At the half-power frequencies. the gain at each frequency is divided by the midband value.18) Aυ A υmid 1 0.5.17) For applications of a communications nature (audio. Obviously. video). Aυ Aυ 10 0 dB − 3 dB − 6 dB − 9 dB − 12 dB mid (dB) f1 100 1000 10. 502 Chapter 11 BJT and JFET Frequency Response . A decibel plot can now be obtained by applying Eq. It should be understood that most amplifiers introduce a 180° phase shift between input and output signals. The smaller the fraction ratio. that is.f and PoHPF 0.7 is a standard phase plot for an RC-coupled amplifier. 11.707 10 f1 100 1000 10. Both values are clearly indicated in the resulting decibel plot of Fig.000 f2 1 MHz 10 MHz f (log scale) Figure 11. In this figure. to permit a visualization of the broad system response.000 f2 1 MHz 10 MHz f (log scale) Figure 11. the midband value is then 1 as indicated. the phase shift will drop below 180°. (11. 20 log10 1 0.6 in mind. there is a phase shift such that Vo lags Vi by an increased angle. Keep Fig.000 100. a decibel plot will be made only for the low. At midband frequencies. 11. 11. and at the cutoff frequencies.5.707 1/ 2. the curve is generally normalized as shown in Fig. however. At low frequencies.

8 R-C combination that will define a low cutoff frequency. will begin with the series R-C combination of Fig.10 R-C circuit of Figure 11. 0 f1 f Figure 11.8 and the development of a procedure that will result in a plot of the frequency response with a minimum of time and effort. therefore. 11.000 100.8 at f 0 Hz.7 Phase plot for an RC-coupled amplifier system. At very high frequencies. Our analysis. 11. with the result that Vo 0 V. an R-C network similar to Fig.5 Low-Frequency Analysis—Bode Plot 503 . + Vi R + Vo – – and the short-circuit equivalent can be substituted for the capacitor as shown in Fig.000 f2 1 MHz 10 MHz f f (log scale) Figure 11. they can be compared to establish which will determine the low-cutoff frequency for the system.8.9. the ratio Av Vo /Vi will vary as shown in Fig.707 Figure 11. As the frequency increases.10. A υ = Vo / Vi 1 0. The result is that Vo Vi at high frequencies.5 LOW-FREQUENCY ANALYSIS— BODE PLOT In the low-frequency region of the single-stage BJT or FET amplifier.8 at very high frequencies.9 R-C circuit of Figure 11. Once the cutoff frequencies due to each capacitor are determined. At f 0 Hz. CE. and Cs and the network resistive parameters that determine the cutoff frequencies. 11. XC 1 2 fC 1 2 (0)C Figure 11. XC 1 2 fC 0 Figure 11. the capacitive reactance decreases and more of the input voltage appears across the output terminals.8 can be established for each capacitive element and the frequency at which the output voltage drops to 0. 11.11. 11. In fact.< (Vo leads Vi ) 360° 270° 180° 90° 0° 10 f1 100 1000 10. Between the two extremes. 11. it is the R-C combinations formed by the network capacitors CC.11 Low frequency response for the R-C circuit of Figure 11. 11. and the open-circuit approximation can be applied as shown in Fig.707 of its maximum value determined.

20).6.8.7% of the input for the network of Fig.f The output and input voltages are related by the voltage-divider rule in the following manner: Vo with the magnitude of Vo determined by Vo For the special case where XC Vo RVi R 2 2 XC R RVi XC RVi 2 R2 X C R. we recognize that there is a 3-dB drop in gain from the midband level when f f1. 11. Av Vo Vi 1 1 ( f1/f )2 magnitude of Av 1 1 j( f1/f ) (11.707 XC (11. In a moment. 11. (11.11.20) 20 log10 Av 1 or Vo Gv 20 log10 1 2 0 dB 3 dB Vi (the maximum value). the output will be 70. Av In the magnitude and phase form. The frequency at which this occurs is determined from XC 1 2 f1C f1 1 2 RC R and In terms of logs. at the frequency of which XC R. Gv while at Av Vo /Vi (11.22) 504 Chapter 11 BJT and JFET Frequency Response .21) tan 1( f1/f ) phase by which Vo leads Vi (11. If the gain equation is written as Av Vo Vi R R jXC 1 1 j(XC/R) 1 1 j(1/ CR) 1 1 j(1/2 fCR) and using the frequency defined above. 11. RVi RVi 2R 2 RVi 1 2R R 2 Vi and Av Vo Vi 1 2 0. 20 log10 1 20(0) In Fig.19) the level of which is indicated on Fig. In other words. we will find that an RC network will determine the low-frequency cutoff frequency for a BJT transistor and f1 will be determined by Eq.

12 from 0. At f f1: 1 2 f1 f f1 f f1 f f1 f 1 and 20 log10 1 20 log10 2 20 log10 4 0 dB At f f1: f1: f1: 2 and 6 dB At f 1 4 4 and 12 dB At f 1 10 10 and 20 log10 10 20 dB A plot of these points is indicated in Fig.707 → 3 dB In the logarithmic form. 1 1 (1) 2 1 2 0. (11. 505 . a straight Figure 11. Note that this results in a straight line when plotted against a log scale.23) on a frequency log scale will yield a result of a very useful nature for future decibel plots.1f1 to f1.12 Bode plot for the low-frequency region.f For the magnitude when f Av f1. Av(dB) 1. the gain in dB is Av(dB) 20 log10 1 1 ( f1/f )2 f1 f f1 f 2 2 20 log10 1 f1 f 2 1/2 ( 1 )(20) log10 1 2 10 log10 1 For frequencies where f by f1 or (f1/f)2 Av(dB) and finally. a plot of Eq. 11. the equation above can be approximated 10 log10 f1 f 2 20 log10 f1 f f f1 (11. In the same figure.23) Ignoring the condition f f1 for a moment.

28)(5 10 3 )(0. results in a 6-dB change in the ratio as noted by the change in gain from f1/2 to f1. Solution (a) f1 Figure 11. simply find f1 from the circuit parameters and then sketch two asymptotes—one along the 0-dB line and the other drawn through f1 sloped at 6 dB/octave or 20 dB/decade. See Fig. Employing this information in association with the straight-line segments permits a fairly accurate plot of the frequency response as indicated in the same figure. the straightline segments (asymptotes) are only accurate for 0 dB when f f1 and the sloped line when f1 f.13: (a) Determine the break frequency.8 1 2 RC 1 (6. there is a 20-dB change in the ratio as demonstrated between the frequencies of f1/10 and f1.1 10 6 F) 318. 11. As stated earlier.13 Example 11. The piecewise linear plot of the asymptotes and associated breakpoints is called a Bode plot of the magnitude versus frequency. find the 3-dB point corresponding to f1 and sketch the curve. As noted by the change in gain from f1/2 to f1: For a 10:1 change in frequency. The calculations above and the curve itself demonstrate clearly that: A change in frequency by a factor of 2.23). 11. (11.5 Hz (b) and (c).14 Frequency response for the R-C circuit of Figure 11.8 For the network of Fig. a decibel plot can easily be obtained for a function having the format of Eq. that when f f1. 3-dB point. (b) Sketch the asymptotes and locate the (c) Sketch the frequency response curve. Figure 11. We know.f line is also drawn for the condition of 0 dB for f f1. EXAMPLE 11. however. equivalent to 1 octave. equivalent to 1 decade. In the future. 506 Chapter 11 BJT and JFET Frequency Response .13. therefore. there is a 3-dB drop from the midband level. Then.14. First.

573° 11.891 0.14. Av(dB) Av and Vo Vi Av(dB) 10 20 10( Vo 1/20) 10( 0.891Vi or Vo is 89. For frequencies f 1 f1 f (11. tan 1 f1 → 90° f For instance.05) 0.f The gain at any frequency can then be determined from the frequency plot in the following manner: Av(dB) but Av(dB) 20 Vo Vi 20 log10 log10 Vo Vi Vo Vi 20 Av(dB) and For example.4° For f f1.01 0. if f 100f1. tan 1 f1 f tan 1 0.15 is determined using the 10x function found on most scientific calculators.15) 0. 1 dB at f 2f1 637 Hz. The gain at this point is From Fig. 10( 3/20) 10 (11.24) 10( 0.1% of Vi at f 637 Hz.707 as expected The quantity 10 0. if Av(dB) Av Vo Vi Av 3 dB. The phase angle of is determined from tan from Eq. tan 1 f1 → 0° f For instance. tan 1 f1 f tan 11 45° For f f1. if f1 100f.22).5 Low-Frequency Analysis—Bode Plot 507 . tan 1 f1 f tan 1(100) 89.25) f1. 11. (11.

In Section 11. The total resistance is now Rs Ri.16.6 LOW-FREQUENCY RESPONSE — BJT AMPLIFIER The analysis of this section will employ the loaded voltage-divider BJT bias configuration. We will now examine the impact of each independently in the order listed. 11. and the cutoff frequency as established in Section 11. CC. If we add the additional 180° phase shift introduced by an amplifier.16 Loaded BJT amplifier with capacitors that affect the low-frequency response. the capacitors Cs. It will simply be necessary to find the appropriate equivalent resistance for the R-C combination. but the results can be applied to any BJT configuration.15 Phase response for the R-C circuit of Figure 11. The magnitude and phase response for an R-C combination have now been established. the phase plot of Fig. VCC RC R1 Cs CC Vo + Rs RL Vi Zi R2 RE CE + Vs – – Figure 11.15.17.7 will be obtained.5 is 508 Chapter 11 BJT and JFET Frequency Response . the general form of the R-C configuration is established by the network of Fig. Figure 11. and CE will determine the low-frequency response. 11.8. 11. 11.6. 11. Cs Since Cs is normally connected between the applied source and the active device. each capacitor of importance in the low-frequency region will be redrawn in an R-C format and the cutoff frequency for each determined to establish the low-frequency response for the BJT amplifier.f A plot of tan 1(f1/f) is provided in Fig. For the network of Fig.

11. that the magnitude of the reactances of CE and CC permits employing a short-circuit equivalent in comparison to the magnitude of the other series impedances. For the network of Fig. that is. assuming that Cs is the only capacitive element controlling the low-frequency response.27).31) Figure 11.19. the ac equivalent network for the input section of Fig. the total series resistance is now Ro RL and the cutoff frequency due to CC is determined by fLC 1 2 (Ro RL)CC (11.26) Rs Cs Ri + Vi System At mid or high frequencies.19. the R-C configuration that determines the low cutoff frequency due to CC appears in Fig.17 Determining the effect of Cs on the low frequency response.28) CC + RL Vo – Thévenin Figure 11. For the network of Fig. the voltage Vi will be 70. The value of Ri for Eq. At fLS. 11.30) C Ignoring the effects of Cs and CE. Using this hypothesis. the ac equivalent network for the output section with Vi 0 V appears in Fig. 11. 11. + ro Vc RC CC RL Ro + Vo . (11. when we analyze the effects of Cs we must make the assumption that CE and CC are performing their designed function or the analysis becomes too unwieldy. 11. From Fig.18 Localized ac equivalent for Cs.16. The voltage Vi will then be Vs related to Vs by – Vi mid RiVs Ri Rs (11.20 Localized ac equivalent for CC with Vi 0 V. The resulting value for Ro in Eq.19 Determining the effect of CC on the low-frequency response. 11. 11.20. the reactance of the capacitor will be sufficiently small + to permit a short-circuit approximation for the element. the output voltage Vo will be 70.27) – Figure 11. R1 R2 re (11.29) System Ro CC Since the coupling capacitor is normally connected between the output of the active device and the applied load. 11.30) is then simply Ro RC ro (11.7% of the value determined by Eq.16. (11.16 will appear as shown in Fig.7% of its midband value at fLC.fLS 1 2 (Rs Ri)Cs f (11.26) is determined by Cs Rs + Vi R2 R2 hie = βre + Vs The voltage Vi applied to the input of the active device can be calculated using the voltage-divider rule: Vi RiVs Ri jXCS (11.18. (11.6 Low-Frequency Response—BJT Amplifier 509 – – – Ri Rs – Figure 11.

the reactance of the capacitor CE will decrease. The effect of CE on the gain is best described in a quantitative manner by recalling that the gain for the configuration of Fig. the effect of one on the other can be ignored with a high degree of accuracy—a fact that will be demonstrated by the printouts to appear in the following example. EXAMPLE 11. . 11. In other words. if the cutoff frequencies established by each capacitor are sufficiently separated. 40 k . the ac equivalent as “seen” by CE appears in Fig. The RC/re. 1k .22. As the frequency increases. keep in mind that Cs. The value of Re is therefore determined by Re RE Rs re (11. 11.23 Network employed to describe the effect of CE on the amplifier gain. RC 4k . the short-circuit equivalents for the capacitors can be inserted. At low frequencies.2 k 100.16 using the following parameters: Cs Rs RL 10 F. there is an interaction between capacitive elements that can affect the resulting low cutoff frequency. CC.” Before continuing. the cutoff frequency due to CE can be determined using the following equation: fLE 1 2 ReCE (11. Although each will affect the gain Av Vo/Vi in a similar frequency range. At fLE the gain result is a maximum or midband gain determined by Av will be 3 dB below the midband value determined with RE “shorted out. and CE will affect only the lowfrequency response.33) E Re RE CE where R s Rs R1 R2. the highest cutoff frequency will essentially determine the lower cutoff frequency for the entire system. Once the level of Re is established. ro CE R1 20 F. 510 Chapter 11 BJT and JFET Frequency Response . 11. CC. or CE will have the greatest impact since it will be the last encountered before the midband level. However. The maximum gain is obviously available where RE is zero ohms. If there are two or more “high” cutoff frequencies. resulting in the minimum gain.9 (a) Determine the lower cutoff frequency for the network of Fig.f CE System Re CE To determine fLE . At the midband frequency level.32) Figure 11. the effect will be to raise the lower cutoff frequency and reduce the resulting bandwidth of the system. 11. (b) Sketch the frequency response using a Bode plot. all of RE appears in the gain equation above.23 is given by Av re RC RE Figure 11. VCC CC R2 1 F 10 k .21 Determining the effect of CE on the low-frequency response. 2. 20 V RE 2k . with the bypass capacitor CE in its “open-circuit” equivalent state. 11. If the frequencies are relatively far apart. reducing the parallel impedance of RE and CE until the resistor RE is effectively “shorted out” by CE.22 Localized ac equivalent of CE.16. the highest low-frequency cutoff determined by Cs. RC Vo Vi RE Figure 11. the network “seen” by CE must be determined as shown in Fig.21. R's + re β For the network of Fig.

32 k 1k Vo Vi Vi Vs 0.32 k 1. Ri fLS R1 R2 1 2 (Rs re 40 k 10 k 1.6 Low-Frequency Response—BJT Amplifier 511 .7 V 2k 26 mV 1.32 k )(10 F) 11.65 mA ) 3.569 ( 90)(0. 11.3 V 2k 15.21 Rs + + Vs Ri Vi Cs – – Figure 11.576 k 1. Vi or so that Vi Vs Ri Ri Avs Rs Vo Vs RiVs Ri Rs 1.576 k and from Fig.76 1576 200 V 50 4V IE 1.24.32 k Ri)Cs fLS (6.24 Determining the effect of Rs on the gain Avs.65 mA 100(15.f Solution (a) Determining re for dc conditions: RE The result is: VB with so that and Midband Gain (100)(2 k ) 200 k 10R2 100 k R2VCC R2 R1 VE RE re re 10 k (20 V) 10 k 40 k 4 V 0.2 k ) 15.76 90 R1 R2 re 40 k 10 k 1.28)(1 k 6.32 k 1.86 Hz 1 1.569) 51.576 k Av The input impedance Vo Vi Zi RC RL re Ri (4 k ) (2.76 1.

67. However.16 with assigned values. 512 Chapter 11 BJT and JFET Frequency Response . The network with its various capacitors appears in Fig. Under Analysis Setup-AC Sweep. we will choose a range of 1 Hz (0 Hz is an invalid entry) to 100 Hz.26 will be obtained. Since our interest will be in the low-frequency range.9 V versus the calculated level of 4 V and that VE is 3. after which the pattern of Fig.25.67 mV. The remaining parameters were removed from the listing to idealize the response to the degree possible. the Start Freq. we return to the original plot.2 V versus the calculated level of 3. and we want to limit to 50 mV for this frequency range. Note that VB is 3.25 Network of Figure 11. The Total Pts. If we choose Plot-XAxis Settings-Linear-OK. Very close when you consider that the approximate model was used. If you want a frequency range starting close to 0 Hz. The output file reveals that the ac voltage across the load at a frequency of 10 kHz is 49. 11. Figure 11.f The results just obtained will now be verified using PSpice Windows. which is very close to the calculated level of 51.3 V. the frequency was set to 10 kHz to establish a frequency in the midband region. The Model Editor was used to set Is to 2E-15A and beta to 100. the computer has selected a log scale for the horizontal axis that extends from 1 Hz to 1 kHz even though we requested a linear scale. 11. Here. resulting in a gain of 49. one must be careful as the program does not recognize 1F as one Farad. CC and CE.21. 11.: will be set at 1000 for a good continuous plot. you would have to choose a frequency such as 0. VBE is very close to the 0. so the remaining frequencies to 1 kHz should be removed with Plot-X-Axis Settings-User Defined-1Hz to 100Hz-OK. will be set to very high values so they are essentially short circuits at any of the frequencies of interest.: at 100 Hz. but the curve of interest is all in the low end—the log axis obviously provided a better plot for our region of interest. The other capacitors. Returning to Plot-X-Axis Settings and choosing Log. The vertical axis also goes to 60 mV.001 Hz or something small enough not to be noticeable on the plot.25. Setting CC and CE to 1 F will remove any affect they will have on the response on the low-frequency region. A simulation followed by Trace-Add-V(RL:1) will result in the desired plot. It must be entered as 1E6uF. A plot of the gain versus frequency will now be obtained with only CS as a determining factor. Our interest only lies in the region of 1 to 100 Hz. and the End Freq.7 V at 0.71 V. we will get a linear plot to 120 Hz. Since the pattern desired is gain versus frequency. A simulation of the network resulted in the dc levels of Fig. The AC Sweep Type will be left on Linear.: at 1 Hz. This is accomplished with Plot-Y-Axis SettingsUser Defined-0V to 50mV-OK. we must use the sequence Analysis-Setup-Analysis Setup-Enable AC Sweep-AC Sweep to obtain the AC Sweep and Noise Analysis dialog box.

at 1 Hz. 513 .707(49.28)(4 k 25. comparing very well to the predicted value of 6.26 Low-frequency response due to CS. CC fLC 1 2 (RC RL)CC 1 2.86 Hz. providing a close match with the calculated level of 25.67 mV) 35. the frequency of the horizontal axis can be read as 6.2 k )(1 F) (6. Following the procedure outlined above will result in the plot of Fig. Note that A2 remains at the lowest level of the plot.27.58 Hz. both CS and CE must be set to 1 Farad as described above. with a cutoff frequency of 25.74 Hz. Figure 11.177-mV level is reached for A1. Note how closely the curve approaches 50 mV in this range. At this point.68 Hz To investigate the effects of CC on the lower cutoff frequency.f Figure 11. 11.12 mV. The cutoff level is determined by 0.68 Hz.27 Low-frequency response due to CC. which can be found by clicking the Toggle cursor icon and moving the intersection up the graph until the 35.

89 ) 2k 1 2 ReCE 1 (6. the start frequency has to be changed to 10 Hz and the final frequency to 1 kHz. Figure 11.17 Hz. 11. the magnitude of the midband gain is 51.30 to form the Bode plot and our 514 Chapter 11 BJT and JFET Frequency Response . 11. 11. 11.28.36 The effect of CE can be examined using PSpice Windows by setting both CS and CC to 1 Farad. For Fig. 11.28)(24.889 k re 15. with a cutoff frequency of 321. since the frequency range is greater. The fact that fLE is significantly higher than fLS or fLC suggests that it will be the predominant factor in determining the low-frequency response for the complete system. To test the accuracy of our hypothesis.30.65 24.76 24. (b) It was mentioned earlier that dB plots are usually normalized by dividing the voltage gain Av by the magnitude of the midband gain. Note the strong similarity with the waveform of Fig. 11.16.29. an asymptote at 6 dB/octave can be drawn as shown in Fig. providing a close match with the calculated value of 327 Hz. In addition. and naturally the ratio Av /Avmid will be 1 in the midband region. with the only visible difference being the higher gain at lower frequencies on Fig. Without question. 11. the plot supports the fact that the highest of the low cutoff frequencies will have the most impact on the low cutoff frequency for the system. The result is the plot of Fig.889 k 100 40 k 10 k 0.35 )(20 F) 106 3058.28. Defining fLE as our lower cutoff frequency f1.76 1k 0.35 327 Hz (8.f CE Rs Re RE 2k fLE R s Rs R1 R2 2k 15. the network is simulated with all the initial values of capacitance level to obtain the results of Fig.28. The result is a 0-dB asymptote in the midband region as shown in Fig.28 Low-frequency response due to CE.21.

11. permitting a sketch of the actual frequency response curve as shown in Fig.30 that the slope has dropped to 12 dB/octave for frequencies less Figure 11. CE. A 6-dB/octave asymptote was drawn at each frequency defined in the analysis above to demonstrate clearly that it is fLE for this network that will determine the 3-dB point.9. 11. 11. the actual curve is 3 dB down from the midband level as defined by the 0.30.6 Low-Frequency Response—BJT Amplifier 515 .30 Low-frequency plot for the network of Example 11. The magnitude plot shows that the slope of the resultant asymptote is the sum of the asymptotes having the same sloping direction in the same frequency interval. It is not until about 24 dB that fLC begins to affect the shape of the envelope.f Figure 11. and CC. Note in Fig. At f1.29 Low-frequency response due to CS. envelope for the actual response.707AVmid level.

Keep in mind as we proceed to the next section that the analysis of this section is not limited to the network of Fig. 11.7 LOW-FREQUENCY RESPONSE — FET AMPLIFIER The analysis of the FET amplifier in the low-frequency region will be quite similar to that of the BJT amplifier of Section 11. 11. 11.31. In addition. Although Fig. 11. appears on the horizontal axis of Fig. 11. than fLC and could drop to 18 dB/octave if the three defined cutoff frequencies of Fig. the magnitude of Av /Avmid is the same as Vo /Avmid since Vo will have the same numerical value as Av.30 were closer together. The plot clearly reveals the change in slope of the asymptote at fLC and how the actual curve follows the envelope created by the Bode plot. which is entered on the bottom of the Add Traces dialog box. 11. a plot of 20 log10 Av /Avmid recalling that if Vs 1 mV. and CS. 11.6. Av /Avmid dB can be obtained by Using PROBE. note the 3-dB drop at f1. The resulting frequencies will then determine whether there is a strong interaction between capacitive elements in determining the overall response and which element will have the greatest impact on establishing the lower cutoff frequency.16. The required Trace Expression. the analysis of the next section will parallel this section as we determine the low cutoff frequencies for the FET amplifier.32 will be used to establish the fundamental equations. CC. There are again three capacitors of primary concern as appearing in the network of Fig. 516 Chapter 11 BJT and JFET Frequency Response . For any transistor configuration it is simply necessary to isolate each R-C combination formed by a capacitive element and determine the break frequencies.32: CG.31 dB plot of the low-frequency response of the BJT amplifier of Fig.f fL C -6dB/octave -20dB/decade -12dB/octave -20dB/decade Figure 11. In fact.25. the procedure and conclusions can be applied to most FET configurations.

11. Ro RD rd (11. and the lower cutoff frequency will be determined primarily by RG and CG. which is also an exact match of Fig. CC For the coupling capacitor between the active device and the load the network of Fig.f Figure 11.34) which is an exact match of Eq. Typically. 11.32 Capacitive elements that affect the low-frequency response of a JFET amplifier.36) 11. 11. RG Rsig. The cutoff frequency determined by CG will then be fLG 1 2 (Rsig Ri)CG (11. (11.37) 1 2 (Ro RL)CC (11.7 Low-Frequency Response—FET Amplifier 517 . Ri RG (11.33 Determining the effect of CG on the low-frequency response. For the network of Fig.35) + Vs Rsig CG System Ri – Figure 11. the ac equivalent network will appear as shown in Fig.32. The resulting cutoff frequency is fLC For the network of Fig. The fact that RG is so large permits a relatively low level of CG while maintaining a low cutoff frequency level for fLG.32.19. 11. CG For the coupling capacitor between the source and the active device.34 will result.33.26). 11.

11. 8mA. 11. the resistance level of importance is defined by Fig. Solution (a) DC Analysis: Plotting the transfer curve of ID IDSS(1 VGS/VP)2 and superimIDRS will result in an intersection at VGSQ 2 posing the curve defined by VGS V and IDQ 2 mA. gm0 gm CG 2IDSS VP gm0 1 2(8 mA) 4V VGSQ VP 4 mS 4 mS 1 2V 4V 2 mS Eq.5 F.f CC System Ro RL System Reg CS Figure 11. . 1M . the resulting value of Req: Req which for rd becomes Req RS 1 gm (11. (b) Sketch the frequency response using a Bode plot.34 Determining the effect of CC on the low-frequency response.01 F) 15.2 k 4.34): 518 fLG 2 (10 k 1 1 M )(0. The cutoff frequency will be defined by fLS 1 2 ReqCS (11.01 F.35. 10 k . RG VP CC 0.10 (a) Determine the lower cutoff frequency for the network of Fig. 11.39) EXAMPLE 11. 20 V RL 2.7 k . 4V RD rd CS 2 F RS VDD 1k .32. In addition. Figure 11. CS For the source capacitor CS.32 using the following parameters: CG Rsig IDSS 0.38) For Fig.40) 1 RS(1 RS gmrd)/(rd RD RL) (11.35 Determining the effect of CS on the low-frequency response.8 Hz Chapter 11 BJT and JFET Frequency Response . (11.

f CC Eq. with the JFET parameters Beta set at 0.32. it defines the low cutoff frequency for the network of Fig. 11.33 )(2 F) Since fLS is the largest of the three cutoff frequencies. The resulting dc levels confirm that VGS is 2 V and place VD at 10.7 k 1k fLS 1 2 mS 1 2.13 Hz Req RS 333. which should be right in the middle 4 V) and VDS 1/2(VDD 20 V).38): 1 2 (333.5mA/V2 and Vto at 4 V (all others set to zero) and the frequency of interest at a midband value of 10 kHz.7 Low-Frequency Response—FET Amplifier 519 .36 Low-frequency response for the JFET configuration of Example 11.2 k ) (2 mS)(1. Using PSpice Windows. 11.10.36.37. 11. of the linear active region since VGS 1/2(VD The 0-V levels clearly reveal that the capacitors have isolated the transistor for the dc biasing.993 mV across the load for a gain of 2. 11.2 k )(0.33 238.499 k ) 3 Using the midband gain to normalize the response for the network of Fig.7 k 2. the network will appear as shown in Fig.60 V. The ac response results in an ac level of 2. (b) The midband gain of the system is determined by Avmid Vo Vi gm(RD RL) (2 mS)(4.993. 11. which is essentially equal to the calculated gain of 3.36): CS fLC 1 gm 2 (4.5 F) 1k 0.5 k 46.73 Hz Eq. (11.32 will result in the frequency plot of Fig. Figure 11. (11.

The large capacitors of the network that controlled the low-frequency response have all been replaced by their short-circuit equivalent due to their very low reactance levels.f Figure 11.: 10 kHz will setup Simulation-Trace-Add-Trace Expression: DB (V(RL:1)/2.8 MILLER EFFECT CAPACITANCE In the high-frequency region.10. which will result in the plot of Fig. the capacitive elements of importance are the interelectrode (between terminals) capacitances internal to the active device and the wiring capacitance between leads of the network. Start Freq. Returning to Analysis and choosing Automatically run Probe after simulation followed by Setup-AC Sweep-Decade-Pts/Decade 1000. 11. and End Freq. Figure 11.38 dB response for the low-frequency region in the network of Example 11.10.38. with a low cutoff frequency of 227. 520 Chapter 11 BJT and JFET Frequency Response .993mV)-OK.37 Schematic network for Example 11.5 Hz primarily determined by the source capacitance. 11.: 10Hz.

40 Demonstrating the impact of the Miller effect capacitance. this “feedback” capacitance is defined by Cf. The result is an equivalent input impedance to the amplifier of Fig.40. Applying Kirchhoff’s current law gives Ii Using Ohm’s law yields Ii and I2 Vi Vo XCf Vi . we obtain Vi Zi and but 1 Zi 1 XCf Av Vi Ri 1 Ri (1 CM and 1 Zi 1 Ri 1 XCM (1 Av)Vi XCf Av) XCM 1 XCf /(1 1 Av)Cf establishing the equivalent network of Fig. 11.39.8 Miller Effect Capacitance 521 .f For inverting amplifiers (phase shift of 180° between input and output resulting in a negative value for Av). Figure 11. Zi Vi I1 AvVi XCf Vi Ri (1 Av)Vi XCf I1 I2 Substituting. In Fig. the input and output capacitance is increased by a capacitance level sensitive to the interelectrode capacitance between the input and output terminals of the device and the gain of the amplifier. 11. with the addition of a feedback capacitor magnified by the Ii + Vi Zi Ri CM = (1 − Aυ ) Cf – Figure 11. 11. 11.39 that includes the same Ri that we have dealt with in previous chapters.39 Network employed in the derivation of an equation for the Miller input capacitance.

However. In Fig. The reason for the constraint that the amplifier be of the inverting variety is now more apparent when one examines Eq.41). 11. The Miller effect will also increase the level of output capacitance.41) is that at high frequencies the gain Av will be a function of the level of CMi. (11. the Miller effect input capacitance is defined by CM i (1 Av)Cf (11. In general. Applying Kirchhoff’s current law will result in Io with I1 Vo Ro and I1 I2 I2 Vo Vi XCf The resistance Ro is usually sufficiently large to permit ignoring the first term of the equation compared to the second term and assuming that Io Substituting Vi Vo /Av from Av Io Io Vo Vo Vo Vi XCf Vo /Vi will result in Vo/Av XCf 1/Av XCf Vo(1 1/Av) XCf and 1 Figure 11. Any interelectrode capacitance at the input terminals to the amplifier will simply be added in parallel with the elements of Fig.41 Network employed in the derivation of an equation for the Miller output capacitance. which must also be considered when the high-frequency cutoff is determined. A positive value for Av would result in a negative capacitance (for Av 1).41) This shows us that: For any inverting amplifier. In general.40. using the midband value will result in the highest level of CMi and the worst-case scenario. The dilemma of an equation such as Eq. (11.41).41. therefore.f gain of the amplifier. therefore. 11. the midband value is typically employed for Av in Eq. the input capacitance will be increased by a Miller effect capacitance sensitive to the gain of the amplifier and the interelectrode capacitance connected between the input and output terminals of the active device. 522 Chapter 11 BJT and JFET Frequency Response . since the maximum gain is the midband value. (11. the parameters of importance to determine the output Miller effect are in place.

The derivation leading to the corner frequency for this RC configuration follows along similar lines to that encountered for the low-frequency region. 11. 11. 11. The high-frequency equivalent model for the network of Fig. (11. CC.42. the RC network of concern has the configuration appearing in Fig. Note the absence of the capacitors Cs. (11. Eq. 11.44. the various parasitic capacitances (Cbe. which are all assumed to be in the short-circuit state at these frequencies. 1 which results in a magnitude plot such as shown in Fig. (11.42b) Av 1 CMo Examples in the use of Eq.or Vo Io XCf 1 1/Av 1 Cf (1 1/Av) 1 CMo f resulting in the following equation for the Miller output capacitance: CMo For the usual situation where Av 1 1 C Av f (11.43 that drops off at 6 dB/octave with increasing frequency. Cce) of the transistor Figure 11.42a) 1. Note that f2 is in the denominator of the frequency ratio rather than the numerator as occurred for f1 in Eq.42 R-C combination that will define a high cutoff frequency. (11. resulting in a shorting effect across the output and a decrease in gain. At increasing frequencies.42) will appear in the next two sections as we investigate the high-frequency responses of BJT and FET amplifiers.43). 11. Cbc. In Fig.21).9 HIGH-FREQUENCY RESPONSE — BJT AMPLIFIER At the high-frequency end. the reactance XC will decrease in magnitude. CWo) introduced during construction.45.44 appears in Fig. there are two factors that will define the 3-dB point: the network capacitance (parasitic and introduced) and the frequency dependence of hfe( ).42a) reduces to Cf (11. and CE.43) Figure 11. have been included with the wiring capacitances (CWi. The capacitance Ci includes 11. The most significant difference is in the general form of Av appearing below: Av 1 j( f/f2) (11.9 High-Frequency Response—BJT Amplifier 523 .43 Asymptotic plot as defined by Eq. 11. Network Parameters In the high-frequency region.

In fact. 11.45.45 High-frequency ac equivalent model for the network of Fig. 11. the capacitance Cbe is the largest of the parasitic capacitances. In general.16 with the capacitors that affect the high-frequency response.46 Thévenin circuits for the input and output networks of the network of Fig.45 will result in the configurations of Fig. and the Miller capacitance CMi. the input wiring capacitance CWi. . and the output Miller capacitance CMo.f VCC RC R1 Cbc CC Cs + Rs Cce CWo RL + – Rs Vi R2 CWi Cbe RE CE Ci = CWi + Cbe + CMi Ib Th1 + Vs R1 R2 Figure 11.44. with Cce the smallest. most specification sheets simply provide the levels of Cbe and Cbc and do not include Cce unless it will affect the response of a particular type of transistor in a specific area of application. The capacitance Co includes the output wiring capacitance CWo. the 3-dB frequency is defined by fHi 1 2 RTh1Ci (11. the parasitic capacitance Cce.44) RTh = Rs R1 R2 Ri 1 + ETh 1 (a) 524 Chapter 11 BJT and JFET Frequency Response – – Co = CWo + Cce + CMo Vo Th2 Ci Ri Figure 11. For the input network.44 Network of Fig. 11. Determining the Thévenin equivalent circuit for the input and output networks of Fig. 11. the transition capacitance Cbe. 11.46. Vs β Ib ro RC RL Co – RTh = RC RL ro 2 + Ci ETh 2 Co – (b) Figure 11.

the lowest frequency would be the determining factor. For the output network. the capacitive reactance of Co will decrease and consequently reduce the total impedance of the output parallel branches of Fig. The various parameters warrant a moment of explanation. If the parasitic capacitors were the only elements to determine the high cutoff frequency. However.47) (11. The only undefined quantity. 11. The resistance rbb includes the base contact. 11. The net result is that Vo will also decline toward zero as the reactance XC becomes smaller. fHo with and Co RTh2 CWo 1 2 RTh2Co RC RL ro Cce CMo (11.9 High-Frequency Response—BJT Amplifier 525 . hfe (or ) Variation The variation of hfe (or ) with frequency will approach.48) (11.f with and Ci CWi RTh1 Cbe CMi Rs R1 R2 Ri CWi Cbe (1 Av)Cbc (11. 11.46) At very high frequencies.45. and Ci in Fig. the decrease in hfe (or ) with frequency must also be considered as to whether its break frequency is lower than fHi or fHo. base bulk. Ri. with some degree of accuracy. The first is due to the actual connection to the base.47. 11. 11.50) The use of hfe rather than in some of this descriptive material is due primarily to the fact that manufacturers typically use the hybrid parameters when covering this issue in their specification sheets.45. the following relationship: hfe hfemid 1 j(f/f ) (11. the effect of Ci is to reduce the total impedance of the parallel combination of R1. and so on. is determined by a set of parameters employed in the hybrid or Giacoletto model frequently applied to best represent the transistor in the high-frequency region. and a gain for the system. a reduction in Ib. The second includes the resistance from the external terminal to the active region of rb'c B Ib rbb' 1 rb'e = g b'e b' I'b Cb'e Cb'c 1 hoe gm Vb'e = gm rb'e I'b ≅ hfe C rce = I' mid b E E Figure 11. and base spreading resistance.45) (11.43. f . R2.49) At very high frequencies. The frequencies fHi and fHo will each define a 6-dB/octave asymptote such as depicted in Fig. It appears in Fig.47 Giacoletto (or hybrid ) high-frequency transistor small-signal ac equivalent circuit. The result is a reduced level of voltage across Ci.

48. f (sometimes appearing as fhfe ) gb e 2 (Cb e Cb c) hfemid gb e. f f (1 ) (11. revealing that hfe will drop off from its midband value with a 6-dB/octave slope as shown in Fig.f the transistors. while the last is the actual resistance within the active base region. For this very reason. 11. A more detailed explanation of the frequency dependence of each can be found in a number of readily available texts.51) or since the hybrid parameter hfe is related to gb e through gm f 1 gm Cb c) hfemid 2 (Cb e Taking it a step further.50): f 1 2 midre(Cbe Cbc) (11. The resistances rb e. common-base high-frequency parameters rather than common-emitter parameters are often specified for a transistor—especially those designed specifically to operate in the high-frequency regions. Note the small change in h f b for the chosen frequency range.52) (11.53) Equation (11. (11. gm hfemid gb e hfemid 1 rb e hfemid hie mid midre 1 re and using the approximations Cb e Cbe and Cb c Cbc will result in the following form for Eq.53) clearly reveals that since re is a function of the network design: f is a function of the bias conditions. The basic format of Eq. and rb c are the resistances between the indicated terminals when the device is in the active region. Recall also the absence of the Miller effect capacitance due to the noninverting characteristics of the common-base configuration. (11.54) A quantity called the gain–bandwidth product is defined for the transistor by the condition hfemid 1 1 j( f/f ) 526 Chapter 11 BJT and JFET Frequency Response .50) is exactly the same as Eq. rce. The following equation permits a direct conversion for determining f if f and are specified. The same figure has a plot of h f b (or ) versus frequency. In terms of these parameters. (11.43) if we extract the multiplying factor hfemid. revealing that the common-base configuration displays improved high-frequency characteristics over the common-emitter configuration. The same is true for the capacitances Cb c and Cb e. although the former is a transition capacitance while the latter is a diffusion capacitance. (11.

The magnitude of hfe at the defined condition point ( fT f ) is given by hfemid 1 ( ( fT/f )2 BW) hfemid fT/f 1 so that or fT hfemid f fT (gain–bandwidth product) (11.0 0. 11.48.0 MHz ve slo pe Midband value for hfb hfb fT 1 kMHz fh . hfb 40 dB Midband value for hfe 1.56) mid f with f fT mid (11. ( fh ) fe 10.48 hfe and hfb versus frequency in the high-frequency region.55) (11. (11. (11.0 MHz fβ .55) gives fT 1 mid 2 midre(Cbe Cbc) (11.57) Substituting Eq.1 MHz 1. ( f α ) fb 10 kMHz Figure 11.707 −3 dB 30 dB hfe 20 dB mid −6 dB /o cta 10 dB hfe = 1 0 dB −3 dB −10 dB −20 dB 0.9 High-Frequency Response—BJT Amplifier 527 .0 MHz 5fβ 100.58) and fT 1 2 re(Cbe Cbc) 11.53) for f in Eq.f hfe hfe hfe . so that hfe dB 20 log10 hfemid 1 j( f/f ) 20 log10 1 0 dB The frequency at which hfe dB 0 dB is clearly indicated by fT in Fig.

CWo 8 pF 40 k .531 k with CWi 6 pF 406 pF fHi 1 2 RTh1Ci 738.04 pF fHo 1 2 RTh2Co 1 2 (1. 11.52 MHz) 252 MHz 528 Chapter 11 BJT and JFET Frequency Response .52 MHz fT mid f (100)(2.531 k )(406 pF) Cbe (1 Av)Cbe [1 ( 90)]4 pF Avmid(amplifier) 1k 40 k 10 k 90 1.2 k CMo 8 pF 1. Cbc 4 pF. R1 10 F. Cce 1 pF. (d) Obtain a PROBE response for the full frequency spectrum and compare with the results of part (c).76 )(40 pF) 2 (100)(15.24 kHz RTh2 Co RC RL CWo 4k Cce 2. (b) Find f and fT. CC 100. RL 2. RE 20 F 20 V 2 k .419 k )(13. ro with the addition of Cbe 36 pF. Solution (a) From Example 11.32 k .and high-frequency regions using the results of Example 11.9: Ri and RTh1 Ci 1.53) gives f 2 1 re(Cbe mid Cbc) 1 )(36 pF 4 pF) 1 2 (100)(15.2 k (a) Determine fHi and fHo.32 k 36 pF 13.76 2.9. RC 4 k .11 For the network of Fig. CWi 6 pF. Rs R1 R2 Ri 0.f EXAMPLE 11. Rs Cs 1 k . R2 1 F.9 and the results of parts (a) and (b). (11.04 pF) 8.44 with the same parameters as in Example 11.6 MHz (b) Applying Eq. that is. (c) Sketch the frequency response for the low. VCC 10 k .419 k 1 pF 1 1 4 pF 90 1 2 (0. CE .

11. In fact. 11.49. the bandwidth will be less than that defined solely by fHi. In any event.9 High-Frequency Response—BJT Amplifier 529 .25 with parasitic capacitances in place.50 Network of Figure 11. Both f and fHo will lower the upper cutoff frequency below the level determined by fHi. therefore. for the parameters of this network the upper cutoff frequency will be relatively close to 600 kHz. (d) In order to obtain a PSpice analysis for the full frequency range. 11. Aυ Aυ mid dB 1 0 –3 –5 fL 10 s fL C 100 fL E 1 kHz 10 kHz 100 kHz fHi 1 MHz fβ 10 MHz fHo 100 MHz f (log scale) f1 BW f2 −6 dB/octave –10 –15 +20 dB/decade –20 −12 dB/octave –25 Figure 11. the parasitic capacitances have to be added to the network as shown in Fig.f (c) See Fig.44. 11. f is closer to fHi and therefore will have a greater impact than fHo.50.49 Full frequency response for the network of Fig. Figure 11. the lowest of the upper-cutoff frequencies defines a maximum possible bandwidth for a system. In general.

51 Full frequency response for the network of Fig. 11.50. 530 Chapter 11 BJT and JFET Frequency Response . ranging from 0. The vertical scale was changed from 60 to 0 dB to 30 to 0 dB to highlight the area of interest using the Y-Axis Settings. the PSpice analysis has been a welcome verification of the hand-written approach. At frequencies where Co approaches its shortcircuit equivalent. The cutoff frequencies defined by the input and output circuits can be obtained by first finding the Thévenin equivalent circuits for each section as shown in Fig. there are interelectrode and wiring capacitances that will determine the high-frequency characteristics of the amplifier. Figure 11.53.10 HIGH-FREQUENCY RESPONSE — FET AMPLIFIER The analysis of the high-frequency response of the FET amplifier will proceed in a very similar manner to that encountered for the BJT amplifier. 11. Even though fHo is more than a decade higher than fHi. At high frequencies. however. Since the network of Fig. while the capacitance Cds is usually quite a bit smaller.54. The low cutoff frequency of 324 Hz is as determined primarily by fLE. 11. Ci will approach a short-circuit equivalent and Vgs will drop in value and reduce the overall gain. The capacitors Cgs and Cgd typically vary from 1 to 10 pF. For the input circuit.52 is an inverting amplifier. 11. In total. 11. the parallel output voltage Vo will drop in magnitude. 11.1 to 1 pF. a Miller effect capacitance will appear in the high-frequency ac equivalent network appearing in Fig.f An Analysis will result in the plot of Fig. 11. As shown in Fig. and the high cutoff frequency is near 667kHz. it will have an impact on the high cutoff frequency.52.51 using the Trace Expression appearing at the bottom of the plot.

62) fHo 1 2 RTh2Co (11. fHi 1 2 RTh1Ci (11.52.60) with Ci CWi Cgs CMi (11. Rsig + + Vs RG Th1 Ci Vgs gm Vgs rd RD RL Th2 Co Vo – – Figure 11.59) and RTh1 Rsig RG (11. CM i (1 Av)Cgd (11.10 High-Frequency Response—FET Amplifier 531 .52 Capacitive elements that affect the high frequency response of a JFET amplifier.f VDD RD CC Cgd Vo Cds + Vs Rsig CG RG CW i Cgs RS CS CW o RL – Figure 11. 11. 11.54 The Thévenin equivalent circuits for the (a) input circuit and (b) output circuit.53 High-frequency ac equivalent circuit for Fig.61) and and for the output circuit.63) Figure 11.

10.17 pF) 11.f with and Co RTh2 CWo RD RL rd Cds CMo (11. CS 2 F 1k .17 pF 2. This is typically the case due to the smaller value of Cds and the resistance levels encountered in the output circuit. CC RD 4 V. 11. 11.64) and CMo 1 1 C Av gd (11. CWi RS . Av)Cgd 3)2 pF 9.2 k 8 mA.5 pF 1 1 2 pF 3 9. RL 2.9 k )(17 pF) RTh2 RD RL 4.9 k 1 2 (1.01 F. Cgs Cds CWo 6 pF (b) Review a PROBE response for the full frequency range and note whether it supports the conclusions of Example 11. 20 V with the addition of 2 pF. RG 1M .12 (a) Determine the high cutoff frequencies for the network of Fig.52 using the same parameters as Example 11. 4. 0.10: CG Rsig 10 k .10 and the calculations above. 532 Chapter 11 BJT and JFET Frequency Response .5 k )(9.7 k .7 k 1.5 F. (b) Using PSpice Windows.55.65) EXAMPLE 11. Av Ci CWi 5 pF 9 pF 17 pF fHi 1 2 RTh1Ci 1 2 (9. the schematic for the network will appear as shown in Fig.57 MHz The results above clearly indicate that the input capacitance with its Miller effect capacitance will determine the upper cutoff frequency.67 kHz Cgs 4 pF 8 pF (1 (1 1M 3. rd 0.5 pF. Solution (a) RTh1 Rsig RG 10 k From Example 11.2 k 945. VDD 5 pF. IDSS Cgd 0. VP 4 pF.5 k Co fHo CWo Cds CMo 6 pF 0.

we find the lower and upper cutoff frequencies to be 225 Hz and 921 kHz.f Figure 11.56 without computer methods for a network as complicated as Fig.52 with assigned values. the Trace Expression is entered as DB(V(RL:1)/2. providing a nice match with the calculated values. 11. Often.56 Frequency response for the network of Example 11. and the plot of Fig. consider how much time it must have taken to obtain a plot such as in Fig.55 Network of Figure 11. Figure 11.10 High-Frequency Response—FET amplifier 533 .: at 10 MHz.12. and boring series of calculations. Under the Add Traces dialog box. lengthy.55. 11.56 is obtained. 11.: at 10 Hz. Under Analysis. 11. Just for a moment. Using the cursor. and End Freq. the AC Sweep is set to Decade with Pts/Decade at 1000. Start Freq. we forget how computer systems have helped us through some painstaking.993mV). respectively.

11 MULTISTAGE FREQUENCY EFFECTS For a second transistor stage connected directly to the output of a first stage. At f1 and f2. (overall) Av1 Av2 Av3 low low low Avn low Figure 11. A 18-dB/octave or 60-dB/decade slope will result for a three-stage system of identical stages with the indicated reduction in bandwidth (f 1 and f 2 ). the drop-off rate in the high. 534 Chapter 11 BJT and JFET Frequency Response . For a single stage. therefore. one poorly designed stage can offset an otherwise well-designed cascaded system. In each case. the content of this chapter should provide a firm foundation for any future analysis of frequency effects. Further. parasitic capacitance (Cbe). In the high-frequency region. The 3-dB point has shifted to f 1 and f 2 as indicated. the cutoff frequencies are f1 and f2 as indicated. there will be a significant change in the overall frequency response. there will be additional low-frequency cutoff levels due to the second stage that will further reduce the overall gain of the system in this region. with a resulting drop in the bandwidth. Assuming identical stages.and low-frequency regions has increased to 12 dB/octave or 40 dB/decade. For each additional stage.57 Effect of an increased number of stages on the cutoff frequencies and the bandwidth.f Even though the analysis of the past few sections has been limited to two configurations. the upper cutoff frequency will be determined primarily by that stage having the lowest cutoff frequency. There is a great deal more literature on the analysis of single-stage amplifiers that goes beyond the coverage of this chapter. an equation for each band frequency as a function of the number of stages (n) can be determined in the following manner: For the lowfrequency region. therefore. Obviously. the upper and lower cutoff frequencies of each of the cascaded stages are identical. and Miller capacitance (CMi) of the following stage.57. However. the output capacitance Co must now include the wiring capacitance (CW1). For two identical stages in cascade. the decibel drop is now 6 dB rather than the defined band frequency gain level of 3 dB. Keep in mind that the Miller capacitance is limited to inverting amplifiers and that f is significantly greater than f if the common-base configuration is encountered. the exposure to the general procedure for determining the cutoff frequencies should support the analysis of any other transistor configuration. 11. 11. The effect of increasing the number of identical stages can be clearly demonstrated by considering the situations indicated in Fig. The low-frequency cutoff is primarily determined by that stage having the highest low-frequency cutoff frequency. Avlow.

11. if f2 f . For instance. it can be shown that for the high-frequency region. f 2 0. The magnitude of this factor for various values of n is listed below. For the RC-coupled transistor amplifier. the number of stages must be increased by a factor of 2 when determining f 2 due to the increased number of factors 1/(1 jf/fx).67) Note the presence of the same factor 21/n 1 in each equation. For a two-stage system the same gain can be obtained by having two stages with a gain of 10 since (10 10 100). f2 ( 21/n 1)f2 (11.000 due to the lower gain requirement and fixed gain–bandwidth product of 106. The bandwidth of each stage would then increase by a factor of 10 to 100.64 0.51f2 or approximately 1 the value of a single stage with f 1 (1/0.66) In a similar manner.43 0. A decrease in bandwidth is not always associated with an increase in the number of stages if the midband gain can remain fixed and independent of the number of stages.64)f1 1. if a single-stage amplifier produces a gain of 100 with a bandwidth of 10. (overall) or Av1 Avmid low n (1 1 jf1/f )n Setting the magnitude of this result equal to 1/ 1 or so that and 1 f1 f1 2 1/2 n 2 ( 3 dB level) results in 1 2 f1 f1 2 2 n 1/2 1 ( f1/f 1)2]n 1 f1 f1 f1 f1 2 n (2)1/2 1 1 2 21/n f1 with the result that f1 (11. while f 1 (1/0. For n 3. n 2 3 4 5 21/n 0.f but since each stage is identical.11 Multistage Frequency Effects 535 . the resulting gain–bandwidth product is 102 104 106. and (Av1 )n low Avlow.56f1. Av1 Avlow (overall) Avmid low Av2 low etc. the design must be such as to permit the increased bandwidth and establish the lower gain level.64f2 or 64% of the value obtained for a single stage. or if they are close enough in magnitude for both to affect the upper 3-dB frequency. consider that the upper cutoff frequency f 2 0.51 0.96f1 or approxi2 mately twice the single-stage value.39 1 For n 2.51)f1 1. Of course.000 Hz.

The first term of the series is called the fundamental term and in this case has the same frequency. The Fourier series expansion for the square wave of Fig. The summation of the terms of the series will result in the original waveform. Figure 11.59a clearly results in a waveform that is beginning to take on the appearance of a square wave. In other words. fs. The next term has a frequency equal to three times the fundamental and is referred to as the third harmonic. as the square wave.12 SQUARE-WAVE TESTING A sense for the frequency response of an amplifier can be determined experimentally by applying a square-wave signal to the amplifier and noting the output response. The use of square-wave testing is significantly less time-consuming than applying a series of sinusoidal signals at different frequencies and magnitudes to test the frequency response of the amplifier.58 is 4 v Vm sin 2 fst 1 sin 2 (3fs)t 3 1 sin 2 (5fs)t 5 1 sin 2 (7fs)t 7 1 sin 2 (nfs)t) n (11. Its magnitude is onethird the magnitude of the fundamental term. it can be reproduced by a series of sinusoidal terms of different frequencies and magnitudes. even though a waveform may not be sinusoidal.59b takes us a step closer to the waveform of Fig. 536 Chapter 11 BJT and JFET Frequency Response . It is therefore reasonable to assume that if the application of a square wave of a particular frequency results in a nice clean square wave at the output.59 Harmonic content of a square wave. the fundamental term through the ninth harmonic are the 9 major contributors to the Fourier series expansion of the square-wave function. 11. Since the ninth harmonic has a magnitude greater than 10% of the fundamental term [ 1 (100%) 11.58 Square wave. the summation of just the fundamental term and the third harmonic in Fig. and the magnitude decreases with each higher harmonic.59 demonstrates how the summation of terms of a Fourier series can result in a nonsinusoidal waveform. 11. 11.f 11. The shape of the output waveform will reveal whether the high or low frequencies are being properly amplified. However. The reason for choosing a square-wave signal for the testing process is best described by examining the Fourier series expansion of a square wave composed of a series of sinusoidal components of different magnitudes and frequencies. then the fundamental Figure 11.58 would require an infinite number of terms. The frequencies of the succeeding terms are odd multiples of the fundamental term. The generation of the square wave of Fig.58.68) 1 sin 2 (9fs)t 9 Figure 11. 11. Including the fifth and seventh harmonics as in Fig.1%]. 11.

60 (a) Poor low frequency response.12 Square-Wave Testing 537 . The actual high cutoff frequency (or BW) can be determined from the output waveform by carefully measuring the rise time defined between 10% and 90% of the peak value. v v 0 T 2 T 3T 2 2T t 0 T 2 T 3T 2 2T t (a) (b) v v 0 T 2 T 3T 2 2T t 0 T 2 T 3T 2 2T t (c) (d) Figure 11.61 Defining the rise time and tilt of a square wave response. the frequency of the applied signal should be at least 20 kHz/9 2. 11. 11. If the response of an amplifier to an applied square wave is an undistorted replica of the input.61.22 kHz. 11. 11. the equation also provides an indication of the BW of the amplifier. as shown in Fig. Figure 11. the low frequencies are not being amplified properly and the low cutoff frequency has to be investigated. the high-frequency components are not receiving sufficient amplification and the high cutoff frequency (or BW) has to be reviewed. if an audio amplifier with a bandwidth of 20 kHz (audio range is from 20 Hz to 20 kHz) is to be tested.f through the ninth harmonic are being amplified without visual distortion by the amplifier. (c) poor high-frequency response. (b) very poor low-frequency response. If the waveform has the appearance of Fig. and since BW fHi fLo fHi.60a and b. If the response is as shown in Fig. Substituting into the following equation will provide the upper cutoff frequency. (d) very poor high-frequency response. For instance. the frequency response (or BW) of the amplifier is obviously sufficient for the applied frequency.60c.

72) EXAMPLE 11.61 and substituting into one of the following equations: V V 100% (11. 11.2 (5 kHz) 318.71) The low cutoff frequency is then determined from fLo P fs (11.31 Hz 11.62 Example 11. Solution (a) vi 4 mV sin 2 (5 103)t 1 sin 2 (15 3 103)t 1 sin 2 (25 5 103)t 1 sin 2 (35 103)t 7 Figure 11. The complete frequency response of a single-stage or multistage system can be determined in a relatively short period of time to verify theoretical calculations or provide an immediate indication of the low and high cutoff frequencies of the system.35 tr V V P fs V 2 s 0.13 1 sin 2 (45 9 103)t (b) tr BW (c) P fLo 18 s 0. 11. 5-kHz square wave to an amplifier resulted in the output waveform of Fig. (b) Determine the bandwidth of the amplifier.13 PSPICE WINDOWS The computer analysis of this chapter was integrated into the chapter for emphasis and a clear demonstration of the power of the PSpice software package. (a) Write the Fourier series expansion for the square wave through the ninth harmonic. 538 Chapter 11 BJT and JFET Frequency Response .70) % tilt P% V V V V tilt P (decimal form) (11.35 16 s 16 s 21.69) The low cutoff frequency can be determined from the output response by carefully measuring the tilt of Fig.62.875 Hz 4.2 50 mV 40 mV 50 mV 0.f BW fHi 0.35 tr (11.4fs 0.13 The application of a 1-mV. The exercises in the chapter will provide an opportunity to apply the PSpice software package to a variety of networks. (c) Calculate the low cutoff frequency.

(a) Determine the common logarithm of the following numbers: 103. 4.7) and compare with 10 log10 0.2 103. What is the * 8.6) and compare with 20 log10 5. 3.4 General Frequency Considerations 10. 25 V are made. Determine: (a) 20 log10 480 using Eq. (a) The total decibel gain of a three-stage system is 120 dB. If the applied ac power to a system is 5 W at 100 mV and the output power is 48 W. Pi 5 mW. (11. Determine the decibel gain of each stage if the second stage has twice the decibel gain of the first and the third has 2.63. (c) Compare the solutions of parts (a) and (b). 11. Pi 20 W. (c) log10(40)(0. (b) Determine the voltage gain of each stage. Pi 5 W. and 0. (b) Determine the natural logarithm of the number of part (a) using Eq. (a) Determine the common logarithm of the number 2. Given the characteristics of Fig. (b) The normalized dB gain (and determine the bandwidth and cutoff frequencies). (c) Determine the natural logarithm of the number of part (a) using natural logarithms and compare with the solution of part (b). PROBLEMS 2.4). (11. 50. (11.f § 11.2 Logarithms 1.7 times the decibel gain of the first. Calculate the power gain in decibels for each of the following cases. (11. Determine GdBm for an output power level of 25 W. § 11. (b) Po 100 mW.05.63 Problem 10 Problems 539 . 6. sketch: (a) The normalized gain. (c) Po 100 W. 7. (a) Po 100 W. 5. (b) Determine the natural logarithm of the same numbers appearing in part (a). determine: (a) The power gain in decibels.707. (b) The voltage gain in decibels if the output impedance is 40 k . Input and output voltage measurements of Vi voltage gain in decibels? 10 mV and Vo 100 V. Figure 11. * 9.125) using Eq. (c) The input impedance. (d) The output voltage. Two voltage measurements made across the same resistance are V1 25 V and V2 Calculate the power gain in decibels of the second reading over the first reading.8) and compare with log10 5. (b) 10 log10 210 using Eq.

fLC. (b) Determine the phase angle at f 100 Hz. and the resulting cutoff frequency? For (a) (b) (c) (d) (e) (f) (g) (h) 40 k . (d) Sketch the frequency response of for the same frequency spectrum of part (b) and compare results. Find AvSmid Vo /Vs. Sketch the asymptotes of the Bode plot defined by the cutoff frequencies of part (e). 1 kHz. 1 kHz. (d) Sketch the asymptotes and locate the 3-dB point. Figure 11.2 kΩ + Vo – – 12. 5 kHz. Use a log scale. (c) Determine the break frequency.6 Low-Frequency Response — BJT Amplifier 14. 5 kHz. 22. determine Vo /Vi at 100 Hz. What is the effect on Avmid .5 Low-Frequency Analysis—Bode Plot 0. (c) Determine the break frequency. and 10 kHz. and 33 540 Chapter 11 BJT and JFET Frequency Response . fLC . + Vi 1. 2 kHz. and plot the resulting curve for the frequency range of 100 Hz to 10 kHz. 11. 15.65: Determine re. (a) (b) (c) (d) What frequency is 1 octave above 5 kHz? What frequency is 1 decade below 10 kHz? What frequency is 2 octaves below 20 kHz? What frequency is 2 decades above 1 kHz? Figure 11. (b) Using the results of part (a). and plot the resulting curve for the frequency range of 100 Hz to 10 kHz. For the network of Fig.64: (a) Determine the mathematical expression for the angle by which Vo leads Vi. (e) Sketch the frequency response for Vo /Vi and compare to the results of part (b). 11. 12. 11.f § 11.9 with ro fLE.65 Problems 15.64: (a) Determine the mathematical expression for the magnitude of the ratio Vo /Vi. the network of Fig. Repeat the analysis of Example 11. 2 kHz. Sketch the low-frequency response for the amplifier using the results of part (f). Find Avmid Vo /Vi. § 11. For the network of Fig. Calculate Zi.64 Problems 11. Determine the low cutoff frequency. and 10 kHz. fLS . and 32 13.068 µ F 11. Determine fLS. and fLE.

Repeat Problem 15 for the emitter-stabilized network of Fig. 14 V 120 kΩ 1 kΩ Vi 0. Repeat Problem 15 for the common-base configuration of Fig. 11.67. Figure 11.2 kΩ 8.f * 16. 11. Repeat Problem 15 for the emitter-follower network of Fig.2 kΩ Figure 11.68 Problems 18. Keep in mind that the common-base configuration is a noninverting network when you consider the Miller effect.66. 25.68.1 µ F + Vs 2. and 34 – Problems 541 .67 Problems 17 and 24 * 18.1 µF Zi 30 kΩ CW = 8 pF i CWo = 10 pF Cbc = 20 pF Cbe = 30 pF Cce = 12 pF β = 100 0. 11.66 Problems 16 and 23 * 17. Figure 11.

Assuming that Cb e Cbe and Cb c Cbc. BJT and JFET Frequency Response 542 Chapter 11 . 11. (g) Determine the low cutoff frequency. Does it have an impact of any consequence on the results? If so. (h) Sketch the asymptotes of the Bode plot defined by part (f).70 Problems 21 and 27 § 11. (f) Determine fLG. (i) Sketch the low-frequency response for the amplifier using the results of part (f). (e) Calculate Avs Vo /Vs.69: (a) Determine VGSQ and IDQ. Sketch the frequency response for the high-frequency region using a Bode plot and determine the cutoff frequency. (c) Calculate the midband gain of Av Vo /Vi. fLC.f § 11. For the network of Fig.9 High-Frequency Response — BJT Amplifier 22. 11. 11. 26. and fLS. and 35 * 20. What effect did the voltage-divider configuration have on the input impedance and the gain Avs compared to the biasing arrangement of Fig. Repeat the analysis of Problem 19 for the network of Fig. Repeat the analysis of Problem 19 with rd 100 k . (b) Find gm0 and gm.65: Determine fHi and fHo.69 Problems 19. find f and fT.70. (d) Determine Zi. 11. 20. For (a) (b) (c) the network of Fig. Figure 11.7 Low-Frequency Response — FET Amplifier 19. which elements? 21.69? * Figure 11.

Repeat the analysis of Problem 22 for the network of Fig.65. 11. 11. 11. Determine fHi and fHo. 25. What § 11. A four-stage amplifier has a lower 3-dB frequency for an individual stage of f1 is the value of f 1 for this full amplifier? 40 Hz. For (a) (b) (c) (d) * the network of Fig. 24. 11.69. 11. each having a gain of 20. (a) Write the Fourier series expansion for the square wave through the ninth harmonic.13 PSpice Windows 32.69: Determine gm0 and gm. Using PSpice Windows. (b) Determine the bandwidth of the amplifier to the accuracy available by the waveform of Fig. Repeat Problem 33 for the JFET configuration of Fig. Using PSpice Windows. 34. § 11. Problems 543 . The application of a 10-mV. (c) Calculate the low cutoff frequency. 29. Repeat the analysis of Problem 22 for the network of Fig. Repeat Problem 33 for the network of Fig. Vo (mV) 100 90 80 70 60 50 40 30 20 10 0 1 2 3 4 5 6 t ( µ s) Figure 11.68.10 High-Frequency Response — FET Amplifier 26.71 Problem 31 § 11. 30.f * * * 23. 11. *Please Note: Asterisks indicate more difficult problems. 11. 35. Sketch the frequency response for the high-frequency region using a Bode plot and determine the cutoff frequency.11 Multistage Frequency Effects 28. Calculate the overall upper 3-dB frequency for a four-stage amplifier having an individual stage value of f2 2.5 MHz.64. Find Av and Avs in the mid-frequency range.68. Repeat the analysis of Problem 22 for the network of Fig. 11. determine the frequency response of Vo /Vs for the BJT amplifier of Fig. determine the frequency response of Vo /Vi for the high-pass filter of Fig. Repeat the analysis of Problem 26 for the network of Fig. 11. 33. 11.67.71. 100-kHz square wave to an amplifier resulted in the output waveform of Fig. 27.12 Square-Wave Testing * 31. Calculate the overall voltage gain of four identical stages of an amplifier. 11.66.71. § 11.70.

1 INTRODUCTION While there are many ICs containing only digital circuits and many that contain only linear circuits.2 COMPARATOR UNIT OPERATION A comparator circuit accepts input of linear voltages and provides a digital output that indicates when one input is less than or greater than the second. the other connected to the input signal voltage. a home timer to turn lights on or off. Interface circuits are used to enable connecting signals of different digital voltage levels. The output is a digital signal that stays at a high voltage level when the noninverting ( ) input is greater than the voltage at the inverting ( ) input and switches to a lower voltage level when the noninverting input voltage goes below the inverting input voltage. the 721 . Timer ICs provide linear and digital circuits to use in various timing operations. One popular application of a VCO is in a phase-locked loop unit.CHAPTER Linear-Digital ICs 17. Figure 17. from different types of output devices. 17. voltage-controlled oscillator (VCO) circuits.1a. interface circuits. As long as Vin is less than the reference voltage level of 2 V.1b shows a typical connection with one input (the inverting input in this example) connected to a reference voltage. Among the linear/digital ICs are comparator circuits. and a circuit in electromechanical equipment to provide proper timing to match the intended unit operation. 17 17. and those that convert a linear voltage into a digital value. A voltage-controlled oscillator provides an output clock signal whose frequency can be varied or adjusted by an input voltage. and phaselocked loops (PLLs). there are a number of units that contain both linear and digital circuits. Circuits that convert digital signals into an analog or linear voltage. When the input rises just above 2 V. as used in various communication transmitters and receivers. The 555 timer has long been a popular IC unit. A basic comparator circuit can be represented as in Fig. and compact disk (CD) players. digital/analog converters. among many others. The comparator circuit is one to which a linear input voltage is compared to another reference voltage. the output being a digital condition representing whether the input voltage exceeded the reference voltage. as in a car alarm. automotive equipment. the output remains at a low voltage level (near 10 V). are popular in aerospace equipment. timer circuits. or from different impedances so that both the driver stage and the receiver stage operate properly.

Thus the high output indicates that the input signal is greater than 2 V.2.+V −Input +V (+10 V) Vref (+2 V) Vin – Output – Output +Input + −V (a) + −V (−10 V) (b) Figure 17. (b) typical application. the reference voltage may be connected to either plus or minus input and the input signal then applied to the other input. The reference voltage level is set at Vref 722 10 k 10 k 10 k ( 12 V) 6V Chapter 17 Linear-Digital ICs . output quickly switches to a high-voltage level (near 10 V).2 Operation of 741 op-amp as comparator. 17. Figure 17. The input Vi going even a fraction of a millivolt above the 0-V reference level will be amplified by the very high voltage gain (typically over 100. Figure 17. as shown in Fig. Also. a sinusoidal signal applied to the noninverting input (pin 3) will cause the output to switch between its two output states. In general use. With reference input (at pin 2) set to 0 V.1 Comparator unit: (a) basic unit.2b. 17. Since the internal circuit used to build a comparator contains essentially an opamp circuit with very high voltage gain.000) so that the output rises to its positive output saturation level and remains there while the input stays above Vref 0 V. the reference level need not be 0 V but can be any desired positive or negative voltage.2b clearly shows that the input signal is linear while the output is digital. When the input drops just below the 0-V reference level.3a shows a circuit operating with a positive reference voltage connected to the minus input and the output connected to an indicator LED. Use of Op-Amp as Comparator Figure 17. we can examine the operation of a comparator using a 741 op-amp. the output is driven to its lower saturation level and stays there while the input remains below Vref 0 V. as shown in Fig.

Vi. As an alternative connection. built-in noise immunity to prevent the output from oscillating when the input passes by the reference level.+12 V 10 kΩ – 741 10 kΩ Vi Vo 470 Ω LED LED on when Vi goes above Vref (= +6 V) + −12 V (a) +12 V 10 kΩ Vi – 741 Vo 470 Ω LED LED on when Vi goes below Vref (= +6 V) + 10 kΩ −12 V (b) Figure 17. and outputs capable of directly driving a variety of loads. the reference voltage could be connected to the noninverting input as shown in Fig. The output.2 Comparator Unit Operation 723 . Some of the improvements built into a comparator IC are faster switching between the two output levels. A few popular IC comparators are covered next. the output will switch to its positive saturation level when the input. 17. With this connection. depending on which input is connected as signal input and which as reference input. goes more positive than the 6-V reference voltage level.3 A 741 op-amp used as a comparator. then drives the LED on as an indication that the input is more positive than the reference level. Vo.4 contains a comparator circuit that can operate as well from dual power supplies of 15 V as from a single 5-V supply (as used in digital logic circuits). Using Comparator IC Units While op-amps can be used as comparator circuits. 17. The output can provide a voltage at one of two distinct levels or can be used to drive a lamp or a relay. The LED can thus be made to go on when the input signal goes above or below the reference level. separate IC comparator units are more suitable. 311 COMPARATOR The 311 voltage comparator shown in Fig. the input signal going below the reference level would cause the output to drive the LED on. describing their pin connections and how they may be used. Since the reference voltage is connected to the inverting input. Notice that the output is taken 17.3b.

5. the output remains high 724 Chapter 17 Linear-Digital ICs . 17. When the input is any positive voltage. while any negative voltage will result in the output going to a high voltage level. The unit also has balance and strobe inputs.4 A 311 comparator (eight-pin DIP unit). A zero-crossing detector that senses (detects) the input voltage crossing through 0 V is shown using the 311 IC in Fig. The input signal going negative (below 0 V) will drive the output transistor off. the output will go high when the input goes above the reference level—but only if the TTL strobe input is off (or 0 V).5 Zero-crossing detector using a 311 IC. the strobe input allowing gating of the output. with the output then going low ( 10 V in this case).Figure 17. the output is low. causing the output to remain in the off state (with output high) regardless of the input signal.6 shows how a 311 comparator can be used with strobing. Figure 17. In this example. from a bipolar transistor to allow driving a variety of loads. The input signal going positive drives the output transistor on. it drives the 311 strobe input at pin 6 low. A few examples will show how this comparator unit can be used in some common applications. If the TTL strobe input goes high. Figure 17. The output is thus an indication of whether the input is above or below 0 V. the output then going high (to 10 V). The inverting input is connected to ground (the reference voltage). In effect.

Figure 17.2 Comparator Unit Operation 725 . 17. unless strobed. These contacts can then be connected to operate a large variety of devices. all four will be drawing power. switching from high to low depending on the input signal level.O.7 shows the comparator output driving a relay. a buzzer or bell wired to the contacts can be driven on whenever the input voltage drops below 0 V. The supply voltage applied to a pair of pins powers all four comparators. the output then acts normally. the relay is activated. If strobed.6 Operation of a 311 comparator with strobe input. Figure 17. As long as the voltage is present at the input terminal. driving the output low. the comparator output will respond to the input signal only during the time the strobe signal allows such operation.Figure 17. 339 COMPARATOR The 339 IC is a quad comparator containing four independent voltage comparator circuits connected to external pins as shown in Fig. For example. Each comparator has inverting and noninverting inputs and a single output. Even if one wishes to use one comparator.8.) contacts at that time. When the input goes below 0 V. closing the normally open (N. 17. In operation.7 Operation of a 311 comparator with relay output. the buzzer will remain off.

17.9 Operation of one 339 comparator circuit as a zero-crossing detector. The operation of one of the comparator circuits is described next. Vo Vref = 0 V – 12 V − (−5 V) (a) V+ Vo Time V− Figure 17. A reference level other than 0 V can also be used. 726 Chapter 17 Linear-Digital ICs . Whenever the input signal goes above 0 V. the other terminal then being connected to the input signal.9 shows one of the 339 comparator circuits connected as a zero-crossing detector. Vi 3 + 2 339 4 5. Quad comparator To see how these comparator circuits can be used.Figure 17.8 IC (339). and either input terminal could be used as the reference.1 kΩ Time Output. The input switches to V only when the input goes below 0 V. Fig. the output switches to V . V + (5 V) Vi 5 Input.

V+ V+ Input + Input > Vref ← output open circuit 339 Input < Vref ← output =V − Vref + Input < Vref ← output open circuit 339 Input > Vref ← output =V− Vref – V− (a) Input – V− (b) Figure 17. the inverting input going below Vref results in the output open circuit while the inverting input going above Vref results in the output at V . the positive input goes above Vref and results in a positive differential input with output driven to the open-circuit state. If the positive input is set at the reference level. resulting in a negative differential input.2 kΩ Vref2 ≅ +1 V 1 kΩ 7 6 – 1 2 +5 V Output low Output high +1 V 12 Output low + Input Figure 17. 17. Operation of a 339 comparator circuit with reference input: (a) minus input. If the negative input is set at a reference level Vref.10 input.11 shows two comparator circuits connected with common output and also with common input. When the noninverting input goes below Vref. the output will be driven to V .1 kΩ Output + 9.10. Figure 17. This operation is summarized in Fig. while a negative differential input voltage drives the output transistor on—the output then at the supply low level.5 kΩ 5 1 3 2 5.1 kΩ Vref1 ≅ +5 V +9 V 8.11 Operation of two 339 comparator circuits as a window detector.2 Comparator Unit Operation 727 . applications in which the outputs from more than one circuit can be wire-ORed are possible. (b) plus Since the output of one of these comparator circuits is from an open-circuit collector. Comparator 1 has a 5-V reference voltage in+9 V 4 – 7.The differential input voltage (difference voltage across input terminals) going positive drives the output transistor off (open circuit). 17.

put connected to the noninverting input. representing the binary values of 1 or zero. The high output indicates that the input is within a voltage window of 1 to 5 V (these values being set by the reference voltage levels used). (b) circuit example with 0110 input.11.1) Figure 17. In total. Comparator 2 has a reference voltage of 1 V connected to the inverting input. The output voltage is proportional to the digital input value as given by the relation Vo D0 20 D1 21 2 4 D2 22 D3 23 Vref (17. Figure 17. A ladder network accepts inputs of binary values at. 0 V or Vref and provides an output voltage proportional to the binary input value.12 Four-stage ladder network used as a DAC: (a) basic circuit. An analog–digital converter (ADC) obtains a digital value representing an input analog voltage. the output will go low whenever the input is below 1 V or above 5 V. typically. One popular scheme uses a network of resistors. while a digital–analog converter (DAC) changes a digital value back into an analog voltage. representing 4 bits of digital data and a dc voltage output. 728 Chapter 17 Linear-Digital ICs . called a ladder network.3 DIGITAL–ANALOG CONVERTERS Many voltages and currents in electronics vary continuously over some range of values. In digital circuitry the signals are at either one of two levels. as shown in Fig. The output will be driven low by comparator 1 when the input signal goes above 5 V.12a shows a ladder network with four input voltages. The output of comparator 2 will be driven low when the input signal goes below 1 V. the overall operation being that of a voltage window detector. 17. 17. Digital-to-Analog Conversion LADDER NETWORK CONVERSION Digital-to-analog conversion can be achieved using a number of different methods.

referred in the diagram as an R-2R ladder. Figure 17. the count is set to zero and the electronic switch connects the integrator to a reference or fixed input voltage. The binary input turns on selected legs of the ladder. a 10-stage ladder network could extend the number of voltage steps or the voltage resolution to Vref/210 or Vref/1024. A reference voltage of Vref 10 V would then provide output voltage steps of 10 V/1024 or approximately 10 mV.In the example shown in Fig. At the end of the fixed count interval. Using more sections of ladder allows having more binary inputs and greater quantization for each step. The ladder network. the output current being a weighted summing of the reference current.12b. 01102. analog. In general. Connecting the output current through a resistor will produce an analog voltage.2) Figure 17. For a fixed time interval (usually the full count range of the counter). if desired. the output voltage resulting should be Vo 0 1 1 2 16 1 4 0 8 (16 V) 6V Therefore.13 DAC IC using R-2R ladder network. the analog voltage connected to the integrator raises the voltage at the comparator input to some positive level. The digital output is obtained from a counter operated during both positive and negative slope intervals of the integrator. The method of conversion proceeds as follows.14a shows a block diagram of the basic dual-slope converter.14b shows that at the end of the fixed time interval the voltage from the integrator is greater for the larger input voltage. 17.3 Digital-Analog Converters 729 . Analog-to-Digital Conversion DUAL-SLOPE CONVERSION A popular method for converting an analog voltage into a digital value is the dualslope method. the voltage resolution for n ladder stages is Vref 2n (17. Digital inputs Current switches R-2 R ladder Io Vref Reference current Figure 17. converts to 6 V. digital. The function of the ladder network is to convert the 16 possible binary values from 0000 to 1111 into one of 16 voltage levels in steps of Vref/16.13 shows a block diagram of a typical DAC using a ladder network. is sandwiched between the reference current supply and current switches connected to each binary input. For example. The analog voltage to be converted is applied through an electronic switch to an integrator or ramp-generator circuit (essentially a constant current charging a capacitor to produce a linear ramp voltage). Figure 17. 17. More ladder stages provide greater voltage resolution. the resulting output current proportional to the input binary value.

The integrator output (or capacitor input) then decreases at a fixed rate. or other form of digital counter. if desired. Setting the reference input value and clock rate can scale the counter output as desired. BCD.15).14 Analog-to-digital conversion using dual-slope method: (a) logic diagram. 17. The counter advances during this time. while the integrator’s output decreases at a fixed rate until it drops below the comparator reference voltage.Analog input Digital input Integrator Comparator Stop count Count pulses Control logic Clear pulse Digital counter Reference input Vref Clock Count over Linear Linear/Digital (a) Digital L ar r ge in pu o tv lta ge ut Inp vol tag e Fixed discharge rate e Smaller in put voltag Smaller digital count Fixed time interval Digital count Larger digital count Count interval (b) Figure 17. which increases one voltage increment for each count step. 17. as shown in Fig. at which time the control logic receives a signal (the comparator output) to stop the count. receiving both staircase voltage and analog input 730 Chapter 17 Linear-Digital ICs . The digital value stored in the counter is then the digital output of the converter.15b. A digital counter advances from a zero count while a ladder network driven by the counter outputs a staircase voltage. Using the same clock and integrator to perform the conversion during positive and negative slope intervals tends to compensate for clock frequency drift and integrator accuracy limitations. The counter can be a binary. LADDER-NETWORK CONVERSION Another popular method of analog-to-digital conversion uses a ladder network along with counter and comparator circuits (see Fig. (b) waveform. A comparator circuit.

1 ms 244 conversions/second Since on the average. 17.1 ms/2 2.1 ms The minimum number of conversions that could be carried out each second would then be number of conversions 1/4.05 ms would be needed. A converter using fewer count stages (and less conversion resolution) would carry out more conversions per second. The conversion accuracy depends on the accuracy of the comparator. and the average number of conversions would be 2 244 488 conversions/second. (b) waveform.4 mV This would result in a conversion resolution of 2. The counter value at that time is the digital output. provides a signal to stop the count when the staircase voltage rises above the input voltage. The amount of voltage change stepped by the staircase signal depends on the number of count bits used.4 mV.Figure 17. A slower clock rate would result in fewer conversions per second. A 12-stage counter operating a 12-stage ladder network using a reference voltage of 10 V would step each count by a voltage of Vref 212 10 V 4096 2. voltage. with some conversions requiring little count time and others near maximum count time. The clock rate of the counter would affect the time required to carry out a conversion. A clock rate of 1 MHz operating a 12-stage counter would need a maximum conversion time of 4096 1 s 4096 s 4. a conversion time of 4.3 Digital-Analog Converters 731 .15 Analog-to-digital conversion using ladder network: (a) logic diagram.

Figure 17. the transistor collector usually being driven low to discharge a timing capacitor. The flip-flop circuit also operates a transistor inside the IC. The output of the flip-flop circuit is then brought out through an output amplifier stage.17 Astable multivibrator using 555 IC.16. Details of 555 4 Reset Vref Astable Operation One popular application of the 555 timer IC is as an astable multivibrator or clock circuit. VCC 8 R Control voltage 5 R ( 2 VCC) 3 Threshold 6 + – + 2 1 F/F ( 1 VCC) 3 Output stage 3 Output 7 Discharge R 1 2 Trigger input – Figure 17. A series connection of three resistors sets the reference voltage levels to the two comparators at 2VCC/3 and VCC/3. 732 .17 shows an astable circuit built using an external resistor and capacitor to set the timing interval of the output signal. The entire circuit is usually housed in an 8-pin package as specified in Fig.16. 17. the output of these comparators setting or resetting the flip-flop unit. Figure 17.4 TIMER IC UNIT OPERATION Another popular analog–digital integrated circuit is the versatile 555 timer.17. 17. The IC is made of a combination of linear comparators and digital flip-flops as described in Fig.16 timer IC. The following analysis of the operation of the 555 as an astable circuit includes details of the different parts of the unit and how the various inputs and outputs are utilized.

44 2RB)C 0.18a shows the capacitor and output waveforms resulting from the astable circuit.6) Figure 17. *The period can be directly calculated from T and the frequency from f (RA 1.4 Timer IC Unit Operation 733 . The capacitor voltage then decreases until it drops below the trigger level (VCC/3). the capacitor voltage rises until it goes above 2VCC/3.17. the discharge transistor is driven on. This voltage is the threshold voltage at pin 6.7(RA RB)C (17.693(RA 2RB)C 0.4) Tlow The total period is T period 0.18 Astable multivibrator for Example 17. Calculation of the time intervals during which the output is high and low can be made using the relations Thigh 0. In addition. (b) waveforms.7RBC Thigh Tlow (17. The flipflop is triggered so that the output goes back high and the discharge transistor is turned off.Capacitor C charges toward VCC through external resistors RA and RB.5) The frequency of the astable circuit is then calculated using* f 1 T (RA 1. causing the output at pin 7 to discharge the capacitor through resistor RB. which drives comparator 1 to trigger the flip-flop so that the output at pin 3 goes low. 17.3) (17. so that the capacitor can again charge through resistors RA and RB toward VCC.7(RA 2RB)C 17.1: (a) circuit. Referring to Fig.44 2RB)C (17. Figure 17.

7(7.3) through (17. Time periods for this circuit can range from microseconds to many seconds. as shown in Fig.1 10 6) 0. Solution Using Eqs.16.575 10 3 RB)C 0.05 ms 0.19b shows the input trigger signal and the resulting output waveform for the 555 timer operated as a one-shot.1 Determine the frequency and draw the output waveform for the circuit of Fig.5 103)(0.7) Referring back to Fig. comparator 1 triggers the flip-flop.19. it triggers the oneshot. 734 Chapter 17 Linear-Digital ICs . the output remains high. When the voltage across the capacitor reaches the threshold level of 2VCC/3. (17. 17. making this IC useful for a range of applications. with the output at pin 3 going high. Figure 17. Monostable Operation The 555 timer can also be used as a one-shot or monostable multivibrator circuit.7(RA 1. the negative edge of the trigger input causes comparator 2 to trigger the flip-flop. 17.7(7. causing the capacitor to remain at near 0 V until triggered again.1 10 6) 103)(0.525 ms 1. 17.5 103 7.575 ms 1. During the charge interval. When the trigger input signal goes negative. The discharge transistor also goes low. 17. with output at pin 3 then going high for a time period Thigh 1.18a.05 ms Tlow T f 0.5 Tlow 1 1. Capacitor C charges toward VCC through resistor RA.18b. Figure 17.19 Operation of 555 timer as one-shot: (a) circuit.EXAMPLE 17.1RAC (17.6) yields Thigh 0. (b) waveforms.525 ms 635 Hz The waveforms are drawn in Fig. with output going low.7RBC Thigh 1 T 0.

1(7. 3 VC V . R1 should be within the range 2 k R1 20 k .825 ms 17. can be calculated from fo 2 V VC R1C1 V (17.5 103)(0. (17. A Schmitt trigger circuit is used to switch the current sources between charging and discharging the capacitor.5 VOLTAGE-CONTROLLED OSCILLATOR A voltage-controlled oscillator (VCO) is a circuit that provides a varying output signal (typically of square-wave or triangular-wave form) whose frequency can be adjusted over a range controlled by a dc voltage. fo. VC. 17. which contains circuitry to generate both square-wave and triangular-wave signals whose frequency is set by an external resistor and capacitor and then varied by an applied dc voltage. Figure 17.21b shows the pin connection of the 566 unit and a summary of formula and value limitations.5 Voltage-Controlled Oscillator 735 . Figure 17. An example of a VCO is the 566 IC unit. VC should be within range 4 V 17.20 Monostable circuit for Example 17. we obtain Thigh 1. A free-running or center-operating frequency. 2.1 10 6) 0.21a shows that the 566 contains current sources to charge and discharge an external capacitor C1 at a rate set by external resistor R1 and the modulating dc input voltage. The oscillator can be programmed over a 10-to-1 frequency range by proper selection of an external resistor and capacitor.2 Figure 17.20 when triggered by a negative pulse.1RAC 1.Determine the period of the output waveform for the circuit of Fig. EXAMPLE 17. and then modulated over a 10-to-1 frequency range by a control voltage.7). and the triangular voltage developed across the capacitor and square wave from the Schmitt trigger are provided as outputs through buffer amplifiers.2.8) with the following practical circuit value restrictions: 1. Solution Using Eq.

22 Connection of 566 VCO unit. V should range between 10 V and 24 V. fo should be below 1 MHz. 3.22 shows an example in which the 566 function generator is used to provide both square-wave and triangular-wave signals at a fixed frequency set by R1. 736 Chapter 17 Linear-Digital ICs . A resistor divider R2 and R3 sets the dc modulating voltage at a fixed value Figure 17. (b) pin configuration and summary of operating data.21 A 566 function generator: (a) block diagram. Figure 17.Figure 17. 4. and VC. C1.

4 V 12 V).23 shows how the output square-wave frequency can be adjusted using the input voltage.4 V peak can drive VC around the bias point between voltages of 9 and 11. the control voltage is VC R2 R4 R3 R4 (V ) 510 18 k 5k 18 k ( 12 V) 9.24. an input modulating voltage. 17.2 kHz). 17. over the full 10-to-1 frequency range.74 12 19.19 12 212.9 kHz The frequency of the output square wave can then be varied using potentiometer R3 over a frequency range of at least 10 to 1.VC R3 R2 R3 V 10 k 1. Vin. (which falls properly in the voltage range 0. An input ac voltage of about 1.4 V.5 k 10 k (12 V) 9 V and V 10. Potentiometer R3 allows varying VC from about 9 V to near 12 V.4 12 32. With the wiper arm of R3 set at the bottom. 17. Using Eq. VC.75V (17. Rather than varying a potentiometer setting to change the value of VC. With the potentiometer wiper set at the top.7 kHz Figure 17.5 kHz The circuit of Fig. can be applied as shown in Fig.19 V resulting in an upper frequency of fo (10 2 103)(220 12 10 12 ) 9. causing the output frequency to vary over about a 10-to-1 range.74 V resulting in a lower output frequency of fo (10 2 103)(220 12 10 12 ) 11.23 Connection of 566 as a VCO unit. to vary the signal frequency. The voltage divider sets VC at about 10. the control voltage is VC R3 R2 R3 R4 R4 (V ) 5k 510 5k 18 k 18 k ( 12 V) 11. The input signal Vin thus frequency-modulates the output voltage around the center frequency set by the bias value of VC 10.4 V ( fo 121.8 V.8) yields fo (10 2 103)(820 12 10 12 ) 10.5 Voltage-Controlled Oscillator 737 .

17.Figure 17. tone decoders. and (4) a wide variety of areas including modems. (2) FM demodulation networks for FM operation with excellent linearity between the input signal frequency and the PLL output voltage. Common applications of a PLL include: (1) frequency synthesizers that provide multiples of a reference signal frequency [e. Vi.25) providing an output voltage. and tracking filters. and a voltage-controlled oscillator connected as shown in Fig. This voltage is then fed to a low-pass filter that pro- Figure 17. 738 Chapter 17 Linear-Digital ICs . telemetry receivers and transmitters. Vo.24 Operation of VCO with frequency-modulating input.6 PHASE-LOCKED LOOP A phase-locked loop (PLL) is an electronic circuit that consists of a phase detector.g.25. are compared by a phase comparator (refer to Fig. An input signal. a low-pass filter. 17. 17. the carrier frequency for the multiple channels of a citizens’ band (CB) unit or marine-radio-band unit can be generated using a single-crystal-controlled frequency and its multiples generated using a PLL]. (3) demodulation of the two data transmission or carrier frequencies in digital-data transmission used in frequency-shift keying (FSK) operation. Ve.. that represents the phase difference between the two signals. AM detectors. and that from a VCO.25 Block diagram of basic phase-locked loop (PLL).

If the PLL center frequency is selected or designed at the FM carrier frequency. Best operation is obtained if the VCO center frequency. there are two important frequency bands specified for a PLL. the voltage. is set with the dc bias voltage midway in its linear operating range. Owing to the limited operating range of the VCO and the feedback connection of the PLL circuit. The 565 typically uses two power supplies. the filtered or output voltage of the circuit of Fig. and voltage-controlled oscillator. although not necessarily in phase. 17. Basic PLL Operation The basic operation of a PLL circuit can be explained using the circuit of Fig.6 Phase-Locked Loop 739 . the two signals to the comparator are of the same frequency. Another external capacitor.vides an output voltage (amplified if necessary) that can be taken as the output voltage from the PLL and is used internally as the voltage to modulate the VCO’s frequency. 17. FREQUENCY DEMODULATION FM demodulation or detection can be directly achieved using the PLL circuit. shown in Fig. An external resistor and capacitor. The capture range of a PLL is the frequency range centered about the VCO free-running frequency. are used to set the free-running or center frequency of the VCO. over which the loop can acquire lock with the input signal. While the loop is trying to achieve lock.26a. the dc voltage will drive the VCO frequency to match that of the input. Once the PLL has achieved capture. We will first consider the operation of the various circuits in the phaselocked loop when the loop is operating in lock (the input signal frequency and the VCO frequency are the same). which are only partially connected internally. the output of the phase comparator contains frequency components at the sum and difference of the signals compared. R1 and C1. amplifier. Changes in the input signal frequency then result in change in the dc voltage to the VCO. varying in value proportional to the variation of the signal frequency.25 as reference. When the input signal frequency is the same as that from the VCO to the comparator. A fixed phase difference between the two signals to the comparator results in a fixed dc voltage to the VCO. 17. The PLL circuit thus operates as a complete intermediate-frequency (IF) strip. V and V . The amplifier allows this adjustment in dc voltage from that obtained as output of the filter circuit.25 is the desired demodulated voltage. Examples of each of these follow. C2. Within a capture-and-lock frequency range. (2) frequency synthesis. and the VCO output must be connected back as input to the phase detector to close the PLL loop. fo. A lowpass filter passes only the lower-frequency component of the signal so that the loop can obtain lock between input and VCO signals. fo. One popular PLL unit is the 565. including (1) frequency demodulation. it can maintain lock with the input signal over a somewhat wider frequency range called the lock range. and (3) FSK decoders. The 565 contains a phase detector. Vd. taken as output is the value needed to hold the VCO in lock with the input signal. The closed-loop operation of the circuit is to maintain the VCO frequency locked to that of the input signal frequency. When the loop is in lock. 17. The VCO then provides output of a fixed-amplitude square-wave signal at the frequency of the input. limiter. and demodulator as used in FM receivers. Applications The PLL can be used in a wide variety of applications. is used to set the low-pass filter passband.

7 Output 8 R1 10 kΩ VCO 9 V7 +5.26b shows the PLL connected to work as an FM demodulator.82 kHz) fo − (c) Figure 17.45 kHz) (= 227. 7 6 VCO 10 C2 Demodulated output Reference output 9 C1 1 V− (a) +6 V 10 C2 330 pF Demodulated output Reference output FM signal input 2 3 5 6 4 Phase detector 3.3 10 )(220 3 (17.7 V C1 220 pF 1 fo = 0.8 kHz 740 Chapter 17 Linear-Digital ICs .6 kΩ Amp. Frequency fo fL fL (= 136. Resistor R1 and capacitor C1 set the free-running frequency. The lock range is fL 8fo V 8(136.V+ 565 2 Input 3 5 4 Output 8 R1 Phase detector 3.36 kHz) fo + 2 2 (= 45.36 6 103) 181.3 R1 C1 +6 V −6 V (b) Figure 17.9) 136.3 R1C1 (10 with limitation 2 k R1 0.6 kΩ Amp.27 kHz) ± fL (± 181. fo.26 Phase-locked loop (PLL): (a) basic block diagram: (b) PLL connected as a frequency demodulator: (c) output voltage vs.3 V +5 V +4. frequency plot. fo 0.36 kHz 10 12 ) 20 k .

27. This output is a multiple of the input frequency as long as the loop is in lock.for supply voltages V 6 V.36 kHz.26c shows the output at pin 7 as a function of the input signal frequency.1 kHz The signal at pin 4 is a 136. Figure 17. FREQUENCY SYNTHESIS A frequency synthesizer can be built around a PLL as shown in Fig.1 kΩ Input A 14 5 1 12 9 7490 8 QA ÷ 2 QB ÷ 4 QC ÷ 8 QD ÷ 16 10 11 3 6 2 7 R0 (1) R0 (2) R 9 (1) R 9 (2) fo (b) Figure 17.6 103)(330 10 ) 156. The output voltage is the demodulated signal that varies with frequency within the operating range specified.6 Phase-Locked Loop 741 . (b) implementation using 565 PLL unit. 17. A frequency divider is inserted between the VCO output and the phase comparator so that the loop signal to the comparator is at frequency fo while the VCO output is Nfo.8 103) (3.8 kHz around the center frequency 136.8 kHz will result in the output at pin 7 varying around its dc voltage level set with input signal at fo. ÷N VCO Output Nfo (a) C2 330 pF R1 10 kΩ 8 2 565 Vi f1 3 9 C1 220 pF −5 V 1 5 7 10 4 10 kΩ Nfo +5 V 5. 17. The input signal can be stabilized at f1 with the resulting VCO output at Nf1 if the loop is set Input f1 Phase comparator fo Low-pass filter Amp.36-kHz square wave. The capture range is fC 1 2 1 2 2 fL R2C2 12 2 (181.27 Frequency synthesizer: (a) block diagram. An input within the lock range of 181. The dc voltage at pin 7 is linearly related to the input signal frequency within the frequency range fL 181.

The RC ladder filter (three sections of C 0. An input at 1270 Hz will correspondingly drive the 565 dc output less positive with the digital output. An output at Nfo (4fo in the present example) is connected through an inverter circuit to provide an input at pin 14 of the 7490.7 INTERFACING CIRCUITRY Connecting different types of circuits. As long as the PLL circuit is in lock. representing the RS-232C logic levels or mark ( 5 V) or space ( 14 V). the closed loop then resulting in the VCO output becoming exactly Nf1 at lock. Figure 17. It is only necessary to readjust fo to be within the capture-and-lock range. may require some sort of interfacing circuit. either in digital or analog circuits. An interface circuit may be used to drive a load or to obtain a signal as a receiver circuit. the VCO output frequency will be exactly N times the input frequency.27b shows an example using a 565 PLL as frequency multiplier and a 7490 as divider.02 F and R 10 k ) is used to remove the sum frequency component. The decoder receives a signal at one of two distinct carrier frequencies. A driver circuit provides the output signal at a 742 Chapter 17 Linear-Digital ICs . which then drops to the low level (mark or 5 V). 17. Using the output at pin 9. FSK DECODERS An FSK (frequency-shift keyed) signal decoder can be built as shown in Fig. which is divided by 4 from that at the input to the 7490. 17. 1270 Hz or 1070 Hz. the loop locks to the input frequency and tracks it between two possible frequencies with a corresponding dc shift at the output.28 Connection of 565 as FSK decoder. Since the VCO can vary over only a limited range from its center frequency. Then an input at frequency 1070 Hz will drive the decoder output voltage to a more positive voltage level. the signal at pin 4 of the PLL is four times the input frequency as long as the loop remains in lock. The input Vi at frequency f1 is compared to the input (frequency fo) at pin 5. which varies between 0 and 5 V.up to lock at the fundamental frequency (when fo f1). respectively.28. As the signal appears at the input. driving the digital output to the high level (space or 14 V). The free-running frequency is adjusted with R1 so that the dc voltage level at the output (pin 7) is the same as that at pin 6. it may be necessary to change the VCO frequency whenever the divider value is changed. Figure 17.

providing high input impedance to minimize loading of the input signal. connection of an input signal to the inverting input would result in an inverted output from the receiver unit. The driver-receiver unit of Fig. the interface circuits may include strobing.voltage or current level suitable to operate a number of loads. This standard states that a digital signal represents a mark (logic-1) and a space (logic-0).29a shows a dual-line driver. Another type of interface circuit is that used to connect various digital input and output units. Figure 17. providing output capable of driving TTL or MOS device circuits. and printers.29 provides an output when the strobe signal is present (high in this case).29 Interface units: (a) dual-line drivers (SN75150). some as inverting and others as noninverting units. 17. As an example. 17. A receiver circuit essentially accepts an input signal.29b shows a dual-line receiver having both inverting and noninverting inputs so that either operating condition can be selected. signals with devices such as keyboards. displays. Connecting the input to the noninverting input would provide the same interfacing except that the output obtained would have the same polarity as the received signal. Furthermore. (b) dual-line receivers (SN75152). 17. video terminals.7 Interfacing Circuitry 743 . which provides connecting the interface signals during specific time intervals established by the strobe. each driver accepting input of TTL signals. One of the EIA electronic industry standards is referred to as RS-232C. or power units. The circuit of Fig. Figure 17. This type of interface circuit comes in various forms. or to operate such devices as relays. The definitions of mark and space vary with the type of circuit used (although a full reading of the standard will spell out the acceptable limits of mark and space signals).

while all transistors remaining off provide a high output voltage.31) that is not connected to any other electronic component.RS-232C-to-TTL Converter For TTL circuits. a mark could be 12 V and a space 12 V. the output is open-collector. Figure 17. For a unit having outputs defined by RS-232C that is to operate into another unit operating with a TTL signal level. The input to the inverter going low results in a 5-V signal from the 7407 inverter output so that a mark from the teletype results in a mark to the TTL input. driving the output transistor on. 17. resulting in an output of 5 V (TTL mark). A mark output from the driver (at 12 V) would be clipped by the diode so that the input to the inverter circuit is near 0 V. an interface circuit as shown in Fig. 17. 5 V is a mark and 0 V is a space. An input mark results when 20 mA of current is drawn from the source through the output line of the teletype (TTY). Another means of interfacing digital signals is made using open-collector output or tri-state output. This current then goes through the diode element of an opto-isolator. 17. which is a TTL space signal. For RS-232C.30b could be used. with the optoisolator transistor remaining off and the inverter output then 0 V. 744 Chapter 17 Linear-Digital ICs . When a signal is output from a transistor collector (see Fig.30a provides a tabulation of some mark and space definitions. A space output at 12 V would drive the inverter output low for a 0-V output (a space). Any transistor going on then provides a low output voltage.30 Interfacing signal standards and converter circuits.30c. Another example of an interface circuit converts the signals from a TTY current loop into TTL levels as shown in Fig. This permits connecting a number of signals to the same wire or bus. Figure 17. A space from the teletype current loop provides no current.

32. 17. 17. To view the dc current through the LED. Analysis of various problems can display the resulting dc bias. place a VPRINT1 component at Vo with DC and MAG selected. draw the circuit of a comparator circuit with output driving an LED indicator as shown in Fig. Program 17. for Vi from 4 to 8 V in 1-V steps.32.8 PSpice Windows 745 .1—Comparator Circuit Used to Drive an LED Using Design Center. 17. place an IPRINT component in series with the LED current meter as shown in Fig.Figure 17. or one can use PROBE to display resulting waveforms. The Analysis Setup provides for a dc sweep as shown in Fig. 17. some of the resulting analysis output obtained is shown in Fig.31 Connections to data lines: (a) open-collector output.34. as shown. 17. The DC Sweep is set. After running the simultation. 17. (b) tri-state output.33. To be able to view the magnitude of the dc output voltage. Figure 17.32 Comparator circuit used to drive an LED.8 PSPICE WINDOWS Many of the practical op-amp applications covered in this chapter can be analyzed using PSpice.

34 shows a table of the output voltage and a table of the LED current for inputs from 4 to 8 V. the output is in-phase with the input.32. Any input above 6 V results in the output going to the positive saturation level (near 10 V). 746 . the output goes to the positive saturation level. 17. 17. The LED will therefore be driven on by any input above the reference level of 6 V and left off by any input below 6 V.34 Analysis output (edited) for circuit of Fig. 17. 17. Program 17. The listing of Fig. Since the input signal is applied to the noninverting input.35. peak sinusoidal signa.32. The input is a 5 V.2—Comparator Operation The operation of a comparator IC can be demonstrated using a 741 op-amp as shown in Fig.33 Analysis Setup for a dc sweep of the circuit of Fig. The circuit of Fig.Figure 17. Chapter 17 Linear-Digital ICs Figure 17. The Analysis Setup provides for Transient analysis with Print Step of 20 ns and Final Time of 3 ms. When the input goes above 0 V. The table shows that the LED current is nearly 0 for inputs up to 6 V and that a current of about 20 mA lights the LED for inputs at 6 V or above.32 shows a voltage divider which provides 6 V to the minus input so that any input (Vi) below 6 V will result in the output at the minus saturation voltage (near 10 V). 17.

1 F) 0.37 Schematic of a 555 timer oscillator.1 F) Figure 17.525 ms 1.3) and (17.36 shows a PROBE output of input and output voltages.35 comparator. Figure 17. 17.5 k )(0.7(RA Tlow RB)C 0.36 Probe output for the comparator of Fig.8 PSpice Windows 747 .37 shows a 555 timer connected as an oscillator.15 k )(0.7(7. Schematic for a near 5 V. Program 17. 17.35.7(7.5 k 7.4) can be used to calculate the charge and discharge times as follows: Thigh 0.Figure 17.3—Operation of 555 Timer as Oscillator Figure 17.7RBC 0. the output goes to the negative saturation level—this being 0 V since the minus voltage input is set to that value.05 ms 0. When the input goes below 0 V. Equations (17. Figure 17.

40 Problem 4 5. at which time the output goes to the high level of 5 V. 3. Draw the resulting output waveform for the circuit of Fig. The resulting trigger and output waveforms are shown in Fig.Figure 17. 17.38 Probe output for the 555 oscillator of Fig. When the trigger charges to the upper trigger level. Identify all pin numbers. Sketch the output waveform for the circuit of Fig. PROBLEMS § 17. 17.40.37. Draw the diagram of a 741 op-amp operated from Vi( ) 5 V. Draw the circuit diagram of a zero-crossing detector using a 339 comparator stage with supplies. 12-V 748 Chapter 17 Linear-Digital ICs .38.39 Problem 2 Figure 17. 15-V supplies with Vi( ) 0 V and 2. 17.2 Comparator Unit Operation 1. Include terminal pin connections. the output goes to the low output level of 0 V. Figure 17. Draw a circuit diagram of a 311 op-amp showing an input of 10 V rms applied to the inverting input and the plus input to ground. 4. The output stays low until the trigger input discharges to the low trigger level. 17.39.

Sketch a five-stage ladder network using 15-k and 30-k resistors.41.6.3 Digital–Analog Converters 8.42.41 * Problem 6 7. Figure 17. 10. Figure 17.42 Problem 7 § 17. Describe the operation of the circuit in Fig. What voltage resolution is possible using a 12-stage ladder network with a 10-V reference voltage? Problems 749 . 17. 17. 9. Sketch the output waveform for the circuit of Fig. calculate the output voltage for an input of 11010 to the circuit of Problem 8. For a reference voltage of 16 V.

001 F.8 PSpice Windows * 26. 17. using an LM111 with Vi 5 V rms applied to minus ( ) input and 5 V rms applied to plus ( ) input.32.35. * 4. 17. 24. 28. How many count steps occur using a 12-stage digital counter at the output of an ADC? 13. Sketch the input and output waveforms for a one-shot using a 555 timer triggered by a 10-kHz clock for RA 5.6 Phase-Locked Loop 20. 4.001 F? 19. What is the lock range of the PLL circuit in Fig. and C1 0.8 k . Use Probe to view the output waveform. 17.26b to obtain a center frequency of 100 kHz? 22. 15. 17. 17. § 17.26b with R1 C1 0. 17. § 17. 12. Calculate the VCO free-running frequency for the circuit of Fig.5 k .7 k and 21. Draw the circuit of a one-shot using a 555 timer to provide one time period of 20 s. thigh 750 Chapter 17 Linear-Digital ICs .22 for R1 R2 1.7 k and C1 0. If RA 7. What is the maximum count interval using a 12-stage counter operated at a clock rate of 20 MHz? § 17. 18. Determine the capacitor needed in the circuit of Fig. C1. 17. 17. R3 11 k .5 Voltage-Controlled Oscillator 17.7 Interfacing Circuitry 23. What value of capacitor. Determine the value of capacitor. 27.001 F? § 17. Examine the output listing for the results. what value of C is needed? 16.22 to obtain a 200-kHz output. What is the difference between open-collector and tri-state output? § 17. Sketch the circuit of a 555 timer connected as an astable multivibrator for operation at 350 kHz.23 for C1 0. What frequency range results in the circuit of Fig. What is a data bus? 25.5 k .7 k .11. Use Design Center to draw a 555 oscillator with resulting output with tlow 5 ms.26b for R1 4. * * 2 ms.001 F. needed using RA RB 7. Use Design Center to draw a schematic circuit as in Fig. *Please note: Asterisks indicate more difficult problems. For a dual-slope converter. Calculate the center frequency of a VCO using a 566 IC as in Fig. Use Design Center to draw a schematic circuit as in Fig.4 Timer IC Unit Operation 14. Describe the signal conditions for current-loop and RS-232C interfaces. C. describe what occurs during the fixed time interval and the count interval. is required in the circuit of Fig.1 k and C 5 nF.

13. We will now turn our attention to the analysis of networks in which the magnitude of the source varies in a set manner. To be v v v 0 Sinusoidal t 0 Square wave t 0 Triangular wave t FIG.1). . 13. The pattern of particular interest is the sinusoidal ac waveform for voltage of Fig.1 Alternating waveforms. the term sinusoidal. 13. For the other patterns of Fig.1 INTRODUCTION The analysis thus far has been limited to dc networks. but frequently the ac abbreviation is dropped. (The letters ac are an abbreviation for alternating current. the descriptive term is always present. absolutely correct.1 is an alternating waveform available from commercial supplies. 13.) To be absolutely rigorous. Of particular interest is the time-varying voltage that is commercially available in large quantities and is commonly called the ac voltage.1.1. square wave.13 Sinusoidal Alternating Waveforms 13. networks in which the currents or voltages are ﬁxed in magnitude except for transient effects. the terminology ac voltage or ac current is not sufﬁcient to describe the type of signal we will be analyzing. Since this type of signal is encountered in the vast majority of instances. 13. The term alternating indicates only that the waveform alternates between two prescribed levels in a set time sequence (Fig. Each waveform of Fig. the abbreviated phrases ac voltage and ac current are commonly applied without confusion. or triangular must also be applied. resulting in the designation square-wave or triangular waveforms.

The most common source is the typical home outlet. is the primary component in the energy-conversion process. Chapter 22 will serve such a purpose. (c) wind-power station. (d) solar panel. at the very least. 13. and industrial systems. as shown in Fig. 13. The increasing number of computer systems used in the industrial community requires.2 SINUSOIDAL ac VOLTAGE CHARACTERISTICS AND DEFINITIONS Generation Sinusoidal ac voltages are available from a variety of sources. (e) function generator. (b) portable ac generator. a brief introduction to the terminology employed with pulse waveforms and the response of some fundamental conﬁgurations to the application of such signals. Although the application of sinusoidal signals will raise the required math level. the chapters to follow will reveal that the waveform itself has a number of characteristics that will result in a unique response when it is applied to the basic electrical elements. as deﬁned by Faraday’s law. oil. The wide range of theorems and methods introduced for dc networks will also be applied to sinusoidal ac systems. In addition. electronic.2(a). or nuclear fusion.2 Various sources of ac power: (a) generating plant. once the notation given in Chapter 14 is understood.510 SINUSOIDAL ALTERNATING WAVEFORMS One of the important reasons for concentrating on the sinusoidal ac voltage is that it is the voltage generated by utilities throughout the world. The power to the shaft developed by one of the energy sources listed will turn a rotor (constructed of alternating magnetic poles) inside a set of windings housed in the stator (the stationary part of the dynamo) and will induce a voltage across the windings of the stator. . 13. communication. which provides an ac voltage that originates at a power plant. gas. In each case an ac generator (also called an alternator). most of the concepts introduced in the dc chapters can be applied to ac networks with a minimum of added difﬁculty. Other reasons include its application throughout electrical. Inverter (a) (b) (c) (d) (e) FIG. such a power plant is most commonly fueled by water power.

13.SINUSOIDAL ac VOLTAGE CHARACTERISTICS AND DEFINITIONS 511 e N df dt Through proper design of the generator. recreational vehicles (RVs). and so on. Deﬁnitions The sinusoidal waveform of Fig. These terms can. 13. methods of analysis. It is important to remember as you proceed through the various deﬁnitions that the vertical scaling is in volts or amperes and the horizontal scaling is always in units of time. position. one can make available sinusoidal voltages of different peak values and different repetition rates. the dc voltage can be converted to one of a sinusoidal nature. Waveform: The path traced by a quantity. howe T1 Max T2 e1 0 t1 Em Em t2 e2 t Ep –p Max T3 FIG.2(b)] are available that run on gasoline. such as the one in Fig. such as the voltage in Fig. Sinusoidal ac voltages with characteristics that can be controlled by the user are available from function generators. be applied to any alternating waveform. 13.. Through an electronic package called an inverter. In an effort to conserve our natural resources. plotted as a function of some variable such as time (as above). make frequent use of the inversion process in isolated areas. a sinusoidal ac voltage is developed that can be transformed to higher levels for distribution through the power lines to the consumer.3 Important parameters for a sinusoidal voltage. Through light energy absorbed in the form of photons. etc. By setting the various switches and controlling the position of the knobs on the face of the instrument. degrees. The function generator plays an integral role in the investigation of the variety of theorems. an ac generator is an integral part of the design. As in the larger power plants. The turning propellers of the wind-power station [Fig. wind power and solar energy are receiving increasing interest from various districts of the world that have such energy sources available in level and duration that make the conversion process viable. For isolated locations where power lines have not been installed. 13. temperature. however. 13.2(e).3 with its additional notation will now be used as a model in deﬁning a few basic terms. solar cells [Fig. . 13. and topics to be introduced in the chapters that follow. Boats. ever.3. portable ac generators [Fig.2(d)] can generate dc voltages.2(c)] are connected directly to the shaft of an ac generator to provide the ac voltage described above. radians. 13.

4. 13. value.5(c)]. denoted by uppercase letters (such as Em for sources of voltage and Vm for the voltage drop across a load). FIG. Peak-to-peak value: Denoted by Ep-p or Vp-p. FIG.5 s [Fig. 13. 13. 13.3).3 may appear different in Fig. 21⁄2 cycles per second. The frequency of the waveform of Fig. For the waveform of Fig. denoted by lowercase letters (e1. or mean. 13. If a waveform of similar shape had a period of 0. .5 Demonstrating the effect of a changing frequency on the period of a sinusoidal waveform.512 SINUSOIDAL ALTERNATING WAVEFORMS Instantaneous value: The magnitude of a waveform at any instant of time.5(b). Period (T ): The time interval between successive repetitions of a periodic waveform (the period T1 T2 T3 in Fig. Peak value: The maximum instantaneous value of a function as measured from the zero-volt level. but they are all bounded by one period of time and therefore satisfy the deﬁnition of a cycle. T2. e2). The cycles within T1. the average value is zero volts and Em is as deﬁned by the ﬁgure. The waveform of Fig. and for Fig. 13. 13. 13. the frequency would be 2 cycles per second. the full voltage between positive and negative peaks of the waveform. and T3 of Fig. since the average value of the function is zero volts.5(a) is 1 cycle per second.3. For the waveform of Fig. 13. the peak amplitude and peak value are the same. Peak amplitude: The maximum value of a waveform as measured from its average. Cycle: The portion of a waveform contained in one period of time. that is. 13. the sum of the magnitude of the positive and negative peaks. Periodic waveform: A waveform that continually repeats itself after the same time interval. 13. Frequency ( f ): The number of cycles that occur in 1 s.3 is a periodic waveform.4 Deﬁning the cycle and period of a sinusoidal waveform.3. as long as successive similar points of the periodic waveform are used in determining T.

the precise standard of 50 Hz was reestablished and everyone was on time again. however. etc. Berlin. Imagine a product able to handle 450. Karlsruhe) (1857–94) Physicist Professor of Physics. requiring that clocks be continually reset.SINUSOIDAL ac VOLTAGE CHARACTERISTICS AND DEFINITIONS 513 The unit of measure for frequency is the hertz (Hz). as one increases. but the transmission of radio signals can occur between 3 kHz and 300 GHz.03 and 51 Hz. L. so the frequencies encompassed within each segment are quite different). In 1994.000 cycles in only 1 s—an incredible number when we compare it to the 60 Hz of our conventional power sources The new Pentium II chip manufactured by Intel can run at speeds up to 450 MHz.000 instructions per second—an incredible achievement. he demonstrated that the reﬂective and refractive properties of electromagnetic waves are the same as those for heat and light waves. Although it is numerically easy to talk about frequencies in the megahertz and gigahertz range. whose output frequency was varying between 50. He was able to measure the wavelength of the electromagnetic waves and conﬁrmed that the velocity of propagation is in the same order of magnitude as light. the other decreases by an equal amount—the two can be related by the following equation: 1 T f T 1 f Hz seconds (s) Courtesy of the Smithsonian Institution Photo No.606 Spurred on by the earlier predictions of the English physicist James Clerk Maxwell. Alarms went off too soon. FIG. VCRs clicked off before the end of the program. a frequency spectrum from 1 GHz to 1000 GHz can be scaled off on the same axis. and C elements. 13. where 1 hertz (Hz) 1 cycle per second (c/s) (13. Since the frequency is inversely related to the period—that is.1) German (Hamburg. The result was that clocks were gaining as much as 4 minutes a day. Berlin.6 Heinrich Rudolph Hertz. A number of terms in the various spectrums are probably familiar to the reader from everyday experiences. Note that the audio range (human ear) extends from only 15 Hz to 20 kHz. microwave.000. etc.7. keep in mind that a frequency of 100 MHz. Other frequencies of particular interest (TV. 66. As with all standards. In 1993.3) . represents a sinusoidal waveform that passes through 100. as shown in Fig.. 13. received all its power from eastern plants. It was indeed unfortunate that such an ingenious. when power was linked with the rest of Europe. f (13. In addition. Karlsruhe Polytechnic and University of Bonn The unit hertz is derived from the surname of Heinrich Rudolph Hertz (Fig. Heinrich Hertz produced electromagnetic waves in his laboratory at the Karlsruhe Polytechnic while in his early 30s.6). industrious individual should pass away at the very early age of 37 due to a bone disease. The frequency standard for North America is 60 Hz. 13.000. The rudimentary transmitter and receiver were in essence the ﬁrst to broadcast and receive radio waves.2) or T (13. whereas for Europe it is predominantly 50 Hz.) are also included for reference purposes. Using a log scale (described in detail in Chapter 21). CB. who did original research in the area of alternating currents and voltages and their effect on the basic R. The uniform process of deﬁning the intervals of the radio-frequency spectrum from VLF to EHF is quite evident from the length of the bars in the ﬁgure (although keep in mind that it is a log scale. for instance. any variation from the norm will cause difﬁculties. Germany.

) 30 MHz – 300 MHz (Very High Freq.) 300 kHz – 3 MHz (Medium Freq.45 GHz Infrared FIG.) 3 kHz – 30 kHz (Very Low Freq.) 3 MHz – 30 MHz (High Freq.514 SINUSOIDAL ALTERNATING WAVEFORMS Microwave Microwave oven EHF 30 GHz – 300 GHz (Extremely High Freq.) 30 kHz – 300 kHz (Low Freq.) Radio frequencies (spectrum) 3 kHz – 300 GHz Audio frequencies 15 Hz – 20 kHz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz 100 GHz 1000 GHz f (log scale) FM 88 MHz – 108 MHz TV channels (2 – 6) 54 MHz – 88 MHz TV channels (7 – 13) 174 MHz – 216 MHz TV channels (14 – 83) 470 MHz – 890 MHz CB 26.) 3 GHz – 30 GHz (Super-High Freq.4 MHz Shortwave 1. 13.9 MHz – 27.7 Areas of application for speciﬁc frequency bands.) SHF UHF VHF HF MF LF VLF 300 MHz – 3 GHz (Ultrahigh Freq. .5 MHz – 30 MHz Cordless telephones 46 MHz – 49 MHz Pagers VHF 30 MHz – 50 MHz Pagers UHF 405 MHz – 512 MHz Countertop microwave oven 2.

Horizontal sensitivity = 50 s/div. 13.8.1 V div. 4 div.3.9 and the indicated sensitivities. Virtually all oscilloscope screens are cut into a crosshatch pattern of lines separated by 1 cm in the vertical and horizontal directions. the polarity and current direction will be for an instant of time in the positive portion of the sinusoidal waveform. b. determine the period.10 (a) Sinusoidal ac voltage sources. 13.2. Solution: From the ﬁgure. FIG. 50 ms div. In each case. This is shown in Fig. (b) sinusoidal current sources. that is. A lowercase letter is employed for each to indicate that the quantity is time dependent. 1000 Hz.SINUSOIDAL ac VOLTAGE CHARACTERISTICS AND DEFINITIONS 515 EXAMPLE 13.8 Example 13.3 The oscilloscope is an instrument that will display alternating waveforms such as those described above. frequency. Solutions: a. T 1 f 1 60 Hz 0. 200 ms s 5 kHz The vertical height above the horizontal axis encompasses 2 divisions. Therefore.9 with the indicated vertical and horizontal sensitivities. 13. For the pattern of Fig. T 1 f 1 1000 Hz 10 3 s 1 ms 0 5 15 25 35 t (ms) EXAMPLE 13. The vertical sensitivity deﬁnes the voltage associated with each vertical division of the display. Vm 2 div.9 Example 13.1 V/div.10 with the symbols for the sinusoidal ac voltage and current. The period is therefore T and the frequency is f 1 T 200 1 10 6 Vertical sensitivity = 0. and FIG. 13.67 ms e 10 V (a recurring value since 60 Hz is so prevalent) b. Solution: One cycle spans 4 divisions. A sinusoidal pattern appears on the oscilloscope of Fig. its magnitude will change with time. 13. and peak value of the waveform. T f 1 T 20 (25 ms 1 10 3 5 ms) 50 Hz 20 ms.2 V e i Deﬁned Polarities and Direction In the following analysis. 0. we will ﬁnd it necessary to establish a set of polarities for the sinusoidal ac voltage and a direction for the sinusoidal ac current. + t e t i – (a) (b) FIG. s EXAMPLE 13. 13.1 Find the period of a periodic waveform with a frequency of a. 13. 60 Hz. 0.01667 s or 16. The horizontal sensitivity deﬁnes the time period associated with each horizontal division of the display.2 Determine the frequency of the waveform of Fig. .

12 Sine wave and cosine wave with the horizontal axis in degrees.11 The sine wave is the only alternating waveform whose shape is not altered by the response characteristics of a pure resistor. such would not be the case. 13. 13. respectively) for each will also have sinusoidal characteristics. 13. since the waves differ only by a 90° shift on the horizontal axis. there are 2p rad around a 360° circle. coil. Note in the last sentence the absence of the term sinusoidal before the phrase ac networks. This phrase will be used to an increasing degree as we progress. FIG. or capacitor is sinusoidal in nature. L. If a square wave or a triangular wave were applied. It is deﬁned by a quadrant of a circle such as in Fig. as shown in Fig. + R. 13. If we deﬁne x as the number of intervals of r (the radius) around the circumference of the circle. if the voltage across (or current through) a resistor. as shown in Fig.13 Deﬁning the radian. It must be pointed out that the above statement is also applicable to the cosine wave.11.12 is the degree. whether smooth or discontinuous. and FIG. inductor. the resulting current (or voltage. however. as shown in Fig. or C v 13. 13. A second unit of measurement frequently used is the radian (rad). sinusoidal is to be understood unless otherwise indicated. and C elements. The sinusoidal waveform is of particular importance. or capacitor.12. since it lends itself readily to the mathematics and the physical phenomena associated with electric circuits. .4) r 1 radian 57. 2p rad 360° (13. 13.3 t THE SINE WAVE – FIG. Consider the power of the following statement: The sine wave is the only alternating waveform whose shape is unaffected by the response characteristics of R. 13. 13. The unit of measurement for the horizontal axis of Fig. The terms deﬁned in the previous section can be applied to any type of periodic waveform.13 where the distance subtended on the circumference equals the radius of the circle.14 There are 2p radians in one full circle of 360°.14.516 i SINUSOIDAL ALTERNATING WAVEFORMS t The need for deﬁning polarities and current direction will become quite obvious when we consider multisource ac networks. L.296° r FIG. then C and we ﬁnd x 2p 2pr x⋅r Therefore. In other words. 13.

we ﬁnd p 90°: Radians (90°) 180° p 30°: Radians (30°) 180° p 180° p rad: Degrees 3 p 3 3p 180° 3p rad: Degrees 2 p 2 p rad 2 p rad 6 60° 270° Using the radian as the unit of measurement for the abscissa.8) . The quantity p is the ratio of the circumference of a circle to its diameter. A sampling of the effort appears below: p 3.5) A number of electrical formulas contain a multiplier of p. 13.15. 13. can be determined from the following equation: distance (degrees or radians) time (seconds) v.6) Degrees 180° p (radians) (13. we would obtain a sine wave. Starting as shown in Fig. The velocity with which the radius vector rotates about the center.14. we will trace a complete sinusoidal waveform after the radius vector has completed a 360° rotation about the center.14159 26535 89793 23846 26433 . 13. as shown in Fig. Sine wave 5 4 0 4 2 3 4 3 2 7 4 2 (rad) FIG. .7) Applying these equations. etc. Although the approximation p 3. i. . It does not. The conversion equations between the two are the following: p 180° Radians (degrees) (13.14 is often applied. called the angular velocity.16(a) and plotting the amplitude (above and below zero) on the coordinates drawn to the right [Figs.15 Plotting a sine wave versus radians.3° (13. Angular velocity (13. all the calculations in this text will use the p function as provided on all scientiﬁc calculators. 13. it is sometimes preferable to measure angles in radians rather than in degrees.296° 57. 13. For 180° and 360°. the two units of measurement are related as shown in Fig. For this reason. It is of particular interest that the sinusoidal waveform can be derived from the length of the vertical projection of a radius vector rotating in a uniform circular motion about a ﬁxed point.THE SINE WAVE 517 with 1 rad 57.16(b) through (i)]. p has been determined to an extended number of places primarily in an attempt to see if a repetitive sequence of numbers appears.

16 Generating a sinusoidal waveform through the vertical projection of a rotating vector. (b) = 45° 0° 45° (c) = 90° 0° 90° (d) = 135° 0° 45° 90° 135° (e) = 180° 0° 180° = 225° (f) 0° 225° = 270° (g) 0° 270° = 315° (h) 315° 0° Sine wave = 360° (i) 225° 270° 315° 360° 0° 45° 90° 135° 180° T (period) FIG. 13.518 SINUSOIDAL ALTERNATING WAVEFORMS (a) = 0° 0° Note equality. .

In Fig. this equation states that the smaller the period of the sinusoidal waveform of Fig.16(i). (13. f 1/T.12) This equation states that the higher the frequency of the generated sinusoidal waveform.7) must be applied. the angle a obtained using Eq. Substituting. 13.4 Determine the angular velocity of a sine wave having a frequency of 60 Hz.57 10 3 2p rad 500 rad/s s 12.5 Determine the frequency and period of the sine wave of Fig. Solution: Since q T and 2p q f 1 T 2p/T. (13.17(b). 13. the higher must be the angular velocity. EXAMPLE 13. The importance of remembering the above will become obvious in the examples to follow.16(i).10) Since q is typically provided in radians per second. If a is required in degrees. the greater must be the angular velocity of the rotating radius vector. where for the same radius vector.11) and (13. or the smaller the time interval before one complete cycle is generated. Thus. Equation (13. (a recurring value due to 60-Hz predominance) EXAMPLE 13. We can now go one step further and apply the fact that the frequency of the generated waveform is inversely related to the period of the waveform.THE SINE WAVE 519 Substituting into Eq.17. The radians subtended in this time interval are 2p.9) and a (13. Equations (13. q 100 rad/s and 500 rad/s. 13. q 2pf (rad/s) (13.12) are veriﬁed somewhat by Fig. Certainly this statement agrees with what we have learned thus far.57 ms 79.11) In words. 2p rad 500 rad/s 1 12.10) is usually in radians. 13. 13. that is. we have a t qt q (13. Solution: q 2pf (2p)(60 Hz) 377 rad/s FIG.8) and assigning the Greek letter omega (q) to the angular velocity. 13.58 Hz .17 Demonstrating the effect of q on the frequency and period. the time required to complete one revolution is equal to the period (T) of the sinusoidal waveform of Fig.16. we have q 2p T (rad/s) (13.

However. the longer the radius vector is permitted to rotate (that is. Relating this statement to the sinusoidal waveform. the longer the time. one might be tempted to interpret the answer as 1.10): a qt. the greater the num- .16 will pass is determined by the angular velocity of the rotating vector and the length of time the vector rotates. FIG. For example. a (°) 180° (1.885°. (13.85 ms EXAMPLE 13. for a particular angular velocity (ﬁxed q). the greater the value of t). (13. determine how long it will take the sinusoidal waveform to pass through an angle of 90°. the greater will be the number of degrees or radians through which the vector will pass.885 rad If not careful. or 10 3 (2p)(60 Hz)(5 s) 1.18. 13. and t a q 90°) since q is in radians per However. Solution: a Eq. The equation a qt states that the angle a through which the rotating vector of Fig. a must be substituted as p/2 ( second: t a q p/2 rad 200 rad/s p 400 s 7. Solution: Eq.6 Given q 200 rad/s.885 rad) p rad 108° 13.11): a 2pft qt.4 GENERAL FORMAT FOR THE SINUSOIDAL VOLTAGE OR CURRENT The basic mathematical format for the sinusoidal waveform is Am sin a (13.18 Basic sinusoidal function. 13.7 Find the angle through which a sinusoidal waveform of 60 Hz will pass in a period of 5 ms.13) where Am is the peak value of the waveform and a is the unit of measure for the horizontal axis. for a particular angular velocity.520 SINUSOIDAL ALTERNATING WAVEFORMS EXAMPLE 13. 13. as shown in Fig.

This format is particularly important since it presents the sinusoidal voltage or current as a function of time. which is the horizontal scale for the oscilloscope.8p .8p. at any time t. First. etc. the general format of a sine wave can also be written Am sin qt (13. . (13. respectively.6428) 3. the greater the angular velocity. for a particular current level.8p) p 5(0.GENERAL FORMAT FOR THE SINUSOIDAL VOLTAGE OR CURRENT 521 ber of cycles shown.214 V 5 sin a.8 Given e 0. EXAMPLE 13. The angle at which a particular voltage level is attained can be determined by rearranging the equation e in the following manner: sin a which can be written a sin 1 Em sin a e Em e Em (13. For a ﬁxed time interval.5878) 144° 2.). a (°) and e 180° (0. be sure that the calculator is in the RAD mode.16) is available on all scientiﬁc calculators. Then simply enter the radian measure and use the appropriate trigonometric key (sin. and the lowercase letters i and e represent the instantaneous value of current or voltage.10).939 V 40°. the greater the number of cycles generated. tan. a The function sin 1 sin 1 i Im (13. For electrical quantities such as current and voltage.15) Similarly. 5 sin 40° 5(0. cos. Recall that the horizontal sensitivity of a scope is in time per division and not degrees per centimeter. Due to Eq. determine e at a 40° and a 5 sin 144° The conversion to degrees will not be required for most modern-day scientiﬁc calculators since they can perform the function directly. Solution: For a For a e 0.14) with qt as the horizontal unit of measure. the general format is i e Im sin qt Em sin qt Im sin a Em sin a where the capital letters with the subscript m represent the amplitude.

The second intersection is determined by a2 180° 23.10): a qt.411 rad 1. See Fig. (Note that no calculations are required. but may require two. (13.522 SINUSOIDAL ALTERNATING WAVEFORMS EXAMPLE 13.578°) 180° 0. six.10. horizontal axis in radians. angle (a) in degrees.422° 4 10 0 1 90° 2 180° t1 t2 In general. 13.411 rad 377 rad/s 0.24 ms 377 rad/s q FIG. Determine the angle at which the magnitude of the sinusoidal function v 10 sin 377t is 4 V.10.73 rad a 7.15) and (13. 10 sin 314t with the abscissa FIG. and so t a/q. a (rad) t2 p (156. or perhaps an inﬁnite number of terms to be represented accurately. Any alternating waveform whose characteristics differ from those of the sine wave cannot be represented by a single term. four. (Once the relationship between degrees and radians is understood.) .73 rad 180° 2. 13. a (rad) and t1 a q p (23.16) will provide an angle with a magnitude between 0° and 90°. However. Solutions: a. take special note of the relative simplicity of the mathematical equation that can represent a sinusoidal waveform.10.15): a1 v (V) sin 1 v Em sin 1 4V 10 V sin 1 0. Thus.9 a. b.578° However.10 Sketch e a. but the most direct route is simply to ﬁnd the period T from T 1/f and break it up into the required intervals. b. c.422°) 2. The time period for each interval can be determined from t a/q. 13. Determine the time at which the magnitude is attained. See Fig 13. Before reviewing the example. angle (a) in radians. time (t) in seconds. For the second intersection. a must be in radians. therefore. b.578° 156. Figure 13. This latter technique will be demonstrated in Example 13. keep in mind that Equations (13.09 ms FIG.19 Example 13. Solutions: a. The sine wave can also be plotted against time on the horizontal axis. EXAMPLE 13. 13. Eq.21.20 Example 13. (13.9.21 Example 13. Eq. there is again no need for calculations. horizontal axis in degrees.4 23.20.19 reveals that the magnitude of 4 V (positive) will be attained at two points between 0° and 180°. Additional description of nonsinusoidal waveforms can be found in Chapter 24.) b.

19) FIG.22. the expression is Am sin(qt v) (13.17) FIG. determine i at t s) 2 rad Am Am sin ( – ) 13. If the waveform passes through the horizontal axis with a positivegoing (increasing with time) slope before 0°. 13.23. See Fig. 13.25 Phase relationship between a sine wave and a cosine wave.18) Am v (p + v) (2p + v) – Am sin v At qt a 0°. by a trigonometric identity. horizontal axis in milliseconds.11 Given i 2 ms.5 PHASE RELATIONS (2 – ) Thus far. that is. we have considered only sine waves that have maxima at p/2 and 3p/2. and 2p. Solution: a a (°) i qt 1000t (1000 rad/s)(2 180° (2 rad) 114. is Am sin v. 13. If the waveform crosses the horizontal axis with a positive-going slope 90° (p/2) sooner.20) FIG.23 Deﬁning the phase shift for a sinusoidal function that crosses the horizontal axis with a positive slope before 0°. as shown in Fig.59° p rad (6 10 3)(sin 114. where v is the angle in degrees or radians that the waveform has been shifted.22 Example 13. 13.59°) (6 mA)(0. 13.46 mA 10 3 6 10 3 sin 1000t. the expression is Am sin(qt v) (13. 13. p. it is called a cosine wave. . as shown in Fig.24 Deﬁning the phase shift for a sinusoidal function that crosses the horizontal axis with a positive slope after 0°. EXAMPLE 13. which. the magnitude is determined by Am sin v.25. 360°: T 180°: 90°: 30°: T 2 T 4 T 12 2p 2p 20 ms 314 q 20 ms 10 ms 2 20 ms 5 ms 4 20 ms 1.PHASE RELATIONS 523 c. as shown in Fig. with a zero value at 0. 13.24. the expression becomes Am sin(qt v) (13.21. If the waveform passes through the horizontal axis with a positive-going slope after 0°. And at qt a 0°.67 ms 12 FIG. as shown in Fig. If the waveform is shifted to the right or left of 0°. p 2 Am cos p 2 sin p 3p 2 2p –p 2 90° 0 sin(qt 90°) sin qt cos qt (13. 13. the magnitude is Am sin( v). 13.9093) 5.10.

therefore. In Fig. .23) If a sinusoidal expression should appear as e Em sin qt the negative sign is associated with the sine portion of the expression. 13. starting at the sin a position.524 SINUSOIDAL ALTERNATING WAVEFORMS or sin qt cos(qt 90°) cos qt p 2 (13. the expression. cos a sin(a 90°). not the peak value Em. For sin a we must travel 180° in the counterclockwise (or clockwise) direction so that sin a sin(a 180°). one should be aware that sin( a) cos( a) sin a cos a (13. 13.21) + cos α – sin α – cos α FIG. would be written e Since sin qt sin(qt 180°) Em( sin qt) the expression can also be written e Em sin(qt 180°) revealing that a negative sign can be replaced by a 180° change in phase angle ( or ).26 Graphic tool for ﬁnding the relationship between speciﬁc sine and cosine functions. Therefore. In other words. The 90° is referred to as the phase angle between the two waveforms. the waveforms are out of phase by 90°. + sin α The terms lead and lag are used to indicate the relationship between two sinusoidal waveforms of the same frequency plotted on the same set of axes. that is. For instance. we ﬁnd that cos a is an additional 90° in the counterclockwise direction. and so on.26. two correct mathematical representations for the functions. If both waveforms cross the axis at the same point with the same slope. Note that the phase angle between the two waveforms is measured between those two points on the horizontal axis through which each passes with the same slope. if not for convenience. they are in phase. There are.22) sin(a 90°) In addition. as listed below: cos a sin a sin a cos a sin(a cos(a sin(a sin(a 90°) 90°) 180°) 270°) etc. In language commonly applied. e Em sin qt Em sin(qt Em sin(qt 180°) 180°) A plot of each will clearly show their equivalence.25. The geometric relationship between various forms of the sine and cosine functions can be derived from Fig. the cosine curve is said to lead the sine curve by 90°. 13. (13. and the sine curve is said to lag the cosine curve by 90°.

i 15 sin(qt 60°) v 10 sin(qt 20°) c. i 2 cos(qt 10°) v 3 sin(qt 10°) d. or v lags i by 40°. EXAMPLE 13. i leads v by 40°.12. i 2 cos(qt 60°) v 3 sin(qt 150°) Solutions: a. i leads v by 80°. b. i leads v by 80°. or v lags i by 80°. 13.12 What is the phase relationship between the sinusoidal waveforms of each of the following sets? a. i sin(qt 30°) v 2 sin(qt 10°) e. v 10 sin(qt 30°) i 5 sin(qt 70°) b. See Fig.27 Example 13. 13. 13.28 Example 13. See Fig. v 10 5 40° 30° 70° i 0 2 3 2 2 t FIG. and by how many degrees or radians. .28.27. i v 10 15 0 – 2 60° 2 20° 3 2 2 t 80° FIG.12. i leads v by 40°. 13.PHASE RELATIONS 525 The phase relationship between two waveforms indicates which one leads or lags.

v and i are in phase.29 Example 13. i 2 cos(qt 2 sin(qt 2 sin(qt i leads v by 110°. 13. See Fig. d. 13. 13. v i 2 2 1 3 2 200° 360° 2 0 2 10° 150° 160° 5 2 3 t – FIG. 13. Or using Note sin(qt 30° 180°) sin(qt 210°) i leads v by 200°. i leads v by 110°. or v lags i by 110°.31. sin(qt 30°) Note sin(qt 30° 180°) sin(qt 150°) v leads i by 160°. See Fig.12. e. See Fig. or v lags i by 200°.12.31 Example 13.30 Example 13. By choice sin(qt 30°) i 2 cos(qt 60°) 2 cos(qt 2 cos(qt 60° 180°) 240°) v 3 3 2 2 5 2 3 2 i – 0 2 2 150° t FIG. i v 0 2 110° 10° 2 3 10°) 10° 90°) 100°) 2 100° – 3 2 2 t FIG. . 13.12. or i lags v by 160°.30. v leads i by 160°.526 SINUSOIDAL ALTERNATING WAVEFORMS c.29. 13.

for example.) (5 div. Substituting into Eq. the average height of the sand may be required to determine the volume of sand available. (13. the longer the distance. Quite obviously.6 AVERAGE VALUE Height Even though the concept of the average value is an important one in most technical ﬁelds. The phase shift between the waveforms (irrespective of which is leading or lagging) is 2 divisions. its true meaning is often misunderstood. In Fig. permitting the use of either waveform to determine the period. of div.) 360° (13. Since the full period represents a cycle of 360°. The result of an increased distance is as shown in Fig. Sand Distance (a) Height Average height Sand Same distance (b) FIG. The average height of the sand is that height obtained if the distance from one end to the other is maintained while the sand is leveled off. 13.AVERAGE VALUE 527 However. 13. First.) v phase shift (no. 13. and v phase shift (no.) T (no.33(b) as determined by A b h.32.32. 13. note that each sinusoidal function has the same frequency. 13. the equation for determining the phase angle can be introduced using Fig. 13.33. The area under the mound of Fig. 13.33. the depth (into the page) of the sand must be the same for Fig. of div.24) will result in v and e leads i by 144°. of div.13. However. so that 2 cos(qt cos a 240°) sin(a 90°) 240° 150°) 90°) 2 sin(qt 2 sin(qt v and i are in phase.24) can be derived] can be formed: 360° T (no. the lower is the average value. 13.) 360° 144° 13.33(a).) e i θ T Vertical sensitivity = 2 V/div. 13. 13. Of course.33(a) and (b) for the preceding conclusions to have any meaning. In Fig. The situation could be one where a landscaper would like to know the average height of the sand if spread out over a distance such as deﬁned in Fig.24) FIG. For the waveform chosen in Fig. 13. The average height has decreased compared to Fig. the following ratio [from which Equation (13.33 the distance was measured from one end to the other. 13. 13.33 Deﬁning average value. as shown in Fig.34(a) the distance extends beyond the end of the original pile of Fig. therefore. 13. 13. . of div.2 ms/div.33(b). In Fig.32 Finding the phase angle between waveforms using a dual-trace oscilloscope. Phase Measurements The hookup procedure for using an oscilloscope to measure phase angles is covered in detail in Section 15.2 ms/div. the period encompasses 5 divisions at 0.34(b). Horizontal sensitivity = 0.33(a) will then equal the area under the rectangular shape of Fig.34(a). (2 div.

if a person traveled 225 mi in 5 h. 13. the average speed was 225 mi/5 h. as shown in Fig.25) Average speed Sand Ground level Distance (a) Height (50 mi/h)(2. Height Average speed (13. 13. some of the sand will be used to ﬁll the depression. resulting in an average value at ground level (or zero volts for a sinusoidal voltage over one full period). 13. below. By ﬁnding the total area under the curve for the 5 h and then dividing the area by 5 h (the total time for the trip). the depression would have the same shape as the mound of sand (over one full cycle). since some area contributions will be from below the horizontal axis.36. area under curve length of curve A2 5h (60 mi/h)(2 h) A1 225 mi/h 5 45 mi/h Equation (13. After traveling a considerable distance by car. some drivers like to calculate their average speed for the entire trip.25) can be extended to include any variable quantity. we obtain the same result of 45 mi/h.35(b). For a sinusoidal waveform. and those below.528 SINUSOIDAL ALTERNATING WAVEFORMS Height Sand Distance (a) Height Average height Sand Same distance (b) If the distance parameter includes a depression.36 Plotting speed versus time for an automobile excursion. 13. the average value is .35(a). or 45 mi/h. resulting in an even lower average value for the landscaper.35 Effect of depressions (negative excursions) on average value. In other words. if we let G denote the average value. For example. as follows: algebraic sum of areas length of curve FIG. over a complete cycle. such as current or voltage. A positive average value will then be above the axis. as shown in Fig. a negative sign.5 h) 5h Average height Sand Same distance (b) G (average value) (13. The average value of any current or voltage is the value indicated on a dc meter. The algebraic sum of the areas must be determined. as shown in Fig.34 Effect of distance (length) on average value. Average speed A1 A2 2 3 Lunch break 4 5 6 t (h) 1 FIG. This is usually done by dividing the miles traveled by the hours required to drive that distance.26) Speed (mi/h) 70 60 50 40 30 20 10 0 FIG. 13. that is. and a negative value. Areas above the axis will be assigned a positive sign. 13. This same distance may have been traveled at various speeds for various intervals of time.

Fig. 13. 13. part (a). 13.37.13 Determine the average value of the waveforms of Fig.14 Find the average values of the following waveforms over one full cycle: a. By inspection. EXAMPLE 13. v2 (Square wave) 14 V v1 10 V 0 1 2 3 4 t (ms) 0 1 2 3 4 t (ms) –10 V (a) FIG.37(a) with a dc shift of 4 V. 13.39 Example 13. In reality. 13.38. 13. 13. v2 v1 4V FIG.39. the area above the axis equals the area below over one cycle. Fig. Using Eq. v (V) 1 cycle 3 0 4 8 t (ms) EXAMPLE 13.37(b). b. resulting in an average value of zero volts. both dc and ac sources of voltage will be applied to the same network. 13. –1 FIG. . (13.AVERAGE VALUE 529 the equivalent dc value.26): G (14 V)(1 ms) (6 V)(1 ms) 2 ms 8V 14 V 6 V 4V 2 2 14 V 4V 0 –6 V 1 2 3 4 t (ms) as shown in Fig. In the analysis of electronic circuits to be considered in a later course.37 Example 13. (13. 13.26): G (10 V)(1 ms) (10 V)(1 ms) 2 ms 0 0V 2 ms b.40.37(b) is simply the square wave of Fig. the waveform of Fig.14. that is.38 Deﬁning the average value for the waveform of Fig.13. 13. Using Eq. It will then be necessary to know or determine the dc (or average value) and ac components of the voltage or current in various parts of the system. –6 V (b) Solutions: a.

40 Example 13.6 10 t (ms) Note Fig.43 Approximating the shape of the positive pulse of a sinusoidal waveform with two right triangles.6 + dc ammeter (between 0 and 10 ms) Note Fig. 13. vav (V) 1 0 1V Solutions: a. We found the areas under the curves in the preceding example by using a simple geometric formula.530 SINUSOIDAL ALTERNATING WAVEFORMS i (A) 1 cycle 4 0 –2 2 4 6 8 10 t (ms) –10 FIG. FIG.14. G (3 V)(4 ms) (1 V)(4 ms) 8 ms 12 V 8 4V 1V 8 t (ms) dc voltmeter (between 0 and 8 ms) FIG. G (10 V)(2 ms) 20 V 8V 10 (4 V)(2 ms) (2 V)(2 ms) 10 ms 16 V 4V 1.44 A better approximation for the shape of the positive pulse of a sinusoidal waveform. Approximating this waveform by two triangles (Fig. however. 13. we obtain (using area 1/2 base height for the area of a triangle) a rough idea of the actual area: FIG.41 The response of a dc meter to the waveform of Fig.40.43). 13.42.094Am which is certainly close to the actual area. For irregular waveforms.6 V 10 – –1. 13. 13. the area of the positive (or negative) pulse of a sine wave is 2Am. 13.42 The response of a dc meter to the waveform of Fig. we must ﬁnd the area by some other means. b h Area shaded 1 2 bh 2 1. If we should encounter a sine wave or any other unusual shape. For example.58Am 2 1 2 p (Am) 2 p Am 2 A closer approximation might be a rectangle with two similar triangles (Fig. 13. 13.41. 13.44): Area Am p 3 2 1 bh 2 Am p 3 p Am 3 2 pAm 3 2. part (b). . b. 13. 13. the area of which we already know through simple geometric formulas. The procedure of calculus that gives the exact solution 2Am is known as integration.39. this method can be especially useful if data such as the average value are desired. Integration is presented here only to make the FIG. iav (A) 0 –1. an exact answer of 2Am could be obtained. If an inﬁnite number of forms were used. We can obtain a good approximation of the area by attempting to reproduce the original wave shape using a number of small rectangles or other familiar shapes.

27) Since we know the area under the positive (or negative) pulse. we have p Area 0 Am sin a da where ∫ is the sign of integration.26): G 2Am p G and G 0.AVERAGE VALUE 531 method recognizable to the reader. Finding the area under the positive pulse of a sine wave using integration.15 Determine the average value of the sinusoidal waveform of Fig. 13. 1 cycle EXAMPLE 13.16 Determine the average value of the waveform of Fig.46. 13. (13. 13. 18 mV/2 9 mV. 0 Am π Solution: By inspection it is fairly obvious that Am 2π α the average value of a pure sinusoidal waveform over one full cycle is zero. Counting down 9 mV from 2 mV (or 9 mV up from 16 mV) results in an average or dc level of 7 mV.47.45 Finding the average value of one-half the positive pulse of a sinusoidal waveform.637Am 0 p Am (13. 0 and p are the limits of integration.16. 0 t – 16 mV FIG. . Integrating. it is not necessary to be proﬁcient in its use to continue with this text. The peak amplitude of the sinusoidal waveform is. 13.46 Example 13.45. Am sin a is the function to be integrated. 13.15.47 Example 13. (13.47. Eq. It is a useful mathematical tool. we obtain Area Am[ cos a]p 0 Am(cos p cos 0°) Am[ 1 ( 1)] Am( 2) Area 2Am 0 p Am (13. +2 mV EXAMPLE 13. 13. 13. Solution: The peak-to-peak value of the sinusoidal function is 16 mV 2 mV 18 mV.26): G 2Am 2Am 2p 0V v FIG. and da indicates that we are integrating with respect to a. G (2Am /2) p/2 2Am p (average the same as for a full pulse) FIG.28) For the waveform of Fig. however. and should be learned. as noted by the dashed line of Fig. we can easily determine the average value of the positive (or negative) region of a sine wave pulse by applying Eq. therefore.

2.532 SINUSOIDAL ALTERNATING WAVEFORMS v (V) 1 cycle 10 Sine wave 0 p 2p 1 EXAMPLE 13. An upward shift is a positive voltage (higher potential at the red or positive lead of the oscilloscope). Occasionally. EXAMPLE 13. the average value is positive and in the vicinity of 2 mV. (b) FIG. If a dc voltage is present. Multiplying the shift by the vertical sensitivity will result in the dc voltage. 13.5 div. the horizontal line will shift up or down. 13.50 Using the oscilloscope to measure dc voltages: (a) setting the GND condition. 13. 13.48. judgments of this type will have to be made. while a downward shift is a negative voltage (lower potential at the red or positive lead of the oscilloscope). and read the voltage or current levels. Solution: G 2Am 0 2p 2(10 V) 2p 3.50(b). First choose GND from the DC-GND-AC option list associated with each vertical channel.17 Determine the average value of the waveform of Fig. as shown in Fig. . (b) the vertical shift resulting from a dc voltage when shifted to the DC option.48 Example 13.18 V FIG.50(a). Oscilloscopes are limited to voltage levels using the sequence of steps listed below: 1. (a) Vertical sensitivity = 50 mV/div.17. simply set the DMM on dc. and switch to the DC option. Solution: From the appearance of the waveform. Shift = 2. determine whether the average value is positive or negative. Apply the oscilloscope probe to the voltage to be measured (if not already connected).18 For the waveform of Fig. t v (mV) 10 mV 0 Instrumentation The dc level or average value of any waveform can be found using a digital multimeter (DMM) or an oscilloscope.49. 13. 13.49 Example 13. 13. For purely dc circuits. The GND option blocks any signal to which the oscilloscope probe may be connected from entering the oscilloscope and responds with just a horizontal line. Set the resulting line in the middle of the vertical axis on the horizontal axis. as demonstrated in Fig.18. and determine its approximate value. FIG.

Vdc (vertical shift in div. and note the shift in the chosen level of part 2.51 Determining the average value of a nonsinusoidal waveform using the oscilloscope: (a) vertical channel on the ac mode. DMMs can read the average or dc level of any waveform by simply choosing the appropriate scale. (b) vertical channel on the dc mode.51(b).) 125 mV The oscilloscope can also be used to measure the dc or average level of any waveform using the following sequence: 1. For the future.AVERAGE VALUE 533 In general. keep in mind that the computer will distribute the waveform above and below the horizontal axis such that the average value is zero. the area above the axis will equal the area below. 13. 3. (a) (b) FIG.9 div. reset the horizontal line to the middle of the screen. as shown in Fig.29) For the waveform of Fig. components will be displayed).) (13. the average value is about Vav Vdc (0.) 4.50(b).51(b).)(5 V/div.5 div. Then switch to DC (to permit both the dc and the ac components of the waveform to enter the oscilloscope). Switch to AC (all dc components of the signal to which the probe is connected will be blocked from entering the oscilloscope— only the alternating. 13. or changing. Note the location of some deﬁnitive point on the waveform. that is. . The procedure outlined above can be applied to any alternating waveform such as the one in Fig.9 div. In some cases the average value may require moving the starting position of the waveform under the AC option to a different region of the screen or choosing a higher voltage scale. that is. note its position on the vertical scale. 13. 13. 13. For the waveform of Fig.) (vertical sensitivity in V/div. Vdc (2.49. 13.)(50 mV/div.29) can then be used to determine the dc or average value of the waveform. 2.5 V Reference level Shift = 0. whenever you use the AC option. such as the bottom of the half-wave rectiﬁed waveform of Fig. Using the GND option. Equation (13.51(a).

The temperature reached by the water is now determined by the ac power dissipated in the form of heat by the resistor.52. A resistor in a water bath is connected by switches to a dc and an ac supply. 13. determined by the resistance R and battery voltage E. The temperature reached by the water is determined by the dc power dissipated in the form of heat by the resistor. during the positive or negative portions of a sinusoidal ac current. the net current in any one direction is zero (average value 0)? It would almost appear that the power delivered during the positive portion of the sinusoidal waveform is withdrawn during the negative portion. The net power ﬂow will equal twice that delivered by either the positive or the negative regions of sinusoidal quantity.534 SINUSOIDAL ALTERNATING WAVEFORMS 13. the ac current through the resistor will have a peak value of Im. a dc current I. The power delivered at each instant will. the average electrical power delivered to the resistor R by the ac source is the same as that delivered by the dc source. The power delivered by the ac supply at any instant of time is Pac but sin2 qt 1 (1 2 cos 2qt) (trigonometric identity) (iac)2R (Im sin qt)2R (I 2 sin2qt)R m . and since the two are equal in magnitude. power is being delivered at each instant of time to the resistor. current of any magnitude through a resistor will deliver power to that resistor. vary with the magnitude of the sinusoidal ac current. but there will be a net ﬂow during either the positive or the negative pulses with a net ﬂow over the full cycle.7 EFFECTIVE VALUES This section will begin to relate dc and ac quantities with respect to the power delivered to a load.52 An experimental setup to establish a relationship between dc and ac quantities. over a full cycle. the net power delivered is zero. will be established through the resistor R. If switch 1 is closed. It will help us determine the amplitude of a sinusoidal ac current required to deliver the same power as a particular dc current. How is it possible for a sinusoidal ac quantity to deliver a net power if. A ﬁxed relationship between ac and dc voltages and currents can be derived from the experimental setup shown in Fig. If switch 2 is closed and switch 1 left open. 13. When this is accomplished. However. The question frequently arises. In other words. understand that irrespective of direction. The ac input is varied until the temperature is the same as that reached with the dc input. iac Switch 2 Switch 1 R e ac generator E Idc dc source FIG. of course.

The effective value of any quantity plotted as a function of time can be found by using the following equation derived from the experiment just described: T i2(t) dt T (13.14 A to deliver the same power to the resistor in Fig.414Eeff (13.32) and Eeff 0.34) As a simple numerical example. in words.31) or Im 2Ieff 1. Pac 2 Im 1 (1 2 cos 2qt) R and Pac 2 I mR 2 2 I mR cos 2qt 2 (13. In summary. Equating the average power delivered by the ac generator to that delivered by the dc source. Pav(ac) 2 Im R Pdc Im 0.EFFECTIVE VALUES 535 Therefore.707Im 2Idc 2 or I 2 R and dc Idc Im 2 which.36) . 2 or The equivalent dc value is called the effective value of the sinusoidal quantity. Ieq(dc) Ieff 0.707Im (13.33) or Em 2Eeff 1.52 as a dc current of 10 A. 13. states that the equivalent dc value of a sinusoidal current or voltage is 1/ 0. since the average value of a cosine wave is zero even though the wave may have twice the frequency of the original input current waveform.414Ieff (13. it would require an ac current with a peak value of 2(10) 14.35) Ieff 0 or Ieff area (i2(t)) T (13.30) The average power delivered by the ac source is just the ﬁrst term.707Em (13.707 of its maximum value.

73 V) 120 V. Determine the peak value of the applied voltage (Em) and the current (Im) if the ac source [Fig.6 W Load (a) (b) FIG. EXAMPLE 13. After i(t) is squared. 13.20 The 120-V dc source of Fig. Note that frequency did not change the effective value in (b) above as compared to (a).20.484 mA. Ieff 0. EXAMPLE 13.707(12 10 3 A) 8. The ﬁnal step is to take the square root of the mean value. Solution: For part (a).484 mA. the length of the cycle or the period of the waveform. 13. . It is then divided by T. 13. Veff 0. states that to ﬁnd the effective value. 13.53 Example 13. the function i(t) must ﬁrst be squared.54(b)] is to deliver the same power to the load.7 V 1s 2s t t (a) (b) (c) FIG. to obtain the average or mean value of the squared waveform.19. i (mA) 12 0 1s t 12 0 i (mA) v 169. For part (c).536 SINUSOIDAL ALTERNATING WAVEFORMS which. the area under the curve is found by integration.6 W to the load.53. This procedure gives us another designation for the effective value.54 Example 13. the root-mean-square (rms) value. in words. Im Idc e 120 V Em iac + – P = 3. 13. For part (b).6 W Load E P = 3.54(a) delivers 3.707(169.19 Find the effective values of the sinusoidal waveform in each part of Fig. the same as available from a home outlet. again Ieff 8.

68 V –1 EXAMPLE 13. 13.55 Example 13.414)(30 mA) (1. 13. 13.21. 13. Solution: v2 (Fig. 13. Solution: v2 (Fig.58): Veff (100)(2) 4.899 V (16)(2) 10 (4)(2) 240 10 v2 (V) 100 16 4 0 2 4 6 8 10 t (s) FIG.42 mA 169. EXAMPLE 13.22.55. . 13.58 The squared waveform of Fig. 13. (– 1)2 = 1 1 v (V) 1 cycle 4 0 –2 –10 4 6 8 10 t (s) 0 4 8 t (s) FIG.57.55.56 The squared waveform of Fig.57.56): Veff (9)(4) 8 (1)(4) 40 8 2.236 V v2 (V) 9 FIG. 13.21 Find the effective or rms value of the waveform of Fig.22 Calculate the effective value of the voltage of Fig.414)(120 V) 42. 13.57 Example 13. 13.6 W 120 V VdcIdc 3 v (V) 1 cycle 30 mA 0 4 8 t (s) (1. FIG.EFFECTIVE VALUES 537 Solution: Pdc and Idc Im Em Pdc Vdc 2Idc 2Edc 3.

the rms value is actually determined by Veff which for the above example is Veff (6 V)2 (1. that is. + 3 sin ω t + vT 7. The question arises.59.06 V)2 37. A unique situation arises if a waveform has both a dc and an ac component that may be due to a source such as the one in Fig. What is the effective value of the voltage vT? One might be tempted to simply assume that it is the sum of the effective values of each component of the waveform.5 V) 6V 1.124 V 6. 20 t (ms) 0 – 40 10 1 cycle Solution: By inspection.61 Generation and display of a waveform having a dc and an ac component.60): (1600)(10 10 3) (1600)(10 10 3) Veff 20 10 3 32. 13.59 Example 13. The effective values of sinusoidal quantities such as voltage or current will be represented by E and I. 13. 13. the peak value of a waveform will always have a subscript m associated with it: Im sin qt. This will m always be the case for any waveform that is not rectangular. 13. These symbols are the same as those used for dc voltages and currents.23.60 The squared waveform of Fig. 1600 v2 (V) 1600 (the maximum value of the waveform of Fig. VT (eff) 0. It might prove interesting to compare the effective and average values of these waveforms.7071(1.06 V 6V 7. Caution: When ﬁnding the effective value of the positive pulse of a sine wave. it must be found by a completely new integration. 13. The combination appears frequently in the analysis of electronic networks where both dc and ac levels are present in the same system. the average value is zero.23 Determine the average and effective values of the square wave of Fig. v2 (Fig.59.1 V V2 dc 2 V ac(rms) (13. 13.06 V.61.538 SINUSOIDAL ALTERNATING WAVEFORMS v (V) 40 EXAMPLE 13. 13.5 V – 6V – 0 t FIG.37) . 13.000 10 20 10 3 Veff 40 V 3 FIG. note that the squared area is not simply (2Am)2 4A2 . To avoid confusion.5 V 6V 4.60) The waveforms appearing in these examples are the same as those used in the examples on the average value. vT 0 10 20 t (ms) FIG. However.

will convert the input signal of zero average value to one having an average value sensitive to the peak value of the input signal. Fundamentally.63(a) to one having the appearance of Fig. 13. The negative portion of the input has been effectively “ﬂipped over” by the bridge conﬁguration. The conversion process is well described in most basic electronics texts.637Vm The movement of the pointer will therefore be directly related to the peak value of the signal by the factor 0. (13. 13.62 is placed between the signal to be measured and the average reading movement. 13.11 . Forming the ratio between the rms and dc levels will result in Vrms Vdc 0.63 (a) Sinusoidal input. 13.37) can be found in Chapter 24.63(a) has been replaced by a pattern having an average value determined by G 2Vm 2p 2Vm 4Vm 2p 2Vm p 0.61) and is not limited to only sinusoidal waveforms. A true rms meter will read the effective value of any waveform (such as Figs. conduction is permitted through the diodes in such a manner as to convert the sinusoidal input of Fig.49 and 13.62 Full-wave bridge rectiﬁer.63(b) is called a full-wave rectiﬁed waveform.ac METERS AND INSTRUMENTS 539 This result is noticeably less than the above solution.637Vm 1. The zero average value of Fig.707Vm 0. Since the label true rms is normally not placed on the face of the meter.8 ac METERS AND INSTRUMENTS + vmovement vi The d’Arsonval movement employed in dc meters can also be used to measure sinusoidal voltages and currents if the bridge rectiﬁer of Fig. 13. 13. it is prudent to check the manual if waveforms other than purely sinusoidal are to be encountered. 13. The resulting waveform of Fig.637.63(b). The bridge rectiﬁer. 13. Instrumentation It is important to note whether the DMM in use is a true rms meter or simply a meter where the average value is calibrated (as described in the next section) to indicate the rms level. 13. – + – FIG. The development of Eq.637Vm 2 0 –Vm (a) 2 0 (b) FIG. vi Vm Vm vmovement Vdc = 0. (b) full-wave rectiﬁed signal. composed of four diodes (electronic switches).

.38) Some ac meters use a half-wave rectiﬁer arrangement that results in the waveform of Fig. 13.64. 13. The result is Meter indication 2. can be used to measure both dc and ac voltages using a d’Arsonval movement and the proper switching networks.65). That is. the dial setting will establish the proper series resistance for the chosen scale and will permit the appropriate dc level to pass directly to the movement. The VOM.39) FIG. read the effective value of any periodic or nonperiodic waveform because a reversal in current direction reverses the ﬁelds of both the stationary and the movable coils. 13. 13.63(b) over one full cycle. 13. called the electrodynamometer movement (Fig. d’Arsonval movement rms scale (full-wave rectifier) Voltmeter (1) (a) Electrodynamometer movement rms scale dc (2) dc ac + 20 V + – Vm = 20 V – + 25 V + e = 15 sin 200t – Voltmeter (1) (b) (2) – FIG. For ac measurements. The movement can.64 Half-wave rectiﬁed signal. can measure both ac and dc quantities without a change in internal circuitry. when the meter is used for dc measurements. Inc.65 Electrodynamometer movement. so the deﬂection of the pointer is always up-scale.540 SINUSOIDAL ALTERNATING WAVEFORMS revealing that the scale indication is 1. A second movement.66 Example 13.11 (dc or average value) full-wave (13.) EXAMPLE 13. Meter indication vmovement Vm Vdc = 0.24. each setting is properly calibrated to indicate the desired quantity on the face of the instrument. which has half the average value of Fig. that is. 13. (Courtesy of Weston Instruments. 13. As discussed above.66(a) and (b).24 Determine the reading of each meter for each situation of Fig.or half-wave rectiﬁer to establish a dc level. the dial setting will introduce a network that employs a full.318Vm 2 1.22 (dc or average value) half-wave (13. introduced in Chapter 2. in fact.11 times the dc level measured by the movement. FIG.

The addition of two leads. In digital meters.67 Frequency counter. frequency. situation (1): By Eq. For a triangular input. there are no moving parts such as in the d’Arsonval or electrodynamometer movements to display the signal level.555 times the peak value. 13. It employs menu buttons to set the vertical and horizontal scales by choosing from selections appearing on the screen. but the scale factor of each input waveform must ﬁrst be known (normally provided by the manufacturer in the operator’s manual). for a sine wave input.) FIG. square. situation (1): Vrms For Fig. Inc.6 V Vdc 25 V Most DMMs employ a full-wave rectiﬁcation system to convert the input ac signal to one with an average value. it is always good practice to read (if only brieﬂy) the operator’s manual if it appears that you will use the instrument on a regular basis.14 V For Fig. the average value is sensed by a multiprocessor integrated circuit (IC). One of the most versatile and important instruments in the electronics industry is the oscilloscope. 13. 13. then it is placed around the current-carrying conductor. the scale factor for an average responding DMM on the ac rms scale will produce an indication for a square-wave input that is 1.38) is employed. For any instrument. Inc. the response is 0.66(a). that is.69 Dual-channel oscilloscope. The accuracy of this instrument is 3% of full scale at 60 Hz.707(15 V) 10. the average value is scaled up by a factor of 1.) .68 Amp-Clamp®. the level of current in rms units will appear on the appropriate scale. (Courtesy of Tektronix. Meter indication 1. For instance. 13. for the DMM of Fig. permits its use as both a voltmeter and an ohmmeter. and so on. 13. dc component.66(b). One can also store up to four measurement setups for future use. 2. Rather.11 to obtain the rms value.707Vm 0.11(20 V) 22. For frequency measurements. The analog oscilloscope of Fig.707Vm 0. Note the relative simplicity of the panel and the high degree of accuracy available. In fact.ac METERS AND INSTRUMENTS 541 Solution: For Fig.69 can display two waveforms at the same time (dual-channel) using an innovative interface (front panel).2 V For Fig. (13. situation (2): Vrms 0.66(a). 13.707 times the peak value. 13.707(20 V) 14. the response is 0. period. The Amp-Clamp® of Fig.11 times the peak value. situation (2): Vrms 0. 13. which in turn determines which digits should appear on the digital display. It provides a display of the waveform on a cathode-ray tube to permit the detection of irregularities and the determination of quantities such as magnitude. as indicated in the ﬁgure. (Courtesy of Simpson Instruments. Obviously. however. the frequency counter of Fig. Through transformer action. the same scale factor of Eq. The loop is opened by squeezing the “trigger”.67 provides a digital readout of sine.66(b).38). Inc. (13. Digital meters can also be used to measure nonsinusoidal signals. 13.68 is an instrument that can measure alternating current in the ampere range without having to open the circuit. which has already been introduced in this chapter.) FIG.27. FIG. 13. and triangular waves from 5 Hz to 100 MHz at input levels from 30 mV to 42 V. and its scales have maximum values ranging from 6 A to 300 A. (Courtesy of Tektronix.

542 SINUSOIDAL ALTERNATING WAVEFORMS A student accustomed to watching TV might be confused when ﬁrst introduced to an oscilloscope. The effect of each position is fundamentally as shown in Fig. which play a major role in power generation and distribution. In the DC mode the dc and ac components of the input signal can pass directly to the display. You will therefore ﬁnd that transformers designed for the international market where they can oper- . Another important factor in the early design stages was the effect of frequency on the size of transformers. The fact that the frequency difference is only 10 Hz reveals that there was agreement on the general frequency range that should be used for power generation and distribution. you will ﬁnd that the size of a transformer is inversely proportional to frequency. as shown in Fig. that is often ignored or treated too lightly in the early stages of scope utilization. In the GND position the input signal is prevented from reaching the scope display by a direct ground connection. 13. there really wouldn’t be a noticeable difference between 50 and 60 cycles per second based on this criterion.70(a). History suggests that the question of frequency selection was originally focused on that frequency that would not exhibit ﬂicker in the incandescent lamps available in those days. at least initially. 13. Working through the fundamental equations for transformer design. it is important to clearly understand that an oscilloscope displays only those signals generated elsewhere and connected to the input terminals of the oscilloscope. The absence of an external signal will simply result in a horizontal line on the screen of the scope. The result is that transformers operating at 50 Hz must be larger (on a purely mathematical basis about 17% larger) than those operating at 60 Hz. however. there is a switch or knob with the choice DC/GND/AC. On most modern-day oscilloscopes. 13. while in Europe and the Eastern countries it is 220 V at 50 Hz. AC GND DC (a) Oscilloscope display AC GND DC (b) Input signal FIG. In the AC position the dc input is blocked by the capacitor. Technically.70(b). 13.9 APPLICATIONS (120 V at 60 Hz) versus (220 V at 50 Hz) In North and South America the most common available ac supply is 120 V at 60 Hz.70 AC-GND-DC switch for the vertical channel of an oscilloscope. which reduces the scope display to a single horizontal line. but the ac portion of the signal can pass through to the screen. There is. an assumption that the oscilloscope is generating the waveform on the screen—much like a TV broadcast. The choices of rms value and frequency were obviously made carefully because they have such an important impact on the design and operation of so many systems. However.

due to real safety concerns. it will simply have to “work a little harder” to perform the given task. also bring back the concern about arcing effects. your concern about safety should increase exponentially. higher installation costs. Again. we must also wonder whether the difference is simply political in nature. Note that 50 Hz is exactly half of this special number. Safety Concerns (High Voltages and dc versus ac) Be aware that any “live” network should be treated with a calculated level of respect. insulation requirements. there is less current in the wire for the same power demand. Somewhere in the discussion we must consider the fact that 60 Hz is an exact multiple of 60 seconds in a minute and 60 minutes in an hour. and skin effect phenomena (Chapter 19). There is no question that larger voltages such as 220 V raise safety issues beyond those raised by voltages of 120 V. however. In addition. Higher voltages.71 Variety of plugs for a 220-V. with 100 cm in a meter. Since accurate timing is such a critical part of our technological design. this could mean as many as 6 to 10 different plugs of the type shown in Fig. 50-Hz connection. All in all. However. there are valid arguments for both sides. For any unit not operating at its design frequency. when higher voltages are supplied. For the three-week tour. found in common home appliances and throughout the industrial community can be smaller in size. In general. It is a debate that could go on at length without an ultimate victor. of course) can run quite well on 50 Hz or 60 Hz for most travel periods. 13. Each country has its own design for the “female” plug in the wall.APPLICATIONS 543 ate on 50 Hz or 60 Hz are designed around the 50-Hz frequency. In general. 13. however. FIG. 100°C the boiling point of water. and so on. it would seem that both sides have an argument that would be worth defending. in the ﬁnal analysis. It is common knowledge that electricity and water do not mix (never use extension cords or plug in TVs or radios in the bathroom) because a full 120 V in a layer of water of any height (from a shallow puddle to a full bath) can be lethal. Electricity in its various forms is not to be feared but should be employed with some awareness of its potentially dangerous side effects. Most equipment (not clocks. other effects of dc and ac voltages are less known. motors. permitting the use of smaller conductors—a real money saver. and. compressors. however. In any event.71. However. higher frequencies result in increased concerns about arcing. both the 120 V at 60 Hz and the 220 V at 50 Hz are obviously meeting the needs of the consumer. . For a 120-V. and so on. On the other side of the coin. 60-Hz supply. The difference in voltage between North America and Europe is a different matter entirely in the sense that the difference is close to 100%. as the voltage and current increase. was this a signiﬁcant motive in the ﬁnal choice? There is also the question about whether the 50 Hz is a result of the close afﬁnity of this value to the metric system. The major problem for the traveler is not the transformer itself but the wide variety of plugs used from one country to another. the plug is quite standard in appearance with its two spade leads (and possible ground connection). However. however. increased losses in the transformer core due to eddy current and hysteresis losses (Chapter 19). Keep in mind that powers of 10 are all powerful in the metric system. international travelers are prepared for most situations if they have a transformer that can convert from their home level to that of the country they plan to visit.

the more the resistance in the body decreases until a fatal current can be established. As mentioned above. it appears every 8. Since voltage is a two-point phenomenon. turning on a switch. say. If you happen to be working on a car under wet conditions.544 SINUSOIDAL ALTERNATING WAVEFORMS V(volts) 170 120 V rms ac voltage 20 0 –20 t tf FIG 13. For voltages beyond 220 V rms. In general. You have probably seen in movies or comic strips that people are often unable to let go of a hot wire.45 GHz at 120 V can do to a meat product in a microwave oven.). in a situation where you can quickly escape the situation. Most electricians have experienced such a jolt many times in their careers. This is evidence of the most important difference between the two types of voltages.3 ms and provides a window to let go. ask an electrician to relate how it feels to hit 220 V. Since the voltage is oscillating. you will probably not be able to let go. you should also be aware of the dangers of high-frequency supplies. there is a period of time when the voltage is near zero or less than. wearing a wedding ring that may have moisture and body salt underneath. and the response (if he or she has been unfortunate to have had such an experience) will be totally different. How often have you heard of a back-hoe operator hitting a 220-V line and having a fatal heart attack? Remember. it is one you will not quickly forget. from the door on a . Before leaving this topic of safety concerns. but you can let go. As discussed in Chapter 5. The reason that we can let go of an ac line is best demonstrated by carefully examining the 120-V rms. it is important to mention that under the wrong conditions. touching the positive terminal may initiate the process whereby the body resistance begins to drop and serious injury could take place. or if you are sweating badly for some reason or. We are all aware of what 2. and so on. therefore. Time plays an important role when this happens. worse yet. etc. the chances of survival go down exponentially with increase in voltage. don’t ever assume that anything is absolutely perfect in design—so don’t make it a habit to view the cooking process in the microwave 6 in. because the longer you are subjected to the dc voltage. If only for a short period of time. It takes only about 10 mA of steady current through the heart to put it in deﬁbrillation. with the best environment (rubber-sole shoes. most human beings can survive a 120-V ac shock such as obtained when changing a light bulb. If it happens to be a “hot” 120-V dc line. For instance. as mentioned above. and a fatality could occur. Although this time interval is very short. you will probably get a good sting. Throw the main circuit breaker and test the lines with a voltmeter before working on the system. However. it is therefore very important that the seal around the oven be as tight as possible. always be sure that the power is disconnected when working on the repair of electrical equipment.72. It is one of the reasons you seldom see a professional electrician wearing any rings or jewelry—it is just not worth the risk.72 Interval of time when sinusoidal voltage is near zero volts. don’t be a hero and work with one line at at time—accidents happen! You should also be aware that the reaction to dc voltages is quite different from that to ac voltages. Don’t assume that throwing a wall switch will disconnect the power. 60-Hz voltage in Fig. Now that we are aware of the additional dangers of dc voltages. 20 V. 13. if you happen to touch a “hot” 120-V ac line. the operator is sitting in a metal container on a damp ground which provides an excellent path for the resulting current to ﬂow from the line to ground. most human beings can also survive a 220-V shock. and is reversing in direction. dc voltages as low as 12 V such as from a car battery can be quite dangerous. However. under dry conditions. However.

treat any situation with high ac voltages or currents.APPLICATIONS 545 continuing basis.6 A every time you turn the switch on will take its toll on the ﬁlament. and high frequencies with added care. the saving grace is that it lasts for only a few milliseconds. This method. Fortunately. You can easily tell if a bulb is bad by simply shaking it and listening for the clinking sound of the broken ﬁlament hitting the bulb. but there is no need to replace the bulb as often.73 Surge currents: (a) single 60-W bulb. this would mean a current of 120 V/14 8. leads to one way of extending the life of a light bulb through the use of dimmers. you will notice that you are unable to get close to the antenna on the dome due to the high-frequency signals being emitted with a great deal of power. Even the GFI safety breakers in the bathroom are typically rated at a 5-ms response time. Standing within 10 ft of an AM transmitter working at 540 kHz would bring on disaster.73(b). it is certainly a problem that the power company has to deal with on a continuing basis. Through advanced design we now have bulbs that are guaranteed to last a number of years. hitting the bulb with 8. They cost more. The results are both an extended life for the bulb and the ability to control the power level. Simply holding (not to be tried!) a ﬂuorescent bulb near the tower could make it light up due to the excitation of the molecules inside the bulb. However. I can remember the days when I was taught to always turn a light off when leaving a room and not to play with a light switch because it cost us a penny (at a time when a penny had some real value) every time I turned the switch on and off. before the bulb heats up.6 A when the light is ﬁrst turned on. in fact. However. Forgetting any inductive effects due to the ﬁlament and wire. and over time there is a ﬁnancial savings. 13. it lasts for only a few milliseconds. In total. Assuming an initial current of 8. if the light switch controlled four 60-W bulbs in the same room. .5 A. One way to suppress this surge current is to place an inductor in series with the bulb to choke out the spikes down the line. If you ever visit the Empire State Building. Bulb Savers Ever since the invention of the light bulb. Any well-designed dimmer (such as the one described in Chapter 12) has an inductor in the line to suppress current surges. and check the food only when the cooking process is complete.5 2 t (s) FIG 13. I measured the cold dc resistance of a standard 60-W bulb and found it to be about 14 . 13.4 A as shown in Fig. which probably exceeds the rating of the breaker (typically 20 A) for the circuit. However. consumers have clamored for ways to extend the life of a bulb.6 A) 34. as shown in Fig. and circuit breakers are not designed to react that quickly. For some of us it is simply a matter of having to pay so much for a single bulb. the surge current through the switch could be as high as 4(8.6 A for a single bulb.5 0 1 2 3 4 (a) 5 6 7 t (ms) IT (A). when you look at the big picture and imagine all these spikes on the line generated throughout a residential community. Left on in the full voltage position. This is a fairly heavy current for the ﬁlament to absorb when you consider that the normal operating current is 60 W/120 V 0.6 0.5 250 ms 1 (b) 1. causing the ﬁlament resistance to quickly increase and cut the current down to reasonable levels. (b) four parallel 60-W bulbs. For interest sake. Also note the large KEEP OUT signs near radio transmission towers for local radio stations. high-energy dc levels. therefore. and eventually the ﬁlament will simply surrender its natural characteristics and open up. over time. four parallel 60-W bulbs 34. Find something else to do. the switch could be used as a regular switch and the life of the bulb could be Ibulb (A) 8.4 2 0 0.73(a).

74 Turn-on voltage: (a) equal to or greater than one-half the peak value. 13. 13. (c) diode characteristics at high current levels. . of your turning on a light bulb with at least 85 V on the line is far better than 2 to 1. 13. which exceeds the rated 0. as shown in Fig. many dimmers now use triacs designed to turn on only when the applied voltage passes through zero.74(a). In fact.546 SINUSOIDAL ALTERNATING WAVEFORMS V (volts) 170 120 V rms ac voltage 120° 180° 0 –85 30° 150° 360° θ 0 –85 170 V (volts) Vapplied 85 85 Vbulb 90° Turn-on Dimmer ensures bulb will not turn on when applied voltage is near its maximum. The chances. (b) when a dimmer is used.75 Bulb saver: (a) external appearance. extended.7 V – +0.7 V Ilamp (for positive region of applied voltage) High resistance Id Low resistance 170 V peak + 168. we ﬁnd that the voltage is at least half of its maximum value of 85 V for a full two-thirds of each cycle. so you can expect the current for a 60-W light bulb to be at least 85 V/14 6 A 67% of the time. If we look at the full sine wave of Fig.6 V – Return (b) – Open circuits for positive region of applied voltage 0 High resistance (diode open circuit) + Vd – Lamp Vd (c) FIG. (a) 120-V rms line + Id +0. (b) basic operation. therefore. or about 67% of the time. If we use a dimmer with a triac designed to turn on only when the applied voltage passes through zero or shortly thereafter. (b) 180° 360° t –170 (a) –170 FIG.5-A rated value by 1100%.

the magnitude entered and read is the peak value of the waveform and not the rms value. However. In other words.7 V as shown for each diode in Fig.slb. On occasion. and it can be used for dc. However. the voltage source VSIN and the current source ISIN are the most appropriate because they have a list of attributes that will cover most areas of normal interest for sinusoidal networks. and “Don’t play with the light switch!” 13. but they don’t have the full range of the above or they are dedicated to only one type of analysis. The sources VAC. 13.75(b) for the positive portion of the input voltage. however. for the purposes of this text. New methods of extending the life of bulbs hit the marketplace every day. the applied voltage will increase from about zero volts. ac. However.COMPUTER ANALYSIS 547 13. the real saving in the device is the manner in which it could help suppress the surge currents through the light bulb. 13.75(c) for the full range of currents through the diode.10 COMPUTER ANALYSIS PSpice (Windows) Schematics offer a variety of ac voltage and current sources. IAC. All in all. 13. For all of the sinusoidal sources. SOURCE.75(b). The symbol for ISIN is simply a sine wave which utilizes the plus-and-minus sign to indicate direction. For most applications in electronic circuits. You may recall from an earlier chapter that the voltage across diodes in the on state is 0.4 V throughout the cycle. one guaranteed way to extend the life of your bulbs is to return to the old philosophy of turning lights off when you leave a room. Contacts are provided on both sides to permit conduction through the simple diode network shown in Fig. This region is characterized as having a large resistance (compared to very small resistance of the vertical region) which will come into play when the bulb is ﬁrst turned on. when the bulb is ﬁrst turned on. For excessive currents the diode characteristics ﬂatten out as shown. 13. and the bulb will last longer simply because it is not pressed to work at full output. they will not provide a transient response against time even if the frequency and transient information are provided under Analysis. Another commercial offering to extend the life of light bulbs is the smaller circular disc shown in Fig. ISRC will be used because it has an arrow symbol like that appearing in the text. reducing the power delivered to the bulb. a number of others are listed. the current will be so high that the diode will enter its high resistance region and by Ohm’s law will limit the surge current—thereby extending the life of the bulb. However. the magnitude provided can . This will become clear when a plot of a quantity is desired and the magnitude calculated by PSpice (Windows) is the peak value of the transient response.74(b). The true characteristics of a diode are shown in Fig. For most situations the reduced lighting is not a problem. and ISRC are ﬁne if the magnitude and phase of a speciﬁc quantity are desired or if a transient plot is against frequency. The two diodes facing the other way are for the negative portion of the supply voltage. giving the bulb time to warm up before the full voltage is applied. The result is that the voltage to the bulb is reduced by about 1.75(a) which is inserted between the bulb and the holder. for a purely steady-state ac response. and some transient analyses. the vertical region is employed. VSRC. Under the library.