Cau Truc Pic 16f877a Vi Xu Ly

201ASP
Mid-Range Family Peripheral Configuration and Assembly Programming
2006 Microchip Technology Incorporated. All Rights Reserved.
201ASP
v8.0
JanuarySlide 1 2007
Objectives

At the end of this class you will:
Understand the basic PICmicro peripherals and their associated registers Have HANDS ON experience initializing Mid-Range peripherals Be able to implement peripherals not covered here Understand interrupts and polling Write your own application code from scratch
201ASP Slide 2
To get the most from this Class

Ideally you should be familiar with the following:

Assembler programming Basic Mid-Range family Instruction set Data and Program memory organization MPLAB Integrated Development Environment Microchip ICD2 debugger
201ASP
Slide 3
201ASP Agenda

Brief review of Mid-Range Architecture, Instruction Set and Tools Interrupts on the Mid-Range PICmicro

Interrupts Lab Input/Output Ports Timers Timer0 Timer1 Timer1 Lab Timer2 Timer2 Lab
201ASP Slide 4
Peripheral discussion:

201ASP Agenda (cont.)

Capture / Compare / PWM Module (CCP)
PWM and Output Compare Labs

Analog Comparator Analog to Digital Converters (ADC)
ADC Lab
Addressable Universal Asynchronous & Synchronous Receiver & Transmitter (AUSART) with the Master Synchronous Serial Port
I2C
I2C Based Temp Sensor Lab
Wrap-Up and additional questions

201ASP Slide 5
Mid-Range Family Basic Architecture and Development Tools
201ASP
v8.0
JanuarySlide 6 2007
Mid-Range PIC Block Diagram

Pages of Program Memory
PROGRAM COUNTER
STATUS
REGISTER
8-bit value from instruction
MUX ALU
Banks of Data Memory
ADC TIMER0
14-bits INSTRUCTION REGISTER
WORKING REGISTER
AUSART
MSSP
PERIPHERALS
2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP Slide 7
Program Memory

Maximum 8K words
Reset Vector
0000h
(8K x 14 bits/word)/1 byte = 14Kbytes of memory
Interrupt Vector 0004h Page 0 Page 1 Page 2 Page 3

0005h 07FFh 0800h 0FFFh 1000h 17FFh 1800h 1FFFh
Reset Vector at 0000h
Program Counter (PC) will go to this address on reset
Interrupt Vector at 0004h
Program Counter (PC) will go to this address upon any Interrupt

201ASP
Slide 8
Program Counter (PC) and Stack

PCLATH
13-bit PC

PCL ALU result (8-bits) or OPCODE(11-bits) PCH Paging bits

PCH<12:8>
CALL, RETURN, RETFIE, RETLW
PCL
PC<12:0>
Updated from PCLATH Specifies page in program memory
Stack Level 1
8 Level Deep Stack
Stores the contents of the PC

Stack Level 8
PUSHES
CALL/Interrupt RETURN, RETFIE,RETLW

201ASP
POPS
Program Memory
Slide 9
Data Memory Map

000h 080h
Special Function Registers 01Fh

020h
Special Function Registers
SFR
09Fh 0A0h
100h 10Fh 110h
SFR
180h 18Fh 190h
128 Bytes
General Purpose Registers

0EFh 07Fh

16Fh

1EFh
Shared Bank1
0FFh
Shared Bank2
17Fh
Shared Bank3
1FFh
Bank 0
201ASP
Slide 10
Special Function Registers (SFRs)

Register File Concept Accessed like any other register Some registers carry across all banks
(PCLATH, INTCON, etc.)
PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2
06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh
TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2
86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh
Bank0
Bank1
201ASP
Slide 11
Status Register
IRP RP1 RP0 TO PD Z DC C
Contains:
Arithmetic status of the ALU The RESET status Bank select bits for data memory
RP1 RP1 0 0 1 1
RP0 RP0 0 1 0 1
BANK0 BANK1 BANK2 BANK3
Indirect Register Bank Select bit: (used for indirect addressing) 1 = Bank 2,3 0 = Bank 0,1
201ASP
Slide 12
PIC16 Instruction Set

addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf
35 single word instructions All are single cycle except for program branches
Byte Oriented Operations f,d Add W and f f,d AND W with f f Clear f Clear W f,d Complement f f,d Decrement f f,d Decrement f, Skip if 0 f,d Increment f f,d Increment f, Skip if 0 f,d Inclusive OR W with f f,d Move f f Move W to f No Operation f,d Rotate Left f through Carry f,d Rotate Right f through Carry f,d Subtract W from f f,d Swap nibbles in f f,d Exclusive OR W with f
201ASP
bcf bsf btfsc btfss addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw
Bit Oriented Operations f,b Bit Clear f f,b Bit Set f f,b Bit Test f, Skip if Clear f,b Bit Test f, Skip if Set Literal and Control Operations k Add literal and W k AND literal with W k Call subroutine Clear Watchdog Timer k Go to address Inclusive OR literal with W k k Move literal to W Return from interrupt k Return with literal in W Return from Subroutine Go into standby mode k Subtract W from literal k Exclusive OR literal with W
Slide 13
PICmicro Development Tools
201ASP
v8.0
January 2007 Slide 14
MPLAB IDE
MPLAB IDE (Integrated Development Environment) Integrates different Microchip and third party tools

Code Editor Cross Compilers Assemblers Simulators, In-Circuit Debuggers, Emulators InProgrammers
201ASP Slide 15
MPLAB IDE
MPLAB IDE (Integrated Development (I Environment) Integrates different Microchip and third party tools

Code Editor Cross Compilers Assemblers Simulators, In-Circuit Debuggers, Emulators InProgrammers
201ASP Slide 16
ICD 2 (In Circuit Debugger)

MPLAB ICD 2 is a low cost, real-time realdebugger and programmer.
Reading/Writing memory space and EEDATA areas of the PIC Programs configuration bits Real time debugging Erase of program memory space with verification
201ASP
Slide 17
PICDEM 2 Plus Board

9V to 5V regulator LEDs 16 x 2 LCD Module
RS232 Connecto r Analog Pot
18, 28 and 40pin DIP sockets

ICD Connecto r Piezo Buzzer I2C Based Temp Sensor
201ASP
Push button Switches
Slide 18
Interrupts
201ASP
v8.0
Polling and Interrupts

Often we would like the processor to perform a task if a specific event occurs Two methods to check if this event has occurred:
Polling:

Continuously check for event at various points in the code INTERRUPTS the Main program and starts an Interrupt Service Routine when an event occurs
201ASP Slide 20
Interrupts:

Polling
bsf PORTA,1 ;Set bit 1 of ;PORTA RA<1> = 1
btfss INTCON,TMR0IF ;Check Timer0 ;interrupt flag ;in INTCON ;register and ;skip the next NO ;instruction if ;it is set goto $-1 ;Go to ;previous ;instruction ;Clear bit 0 of ;PORTA
201ASP
TMR0IF = 1 ??
YES
RA<1> = 0
bcf
PORTA,1
Slide 21
Interrupts
Reset code goto 000h Start
no interrupt
;========================= int_vector code 004h

Interrupt Service Routine (ISR)
Main program execution

retfie instruction interrupt flag set
retfie
;return from ;interrupt ;========================= code
main_prog
Execute ISR at address 004h
Start ;start label for main code Main program

code
end
Enabling Interrupts

Processor must be told that interrupts will be used
A number of registers with interrupt enable bits do this:

Interrupt Control (INTCON) Peripheral Interrupt Enable 1 (PIE1) Peripheral Interrupt Enable 2 (PIE2)
201ASP
Slide 23
Interrupt Logic
TMR0IE TMR0IF INTE INTF RBIE RBIF TMR2IE TMR2IF ADIE ADIF
Other peripherals
2007 Microchip Technology Incorporated. All Rights Reserved. 201ASP
Interrupt
GIE
PEIE
Slide 24
INTCON Register
(Core Interrupts)
Enable Bits
GIE PEIE TMR0IE INTE RBIE
Description
Global Interrupt Enable Peripheral Interrupt Enable Timer0 Interrupt Enable External Interrupt Enable PORTB change Interrupt Enable
Must be set to use any Interrupts Must be set to use any Peripheral Interrupts
GIE
PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF Flag Bits Description
Timer0 Overflow Interrupt Flag RB0/INT External Interrupt Flag PORTB Change Interrupt Flag
Slide 25
Flags will set even if interrupts arent enabled!

TMR0IF INTF RBIF

201ASP
Enabling a Core Interrupt

Int_vect CODE 004h ;clear external interrupt ;flag to enable ;further interrupts bcf INTCON,INTF <ISR code> retfie
goto $ address goto $ address
Program Counter Stack
Main Start
CODE <code to set up PORTB > ; initialize INTCON clrf INTCON ;enable an external ;interrupt on the INT pin bsf INTCON,INTE ;enable global interrupts bsf INTCON,GIE ; sit here and loop forever goto $
INTCON 1 0 0 0
GIE
1 0
INTE
1 0
INTF
Interrupt detected on RB0/INT Pin!!
201ASP
Slide 26
Peripheral Interrupts

Two registers ENABLE interrupts for peripherals

Peripheral Interrupt Enable 1 (PIE1) Peripheral Interrupt Enable 2 (PIE2)
Two registers display peripheral REQUESTS for an interrupt (Flags)

Peripheral Interrupt Request 1 (PIR1) Peripheral Interrupt Request 2 (PIR2)
*Flags will set even if interrupts are not enabled!!

PIE1 and PIR1 Registers*

PIE1 Register (Peripheral Interrupt Enables)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
PIR1 Register (Peripheral Interrupt Requests)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
Enable
ADIE RCIE TXIE SSPIE
Flag
ADIF RCIF TXIF SSPIF
Condition
ADC conversion complete AUSART receive buffer is full AUSART transmit buffer is full I2C or SPI Interrupt Timer1 register capture or compare match Timer2 value and PR2 period value match Timer1 register has overflowed
CCP1IE CCP1IF TMR2IE TMR2IF TMR1IE TMR1IF
*Check individual datasheets for bit locations

PIE2 and PIR2 Registers*

PIE2 Register (Interrupt Enables)
OSCFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE
PIR2 Register (Interrupt Flags)

OSCFIF C2IF C1IF EEIF BCLIF ULPWUIF CCP2IF
Enable
OSCFIE C2IE C1IE EEIE BCLIE ULPWUIE CCP2IE
Flag
OSCFIF C2IF C1IF EEIF BCLIF
Condition
System Oscillator Failed Comparator2 output changed Comparator1 output changed Write operation completed Bus collision occurred in MSSP I2C mode Timer1 Capture or Compare match occurred
ULPWUIF Wake-up condition occurred CCP2IF
*Check individual datasheets for bit locations

Int_vect CODE
Enabling a Peripheral (Timer 1) Interrupt

004h
banksel PIR1 bcf PIR1, TMR1IF <ISR code> retfie
goto $ address goto $ address
Program Counter Stack
Main Start
CODE banksel bcf banksel bsf bsf bsf PIR1 PIR1,TMR1IF PIE1 PIE,TMR1IE INTCON,PEIE INTCON,GIE
INTCON 0 1 1
GIE PEIE
PIE1 1
TMR1IE
PIR1 1 0
TMR1IF
<code to set up Timer1> ; sit here and loop forever goto $
Timer1 Overflow!
201ASP Slide 30
Interrupt Latency

Interrupt Latency:
Time from interrupt event to execution of instruction at address 0004h Synchronous interrupts (typically internal)

latency is 3 instruction cycles (Tcy) latency is 3 3.75 instruction cycles
Asynchronous interrupts (typically external)

201ASP
Slide 31
Context Saving

During an interrupt:

Only the PC value is saved (on the stack) Registers changed in the Interrupt Service Routine (ISR) are permanently changed
Key registers you may want saved:

Working register Status PCLATH (Program Counter Latch High) User defined registers
201ASP Slide 32
Interrupt Priority

Mid-Range PIC microcontrollers treat all Interrupts with the same priority The user must do the following:

Determine source of interrupt Determine the order in which the interrupts are serviced.
201ASP
Slide 33
Interrupt Priority Example

INT_VECTOR CODE 0x004 ;interrupt vector location ;save WREG ;movf affects Z bit, ;use swapf instead ;save STATUS register ;Save context movwf temp_w swapf STATUS,w movwf ;Check btfsc call btfsc call btfsc call temp_status
flags in order of priority INTCON,RBIF ;PORTB change? PORTB_ISR PIR1,TMR2IF ;Timer2 interrupt? Timer2_ISR PIR2,TMR1IF ;Timer1 interrupt? Timer1_ISR
Restore_context: swapf temp_status,w movwf STATUS ;restore STATUS reg movf temp_w,w ;restore WREG retfie ;return from interrupt
Interrupt Hands on Lab
201ASP
v8.0
Interrupt

The objective of this is to:
Learn how to set up and enable an interrupt on the Mid-Range PIC Become more familiar with the MPLAB IDE, the PICdem2 Plus and the ICD2

Building a Project Using the ICD to set a break point
201ASP
Slide 36
Interrupt Lab Overview

Interrupt Vector
Call debounce delay function Increment Count variable Clear IF
Main Program
Clear Variables Initialize PORTB (RB0) for S3 input Enable Interrupts No Operation NOP
Return to Main
201ASP
Slide 37
Lab Specifics

Code is located in C:\RTC\201_ASP\Lab1-INT The S3 switch is connected to the RBO/INT pin on PORTB The push_count register will display the # of times S3 has been pushed. Use MPLAB and the ICD to set a breakpoint in the code to view the changing value of the register named push_count
201ASP
Slide 38
What you need to know

The function of the INTCON register bits Jumper J6 must be removed in order for the INTE pin to work A subroutine called debounce is given
masks the mechanical bouncing of S3
How to setup break points and a Watch Window in MPLAB
201ASP
Slide 39
Interrupt Lab Solution
bsf bsf bsf bsf bcf
STATUS,RP0 TRISB,0 INTCON,INTE INTCON,GIE STATUS,RP0
; ; ; ; ;
point to BANK1 ### initialize PORTB<0> as input ### enable INTE interrupts ### Enable global interrupts return to BANK0
201ASP
Slide 40
Peripherals
201ASP
v8.0
Mid-Range Family Peripherals

I/O Ports Timers (0, 1, 2) Capture/Compare/PWM Comparators Analog-to-Digital Converter AUSART I2C and SPI Serial Interface
201ASP
Slide 42
I/O Overview

Up to 35 bi-directional Input/Output pins
some multiplexed with peripheral functions
High drive capability
25mA source or sink

Direct, single cycle bit manipulation Most I/Os have ESD protection After Reset:

Analog capable pins come up as Analog Digital I/O pins come up as Input
201ASP Slide 43
PORTx and TRISx Registers

Every PORT (A, B, C, D, E) will have a corresponding direction register TRISx

PORTB Register
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
Data
Configures Data Direction
PORTB Tri-State Register (TRISB)
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
1 = corresponding PORTB pin is an INPUT 0 = corresponding PORTB pin is an OUTPUT

Configuring Analog Inputs for Digital

I/Os with digital and analog capabilities default to analog on reset
201ASP
Slide 45

Two ways to configure Analog inputs as Digital:

1) Analog Select Registers (ANSEL and ANSELH)

For devices with > 8 analog pins
OR 2) ADC Control register 1 (ADCON1)

For devices with 8 or less analog pins
Analog Select Register (ANSEL)

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
Analog Select High Register (ANSELH)

ANS13 ANS12 ANS11 ANS10 ANS9 ANS8
1 = Pin assigned as Analog Input 0 = Digital I/O ADC Control Register 1 (ADCON1)
ADFM ADCS2
Port Configuration Bits
PCFG3 PCFG2 PCFG1 PCFG0

Slide 46

PCFG AN7 AN6 <3:0> AN5 AN4 AN3 AN2 AN1 AN0 Vdd
ADC Control Register 1 (ADCON1)

ADFM ADCS2
Port Configuration Bits

Slide 47
Initializing Digital I/O

Initialize PORTB

RB4 through RB7 as Digital Inputs RB0 through RB3 as Digital Outputs
;------------configure PORTB for digital ---------------------banksel PORTB ;Go to bank containing PORTB register clrf PORTB ;Initialize PORTB data banksel ANSELH ;Go to bank containing ANSELH register clrf ANSELH ;Set as all digital ;-----------Set up direction of each PORTB pin----------------banksel TRISB ;Go to bank containing TRISB register movlw b11110000 ;Move value to set TRISB<7:4> high and ;TRISB<3:0> low into W register movwf TRISB ;Move value in W into TRISB
201ASP
Slide 48
PORTB Interrupt & Weak Pull-Up Options

All PORTB pins have Interrupt-on-Change and Weak Pull-Up options 1
Weak Pull-Up PORTB Register (WPUB)

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
1 = Pull-up enabled 0 = Pull-up disabled
RB3
Devices without WPUB register use RBPU bit in OPTION register Interrupt-On-Change PORTB Register (IOCB)
1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled HIGH LOW
IOCB7 IOCB6 IOCB5 IOCB4 ICOB3 IOCB2 IOCB1 IOCB0 1
Devices without IOCB rely on RBIE bit in INTCON
RB4
Interrupt Control Register (INTCON) GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF RBIF *PORTB must first be read/written and then RBIF can be cleared in software
Timers
201ASP
v8.0
Timers

Timers are used for many functions:

timing reference to generate an event count the number of events waveform generation etc...
PIC16F877 has 3 timers

Timer0 Timer1 Timer2

201ASP Slide 51
Timer Comparison
TIMER0
SIZE OF REGISTER CLOCK SOURCE (Internal) CLOCK SOURCE (External ) CLOCK SCALING AVAILABLE (Resolution) INTERRUPT EVENT and FLAG LOCATION CAN WAKE PIC FROM SLEEP?
TIMER1
16-bits (TMR1H:TMR1L) Fosc/4 T1CKI pin or Timer 1 oscillator (T1OSC) Prescaler 3-bits (1,2,4,8)
TIMER2
8-bits (TMR2) Fosc/4 None
8-bits (TMR0) Fosc/4 T0CKI pin
Prescaler 8-bits (1:2 1:256)
Prescaler (1:1,1:4,1:8) Postscaler (1:1 1:16) TMR2 matches PR2 (TMR2IF in PIR2) NO
On overflow FFh 00h (TMR0IF in INTCON) NO
On overflow FFFFh 0000h (TMR1IF in PIR1) YES
201ASP
Slide 52
Timer 0 Block Diagram

DATA BUS
Fosc/4
8
synchronize
T0CKI pin
scaled clock
TMR0
PS2 WDT out 0 0 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TMR0 RATE 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Watchdog Timer
prescaler
OPTION register
RBPU INTEDG TOCS TOSE
PSA
PS2
PS1
PS0
0 0
Prescaler Rate Select Bits Prescaler Assignment TMR0 Clock Source Select
1 = TOCKI, 0 = Fosc/4
1 1
1= prescaler assigned to WDT 1 0= prescaler assigned to Timer 0
Source Edge Select
1 = increment TMR0 on high-to-low transition 0 = increment TMR0 on low-to-high transition

Timer 0 Block Diagram

DATA BUS
Fosc/4
8
synchronize
T0CKI pin
scaled clock
TMR0
Watchdog Timer
prescaler
INTCON register TMR0IF
If the external clock source (TOCKI) is used it will be synchronized to the internal clock Timer 0 is readable or writeable Timer 0 interrupt flag is set on TMR0 roll-over (FF to 00)
Timer0 Initialization
;Make sure the Timer0 count ;register (TMR0) is clear banksel TMR0 clrf TMR0 ;Clear Timer0 interrupt flag bcf INTCON,TMR0IF ;Setup the Option register to ;increment Timer0 from internal ;clock with a prescaler of 1:16 banksel OPTION_REG movlw b00000011 movwf OPTION_REG ;The TMR0 interrupt is disabled, do ;polling on the flag bit (TMR0IF) btfss INTCON,TMR0IF goto $-1 <continue>
TMR0
Timer0 incrementing
0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1
INTCON
1 0
Flag on overflow TMR0IF This interrupt flag will set on Timer0 overflow even if interrupts are disabled OPTION_REG
0 0 0 0 0 0 1 1
TOCS PSA PS<2:0>
Prescaler Selects Timer 0 Prescaler Assignment Clock Source value = 1:16 (WDT or TMR0) (External or Internal)
Slide 55
201ASP
Timer1 Block Diagram

T1OSI T1OS0
T1 OSC
prescaler
Fosc/4
synchronize
T1CKI pin
TMR1H
TMR1L
Enable
Timer1 Control Register (T1CON)

T1GINV T1CKPS1 1 1 0 0 TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON T1CKPS0 1 0 1 0 scale 1:8 1:4 1:2 1:1
TMR1ON
Timer1 On LP Oscillator Enable

1 = T1OSC selected 0 = T1CKI can be used 1 = Enable Timer1
Clock Source Select

1 = External (T1CKI) 0 = Internal (FOSC/4)
201ASP
Slide 56

T1OSI T1OS0
T1 OSC
prescaler
Fosc/4
synchronize
T1CKI pin
TMR1H
TMR1L
Enable

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
TMR1ON
Timer1 Gate Enable and Timer1 Gate Invert are available on some devices
Timer1 External Clock Input Synchronization

1 = do not synchronize external clock input 0 = synchronize external clock input with internal clock (Fosc/4)
201ASP
Slide 57
Timer1 Interrupt Setup

Main Code 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Start 1 1 1 1 1 1 1 ;Start by clearing the Timer1 interrupt flag banksel PIR1 PIR1 bcf PIR1, TMR1IF ;Enable Timer1 interrupt banksel PIE1 bsf PIE1, TMR1IE
TMR1H
TMR1L
0 1 0 0 1 1
1 0
TMR1IF
PIE1
1
TMR1IE
;Enable Global and Peripheral Interrupts bsf INTCON, PEIE INTCON bsf INTCON, GIE
1 1
GIE PEIE
TMR1H
;Make sure the TMR1 registers are clear banksel TMR1H clrf TMR1H clrf TMR1L ;Make sure the TMR1IF flag in PIR1 ;is cleared banksel PIR1 bcf PIR1,TMR1IF ;Setup T1CON register for internal clock ;with 1:8 prescaler, Timer1 is stopped ;and T1 osc is disabled movlw b00110000 movwf T1CON ;Start Timer1 incrementing bsf T1CON, TMR1ON ;The TMR1 interrupt is disabled, do ;polling on the Timer1 flag bit btfss PIR1, TMR1IF goto $-1
0 0 0 0 0 0 0 0
TMR1L
TMR1H:TMR1L INCREMENTING 0 0 0 0 0 0 0 0 OVERFLOW!!
PIR1 (Peripheral Interrupt Request)
0 0 0 0 0 0 0 0 1
TMR1IF
T1CON (Timer1 Control)
0 0 1 1 0 0 0 0 1
Input clock prescale bits (T1CKPS<1:0>) Timer1 oscillator enable bit (T1OSCEN) TMR1ON Clock source select bit (TMR1CS)
Slide 59
201ASP
Timer1 Lab
201ASP
v8.0
Timer1 Lab

Objective of this lab is to become familiar with the operation of Timer1

AND
To gain experience enabling Peripheral Interrupts
201ASP
Slide 61
Lab Overview
Interrupt Vector
Save Context Clear IF Reload Timer1 Toggle LED 0 5th Int. ?
YES
Main Program
Initialize PORTB Initialize Timer1 clock source and pre-scaler: Timer1 interrupts every 100,000 Instruction cycles Enable Timer1, Global and Peripheral Interrupts NOP Main Loop
NO
Toggle LED 3 Restore Context Retfie

Slide 62
Lab Specifics

The code for the lab is in

C:\RTC\201_ASP\Lab2-TMR1
Within lab2.asm complete the following

Set Timer1 clock source to Fosc/4 Set Timer1 pre-scaler to 2 Load Timer1 with 0x3CB0 (65,536 50,000) Start Timer1 Enable Timer1, Global and Peripheral Interrupts
201ASP Slide 63

Register Operations of INTCON, T1CON, TMR1H, TMR1L and PIE1 With a value of 0x3CB0 and a pre-scaler of 2, Timer1 will overflow every 100,000 cycles The interrupt vector code to toggle the LEDs has been provided
201ASP Slide 64
Timer1 LAB Solution

;******************************************************************* ;Set code to Select clock source, Set pre-scaler to 2, load hex 3CB0 ;into Timer1 and turn on Timer1 ;******************************************************************* movlw 0x3C ; ### initialize TMR1L and TMR1H movwf TMR1H ; ### movlw 0xB0 ; ### movwf TMR1L ; ### bsf T1CON,T1CKPS0 ; ### configure prescaler to 1:2 bsf T1CON,T1CKPS1 ; ### bcf T1CON,TMR1CS ; ### set clock source to Fosc/4 bsf T1CON,TMR1ON ; ### turn TMR1 on ; ;******************************************************************* ;Enable Timer1 interrupts, Peripheral Interrupts and Global Interrupts ;******************************************************************* bsf STATUS,RP0 ; ### point to BANK1 bsf PIE1,TMR1IE ; ### enable TMR1 interrupts bsf INTCON,GIE ; ### enable Peripheral interrupts bsf INTCON,PEIE ; ### enable Global interrupts bcf STATUS,RP0 ; ### return to bank0
Lab Questions
Question: Was Timer 1 still running during the time it took to service the Interrupt? Answer: Yes Question: What effect did this have on the value to be placed to reload TMR1L and TMR1H? Answer: Everything to be precise the latency of reloading Timer1 should be considered.

TMR2 OUTPUT Prescaler 1:1, 1:4, 1:16
TMR2
Fosc/4
COMPARATOR PR2
Postscaler 1:1 1:16

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
T2CKPS1 0 0 1
T2CKPS2 0 1 X
Scale 1:1 1:4 1:16

201ASP Slide 67
Timer2 ON 1 = Timer2 enabled
TOUTPS3 0 0 0 0 0 0

TOUTPS2 0 0 0 0 1 TOUTPS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TOUTPS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SCALE 1:1 1:2 1:3 1:4 1:5 TMR2 1:6 1:7 1:8 1:9 1:10 COMPARATOR 1:11 1:12
TMR2 OUTPUT
Fosc/4
1 Prescaler 01:1, 1:4, 1:16 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1
Postscaler 1:1 1:16
PR2 1:13
1:14 1:15 1:16

T2CKPS1 0 0 1
T2CKPS2 0 1 X
Scale 1:1 1:4 1:16

201ASP Slide 68
Timer2 ON 1 = Timer2 enabled

Start Timer2 Counting
Prescaler 1:1, 1:4, 1:16 TMR2 OUTPUT
TMR2 1 1 1 1 0 1 1 0 1 0 0 1 COMPARATOR
Postscaler 1:1 1:16
Fosc/4
Load Period Register
PR2 1 1 1 1 1 0 0 0
PIR1 1
TMR2IF

Flag set on first match with postscaler = 1:1
201ASP
Slide 69
Timer2 Incrementing
TMR2 (Timer2 Counter) ;Disable the Timer2 interrupts in the PIE1 ;register. Make sure the Timer2 interrupt ;flag in PIR1 is cleared. PR2 (Period Register Timer2) banksel PIE1 bcf PIE1,TMR2IE banksel PIR1 bcf PIR1,TMR2IF PIE1 (Peripheral Interrupt Enable) ;Setup T2CON register for Postscaler = 1:15, ;Prescaler = 1:16, Timer2 off movlw b01110010 TMR2IE movwf T2CON PIR1 (Peripheral Interrupt Request) ;Make sure the TMR2 register is clear banksel TMR2 clrf TMR2 TMR2IF ;Load the Period register Flag is set banksel PR2 movlw b10000000 T2CON (Timer2 Control) movwf PR2 ;Start Timer2 incrementing banksel T2CON bsf T2CON,TMR2ON ;The Timer2 interrupt is disabled, do TMR2ON Postscaler = 1:15 ;polling on the Timer2 interrupt flag (TOUTPS<3:0>) btfss PIR1,TMR2IF Prescaler = 1:16 goto $-1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0
0 1
0 1 1 1 0 0 1 0 1
(T2CKPS<1:0>)
201ASP
Slide 70
Timer2 Lab
201ASP
v8.0
Timer2 Lab

The Goal of Lab 3 is to become familiar with the following:

Timer2 Clock Source Setting the Prescaler Setting the Postscaler Turning on Timer2 Setting the Interrupt Enable bits needed for Timer2 to successfully generate an interrupt.
201ASP
Slide 72
Lab Overview
Interrupt Vector
Save Context
Main Program
Initialize PORT B Set up Timer2 Period, Prescaler, Postscaler
Increment counter the number of times Timer2 has interrupted
Output 3 LSBs of count to LEDs Restore context retfie

201ASP
Enable interrupts NOP
Slide 73
Lab Specifics

Code for this lab is in

C:\RTC\201_ASP\Lab3-TMR2
Complete the following sections of code

Set Timer2 prescaler to a value of 4 Set Timer2 postscaler to a value of 13 Turn Timer2 on Configure the GIE and PEIE bits in the Interrupt Control register (INTCON) Configure the Timer2 Interrupt Enable bit in the Timer2 Configuration register (T2CON)
201ASP Slide 74

Special Function Registers (SFRs) needed for this lab are:

INTCON(Interrupt Control) PIE1..(Peripheral Interrupt Enable 1) PR2...(Timer2 Period Register) T2CON..(Timer2 Control)
With the Period register (PR2) set to 250, the prescaler at 4, and the postscaler at 13, Timer2 will interrupt every 13 ms (about 1/80 second) with a 4Mhz oscillator (Fosc/4 = 1Mhz).
201ASP Slide 75
Timer2 Lab Solution

;***************************************************************** ; configure Timer2 prescaler of 4, PR2 of 250 and a postscaler ; of 13 and turn timer2 on. ;***************************************************************** ; BANKSEL T2CON ; point to bank containing T2CON movlw 0x60 ; ### set TMR2 postscaler = 1:13 movwf T2CON ; ### bsf T2CON,T2CKPS0 ; ### set TMR2 prescaler = 1:4 bsf T2CON,TMR2ON ; ### turn on TMR2 ;***************************************************************** ;Enable Timer2 interrupts, Peripheral and Global Interrupts ;***************************************************************** bsf bsf bsf bsf bcf STATUS,RP0 PIE1,TMR2IE INTCON,PEIE INTCON,GIE STATUS,RP0 ; ; ; ; ; point to BANK1 ### enable TMR2 interrupts ### enable peripheral interrupts ### enable global interrupts return to BANK0
201ASP
Slide 76
Lab Questions
Question: Like Timer1, does Timer2 keep running during Interrupt latency? Answer: Yes it does! Question: Does the user have to account for the free running Timer2 in order to ensure a precise interrupt period? Answer: No, Interrupt occurs on match not overflow
Capture/Compare/PWM Module
201ASP
v8.0
Capture
Capture/Compare/PWM (CCP) Overview
Times the duration of an external event using an input pin Changes an output pin or generates an interrupt when a specific amount of time has passed Creates a reconfigurable, steady duty-cycle, square wave output at a defined frequency Provides enhanced features for various bridge connectivity
Compare
Pulse Width Modulation (PWM)
* Module interfaces with Timers 1 and 2

Capture
Capture/Compare/PWM (CCP) Overview

Timer 1
Times the duration of an external event using an CCP Timer Resource input pin MODE Changes an output pin or generates an interrupt Compareamount of time hasTimer 1 when a specific passed Creates a reconfigurable, steady duty-cycle, square wave output at a defined frequency Provides enhanced features for various bridge connectivity
Compare Capture
PWM Pulse Width Modulation (PWM) Timer 2
* Module interfaces with Timers 1 and 2

CCP Control Registers

CCP1 Control Register (CCP1CON) P1M1 P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 BIT
CCP1M<3:0> CCP1<X:Y> P1M<1:0>
FUNCTION
CCP Mode Select Bits configure the module as Input Capture, Output Compare, or PWM PWM duty cycle 2 LSBs (8 MSBs located in CCPR1L) These PWM output configuration bits are available for Enhanced CCP (ECCP) modules only. They provide half-bridge or full-bridge output steering control.
201ASP
Slide 81
CCP Control Register

CCP1 Control Register (CCP1CON) P1M1 P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPxM CCPxM2 BIT 3
0 0 CCP1M<3:0> 0 0 0 0 CCP1<X:Y> 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1
CCPxM1
CCPxM0
CCP FUNCTION Mode Selected
CCP Mode Select Bits configure the module as Input Capture, 0 0 Capture/Compare/PWM off (resets CCP module) Output Compare, or PWM 0 1 Unused (reserved)
0 Compare mode, toggle output PWM1duty cycle 2 LSBs (8 MSBs located in CCPR1L)on match 1 1 Unused (reserved)
P1M<1:0>
These PWM output configuration bits are available for Enhanced 0 0 Capture mode, every falling edge CCP (ECCP) modules only. They provide half-bridge or full-bridge 0 1 Capture mode, every rising edge output steering control.
1 1 0 0 1 1 x 0 1 0 1 0 1 x Capture mode, every 4th rising edge Capture mode, every 16th rising edge Compare mode, set output on match Compare mode, clear output on match Compare mode, generate software interrupt on match Compare mode, trigger special event PWM mode
201ASP
Slide 82
Capture Mode
CCPx
Prescaler 1, 4, 16
CCPxIF in PIRx
TMR1H
Edge Detect and
TMR1L
Single Buffered
System Clock (Fosc)
CCPRxH CCPRxL
P1M1
P1M0
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPxCON
201ASP
Slide 83
Capture Mode
CCPx
CCPxM3 0 0 CCPxM2 1 1
Prescaler 1, 4, 16
CCPxIF in PIRx
TMR1H
CCPxM1
TMR1L
Edge Detect 0 and 0

0 1 0 1
CCPxM0
MODE Capture every falling edge Single Buffered Capture every rising edge Capture every 4th rising edge Capture every 16th rising edge
0 1 1 System Clock (Fosc) 0 1 1
CCPRxH CCPRxL
P1M1
P1M0
CCPxCON
201ASP
Slide 84
Capture Initialization
TMR1H ;Turn off CCP module CCP1 0 0 0 0 0 0 0 0 banksel CCP1CON Pin clrf CCP1CON TMR1L 0 1 ;Make sure Timer1 is off 0 Current Timer1 0 0 0 0 0 0 TIMER1 INCREMENTING!! Value 0 bcf T1CON,TMR1ON 4th 3nd 2rd 1st ;Clear Timer1 registers Rising Edge CCPR1H clrf TMR1H Detected!! clrf TMR1L ;Disable all interrupts for CCP CCPR1L bcf PIR1,CCP1IF Captured! banksel PIE1 bcf PIE1,CCP1IE PIR1 ;Set CCP1 pin for input 1 0 bsf TRISC,2 ;Set Capture for every 4th rising edge CCP1IF CCP1CON banksel CCP1CON movlw b00000110 0 0 0 0 0 1 0 0 0 1 movwf CCP1CON ;Start Timer1 incrementing T1CON bsf T1CON,TMR1ON ;Test the interrupt flag for capture 1 0 btfss PIR1,CCP1IF TMR1ON goto $-1
Compare Mode
TMR1H TMR1L
CCPxIF in PIRx
COMPARATOR
Does TMR1H:TMR1L = CCPRxH:CCPRxL
NO YES OUTPUT LOGIC

CCPx
??
CCPRxH CCP1CON
P1M1 P1M0
CCPRxL
Special Event Trigger
201ASP
Slide 86
Compare Mode
TMR1H TMR1L
CCPxIF in PIRx
COMPARATOR
CCPxM3 1 1 1 CCPxM2 CCPxM1 Does TMR1H:TMR1L = 0 0 CCPRxH:CCPRxL 0 0 0 1 0
NO
CCPxM0 MODE
??
0 1
OUTPUT YESSet output on match (CCPxIF is set) CCPx LOGIC

Clear output on match (CCPxIF is set) Generate software interrupt on match (CCPxIF is set CCP1 pin unaffected) Trigger special event (CCPxIF is set, CCP1 resets TMR1 or TMR2 and starts an A/D conversion if enabled) Event Trigger Special
CCPRxH
CCPRxL
P1M1
P1M0
201ASP
Slide 87
Compare Initialization
TMR1H
;Turn off the CCP module banksel CCP1CON clrf CCP1CON ;Turn off Timer1 bcf T1CON,TMR1ON ;Clear Timer1 result registers clrf TMR1H clrf TMR1L ;Disable CCP1 interrupt and make sure ;its flag is clear banksel PIE1 bcf PIE1,CCP1IE banksel PIR1 bcf PIR1,CCP1IF ;Make CCP1 pin output banksel TRISC bcf TRISC,2 ;Initialize Compare to set output on match banksel CCP1CON movlw b00001000 movwf CCP1CON ;Load Compare value into CCPR1H:CCPR1L banksel CCPR1H movlw b10000000 movwf CCPR1H clrf CCPR1L ;Start Timer1 incrementing bsf T1CON,TMR1ON ;Test CCP1IF for Timer1 match with CCPR1x btfss PIR1,CCP1IF goto $-1
TMR1L TMR1H:TMR1L = 1000 0000 0000 0000 0 0 0 0 0 0 0 0 TIMER1 INCREMENTING!! (CCPR1H:CCPR1L Value) CCPR1H
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 1 0
CCPR1L
T1CON
TMR1ON CCP1CON
0
PIR1
1 0
0 1 0
CCP1IF
Slide 88
PWM Mode

Generates a Pulse-Width Modulated (PWM) signal on the CCP1 and CCP2 pins Duty cycle, period and resolution determined by the following registers
Register
PR2 T2CON CCPRxL CCPxCON
Description
Period Register Timer2 Control 2 Duty Cycle Registers 2 CCP Control Registers
201ASP
Slide 89
PWM Block Diagram

Period 1
CCP1<X:Y> DUTY CYCLE CCPR1L VALUE DOUBLE BUFFER
Period 2
10
LATCH
CCPR1H
10
TMR2 = CCPR1H COMPARATOR 10

TMR2 incrementing TMR2 Reset to 0s
(1)
Period Start
CCP1 Output Pin
R
Latch
8 COMPARATOR TMR2 = PR2 8 PR2

0 1 CCP1 pin
Note (1): TMR2 is concatenated with the 2-bit FOSC, or 2-bits from Prescaler to create 10-bit time base
201ASP Slide 90
PWM Initialization
TMR2
;Turn off CCP1 pin by setting TRISC bit HIGH banksel TRISC bsf TRISC, 2 ;configure pin as input ;Clear Timer2 banksel TMR2 clrf TMR2 ;Set up Period and Duty movlw b01111111 movwf PR2 movlw b00011111 movwf CCPR1L Cycle ; ;Load a Period Value ; ;Load Duty Cycle Value
0 0 0 0
PR2
0 0 0 0
0 1 1 1 1 1 1 1
CCPR1L
0 0 0 1 1 1 1 1
CCP1CON
0 0 1 0 1 1 0 0
duty cycle LSBs CCP1<X:Y> PWM Mode CCP1M <3:0>
;Configure CCP module for PWM ;and LSBs of Duty Cycle = b10 movlw b00101100 movwf CCP1CON ;Turn CCP1 pin back on (make it an output) banksel TRISC bcf TRISC,2 ;Start the PWM by turning on Timer2 ;Configure Prescaler and Postscaler to 1:1) movlw b00000100 movwf T2CON
T2CON
0 0 0
0 0 1 0 0
Prescaler bits T2CKPS<1:0>
TMR2ON
Prescaler bits TOUTPS<3:0>
201ASP
Slide 91
Pulse Width Modulation (PWM) Lab
201ASP
v8.0
PWM Lab Objectives

Become familiar with the CCP module configuration and operation in PWM mode Gain additional exposure to Timer2 configuration
201ASP
Slide 93
PWM Lab Overview

The PWM waveform is output on the CCP1 pin (RC2) that will emit a tone on the PICdem2 plus onboard buzzer. When the lab is completed, a 50% duty cycle at a period of 256/(Fosc/4) will drive the buzzer.
201ASP
Slide 94
PWM Lab Overview

Main Code
Load PR2 value Set up RC2 as output pin
Load CCPR1L for 50% duty cycle
Configure CCP as 8-bit PWM Turn on Timer2 w/ 1:1 pre scaler
NOP
201ASP
Slide 95
PWM Lab Specifics

Code for the lab is in C:\RTC\201_ASP\Lab4-PWM Complete the following sections

Configure PORTC pin 2 ( CCP1) as an output Set CCP in PWM mode Clear CCP1X and CCP1Y (8-bit PWM) Configure Timer2 with 1:1 pre-scaler
201ASP
Slide 96

The code to load PR2 (Timer2) and to set a 50% duty cycle has been provided. These values can be seen in the code The CCP1 pin is RC2 (Pin 2 of PORTC) on the PIC16F877 Registers needed to complete this lab are:

TRISC T2CON CCP1CON

201ASP Slide 97
PWM Lab Solution

;***************************************************************** ; Set CCP1 as an output ;***************************************************************** bcf TRISC,2 ; ### config CCP1 pin PORTC<2> as output bcf movlw movwf STATUS,RP0 0x80 CCPR1L ; point to BANK0 ; establish duty cycle @ 50%
;***************************************************************** ; Put CCP1 module in PWM mode. ;***************************************************************** movlw movwf 0x0C CCP1CON ; ### configure CCP for PWM ; ###
;***************************************************************** ; Configure Timer2 pre and post scale of 1:1 and turn Timer2 on ;***************************************************************** bsf T2CON,TMR2ON ; ### turn on TMR2
201ASP
Slide 98
PWM Lab Questions

Question: Why didnt we have to enable the interrupts for the PWM to work? Answer: PWM will run concurrently with the PICmicro MCU without slowing the processor down
201ASP
Slide 99
Output Compare Lab
201ASP
v8.0
Output Compare Lab

Goals of the lab are to gain experience with the following:

Setting up the CCP for Output Compare Configure the Special Event Flag to reset Timer1 Configure the CCP to generate an Interrupt on Timer1 overflow Using an Interrupt Vector to modify the interval between Interrupts
201ASP
Slide 101
Compare Lab Overview

This lab configures the CCP into output compare mode driven by Timer1 An Interrupt is used to change the sound of the buzzer During the Interrupt Service Routine (ISR):

The RC2/CCP1 pin (connected to buzzer) is toggled The ISR period is reduced:

The Compare Register (CCPR1L) is decremented The Timer1 count registers are reset
The combination of a reduced period and the CCPR1L roll-over will cause the buzzer to emit a chirping sound
201ASP Slide 102
Compare Lab Overview

Interrupt Vector
Save Context Clear IF Initialize Timer1 Toggle CCP Output Pin
Main Program
Configure CCP as Output Compare
Drives Buzzer
Initialize PORT C Decrement CCPR1L Reset Timer1 RETFIE
Turn on timer1 NOP
201ASP
Slide 103
Compare Lab Specifics

The code for this lab is in C:\RTC\201_ASP\Lab5-CCP Complete the following sections:
Configure the CCP as an Output Compare that sets the Special Event Flag and CCP1IF Configure Timer1 with a clock source of Fosc/4 and a pre-scaler of 1:8 Configure Special Function Registers to allow the CCP interrupt to occur
201ASP
Slide 104

The registers needed to complete this lab are:

INTCON (Interrupt Control) T1CON (Timer1 Control) CCP1CON (CCP1 Control) PIE1 (Peripheral Interrupt Enable)

The Interrupt Vector has been provided The Value of CCPR1L will rollover from 0 to 0xFF and continue to decrement
201ASP
Slide 105
Compare Lab Solution

; ; Set CCP1CON to Output Compare mode with Special Event Trigger ; to clear the Timer 1 register pair on a match ;**************************************************************** movlw 0x0B ; ### value for CCP1CON movwf CCP1CON ; move to CCP1CON ; ; Configure Timer 1 for Fosc/4 operation. 8:1 Prescaler ; ;**************************************************************** movlw 0x30 ; ### value for TMR1 movwf T1CON ; ### move to TMR1 control register ; ; Enable Timer 1 interrupts, Peripheral Interrupts and ; Global Interrupts ;**************************************************************** bsf PIE1,CCP1IE ; ### enable CCP1 interrupt bsf INTCON,PEIE ; ### enable peripheral interrupts bsf INTCON,GIE ; ### enable global interrupts
201ASP
Slide 106
Lab Question
Question: The PWM did not require an interrupt in order to work. Do we need an interrupt to operate in output compare mode? Answer: Not necessarily
Peripherals always set their associated interrupt flag, so you have the choice of polling or directly responding to the interrupt. The choice is based on the need of your application.
201ASP Slide 107
Comparators
201ASP
v8.0
Comparator Overview

Comparator Module:
Compares analog input voltage to a reference and outputs a digital result

Vref
Analog Input (Vin) Reference Voltage (Vref)
Vin +
Comp Output (Vout)
Vout
201ASP
Slide 109
Comparator Reference Voltage

Voltage Reference can be either:

External from a device pin Internally generated with the Voltage Reference Module

Provides 16 selectable voltages from 0 to 75% of VDD
Some devices can also scale VREF+ and VREFIndependent of VDD

8R R R R R VRR
Some devices also have a fixed reference (0.6V)
VREF+
VRSS = 1
VRSS = 0
VDD CVREF
To Comparators and ADC Module
15
8R VREF-
VRSS = 1
CVREF VROE
4 VR<3:0> VREN
201ASP
VRSS = 0
Slide 110
Comparator Interrupts

An Interrupt occurs when the comparator output changes

Some devices share one flag for both comparators Some devices have independent flags
Must read the comparator output before clearing interrupt flags

Outputs found in the comparator control register (CMCON or CMxCON0) Resets the output mismatch condition
201ASP
Slide 111
Comparators and Sleep Mode

Comparators remain active in Sleep
A Comparator output change will wake-up core
After wake-up, the instruction following the SLEEP instruction or an Interrupt Service Routine (ISR) is executed
201ASP
Slide 112
Analog-to-Digital Converter (ADC)
201ASP
v8.0
ADC Overview

Analog-to-Digital Converter Module
Converts analog input signal into an 8 or 10-bit binary value Selectable internal or external reference voltage Interrupt can be generated after conversion is completed

The interrupt can wake the PICmicro from SLEEP
ADC Analog Input

Digital Output
Slide 114
ADC Control Registers

The ADC implements two control registers

ADCON0 and ADCON1 Devices with > 8 analog inputs do not have same bits shown below

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON
BIT
FUNCTION
ADCS<1:0> A/D Conversion Clock Select bits Use with ADCS2 in ADCON1 CHSx bits GO/DONE ADON Analog Channel Select bits 1 = A/D Conversion in progress 0 = A/D Conversion is completed Enables the ADC module
201ASP Slide 115
ADC Control Registers

The ADC implements two control registers

ADCON0 and ADCON1 Devices with > 8 analog inputs do not have same bits shown below

ADFM BIT ADFM ADCS2 PCFG<3:0> ADCS2 PCFG3 PCFG2 PCFG1 PCFG0
FUNCTION ADC Result Registers Format bit 1 = Right Justified, 0 = Left Justified A/D Conversion Clock Select bit Use with ADCS<1:0> in ADCON0 Port Configuration Bits Configures I/O as analog or digital
201ASP
Slide 116
ADC Result Registers

10 bit ADC result in is placed in two registers

ADRESH and ADRESL Left or Right Justified

Determined by Format Select bit (ADFM) in ADCON1 register ADRESL

LSB
ADRESH
MSB
Left Justified (ADFM = 0)

ADRESH
MSB
ADRESL
LSB
Right Justified (ADFM = 1)

ADC Module Diagram

Fosc
Conversion clock scaler
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
VREF+ pin
ADC
Holding Capacitor
Start Conversion Conversion Complete

00000011 11111111 ADRESH ADRESL Left Justified Right Justified VREFpin
ADCON0 ADCS1 ADCS0 CHS2 ADCON1 ADFM ADCS2

CHS1
CHS0
GO/DONE
ADON
Vss

201ASP Slide 118
ADC Module Diagram

PCFG <3:0>
Port Config Bits

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Fosc
AN7 AN6 AN5 AN4 AN3 Conversion clock scaler
AN2
AN1 AN0 Vdd
VREF+ pin
ADC
Holding Capacitor
Start Conversion Conversion Complete

00000011 11111111 ADRESH ADRESL Left Justified Right Justified VREFpin
ADCON0 ADCS1 ADCS0 CHS2 0 ADCON1 0 ADFM ADCS2 1

0 CHS1
CHS0 0
GO/DONE 0 1
ADON
Vss

201ASP Slide 119
Timing Considerations for ADC

When an A-to-D channel is selected time must be taken for the holding capacitor to charge All 10 bit conversions take 11 cycles to complete User must select the appropriate ADC clocking based on the system clock frequency
201ASP
Slide 120
Analog-to-Digital Conversion LAB
201ASP
v8.0
ADC Lab

This Lab will familiarize you with:

Setting up the ADC module Operating a peripheral from the Main program, not an interrupt vector Using the value read from one peripheral (ADC) to drive another peripheral (CCP in PWM mode)
201ASP
Slide 122
ADC Lab Overview

Main Program
Configure Timer 2 Configure PORT C Configure CCP for PWM Configure and Turn on ADC
Enable interrupts
Continued on next page
ADC Lab Overview (cont.)

Continued from Previous Page
Main Loop
TMR2IF=1 YES Start ADC
NO
NO ADC done? YES Put ADC value in CCPR1L Output 4 LSBs of ADC value to LEDs
ADC Lab Specifics

Complete the following sections of code in the project C:\RTC\201_ASP\Lab6-ADC
Configure the ADC to return a left justified value Set ADC Conversion Clock to FOSC/32 Turn on ADC unit Complete the code to start an ADC and wait for the conversion to finish in the main control loop
201ASP Slide 125

This lab does not do the ADC conversion in an interrupt routine. We will use a polling method. Writing the value of the ADC conversion into CCPR1L will change the duty cycle of the buzzer ADCON1 and ADCON0 special function registers are used to complete this lab
201ASP Slide 126
ADC Solution
;************************************************************************* ; Configure ADC: Channel 0, left justified, Tad = 8 * Tosc, turn on ADC ;************************************************************************* clrf ADCON0 ; ### ensure default channel is set to channel 0 bsf ADCON0,ADCS1 ; ### set Tad = Fosc/4 bsf ADCON0,ADON ; ### turn on ADC bsf STATUS,RP0 ; ### point to BANK1 movlw 0x0E ; ### left justify, configure AN0 analog movwf ADCON1 ; ; Enable Timer 2 interrupts, Peripheral Interrupts and Global Interrupts ; bsf PIE1,TMR2IE bsf INTCON,GIE bsf INTCON,PEIE bcf STATUS,RP0 ; return to BANK0 ; ;************************************************************************* ; add three lines of code to start the ADC conversion and wait for the ; conversion to complete ;************************************************************************* bsf ADCON0,GO ; ### start ADC conversion btfsc ADCON0,GO ; ### Is the conversion done? goto $-1 ; ### no: loop until done
ADC Lab Question

Question: Instead of waiting for TMR2IF to be set in the main program, could we start the ADC from within an interrupt routine? Answer: YES
201ASP
Slide 128
ADDRESSABLE Universal Synchronous Asynchronous Receiver Transmitter (AUSART)
201ASP
v8.0
AUSART Overview

Serial I/O communications peripheral
Sometimes called Serial Communications Interface (SCI) Can be synchronous or asynchronous Can receive and transmit

Main Functions:

Full-duplex asynchronous transmit and receive Half-duplex synchronous master and slave
Most common use
RS-232 communications to a PC serial port

Needs driver for RS-232 level shifter
Enhanced (EUSART) features allow interface with a Local Interconnect Network (LIN) bus system
201ASP Slide 130
AUSART Registers

Baud rate generator registers

SPBRG (8 bit for AUSART) SPBRG and SPBRGH (16 bit for EUSART) TXSTA RCSTA TXREG RCREG
201ASP Slide 131

Transmit status and control
Receive status and control
Transmit data register
Receive data register
TXSTA Register
CSRC
Bit CSRC
TX9
TXEN
SYNC
SENB
BRGH
TRMT
TX9D
Function Clock Source Select 1 = Master Mode (clock generated internally from BRG) 0 = Slave Mode (clock from external source) Ninth bit transmission enable Transmit Enable bit, 1 = Tx enabled, 0 = Tx disabled AUSART Mode , 1 = Synchronous Mode, 0 = Asynchronous Mode For EUSART only 1 = Send sync break character bit 0 = Sync break transmission is completed Baud Rate Select, 1 = High Speed, 0 = Low Speed Transmit Shift Register (TSR) status 1 = TSR empty, 0 = TSR is full Ninth bit of transmit data
201ASP Slide 132
TX9 TXEN SYNC SENB
BRGH TRMT TX9D
RCSTA Register
SPEN
Bit SPEN Serial Port Enable
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled
RX9
SREN
CREN
ADDEN
Function
FERR
OERR
RX9D
RX9 SREN CREN ADDEN
1 = Enable 9-bit data reception, 0 = 8-bit data Synchronous mode (Master), 1 = enable single Rx, 0 = disable single Rx Continuous Receive Enable, 1 = enable, 0 = disable Address Detect Enable bit
1 = enable (enable interrupt and load the Rx buffer when RSR<9> is set) 0 = disable and use 9th bit for parity
FERR OERR RX9D
1 = framing error occurred (Stop bit not detected) 1 = Overrun error occurred (FIFO was still full when other data was loaded) Ninth bit of received data
201ASP Slide 133
Transmit Block Diagram

DATA BUS TXREG TXIF TXIE
Interrupt
Set TXIF
TXEN
MSB LSB
Clear TXIF
Pin Buffer and Control SPEN
Transmit Shift Register (TSR) Baud Rate Generator TX9D TX9
TX/DT pin
Enables Serial Port

TRMT
Ninth data bit
Set TRMT bit Indicates shift register is empty Clear TMRT bit TSR has data in it
201ASP Slide 134
Receive Block Diagram

Enable Serial Port
SPEN
RX/DT pin
Receive Shift Register (RSR) Pin Buffer and Control Data Recovery
RX9
STOP START
Baud Rate Generator
FIFO
Set RCIF flag Clear RCIF flag

RCIE RCIF
RCREG
RX9D
Interrupt
Data Bus
201ASP
Slide 135
MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
201ASP
v8.0
MSSP Overview

The MSSP module can operate in one of two modes:
SPI (Serial Peripheral Interface)

3 pins are used

Serial Data Out (SDO) Serial Data In (SDI) Serial Clock (SCK)
I2C (Inter-Integrated Circuit)

Full Master mode Slave mode (with general address call) 2 pins are used

Serial Clock (SCL) Serial Data (SDA)
The MSSP Control Register (SSPCON) determines which mode you are in.
We will cover
2C I
mode only
Slide 137
201ASP
I2C Conditions

Conditions :
START (S) STOP (P) ACKNOWLEDGE (A) RESTART (R)
SDA SCL
SDA pulled LOW released while SCL is still HIGH
Recipient does quickly followed Stop conditionLOW drive SDA SDA goes not during LOW th clock pulse of by a9Start condition SCL
NEGATIVE or NOT-ACKNOWLEDGE (N)

201ASP Slide 138
External IC EEPROM Read

MASTER
+5V
SCL
SDA
READ WRITE GOTO STOP DATA MODE ADDRESS
BUSY BUSY
PIC
LISTEN
EEPROM SLAVE START MEMORY RESTART STOP ACK NACK ADDRESS ADDRESS
LISTEN
EEPROM
LISTEN
SLAVES
ACK DATA
201ASP
Slide 139
MSSP Control Registers 2

(I C mode)
P S
1 of 3: MSSP Status Register (SSPSTAT)

SMP CKE D/A R/W UA BF
CONTROL BITS DETECTION BITS (FLAGS)
BIT SMP CKE D/A P S R/W UA BF
FUNCTION Slew Rate Control bit Not used in I2C mode Last byte Rx/Tx was data or address Stop Condition Detected Start Condition Detected Slave :READ/WRITE or Master = transmit in progress Address needs to be updated The SSPBUF register is full
201ASP
Slide 140

(I C mode)
P S
1 of 3: MSSP Status Register (SSPSTAT)

SMP CKE D/A R/W UA BF
BIT SMP CKE D/A P S R/W UA BF
FUNCTION Slew Rate Control bit Not used in I2C mode Last byte Rx/Tx was data or address Stop Condition Detected Start Condition Detected Slave :READ/WRITE or Master = transmit in progress Address needs to be updated The SSPBUF register is full
201ASP
Slide 141

(I C mode)
2 of 3: MSSP Control Register 1 (SSPCON)
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
FUNCTION Write Collision Detected A write to the SSPBUF before previous value processed Enables MSSP module Enables clock Mode Select Bit
Mode Select bits

201ASP Slide 142
SSPM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SSPM2 0 0 0 1 1

SSPM1 SSPM0 Mode
(I C mode)
0 0
0 1
SPI Master mode, clock = FOSC/4 SPI Master mode, clock = FOSC/16
2 of 3: MSSP Control Register 1 (SSPCON) 0 1 0 SPI Master mode, clock = FOSC/64

WCOL SSPOV SSPEN Master mode, clock = TMR2 output/2 SSPM0 1 1 SPI CKP SSPM3 SSPM2 SSPM1
0 CONTROL BITSSPI Slave mode, DETECTION BITS (FLAGS) enabled 0 clock = SCK pin, SS pin control 0 1 SPI Slave mode, clock = SCK pin, SS pin control disabled, FUNCTION SS can be used as I/O pin 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 I2C Slave mode, 7-bit address Write Collision Detected I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) Reserved Reserved Reserved Reserved
BIT
1 WCOL 1 SSPOV 0
A1 write to I2C Slave mode, 10-bit address the SSPBUF before previous value processed Enables MSSP module Enables clock
SSPEN
0
CKP 0
0 SSPM3 1 SSPM2 1 1
I2C firmware controlled Master mode (Slave idle) Mode Select Bit
SSPM1 SSPM0
1
Mode Select bits

201ASP Slide 143
I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

(I C mode)
3 of 3: MSSP Control Register 2 (SSPCON2)
GCEN ACKSTAT ACKDT
CONTROL BITS
ACKEN
RCEN
PEN
RSEN
SEN
DETECTION BITS (FLAGS)
BIT GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
FUNCTION Generates an interrupt when a call is received (slave mode) 0 = Acknowledge received from slave (transmit mode) 0 = ACK 1 = NACK (receive mode) Initiate ACK/NACK condition (Transmits ACKDT bit) Enables receive mode Initiates a STOP condition Initiates a RESTART condition Initates a START condition Initiates a START condition
201ASP
Slide 144

(I C mode)
3 of 3: MSSP Control Register 2 (SSPCON2)
GCEN ACKSTAT ACKDT
CONTROL BITS
ACKEN
RCEN
PEN
RSEN
SEN
DETECTION BITS (FLAGS)
BIT GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
FUNCTION Generates an interrupt when a call is received (slave mode) 0 = Acknowledge received from slave (transmit mode) 0 = ACK 1 = NACK (receive mode) Initiate ACK/NACK condition (Transmits ACKDT bit) Enables receive mode Initiates a STOP condition Initiates a RESTART condition Initates a START condition Initiates a START condition
201ASP
Slide 145
Tx/Rx Buffer (SSPBUF)

Buffer register containing Tx and Rx data

SSPBUF interfaces to a shift register (SSPSR) for shifting data in or out
When full, the Buffer Full (BF) bit in the SSPSTAT register is set Any write to the SSPBUF register during Tx/Rx of data will be ignored, and the write collision detect bit (WCOL) of the SSPCON register will be set
201ASP
Slide 146
I2C Address Register (SSPADD)

Slave mode:
Contains the slave address of the PIC Compared against the received value
Master mode:
Used to calculate the clock speed (BAUD rate) of the I2C system.
Fosc BAUD RATE = 4 v ( SPADD 1)

*NOTE: FOSC is the frequency of the oscillator not the Instruction Clock TCY
MSSP Interrupts

The MSSP interrupt flag (SSPIF) is set in the PIR1 register with the following events:

START condition STOP condition Tx or Rx complete Acknowledge transmit RESTART condition
201ASP
Slide 148
I2C Based Temp Sensor Lab
201ASP
v8.0
I2C Based Temp Sensor Lab Objective

Configure some MSSP control registers to enable I2C communication to the I2C based Temp sensor on the PICDEM 2 Plus board. Temperature reading (lowest 4 bits) will be displayed on the LEDs.
201ASP
Slide 150
I2C Lab Overview

This lab configures the MSSP as an I2C Master The TC74 Temperature Sensor is then read by the MSSP module The temperature reading is then sent to PORTB to be displayed on the 4 LEDs
201ASP
Slide 151
I2C Lab Overview

Main Code
Configure I/0s Configure MSSP
Initiate I2C start condition
Send Temp Sensor Address
Loop
Read Temperature
Display Temp LSB on PORTB LEDs

I2C Lab Specifics

Code for the lab is in C:\RTC\201_ASP\Lab7-I2C Complete the following sections:
Disable the slew rate control

Well be using I2C standard rate (100KHz)
Configure the MSSP to operate as an I2C master and enable the data (SDA) and clock (SCL) pins Start the data transfer and check for when it has completed
201ASP Slide 153

Slew rate control is found in the SSPSTAT register Registers needed to complete this lab are:

SSPSTAT SSPCON SSPCON2
201ASP
Slide 154
I2C Lab Solution

;-------------------------------------------------------------; set the slew rate and baud rate for 100 kHZ operation BANKSEL SSPSTAT bsf SSPSTAT,SMP ; ### point to correct BANK for SSPSTAT ; ### Set for standard speed slew rate
;-------------------------------------------------------------; Configure as I2C master with Fosc/4 Clock source BANKSEL SSPCON bsf SSPCON,SSPM3 bsf SSPCON,SSPEN
; ### set to I2C master mode with ; Fosc/4 clock source ; ### Enable SDA and SCL pins to ; operate in I2C mode
;-------------------------------------------------------------BANKSEL bsf btfsc goto SSPCON2 SSPCON2,SEN SSPCON2,SEN $-1 ; ; ; ; Initiate a START condition ### set the SEN bit ### is it finished? no: test again
201ASP Slide 155
Multiple Interrupt Lab
201ASP
v8.0
Multiple Interrupts Lab

This Lab involves:

Dealing with 2 (or more) concurrent interrupts Determining the source of an interrupt Deciding which interrupt request will be serviced first
201ASP
Slide 157
Lab Overview
Main Program
Set up CCP as Output Compare just as in Lab 6 Enable Timer1 and PORTC as In Lab 6 Setup PORTB and enable External Interrupts on S3as in Lab 1 NOP
Continued on next slide
201ASP
Slide 158
Interrupt Service Routines
Lab Overview
INT_ISR
Call debounce Delay routine
CCP_ISR
Clear IF Put -1 in WREG
Toggle variable Called push_flag
push_fla g Set ?
Clear IF
Put 0 in WREG Add WREG to CCPR1L
Return to Main
Return to Main
Lab Overview (cont.)

Save context
Interrupt Handler
NO
Did CCP generate the interrupt?
YES
Did INT generate the interrupt?
Go to CCP service routine
YES
Service External Interrupt
NO
Return to Main
Lab Specifics

Lab is found in:
C:\RTC\201_ASP\Lab8-MXINT
The two Interrupt Service Routines (ISRs) are provided:

INT_ISR CCP_ISR
Complete the following sections of code
When an interrupt occurs, determine the cause and transfer control to the appropriate ISR Set the Special Function Registers (SFRs) to enable INT and CCP1 Interrupts to occur
201ASP Slide 161
What you need to know for Lab

INTCON, and PIR Special Function Registers are used in this lab
201ASP
Slide 162
Lab Solution
Int_Service_Routine call save_regs; btfsc goto btfsc goto Finish_Int call retfie INTCON,INTF INTE_ISR PIR1,CCP1IF CCP_ISR Restore_Regs
; save W, STATUS, & PCLATH ; ### test for INTE interrupt request ; ### test for CCP interrupt request ; restore W, STATUS & PCLATH
201ASP
Slide 163
Lab Solution ( cont.)
bsf bsf bsf bsf bcf
PIE1,CCP1IE INTCON,INTE INTCON,GIE INTCON,PEIE STATUS,RP0
;### enable CCP1 interrupt ;### enable ;### enable ;### enable ; return to INTE interrupt global interrupts peripheral interrupts BANK0
201ASP
Slide 164
Lab Questions
Question: Why is there a noticeable silence when S3 is pushed? Answer: Since debounce is called during an interrupt and the GIE bit is cleared, the CCP1 interrupt that toggles the buzzer is not allowed to operate. Therefore, the buzzer goes quiet.
201ASP
Slide 165
Lab Questions (cont.)

Question: How can this silence be eliminated and the buzzer continue to run? Answer: 1. Capture S3 in Main and call debounce while GIE is set 2. Use a timer to accomplish the delay 3. Re-enable interrupts during the INT ISR
201ASP Wrap-Up
201ASP
v8.0
Peripherals Class Wrap-up

Today we covered the following peripherals on the Mid-Range family

I/O ports Interrupt structure and processing Timers (timer0, timer1, timer2) CCP Module ( Output Compare, Input Capture, PWM) Comparators and Analog-to-Digital Converters

Voltage Reference
AUSART Serial Port I2C using the MSSP module

201ASP Slide 168
Final Word

This discussion has followed the standard Microchip datasheet flow:

Overview of Peripheral Use these sections to: Develop logical flow charts or pseudo-code (Avoid Spaghetti Programming!!) Other Tips: Comment your code thoroughly Choose descriptive names for user defined registers
Register Description and Configuration Enhanced or Special Features
*Packaging and Electrical Specifications are at the end of the datasheet

Resources

Visit www.microchip.com for: 24/7 technical support Application Notes Web Seminars Code examples Datasheets and Much More!
201ASP
Slide 170
Thank You!!
201ASP
v8.0

Cau Truc Pic 16f877a Vi Xu Ly

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Cau Truc Pic 16f877a Vi Xu Ly

Uploaded by

Copyright:

Available Formats

201ASP

Mid-Range Family Peripheral Configuration and Assembly Programming

2006 Microchip Technology Incorporated. All Rights Reserved.

At the end of this class you will:

2007 Microchip Technology Incorporated. All Rights Reserved.

To get the most from this Class

Ideally you should be familiar with the following:

2007 Microchip Technology Incorporated. All Rights Reserved.

2007 Microchip Technology Incorporated. All Rights Reserved.

201ASP Agenda (cont.)

Capture / Compare / PWM Module (CCP)

PWM and Output Compare Labs

Analog Comparator Analog to Digital Converters (ADC)

I2C Based Temp Sensor Lab

Wrap-Up and additional questions

2007 Microchip Technology Incorporated. All Rights Reserved.

Mid-Range Family Basic Architecture and Development Tools

2006 Microchip Technology Incorporated. All Rights Reserved.

Mid-Range PIC Block Diagram

8-bit value from instruction

Banks of Data Memory

(8K x 14 bits/word)/1 byte = 14Kbytes of memory

Interrupt Vector 0004h Page 0 Page 1 Page 2 Page 3

Reset Vector at 0000h

Program Counter (PC) will go to this address on reset

Interrupt Vector at 0004h

Program Counter (PC) will go to this address upon any Interrupt

2007 Microchip Technology Incorporated. All Rights Reserved.

Program Counter (PC) and Stack

PCL ALU result (8-bits) or OPCODE(11-bits) PCH Paging bits

Updated from PCLATH Specifies page in program memory

8 Level Deep Stack

Stores the contents of the PC

CALL/Interrupt RETURN, RETFIE,RETLW

2007 Microchip Technology Incorporated. All Rights Reserved.

Data Memory Map

Special Function Registers 01Fh

Special Function Registers

100h 10Fh 110h

180h 18Fh 190h

General Purpose Registers

General Purpose Registers

General Purpose Registers

General Purpose Registers

2007 Microchip Technology Incorporated. All Rights Reserved.

Special Function Registers (SFRs)

TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2

86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh

2007 Microchip Technology Incorporated. All Rights Reserved.

BANK0 BANK1 BANK2 BANK3

2007 Microchip Technology Incorporated. All Rights Reserved.

PIC16 Instruction Set

2007 Microchip Technology Incorporated. All Rights Reserved.

PICmicro Development Tools

2006 Microchip Technology Incorporated. All Rights Reserved.

January 2007 Slide 14

2007 Microchip Technology Incorporated. All Rights Reserved.

2007 Microchip Technology Incorporated. All Rights Reserved.

ICD 2 (In Circuit Debugger)

MPLAB ICD 2 is a low cost, real-time realdebugger and programmer.

2007 Microchip Technology Incorporated. All Rights Reserved.

PICDEM 2 Plus Board

RS232 Connecto r Analog Pot