Chapter 5 I/O Interfacing

Input and output (I/O) are two other integral components of a microprocessor-based system. I/O devices, such as keyboards and displays, and the ears and eyes of the MPUs, they are the communication channels to the outside world. 5.1 Interfacing Output Devices In peripheral-mapped I/O, a device is identified with an 8 bit address, and I/O related control signals are used to enable the device. The process of data transfer is in many similar to that of readily from or writing into a memory register. The Z80 uses the instruction IN to read (input) data from an input device and uses the instruction OUT to write (send) data to an output device. 5.1.1 OUT Instruction The Z80 microprocessor has several output instructions to send (copy or write) data to an output device. It can send data from the accumulator, internal-purpose registers, or memory registers to an

output device. The OUT instructions include the 8 bit address of a device as an operand. The address range from 00H to FFH is called the I/O or peripheral map, and an address can be referred to as a device address, port address, or port number. opcode OUT operand (8-bit),A Description This is a 2byte instruction with the hexadecimal opcode D3, and the second byte is the port address of an output device. This instruction transfer (copies) data from the accumulator to the output device. Typically, to display the contents of the accumulate at an output device (such as LEDs) with the address, for example, 07H the instruction with be written and stored in memory as follows;

Memory Address 2050 2051

Machine Code 03 07

Mnemonics OUT (07H), A

When the microprocessor reads and executes the machine codes written at memory register 2050H and 20541H, it will transfer (copy) the byte from the accumulator to the LED port with address 07H and display the byte. 5.1.2 Execution of OUT Instruction and Timing The OUT has three machine cycles; Opcode Fetch, Memory Read and I/O Write. The Z80 reads the opcode an the port address from memory in the first two machine cycles and writes into the port in the third cycle. Devices 5.1.3 Basic Concepts in Interfacing Output

The concepts in interfacing output devices are similar to those in interfacing memory. The steps can be listed as follows:

1.

Describe the low-order address bus to generate a unique pulse corresponding to the port address on the bus; this is called the I/O address (IOADR ) pulse. Combine (AND) the I/O address pulse (IOADR ) ,
I R OQ

2.

, and

W R

to generate the IOSEL (I/O (I/O Write)by combining

IO R W

select) pulse (Figure 5.2 (a)).Another approach is to generate the

I R OQ

IO R W

and

W R

, and then combine

with the

(IOADR ) (I/O address) pulse to generate the IOSEL pulse (Figure 5.2(b)). The critical concept here is that the decoded address,
I R OQ

, and

W R

are all necessary to latch the data at the appropriate time; how these signals are combined is often dictated by the availability of decoding devices (chips) in the system. 3. Use the IOSEL pulse to enable (activate) the output device. The generated IOSEL pulse is active high because latches are generally used as output devices and an active high-to-low pulse is needed to enable the latch and to store data bits. For input devices, the IOSEL pulse is generally active low (explained in Section 5.3). 5.2 Illustrative Example 1: Interfacing LEDs In this section, we will analyze an actual interfacing circuit with the port address 07H to display binary at an LED port and a single digit at a sevensegment LED. A group of 8 LEDs will be used to indicate binary 15 and 05 and will be connected to the data bus using the 7475 latches. Similarly, an interfacing of a seven-segment LED will be demonstrated using an octal latch 74 LS373.
5.2.1 Hardware

5.2.2 Interfacing Circuit

1.

An 8-input NAND gate with five inverters is used to decode the low-order address bus A7-A0. The output of the NAND gate is asserted when the address is 0 0 0 0 0 1 1 1 (07H); thus, the NAND gate performs the decoding function to generate the I/O address (IOADR ) pulse. The control signals and are ANDed in (active low).

2.

I R OQ

W R

a negative AND gate (physically, an OR gate) to generate the control signal The
IO R W IO R W

is again ANDed (through a NOR gate)

with the I/O address pulse to generate the I/O select pulse (active high). The IOSEL pulse is asserted only when the address is 07H and the control signals
3.
IO Q R

and

W R

are low.

The IOSEL pulse is used to enable the latches 7475. The data bus D7-D0 is connected to the D input, and the LED cathodes are connected to the Q output of the latch. The LED anodes are connected to the +5 V power supply through the current-limiting registers.

Instructions

To display data, for example, 97H, at this LED port, instructions are as follows: LD A, 97H; byte OUT (07H), A; port 07H The first instruction (LD) stores the second byte 97H in the accumulator, and the OUT instruction sends the byte (97H) from the accumulator to the LED port 07H. When the I/O select pulse is asserted, the byte 97H enters the latch and is displayed by the LEDs. When IOSEL goes low (inactive), the byte is latched and continues to be displayed by the LEDs. 5.2.3 Using a Seven-Segment LED as a Display Device A seven-segment LED consists of seven lightDisplay the accumulator contents at Load accumulator with the specified

emitting diodes (A through G) and one diode (DP) for the decimal point.

Instructions The following instructions are necessary to display digit 1 at the output port: LD A, 79H accumulator OUT (07H), A HALT When the microprocessor executes the OUT instruction, the IOSEL goes active and enables (LE) the latch, and the code 79H is passed on from the data bus to the latches. The output buffer of the latch ; Display digit 1 at port 07H ; Load code for digit 1 in the

is already enabled by grounding

O E

, thus, the code

displays digit 1 at the seven-segment LED by the turning on the segments B and C. 5.3 Interfacing INPUT Devices

The interfacing of input devices is almost identical

to that of interfacing output devices, but with some differences in bus signals and circuit components. 5.3.1 IN Instruction The Z80 instruction set included several instructions to read (copy) data from such input devices as switches, keyboard, and A/D data converters. These instructions can read an input device and place the data into the accumulator, Z80 registers, or memory registers. The addresses for devices can range from OOH to FFH. Opcode IN Operand A, (8-bit) Description This is two byte instruction with the hexadecimal opcode DB, and the second byte is

the port address on an Input device. This instruction reads (copies) data from and input device and places the data byte into the accumulator. To read switch positions, for example, from and input port with the address 84H, the instructions will be written and stored in memory as follows: Memory Address 2065 2066 Machine Code DB 84 Mnemonics IN A, (84H)

When the microprocessor is asked to execute these instructions, it will first read the machine codes stored at locations 2065H and 2066H, then read the switch positions at port 84H by enabling the interfacing device of the port. The data byte indicating switch positions from the input port will be placed in the accumulator.

5.3.2 Execution of IN Instruction and Its Timing The IN instruction has three machine cycles: Opcode Fetch, Memory Read and I/O Read. In the first two machine cycles, the Z80 reads the opcode DB and the port address 84H.. In the third machine cycle, the Z80 reads a data byte from the input port as follows:
1.

The port address 84H is placed on low-order address bus at the beginning of the machine cycle M3 (I/O Read). During T2, the control signals automatically after T2. and are

2.

IO Q R

R D

asserted, and one Wait state is inserted During T3, the Z80 reads the data bus and then
R causes the control signals ( IO Q and

3.

R D

) to go

inactive.

5.3.3 Basic Concepts in Interfacing Input Devices

To interface an input port with the address 84H we need to logically AND the information on the address bus with the control signals and enables the input port. The steps are as follows; 1. Decode the low-order bus to generate the I/O address pulse.
2.

Combine the I/O address pulse with the control signals

I R OQ

and

R D

to generate the signal I/O to generate an

IO D R

Select ( IOSEL , Figure 5.8). Another approach is to combine

I R OQ

and

R D

IO D R

signal and then to combine the

with the I/O

address pulse to generate the I/O select pulse.

3. Enable the input interfacing device using the I/O select pulse.

Chapter 5 I/O Interfacing

5.1.1 OUT Instruction

5.1 Interfacing Output Devices 5.1.2 Execution of OUT Instruction and Timing Devices 5.1.3 Basic Concepts in Interfacing Output

5.2 Illustrative Example 1: Interfacing LEDs

5.2.1 Hardware 5.2.2 Interfacing Circuit

5.2.3 Using a Seven-Segment LED as a Display Device 5.3 Interfacing INPUT Devices 5.3.1 IN Instruction 5.3.2 Execution of IN Instruction and Its Timing 5.3.3 Basic Concepts in Interfacing Input Devices