1.0 Cmos Opamp: 1.1. General Opamp Block Diagram

1.
0 CMOS OPAMP

1.1. General Opamp Block Diagram

A1 -A2 A3
Cc
V
1
V
2
V
O
V
in
Differential
stage gain
Inverter
stage gain
Buffer
stage gain

Figure 1. Opamp General Block Diagram

Note the second stage needs to have a negative gain because of the feedback capacitor. With a positive
gain an oscillator or unstable system will be implemented instead. The last stage is a buffer to convert the
high output impedance of the inverter stage to a low output impedance. This is needed in developing a
good opamp. Ideal opamp requires r
in
= and r
o
=0.

Figure 2. The Effect of Compensation Capacitance Cc.

At the input side,

A) 1 ( sC
1
I
V
;
sC
1
I
A) 1 ( V
;
sC
1
I
AV V
;
sC
1
I
V V
c 1
1
c 1
1
c 1
1 1
c 1
2 1
+
= =
+
=
+
=

This is known as the miller capacitance. The feedback capacitance value appears at the input side of the
gain stage with a value magnified by (1+A).

At the output side,

1 >> A when ;
sC
1
)
A
1
1 ( sC
1
I
V
;
sC
1
I
)
A
1
1 ( V
;
sC
1
I
A
V
V
;
sC
1
I
V V
c
c
2
2
c 2
2
c 2
2
2
c 2
1 2
=
+
= =
+
=
+
=

1

Due to Miller effect, the load of the first stage is effectively the compensation capacitance Cc magnified by
(1+A
2
)

A1
V
in
V
1
Cc(1+A2)=C
eq
=A2Cc

Figure 3. The Miller Capacitance Loading the First Stage.

The gain

o1 m2 o1 m1
in
1
Z g Z g
V
V
= A1 = =
where:
Z rds2 / /rds4 / /
1
sC
1
sC s(1+ A2)C sA2C
o1
eq eq C C
|
\
|
.
| =
1 1

The voltage gain of the opamp, assuming the output buffer has unity gain (A3=1),

sCc
g
sCc
g
A3
sA2Cc
g
A3A2 = A3A2A1
V
V
= Av(s)
m2 m2 m2
in
o
= = |
.
|
\
|
=

The unity gain bandwidth, w
GB
is the radian frequency when the gain is 1. That is,

1
Cc jw
g
) Av(jw Av(s)
GB
m2
GB
= = =
Solving for w
GB
,

C
m2
GB
C
g
w =

1.2. Slew Rate Determination

2
VDD
M5
M1 M2
M3 M4
-A2
Cc
Vin- Vin+
V1
V2
Vbias
Differential stage gain
Inverter stage gain

Figure 4. The Differential Gain Stage of the Opamp.

Slew rate is the maximum rate at which the output changes when input signals are large. When
vin+ >>0 (vin-<<0) is large positive (negative), M1 is on and M2 is off. Hence I
SD1
=I
SD5
, since I
SD2
=0. The
current flows through M3 which is then mirrored to M4, therefore I
SD1
=I
DS3
=I
DS4
=I
SD5
. The current in the
compensation capacitor can only flows through M4, since M2 is off and the input impedance of the second
stage A2 is . That is I
Cc
=I
DS4
=I
SD5.

On the other hand, when vin+<<0 (vin->>0) is large negative (positive), M1 is off and M2 is on. Hence,
I
SD1
=0 which flows through M3 and mirrored to M4, therefore I
DS3
=I
DS4
=0. That is, current source I
SD5

flows through M2, then to Cc directly, since M4 is off.

In both cases, the maximum current that flows through Cc is I
SD5.

The output voltage of the opamp is approximately equal to v2, since A31.

Cc
2I
Cc
I
t
Cc
q
t
) (V
= SR
SD1 SD5 o
= =
|
.
|
\
|
=
d
d
d
d

1.3. OpAmp First Order Model

The objective of compensation is to make the opamp to behave as a single pole in the frequency
of interest. That is, at least within the unity gain bandwidth frequency, w
GB
. The desired transfer function is
3

1
VO
p
s
1
A
= Av(s)
+

where:
A
VO
is the dc gain of the opamp, and p
1
is the real axis dominant pole.

DB
w
A
VO
w
BW
=p
1
w
GB
-20db/dec
Figure 5. Bode Plot of Opamp First Order Model

The relation between the unity gain bandwidth, w
GB
, and the dominant pole p
1
can be obtained by the
finding the radian frequency when the magnitude of the voltage gain is equal to 1. That is,

1
p
w
j
A
p
w
j + 1
A
) Av(jw
1
GB
VO
1
GB
VO
GB
= =

1 VO GB
p A w

At midband frequency, the gain is approximately given by :

s
w
s
p A
p
s
A
p
s
+ 1
A
= Av(s)
GB 1 VO
1
VO
1
VO
= =

1.4. An Opamp with Feedback

4
Av(s)
V
o
V
in
+
B

Figure 6. Ideal Feedback Configuration.

V A V A V
O V in V
=
O

V A A
O V V
( ) 1+ = V
in

Hence, the closed loop response is given by:

GB
GB
GB
CL
w
s
1
1 1
/s w + 1
/s w
Av(s) + 1
Av(s)
) s ( A

+
|
|
.
|
\
|
= = =
where: (1/) is the dc gain of the closed loop system. LG(s)=A
v
(s) is the loop gain. The frequency when
the closed gain is 3 Db down occurs when the LG becomes unity. That is,

1
jw
w
LG(s)
3db -
GB
= =
That is,

1 ; w w w
GB GB 3db -
= = =

1.5. Settling Time Determination

Opamps are compensated to behave as a simple pole system up to a radian frequency of w
GB
. This
is the case whenever the PM of the Opamp is designed for at least 60. The settling time is the time needed
for the output of the opamp to reach a final value to within a predetermined tolerance. This can be
determined using the first order model of the opamp given by:

)
p
(1
A
) ( A
1
VO
V
s
s
+
=

The unity feedback (=1) closed loop gain is given by:

5
1 VO
1
VO
VO
1 VO
VO
1 VO VO
VO
1
VO
V
V
CL
p A
1
)
A
1
1 (
)
A
1
1 ( p A
1
A
1
1
1

p A
)
A
1
1 (
1
A
p
1
A
) ( A 1
) ( A
) ( A
s s
s s
s
s
s
+
+
+
+
+
=
+ +
=
+ +
=
+
=

The step response is obtained as follows:

)
p A
1 (
)
A
1
1 (
) U( ) ( A ) ( V
1 VO
1
VO
CL O
s
s
s s s
+
+
= =

Taking the inverse Laplace Transform, one gets,

= = + =
+ =

1
A
1
1 )
A
1
(1 ) ( V
u(t) ) 1 ( )
A
1
(1 t) ( V
VO
1
VO
O
t w 1
VO
O
GB
e
For large A
VO
,

= =
=
1 ) ( V ) 1 ( ) t ( V
u(t) ) 1 ( t) ( V
O
t w
s O
t w
O
s GB
GB
e
e

Solve for t
s
in term of

)
1
ln( )
1
ln(
p A
1
)
1
ln(
w
1
) ( t
1 VO GB
s

= = =

For a step input the output initially slews, then slowly settles toward its final value, determined by the gain
bandwidth product.

t
s
(settling time)
<1% 4.6 5
<.5% 5.3 6

6
1.6. Opamp Second Order Model

For compensation of an Opamp, we need at least a second order model

) s/p 1 )( s/p + (1
A
= Av(s)
2 1
VO
+

DB
w
A
VO
p
1
w
GB
-20db/dec
p
2
-40db/dec
Figure 7. Bode Plot of Opamp Second Order Model.

For frequency w>>p
1
, the model reduces to:

) s/p 1 ( s
w
) s/p 1 ( s
p A
) s/p 1 )( (s/p
A
Av(s)
2
GB
2
1 VO
2 1
VO
+
=
+
=
+

The loop gain for this second order model is given by:

) s/p 1 ( s
w
= Av(s) = LG(s)
2
GB
+

The radian frequency at 3db down is obtained by setting the magnitude of LG(s) to 1.

7
1
) /p jw 1 ( jw
w
= ) LG(jw
2 3db - 3db -
GB
3db -
=
+

When p
2
>>w
-3db
, then

1 ; w
w
) p / w ( 1
w
= w
3db -
3db - 2
2 3db -
3db -
GB
= = +

Phase margin is the phase angle between the loop gain phase angle and -180 degree. It is a measure of
stability. First let us determine the loop gain phase angle:

) jw/p + (jw)(1
w
= LG(jw)
2
GB

) w/p ( tan -90 = LG(jw)) (
2
-1

o
The phase margin is computed as follows:

) /p w ( tan 90 = (-180) - )) LG(jw ( = PM
2 3db -
-1
3db -

o
PM) tan(90 p w
2 3db -
=
o

The closed loop gain is given by:

2
2 1 VO VO
2 1
CL0
CL
s
) p p )( A 1 (
1
+ s
A 1
) p / 1 (1/p
+ 1
A
Av(s) + 1
Av(s)
) s ( A

+ +
+
= =
where:
1 A ;
1
A + 1
A
A
VO
VO
VO
CL0
>> =

Comparing with general second order transfer function:

2
2
0 0
VO
2
s
) (w
1
+ s
Q w
1
+ 1
A
= s) ( H
where:
w
o
is the resonant frequency, and Q is the Q factor. We obtain,

2 GB 2 1 VO 0
p w ) p p )( A + (1 w =
8
2
GB
2
1 VO
2
2
1
1 VO
2 1
2 1 VO
2 1
2 1 VO
2 1
VO
0
p
w
p
p A
) p
p
p
(
)p A 1 (

) p (p
) p p )( A + (1
) p / 1 (1/p
) p p /( ) A + (1
Q
) p / 1 p / 1 (
A 1
Q w

=
+
+
=
+
=
+
=
+
+
=

The step response overshoot is a function of Q,

1 Q 4
2
100 = overshoot %

e

That is, when Q=0.5 there is no overshoot (%overshoot=0). In addition,
w
o
= w
-3db
and PM65

PM w
p2
/w
GB
Q %overshoot
55 1.4285 0.925 13.3%
60 1.733 0.817 8.7%
65 2.1459 0.717 4.7%
70 2.748 0.622 1.4%
75 3.733 0.527 0.008%

For no overshoot, select PM=75. Note that Q is proportional to . That is the worst case PM occurs when
=1. Thus for opamp compensation where 0<(s)<=1 is frequency dependent , if the opamp is
compensated for =1, it is guaranteed to be stable for all other .

1.7. Small Signal Equivalent Circuit

9
V-
V+
Yc
(9) (6)
(7)
(1) (2)
(5)
(3) V
DD
(4) V
SS
M1 M2
M3 M4
M5
M6
M7

Figure 8a. Schematic Diagram of Unbuffered Opamp Circuit.

10
g
d
s
2
g
d
s
4
g
d
s
6
g
d
s
7
+
-
V
o
+
-
Y
C
V
1a
=v
id
g
d
s
2
g
d
s
4
g
d
s
6
g
d
s
7
+
-
V
o
+
-
Y
C
V
1a
=v
id
g
m
2
V
1
a
g
m
6
V
1
b
V2a=V1b
+
-
g
m
1
V
1
a
V2a=V1b
+
-
g
m
6
V
1
b
+
-
V
1a
=v
id
+
-
g
m
2
V
1
a
g
m
6
V
1
b
V2a=V1b
+
-
R
1
C
1
R
2
C
2
V
2b
=V
o
(a)
(b)
(c)
Y
C
Vx
Vx
Vx
I3
I2
I1
V
1
V
2
+
+
Y1
Y3
Y2
g
m
2
V
1
V
X
g
m
6
V
X
(d)
C
2
C
1
C
1
C
2

Figure 8. Opamp Small Signal Equivalent Circuit of the First Two Stages.

In Figure 8(a) each amplifier stage is replaced by its equivalent circuit. C1 and C2 are the parasitic
capacitances of the Opamp at node 6 and 9 respectively. The second stage of an opamp is an inverter stage.
The overall gain of the opamp can be made positive, by switching the positive and negative inputs of the
differential gain stage. That is the positive input is now the gate of M2. Figure 8(b) shows this by reversing
the polarity of the first controlled current source and replacing g
m1
by g
m2
to indicate M2 gate is the
positive input. Figure 8(c) simplify the equivalent circuit by combining the resistances and
capacitances.That is,
11

DS6 7 6 ds7 ds6
2
SD2 4 2 ds4 ds2
1
I ) (
1
g g
1
R
I ) (
1
g g
1
R

+
=
+
=
+
=
+
=

From Figure 8(c), the port current equations are derived to obtain the Y parameters:

x 3 m6 2 3 2 x 2 3 2 2 x m6 2
1
)V Y - (g )V Y (Y ) V - (V Y V Y V g I
0 I
+ + = + + =
=

At node
x
V

2
3 1
3
1
3 1
m2
x
2 3 1 m2 x 3 1
2 x 3 1 m2 x 1
x 3
x 1 3
2 x 3 1 m2 3
V
Y Y
Y
V
Y Y
g
- V
0 V Y - V g )V Y (Y
0 ) V - (V Y V g V Y
, V for solve and I Substitute
V Y I
0 ) V - (V Y V g I
+
+
+
=
= + +
= + +
=
= + +

Substituting to
x
V
2
I

2
3 1
3 m6 3 2 3 1 2 1
1
3 1
m2 m6 3
2
3 1
3
1
3 1
m2
3 m6 2 3 2 2
V
Y Y
Y g Y Y Y Y Y Y
V
Y Y
)g g - (Y

V
Y Y
Y
V
Y Y
g
- ) Y - (g )V Y Y ( I
+
+ + +
+
+
=
(
+
+
+
+ + =

The resulting Y-parameter matrix is

3 2 3 1 2 1
3 1
3 m6
3 1
m2 m6 3
Y Y Y Y Y Y where
Y Y
Y g
Y Y
)g g - Y (
0 0
Y
+ + =
(
(
+
+
+
=

The voltage gain is

3 m6
m2 3 m6
L 22
21
1
2
v
Y g
)g Y - g (
Y y
y -
V
V
A
+
=
+
= =

12
Case1: 0 C or 0, Y
c 3
= =
2 1
2 2 2
1 1 1
Y Y
sC G Y
sC G Y
=
+ =
+ =

Solving for the voltage gain,

) C sR 1 ( ) C sR 1 ( G G
g g
) sC G ( ) sC G (
g g
Y Y
g g
Y g
)g Y - g (
Y y
y
V
V
A
2 2 1 1 2 1
m6 m2
2 2 1 1
m6 m2
2 1
m6 m2
3 m6
m2 3 m6
L 22
21
1
2
v
+ +
=
+ +
= =
+
=
+
= =

)
p
s
- (1 )
p
s
- (1
A
s) C R + s)(1 C R + (1
R R g g
A
2 1
V0
2 2 1 1
2 1 m2 m1
v
= =

where:

2 1 m2 m1 V0
R R g g A =

1 1
1
C R
1
p

=

2 2
2
C R
1
p

=

Case2:
C 3 3
sC sC Y = =

3 2 3 2 2 1 C
2
C 3 1 2 3 2 1 2 1
3 2 2 3 1 1 2 2 1 1 3 2 3 1 2 1
C C C C C C where
s )]s C (C G ) C (C [G G G
) sC ( ) sC G ( ) sC ( ) sC G ( ) sC G ( ) sC G ( Y Y Y Y Y Y
+ + =
+ + + + + =
+ + + + + + = + + =

Solving for the voltage gain,

C 2 1
2
3 2 1 m6 1 3 1 2 3 2
m6
3
2 1 m6 m2
3 m6
2
C 3 1 2 3 2 1 2 1
m2 3 m6
3 m6
m2 3 m6
v
R R s ] C R R g )R C (C )R C s[(C 1
)
g
C
s - 1 ( R R g g

C sg s )]s C (C G ) C (C [G G G
)g sC - g (
Y g
)g Y - g (
A
+ + + + + +
=
+ + + + + +
=
+
=

Compare the denominator with,

2 1
2
1 2 1
2
2 1 2 1
p p
1
s
p
1
s 1
p p
1
s )
p
1
p
1
s( 1 )
p
s
- (1 )
p
s
- (1 = D(s) + + + =

13

C 2 1 m6 C 2 1 m6 1 C 1 2 C 2
1
C R R g
1
C R R g R ) C (C R ) C (C
1
p

+ + + +

L 2 1 C 1 2
L
m6
2
m6
C 1 C 2 2 1
C m6
2
C C C C C C ;
C
g
C
g
C C C C C C
C g -
p >> >>
=
+ +

C
m6
1
C
g
z =

A
V0
-20db/dec
-40db/dec
-20db/dec
w
p
1
p
2
z
w
GB
Figure 9. Bode Plot of Second Order System with RHP zero

For good stability a phase margin of at least 60 is desirable This can be achieved as follows:

GB
V0 1 V0 GB
w 10 z
A ; p A w
=
Then
14

m2
C
L
m6
GB 2
g
C
C
2 . 2 g
or
w 2 . 2 p
=
=

This is shown below:

That is, the transfer function has two poles and one RHP zero. The RHP zero contributes a negative phase
angle.

)
p
1 )(
p
1 (
)
z
1 ( A
) ( A
2 1
V0
V
s s
s
s
+ +
=
The phase angle at the unity gain radian frequency (w
GB
) is
) p / w ( tan ) p / w ( tan ) / w ( tan ) w ( A
2 GB
1
1 GB
1
GB
1
GB V

= z

The phase margin PM is given by:
m2
C
L
m6
C
m2
L
m6
GB 2
2 GB
1
2 GB
1
2 GB
1
V0
1 1 -
2 GB
1
1 GB
1
GB
1
GB V
g
C
C
2.2 g
C
g
2 . 2
C
g
2.2w p
3 . 24 ) p / w ( tan
)] p / w ( tan 90 7 . 5 [ 180 )] p / w ( tan ) A ( tan ) 1 . 0 ( [-tan 180 60
)] p / w ( tan ) p / w ( tan ) / w ( tan [ 180 ) w ( A 180 PM
=
=
=
=
+ + =
= + = + =

o
o o o
z
To achieve the assumption z=10w
GB
, the compensation capacitance Cc must be selected properly.
L C
m2
C
L
m6
C
m2
L
m6
GB 2
m2 m6
C
m2
C
m6
GB
0.22C C
Combining
g
C
C
2 . 2 g
C
g
2 . 2
C
g
; 2.2w p
10g g
C
g
10
C
g
; 10w z
> > >

= = =

In addition,
L C
C
m6
L
m6
2
C C
C
g
C
g
z p < < < . Hence,
L C L
C C 0.22C < <

Case 3:
3 3
3 3
3
C C 3 3 3
3 3
sC G
C sG
Y ;
sC
1
G
1
sC
1
G
1
sC
1
R Z
+
= + = + = + =
15

3 2 3 1 2 1 C
3 2 3 1 2 1 G
3 3
3
3 2 1
2
3 2 1 3 1 2 C 1 3 2 2 3 1 3 G 3 2 1
3 3
3 3
2 2
3 3
3 3
1 1 2 2 1 1
3 2 3 1 2 1
C C C C C C
G G G G G G
: where
sC G
s C C C )s C C G C C G (G )s C G G C G G C ( G G G

sC G
C sG
) sC (G
sC G
C sG
) sC (G ) sC )(G sC (G
Y Y Y Y Y Y
+ + =
+ + =
+
+ + + + + + +
=
|
|
.
|
\
|
+
+ +
|
|
.
|
\
|
+
+ + + + =
+ + =

{ }
3 2 1 3 2 1
3 2 3 2 3 1 3 1 C 2 1
3 3 3 2 1 m6 1 3 1 2 3 2
3 2
m6
3
3 3 3 m6 m1
V
3 2 1 3 2 1
3 2 3 2 3 1 3 1 C 2 1
3 2 1 m6 1 1 2 2 3 3 2 1
3 2
3 2 1
3 m6
3 3 3 m6
3 m6 m1
3
3 2 1
2
3 2 1 3 1 2 C 3 3 m6 1 3 2 2 3 1 3 G 3 2 1
m1 3 3 3 m6 3 m6
3 3
3 3
m6
m1
3 3
3 3
m6
3 m6
m1 3 m6
V
C C C R R R a'
C C R R C C R R R R b'
C R C R R g )R C (C )R C [(C c'
: where
s a' s b' s c' 1
s
g
C
- C R 1 R g g
A
C C C R R R a
] C C R R C C R R R [R b
] C R R g C R C R )C R R R [( c
: where
as bs cs 1 G G G
s
G g
C G - C g
1 G g g

s C C C )s C C G C C G (G )s C G g C G G C G G C ( G G G
)s]g C G - C (g G [g

sC G
C sG
g
)g
sC G
C sG
- g (
Y g
)g Y - g (
A
=
+ + =
+ + + + + =
+ + +
(
|
|
.
|
\
|
+
=
=
+ + =
+ + + + + =
+ + +
(
+
=
+ + + + + + + +
+
=
+
+
+
=
+
=

2.0Opamp Design Specification
16

M10
w=300u
l=6.6u
M1
w=36.6u
l=6.6u
M2
w=36.6u
l=6.6u
V- V+
M5
w=30u
l=6.6u
M7
w=90u
l=6.6u
Cc
M3
w=5.4u
l-6.6u
M4
w=5.4u
l-6.6u
M6
w=32.4u
l=6.6u
M9
w=300u
l=6.6u
M8
w=873.6u
l=6.6u
Vo
(10)
(9) (6)
(7)
(1) (2)
(8)
(5)
(3) V
DD
(4) V
SS
IB=100uA

Figure 10

Vdd =+5V, Vss=-5V, Ao>=15,000, GB=2(5MHz), SR = 10V/uS, Ro 1.46k
-4.5 <=CMR<=3, PM>60

SPICE Parameters: Kn=40uA/V2 , Kp=15uA/V2, =0.02

(1) Determine I
D5
from the SR specification.
Let Cc=1pF

C
SD5
C
I
= SR

uA 5
2
uA 10
2
I
I I
333 . 5
6)(0.5) - E 15 (
6) - E 10 ( 2
V K
I 2
L
W
0.5 | -1 | 3.5- - 5 | V | - V - V | V | - V V
10uA 12) - 6)(1E - (10E ) SR)(C ( I
SD5
SD2 SD1
2 2
SD5(SAT) P
SD5
5
TP0 bias DD TP0 SG5 SD5(SAT)
C SD5
= = = =
= = =
|
.
|
\
|
= = = =
= = =

(2) Determine (W/L)
1
from the w
GB
and positive CMR specifications
17
From w
GB
specification,

31.4umho 5E6) 12)(2 - E 1 ( w C g
I W/L) ( K 2
C
1
C
g
= w
GB C m1
SD1 1 P
C C
m1
GB
= = =
=

57 . 6
6) - 6)(5E - 2(15E
6] - 31.4E [
I K 2
) g (
L
W
2
SD1 P
2
m1
1
= = =
|
.
|
\
|

From the positive CMR specification,

G1(max) SD5(SAT) DD SG1
SG1 SD5(SAT) DD G1(max)
V - V - V V
V - V V V
=
=

From the gate bias, V
bias
, V
SD5
can be determined.

666 . 2
6)(0.5) - E 15 (
6) - E 5 ( 2
V K
I 2
L
W
0.5 | -1 | 1.5- | V | - V V
5 . 1 3 5 . 0 5 V - V - V V
2 2
SD1(SAT) p
SD1
1
TP0 SG1 SD1(SAT)
G1(max) SD5(SAT) DD SG1
= = =
|
.
|
\
|
= = =
= = =

To satisfy both specifications select the higher (W/L) ratio. For matching and symmetry, we also choose
(W/L)
2
= (W/L)
1
=6.57

(3) Determine (W/L)
3
=(W/L)
4
ratio from negative CMR

4
2 2
SS G1(min) N
DS3
3
L
W
1
(-5)) - 6)(-4.5 - (40E
6) - E 5 ( 2
) V - V ( K
I 2
L
W
|
.
|
\
|
= = = =
|
.
|
\
|

(4) Determine (W/L)6 from the PM>60 specification.

) p / w ( tan - z) / w ( tan - 90 PM
2 GB
-1
GB
-1
=

2 1 C 2
2 1
m6
2
C
m6
C
m2
GB
C C C since ; p z ;
C C
g
p ;
C
g
z ;
C
g
w + > <
+
= = =
A pessimistic estimate of PM is obtained by assuming
2
p z = . That is,

18
|
.
|
\
|
>
|
.
|
\
|
<
<
|
|
.
|
\
|
|
|
.
|
\
|
=
|
|
.
|
\
|
<
2
PM 90
tan
g
g
2
PM 90
tan
g
g
2
PM 90
g
g
tan
g
g
tan 2 90
/C g
/C g
2tan - 90 PM
m2
m6
m6
m2
m6
m2 1 -
m6
m2 1 -
C m6
C m2 1 -

To achieve PM>60,

6 - 120E 6 - E 122 . 117
60)/2) - tan((90
6 E 4 . 31
g
m6
=
>

From step 4 V
DS6(SAT)
=V
DS3(SAT)
=0.5V

6
6)(0.5) - E 40 (
6 - E 120
V K
g
L
W
DS6(SAT) N
m6
6
= = =
|
.
|
\
|

The current through M6 is given by

uA 30
6)(6) - E 40 ( 2
6) - E 120 (
W/L) ( 2K
g
I
2
6 N
2
m6
DS6
= = =

For balance condition the current through M6 must be properly ratioed with the current through M3,

30uA uA) 5 (
1
6
I
(W/L)
W/L) (
I
DS3
3
6
DS6
= = =

(5) Determine (W/L)
7
from the balance condition and that I
SD7
=I
DS6

16 999 . 15 ) 333 . 5 (
uA 10
uA 30
W/L) (
I
I
(W/L)
5
SD5
SD7
7
= = =

(6) DC gain A
VO
is computed and compared with the specification:

000 , 15 700 , 15
6) - .02)(30E 6)(.02 - E 5 )( 02 . 02 (.
6) - 6)(120E - (31.4E

I ) ( I ) (
g g
) g g )( g (g
g g
R R g g A
DS6 7 6 SD2 4 2
m6 m2
ds6 ds5 ds4 ds2
m6 m2
2 1 m6 m2 V0
=
+ +
=
+ +
=
+ +
= =

19

(7) From the output resistance specification Ro 1.46k, (W/L)
8
can be determined. The output resistance
is given by:

SD8 8 P SD8 8 m8
O
I (W/L) K 2
1
I 2
1
g
1
R = = =

Solving for (W/L)
8
, assuming I
SD8
= 100uA and Pspice parameter K
P
=15 uA/V
2

156
6) - E 100 ( 3) + 6)(1.46E - E 15 ( 2
1
I R K 2
1
(W/L)
2
SD8
2
O P
8
= = =
(8) Determine the (W/L) of the current mirrors. First set up the current source M10 to 100uA using the
biasing current source IB. The V
GS8
is set up to guarantee it operates at saturation by adding -0.5v beyond
its threshold voltage of V
tp
=-1v . That is V
SG10
= 1.5v. (W/L)
10
can now be determined as follows:

33 . 53
(-1)) - 6)(1.5 - (15E
6) - E 100 ( 2
|) V | V ( K
I 2
W/L) (
2 2
tp SG10 P
SD10
10
= =
=

The rest of current sources are determined by proportionality as follows:

I
SD9
= 100uA = > (W/L)
9
= (W/L)
10
(I
SD9
/I
SD10
) = (53.33)(100uA/100uA)=53.33

This complete the design. The results is summarized in the following table:

PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
I(Ua) 5 5 5 5 10 30 30 100 100 100
T P P N N P N P P P P
W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33
W(u) 36.792 36.792 5.6 5.6 29.865 33.6 89.6 873.6 298.65 298.65
L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6
Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6

Finding the W, L to the nearest multiple of =0.6 length.

PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
I(Ua) 5 5 5 5 10 30 30 100 100 100
W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33
W(u) 36.6 36.6 5.4 5.4* 30* 32.4* 90* 873.6 300 300
L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6
Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6

20
* Adjusted to satisfy the balance condition to minimize the input offset voltage, Vos:

6 6
30
90
2
4 . 5
4 . 32
(W/L)
W/L) (
2
(W/L)
W/L) (
5
7
4
6
=
=
=

3.0 Opamp Simulation

3.1. DC Offset Voltage and Differential Gain Determination

* Filename="opamp11.cir"
* MOS Diff Amp with PMOS Input and Current Mirror Load

* Input Signals
VID 11 0 DC 0V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

* Netlist for OpAmp Offset Measurement
M1 7 1 5 5 PMOS1 W=36.6U L=6.6U
M2 6 2 5 5 PMOS1 W=36.6U L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6 4 4 NMOS1 W=32.4U L=6.6U
M7 9 8 3 3 PMOS1 W=90U L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
Cc 9 6 1pF

*Bias current
IB 8 4 100UA

* SPICE Parameters
21
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U

*Analysis
.OP
.DC VID -300uV 300uV .1uV
.TF V(10) VID
.PROBE
.END

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

( 1) 0.0000 ( 2) 0.0000 ( 3) 5.0000 ( 4) -
5.0000

( 5) 1.3115 ( 6) -3.4878 ( 7) -3.4878 ( 8)
3.5084

( 9) -1.1378 ( 10) .1495 ( 11) 0.0000 ( 12)
0.0000

The output voltage Vo=V(10) is 0.145V at quiescent operating point. This
non-zero output voltage can be corrected or reduced by applying an input
offset voltage, Vos. This offset is determined by finding the value of VID that makes the output
22
voltage Vo=V(10)=0. From the above graph, this is equal to 8.2484uV. The resulting output
voltage from simulation is 2.753E-6V, as shown below:

Modify the VID line in the netlist as follow:

VID 11 0 DC 8.2484uV


( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -
5.0000

( 5) 1.3115 ( 6) -3.4864 ( 7) -3.4878 ( 8)
3.5084

( 9) -1.2881 ( 10)-2.753E-06 ( 11)-8.248E-06 ( 12)
0.0000

The differential gain can be obtained from the DC transfer
characteristic by locating two points centered about the bias point of
Vid=Vos=-8.2484uV. For accuracy, the two points must be far apart. From
the graph:

4 E 833 . 1
6) - (-169.4E - 6) - E 5 . 225 (
) 8356 . 2 ( 4048 . 4
A
vd
+ =

=

This is very closed to the value obtained using TF analysis of 1.810E+4,
as shown below:

**** SMALL-SIGNAL CHARACTERISTICS

V(10)/VID = 1.810E+04

INPUT RESISTANCE AT VID = 1.000E+20

OUTPUT RESISTANCE AT V(10) = 1.342E+03

3.2. Common-mode Voltage Range Determination


* Input Signals
VID 11 0 DC 8.2484uV
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

* Netlist for Measuring Input CMR
M1 7 1 5 5 PMOS1 W=36.6U L=6.6U
M2 6 2 5 5 PMOS1 W=36.6U L=6.6U
23
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6 4 4 NMOS1 W=32.4U L=6.6U
M7 9 8 3 3 PMOS1 W=90U L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
Cc 9 6 1pF

* Bias current
IB 8 4 100UA

* SPICE Parameter

* Analysis
.DC VIC -5V 5V .05V
.TF V(10) VIC
.PROBE
.END

24
The common-mode input range is determined when the output cease to follow the input linearly. At the
low end, it determines V
G1
(min)=-4.4255, and at the high end, it determines V
G1
(max)=3.1383. These are
very closed to the corresponding design specifications of V
G1
(min=-4.5 and V
G1
(max)=3.
The common-mode gain is obtained by locating two points as far apart in the linear range about the
operating point. This is shown in the graph above, and computed as follows:

49373 . 0
) 3192 . 4 ( 1915 . 3
) 0677 . 2 ( 6406 . 1
A
cm
=

=

This is very closed to the value obtained using the TF analysis of 0.4984, as shown below:


V(10)/VIC = 4.984E-01

INPUT RESISTANCE AT VIC = 1.000E+20


The common mode reject ration CMRR is calculated as follows:

5 . 37125
49373 . 0
4 E 833 . 1
A
A
CMRR
cm
vd
=
+
= =

3.3. Opamp Frequency Response


* Input Signals
VID 11 0 DC 8.2484uV AC 1V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

* Netlist for Frequency Response Measurement
M1 7 1 5 5 PMOS1 W=36.6U L=6.6U
M2 6 2 5 5 PMOS1 W=36.6U L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6 4 4 NMOS1 W=32.4U L=6.6U
M7 9 8 3 3 PMOS1 W=90U L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
25
Cc 9 6 1pF
CL 10 0 2pF

*Bias current
IB 8 4 100UA

* SPICE Parameters

* Analysis
.AC DEC 10 0.1HZ 10000MegHz
.TF V(10) VID
.PROBE
.END

Pspice simulation results:

M 16 . 5 f ; 63 PM ; 4 E 810 . 1 A
GB VO
= = + =
o


V(10)/VID = 1.810E+04

26


The theoretical bandwidth and gain bandwidth are calculated as follows:

M 3 . 22
2
E6 140
2
z
f
E6 140
12) - E 1 (
6) - E 140 (
C
g
z
M 5 ) 318 )( 15700 ( f A f
Hz 318
2
2000
2
p
f
2000
12) - 14E6)(1E 6)(5E6)(.7 - E 140 (
1
C R R g
1 -
p
M 714 .
6) - E 35 )( 02 . 02 (.
1
I ) (
1
R
M 5
6) - E 5 )( 02 . 02 (.
1
I ) (
1
R
umho 140 g
umho 4 . 31 g
z
C
m6
1 V0 GB
1
1
C 2 1 m2
1
6 7 6
2
2 4 2
1
m6
m2
= = =
= = =
= = =
= = =
=
=
=
+
=
+
=
=
+
=
+
=
=
=

Simulation results are : f
1
=258Hz, f
GB
=5.16M, f
z
and f
2
are difficult to obtain accurately from bode plot.

3.4. Slew Rate Measurement


* Input Signal
VIN 2 0 PWL(0,-5V 10us,-5V 10.01us,5V 30us, 5V 30.01us,-5V 1s, -5V)

*Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

* Netlist for Slew Rate Measurement
M1 7 1 5 5 PMOS1 W=36.6U L=6.6U
M2 6 2 5 5 PMOS1 W=36.6U L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6 4 4 NMOS1 W=32.4U L=6.6U
M7 9 8 3 3 PMOS1 W=90U L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
Cc 9 6 1pF

* Bias current
IB 8 4 100UA
27

* External Component for Slew Rate Measurement
VSH 1 10 DC 0V

* SPICE Parameters

*Analysis
.TRAN .1ns 40us
.PROBE
.END

The positive slew rate is the slope of the rising edge of the output. This is computed from the two points on
the rising edge. That is,

V/us 96 . 7
085 . 10 931 . 10
) 2985 . 3 ( 4386 . 3
SR =

=
+

Similarly, the new slew rate is computed as follows:

28

V/us 55 . 10
014 . 30 619 . 30
6491 . 3 7368 . 2
SR
-
=

=

4.0 Op Amp Design Specification

Vdd =+5V, Vss=-5V, Ao>=30,000, GB=2(5MHz), SR = 10V/uS, Ro 1.46k
-4.5 <=CMR<=3

SPICE Parameters: Kn=40uA/V2 , Kp=15uA/V2, =0.02

Increasing Overall DC Gain

DC gain A
VO
is computed and compared with the specification:

000 , 30 700 , 15
6) - .02)(30E (.02
6) - (120E
6) - E 5 )( 02 . 02 (.
6) - (31.4E

I ) (
g
I ) (
g

) g g (
g
) g (g
g
] R ][g R g [ A A A
DS6 7 6
m6
SD2 4 2
m2
ds6 ds5
m6
ds4 ds2
m2
2 m6 1 m2 V2 V1 V0
=
(
+
(
+
=
(
+
(
+
=
(
+
(
+
= = =


M 16 . 5 f ; 63 PM ; 4 E 810 . 1 A
GB VO
= = + =
o

Increasing Overall Gain By Increasing A
V1

SD2
2
4 2
P
SD2 4 2
SD2 2 P
SD2 4 2
m2
V1
I
(W/L)
) (
2K
I ) (
I (W/L) 2K
I ) (
g
A
+
=
+
=
+
=

The current I is half the bias current and is independent of ( . That is, the gain can be
adjusted by simply adjusting while remains constant. The gain is proportional to
SD2 SD5
I
I
2
W/L)
2
W/L) (
SD2 V1
A
2
(W/L) . For example to increase the overall gain by 2, one needs to increase (W/L) by a
factor of 4.
2 1
(W/L) ,

PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
I(Ua) 5 5 5 5 10 30 30 100 100 100
29
W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33
W(u) 4*36.6 4*36.6 5.4 5.4 30 32.4 90 873.6 300 300
L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6
Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6

Increasing Av1

* Increasing Overall Gain By Increasing W/L of M1 & M2
* Input Signals
VID 11 0 DC 8.2484uV AC 1V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
M2 6 2 5 5 PMOS1 W={4*36.6U} L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6 4 4 NMOS1 W={32.4U} L=6.6U
M7 9 8 3 3 PMOS1 W={90U} L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
Cc 9 6 1pF

*Bias current
IB 8 4 100UA

* SPICE Parameters

* Analysis
30
.TF V(10) VID
.PROBE
.END

Before increasing (W/L) of M1 and M2


V(10)/VID = 1.810E+04



After Increasing (W/L) of M1 and M2 by 4


V(10)/VID = 3.590E+04



Although the DC gain increases the PM decreases.
31
AV0=3.590E+4; PM=29; f
GB
=10.596M

The Overall Gain Is Independent of
V2
A

The second stage gain can not be used to increase the overall gain but is used to adjust the phase margin as
shown below:

DS6
6
7 6
N
DS6 7 6
DS6 6 N
DS6 7 6
m6
V2
I
W/L) (
) (
K 2
I ) (
I W/L) ( K 2
I ) (
g
A
+
=
+
=
+
=

Since is determined by current mirror, increasing ( increases I proportionately as shown
below:
DS6
I
6
W/L)
DS6

constant
I
W/L) (
I
(W/L)
I
(W/L)
W/L) (
I
DS4
4
DS6
6
DS4
4
6
DS6
= = =
That is, increasing or does not increase the overall gain, but g is increased by
DS6
I
6
W/L) (
m6
DS6 6
I W/L) (
DS6
I
. That is, g is doubled by increasing ( by a factor of 2, and by current mirror
is also increase by a factor of 2. Similarly, ( must be doubled, since I = . The phase
margin, which deteriorates when increasing (W/L) or g , can be compensated by increasing .
m6 6
W/L)
m2
7
W/L)
2
DS6 DS7
I
m6
g

PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
I(Ua) 5 5 5 5 10 2*30 2*30 100 100 100
W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33
W(u) 4*36.6 4*36.6 5.4 5.4 30 2*32.4 2*90 873.6 300 300
L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6
Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6


M 7 . 9 f ; 51.3 PM ; 4 E 590 . 3 A
GB VO
= = + =
o


V(10)/VID = 3.590E+04



32

The phase margin can be increased further by increasing both ( and . The desired phase
margin of 65 is approached when and ( are increased by a factor of 4
6
W/L)
7
W/L) (
6
W/L) (
7
W/L)

PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
I(Ua) 5 5 5 5 10 4*30 4*30 100 100 100
W/L 6.57 6.57 1 1 5.333 6 16 156 53.33 53.33
W(u) 4*36.6 4*36.6 5.4 5.4 30 4*32.4 4*90 873.6 300 300
L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6
Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6

The Overall Gain Is Independent of But Adjust Phase Margin
V2
A

* Increasing Overall Gain By Increasing W/L of M1 & M2
* Input Signals
VID 11 0 DC 8.2484uV AC 1V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

33
M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
M2 6 2 5 5 PMOS1 W={4*36.6U} L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6 4 4 NMOS1 W={4*32.4U} L=6.6U
M7 9 8 3 3 PMOS1 W={4*90U} L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
Cc 9 6 1pF

*Bias current
IB 8 4 100UA

* SPICE Parameters

* Analysis
.TF V(10) VID
.PROBE
.END


M 17 . 9 f ; 61.5 PM ; 4 E 590 . 3 A
GB VO
= = + =
o


V(10)/VID = 3.590E+04


34

5.0 Phase Margin Correction By Moving the Zero from RHP to
LHP

The location of zero is given by:

) R
g
1
( C
1
) R
g
1
( C
1
z
C
m6
C 3
m6
3

=
=

The zero can be moved from the RHP to the LHP by selecting
m6
C
g
1
R >> , with this choice the zero
is approximately given by:
C C
C R
1 -
z

A zero in the LHP increase the phase margin rather decrease as in the case of RHP zero. The transfer
function of an op amp compensated by resistor R and capacitor connected in series is given by:
C C
C

35
|
|
.
|
\
|
|
|
.
|
\
|
|
|
.
|
\
|
|
.
|
\
|
=
3 2 1
V0
V
p
s
1
p
s
1
p
s
1
z
s
- 1 A
s) ( A

where:

C C
1 C
3
2 1
m6
2
C 2 1 m6
1
C R
1
z
C R
1
p
C C
g
p
C R R g
1
p

3 2 1
2 1
V0
V
p p p since ;
p
s
1
p
s
1
z
s
- 1 A
s) ( A << <<
|
|
.
|
\
|
|
|
.
|
\
|
|
.
|
\
|

|
|
.
|
\
|
|
|
.
|
\
|
|
.
|
\
|
+ = + =
|
|
.
|
\
|
|
|
.
|
\
|
|
.
|
\
|
=
2
GB 1 -
1
GB 1 - GB 1 - o
GB V
o
2
GB 1 -
1
GB 1 - GB 1 -
GB V
p
w
tan
p
w
tan
z
w
tan 180 ) w ( A 180 PM
p
w
tan
p
w
tan
z
w
tan ) w ( A

With extra phase margin introduced by the LHP zero, the phase margin can be increased without
increasing the sizes of M6 and M7. To make sure that the op amp behaves as single order system within the
gain bandwidth, . One positions the zero 20% (
GB
w
GB
1.2w z = ) over the gain bandwidth. In the
previous example, the non-dominant pole was position at p . Where w is the
original gain bandwidth prior to doubling g which double the gain bandwidth. The new phase margin
gain be calculated as follows:
'
GB GB
w 2 . 2 =
2
1.1w =
'
GB
m2

( ) ( ) ( ) 53 . 87 909 . 0 tan A tan 833 . tan 180
1.1w
w
tan
p
p A
tan
1.2w
w
tan 180
p
w
tan
p
w
tan
z
w
tan 180 ) w ( A 180 PM
1 -
V0
1 - 1 - o
GB
GB 1 -
1
1 V0 1 -
GB
GB 1 - o
2
GB 1 -
1
GB 1 - GB 1 - o
GB V
o
+
|
|
.
|
\
|
|
|
.
|
\
|
|
|
.
|
\
|
+ =
|
|
.
|
\
|
|
|
.
|
\
|
|
.
|
\
|
+ = + =

36

The value of to place the zero is calculated as follows:
C
R

k 25 . 13
6) - x31.4E 2 ( 2 . 1
1
g 2 . 1
1
R
C
g
2 . 1 w 2 . 1
C R
1
z
m2
C
C
m2
GB
C C
= = =
= = =

PAR M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
I(Ua) 5 5 5 5 10 35 35 100 100 100
W/L 6.57 6.57 1 1 5.333 7 18.665 156 53.33 53.33
W(u) 4*36.6 4*36.6 5.4 5.4 30 37.8 105 873.6 300 300
L(u) 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6 6.6
Leff(u) 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6

pF 1 C k, 25 . 13 R
C C
= =

M10
w=300u
l=6.6u
M1
w=4*36.6u
l=6.6u
M2
w=4*36.6u
l=6.6u
V- V+
M5
w=30u
l=6.6u
M7
w=90u
l=6.6u
Cc
M3
w=5.4u
l-6.6u
M4
w=5.4u
l-6.6u
M6
w=32.4u
l=6.6u
M9
w=300u
l=6.6u
M8
w=873.6u
l=6.6u
Vo
(10)
(9)
(7)
(1) (2)
(8)
(5)
(3) V
DD
(4) V
SS
Rc
(6b) (6a)
IB=100uA

Fig 10a

* Filename="opamp33z.cir"

* Input Signals
37
VID 11 0 DC -8.2484uV AC 1V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U
M7 9 8 3 3 PMOS1 W={90U} L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
Cc 9 6b 1pF
Rc 6a 6b {13.25k}

*Bias current
IB 8 4 100UA

* SPICE Parameters

* Analysis
.TF V(10) VID
.PROBE
.END


M 294 . 10 f ; 85.5 PM ; 4 E 590 . 3 A
GB VO
= = + =
o


V(10)/VID = 3.590E+04

38



( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000

( 5) 1.1562 ( 7) -3.4870 ( 8) 3.5084 ( 9) -1.5153

( 10) -.2260 ( 11)-8.248E-06 ( 12) 0.0000 ( 6a) -3.4842

( 6b) -3.4842

6.0 Implementation of Rc with NMOS Transistor

Transistor M11 has VDS11=0 since no dc bias current flows through its because of capacitor Cc.
Therefore, it is operating at the ohmic or triode region. That is,

DS DS TN GS N D
/2]V V - V - (W/L)[V K I =

The resistance value implemented by this transistor is givcen by

39

| |
| | 65 . 1 ) 6 . 0 ( 2 ) 5 ( 4836 . 3 ( ) 6 . 0 ( 2 1 1
2 V 2 V V
F SB TO TN
= + + =
+ + =

u
u
27
6
276 . 0
1.65) - (-3.4842) - 3)(5 6(13.25E - E 40
1
) V (V R K
1
W/L) (
) V (W/L)(V K
1
V
I
r R
TN GS C N
TN GS N
1
DS
D
DS10 C
= =
+
=
=
|
|
.
|
\
|
= =

M10
V
DD
V
SS
M1 M2
M3 M4
M5 M7
M6
M9
M8
C
c
M11
V
DD
(6a)
(6b)
(8)
(1) (2)
V-
V+
(5)
(7)
(4)
(3)
(9)
(10)
IB

* Filename="opamp33m.cir"
* Input Signals
VID 11 0 DC -8.2484uV AC 1V
E- 1 12 11 0 -0.5
40
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U
M7 9 8 3 3 PMOS1 W={90U} L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
M11 6b 3 6a 4 NMOS1 W=6U L=27U
Cc 9 6b 1pF
*Rc 6a 6b {13.25k}

*Bias current
IB 8 4 100UA

* SPICE Parameters

* Analysis
.PROBE
.TF V(10) VID
.END


M 9 . 11 f ; 87.7 PM ; 4 E 590 . 3 A
GB VO
= = + =
o


V(10)/VID = 3.590E+04


41


( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000

( 5) 1.1562 ( 7) -3.4870 ( 8) 3.5084 ( 9) -1.5137

( 10) -.2244 ( 11)-8.248E-06 ( 12) 0.0000 ( 6a) -3.4843

( 6b) -3.4843

42
7.0 Opamp with ClassAB Output Buffer
M10
V
DD
V
SS
M1 M2
M3 M4
M5
M7
M6
M9
M8
C
c
M11
V
DD
(6a)
(6b)
(8)
(1) (2)
V-
V+
(5)
(7)
(4)
(3)
(9)
(10)
M12
M13
(13)
(14)
k*(W/L)p
(W/L)n
(W/L)n
(W/L)p
k*(W/L)n
I
k*I
(W/L)p
IB

Figure 12b

k=3

* Filename="op33zab2.cir"
* Input Signals
VID 11 0 DC -8.2484uV AC 1V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
43
M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U
M7 14 8 3 3 PMOS1 W={90U} L=6.6U
M8 4 9 10 10 PMOS1 W={3*90U} L=6.6U
M9 3 14 10 4 NMOS1 W={3*32.4U} L=6.6U
M10 8 8 3 3 PMOS1 W=300U L=6.6U
M11 6b 3 6a 4 NMOS1 W=6U L=27U
M12 9 9 13 13 PMOS1 W=90U L=6.6U
M13 14 14 13 4 NMOS1 W=32.4U L=6.6U
Cc 9 6b 1pF

*Bias current
IB 8 4 100UA

* SPICE Parameters

* Analysis
.PROBE
.DC VID -5V 5V .1V
.TF V(10) VID
.END


3 E 113 . 1 R ; M 9 . 10 f ; 86.1 PM ; 4 E 065 . 3 A
O GB V0
+ = = = + =


V(10)/VID = 3.065E+04




( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000

( 5) 1.1562 ( 7) -3.4870 ( 8) 3.5084 ( 9) -3.5234

( 10) -2.0125 ( 11)-8.248E-06 ( 12) 0.0000 ( 13) -2.0182
44

( 14) .6098 ( 6a) -3.4843 ( 6b) -3.4843

45
8.0 Process and Temperature Independent Opamp Design Using Widlar
Current Source

V
DD
V
SS
(8)
(3)
Rb
MB1
MB2
(W/L)p
MB3
MB4
(W/L)n
4(W/L)n
(W/L)p
(15)
(16)
I I
I
Msnk1
(W/L)n
Msrc1
(W/L)p
(4)
(5)
+
Vsnk
Msnk2
2(W/L)n
I 2I
Msnk3
3(W/L)n
3I
+
Vsrc
2I
3I
Msrc2
2(W/L)p
Msrc3
3(W/L)p
(2)

Figure 12

I I I
D4 D3
= =

b GS4 GS3
IR V V + =

Subtracting the threshold voltage (neglecting body effect) from both sides, one obtains:
TN0
V

b
4 N 3 N
b TN0 GS3 TN0 GS3
IR
W/L) ( K
I 2
W/L) ( K
I 2
IR V - V V - V
+ =
+ =

46
Solve for Rb,

b
4
3
3 N
R
(W/L)
(W/L)
1
I (W/L) K 2
2
=
(
(

or

3 4
b
m3
b
4
3
m3
4(W/L) (W/L) If ;
R
1
g
R
(W/L)
(W/L)
1 2
g
= =
(
(
=

Thus is determined by geometric ratio only. It is independent of power supply voltage, process
parameter, and temperature. This is only true to the first order of approximation, since the body effect is
neglected. In addition all other transconductance are also stabilized since all transistor currents are derived
from the same biasing network. That is,
m3
g

r transisto channel - p for ; g
I (W/L) K
I (W/L) K
g
r transisto channel - n for ; g
I (W/L)
I (W/L)
g
m3
D3 3 N
Di i P
mi
m3
D3 3
Di i
mi
=
=

Design a 10uA widlar current source with the minimum transistor sizes for biasing an opamp circuit.
Assuming all transistors are of the same length L=6.6u. The minimum width corresponding to (W/L)=1
and 6 . 0 = is obtained as follows:

5.4u W
1
2(0.5) - 6.6u
W
2LD - L
W
L
W
eff
= = =

The minimum W for the widlar current source is 2(5.4u)=10.8u, since the differential amplifier input stage
load current is half of the widlar design current value. The minimum pmos transistor (W/L) is calculated to
achieve the same transconductance. That is,

30u 28.8u u) 8 . 10 (
15u
u 40
W
K
K
W
L
W
K
K
L
W
N
P
N
P
N
eff P
N
P
eff
= = =
|
|
.
|
\
|
=
|
|
.
|
\
|

The widlar cu
* Widlar Source = Supply Independent
47
* Input Signals

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

VSNK 5 0 DC 0VOLT
VSRC 2 0 DC 0VOLT


MB1 15 8 3 3 PMOS1 W=30U L=6.6U
MB2 8 8 3 3 PMOS1 W=30U L=6.6U
MB3 15 15 4 4 NMOS1 W={10.8U} L=6.6U
MB4 8 15 16 4 NMOS1 W={4*10.8U} L=6.6U
Msrc1 2 8 3 3 PMOS1 W=30U L=6.6U
Msrc2 2 8 3 3 PMOS1 W={2*30U} L=6.6U
Msrc3 2 8 3 3 PMOS1 W={3*30U} L=6.6U
Msnk1 5 15 4 4 NMOS1 W=10.8U L=6.6U
Msnk2 5 15 4 4 NMOS1 W={2*10.8U} L=6.6U
Msnk3 5 15 4 4 NMOS1 W={3*10.8U} L=6.6U
Rb 16 4 20K

* SPICE Parameters

* Analysis
.PROBE
.OP
.DC VSNK -5V 5V .1V
*.DC VSRC -5V 5V .1V
.END
48

49

NAME MB1 MB2 MB3 MB4 Msrc1
MODEL PMOS1 PMOS1 NMOS1 NMOS1 PMOS1
ID -9.89E-06 -8.70E-06 9.89E-06 8.70E-06 -9.30E-06
VGS -1.46E+00 -1.46E+00 1.50E+00 1.33E+00 -1.46E+00
VDS -8.50E+00 -1.46E+00 1.50E+00 8.37E+00 -5.00E+00
VBS 0.00E+00 0.00E+00 0.00E+00 -1.74E-01 0.00E+00
VTH -1.00E+00 -1.00E+00 1.00E+00 1.11E+00 -1.00E+00
VDSAT -4.59E-01 -4.59E-01 4.99E-01 2.20E-01 -4.59E-01

NAME Msrc2 Msrc3 Msnk1 Msnk2 Msnk3
MODEL PMOS1 PMOS1 NMOS1 NMOS1 NMOS1
ID -1.86E-05 -2.79E-05 1.06E-05 2.11E-05 3.17E-05
VGS -1.46E+00 -1.46E+00 1.50E+00 1.50E+00 1.50E+00
VDS -5.00E+00 -5.00E+00 5.00E+00 5.00E+00 5.00E+00
VBS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
VTH -1.00E+00 -1.00E+00 1.00E+00 1.00E+00 1.00E+00
VDSAT -4.59E-01 -4.59E-01 4.99E-01 4.99E-01 4.99E-01

9.0 Inferred Biasing

50
V
DD
V
SS
(8)
(3)
Rb
MB1
MB2
(W/L)p
MB3
MB4
(W/L)n
4(W/L)n
(W/L)p
(15)
(16)
I
I
I
Msnk1
(W/L)n
Msrc1
(W/L)p
(4)
(5)
+
Vsnk
Msnk
(W/L)n
I I
NOTE: V(5)=V(15)
(6)
Figure 12a

* Input Signals

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

VSNK 6 0 DC 0VOLT


MB1 15 8 3 3 PMOS1 W=30U L=6.6U
MB2 8 8 3 3 PMOS1 W=30U L=6.6U
51
MB3 15 15 4 4 NMOS1 W={10.8U} L=6.6U
MB4 8 15 16 4 NMOS1 W={4*10.8U} L=6.6U
Msrc1 5 8 3 3 PMOS1 W=30U L=6.6U
Msnk1 5 5 4 4 NMOS1 W=10.8U L=6.6U
Msnk 6 5 4 4 NMOS1 W=10.8U L=6.6U

Rb 16 4 20K

* SPICE Parameters

* Analysis
.PROBE
.OP
.DC VSNK -5V 5V .1V
*.DC VSRC -5V 5V .1V
.END


( 3) 5.0000 ( 4) -5.0000 ( 5) -3.5010 ( 6) 0.0000

( 8) 3.5413 ( 15) -3.5010 ( 16) -4.8260

52

53

V
DD
(3)
Rb
MB3
MB4
(W/L)n
4(W/L)n
(16)
I
MB1
MB2
(W/L)p
(W/L)p
I
+
MB3a
(W/L)n
MB4a
(W/L)n
Msnka
(W/L)n
Msnkb
(W/L)n
Vsnk
MB1a
(W/.L)p
MB2a
(W/L)p
(4) VSS
(2)
(15a)
(15b)
(8b)
(15a)
(15b)
8a)
(14)
(13)
(12)
10.0 Cascode Widlar Current Sink

54

Figure 12b

* Input Signals

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

VSNK 2 0 DC 0VOLT


MB1 13 8b 3 3 PMOS1 W=30U L=6.6U
MB1a 15a 8a 13 13 PMOS1 W=30u L=6.6U
MB2 8b 8b 3 3 PMOS1 W=30U L=6.6U
MB2a 8a 8a 8b 8b PMOS1 W=30U L=6.6U
MB3 15b 15b 4 4 NMOS1 W={10.8U} L=6.6U
MB3a 15a 15a 15b 4 NMOS1 W=10.8U L=6.6U
MB4 14 15b 16 4 NMOS1 W={4*10.8U} L=6.6U
MB4a 8a 15a 14 4 NMOS1 W=10.8U L=6.6U
Msnka 12 15b 4 4 NMOS1 W=10.8U L=6.6U
Msnkb 2 15a 12 4 NMOS1 W=10.8U L=6.6U

Rb 16 4 15.5K

* SPICE Parameters

* Analysis
.PROBE
.OP
.DC VSNK -5V 5V .1V
.TF V(2) VSNK
.END


V(2)/VSNK = 1.000E+00

INPUT RESISTANCE AT VSNK = 1.489E+09

55


( 2) 0.0000 ( 3) 5.0000 ( 4) -5.0000 ( 12) -3.4910

( 13) 3.4907 ( 14) -3.4842 ( 16) -4.8434 ( 8a) 2.0117

( 8b) 3.5058 ( 15a) -1.3184 ( 15b) -3.4956

56

11.0 Opamp Design with Process and Temperature Independent
Implementation 1

V
DD
V
SS
M1 M2
M3 M4
M5
M7
M6
M9
M8
C
c
M11
V
DD
(6a)
(6b)
(8)
(1) (2)
V-
V+
(5)
(7)
(4)
(3)
(9)
(10)
M12
M13
(13)
(14)
k*(W/L)p
(W/L)n
(W/L)n
(W/L)p
k*(W/L)n
I
k*I
(W/L)p
Rb
MB1
MB2
(W/L)p
MB3 MB4
(W/L)n
4(W/L)n
(W/L)p
(15)
(16)

Figure 12c

* Input Signals
VID 11 0 DC -8.2484uV AC 1V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
57
M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U
M7 14 8 3 3 PMOS1 W={90U} L=6.6U
M8 4 9 10 10 PMOS1 W={3*90U} L=6.6U
M9 3 14 10 4 NMOS1 W={3*32.4U} L=6.6U
M11 6b 3 6a 4 NMOS1 W=6U L=27U
M12 9 9 13 13 PMOS1 W=90U L=6.6U
M13 14 14 13 4 NMOS1 W=32.4U L=6.6U
MB1 15 8 3 3 PMOS1 W=30U L=6.6U
MB2 8 8 3 3 PMOS1 W=30U L=6.6U
MB3 15 15 4 4 NMOS1 W={10.8U} L=6.6U
MB4 8 15 16 4 NMOS1 W={4*10.8U} L=6.6U
Rb 16 4 19K
Cc 9 6b 1pF

* SPICE Parameters

* Analysis
.PROBE
.DC VID -5V 5V .1V
.TF V(10) VID
.END


3 E 113 . 1 R ; M 43 . 9 f ; 88.5 PM ; 4 E 180 . 3 A
O GB V0
+ = = = + =


V(10)/VID = 3.180E+04




( 1) 4.124E-06 ( 2)-4.124E-06 ( 3) 5.0000 ( 4) -5.0000

58
( 5) 1.1533 ( 7) -3.4964 ( 8) 3.5174 ( 9) -3.5295

( 10) -2.0277 ( 11)-8.248E-06 ( 12) 0.0000 ( 13) -2.0334

( 14) .5814 ( 15) -3.4753 ( 16) -4.8170 ( 6a) -3.4936

( 6b) -3.4936

59
12.0 Opamp Design with Process and Temperature Independent
Implementation 2

V
DD
V
SS
M1 M2
M3 M4
M5
M7
M6
M9
M8
MB1
(W/L)p
MB3a
(W/L)n
MB3
MB2
(W/L)p
MB4a
(W/L)n
MB4
4(W/L)n
C
c
M11
Rb
(6a)
(6b) (9)
(10)
(8)
(1) (2)
V+ V-
(7)
(5)
(4)
(3)
(13)
(14)
(15)
(16)
(W/L)n

Figure 12a

* Filename="opamp33b.cir"
* Input Signals
VID 11 0 DC -8.2484uV AC 1V
E- 1 12 11 0 -0.5
E+ 2 12 11 0 0.5
VIC 12 0 DC 0V

* Power Supplies
VDD 3 0 DC 5VOLT
VSS 4 0 DC -5VOLT

M1 7 1 5 5 PMOS1 W={4*36.6U} L=6.6U
M2 6a 2 5 5 PMOS1 W={4*36.6U} L=6.6U
M3 7 7 4 4 NMOS1 W=5.4U L=6.6U
M4 6a 7 4 4 NMOS1 W=5.4U L=6.6U
M5 5 8 3 3 PMOS1 W=30U L=6.6U
60
M6 9 6a 4 4 NMOS1 W={32.4U} L=6.6U
M7 9 8 3 3 PMOS1 W={90U} L=6.6U
M8 4 9 10 10 PMOS1 W=873.6U L=6.6U
M9 10 8 3 3 PMOS1 W=300U L=6.6U
M11 6b 13 6a 4 NMOS1 W={20.4U} L=6.6U
MB1 13 8 3 3 PMOS1 W=30U L=6.6U
MB2 8 8 3 3 PMOS1 W=30U L=6.6U
MB3a 13 13 14 4 NMOS1 W=10.8U L=6.6U
MB3 14 14 4 4 NMOS1 W=10.8U L=6.6U
MB4a 8 13 15 4 NMOS1 W=10.8U L=6.6U
MB4 15 14 16 4 NMOS1 W=43.2U L=6.6U

Cc 9 6b 1pF

*External Bias Resistor
Rb 16 4 {17.5K}

* SPICE Parameters

* Analysis
.DC VID -5V 5V .1V
.TF V(10) VID
.PROBE
.END


3 E 379 . 1 R ; M 65 . 8 f ; 83 PM ; 4 E 790 . 3 A
O GB V0
+ = = = + =


V(10)/VID = 3.790E+04




( 1) 4.155E-06 ( 2)-4.155E-06 ( 3) 5.0000 ( 4) -5.0000

( 5) 1.1520 ( 7) -3.5007 ( 8) 3.5216 ( 9) -1.5420
61

( 10) -.2603 ( 11)-8.310E-06 ( 12) 0.0000 ( 13) -1.3042

( 14) -3.4895 ( 15) -3.4575 ( 16) -4.8343 ( 6a) -3.4979

( 6b) -3.4979

| | | |
| | 64 . 1 ) 6 . 0 ( 2 ) 5 ( 4979 . 3 ( ) 6 . 0 ( 2 1 1
2 VSS - V(6a) 2 V 2 V 2 V V
F TO F SB TO TN
= + + =
+ + = + + =

u
u
6 . 6
4 . 20
4 . 3
1.64) - (-3.4979) - 3)(-1.3042 6(13.25E - E 40
1
) V V(6a) ) 13 (V( R K
1
W/L) (
) V ) a 6 ( V ) 13 (W/L)(V( K
1
) V (W/L)(V K
1
V
I
r R
TN C N
TN N TN GS N
1
DS
D
DS10 C
=
+
=

=

=
=
|
|
.
|
\
|
= =

62

1.0 Cmos Opamp: 1.1. General Opamp Block Diagram

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