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Seminar Report

Chameleon Chip

A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically. This allows the chip to adapt effectively to the
programming tasks demanded by the particular software they are interfacing with at any given time. Ideally, the reconfigurable processor can transform itself from a video chip to a central processing unit (CPU) to a graphics chip, for example, all optimized to allow applications to run at the highest possible speed. These chips are like providing a "chip on demand." In practical terms, this ability can translate to immense flexibility in terms of device functions. For example, a single device could serve as both a camera and a tape recorder (among numerous other possibilities): you would simply download the desired software and the processor would reconfigure itself to optimize performance for that function. According to a recent Red Herring magazine article, that type of device versatility may be available by 2003. Reconfigurable processor chip usually contains several parallel processing computational units known as functional blocks. These functional blocks are connected in all the possible way. While reconfiguring the chip, the connections inside the functional blocks and the connections in between the functional blocks are changing. That means when a particular software is loaded the present hardware design is erased and a new hardware design is generated by making a particular number of connections active while making others idle. This will define the optimum hardware configuration for that particular software. The key to the design is the small size of each processing element. The smallest segments of the chip can be defined with just 50 bits of software code, so the entire chip can be reprogrammed with just 50,000 bits of software description. It takes just 20 microseconds to reconfigure the entire processing array. Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology). Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves. 1

Seminar Report

Chameleon Chip

In a conventional ASIC or FPGA, multiple algorithms are implemented as separate hardware modules. Four algorithms would divide the chip into four functional areas. With Reconfigurable Technology, the four algorithms are loaded into the entire reconfigurable Fabric one at a time. First, the entire Fabric is dedicated to algorithm 1; during this processing time, algorithm 2 is loaded into the background place. In a single clock cycle, the entire Fabric is swapped to algorithm 2; during this processing time, algorithm 3 is loaded into the background plane. The entire reconfigurable fabric is dedicated to just one algorithm at a time. The result: much higher performance, lower cost and lower power consumption



The most important parts are the logic circuits. Machine design supposes that some pins are considered as the configuration inputs and another as data or control inputs and outputs. a new reconfigurable machine is established. 2) A high-performance 32-bit Reconfigurable Processing Fabric (RPF) 3 www. which are used to construct the circuit. and 64-bit high-performance memory controller.seminarsonly. ARCHITECTURE The Chip incorporates three core architectural technologies: 1) A Complete 32 bit Embedded Processor system It provides all of the basic building blocks for a complete system: a 32-bit ARC processor. which configure function blocks according to data in the configuration memory.The various possible connections between functional blocks are encoded to bits known as Configuration bits. These fully integrated and fully verified modules simplify design. Resulting configuration stream is downloaded into configuration memory through configuration inputs. Thus. debug and verification. A new chip must inside determine the set of the function blocks (FB). Further it defines structure and writing mechanisms of the configuration memory.Seminar Report Chameleon Chip THE GENERAL ARCHITECTURE OF A RECONFIGURABLE CHIP The chip architecture depends on the given task. 32-bit interface. The structure of Reconfigurable chip is designed in some developmental tool . rules of their interconnections and ways of the input/output .

32-bit Data path Units and 24. split-transaction bus provides 2GByte/sec on-chip bandwidth amongst the subsystems in the Embedded Processor System and the RPF. 16x24-bit 4 www.seminarsonly. It consists of 84. providing tremendous computational power. exploit platform-based design and enable you to implement your own algorithms to differentiate your product ARC 32 BIT PCI BUS PCI CONTROLLER RECONFIGURABLE PROCESSING FABRIC (RPF) The Fabric (RPF or “Fabric”) provides unmatched algorithmic computation power to Chameleon Chip. This 128-bit.Seminar Report Chameleon Chip The RPF has 108 parallel computation 128 . This is where the "heavy lifting" (Rec Roadrunner Bus links these system modules. 3) Instantaneous reconfigurability These core technologies combine to eliminate the performance/flexibility compromise.

5 www. The fabric is divided into Slices. The high-performance 32bit Data path Unit (DPU): The Tile includes seven Data path Units. The CS2112 includes four Slices. The Dynamic Interconnect connects the modules within the fabric’. and Control Logic Units. The DPU is a data processing module that directly supports all C and Verilog (Verilog is a hardware description language used to design and document electronic systems) operations.000 16-bit Million MultiplyAccumulates Per Second and 24. There are 3 routing classes: a) Local routes-connects near by 7 DPUs with a delay of 1 clock cycle.Seminar Report Chameleon Chip Multipliers.000 16-bit Million Operations Per Second. each of which can be independently . Operating at 125Mhz. Each Slice consists of three Tiles. The Tile is built with 32-bit Data path Units. Local Store Memories. b) Intra-slice routes-connects DPUs within a slice with a delay of 1 clock cycle c) Inter-slice routes-connects DPUs in different slices with a delay of 2 clock cycles. The routing multiplexers select operands. the basic unit of reconfiguration.seminarsonly. onfiguration) is performed. they provide up to 3. 16x24-bit SingleCycle Multipliers.

com ROUTING M UX 6 . DAT www. The DPU also includes two 32-bit AND/OR Mask operators.Seminar Report Chameleon Chip The DPU includes a 32-bit real-time Barrel Shifter for shifting operations. The Operator supports number calculation signed/unsigned shifting and bit-field masking data operation modes.seminarsonly. At the heart of the DPU is the 32-bit Operator. which directly implements all C and Verilog operators.

The CLU includes the Programmable Sum-ofProducts(PSOP) and the Control State Memory (CSM). where each Instruction represents a complete DPU configuration. Dynamic Interconnect The Fabric provides 100% routability Connecting embedded processor system with the RPF results in Dynamic Interconnect: routes can be changed one a clock-byclock basis for flexible and optimal dataflow. With a total of 24 multipliers. The CSM stores eight userspecified Instructions for each of the seven DPUs in the Tile. Each PIO bank of 40 PIO pins delivers 0.Seminar Report Chameleon Chip 16x24 Single-Cycle Multiplier The Tile includes two 16x24-bit single-cycle multipliers. The LSM is accessed directly by the DMA Subsystem and the neighboring DPUs/Multipliers. PROGRAMMABLE I/O RCP includes banks of Programmable I/O (PIO) pins which provide tremendous bandwidth. Control Logic Unit (CLU) The Control Logic Unit directly implements finite state machine sequencing and conditional operation. the CS2112 delivers 3. 7 www.000 Million Multiply-Accumulates per Second. The PSOP implements conditional state sequences on a configurable context basis.seminarsonly.5 GBytes/sec I/O . Local Store Memory (LSM) The Tile includes four 32-bit wide by 128 word deep Local Store Memories.

transferring configuration data from off-chip memory through the 64-bit Memory Controller to the Background Configuration Plane.Seminar Report Chameleon Chip EMBEDDED PROCESSOR SYSTEM The Embedded Processor Systems provides all of the basic building blocks for a complete . debug and verification. It includes a 4 Kbytes instruction cache and a 4 Kbytes data memory. This integrated system platform consists of:  32-bit ARC Processor The Processor delivers 120 MIPS at 125 MHz and it employs 64 general-purpose 32-bit registers and a 32-bit address space. The Configuration Controller is an optimized DMA Controller. transferring data between the modules in the Embedded Processor System and to/from the Local Store Memories.seminarsonly.  Configuration Subsystem The Configuration Subsystem includes the Configuration Controller and the two Configuration Planes.  32-bit PCI ControllerInterface to PCI bus  64-bit Memory ControllerInterface to Memory  DMA SubsystemIt supports 16 DMA Channels. This transfer can take place during full-speed operation of the Fabric. loading a new configuration while the prior configuration is running on the Fabric TECHNOLOGIES USED IN CHIP 8 www. These fully integrated and fully verified modules simplify design.

As mentioned earlier. debugging and verifying RCP designs. This technology reconfigures fabric in one clock cycle and increases voice/data/video channels per chip. C~SIDE Development Tools Without the necessary software tools. The Chameleon Systems Integrated Development Environment (C~SIDE) is a complete toolkit for designing.seminarsonly. with eConfigurable Technology. With this software. this operation does not interfere with active processing on the Fabric. 9 . the four algorithms are loaded into the entire reconfigurable processing Fabric one at a time. C~SIDE includes an optimized GNU C compiler for the ARC Processor and an optimized Verilog To Bits (V2B) synthesizer for the Reconfigurable Processing Fabric. As a result customers had to give their algorithms to developers. an instruction-set simulator and a unified debug environment for the ARC core and the RPF. Loading the Background Plane from external memory requires just 3 µsec per Slice. C~Side uses a combined C language and Verilog (Verilog HDL is a hardware description language used to design and document electronic systems) flow to map algorithms into the chip's reconfigurable processing fabric (RPF). 2. each Slice can be configured independently. Chameleon Systems are providing the ability for the customers to do the programming themselves thus keeping the secrecy of their algorithms.Seminar Report 1. Chameleon Chip eCONFIGURABLE™ TECHNOLOGY eConfigurable™ Technology is used for instantaneous reconfiguration. Swapping the Background Plane into the Active Plane requires just one clock cycle. an interactive floor planner. no one but the inventors has been able to port software to the processors.

but can be edited for precise control of any function. The eBIOS calls are automatically generated at compile time. So a mapping is needed between them. One end of design is a C/C++ program and the other side is processing .Seminar Report Chameleon Chip 3. But C is not a hardware description language (HDL). DESIGN PROCESS Design process consists of converting a C/C++ program to a hardware configuration. For that an assembler is provided by Chameleon Systems. Now C/C++ algorithm is mapped to a hardware configuration 10 www. When an assembly language like description of C/C++ program is given to this assembler it will generate Verilog descriptions.When a hardware description in verilog is obtained it can be converted to configuration bits using VerilogToBits (V2B) synthesizer. Configuration bits actually specify hardware configuration. eBIOS provides resource allocation. To specify a hardware configuration a HDL is needed. configuration management and DMA services. eBIOS™ eBIOS provides a interface between the Embedded Processor System and the Fabric.seminarsonly. Now a mapping between C/C++ program and verilog is needed. For that purpose Chameleon Systems uses a HDL called Verilog.

system architects continue to struggle with the requirement that communication systems deliver both performance and flexibility. The RCP fills the void between fast but inflexible ASICs. digital signal processors (DSPs).Seminar Report Chameleon Chip DESIGN PROCESS C/C++ PROGRAM ASSEMBLER VERILOG V2B CONFIGURATION BITS HARDWARE COMPARISON WITH OTHER TECHNOLOGIES Today’s system architects have at their disposal an arsenal of highly . high-performance semiconductor technologies. such as application-specific integrated circuits (ASICs). Enter the reconfigurable processor. and flexible but slow and costly DSPs and 11 www.seminarsonly. application-specific standard products (ASSPs). and field-programmable gate arrays (FPGAs). However. an entirely new category of semiconductor solution that serves as a system-level platform for a broad range of applications.

•COMPARIS TEC RCP FLEXIB ILITY COST PERFOR 12 TABLE 1 HIGH LOW HIGH .seminarsonly.Seminar Report Chameleon Chip FPGAs.Table1 shows the comparison of RCP with other technologies in terms of Flexibility. cost. performance and time – factors.

or FPGA-based solutions with equivalent data  Increasing bandwidth. Prototyping using RCPs and associated tools enables a fast all-software . RCPs substantially reduce development cycles and costs normally associated with ASIC design  Reducing manufacturing cost. higher internal and external I/O speeds. Converting a prototype to an ASIC solution for cost reduction and then manufacturing the ASIC is a lengthy and costly process.seminarsonly. closer interaction between the on-chip RISC processor and the reconfigurable data stream logic. DSP processing speed is typically limited by an internal bus that provides the interconnect for multiple execution units. the manufacturing cost advantage of an RCP over DSP.  Reducing development cost.  Reducing power. and the algorithmic flexibility to adapt to 13 www. Every feature of the RCP — more fundamental processing power.Seminar Report Chameleon Chip ADVANTAGES  Early and fast design Design cycle time and cost actually increase due to the fact that FPGAs are bitoriented arrays that incur large silicon overhead when used to process wide data streams. Measured by chip count or silicon area. RCPs achieve better speed/power characteristics than DSPs and FPGAs.

14 www. Morphics Technology in Campbell. which offered them a spectrum of programmable or hard-wired options. Besides QuickSilver and Chameleon. California. Ultimately. there is a "learning curve" for designers unfamiliar with reconfigurable logic.  At present. They should expand from there.  Several startups in reconfigurable computing have chosen the next-generation wireless market as the key battleground. That will let users draw data-flow diagrams in lieu of writing code. DISADVANTAGES  Inertia might be the worst problem facing reconfigurable computing. and they're comfortable designing things the old way. the complete RCP design process should merge seamlessly with the equipment manufacturer’s other design tools.  Controlling the development time and costs in an RCP design requires a comprehensive set of tools – a design environment with a graceful flow from systems design to executable files that run the embedded microprocessor and configure the fabric. Because designer has to study Chameleon’s assembly like design entry language. is also targeting the wireless market.Seminar Report Chameleon Chip predetermined conditions — enables the development of higher system bandwidth cost effectively. Hardware and software debugging and verification tools are also necessary. Researches are going on to help designers enter their design through such tools as Matlab or . Engineers are slow to change. .Seminar Report Chameleon Chip 15 www.

com . provides very high bandwidth.Using DSL Technology the remaining bandwidth can be effectively used for fax and voice transmission. With a reconfigurable processor. With a fixed processor the channels must be able to support both simple voice calls and high-bandwidth data connections. Hence they can be effectively used in local switching stations. Wireless Base stations The reconfigurable technology mainly focuses on base stations and their unpredictable combination of voice and data traffic. First generation Reconfigurable Communication Processor. 3. each channel can be allotted the exact amount of bandwidth it requires. the DSL technology cannot be efficiently and effectively implemented. 2.Seminar Report Chameleon Chip APPLICATIONS 1. which can provide Millions Hz of bandwidth.seminarsonly. Usual frequency range used in telecommunication range from 30004000Hz. CS2112. which means many voice calls do not use up all the bandwidth that is assigned to them. 16 www. High-Performance DSL (Digital Subscriber Line Technology) DSL technology brings high Bandwidth to homely users. So if Processors employed in telephone switching stations can’t handle that much bandwidth requirement. Wireless Local Loop (WLL) Reconfigurable technology is widely applied in Wireless Local Loops also because of their high processing power.Base-station infrastructure will have to be adaptive enough to accommodate those requirements. bandwidth and reconfigurable nature. Telephone communication lines usually used consists of two wires.

the processor will reconfigure itself to provide a new hardware design for the new protocol so that they can be used with new protocols and coming protocols also. If these protocols get changed. 17 www. If reconfigurable processors are used in cell phones. A cell phone uses some protocols to communicate with each other.seminarsonly. Cell phones cannot communicate. Software-Defined Radio (SDR) SDR concept is applied in Cell phone .Seminar Report Chameleon Chip 4.

the phone will automatically adjust so that the quality improves. If these adaptable chips can reach cost-performance parity with hard-wired chips. 18 www. At the same time. or games. Nobody has figured out a way to get a chip to meet all the criteria for the ultimate consumer device. someone will make a chip that does everything for the ultimate consumer device. Today.seminarsonly. These chips are referred to as reconfigurable processors. videos. Now a new kind of chip adapts to any programming task by effectively erasing its hardware design and regenerating new hardware design that is perfectly suited to run the software at hand. These new chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost . But we might be getting closer. so will the gadgets of the information age.Seminar Report Chameleon Chip CONCLUSION One day. the device will also serve as a handheld organizer and a player for music. designing such a chip crosses too many architectural boundaries. If the reception is poor. The chip will be smart enough to be the brains of a cell phone that can transmit or receive calls anywhere in the world.

com/ghp_japan/misty/misty1megafunc. 19 www. "CHAMELEON: A dynamically reconfigurable hardware-based cryptosystem.htm 6. Matt Moe. MA. and I. Herman Schmit . Mitsuyama.seminarsonly. R. 5. Andre DeHon. J. Mihai Budiu . Hauser . EUROMEDIA. Reed Taylor. Cambridge. Garp: a MIPS processor with a reconfigurable coprocessor. ." in Proc. Massachusetts Institute of Technology. Reconfigurable Architectures for General-Purpose Computing.seminarsonly. Andales.Seminar Report Chameleon Chip REFERENCES 1 J. http://www. Srihari Cadambi . Onoye. 3 4 Z. www. T. 2 Seth Copen Goldstein . PipeRench: A Reconfigurable Architecture and Compiler. Shirakawa. R. Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines.

seminarsonly. Nobody has figured out a way to get a chip to meet all the criteria for the ultimate consumer device. Now a new kind of chip adapts to any programming task by effectively erasing its hardware design and regenerating new hardware design that is perfectly suited to run the software at hand.Seminar Report Chameleon Chip ABSTRACT Today. But we might be getting . 20 www. This new chip is called CHAMELEON CHIP. These chips are referred to as reconfigurable processors. designing a chip crosses too many architectural boundaries. These new chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost speed.


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