VHDL code for 8 point FFT algorithm

A Fast Fourier Transform(FFT) is an efficient algorithm for calculating the discrete Fourier transform of a set of data. A DFT basically decomposes a set of data in time domain into different frequency components. DFT is defined by the following equation:

A FFT algorithm uses some interesting properties of the above formula to simply the calculations. You can read more about these FFT algorithms here. Many students have been asking doubts regarding vhdl implementation of FFT, so I decided to write a sample code. I have selected 8 point decimation in time(DIT) FFT algorithm for this purpose. In short I have wrote the code for this flow diagram of FFT. This is just a sample code, which means it is not synthesisable. I have used real data type for the inputs and outputs and all calculations are done using the math_real library. The inputs can be complex numbers too. To define the basic arithmetic operations between two complex numbers I have defined some new functions which are available in the package named fft_pkg. The component named, butterfly , contains the basic butterfly calculations for FFT as shown in this flow diagram. I wont be going any deep into the theory behind FFT here. Please visit the link given above or Google for in depth theory. There are 4 vhdl codes in the design,including the testbench code, and are given below. The package file - fft_pkg.vhd:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.MATH_REAL.ALL; package fft_pkg is type complex is record r : real; i : real; end record; type comp_array is array (0 to 7) of complex; type comp_array2 is array (0 to 3) of complex; function add (n1,n2 : complex) return complex; function sub (n1,n2 : complex) return complex; function mult (n1,n2 : complex) return complex; end fft_pkg;

r .r:=n1.n2.n2 : complex) return complex is variable diff : complex.r. prod.ALL.i:=n1.r:=n1. end add.(n1. return sum.r:=(n1.i. return diff.r + n2. --input signals in time domain y : out comp_array --output signals in frequency domain . begin sum. return prod.i .package body fft_pkg is --addition of complex numbers function add (n1. use work.r.i:=(n1. library work.i * n2. end mult.r) .i). use IEEE.ALL. use IEEE.fft_pkg.r * n2. begin prod.vhd: library IEEE.i + n2.r * n2.fft8.MATH_REAL.i.n2.i:=n1. diff.r).i) + (n1.STD_LOGIC_1164. function mult (n1. function sub (n1. --subtraction of complex numbers.ALL.i * n2. end sub. end fft_pkg.n2 : complex) return complex is variable prod : complex. entity fft8 is port( s : in comp_array.n2 : complex) return complex is variable sum : complex. --multiplication of complex numbers. sum. The top level entity . begin diff.

7071. --inputs w :in complex.y(0). architecture Behavioral of fft8 is component butterfly is port( s1. port map(g2(0).0.y(5)).w(0). end fft8.w(0).g1(6). and i has range from 0 to 7. port map(s(3).ALL. . library IEEE.g1(3)). constant w : comp_array2 := ( (1.g1(2).-0.y(2).y(7)).0.g1(6).1.y(1).y(3).w(3). (0.g2(5).g2 : comp_array := (others => (0.w(0).ALL. port map(g2(2).0).w(1).y(4)).g1(2).-0.w(2). --W_N^i = cos(2*pi*i/N) . port map(s(0).w(0).g2(5).g2(6)).vhd: butterfly's. library work.g2(2)).y(6)). -. begin --first stage of bf11 : butterfly bf12 : butterfly bf13 : butterfly bf14 : butterfly butterfly's.butterfly. port map(s(1). Butterfly component . (0.phase factor g1.0.7071).g2(7). --second stage of butterfly's.s(4).g2(4).s(6). end component.g1(5)).s(5).w(0).w(2).STD_LOGIC_1164.g1(4).g2 :out complex -.7071) ).7071. port map(g2(1).g1(7).g1(1)).g2(1).j*sin(2*pi*i/N).w(0). port map(g2(3). --phase factor.0.g2(6).g1(3). use IEEE. port map(s(2). (-0. use work. bf22 : butterfly port map(g1(1). --third stage of bf31 : butterfly bf32 : butterfly bf33 : butterfly bf34 : butterfly end Behavioral.g2(3)).0)). W_N = e^(-j*2*pi/N) and N=8 here.g2(0).g1(0).0.g2(7)).outputs ).fft_pkg.s(7). signal g1.). bf24 : butterfly port map(g1(5). bf21 : butterfly port map(g1(0).w(0).0).s2 : in complex.g2(4).w(2).g1(7)). bf23 : butterfly port map(g1(4).

fft8 PORT MAP ( s => s.entity butterfly is port( s1. BEGIN -.2).w)).w)). end Behavioral. s(3) <= (-3. end butterfly.6.outputs ). USE ieee. g1 <= add(s1. -. ENTITY tb IS END tb.Instantiate the Unit Under Test (UUT) uut: entity work.2).7).std_logic_1164.1.-2. s(2) <= (1.ALL.mult(s2. ARCHITECTURE behavior OF tb IS signal s. Testbench code .-2.0). architecture Behavioral of butterfly is begin --butterfly equations.tb_fft8.s2 : in complex.1. s(5) <= (-1. s(4) <= (4.phase factor g1.all.g2 :out complex -. s(0) <= (-2. --inputs w :in complex.0.2). .0.vhd: LIBRARY ieee. g2 <= sub(s1.Stimulus process stim_proc: process begin --sample inputs in time domain. y => y ). s(1) <= (-2. use work.- -.y : comp_array.fft_pkg. library work.5).

You will get the output in the output signal 'y'. wait. END. end process. Hope the codes are helpful for you.5).5. Copy and paste the above codes into their respective files and simulate. Once again.8.s(6) <= (0. the code is not synthesisable.2).1. In case you want a synthesisable version of the codes or want a customized FFT vhdl code then contact me.-4. . s(7) <= (-2.

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