ECE, 5th SEM ENRL NO.

- 014209208

AMIT KUMAR

MOS FABRICATION AND LAYOUT GENERATION BY L-EDIT # PLACING A SET OF PATTERNED LAYERS ONE ABOVE PREVIOUS USING APPROPRIATE MASK # USING LAYER IN A SOFTWARE PICTORIAL REPRESENTATION OF A MOS .

GENERATION OF VARIOUS COMPONENT LAYOUT • • • • • NMOS PMOS CMOS INVERTER OR GATE NAND GATE etc. .

SIMPLE NMOS LAYOUT NMOS structure NMOS layout .

Title SiO2 Insulator W Source p+ channel p+ Polysilicon Gate L Drain G S SB G substrate connected to VDD D n substrate p transistor SiO2 Insulator W Source n+ channel Polysilicon Gate L Drain n+ D D G SB G S S substrate connected to GND p substrate n transistor .

GENERATED LAYOUT OF CMOS INVERTER • PMOS INTERCONNECTED • NMOS .

GENERATION OF NOR GATE • A LAYOUT OF NOR • GATE BY NOS AND • PMOS • INTERCONNECTION .

DESIGN RULES 1st MICRON RULE 2nd LAMBDA RULE .

LOGICAL REPRESENTATION OF AN AND GATE USING NAND AND INVERTER .

LAYOUT OF AND GATE BY NAND GATE .

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Composite layout and cross-section view of n-well CMOS device (excludes passivation and patterning of wire-bonding pads) .

GENERATED LAYOUT OF A NAND GATE .

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