Solution Manual for Modern Digital Electronics
Third Edition
R P Jain
CHAPTER 1
1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure being measured and can assume any value in the given range. (b) Digital. An electric pulse is produced for every person entering the exhibition using a photoelectric device. These pulses are counted using a digital circuit. (c) Analog. The reading of the thermometer is proportional to the temperature being measured and can assume any value in the given range. (d) Digital. Inputs are given with the help of switches, which are converted into digital signals 1 and 0 corresponding to the switch in the ON or OFF position. These signals are processed using digital circuits and the results are displayed using digital display devices. (e) Analog. It receives modulated signals which are analog in nature. These signals are processed by analog circuits and the output is again in the analog form. (f) Digital. It has only two possible positions (states), ON and OFF. (g) Digital. An electric pulse is produced for every vote cast by pressing of switch of a candidate. The pulses thus produced for each candidate are counted separately and also the total number of votes polled are counted. 1.2 (a)
(i) S1 OFF OFF ON ON (iii) S OFF ON S2 OFF ON OFF ON Bulb ON OFF Bulb OFF OFF OFF ON (iv) (ii) S1 OFF OFF ON ON S1 OFF OFF ON ON S2 OFF ON OFF ON S2 OFF ON OFF ON Bulb OFF ON ON ON Bulb OFF ON ON OFF
(b) (i) S1 0 0 1 1 (iii) S 0 1 S2 0 1 0 1 Bulb 1 0 Bulb 0 0 0 1 (iv) (ii) S1 0 0 1 1 S1 0 0 1 1 S2 0 1 0 1 S2 0 1 0 1 Bulb 0 1 1 1 Bulb 0 1 1 0
(c)
(i) AND
(ii) OR
(iii) NOT
(iv) EXOR
1.3
1 Input A 0 1 Input B 0 0 1 2 3 4 5 t(ms) 0 1 2 3 4 5 t(ms)
1 AND 0
1 OR 0
1 NAND 0
1 NOR 0
1 EXOR 0
1.4
Inputs A 0 0 1 1 B 0 1 0 1 (a) 1 0 0 0 Outputs of (b) (c) 1 1 1 0 0 0 0 1 (d) 0 1 1 1
The operations performed are (a) NOR (b) NAND
(c) AND
2
(d) OR
5
For Fig. 1.8 (a) A 0 1 Y 1 0 (b) A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1
A+B
Y 0 1 1 1
1 0 0 0
(c)
A 0 0 1 1
B 0 1 0 1
A
1 1 0 0
B
1 0 1 0
1.1.6
(a) A 0 1 Y 1 0 (b) A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1
AB
1 1 1 0
Y 0 0 0 1
(c)
A 0 0 1 1
B 0 1 0 1
A
1 1 0 0
B
1 0 1 0
For Fig. 1. NOR (c) NAND (a)
Inputs A 0 0 1 1 B 0 1 0 1
(b) AND (d) OR
AB 0 0 1 0
AB
0 1 0 0
Output Y 0 1 1 0
(b) EX–OR (c) A
Y
B 3
.7
(a) NAND.6 1.
the resulting truth table will be same as that of the AND gate. the higher of the two voltages is designated as 1 and the lower voltage as 0. the lower of the two voltage is designated as 1 and the higher voltage as 0. (a) In the truth table of positive logic AND gate replace all zeros by ones and all ones by zeros. the logic system will change from positive to negative and viceversa.
A Y1 Y
Y1 = AB
and
Y2 = AB
B
Y2
1. The resulting truth table is same as that of the OR gate. In the positive logic system. Therefore. if 1s and 0s are interchanged. but the results are equally valid for any number of inputs.(d) \
Y = AB + A B
Y = AB + A B
= AB ⋅ A B
Y = Y = AB ⋅ AB = Y1 ⋅ Y2
where. we shall consider 2input gates. Similarly.8
For simplicity.9
. (b) Repeat part (a) for NAND and NOR gates. On the other hand in the negative logic system. (a) A + A B + A B = (A + A B ) + A B = A (1 + B ) + A B = A × 1 + AB = A + AB = (A + A ) (A + B) = A + B (b) AB + A B + A B = (A + A ) B + A B = B + A B = (B + A ) (B + B ) = A +B (c) A BC + A B C + AB C + ABC = A BC + A B C + AB (C + C ) = A BC + A B C + AB = A BC + A (B + B C) = A BC + A (B + B ) (B + C)
4
1. if all ones and zeros are interchanged in the truth table of the OR gate.
and one 3input OR gate.10 (a)
A 0 0 1 1 B 0 1 0 1
AB
AB 0 0 1 0
A + A B + AB 0 1 1 1
A+B 0 1 1 1
0 1 0 0
(b)
A 0 0 1 1 B 0 1 0 1 AB 0 0 0 1
AB AB
AB + A B + A B 1 1 0 1
A +B
0 1 0 0
1 0 0 0
1 1 0 1
(c)
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1
A BC
0 0 0 1 0 0 0 0
AB C 0 0 0 0 0 1 0 0
AB C 0 0 0 0 0 0 1 0
ABC LHS 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1
AB 0 0 0 0 0 0 1 1
BC 0 0 0 1 0 0 0 1
CA 0 0 0 0 0 1 0 1
RHS 0 0 0 1 0 1 1 1
1.= A BC + AB + AC = C (A + A B) + AB = C (A + A ) (A + B) + AB = C (A + B) + AB = AB + BC + CA 1. two 2input AND gates. two inverters. whereas the realization of RHS requires only one two input OR gate.
A A B B
(i) 5
(ii)
.11
(a) The realization of LHS requires.
four 3input AND gates and one 4input OR gate. whereas the realization of RHS requires only one inverter and one 2input OR gate. three 2input AND gates and one 3input OR gate.(b) The realization of LHS requires two inverters.12
(a) AB + CD = AB + CD = AB ⋅ CD
6
.
A
B C
(i) A B
C
(ii)
1. whereas the realization of RHS requires only three 2input AND gates and one 3input OR gate.
A A B B
(i)
(ii)
(c) The realization of LHS requires three inverters.
This can be proved by making truth table as given below:
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 (A × B) × C 0 0 0 0 0 0 0 1 A × (B × C) 0 0 0 0 0 0 0 1
7
.(b) (A + B) (C + D) = ( A + B) ⋅ ( C + D )
= ( A + B) + ( C + D ) (i) The left hand side of (a) can be realized by using two 2input AND gates followed by one 2input OR gate. then the AND operation is associative. Hence an ANDOR configuration is equivalent to a NANDNAND configuration. the AND operation is commutative. while the right hand side is realizable by two 2input NOR gates followed by another 2input NOR gate.13
(a) A B A B Y C D (i) (b) A B A B Y C D (i) C D (ii) Y C D (ii) Y
1.14 (a) Since A × B = B × A Therefore. If A × (B × C) = (A × B) × C. Hence an ORAND configuration is equivalent to a NORNOR configuration. (ii) The left hand side of (b) is realizable by two 2input OR gates followed by a 2input AND gate.
1. while the right hand side is realizable by two 2input NAND gates followed by another 2input NAND gate.
16 1. .. the NAND operation is commutative. then (1 Å 0) Å 0 Å 0 Å . .. which means the EXOR operation is commutative. = 0 Å 0 Å 0 Å 0 Å .15 (a) Since = A ⋅ B = B ⋅ A . . =1 Å0=1 (ii) If only two of the variables are 1 and all others are zero. if only three of the variables are 1. The associative property requires A + (B + C) = (A + B) + C which can be proved by making the truth table in a way similar to the truthtable of (a) above (c) Since. . From the Table we observe that the last two columns are not identical. which means the NOR operation is commutative. =0 Å1Å0Å0Å0Å.
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1
A ⋅ ( B ⋅ C)
1 1 1 1 0 0 0 1
( A ⋅ B) C
1 0 1 0 1 0 1 1
(b) Since. therefore. The associative property requires (A Å B) Å C = A Å (B Å C) This can be proved by making truth table 1. (b) Since. then (1 Å 1) Å 1 Å 0 Å 0 Å . A Å B = B Å A. . =1
8
. . . By making a truth table similar to the truth table of (a) above we can verify that
( A + B) + C ≠ A + ( B + C )
1. which means
A ⋅ ( B ⋅ C ) ≠ ( A ⋅ B) ⋅ C
This shows that the NAND operation is not associative. therefore. the NOR operation is not associative. .Since the last two columns of the truth table are identical.17 Therefore. A + B = B + A . which proves that the AND operation is associative. OR operation is commutative. . Two possible realizations are given on page 9: (i) If only one of the variables is 1 and all others are zero. . To verify whether the NAND operation is associative or not. then (since EXOR operation is commutative and associative) (1 Å 1) Å 0 Å 0 Å 0 Å . A + B = B + A. = 0 (iii) Similarly. = 1 Å 0 Å 0 Å . we prepare the truth table as given below.
A B C D
AÅB AÅBÅC
Y AÅBÅCÅD or
A B
AÅB
C D CÅD Fig. . 000 to 11 . The number of pins = 4 ´ 3 + 2 = 14. two for inputs and one for output. Hence it is a 14pin IC. The number of pins = 2 ´ 6 + 2 = 14. (c) 7408 is a quad 2input AND gate. (f) 7420 is a dual 4input NAND gate. (b) 7404 is a hex inverter. 1.
9
. (g) 7427 is a triple 3input NOR gate. The number of pins = 4 ´ 3 + 2 = 14. it is packaged as 14pin IC. The number of pins = 4 ´ 3 + 2 = 14. Since a logical variable can assume one of the two values (0 or 1) the number of possible combinations is 2N. . therefore. The number of pins = 5 ´ 2 + 2 = 12. The number of pins = 3 ´ 4 + 2 = 14. (h) 7432 is a quad 2input OR gate.17
Y AÅBÅCÅD
1. 111 in normal binary ascending order. . This means there are four identical 2input NOR gates.18
1. Two pins are left free (NC). The number of pins = 3 ´ 4 + 2 = 14. It is obvious from the above discussion that Z = 1. . Since 12pin IC package is not used. (d) 7410 is a triple 3input NAND gate.19
In the same way we can try higher number of ones. (a) 7402 is a quad 2input NOR gate. Two pins are required for the power supply (VCC and GND). the four gates requires 3 ´ 4 = 12 pins. b2b1b0 and write all combinations from 00 . if an odd number of variables are 1 and Z = 0 if an even number of variables are 1. (e) 7411 is a triple 3input AND gate. . Take an Nbit binary number bN–1 bN–2 . Therefore. Each gate requires three pins. .
20
1.4V = 0 2V = 1 Logic Circuit B –0.55V = 0
Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 AND Y1 0 0 0 0 0 0 0 1 OR Y2 0 1 1 1 1 1 1 1 Output NAND Y3 1 1 1 1 1 1 1 0 NOR Y4 1 0 0 0 0 0 0 0
1.75V = 1 –1. (a) (i) 7408 and 7432 (ii) 7400 (b) (i) 7432 and 7408 (ii) 7402 Logic Circuit A 0.21
(i) 7486 is a quad EXOR gate.
A B C Y or A B C Logic 1 (b) A B C Y or A B C Logic 0 (c) A B C Y or A B C Logic 1 (d) A B C Y or A B C Logic 0 10 Y Y Y Y
.23
(a)
Yes.22
1. The number of pins = 3 ´ 4 + 2 = 14.1.
24
1. AND — by connecting one of the inputs to logic 0 OR — by connecting one of the inputs to logic 1 NAND — by connecting one of the inputs to logic 0 NOR — by connecting one of the inputs to logic 1.26 1.25 1.1.27
Yes. (a) Activehigh (b) Activelow (c) Activehigh (d) Activelow (a) Activelow (b) Activehigh (c) Activelow (d) Activehigh (a)
A B Y C
Y = A × B × C = (A × B) × (C) (b)
A B Y C
Y = A + B + C = (A + B) + (C) (c)
A B AB Y C AB
C
Y = A ⋅ B ⋅ C = ( A ⋅ B) + C
= ( A ⋅ B) ⋅ C
= A⋅ B⋅C
(d)
A B C 11 Y
.
1.28
(a) A Å B = A B + A B
A Å B = AB + A B
= AB + AB = A Å B (b) A ⊕ B = AB + AB A Å B = AB + A B = AB + AB
A Å B = AB + A B = AB + AB (c) B Å (B Å AC) = B Å B Å AC = 0 Å AC = AC
12
.
625)10 (g) 0.CHAPTER 2
2.125 + 0.125 = (10.1875)10 (f) 1010.0625 = (13.0011 = 1 ´ 23 + 1 ´ 22 + 0 ´ 21 + 1 ´ 20 + 0 ´ 2–1 + 0 ´ 2–2 + 1 ´ 2–3 + 1 ´ 2–4 = 8 + 4 + 0 + 1 + 0 + 0 + 0.5 + 0.5 + 0.1 (a) 111001 = 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 16 + 8 + 0 + 0 + 1 = (57)10 (b) 101001 = 1 ´ 25 + 0 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 0 + 8 + 0 + 0 + 1 = (41)10 (c) 11111110 = 1 ´ 27 + 1 ´ 26 + 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 1 ´ 22 + 1 ´ 21 + 0 ´ 20 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254)10 (d) 1100100 = 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100)10 (e) 1101.125 = (0. (b) (255)10 = (11111111)2 (c) (15)10 = (1111)2
13
37 2 18 2 9 2 4 2 2 2
1 2
18 9 4 2 1 0
0
0
1
0
1
.1010 = 8 + 2 + 0.875)10 Quotient Remainder 1 0 1 0 0 1 1 Thus (37)10 = (100101)2 Similarly.25 + 0.2 (a) = 0.11100 2.
(d) Integer part: (26)10 = (11010)2 Fractional part: 0.25 0.5 ´2 ´2 0.5 1.0 ¯ ¯ 0 1 Therefore, (26.25)10 = (11010.01)2 (e) Integer part: (11)10 = (1011)2 Fractional part: 0.75 0.5 ´2 ´2 1.5 1.0 ¯ ¯ 1 1 Thus (11.75)10 = (1011.11)2 (f) 0.1 0.2 0.4 0.8 0.6 0.2 0.4 0.8 ´2 ´2 ´2 ´2 ´2 ´2 ´2 ´2 0.2 0.4 0.8 1.6 1.2 0.4 0.8 1.6 ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ 0 0 0 1 1 0 0 1... Thus, (0.1)2 = (0.00011001)2 The process may be terminated at the required number of significant bits. 2.3 (a) 1 1 1 1 0 0 ¬ Carry 1 1 0
1 0 +1 1 1 1 0 Final carry (b) 1 1 + 1 0 Final carry 2.4 (a) 01000 –01001 1 0 1 0 1 1 0 0
1 0. 1. 0.
1 1 0 0 1 1 0
¬ Carry 0 0 1 1
01000 + 10111 (2’s complement) 11111 Since the MSB of the sum is 1, which means the result is negative and it is in 2’s complement form. 2’s complement of 11111 = 00001 = (1)10 Therefore, the result is –1.
14
(b)
(c)
01100 Þ 01100 –00011 + 11101 (2’s complement) 101001 = + 9 Ignore 0011.1001 Þ 0011.1001 –0001.1110 +1110.0010 (2’s complement) 10001.1011 = + 1.6875 Ignore Quotient
375 8 46 8 5 8
2.5 (a)
Remainder 7 6 5 6 7
46 5 0
5 Therefore, (375)10 = (567)8 = (101110111)2 (b) Quotient Remainder 249 31 1 8 31 3 7 8 3 0 3 8 3
7
1
(c)
2.6 (a)
(b) (c)
Therefore, (249)10 = (371)8 = (011111001)2 Integer part: (27)10 = (33)8 = (011011)2 Fractional part: 0.125 ´8 1.000 ¯ 1 Thus (0.125)10 = (0.1)8 = (0.001)2 Therefore, (27.125)10 = (33.1)8 = (011011.001)2 11 011 100.101 010 = (334.52)8 (334.52)8 = 3 ´ 82 + 3 ´ 81 + 4 ´ 80 + 5 ´ 8–1 + 2 ´ 8–2 = (220.65625)10 01 010 011.010 101 = (123.25)8 = (83.328125)10 10 110 011 = (263)8 = (179)10
15
2.7 (a)
375 16 23 16 1 16
Quotient 23 1 0
Remainder 7 7 1
1 7 7 Therefore, (375)10 = (177)16 (or 177H) = (0001 0111 0111)2 (b) Quotient Remainder 249 15 9 16 15 0 15 16 F 9 Therefore, (249)10 = (F9)16 (or F9H) = (1111 1001)2 (c) Integer part: Quotient Remainder 27 1 11 16 1 0 1 16 1 B Thus (27)10 = 1BH Fractional part: 0.125 ´ 16 2.000 ¯ 2 \ (0.125)10 = 0.2H \ (27.125)10 = (1B.2)16 = 1B.2H = (00011011.0010)2 2.8 (a) 1101 1100.1010 10 = (DC.A8)16 (DC.A8)16 = 13 ´ 161 + 11 ´ 160 + 10 ´ 16–1 + 8 ´ 16–2 = (220.65625)10 (b) 0101 0011.0101 01 = (53.54)16 = (83.328125)10 (c) 1011 0011 = (B3)16 = (179)10 2.9 For each decimal digit write its natural BCD code (a) 46 = 0100 0110 (BCD) (b) 327.89 = 0011 0010 0111.1000 1001 (BCD) (c) 20.305 = 00100000.0011 0000 0101 (BCD) 2.10 For each decimal digit write its 4bit Excess3 code. (a) 46 = 0111 1001 (Excess3) (b) 327.89 = 0110 0101 1010.1011 1100 (Excess3) (c) 20.305 = 0101 0011.0110 0011 1000 (Excess3)
16
form 6bit Gray Code as given in Table 2.2.9). Table 1
Decimal No. a 1 is to be attached as MSB and the resulting 8bit code with even parity will be 11010010 Similarly. From Table 2.12 Writing the 6bit code for each character (See Table 2.8 formulate 5bit Gray code as given below in Table 1.13 (a) Write the 7bit ASCII code for each character (See Table 2.P. the code for l is 0101110 which has four ones. For example.9) R.P.11 Starting from 4bit Gray code given in Table 2.10) R. we obtain 100111 001011 000011 101100 101000 2. 0 1 2 0 : 17 : 30 31 32 33 : 46 : 62 63 G5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 G4 0 0 0
Table 2
G3 0 0 0 G2 0 0 0 G1 0 0 1 G0 0 1 1
1 1 1 1 1 1
1 0 0 0 0 1
1 1 1 1 1 1 0 0
1 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 0 0 1 1 1 0
0 0 0
0 0 0
1 0 0
1 1 0
Similarly. Therefore.9) R.14 (a) Count the number of ones for every character from ASCII table and attach a 1 or 0 as the MSB for odd or even number of ones respectively. 0 1 2 : : 13 14 15 16 17 18 : : 29 30 31 G4 0 0 0 : : 0 0 0 1 1 1 : : 1 1 1 G3 0 0 0 G2 0 0 0 : : 0 0 0 0 0 0 G1 0 0 1 G0 0 1 1 3 1 1 0 0 1 1 Decimal No.P. we obtain (46)10 = 111001 (Gray Code) 2.
17
. JAIN = 101001 011011 100111 011011 100001 010001 011001 100101 2. which has three ones. a 0 is to be attached as MSB and the resulting 8bit code with even parity will be 00101110. the ASCII code for R is 1010010. JAIN = 11011001 01001011 11010111 01001011 11010001 11000001 11001001 11010101 (c) Write the 6bit internal code for each character (See Table 2. Therefore. JAIN = 1010010 0101110 1010000 0101110 1001010 1000001 1001001 1001110 (b) Write the 8bit EBCDIC code for each character (See Table 2.
6. 25 = 32 and 26 = 64. the result is positive (d) If the MSB of the sum is 1.18 Consider the following examples: (i) 7 0111 Þ 0111 –3 –0011 + 1100 (1’s complement) 4 10011 1 EndAround Carry (EAC) 0100 = 4 (ii) 3 0011 Þ 0011 –7 – 0111 + 1000 (1’s complement) –4 1011 = –4 in 1’s complement form From the above examples the rules of subtraction can be summarized as: (a) Add ones complement of the subtrahend to the minuend. R = 11010010 = D2 H and l = 00101110 = 2EH for even parity and R = 01010010 = 52H and l = 10101110 = AEH for odd parity.3.20 132 ´ 7 bits. 8bit ASCII code for R with odd parity is 01010010 (b) Repeat part (a) for EBCDIC code.19 100 ´ 20 ´ 8 bits. (b) Repeat part (a) for EBCDIC code.7 requires p1 = 1 odd parity for 2. For example. therefore. 2.16 (a) Since. if binary to hexadecimal conversion is used.5.6. (b) If a carry is produced. 2. add endaround carry (EAC) (c) If the MSB of the sum is 0. 8 bits are required to encode 130 elements of information. the resulting format will be hexadecimal.
Decimal digit 9 Position BCD odd parity for 1.5.15 (a) Attach 0 or 1 as MSB to make the number of ones odd. For example. 2. 2. 2.In a similar way parity bit can be attached to every character. the result is negative and it is in one’s complement format.7 requires p2 = 1 odd parity for 4.21 Let us consider the BCD code for 9 and find out its Hamming code for error correction.7 requires p3 = 1 ® 1 p1 : : : 1 : 1 : 1 2 p2 : : : : : 1 : 1 18 Hamming Code 3 4 5 n1 p3 n2 1 : : 1 : 1 : 1 : : : : : : : 0 0 : : 0 : 0 : 0 6 n3 0 : : 0 : 0 : 0 7 n4 1 : : 1 : 1 : 1
. the minimum number of bits required to encode 56 elements of information is 6.3. 2.17 In the 8 bit ASCII code with the parity bit. 2. (b) 27 < 130 < 28 Therefore.
Decimal digit 0 1 2 3 4 5 6 7 8 9 Position ® 1 p1 1 0 1 0 0 1 0 1 0 1 2 p2 1 0 0 1 1 0 0 1 0 1 Hamming code 3 4 5 n1 p3 n2 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 6 n3 0 0 1 1 0 0 1 1 0 0 7 n4 0 1 0 1 0 1 0 1 0 1
19
. Hamming code is determined for each BCD digit and the complete sequence is given below. Similarly. Hamming code for decimal digit 9 is 1 1 1 0 0 0 1.Therefore.
232 mA Percent change =
5. (b) All the covalent bonds are intact at 0 K and hence there are no free charge carriers. we obtain I1 » I0 exp (700/hVT) and \ or (b) I2 » I0 exp (750/hVT) I2/I1 = exp (50/2 ´ 26) = 2. i. whereas in a metal an increase in the temperature results in a greater thermal motion of the ions.2)
From Eqs. 3.6%
3.616 ´ 2 = 5. This results in a decrease in the mobility and hence resistivity increases with temperature. (3.3 From the V–I relation of the diode. and hence decreases the mean free path of the free electrons. we obtain
and
» I0 exp (V1/hVT) I2 = 2I1 » I0 exp (V2/hVT)
I1 2 = exp (V2 – V1/hVT)
(3.2). V2 = 700 + 36 = 736 mV Percentage change =
736 − 700 × 100% 700
or (b)
= 5.693 mV » 36 mV Since. V1 = 700 mV Therefore.1) (3. whereas at room temperature some of the covalent bonds break away resulting in small conductivity. which decreases the resistivity of the semiconductor material..1) and (3.2 (a) Using the VI relation of the diode.4
I2 = 10 = e {(V2 – V1)/2 ´ 26} I1
or V2 – V1 = 52 1n 10 = 119.CHAPTER 3
3.1 (a) The number of covalent bonds breaking away increases with temperature.616 I2 = 2.5 (a) The circuit will be under steadystate at t = 20ms.
dQ =0 dt
20
. V2 – V1 = hVT 1n 2 = 2 ´ 26 ´ 0.e.73 mV
3.14% 3. 232 − 2 × 100% 2 = 161.
∴ I1 ≈
Since. 5 × 10 −3 dt τ IR ≈
Solving this with initial condition Q(0) = 10–9 C (part (a)).
VR = 5 = 0.099 ms (c) The various waveforms are given below. we obtain Q = – 0.5 mA Excess Q Minority Charge 0 0 t 1.7V 0 5V Id 1 mA 0 0. 5 mA R 10 The differential equation is dQ Q + = − 0.1 ms
Vi V1 = 0V 0 V2 = 5V Vd 0. \
V1 R
=
10 = 1mA 10
Q =I t
Q = 1 ´ 10–6 ´ 10–3 = 10–9 C
(b) The diode will turn off when excess minority charge has been removed.5 ´ 10–9 e–t Set Q = 0 for cutoff \ t = 1.099 ms 21 t tR t t
tR
t
.5 ´ 10–9 + 1. The recovery time constant tR = RCO = 10 ´ 103 ´ 10 ´ 10–12 = 0.
1 ≈ 2 mA 3 The current IB remains same as in part (a). Therefore. Therefore. therefore.
⋅
6 − 0. sat RC
V BB − V BE . 3
£ 127. the transistor is conducting (i. with VCC = 6V. sat RC
or RC ≥ 10 − 0.1 mA Since IC>hFE IB. If the value of RC used is more than 4.7 kW. (b) The value of RC required for the transistor to be in saturation is given by IC = VCC − VCE .27 kW
22
. now IC < hFEIB which means the transistor is certainly operating in the saturation region. sat RB
5 − 0. the collector current IC and the base current IB are given by IC = and IB =
VCC − VCE . sat (= 0.6 (a) Since the EB junction is forwardbiased.7kW.1 V) respectively. 8 = 21 µA 200
=
hFE IB = 21 ´ 100 = 2.. Therefore.7 kW \ The value of Rc just sufficient for saturation will be 4. It may either be operating in the active region or in the saturation region. 33 mA 3
5 − 0.8 V) and VCE. the transistor will continue to be operating in the saturation region. sat RB
=
10 − 0.e. 1 = 3. 1 ³ 4. IC is flowing). 1 kW 2. Then the base and collector voltages will be VBE. Hence it is conducting in the active region. Let us assume that the transistor is operating in the saturation region. let us again assume that the transistor is operating in the saturation region. (c) The value of RB required to drive the transistor into saturation is given by IC ≤ h FE × or RB ≤ 100 ⋅
≤ h FE I B
V BB − V BE .3. 8 kW 3. sat (= 0. therefore the transistor cannot be in saturation.
the range of VBB for active region is 0. sat RB ⋅ h FE
or. we obtain. 3.1 < 100 ⋅ + 0.25 V 3. 8 2 100
< 3. hFE (min) = R ⋅ V C BB − V BE .3 3.8 For the transistor to be in saturation
VCC − VCE . 1 = 200 ⋅ 1 5 − 0. RCIC + VCE. sat + RE (IC + IB) = VBB
Substituting the values. 53 IC + 50 IB = 4.The value of RB just sufficient to drive the transistor into saturation will be 127.8
23
.25 V Therefore. 8
= 233. the transistor will be driven deeper into saturation.9 Assume the transistor to be in saturation.27 kW. cut–in £ 0. sat RC h FE
5 − 0.5 V < VBB < 3. If a smaller value of RB than the value calculated above is used. Writing KVL equations for the collector and base circuits. sat + RE (IC + IB) = VCC and RBIB + VBE.
VBB <
R B VCC − VCE . sat RC
≤
V BB − V BE . sat ⋅ + V BE .5 V (b) For active region operation
VCE − VCE . sat RC ≥ V BB − V BE .25 V (c) The range of VBB for saturation region is VBB ³ 3. sat RB
⋅ h FE
R B VCC − V CE.7 (a) For the transistor to be in the cutoff region. sat 5 − 0. the voltage VBB £VBE. sat or.
the voltage at B will change as soon as Vi changes because of the capacitive voltage divider.43 ´ 10–2 mA 3. IC = 0. given below:
C + Vi – Equivalent circuit at the transistor input B RB Ri Ci
When fast changes occur in Vi. the voltages at B change with the time constant Ci (RBRi) If a capacitor C is connected across RB. KVL for the base circuit will be [RB + (1 + hFE) RE] IB = 5 – 0. 5 µA 100
\ The minimum value of Vi required for the load transistors to be in saturation is Vi(min) = 25 ´ 10–3 ´ 10 + 0.096 mA and IB = –6.sat =
5V = 2.10 The equivalent circuit at the input of a transistor consists of input resistance Ri in parallel with the input capacitance Ci as shown in Fig. 3. Assuming VBE = 0.7 V in the active region. This helps in improving the switching speed of transistor circuit. hence the transistor is not in saturation.214 mA Since IB comes out to be negative.43 ´ 10–4 mA \ IC = hFE IB = 8.43 ´ 10–2 mA and IE » –8.8 = 1. IB = 8.2 Solving these equations.7 or.11 (a) For the load transistors IC.05 V
24
.and 50 IC + 100 IB = 4.5 mA 2 kW 2.sat = IB. 5 mA = 2.
Now. the voltage Vi = VO can be determined using the principle of superposition and is given by Vi = VO = = 3.8 V 10 kW 0. 8 mA 10
= 0. and the voltage at Y is 5 V. 8 − 0.8 V (a) (b) Vi 5 kW 0. Similarly.12 (a) When both the transistors are cutoff. (c) Assume T1 to be cutoff and T2 to be in saturation. the transistor is definitely in saturation.(b) Assuming the load transistors to be in saturation the equivalent circuit at their input will be as shown in Fig.8 5+2 5+2
(c) The base current IB1 = I B2 =
3. I B = = 0. IC = 5 = 5 mA.13 (a) Assume the transistor to be in saturation. (a).042 = 6. there is no current drawn from the supplies. Since T2 is in saturation. 042 mA 1 100 hFE IB = 150 ´ 0.3 mA 3. (b) When both the transistors are in saturation. 8 Therefore. 3. (b).
æ VCC ö the voltage at Y will be 0 V. which reduces to the circuit shown in Fig. The currents I1 and I2 will be same ç = è RC ÷ ø
and IC2 = I1 + I2. the voltage at Y is 0V.3 mA
Since IC < hFE IB.8 V
5 2 ´5+ ´ 0.
5 − 0. therefore.
25
. if T1 is in saturation and T2 is cutoff then IC1 = I1 + I2
(d) V1 0V 0V 5V 5V V2 0V 5V 0V 5V Y 5V 0V 0V 0V
It performs NOR operation.8 V
10 kW Vi 0.
075 mA Since IC < hFE ⋅ IB
Therefore. the load transistors will not remain in saturation.15 Let T1 be cutoff. I1 = (5 – 0. IC = I + I1 = 5 + 1.(b) When S1 is closed. Therefore. 3. I C = I + I1 + I2 = 5 + 2 ´ 1.7/4) = 1. RC 3.15 Now IC <hFE⋅IB
Which means the transistor no longer remains in saturation.075 mA assuming the transistor to be in saturation. If this current flows through RC of driver.075 = 7.075 = 6. Therefore. 3. if we again assume the transistor to be in saturation. the voltage at its collector will be VO = 5 – 2 ´ 103 ´ 25 ´ 100 ´ 10–6 =0 Which shows that it is not possible to have a base current of 25 mA for each of the load transistor. the transistor continues to remain in saturation. (c) When both S1 and S2 are closed. it is conducting in the active region. Therefore. Therefore.16 The effective resistance = RC  RC = 2
26
. the circuit will be as shown below:
VCC RC T1 VCC RC
T2
Now. Hence. the transistor will be operating in the active region.14 The base current required for each transistor to be in saturation is 25mA. Therefore. This requires the base current to be doubled for the transistor to remain in saturation. total base current will be 25 ´ 100 mA. the total resistance in the collector circuit of T2 is RC  RC = RC/2 which means its collector current increases.
the circuit functions as an inverter. 3. therefore. Thus. we get a load curve AB as shown below. therefore. the time constant = VDS1 = VDD – VDS2 Take various values of ID and for each ID determine VDS2 from the curve of (a). mA Load curve 4 3 2 1 0 A 0 5 10 B VGS = 5 V 4 V 3 V 2 V 1 V VDS. the VDS VS ID characteristic will be same as the characteristic for VGS = 0 in Fig.RC ⋅ CO 2 3. From this we see that when Vi = 0. V
27
. VO = 5V VO » 0V
Therefore. Since the current ID is same in both T1 and T2. and Vi = 5V. ID on the characteristic of Fig.28.
Therefore. 3. for a given value of ID.41(b).17 (a) Since VGS = 0. (b) Transistor T2 acts as load for T1. the vi characteristic of the load is that of part (a). Calculate VDS1 and locate a point corresponding to VDS1. the voltage.
ID.
we can consider
28
. The value of noise margin decreases with increased N.2V. all the transistors TA.077 0.48 mW 4. Alternatively. Therefore. the load gates are in saturation and T1 and T2 are cutoff.055 1.05 0. The current drawn from the supply. the fanout of this combination will be 10. 6 − 0.14 1.106 0.2 (a) & (b)
hFE = 10 N 5 6 7 8 9 10 VO 1. 312 mA 640
I1 + I 2 3.14V.984 hFE = 20 Noise Margin D1 0.09 1. 6 − 1.015 Load gate transistors not in saturation ’’ ’’ VO 1.04 Noise Margin D1 0.04 <1.14 1.
I1 =
VCC − VO 3.CHAPTER 4
4. TB. 14 = = 3.997 0.064
The voltage VO and noise margin D1 are given in Table.1 When the output of the driver gate is high.578 mA Average Power drawn from the supply = VCC ´ Iav = 3. each gate will be able to drive 5 gates.135 0. the load gate transistors come out of saturation.578 mW = 16.1 0. Therefore.09 1.026 0. The current drawn from the supply I2 = Average current
3.04 <1. VO = 1. (c) Fan out and noise margin increases with increase in hFE. and TD are cutoff. hence Y = Y1 = Y2 = 1 Corresponding to this. 844 mA 640 RC
when the output of the driver is low. if N > 7. Therefore.6 ´ 4.3 (a) Let us consider all the possible cases: Case I A = B = C = D = 0.17 0. T1 and/or T2 are in saturation and VO = 0. 4.055 <1. 312 = 2 2
= I av =
= 4. (d) For hFE = 10. 844 + 5. TC.22 0. 2 = 5.
the fanout is 10. The state of transistor T2
29
.1)
When the output is high. Therefore. Consequently. The transistor whose input is HIGH will be driven to saturation forcing the output voltage to LOW. which means the base current of 5 + 5 load transistors can flow through R¢C and give same output voltage corresponding to logic 1 as the output voltage of each gate individually while driving 5 load gates. Case II At least one of the inputs of each gate P and Q are HIGH.844 ´ 2 mA Similarly. the current drawn from the supply is IH = 3. the timeconstant will be
æ RC RB ç 2 + N è
ö ÷ × (2 CO + NCi ) ø
(see Prob.96 mW 4.equivalent collector resistance R¢C = RC  RC = RC/2. Case IV A = B = 0 and at least one of the inputs to gate Q is LOW. the propagation delay timeconstant for a single driver (without wiredlogic) is
RB æ ç RC + N è
ö ÷ × ( CO + NCi ) ø
where. there is no problem of fanout.6 ´ 9.156 mW = 32. This will drive the corresponding transistors into saturation and consequently Y = Y1 = Y2 will be LOW and hence the load transistors will be cutoff. This will lead to a situation similar to that of Case III. for low output IL = 5. With load gates.312 ´ 2 mA \ Iav = 9. Case III At least one of the inputs to gate P is HIGH and C = D = 0. (b) Without load gates. Therefore.4 (a) This circuit has active pullup (consisting of T2 and 100 W resistor) instead of passive pullup RC used in normal RTL gates. 4. the propagation delay timeconstant
=
RC ⋅ 2C O 2
= RC ⋅ CO which is same as the propagation delay timeconstant of a single gate. RB is the resistance in the base circuit of a load gate.156 mA Power drawn from the supply = 3. With wireANDing. N is the number of load gates. Y = Y1 = Y2 will be LOW and this situation is similar to that of Case II. Ci is the input capacitance of a load gate.
(b) If it is driving N load gates. i. T2 is in saturation (since T1 is cutoff) and viceversa.8 . N ³ 3 since N is an integer. The output voltage VO will be HIGH.6 . sat − or IB =
450 I – VBE.e.6 ´ç ê2 ÷ ú ³ 100 + 450/ N 1090 ê N è 100 + 450/ N ø ú ë û
From the above equation.
VCC(3. Prob. when the input Vi is HIGH.8 V Equivalent input circuit of load gates
Fig.6 2. 4.0. sat − V BE. Therefore.6 V)
640 W 450 W IB
100 W T2 IO 450 W/N P VBE.IB ³ IO \
öù 30 é 450 æ 2. sat = 0 N O
öù 450 æ 2. Prob..6 1 é ê 3. 2 − 0. 8 100 + 450 / N 2. sat » 0. while T2 is cutoff and VO = VCE. if T3 is cutoff. T3 will be in saturation. Therefore. 4.will always be opposite to that of T3. 6 100 + 450 / N
= =
Writing KVL for the closed path P. we obtain VCC – 1090 IB – VBE. we obtain N ³ 2.4(a).0.5.8 ç 100 + 450/ N ÷ ú 1090 ê N è øú ë û
For T2 to be in saturation hFE. the output circuit corresponding to HIGH state will be as shown in Fig. T2 is in saturation and T3 is cutoff.4(a)
IO =
VCC − VCE .sat » 0 V. sat 100 + 450 / N 3. When Vi is LOW.
30
. 6 − 0.
but the noise margin D0 will be reduced from 0. . = IN.
5 − 1. 2 100
= 32 mA
VCC = 3. which means N can be taken as 70. 4. 2 − 0 . whereas T2A and T3B are cutoff. 6 = N ⋅ I1 100 + 450 / N
The values of I1 for various values of N are given in Table Table
N1 30 40 50 60 70 I1 (mA) 750 585 480 403 349
The base current required for saturation for a normal RTL is about 300 mA. 7 mA 5 and IB = 0. 6 − 0. Prob. Neglecting the base currents IE2B = I C 3 A =
3.7 = 1.54 mA This will increase the fanout to 17.Since. ∴ I1 =
31
. 4. I1 = I2 = .8 V to 0. .8 + 0. which is very large. IO =
2.2 V. (c) The relevant portion of the circuit is shown in Fig.16 = 0. Here T3A and T2B are in saturation.5 (a) When all the inputs are HIGH the voltage at the point P will be Vp = 0. 5 = 0.4(b)
4.4(b). Prob. Therefore.6 V
100 W T2A IC3A A = 1 T3A T3B T2B
100 W
IE2B B = 0
Fig.5 volts.7 – 0.
7 The Fig.7 ´ 3 = 2. Prob. but the noise margin D0 will be increased to 1. and IB = 0.82 ´ 10 + 2.7 shows the relevant portion of the circuit.sat » 0. the collector current of T1 is given by. N¢ IL + MI¢1 where.6 For a fanout of 10.82 mA Assuming T1 to be in saturation. which means the input diodes of all the load gates driven from this combination are conducting. N¢ is the fanout with the wireANDed connection. Prob.2 V. This collector current must be same as the collector current of the single gate driving N gates which is given by NIL + I¢1 \ NIL + I¢1 = N¢IL + MI¢1
VCC(5 V) I¢1 RC T1 Y1 Y P1 IL VCC(5 V) R
VCC RC T2 I¢1 Y2
IL P2
VCC R
VCC RC TM I¢1 YM
IL
VCC R PN¢
M Gates wireANDed Fig. The worst condition corresponds to the situation when the output transistor of one of the driving gates is in saturation and all others are cutoff. 0. 4.8 + 0.4 V. Corresponding to this the output voltage at Y is VCE.26 mA This will reduce the fanout to 6.182 = hFE ´ 0.42 mA. 4.9 V \ I1 = 0. 4. Assuming all the other inputs of load gates to be HIGH.(b) In this case VP = 0.4 or hFE » 26 4.7 32
N¢ Load gates
. IL = 0.
VCC – VP = R1I1 + R2IB1 Also I1 = (1 + hFE) IB1 IB1 =
5 − 2. 182 0.or
N¢ = N – (M – 1) I¢1/IL = N – (M – 1) 2. the assumption that T1 is in saturation is inconsistent.8 = 1.9 If any input is LOW. If all the inputs are HIGH.9 V. Hence Y = 0.8 + 0.7 V Since the voltage at P is higher than the voltage at the collector of T1. sat = 1. 75 × 31 + 2 V BE 2 .2 V Here. This shows that the circuit operates as a NAND gate.543 – 0. sat = 0. sat 5
= 0. 4. the voltage drop across R2 will reversebias the CB junction of T1 and therefore T1 will definitely be operating in active region. 2 = 1.sat R1 + R 2
=
\
5 − 0.8 When all the inputs are HIGH.543 mA. I2 =
IB2 = I1 – I2 = 1.7 + 0. In fact when T1 is conducting. T1 will be in active region and T2 in saturation region. If we assume that the transistor T1 is in saturation. 093 mA 1. D2. VBE has been assumed to be 0. 82 = N – 2. therefore.7 V in active region. (a) When all the inputs are HIGH. sat + VD + VBE.
and
I1 = 1. which keeps T1. VP = 0.7 + 0. Therefore.3 V The voltage at the collector of T1 = VCE. sat = 0. 78 µA 1. the input diodes are nonconducting.383 mA Standard load =
VCC − V D − VCE. Hence T1 is in active region.182 RC
33
IC2 = N ⋅ I L +
. IB1 cannot exist.16 = 1.7 + 0. 2 × 10 3 = 49. the corresponding input diode conducts and therefore. Hence Y = 1.2 + 0. VP = VBE1 + VD + VBE3.7 + 0.16 mA. 75 + 2 VCC − VCE . the input diodes will be nonconducting.8 = 2.8 = 2. sat = 0. sat + VD + VBE. 7 − 0. 093 N + 2. then VP = VBE.66 (M – 1)
4. and T2 cutoff.
(b) Noise margins D1 = 0. T1 will be conducting in active region. VCC – VP = R1 (1 + hFE) IB1 + R2 IB1
34
.6) = – 3. sat = 0. active + VZ + VBE. VP = 8. IC2 £ hFE IB2 or.4 V.5 – 0. 1. the power P (1) = I1 ´ Vcc = 1.4 V The 1 level noise margin = D1 = Vg + VZ + Vg – VP = 0.9 V Corresponding to this T1 and T2 will be nonconducting.2 V (b) When all the inputs are HIGH.6)] = – 7.465 mW The average power Pav =
= P ( 0 ) + P (1) 2 18. the power P (0) = (I1 + I¢1) VCC = (1. VP = VBE.6 + 0. 625 + 5.12.8 = 8.182) ´ 5 = 18. the fanout of this gate is 35 which is much higher than the fanout of the DTL gate of Fig.10 (a) When at least one of the inputs is LOW. 465 = 12 .5 + 0. Therefore. 045 mW 2
4. Writing KVL from VCC to VP.093 N + 2.625 mW When the output is HIGH.9 =7V The 0 level noise margin = D0 = – [V (1) – (VP – VDg)] = – [15 – (8.7 = 0.7 + 6.4 V (c) When the output is LOW.9 + 0.383 or.9 = 0.For T2 to be in saturation. Zener will be in the breakdown region and T2 in saturation.5 + 6.2 + 0.182 £ 30 ´ 1. VP = V (0) + VD = 0. When all the inputs are HIGH. 4.7 V D0 = –V(1) + (VP – VDg) = – 5 + (2.5 – 0. N < 36 Therefore.093 ´ 5 = 5.4 – 0.2 – 0.9 + 0.543 + 2.
therefore.or. 4 = R1 (1 + h FE ) + R 2 3 ( 41) + 12
= 0. Basecollector junction of T1 is forwardbiased T2 and T3 are in saturation.13 (a) When the output is LOW. therefore. Hence the temperature sensitivity of the HTL gate is significantly better than that of the DTL gate. The input diode and the baseemitter junction of T1 are in polarity opposition.9867 + 0.16 = 1.12 The noise margins depend upon temperature because the voltage across a conducting diode and VBE are temperature dependent.8 = 2. Therefore.9867 mA N¢ = N – (M – 1) I¢1/IL = N – 1. the temperature sensitivities of these two junctions cancel. Since the temperature sensitivity of a Zener diode is positive whereas for a forwardbiased diode it is negative.03 (M – 1) 4.48 mW 4. Therefore.004 – 0. 3 = 0 .94 mA.8 + 0.95 mA \ IC2 = 0.
IB1 =
VCC − V P 15 − 8.004 + 0.2 = 1V Current through RC2 =
5 −1 = 2. (c) N £ 76 P(0) = (I1 + I¢1) ´ VCC = (2. VB1 = 0. 4
35
. 857 mA 1. I¢1 = 0.0489 = 2.86 mW P(1) = I1 ´ VCC = 0. I1 = 41 ´ 0. the temperature sensitivities of Z and the baseemitter junction of T2 cancel (their magnitudes are of the same order).844 or. the temperature sensitivity of the circuit depends on the temperature sensitivities of D2 and the baseemitter junction of T2. 8 = 0.7 + 0.3 V Current through RB1 =
5 − 2.8 + 0.94 ´ 15 = 14. 9867 mA 15 The load current IL = 0. 675 mA 4
VC2 = 0. In HTL.004 mA \ IB2 = I1 – I2 = 2.0489 mA The current through Zener diode.9867) ´ 15 = 44. D2 is replaced by the Zener diode.11 IL = 0.844 mA The current through RC = 14.1 mW \ Pav = 29.95 N £ 40 ´ 1. 4.
both T3 and T4 will be conducting simultaneously for some time which will cause almost short circuiting of the VCC supply. This means T4 will be in saturation and its collector current would be IC4 =
VCC − VCE 4 . The base current and the collector current of T4 will become IB4 =
= VCC − V BE 4 .385 mA 4. the change in output from logic 0 to logic 1 will be faster. 4. therefore. 4. T4 and D are cutoff. IC4 = 0 Therefore. the shorting of output to ground will not have any effect.025 + 41.7 = 0. 4. 7 = 2. 9 4
= 1.2 + 0. Prob.15 (a) If RC4 = 0.8 V if the diode D is not present. (c) (i) When output is in LOW state. 8 − 0.025 mA (c) The total current will be sum of current through RB1 (as given in (b) part above) and given in Eqs. sat 100 5 − 0. 2 = 46 mA 100
=
which is very large and will increase significantly the power dissipation. \ VB1 = 0.10 and 4. 2 − 0. Since T3 does not turn off (because of storage time) as quickly as T4 turns on. T3 and T4 are cutoff \ ICC1 = Current through RB1 =
5 − 0. sat − VCE 3.11 = 1.sat − V D RC 2 5 − 0 . 5 mA 1. it is simply a wastage of power. (ii) When output is in HIGH state. therefore. Moreover.857 = 3.532 mA (b) At least one of the inputs is LOW.675 + 2. VB4 = 1 V which makes VBE4 = 0. 4
36
.36 = 42.15.14 The current I remains same and it does not affect the fanout of the gate G1. ICC(0) = 0.Since. (b) When the output is in LOW state.9 T2. the relevant portion of the circuit with output shorted to ground is shown in Fig.
The corresponding current drawn from the power supply will be IC4 + IB4 = 41.4 mA.16 Let the output transistor T3 of one gate is in saturation. 44 kW I OL + 8 I IL 16 − 8 × 1. 4. (i) When the output Y = 1. VCC – (5 IOH + 6 IIH) RC ³ VOH
37
.56 kW 4.and
IC4 =
VCC − VCE 4 . 4.15
4. The voltage at Y will be LOW. Prob. 4 = = 1. 4.5 mA
This large current will continuously be drawn from the supply as long as at least one of the inputs is LOW.4 kW T4 IB4 C2 E2 C3 D Is IC4
E3
Fig.5 = 43. Prob. 2 − 0. 7 = 41 mA 100
=
\
Is = IC4 + IB4 = 41 + 2.sat − V D RC 4 5 − 0. This continuous current will damage these transistors. 6
= 4. 1. 4.
VCC = 5V RC4 = 100 kW RC2 = 1. RC(max) =
VCC − VOH (5 − 2.56 kW RC(min) =
Therefore.18. the currents drawn from the supply will be same as the currents without this connection. When both the outputs are HIGH or LOW.17 The circuit is shown in Fig.17. which will make the transistor T4 of the gate whose T3 is cutoff to conduct through T3 of the other gate which is in saturation.44kW < RC < 4. 4) × 10 3 kW = I OH + 8 I IH 250 + 8 × 40
VCC − VOL 5 − 0.18 The relevant portion of the circuit is given in Fig. while that of the other gate is cutoff. Prob. This will damage the transistor T4 and the diode D.
4 ) × 10 3 kW = 1.17 VCC = 5 V IOL IOH IOH IOH IOH IOH Fig.which gives RC(max) =
VCC − VOH ( 5 − 2 .18 38 RC
Load gates
IIH IIL IIH IIL IIH IIL IIH IIL IIH IIL IIH IIL
Y
. 74 kW = 5 I OH + 6 I IH 5 × 250 + 6 × 40
VCC = +5 V RC IIH IOH
Output circuit of opencollector gate
Fig. 4. Prob. Prob. 4.
159 kW 40 − 7 × 1. 72 kW 16 − 6 × 1. 6
and
Therefore. 4. 4 ≈ 0. 30 A Lamp
7407
Fig. it is assumed that only one of the driving gates has its output transistor in saturation while the output transistors of all the other gates are cutoff. (i) ALS driving standard devices IOH (ALS) = – 400 mA IOL (ALS) = 8 mA (74 series) IIH (Standard) = 40 mA IIL (Standard) = – 1. 4. 0.(ii) When the output Y = 0.
VCC − VOL £ IOL + NIIL RC
which gives RC(min) =
VCC − VOL I OL + NI IL 5 − 0. A value of RC = 1 kW is reasonable.159kW < RC < 1.19 Let us assume a supply voltage VCC = + 5V and corresponding VOH = 2.74 kW. Prob.72 kW and 1. which means a lamp load along with the necessary supply voltage may be connected as shown in Fig. 4 ≈ 0.4 V \ RC(max) = RC(min) =
( 5 − 2. 6
=
Therefore. RC should be between 0.20. 4.21 Let us take ALS devices driving other devices.28 kW 4. 28 kW 7 × 250 + 7 × 40 5 − 0. 4 ) × 10 3 ≈ 1.20 (a) No (b) No (c) No
VCC = +5 V A
(d) Yes
VCC = +10 V 10 V.20
7407 is an opencollector noninverting buffer with VOH = 30V (maximum). Prob. 4.6 mA
39
.
(a) The noise voltage at the collector of T2 = the noise voltage at the base of T4.002 Vn Therefore. if the terminal P is grounded. the complete table can be verified. Prob.22 Case I Let T2 be cutoff. 4. we obtain (a) VYQ =
R E 4 (1 + h FE ) V R C 2 + (1 + h FE ) R E 4 n
1. Then the output circuit will appear as shown in Fig.797 Vn (b) VYP = – (Vn – 0. whereas it is 10 when the output is HIGH. 1.Here. 5) n = 0.22(a). Prob. Prob. the fanout is 20. Case II Let T2 be conducting and T1 be cutoff. the noise voltage present in the output is negligibly small. Therefore. the fanout is 5 (ii) ALS driving ALS IIH (ALS) = 20 mA IIL (ALS) = – 0. whose equivalent circuit is shown in Fig. 3 Since T4 is operating as an emitterfollower.
P RC2 T4 Vn RE4 Q (a) Fig. Similarly.22 (b) Y Vn RC2 B4 I E4 RE4 Q C4 hFE I Y P
From the equivalent circuit. when the output is LOW.1 mA Which gives a fanout of 20 when the output is HIGH and 80 when it is LOW. therefore. 4. Therefore. VYQ = 0.18 + 0. and
– IOH (ALS) = 10 ´ IIH (Standard) – IOL (ALS) = 5 ´ IIL (Standard)
This means. 797 Vn . 5 (101) V 0. = 1. 4.998 Vn =
(b) VYP = – (Vn – VYQ) = – 0. 4. 3 + (101) (1.203 Vn
40
.18 Vn = 0. the fanout is 5.797 Vn) = – 0.22(b).
Also 5.25
5. Prob. 4.7V VOL ECL (a) Output logic level voltages of ECL
TTL (c) Input logic level voltages of TTL
.26
2. input/output logic levels of MC10H125 IC.75 V) T4
RC2
RE4
Fig.e. it can be proved for all the other cases. Prob. Corresponding to this T4 of G1 is acting as an emitter follower while that of G2 is acting as a diode. 4. In this when Y1 and Y2 are connected together.55 V) 5. Prob. Similarly. Similarly. The relevant portions of the circuits are shown in Fig.26 41
–1.2 V supply voltage will appear across the output transistor T4 or T3.25. Consequently T4 goes to cutoff.5V –0. (b) The 5. Therefore.2 V supply gets applied to their bases through RC2 and RC1 respectively. when Y1 = 1 and Y2 = 0 identical situation will prevail making the output 1. This confirms that OR operation is performed when the outputs are connected in wired logic.This again shows that the noise voltage is very small between Y and P and hence the terminal P is grounded.2 V
4.9V VOH VOH 2V 0.26 The output logic levels of ECL.2 V supply will appear across RE4 or RE3 and no damage is caused to the supply and the circuit. Prob..5V VOL –1.2 V Y2 (0. When Y1 and Y2 both are same. and E = 0 Therefore. a current spike of 41.4 mA is produced. Y1 = 0 and Y2 = 1.75 V (i. the output will be equal to Y1 = Y2.25 Let A = B = C = 0. 4. the output transistor will burn out. 4.85 V) T4 Y1 RE4 (1. 4.24 In a TTL gate. 4. whereas in the case of ECL the change in current is negligibly small when the output changes from LOW to HIGH and viceversa.
VCC = 0 VCC = 0
RC2 (0.8 VIH VIL
0. the voltage across T4 acting as a diode). when the output changes from V(0) to V(1). D = 1.13V VIH –1. the voltage at the output terminal will be equal to – 0. 4. and the input logic levels of TTL are shown in Fig.23 (a) The 5.48V VIL MC10H125 Translator (b) Input/output logic level voltages of Translator Fig.
4. 4. VIH (Translator) < VOH (ECL) VIL (Translator) > VOL (ECL) which shows that the input of MC10H125 IC is ECL compatible. If the output accidently gets shorted.27 The output Y of ECL NOR gate is Y = A + B The output of the Translator circuit is Y and the output of TTL Inverter will be Y = Y.From the logic levels. 4. T1 is cutoff.29 Its operation is given below
Inputs A 0 0 VCC VCC B 0 VCC 0 VCC T1 OFF ON OFF ON State of T2 OFF OFF ON ON T3 ON OFF ON OFF T4 ON ON OFF OFF Output Y VCC 0 0 0
42
. since T2 is not meant to carry such large currents.27
Y
TTL
The complete circuit is shown in the above figure. large current from VDD will continuously flow through the load transistor T2 which may damage the load transistor. it does not cause any problem. 4. 3. Now if the output gets shorted to ground. we observe. VIH (TTL) < VOH (Translator) VIL (TTL) > VOL (Translator) which shows that the output of the translator is compatible with TTL. The normal current through T1 and T2 is extremely small being the OFF current of either T1 or T2. (b) Consider the CMOS inverter of Fig. and if the output gets shorted to ground. This will cause a relatively very high current to flow through T2 which may damage it. the output voltage is LOW (» 0V). Similarly. A B ECL Y Y MC10H125 Translator
Fig. 4. When T1 is ON.25. Prob.33. On the other hand when Vi is LOW. whole of VCC will appear across T2 which is conducting.28 (a) Consider the NMOS inverters shown in Fig.
37V VIL 2V 0.
TTL/CMOS 54/74 54H/74H 54L/74L 54S/74S 54LS/74LS 54AS/74AS 54ALS/74ALS 74HC 400 500 200 1000 4000 2000 400 74HCT 400 500 200 1000 4000 2000 400 74AC 400 500 200 1000 4000 2000 400 74ACT 400 500 200 1000 4000 2000 400
4.34. CMOStoECL interfacing is possible using TTLtoECL translator.8V
CMOS (a)
MC10H124 translator (b) Fig.31
54/74 (a) 74HC/74HCT (b) 74 AC/74 ACT 2 15 54H/74H 2 12 54L/ 74L 21 133 54S/ 74S 2 12 54LS/ 74LS 11 66 54AS/ 54ALS/ 74AS 74ALS 8 48 40 240
4. maximum possible number of ALS gates which can be driven is 140.76V VIH VOL 0. VIH (Translator) < VOH (CMOS) VIL (Translator) > VOL (CMOS) which shows that the input of the translator is compatible with CMOS. Prob.
VOH 3.34 The output logic levels of MC10H125 translator and the input logic levels of CMOS (74HCT & 74 ACT) are shown in Fig. The remaining 14 mA of current can drive 140 74ALS gates. Therefore.33 The output logic levels of CMOS and the input logic levels of MC10H124 TTLtoECL translator are given in Fig.33
From these logic levels. we observe.32 When output is HIGH.30 The fanout is given below. it can drive 20 74AS gates requiring 10 mA of current. therefore. Since the output of the translator is compatible with ECL. 4. 4. When output is LOW. Prob.33.4. 4. 4. Prob. it can drive a total of up to 1200 gates.
43
. 4.
ECLtoCMOS interfacing is possible.VOH
2. Since the input of the translator is compatible with ECL. a resistance R and VCC are required to be connected to pull up the voltage at P corresponding to VOH (Translator) VCC R P MC10H125 Translator (c)
Fig. VIL (CMOS) > VOL Translator but VIH (CMOS) < VOH (Translator) Therefore. therefore. 4.5V
VOL
MC10H125 Translator (a)
CMOS (74HCT & 74ACT) (b)
Fig. Prob.5V VIH = 3.34
CMOS
44
. we observe.5V For these CMOS ICs.34
From these logic levels. 4. and 74 AC series VIL = 1.5V VIH 2V 0. For CMOS 74 HC. Prob. VIH (CMOS) < VOH (Translator) VIL (CMOS) > VOL (Translator) Therefore.35V VIH = 3.8V VIL 0.85V and for CMOS 74 C series VIL = 1. the output of the translator is compatible with these CMOS devices.
1 Let S1 and S2 be the two switches. 5. 5.2 (a) A 0 0 0 0 0 0 0 B 0 0 0 0 1 1 1 Inputs C 0 0 1 1 0 0 1 45 D 0 1 0 1 0 1 0 Output f 0 0 0 0 0 1 1 (Contd. Prob. Prob. The resulting circuit will be NANDNAND realization.CHAPTER 5
5.)
. The circuit diagram of the system is shown in Fig. 5. 5.1(b):
S1 S2 L
Fig. Prob. Prob.1(b)
(d) Replace each of the AND gates and the OR gate in the above figure by NAND gates.1(a)
Bulb
(a) The truth table is given below:
S1 0 0 1 1 S2 0 1 0 1 L 0 1 1 0
(b) The logic equation is L = S 1 S2 + S1 S 2 (c) The ANDOR realization is given in Fig.1(a):
0 S1 1 L 0 S2 ON = 1 OFF = 0
1
Supply Fig.
5.
(Contd. Prob. Prob. 5. Prob.3 (a) f1 = (A + B + C + D ) ( A + B + C + D) ( A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) ( A + B + C + D) ( A + B + C + D ) f2 = (A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (b) The Kmaps for f1 and f2 are given in Fig. The simplified expression is f = BC + BD
CD AB 00 00 01 11 10 1 1 1 (a) Fig.3 46 0 01 0 11 0 0 10 0 CD AB 00 00 01 11 10 0 0 0 0 0 0 (b) 0 0 0 01 11 10
. Prob. 5.2.3(a) and (b) respectively.) Inputs A 0 1 1 1 1 1 1 1 1 B 1 0 0 0 0 1 1 1 1 C 1 0 0 1 1 0 0 1 1 D 1 0 1 0 1 0 1 0 1 Output f 1 0 0 0 0 0 1 1 1
(b) The Kmap is given in Fig. The minimized expressions are:
CD AB 00 00 01 11 10 0 0 0 0 (a) Fig. 5.2 1 1 B 1 BC D (b) BD 01 11 10 B C f
5. 5.
5. 5. 5. Prob. Prob. 5.4 (a)
A B C D
B C
B D
A D
f
A B
Fig.3(c) and (d) for f1 and f2 respectively.
B C D
A
C
A B f1 B f2
A B C
A B D
A B D A B C
D A C D
Fig.3
(c)
(d)
(d) Replace all the AND and OR gates in figures (A) and (B) by NOR gates to obtain realizations using only NOR gates. Prob.f1 = ( B + C + D) ( A + B + C) ( A + B + D) (A + B + D ) (A + B + C ) f2 = (A + C ) (A + B) ( A + C + D ) (B + D ) (c) The ORAND realizations are shown in Fig.4(a)
47
.
5. Prob. Prob.4(b)
(c) Realization for (a) requires 7400 – 1 7420 – 1/2 7430 – 1 a total of three chips.5 48
. Realization for (b) requires 7427 – 1 74260 – 1 a total of only two chips. 5. 5.(b)
A B C D A B C
f
A B D
A B D Fig.5 (a)
A C
A C D
7410
Y
B
(b)
A B C
A B C
B C D
Y
1/ 3 7427
7427 Fig.
8 (a) Figure Prob.7 (a)
CD
AB 00
01 11 1 1
10 1 1 1 1 A
00 01 11 10 C 1 1 1 1
1 1
Fig. 3. 8. 13. 5. 15) (c) f = A + C
A f B Fig. 5. 5. 10. 5. Prob. 7. 6.7(a)
(b) f = å m (2. Using offset adjacencies shown in the Kmap. 14. 5. Prob.7(b)
5. 9.6
5. 12.6
A
D
3/4
7402
C
D
f
B Fig. the expression for f1 can be written as f1 = (C ¤ D) (A ¤ B) + (C ⊕ D) (A ⊕ B) = (A ⊕ B) ¤ (C ⊕ D)
CD AB C D (A ¤ B) 00 01 11 10 1 1 1 1 1 1 1 1
00 01 11 10
C D (A Å B)
CD (A ¤ B) C D (A Å B)
Fig.(c) Realization of (a) requires only one chip whereas (b) requires two chips.8 (i) below gives the Kmap. Prob. 5. Prob. 11.8(i) 49
.
8(iv).9.9 Truth table of BCDtoExcess3 code converter is given below. Prob. 5.8(ii) f1
Its realization using EXOR gates is given in Fig. (b) Its Kmap is given in Fig. Prob.A B C D Logic 1 Fig. E1. 5. This realization requires only one 7486 IC chip. Prob.
BCD D 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 Excess3 E1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0
Here only ten out of sixteen combinations are used and the other six are taken as don’tcare conditions. 5. Prob. Prob. Pro. 5. The minimized expressions are: E0 = A
50
. E2 and E3 are given in Fig.
CD AB 00 00 01 11 10 1 1 1 1 (iii) 1 1 1
A
01 11 1 10
B
A B D A C D Fig. The Kmaps for the outputs E0. 5. This requires one 7410 chip and one gate of 7400 chip.8(ii).8
f2
(iv)
5.8(iii) The minimized expression is f2 = A B + AB D + ACD The realization using NAND gates is given in Fig. 5.
11(c).11(b). Prob. A = E0 B = E1 E 0 + E1 E 0 C = E 2 E 1 + E2 E1 E0 + E3 E1 E 0 D = E3 E2 + E3 E1 E0 The circuit can now be drawn using NAND gates. The Kmaps can then be prepared and minimized.10 Truth table of Excess3toBCD converter can be prepared using the truthtable of Prob. 5. and f3 can be drawn using NOR gates. 5. Prob. Prob.9. 5. The minimized expression is
f1 = C D = C + D
(b) The Kmap is shown in Fig. 5.11(a).
51
. The minimized expression is
f 3 = ( A + B + C + D ) ( B + C + D) ( A + B + C ) ( A + C + D )
The circuits for f1. 5. Prob.9
E1 = BA + B A E2 = CB A + C A + C B E3 = D + CA + CB The circuit can be drawn using NAND gates. The minimized expression is
f 2 = ( A + B + D) ( B + C + D ) ( A + C )
(c) The Kmap is shown in Fig. f2. 5.11 (a) The Kmap is shown in Fig. The minimized expressions are given below. 5.BA
DC 00 1 0 0 1
01 11 1 0 0 1 E0 (a) ´ ´ ´ ´
10 1 0 ´ ´
BA
DC 00 1 0 1 0
01 11 1 0 1 0 ´ ´ ´ ´ E1 (b)
10 1 0 ´ ´
00 01 11 10
00 01 11 10
BA
DC 00 0 1 1 1
01 11 1 0 0 0 E2 (c) ´ ´ ´ ´
10 0 1 ´ ´
BA
DC 00 0 0 0 0
01 11 0 1 1 1 ´ ´ ´ ´ E3 (d)
10 1 1 ´ ´
00 01 11 10
00 01 11 10
Fig.
Prob. Prob.
A = 0 BC DE 00 00 01 11 10
A BE
BC 10 1 DE 00 01 11 10
A = 1 AB CDE 00 1 1 1 1 1 1 1 01 11 10 1
AC E
01 11
1 1
1 1 1
ABD
BC Fig.11
5. Prob. 513(a).12 and the minimized expression is
f 1 = A BE + AC E + ABD + BC + AB CD E
This can be realized using NAND gates.CD
AB 00
01 11
10
CD
AB 00
01 11 0
10
00 01 11 10 0 0 0 0 0 0 (a) CD AB 00 0 0 0 0 0 0
00 01 11 10 0
0 0 0 (b) 0 0 0
01 11 0
10 0 0
00 01 11 10 0 0
0
(c) Fig. 5. the minimized expression for f2 is
f 2 = C E + ABD + ADE + AD E + B CE + CDE + AB E
which can be realized using NAND gates. 5.
52
.13 (a) Its Kmap is given in Fig. Similarly.12
5. Prob. 5.12 The Kmap for f1 is shown in Fig.
(a)
CD
AB 00 00 01 11 10 1 1
01 11 0 1 0 0 1 0
10
1 0 0
Fig. Prob.18 of the book and Y = C D + CD (c) Realization of part (a) requires 2 IC chips (7410) whereas for part (b) one IC chip (7400) only is required.14 (a) Figure Prob. Prob. 5.13(b)
(b) The Kmap is given in Fig. 5. f2 = A C D + BC + AB
53
(SOP)
.14(a) and (b) show the Kmaps of f1 for NAND and NOR realizations respectively. 5.13(c)
5. 5. Prob. (b) Similar to part (a). the minimized expressions are obtained which are given below. 5. The minimized expressions are f1 = ABC + CD + BD + AD (SOP) and f1 = ( A + B + C ) (C + D) ( B + D) ( A + D) (POS) Circuits using NAND and NOR gates can be designed using the above expressions.
C
D Y C
D
Fig.13(a)
The minimized expression is
Y = AC D + B C D + ACD
A C D B C D A C D
Y
Fig.
AB CD 00 01 11 10 1 1 ´ (a) Fig.14 1 ´ 1 00 01 11 10 1 1 1 CD 00 01 11 10 ´ 0 0 (b) 0 0 AB 00 0 01 0 11 0 ´ 10
5. Prob.15 Its Kmap and circuit realization are given in Fig. 5.15.
(a)
A C (B Å D)
AB CD 00 00 01 11 10 A C (B ¤ D) 1 01 11 1 1 D f1 10 1 A B
C
(b)
B 01 11 1 1 1 A 1 1 A(C Å D)
A (B Å C)
AB CD 00 00 01 11 10
10
C
A
1
1
f2
1 C D
54
.and
f2 = ( A + B ) ( B + D ) ( B + C ) ( A + C )
(POS)
These equations can be used to design circuits with NAND and NOR gates. Prob. 5.
5.15 f3
A C(B Å D)
5.16 Its truth table is given in Table Prob. 5.16
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4bit word B C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Odd parity bit PO 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 Even parity bit PE 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
The Kmap for Po is given in Fig. Prob.(c)
AB CD 00 00 01 11 10 1 1 01 11 1 1 10 A C A C (BÅD) B D Fig. 5. 5.16(a).16 55 1 0 1 0 10 0 1 0 B 1 D (b) A C Po
. 5. from which Po is obtained as Po = AC (B ¤ D) + A C (B Å D) + A C (B Å D) + AC (B ¤ D) = (A Å C) ¤ (B + D) Its realization using EXOR and EXNOR gates is given in Fig. Prob. Table Prob.16. 5.
AB CD 00 00 01 11 10 1 0 1 0 01 11 0 1 0 1 (a) Fig.16(b). Prob. Prob.
5. Its truth table is given in Table Prob. (b) The Kmap using 0’s is given in Fig. Prob. we can minimize the function using 1s which will lead to a circuit realizable by NAND gates.17 From the truthtable given in Prob.19 Let the augend. 5.18 (a) The Kmap using 1’s is given in Fig.17. 5. 5.17 (b) PE
5. These are given in Fig. addend. 5. Prob. and the carry inputs to the fulladder be An. and Cn – 1 respectively and Sn. Prob. Kmap is prepared and the circuit is designed.18(b). 5.19(a)
An 0 0 1 1 Bn 0 1 0 1 56 S1 0 1 1 0 C1 0 0 0 1
. Similarly. 5. Bn.16. PE = A ⊕ B ⊕ C ⊕ D
AB CD 00 00 01 11 10 1 (a) 1 1 1 01 11 1 1 1 10 1 A B C D Fig. The minimized expression for f1 is
f 1 = ABC D E + ABCD F + CEF + A B C DEF
The circuit for f1 can be realized using NAND gates. we can minimize using 0’s which will lead to a circuit realizable by NOR gates. and Cn be the sum and carry outputs respectively. (a) An and Bn are applied at the two inputs of first halfadder HA – 1.18(a). Table Prob.5. The minimized expression for f2 is f2 = (A + B + C + D + E + F ) ( A + B + D + E + F) ( A + B + C + E + F ) (A + C + D + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + D ) (A + B + D + E) (B + C + D + E) (B + C + D + F ) (A + B + C + D) The circuit for f2 can be realized using NOR gates. Its outputs are S1 (Sum) and C1 (Carry). Similarly. Prob. 5.19.
Prob. Prob.18(a)
0 1 CD 10 0 EF 00 01 11 10 CD 00 0 00 0 0 0 0 01 11 10 0
B
A CD 00 00 0 01 11 10 CD 00 00 1 01 11 10 0 0 0 0 0 0
EF
01 11 0 0
0
0 0
0
EF
01 11 0
10
EF
01 11
10
00 0 01 11 10 Fig.B
A CD 00 00 0 01 11 10 1
0 CD 00
1
EF
01 11
10
EF
01 11
10
00 1 1 01 11 10 1 1
AB CDEF
CD 00 00 1 01 11 10 1 1 1 1 1
CEF
01 11 10 EF
CD 00 01 11 10 00 01 11 10 1 1
EF
ABC D E
ABCDF Fig.18(b) 57
. 5. 5.
C1. 5. Prob 5.19(b)
C1 0 0 1 0 0 1 S1 0 1 0 0 1 0 Cn – 1 0 0 0 1 1 1 Cn 0 0 1 0 1 1 Sn 0 1 0 1 0 1
Kmaps for Cn and Sn are shown below: Cn – 1
C 1 S1 00 0 1 0 0 01 0 1 11 ´ ´ 10 1 1 Cn – 1 C1 S1 00 0 1 0 1
01 1 0
11 ´ ´
10 0 1
Kmap for Cn
Kmap for Sn
Cn = C1 + S1 × Cn – 1 Sn = S1 C n .1 + S 1 Cn – 1 = C1 + C2 = S1 Å Cn – 1 Sn and Cn are generated using HA –2 and an OR gate as shown in the block diagram.An
Bn
Cn – 1
HA – 1 C1
S1 HA – 2 C2
S2 = Sn
Cn
Fig.
58
. and Cn – 1 is given below: Table Prob.19(a)
Truth table of the fulladder using input variables S1.
Since the propagation delay time (tpd) of AND–1 is less than the tpd of EXOR(1). 5. 8. D) = p M(2. 11. 9. 5. 15) Table (a)
Group 0 1
Grouping of minterms according to number of 1’s.(b)
An Bn
EX–OR(1)
S1
EX–OR(2) S2 = Sn C2
C1 AND2 AND–1 Cn–1 Fig. 5. B. Propagation dealy time for Cn = tpd [EXOR(1) + tpd (AND2) + tpd(OR) = 20 + 10 + 10 = 40 ns.19(b) OR Cn
5. therefore. C. 7. 6. 3. 1. 12) = S m (0. 1 0.
A 0 1 4 3 5 6 11 13 14 15 0 0 0 0 0 0 1 1 1 1 Variables B C D 0 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 Check for inclusion in groups of 2 ü ü ü ü ü ü ü ü ü ü
Minterm
2
3 4
Table (b)
Group 0 Minterms A 0. 14. Prob. 4. 10. 13.20 Propagation delay time for Sn = tpd [EXOR(1)] + tpd [EX –OR(2)] = 20 + 20 = 40 ns.) 59
0 — — 0
.21 f (A. 3 1. it is not counted. 4 1. 5 0 0 0 0
Grouping of two minterms
Variables Check for inclusion B C D in groups of 4 0 — 0 0 — 0 1 1 ü ü ü (Contd.
(Contd. 11 BC Dü 5. 1. 14 ACD ü 11. we see that the column for minterms 0 contains only one ´. starting from the primeimplicant A B D.) Group 1 Minterms A 4. A C is an essential primeimplicant.5 4. therefore. 4. All the other columns contain 2 or more Xs. the minimized function is f (A. Therefore. 15 0 0 — — — 1 1 1 Variables Check for inclusion B C D in group of 4 1 1 0 1 1 — 1 1 0 — 1 0 1 1 — 1 — 0 1 1 0 1 1 — ü
2
3
Table (c) Grouping of 4 minterms
Group 0 Minterms A 0. 5 0. 6 A B Dü B CDü 3. 6 3. 15 13. 4. 15 ABC 14. Depending upon the primeimplicants selected above. 15 14. 15 ü
ü
ü ü ü ü ü
From the PI table. 1. 5 Ä AC ü 1. 14 11.
60
.13 BC D ü 6. 3 AB Dü 4. C. 11 5. we see the minterms that are covered by each primeimplicant and find the minimum number of primeimplicants that will cover all the minterms.13 6. 5 0 0 Variables B C — — 0 0 D — —
Table (d) PI table
PI terms Decimal numbers 0 1 ´ ´ 3 ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ Minterms 4 5 6 11 13 14 15 ´ ´
0. 15 ABD 13. D) = AC + ABD + ABD + B CD + BC D + BCD + ACD There can be other options also. 4. B. 1.
D) = Sm (1. 9. and AD from Table (c) and AB C and AB C from Table (b). CD.5. 5. 11. 13* 9. 13* 11. 9. 9. 13*. 3. B.
61
.
Group Minterm/ don’t care term 1 2* 8 3 5 9 11 13* 15 A 0 0 1 0 0 1 1 1 1 Variables B C 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 1 D 1 0 0 1 1 1 1 1 1 Check for inclusion in group of 2 ü ü ü ü ü ü ü ü ü
1
2
3 4
Table (b)
Group
Grouping of 2 minterms/don’t care terms
A 0 0 — 0 1 — — 1 1 1 1 Variables B C 0 — 0 0 0 0 1 0 — — 1 — 0 0 1 0 1 0 — 0 1 — D 1 1 1 — — 1 1 1 1 1 1 Check for inclusion in group of 4 ü ü ü
Minterms/ don’t care terms 1. 3. 9 3. 11 9. 3. 11.22 f (A. 5 1. 3 1. 15 9. C. 11 1. 8. 9. 15 A — — — — 1 1 Variables B C 0 — 0 — — — — 0 — 0 — — D 1 1 1 1 1 1
1
2
There are a total of 5 primeimplicants BD . 15
1
2 3
ü ü ü ü ü ü
Table (c)
Group
Grouping of 4 minterms/don’t care terms
Minterms/ don’t care terms 1. 13* 9. 5. 9. 15) + d(2. 11 1. 9 2*. 13) Table (a) Grouping of minterms/don’t care terms according to number of 1’s. 11. 5. 3 8. 13* 1. 11 5. 15 13. 13*.
11. and ABC . 26. Except the minterm 3 all the other minterms have heen covered by the essential primeimplicatns. 9. 5. AD. 13* ü ´ AD 9. B. E) = Sm (8. 13. 13*. 3 AB C 8. 10 0 0
Grouping of 2 minterms
B 1 1 Variables C D 0 0 0 — E — 0 Check for inclusion in group of 4 ü ü (Contd.) 62
. 15 ü ABC 2*. 21. C. B. D) = B D + C D + AD + AB C . C. 9 8. 18 .implicants are: CD. 25. D.Table (d) PI Table
PI terms Decimal numbers 1 2* Minterms/don’t care terms 3 5 8 9 11 13* ´
Ä
15
BD 1. 24. The minimized function is f (A. 27. Therefore. 9. 5. B D is to be included in the minimized expression.23 f (A. 10. 30. 15. 11. 31) Table (a)
Group 1
Grouping of minterms according to number of 1’s
A 8 16 9 10 18 24 11 13 21 25 26 15 27 30 31 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 B 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 Variables C D 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 E 0 0 1 0 0 0 1 1 1 1 0 1 1 0 1 Check for inclusion in group of 2 ü ü ü ü ü ü ü ü ü ü ü ü ü ü
Minterm
2
3
4 5
Table (b)
Group Minterms A 1 8. 16. 11 ´ CD 1. 9. 3. 9 ü
´ ´ ´
Ä ü
´ ´ ´ ´
Ä
´
´ ü ´ ü
The essential prime.
27 13. 27 26. 11 8. 18 16. 11. 11. 30 15. 25 10. 26 24. 9. 31 31 31 31 0 — 0 — — — 1 1 0 — 0 — — — 1 1 — — 1 1 B Variables C D 0 0 0 0 0 0 0 0 — 0 — 0 0 0 0 0 — — — — 63 — 0 — — 0 — — — — — — — 1 1 — — 1 1 1 1 E — — — 0 — 0 0 0 1 1 1 1 — — — — 1 1 — — Check for inclusion in group of 8 ü ü ü ü ü
1
1 1 1 1 1 1 — — 1 1 1 1 1 1 1 1 1 1 1 1
ü ü ü ü ü ü
2
3
. 11 8. 15 9. 27 26. 11. 9. 13. 11 9. 10. 15.(Contd. 13. 24. 11 10. 27 24. 25 24. 27. 25. 26. 26. 26. 9. 10. 24. 31 — 1 1 0 0 — 0 — 1 1 1 0 — 0 1 1 1 — 1 1 B Variables C D 0 0 0 0 — 0 0 0 0 0 0 — 0 1 0 0 — 1 — 1 0 — 0 — 0 0 1 1 1 0 — 1 1 — — 1 1 1 1 1 E 0 0 0 1 1 1 — 0 0 — 0 1 1 1 1 — 0 1 1 — Check for circlusion in group of 4 ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü
2
3
4
1 0 — 1 1 1 1 1 — 1 1 1 1 1 1 1 1 1 1 1
Table (c) Grouping of 4 minterms
Group Minterms A 8. 26 18. 27.) Group Minterm A 8. 11. 24 16. 25 8. 24. 18. 27 11. 25. 24. 27 10. 27. 15 25.31 30. 27 24. 11. 13 9. 10. 31 27. 10. 26 9. 30. 26. 11. 15. 27 10. 25 8. 25. 24. 25. 15 9. 26. 15 11. 26 11. 24 9. 26 8. 24. 26. 26 16. 9. 18. 30. 27 9. 11. 27. 26 16.
27. 24. 10. D. 9. 27. 15. C. 27
´
Ä
´
´ ´ ´ ´ Ä ´ ´ ü
´
´ Ä ´ ´ ü
´ ´
´ ´
´ Ä ü ü ü
´ ´
The minimized function is f (A. 9.Tabe (d)
Group 1 Minterms
Grouping of 8 minterms
A B 1 Variables C D 0 — E —
8. 24. 26 ACE ü 9. 31 ABD ü 26. 13. B. 11. 18. 24. 31 ü 8. 26. 30. 15 ABE BDE 11. ´ BC 25. 27
—
Tabe (e) PI Table
PI terms Decimal numbers 8 Minterms 9 10 11 13 15 16 18 21 24 25 26 27 30 31
Ä
21 AB CDE ü ü 16. E) = A B C D E + A C E + A BE + ABD + B C
64
. 25. 11. 26. 11. 10.
CHAPTER 6
6. 5. and C are to be connected to S2. S1 .3). 4. i. the data output is inverted input. Since the data output is 1 when the input variables correspond to decimal numbers 2. 6. 11. the inputs A. 6.. complement of the data input line selected. In this. and S0 Table Prob. 10. 7.
Logic 0 Logic 1 0 1 2 3 4 5 6 7 16:1 8 9 Multiplexer 10 74150 11 12 13 14 15 G S3 S2 S1 S0 Logic 0 (MSB) A B C D (LSB) Fig.1
Y
(b) To realize a four variable truthtable or logic expression using an 8:1 multiplexer the truth table is partitioned as shown by dotted lines (Table 6.e. The circuit is shown in Fig. 3. 8. 9. B.1. 13. therefore. Prob. 12 and 15. the data input lines corresponding to these decimal numbers are to be connected to logic 0 and the data input lines 0.1(b)
A 0 0 0 0 1 1 1 1 Inputs B 0 0 1 1 0 0 1 1 65 C 0 1 0 1 0 1 0 1 Output Y 0 D D 1 D 1 D D
. Prob. 1. and 14 are to be connected to logic 1.1 (a) In the 16:1 multiplexer IC 74150. 6. 6.
Prob. 6.select inputs respectively. (ii) Another method can use two 16:1 multiplexers with their select lines connected together. (i) A 32:1 multiplexer will have five selection lines.3. 6. the circuit is shown in Fig.1(b)
C
6. B. This IC also has the data output which is complement of the data input line selected. we observe the relationship between input D and output Y for each group of two rows.1(b). 6. If A is connected to the Enable input of one of the 16:1 multiplexers. Assuming 74152 IC. B.3. The complete circuit is shown in Fig. Prob. 6. D. 6. Thus for the first 16 of the 32 data inputs one multiplexer gives output depending upon the select inputs while for the remaining 16 data inputs the other multiplexer gives the output. Now. and D . To realize this.2(ii). Prob. the system will function as a 32:1 multiplexer. D.2(i). and E. then for A = 0. 6. A.
66
. while the enable input of the other multiplexer is connected to A .1(b).
Logic 1 0 D 1 2 D Logic 0 3 4 5 6 7 S2 S1 S0 74152 Y
A B Fig. The select line of the 2 : 1 multiplexer is driven from input A. Prob. C. The complete circuit is shown in Fig. 1. This is followed by a 2:1 multiplexer to select one of the two outputs. the first multiplexer is enabled and for A = 1 the second multiplexer is enabled.2 A 32:1 multiplexer can be designed using two 16:1 multiplexers following any one of the following approaches. using 8:1 multiplexers requires one multiplexer for Sn and one for Cn output. Prob. The implementation of this function using a 74152 IC is shown in Fig. There are four possible values of Y and these are 0.3 The truth table of a fulladder in given in Table Prob. 6. and C and then make the connections accordingly. Now if the two outputs are ORed together. From this table. 6. These are given in Table Prob. we note the output Y for each of the combinations of A. say. where A is the MSB.
E) G3 S3 S2 S1 S0 16 17 18 31 G2 M2 16 : 1 Y2
ì ï Data ï inputsí ï ï î
Logic 0
Logic 0
Fig. Prob. 6. B. E) S3 S2 S1 S0
ì ï Data ï í inputs ï ï î
A (MSB)
16 17 M2 18 16 : 1 31 G2
Y2
·
Fig. 6.ì ï ï Data í inputs ï ï î
G1 E (LSB) D C B
0 1 2
M 1 Y1
15 16 : 1 S3 S2 S1 S0
Output F (A. B.2(ii) 67
. C. C.2(i)
ì ï ï Data í inputs ï ï î
G1 Logic 0 B C D E (LSB)
0 1 2 M1 Y1 15 16 : 1 A(MSB)
S3 S2 S1 S0 S 0 Output M3 Y 1 2 : 1 F (A. D. D. Prob.
6.3 68 74152 IC2 Cn S2 S1 S0 S2 S1 S0 74152 IC1 Sn
. 6.3
An 0 0 0 0 1 1 1 1 Inputs Bn 0 0 1 1 0 0 1 1 Outputs Cn–1 0 1 0 1 0 1 0 1 Sn 0 1 1 0 1 0 0 1 Cn 0 0 0 1 0 1 1 1
The gates required for NANDNAND realization are: 4input NAND gate 1 3input NAND gates 5 2input NAND gates 3 Inverters 3
Logic 1 0 1 2 3 4 5 6 7 Logic 0 An Bn Cn–1 Logic 1 0 1 2 3 4 5 6 7 Logic 0 Fig. Prob.Table Prob.
6.4 The A inputs are applied directly to the adder. On the other hand.5 (i) gives the truth table of GraytoBCD code converter. 6. the following IC packages will be required: 7420 – 1 7410 – 2 7400 – 1 In contrast to four packages required in NANDNAND realization. when S is in SUB position. the realization using 8:1 multiplexers require only 2 IC packages. whereas the B inputs are applied through EXOR gates. The complete circuit is shown below. Also Cin = 0.
64444 74444 8 4 4
B3 B2 B1 B0
B Input
A3 A2 A1 A0
64748
A input
7 4 8 3 4bit Adder
ADD Cin S SUB VCC
C0
S3
S2
S1
S0
6. the circuit functions as a 4bit adder.5(i)
G3 0 0 0 0 0 0 0 0 1 1 Gray code G2 G1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 G0 0 1 1 0 0 1 1 0 0 1 69 D 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 BCD code B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 0 1 0 1 0 1
. Table Prob. the EXOR gates function as inverters. When the switch S is in ADD position the outputs of the EXOR gates will be same as the B inputs. therefore. Also Cin = 1.Therefore. Therefore. the circuit adds A to the 2’s complement of B and hence functions as a 4bit subtractor.5 Table Prob 6.
These are given in Table Prob. 6.6(i) shows a commonanode 7segment display device. 6. C. It requires one 74154.6(i)
D 0 0 0 0 0 0 C 0 0 0 0 1 1 BCD Inputs B A 0 0 1 1 0 0 0 1 0 1 0 1 a 0 1 0 0 1 0 b 0 0 0 0 0 1 SevenSegment Outputs c d e f 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 g 1 1 0 0 0 0 (Contd. and one 7400 IC packages.)
70
. Table Prob.5 (ii). 6. 6. we can obtain the expressions for the D. Prob. Table Prob.5(b). one 7420. 6. Prob 6. 6.5(ii)
G3 0 0 1 1 G2 0 1 0 1 D 0 0 X 1 C 0 1 X 0 B G1
G1 X 0
A G1 ⊕ G0
G 1 ¤ G0 X G1 ⊕ G0
The G3 and G2 are used as the select inputs.6(i) and Fig. one 7430. and B outputs.6 The truth table of BCDto7segment decoder is given in Table Prob.(a) For A output (i) When G3 G2 = 00
G1 0 0 1 1 G0 0 1 1 0 A 0 1 0 1
(ii) When G3G2 = 01
G1 1 1 0 0 G0 0 1 1 0 A 0 1 0 1
\ A = G1 ⊕ G0 (iii) When G3 G2 = 10
G1 1 1 0 0 G0 0 1 1 0 A X X X X
\ A = G1 ¤ G0 (iv) When G3 G2 = 11
G1 0 0 1 1 G0 0 1 1 0 A 0 1 X X
\A= X \ A = G1 ⊕ G0 Similarly. The complete circuit can be drawn which requires two 74153 packages and one 7486 package. (b) The complete circuit is shown in Fig.
we can prepare Table Prob. The ICs required are: 74153 3 1 packages 2
71
. 6. 6. 6.5(b)
(a) From Table Prob.6(i) (Contd. 6. 6. The circuit for generating data inputs for the multiplexers corresponding to Table Prob.)
D 0 0 1 1 1 1 1 1 1 1 C 1 1 0 0 0 0 1 1 1 1 BCD Inputs B A 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 a 1 0 0 0 X X X X X X b 1 0 0 0 X X X X X X SevenSegment Outputs c d e f 0 0 0 0 X X X X X X 0 1 0 1 X X X X X X 0 1 0 1 X X X X X X 0 1 0 0 X X X X X X g 0 1 0 0 X X X X X X
Y0 Y1 Y2 Y3 Y4 Y5 G1 G0 74154 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 S3 S2 S1 Y15 S0 Aü (LSB)ï ï ï ï ï ï Bï ï ï ï ï BCD ï ýoutputs ï ï Cï ï ï ï ï ï ï ï Dï (MSB) ï þ
0 13 4 444 44 2 2 1 3
G
G
G
G
Gray code inputs Fig.6(i). Prob.Table Prob. Prob.6 (ii) is shown in Fig.6(ii) which gives outputs in terms of A and B inputs for each combination of D and C inputs. 6.6 (ii).
6.6(ii)
(b) The circuit is designed in a way similar to Prob.5. 6. 6.6(ii)
D 0 0 1 1 Inputs C 0 1 0 1 a
BA
b 0 B⊕ A 0 X
c
Outputs d
BA
e A A+ B A X
f A+B AB 0 X
g
B
A 0 X
BA 0 0 X
B¤A A X
AB 0 X
B
A+ B
B
BA
A+B AB BA
BÅA
B¤A
A
A Fig.6(i)
Table Prob. Prob.7408 7432 7404
3/4 package 3/4 package 1/2 package
Anode
a b c d e f g f e
a b g c d · DP DP
Fig. Prob. 6. The ICs required are: 74154 one package 7420 one package 7410 one package
72
.
we observe the savings in hardware when demultiplexers/decoders are used for the realization of multiple output systems.5(i) can be rearranged suitably to give the truth table of BCDtoGray code converter. and B inputs are to be applied to the S2.7(a)
D 0 0 0 0 1 C 0 0 1 1 0 B 0 1 0 1 0 G3 0 0 0 0 1 G2 0 0 1 1 1 G1 0 1 1 0 0 G0 A
A A A A
The circuit can now be designed using four 74151A ICs (one for each of the outputs). The IC packages required are same as in part (b) with 74154 replaced by 7442. 6. 6. Table Prob.7 (c).7 (a) is obtained following the procedure used in Prob. Here eight rows of the truth table are grouped together. Table Prob.7(c)
D 0 1 G3 0 1 G2 C 1 G1 B⊕ C 0 G0 A ⊕ B A
73
. 6. 6. 6. (b) Table Prob. Table Prob.5 (a). These outputs are to be connected exactly in the same way as in the case of part (b) realization. 6. 6. 6.7430 one package 7404 1/6 package (c) The IC 7442 is a BCDtodecimal decoder circuit with activelow outputs.7 Table Prob. 6. we obtain Table Prob. C. The D.1(b). S1. (d) From the IC packages requirements for parts (a). and S0 select inputs respectively. Table Prob. 6.7(b) can be obtained from the truth table following the procedure of Prob.7(b)
D 0 0 1 1 C 0 1 0 1 G3 0 0 1 X G2 0 1 1 X G1 B
B 0 X
G0 A⊕ B A⊕ B A X
(c) Following the approach similar to (b). (b). (a) From the truth table. The circuit can now be designed using two 74153 ICs and two EXOR (7486) gates. and (c).
f2.8(i) (a) The truth table is reduced to Table Prob. 6.8(ii) for realization using 8 : 1 multiplexers. Table Prob. 6. 6. (f) The package count for each part are given in Table Prob 6.1.7(d) Table Prob. 7404 – 1 74153 – 2. 7430 – 2. of IC packages 74151A – 4. 6. and f3 can be designed following the procedure outlined in Example 6. 5. (b) Using the truth table the circuits for f1. (d) Following the procedure used in Example 6. f2. The realizations will require one 16 : 1 multiplexer for each output. 7486 – 1 7442 – 1.The circuit can now be designed using one 74157 (Quad 2:1 multiplexer) IC and two EXOR gates of 7486.7(d)
Part a b c d e No. (c) The circuit can be designed using one demultiplexer and two 8input and one 6input NAND gates.3. and f3 outputs using multiplexers and inverters.8(i)
D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inputs C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Outputs B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 74 f1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 f2 1 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1 f3 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0
. the circuit can be designed using one BCDtodecimal decoder IC 7442 and NAND gates (2. 7420 – 1 7400 – 3
6. f2.8 The truth table for f1. (e) The minimized expressions are G3 = D G2 = C + D G1 = C B + C B G0 = B A + B A The realization will require eleven 2input NAND gates. The circuits can now be designed for f1. 4. 7486 – 1 75157 – 1. and 6input). and f3 outputs is given in Table Prob.
6.Table Prob. 6. and D are used as select inputs S2. which selects output of one of the multiplexers M1 through M5. S1. The lower order three select bits C. B. E. and A are used as S2.9 75
. The higher order three select bits F.8(ii)
D 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 f1
A A A A A A A A
f2 1 1 0 0 0 A
A 1
f3 0 A 1
A A 0 A 0
6. and S0 for the multiplexer M6. Prob.9 In a 40:1 multiplexer. S1. there are 40 data input lines (I0 through I39). S0 select inputs respectively for 8:1 multiplexers M1 through M5.
I0 – I7 G M1 S2 S1 S0 C B A I8 – I15 S2 S1 S0 G M2 0 1 2 3 4 M6 5 6 7 G S2 S1 S0
Y
I16 – I23 G I24 – I31
M3 S2 S1 S0 C B A S2 S1 S0 M4 G C B A (LSB)
F E (MSB)
D
I32 – I39 Enable
S2 S1 S0 G M5 Fig. 6 select lines FEDCBA.
and A. D is active0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
D X2 X1 X0 (LSB) C B A D1 7442
D X2 X1 X0 0 1 2 3 D6 4 D 7442 5 6 7 8 C B A9 C B A D2 7442
8 9 10 11 12 13 14 15
D X2 X1 X0 ( C B A D3 7442
Enable
16 17 18 19 20 21 22 23
X5 X4 X3 (MSB) X2 X1 X0
D C B A D4 7442
24 25 26 27 28 29 30 31
D X2 X1 X0 C B A D5 7442
32 33 34 35 36 37 38 39
Fig. 6. data input 7 of M2 (I15) will appear at the output Y.For example if the select inputs are 011111.10 The BCDtodecimal decoder is to be used as an 1 : 8 demultiplexer. B. 6. Prob. The address inputs for demultiplexers D1 through D6 are C.10 76
.
X4. P4 and Q4 are applied at the A and B inputs respectively of adder # 4 and similarly the other inputs are applied as shown below. The complete circuit is shown in Fig. 6.11 For the fulladder circuit designed using halfadder circuits shown in Fig. the propagation delay time for the carry to propagate from C–1 to Cn–1 in the circuit of Fig.low input for demultiplexer function. if the 6bit select inputs are 001111. Prob. For an nbit adder. 6. A select inputs respectively of each decoder chip D1 through D5. 6. Prob. which activates decoder D2 and the output 7 of this decoder goes low. B. Prob.12 (a) will be n ´ 40 = 40 ns. For example. X1.10. 6. The lower order three bits of the address X2.11
C2 OR
Cn
The propagation delay time for Cn is tpd = tpd [EXOR(1)] + tpd (AND2) + tpd (OR) = 20 + 10 + 10 = 40 ns This is the propagation delay time for carry to travel one fulladder. The higher order three bits of the address X5. Therefore. This corresponds to output on line 15 (which is same as the decimal equivalent of 001111). 6. and X0 are applied at the C. 6. and X3 are applied at the C. this carry has to ripple through all the n adders.11.12 77
C0
S15–S12
S11–S8
S7–S4
S3–S0
. and A select inputs respectively of D6. The outputs 8 and 9 of D1 through D5 are not used in this configuration. 6. Prob.12 Let the four digits BCD numbers be P4P3P2P1 and Q4Q3Q2Q1. B. then output 1 of D6 is activated.
Q4 P4 Q3 P3 Q2 P2 Q1 P1
BCD adder #4 C¢¢¢¢ C2 0
BCD adder #3 C¢¢¢ C1 0
BCD adder #2 C¢¢ C0 0
BCD adder #1 C¢0 C–1
144444444444444 2444444444444444 4 3
5digit output Fig.
EX–OR(1) An Bn S1 EX–OR(2) S2 = Sn C1 AND2 AND–1 Cn–1 Fig.
14 78
. Prob. 6. Using Kmaps the minimized expressions given below are obtained. and A < B outputs are connected to the corresponding cascading inputs of C2 respectively. 6.14 The comparator C1 compares the least significant four bits.13
Inputs A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 Outputs A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
A > B = A0 B 1 B0 + A1 A0 B 0 + A1 B 1 A = B = A1 B 1 (A0 ¤ B0) + A1B1 (A0 ¤ B0) = (A0 ¤ B0) (A1 ¤ B1) A < B = A 1 A 0 B0 + A 0 B1B0 + A 1B1 The complete circuit can be drawn using gates.6. A = B.13. The complete circuit is shown below. 6. Its A > B.
A0 – A3 B0 – B3 C1 7485 A>B A=B A<B A4 – A7 A>B A=B A<B 7485 A>B A=B A<B B4 – B7 C2 A>B A=B A<B
Logic 1 Logic 0 Fig. Table Prob.13 Its truth table is given in Table Prob. 6.
and A inputs respectively.15 The operation is given below. D and E inputs are connected to logic 0. B. 6. C1. and B1) are applied to C. The other three bits (D1. Prob.6.
Inputs CIC 1 A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B = 1001 = 1011 =1 =0 =1 = 0000 = 0000 =1 =0 =1 = 1011 = 1101 =1 =0 =1 = 0010 = 0001 =1 =0 =0 = 0010 = 0011 =0 =1 =0 = 0001 = 1000 =0 =0 =1 Outputs
A>B=0 A<B=1
CIC 2
A>B=0 A<B=0
CIC 3
A>B=0 A<B=0
CIC 4
A>B=1 A<B=0
CIC 5
A>B=0 A<B=1 A=B=0
CIC 6
A>B=0 A=B=0 A<B=1
6.16 The leastsignificant bit (A1) of BCD input is same as the leastsignificant bit of the output. The binary output is obtained at B3B2B1B0 outputs as shown in Fig.16.
79
.
A . Connect EVEN and ODD inputs to logic 1 and 0 respectively. Therefore.18 Apply the 6bit input to A through F inputs and connect the other two inputs G and H to logic 0. This shows that the circuit is a priority encoder.ì A1 ï BCD ï B1 inputs í C ï 1 ïD î
1
B0 A B C D E G 74184 Y1 Y2 Y3 Y4 Y5
B1 ï Binary ï ý outputs B B3 ï þ
2
ü ï
(MSB)
Fig. The circuit is shown below. If two inputs are given simultaneously. then å EVEN output is 1 if the 7bit input is even and 0 if the 7bit input is odd. Prob.G A . Prob. then E0 of IC2 will be HIGH. these seven bits along with the å EVEN output bit will give an 8bit word with odd parity.16
6. which will disable the IC1 chip. å EVEN output will be 1. if the parity of the 6bit word is ODD. one of which is in IC1 and the other one in IC2. 6. If EVEN and ODD inputs are at logic 1 and 0 respectively. the highest numbered input will appear in the binary form at the output. whereas.19
80
.G SEVEN
ü ï 8bit odd ý parity word ï þ
74180 H EVEN SODD ODD
Logic 1
Logic 0 Fig.17 The IC 74148 is a priority octaltobinary encoder. then å ODD output will be 1. 6.19 The 7bit input is applied at A through G inputs and H = 0. If the parity of the 6bit word is even. 6. If more than one inputs are given in the same chip. 6.
Prob. 6.
B0 B1 B2 B3 B4 B5 B6 B7 7486 B8 B9 Logic 1 Fig. 6. Prob.21. 6.20
Parity of B0 – B7 åEVEN EVEN ODD 1 0 P1 åODD 0 1 Parity of B8 – B13 EVEN ODD EVEN ODD åEVEN 1 0 0 1 P2 åODD 0 1 1 0
From the table we see that the parity of B0 – B13 and åODD of P2 is even. 6.20 and its operation is given in Table Prob.20 The circuit is shown in Fig. 6.21 and its operation is explained in the Table Prob. Prob.21 The circuit is shown in Fig.20 ODD
ü ï ý ï þ
Table Prob. 6.6. 6. 6.21 81 A B C S EVEN D E F 74180 G H EVEN SODD ODD
1 on even parity
15bit even parity word
Logic 1
B14
.
B0 – B7 SEVEN P1 74180 SODD EVEN B8 – B13 Logic 0 SEVEN P2 74180 SODD
G H
B0 – B13
EVEN ODD Fig. Prob.20.
and M4. Prob. The leastsignificant bits of the BCD digits are applied at the data inputs of M1 and similarly higher order bits are applied to M2. Prob. M3.24 See Fig. Prob. 6. Here P1.26 Let the four BCD digits be ABCD.23. 6. 6.21
Parity of B0 – B7 EVEN EVEN ODD ODD Parity of B8 – B9 EVEN ODD ODD EVEN Cascading inputs EVEN ODD 1 0 0 1 0 1 1 0 Outputs åEVEN 1 0 1 0 åODD 0 1 0 1
6. The circuit is given in Fig.25 6. and P3 are 9bit parity checkers. The select input are fed from the mod4 counter. Prob.22
b0 – b 7 SEVEN P1 EVEN ODD
b8
b9 – b16
SEVEN P2 EVEN ODD SEVEN P10 EVEN ODD High on EVEN High on ODD
b17
b72 – b79
SEVEN P9 EVEN ODD Fig. P2. 6.Table Prob. Prob.24 (a and b) 6.25 See Fig. with A as MSD. which drives a BCDtodecimal decoder.26. 6.23 The circuit is given in Fig. 6. 6.
82
.22
b80
6.
23 (a) VCC VCC Current Limiting resistor
VCC BCD input (MSB) ìD
ïC í ïB îA
7442
GND
0 1 2 3 4 5 6 7 8 9
Fig. Prob.24(a)
83
. 6. Prob. 6.b0 P1 b8
SEVEN
b9 P2 b15
SEVEN
High on EVEN
SODD
High on ODD
b16 SEVEN P3 b24 Fig.
the display would appear to be continuous. 6.26. When the counter output is 00. when the counter outputs are 01. 6. digit A is selected and at the same time anode A1 goes HIGH. 10.(b)
+170 V R = 10 kW 0 1 2 3 4 5 6 7 8 9 Anode
NIXIE Tube 0 1 2 3 4 5 6 7 8 9 +5V VCC 74141
D C A 1444 24444 4 B 3 BCD Input (b) Fig.27 For R to glow. and D digits are displayed respectively on second. thereby displaying the digit A on the leftmost 7segment display. The circuit is to be designed in a way similar to that of Prob. If the clock frequency is sufficiently high. Similarly. third. In this way each display will be ON for onefourth of the total time. Seven 5:1 multiplexers and a mod5 counter will be required for this.25
14 15
Detects 0001111
The multiplexer outputs are decoded by the BCDto7segment decoder with activelow outputs. Prob.27. C. 6.
84
. and 11 B. 6. Prob. the inputs required at the rows for each column are as given in Table Prob. One column must glow at a time in sequence.24 0 1 2 3
(LSB)
A B C D Enable (logic 0) D1
E F G H D2
0 1
15
Detects 0001 Fig. 6. and fourth displays in sequence.
6. Prob. 6.27
Row/Column ® ¯ 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 2 1 0 0 1 0 0 0 3 1 0 0 1 1 0 0 4 1 0 0 1 0 1 0 5 0 1 1 0 0 0 1
85
.26
Table Prob.A0 B0 C0 D0
0 1 M1 2 3 S S 1 0 BCDto7segment decoder a b c d e f g Buffer inverters ··· 0 1 2 3 4 BCDtodecimal decoder
A1 B1 C1 D1
0 1 M2 2 3 S S 1 0
A B C (MSB) D
A2 B2 C2 D2
0 1 2 M3 3 S S 1 0
A1
A2
A3
A4
A3 B3 C3 D3
0 1 2 M4 3 S S 1 0
Q0
Q1
Q2
Q3
Mod4 counter
Clock Fig.
1 When S = R = 0. On the other hand if Qn = 0 then Sn = 1 which will make Qn+1 = 1. Q1 = 1 and Q = 0 in a manner similar to part (a) and also Q and Q will remain unchanged when S and R both are made 0. whatever may be the other input of G3.3
R Q
Q
S Fig. then Sn = Q n and Rn = Qn. Therefore. we find that the FLIPFLOP will go to the reset state when a clock pulse is applied. therefore. which makes the lower input of G1 as 0 while the upper one becomes one giving again Q = 1.e.5 (i) When Jn = Kn = 0. R. G1 and G2 will act as inverters.. Therefore. Qn+1 = Qn. 7. Q will be 0 which makes one of the inputs of G3 0. the inputs and output of G2 remain unaffected. Now. it will go to set state in this condition when a clock pulse is applied. Now if S = R = 0. Therefore. (b) If Cr = 0. (iii) If Jn = 0 and Kn = 1 then Sn = 0 and Rn = Qn. making this circuit identical to a normal clocked S – R FLIPFLOP as shown in Fig. Therefore.5. if Qn = 1. (ii) When Jn = 1 and Kn = 0. That is. (c) If Pr = Cr = 1. if Qn = 1 then Sn = 0. if Qn = 0. whatever may be the state of the FLIPFLOP. Qn+1 = Q n. 7. Hence. its output Q = 1. This makes both the inputs of G2 as 1 giving an output Q = 0. This means the outputs do not change.4 is same as that of Fig. the AND gates are disabled resulting in Sn = Rn = 0. Sn = Rn = 0 and the output Qn+1 = Qn = 1. Prob 7. (iv) If Jn = Kn = 1. 7. Now. then the FLIPFLOP is reset following the same logic as discussed in part (a). Since one of the inputs of G1 is 0.3
7. the FLIPFLOP is set irrespective of the S. the circuit of fig. (b) With S = 0 and R = 1. Following the above discussion. the AND gates G5 and G6 are enabled.CHAPTER 7
7. when a clock pulse is applied. then Sn = Q n and Rn = 0.3.2 (a) With S = 1 and R = 0.e. and CK inputs. the outputs Q and Q will not change. the outputs of the gates G3 and G4 will be 1. i. Therefore. This results in both the inputs of AND gate G5 to be 1 giving Q = 1. then Sn = 1 and Rn = 0 which makes Qn+1 = 1. the outputs of G3 and G4 are 0 and 1 respectively. 7.4 (a) With Pr = 0. 7. Similarly. i. 7.
86
.. then Sn = 0 and Rn = 1 which will make Qn+1 = 0. its output will be 1.
8
Clock Input
Q2 = Q
Output í
ìQ îQ
7. Q and Q will become 0 and 1 respectively. Y1 = Y2
7.7 Q1 = Q and 7. Now.9
Clock Input
Output í
ìQ îQ
7.6 Y1 = ( J ⋅ Q ) ⋅ CK
= J ⋅ Q ⋅ CK
and
Y2 = J ⋅ Q ⋅ CK Hence. R = Q = 0 and S = Q = 1 and on
87
.10
Clock
Input
Output Q
7.11 Let Q = 1 and Q = 0. This makes R = Q = 1 and S = Q = 0.7. When a clock pulse is applied.
From this table we observe that when Tn = 0. whereas. a clock pulse will make Q and Q 0 and 1 respectively.14(b). 7. 7.13 When Q = D = 0. 7.12 The truth table is given in Table Prob. 7. Now
Q = D = 1 and the next clock pulse will change the Q output to 1. Q and Q become 1 and 0 respectively. Qn+1 = Q n. which give
Y1 = Q + CK + J = Q ⋅ J ⋅ CK and Y2 = CK + K + Q = Q ⋅ K ⋅ CK Table Prob. The Kmaps can be prepared and minimized. 7. 7. The minimized expressions are:
88
. when Tn = 1. Table Prob. The Kmaps for Y1 and Y2 are shown below.14 The characteristic table and the truth table for decoder are given in Table Prob. Thus. Qn+1 = Qn. the outputs change with every clock pulse.application of a clock pulse. This show that Q and Q change with every clock pulse. 7.14 (a).14 (a)
CK 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 J 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Characteristic table K Qn 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qn + 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Truth table for decoder Y1 Y2 1 X 1 X 1 X 1 X 1 X 1 1 0 X 0 1 X 1 X 1 X 1 X 1 X 1 X 0 1 1 1 0
(b) The excitation table and the truth table for decoder are given in Table Prob.12
Tn 0 0 1 1 Qn 0 1 0 1 Sn 0 1 1 0 Rn 1 0 0 1 Qn+1 0 1 1 0
7. and hence the circuit behaves as a toggle switch.12.
15(a).KQ
CKJ 00 00 1 01 ´ 11 ´ 10 1
01 1 ´ ´ 1
11 0 ´ 1 0
10 1 ´ 1 1
KQ
CKJ 00 ´ 1 1 ´
01 ´ 1 1 ´
11 1 1 0 1
10 ´ 1 0 ´
00 01 11 10
Y 1 = Q + CK + J = Q ⋅ J ⋅ CK (a)
Y 2 = CK + K + Q = Q ⋅ K ⋅ CK (b)
Y1 = CK + D = CK ⋅ D and Y = CK + D = CK ⋅ D Table Prob. we obtain Y1 = CK ⋅ T ⋅ Q Y2 = CK ⋅ T ⋅ Q Complete circuits can be drawn for each of the above cases. 7. 7.15(i) from which we obtain the minimized expressions for S and R as S = D and R = D and Table Prob. 7. The Kmaps for S and R outputs are prepared as shown in Fig. 7.15 (a) The truth table required for conversion from SR to D FLIPFLOP is given in Table Prob.14(b)
CK 0 0 0 0 1 1 1 1 Excitation table D 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 1 0 0 1 1 Truth table for decoder Y1 Y2 1 X 1 X 1 1 0 X X 1 X 1 X 0 1 1
(c) Using the above method.15(a)
Data input D 0 1 0 1 Output Q 0 0 1 1 89 SR FF inputs S R 0 1 0 X X 0 1 0
. 7. Prob.
7.15(b) from which the minimized expressions are obtained as J= D and K= D
Table Prob.15(i)
(b) The required truth table is given in Table Prob. 7. 7. 7. 7.15 (d) gives the required truth table from which we obtain the minimized expressions for S and R as S = T ⋅Q and R =T⋅Q
90
.15(b)
Data input D 0 1 0 1 Output Q 0 0 1 1 J 0 1 X X JK FF inputs K X X 1 0
(c) The required truth table is given in Table Prob.15(c) and the minimized expression for D is given by D = JQ + KQ Table Prob. 7.15(c)
Data inputs J 0 0 1 1 0 1 0 1 K 0 1 0 1 1 1 0 0 Output Q 0 0 0 0 1 1 1 1 DFF input D 0 0 1 1 0 0 1 1
(d) Table Prob. Prob.Q
D 0 0 1 0 0 1 1 ´ (a) Q
D 0 0 1 ´ 1 1 0 0 (b)
Fig.
While the clock is HIGH. The minimized expressions obtained are given below: (f) (g) (h) (i) (j) (k) T = J Q + KQ T =D⊕Q D = S + RQ D =T⊕Q T = S Q + RQ J = S. Therefore. 7. if the switch is changed over to position 0.17. Therefore. even if the switch
91
. Q will become 0.16 Let the inputs to the latch be Y1 and Y2. Y1 and Y2 will remain unaltered. Q becomes 0. all the other conversions can be made. if there is any change in D. 7. When the clock goes back to 0. Prob. Pr = 0 and Cr = 1. This means the state of the FLIPFLOP cannot change. (ii) When the clock is HIGH: Y1 and Y2 are complement to each other and for each value of D we find that the values of Y1 and Y2 do not change. Case II: Let D = 1. K = R
7. if there is any change in D.Table Prob.17 The waveforms obtained are shown in Fig. 7. (i) When the clock is LOW: Y1 = Y2 = 1 independent of D input and the state of the FLIPFLOP cannot change. as soon as it makes contact for the first time. When the clock comes back to 0 from 1. then Y1 = Y2 = 1 which also does not affect the output Q. Y1 and Y2 will remain unaltered. 7. (iii) When the clock goes from LOW to HIGH: Case I: Let D = 0 Y1 will remain 1 and Y2 changes from 1 to 0. then Y1 = Y2 = 1 which will not affect the output Q. Y2 will remain 1 and Y1 changes from 1 to 0. while the clock is HIGH.15(d)
Data input T 0 1 1 0 Output Q 0 0 1 1 S S – R FF inputs R X 0 1 0
0 1 0 X
(e) The truth table can be prepared and expressions for J and K inputs obtained. Therefore. Q goes to 1. Now. Now. Now.18 (a) When the switch is in position 1. J=K=T Similarly. Q = 1.
Clock
1 0 0 1 1 2 3 4 5 6 7 8 9 10 11 12
J 0 1 Q 0 1 Q 0 (b) Fig. the operation will not be reliable. This means. Prob. When CKD goes HIGH. 7. 7. 7.17 (a)
debounces.21 The waveform at CK will be as shown in Fig.19 The clock.21. (b) When the switch is in position 1. 01 and 10. the data is loaded into the destination FF. if the delay time Dt2 is more than it takes to change the present output of the source FF. Similarly.19. the output Q will not be affected.
92
.
Clock
CKS
Dt1
CKD
Dt2
Fig. at the first contact Q becomes 1. Prob.20 The waveforms are shown in Fig. Prob. the clock skew may violate the hold time requirements of the destination FF. CKs and CKD waveforms are shown in Fig. the level triggered Dtype FF will operate as a positiveedgetriggered FF. Prob. Prob 7. Now.20. At the rising edge of the clock CKs. 7. 7. the outputs Q and Q do not change. 7. Q = 0 and Q = 1. In fact.19
7. the switch will operate in the reverse switching. When the switch is thrown to position 0. the data present at the data input terminal Ds is loaded into the source FF. This difficulty can be overcome by adding additional delay to assure reliable operation. The states of the counter are 00. when the switch debounces. Now.
Prob. 7. 7.1 Clock pulses 1 0 1 0 1 Q 0 = J1 Q1 0 1 0
2
3
4
5
6
7
J 0 = Q1
Fig. Prob.21
93
.20
Fig.
The circuit effectively reduces to that of Fig.
94
. Prob.1 (i) When the mode control input. 8. it functions as a leftshift register. Prob.1(i)
(ii) When M = 0.2
A 5stage twistedring counter is shown in Fig. This is a rightshift register.CHAPTER 8
8. Therefore.
Q3 FF3 D3 Q2 FF2 D2 Q1 FF1 D1 D0 FF0 Q0
Serial input
Fig. 8.1(ii)
8. Q4 = Q3 = Q2 = Q1 = Q0 = 0. 8. Table Prob. Prob. 8.e.2(a). M = 1. i. 8. In this case the data will get shifted to the left direction. the circuit comes back to its initial state. i.2(b).2
At the end of clock pulse 0 1 2 3 4 5 6 7 8 9 10 Q4 0 1 1 1 1 1 0 0 0 0 0 Q3 0 0 1 1 1 1 1 0 0 0 0 Outputs Q2 0 0 0 1 1 1 1 1 0 0 0 Q1 0 0 0 0 1 1 1 1 1 0 0 Q0 0 0 0 0 0 1 1 1 1 1 0
At the end of the tenth clock pulse.1(ii). The various outputs when clock pulses are applied are given in Table Prob... The circuit effectively reduces to that of Fig. Prob. Prob. all the A AND gates are enabled and all the B AND gates are disabled.1(i). 8. Its state diagram is shown in Fig. 8.
Serial input D3 FF3 Q3 D2 FF2 Q2 D1 FF1 Q1 D0 Q0 FF0
Fig. all the B AND gates are enabled and all the A AND gates are disabled.e. Let us assume that all the FLIPFLOPs are in the clear state.2. it is a mod10 counter. 8. Prob.
Figure Prob. . 1. The minimized expressions are given by Y0 = Q 4 Q 0 Y1 = Q4 Q 3 Y2 = Q3 Q 2 Y3 = Q2 Q 1 Y4 = Q1 Q 0 Y5 = Q4Q0 Y6 = Q 4Q3 Y7 = Q 3Q2 Y8 = Q 2Q1 Y9 = Q 1Q0
Table Prob. . . The Kmap is to be prepared for each output.2(b)
8.3 gives the Kmap for Y0 . 8. respectively. 8. 8. the Y outputs are don’t care. Prob.3.2(a)
00000
10000
11000
11100
11110
00001
00011
00111
01111
11111
Fig. 2. The truth table for the decoder is given in Table Prob. be the outputs corresponding to pulses 0. . 8. Prob. 8.D4 Q4 FF4 Clock Clear
D3 Q3 FF3
D2 Q2 FF2
D1 Q1 FF1
D0 Q0 FF0 Q0
Fig. . Y1. For all the remaining combinations of Q’s.3
Q4 0 1 1 1 1 1 0 0 0 0 Q3 0 0 1 1 1 1 1 0 0 0 Inputs Q2 Q1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 Q0 0 0 0 0 0 1 1 1 1 1 Y0 1 0 0 0 0 0 0 0 0 0 Y1 0 1 0 0 0 0 0 0 0 0 Y2 0 0 1 0 0 0 0 0 0 0 Y3 0 0 0 1 0 0 0 0 0 0 Outputs Y 4 Y5 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Y6 0 0 0 0 0 0 1 0 0 0 Y7 0 0 0 0 0 0 0 1 0 0 Y8 0 0 0 0 0 0 0 0 1 0 Y9 0 0 0 0 0 0 0 0 0 1
95
. Similarly. other Kmaps can be prepared.3 Let Y0.
Prob.
1 Clock Pulses Q3 Q2 Q1 2 3 4 5 6 7 8 9 10 11 12 13
Q0 Fig. which are designed in the same way as Prob. The required. 8.4(i). Prob.4(ii)
8.3 Q4 = 1 Q3Q2 Q1Q0 00 00 01 11 10 0 ´ ´ ´ 01 ´ ´ ´ ´ 11 0 ´ 0 0 10 0 ´ ´ ´
8.
Q3Q2 Q1Q0 00 00 01 11 10 1 0 0 ´ Q4 = 0 01 ´ ´ 0 ´ 11 ´ ´ 0 ´ 10 ´ ´ ´ ´ Fig. Prob. From the count sequence we observe that Q0 changes with every clock pulse.5. Prob. a 4stage twistedring counter is required. 8.5 The count sequence is given in Table Prob. Prob. This can be obtained by using a Ttype FLIPFLOP (FF0) with T0 = 1. 8. 8.4(ii).
96
. 8. The waveforms at the Q outputs are shown in Fig.The circuit can be drawn using ten 2input AND gates.4(i) Q3
Q2
f1
Q1
Q0
f2
Q2
f3
Q0
f4
Q3
Q1
Fig. 8. 8.3.4 To generate these waveforms. waveforms can be obtained by using decoders shown in Fig.
8. the desired changes in Q1 will be obtained. 8. therefore. The AND gates A are enabled when UP/ DOWN input is at logic 1. Prob.5.
T0 = T1 = T2 = 1 T0 Clock Q0 FF0
Q0
T1 Q1 FF1
Q1
T2 FF2
Q2
Q2
Fig. Q2 changes whenever Q1 goes from 0 to 1. Prob.6 For a ripple UP counter Q outputs of the preceding stages are to be connected to the clock inputs of the succeeding stages. 8. The complete circuit is shown in Fig. whereas the AND gates B are enabled when UP/DOWN input is at logic 0 connecting Q outputs to the clock inputs.5
Q2 0 1 1 1 1 0 0 0 Q1 0 1 1 0 0 1 1 0 Q0 0 1 0 1 0 1 0 1
8. The desired changes in Q2 can be obtained by using Q1 as the clock input for FF2 with T2 = 1. whereas for a DOWN counter Q outputs are to be connected to the clock inputs.Q1 changes whenever Q0 changes from 0 to 1.
T0 = T1 = T2 = T3 = 1 T0 Clock pulses Q0 FF0 A0 T1 Q1 FF1 B0 A1 T2 Q2 FF2 B1
Q2
A2
T3
Q3 FF3
Q0
Q1
B2
Q3
UP/ DOWN Fig.5
Table Prob. ANDOR gates are used between stages as shown below.6
97
. 8. Prob. Therefore. if Q 0 is used as the clock input for FF1 with T1 = 1. connecting Q outputs to clock inputs. Similarly.
D0
D1
D2
D3
Load
Pr Q0 FF0 Q0
Pr Q1 FF1 Q1 Fig. Prob. 8.7
Pr Q2 FF2
Q2
Pr
Q3
FF3 Q3
The preset inputs are used for asynchronous loading. The relevant portion of the circuit is shown on next page. When load input is HIGH, the data at the D inputs will be entered in the FLIPFLOPs. The other details will be same as in Prob. 8.6. 8.8 At the end of the tenth pulse Q3 = Q1 = 1, the output of G becomes 0. Also CK = 0, therefore, the output of the latch is 0. Now if Q1 or Q3 goes to 0, the output of the latch continues to be 0. When the eleventh clock pulse appears at CK, the output of the latch will go to 1 and normal counting will proceed. 8.9 (a) For the divideby5 circuit, the count sequence will be 000, 001, 010, 011, 100, 000. Therefore, as soon as the count reaches 101, all the three FLIPFLOPs must be cleared. The circuit is shown in Fig. Prob. 8.9.
T0 = T1 = T2 = 1 T0 Clock pulses Q0 FF0 Cr Q 0 T1 Q1 FF1 Cr Q 1 Fig. Prob. 8.9 T2 Q2 FF2 Cr Q 2
(b) For the divideby7, the resetting of FLIPFLOPs is required as soon as the count reaches 111. Therefore, a 3input NAND gate with inputs Q0, Q1, and Q2 will be required to clear the FLIPFLOPs. 8.10 The waveforms are shown in Fig. Prob. 8.10. It is clear from the waveforms that the frequency divisions by 3, 6, and 12 are obtained at the QC, QD, and QA outputs respectively.
98
Clock 1 pulses 0 1 QD QC 0 1 0 1 QB QA 0 1 0
1
2
3
4
5
6
7
8
9
10 11 12 13
Fig. Prob. 8.10
8.11 The states of the circuit of Prob. 8.10 are given below.
QD 0 0 0 1 1 1 0 0 0 1 1 1 0 QC 0 0 1 0 0 1 0 0 1 0 0 1 0 QB 0 1 0 0 1 0 0 1 0 0 1 0 0 QA 0 0 0 0 0 0 1 1 1 1 1 1 0
(a) The ÷ 7 counter is obtained by terminating the count sequence when QB = QA = 1. The circuit is shown in Fig. Prob. 8.11(a).
Output QA QB QC
QD
A input 7 Clock pulses B input R1 R2 4 9 2
Fig. Prob. 8.11(a) 99
(b) The ÷ 9 counter is obtained by terminating the count sequence as soon as QD = QA = 1. The circuit is shown in Fig. Prob. 8.11(b).
Output QA QB QC QD
A input Clock pulses B input
7
4
9 R1
2 R2
Fig. Prob. 8.11(b)
(c) The ÷ 11 counter is obtained by terminating the count sequence as soon as QD = QC = QA = 1. The circuit is shown in Fig. Prob. 8.11(c).
Output QA QB QC QD
·
A input Clock pulses B input 7 4 9 R1 2 R2
Fig. Prob. 8.11(c)
8.12 If we use the complements of QD, QC, QB, and QA as outputs, we obtain the DOWN counter. The sequence is given in Table Prob. 8.12.
QD QC QB QA
0 1 1 1 1 1 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0 0 1 1 1 1 100
0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 (Contd.)
)
QD QC QB QA
0 0 0
0 0 0
1 1 0
1 0 1
8. Prob.14 IC7490 is a decade counter. 8. two IC packages will be required. Prob. a divideby16 counter followed by a divideby8 counter will become a divideby128 counter.14 101
. IC 7493 is a 4bit binary counter.13.13 Since 128 = 16 ´ 8. 8. The resulting circuit is shown in Fig.13
Logic 0
8. therefore. To get a divideby96 counter. If two such ICs are cascaded. it becomes a divideby100 circuit. Prob. The complete circuit is shown below.
100 101
QA QB QC A input Clock pulses B input
QD A input
QA
QB
QC
QD
IC1 7490 S1 S2 R1 R2
IC2 7490 S1 S2 R1 R2
B input
Fig. 8.(Contd. Therefore.
Q0 QA Q1 QB Q2 QC Q3 QD QA Q4 QB Q5 QC Q6 QD
A input Clock pulses B input
A input IC1 7493 R1 R2 B input IC2 7493 R1 R2
Logic 0 Fig. the counter is reset as soon as it becomes 1001 0110.
15
8. For the mod6 counter. 8.15. The complete circuit is shown in Fig. Prob. 8.
QA
QB QC QD
QA
QB QC QD
A input Clock pulses B input 7493 R1 R2 A input B input 7492 R1 R2
Fig. QA output of 7492 is connected to B input and the QD output of 7493 is connected to A input of 7492. Prob.8. Prob.16
Clock pulses QA
1
2
3
4
5
6
7
8
9
10
11
12 13
QB
QC QD Fig. QC.15 Since 78 = 13 ´ 6. For the mod13 counter QD. therefore.16
102
. we have to use 7493 as a mod13 and 7492 as mod6 counters. and QA outputs of 7493 are ANDed and used to clear the counter when the count reaches 1101. 8.
Prob. Prob.18
8. The waveforms are
1 Clock pulses QA 2 3 4 5 6 7 8 9 10 11 12 13 14
QB
QC QD Cr Fig.8.17
Clock pulses QA
1
2
3
4
5
6
7
8
9
10
11
12
13
QB
QC QD
RC Fig. 8. 8.19 The counter ICI operates as a counter for counting in the UP direction when Cr = L = 1. When the count reaches the maximum value (111 in 4bit binary and 1001 in decade counter) its RC output goes HIGH which makes ENP = ENT of IC2 HIGH for one clock cycle advancing its output by 1 and making Q
103
.18 The counter have states from 0000 to 1100. The clearing operation will occur at the rising edge of the next clock.17
8.
Alternative II: Connect the circuit shown in Fig. 8. Prob. and 0001.
QA +VCC CKUP CKDOWN Cr PA PB PC PD L Borrow 74192 QB QC QD Carry
Clock pulses
+VCC Fig. 8.20(b) between QC. whereas only one type of operation is possible in the circuit of Fig. As soon as the count reaches 1100.20(a) between the QC. When the output becomes 0.27. Prob. 8. 8.20 Alternative I: Connect the circuit shown in Fig. QD outputs and the clear input (with L = 1). RC outputs of both of these ICs will go HIGH. 8.21(a) and waveforms are shown in Fig. The circuit is given in Fig.
QC QD (a) Fig.21(a)
104
. the clock pulses are applied at CKDOWN input. Prob.21 For the DOWN counter. When the outputs of IC1 and IC2 both reach the maximum count. QD outputs and load (L) input (with Cr = 1). the counter is loaded with preset inputs 0101 and the states will be: 0101. 8. As soon as the count becomes 1100. the counter is loaded with P inputs which must be PA = PB = PC = PD = 0. the counter is cleared. Prob. This will make ENP = ENT of IC3 HIGH and therefore. 8.outputs of ICI 0 at the next clock cycle.20 QC QD (b)
Cr
L
8. 0011. Prob. Prob. 0100. After this clock cycle ENP = ENT = 0 for IC2 and IC1 will go on counting the pulses. This way the counting will continue. the next clock pulse will be registered in this counter and simultaneously IC1 and IC2 will be cleared. 0010. 8.21(b). There are two possible operations in this circuit.
8. 8.Clock 1 pulses 0 1 QA 0 QB 1 0 QC QD 1 0 1 0
Borrow Fig. Prob.22(a).)
. Prob.21(b)
8.22(i) from which Table Prob. 8. Its state table is given in Table Prob.22 The modified state diagram is given in Fig.22(a) 00 0 0 1 1 01
Table 8.22(i)
Next State Present State A B 0 0 1 1 0 1 0 1 X=0 A 1 0 0 1 B 1 0 1 0 A 0 1 1 0 X=1 B 1 0 1 0
Table Prob. 8. Prob. 8.22(ii) is obtained to determine the FF inputs.
1 11 1 0 0 10 Fig.22(ii)
X 0 0 Counter State QA QB 0 1 0 1 JA 1 X 105 FLIPFLOP Inputs KA JB X 0 1 X KB X 1 (Contd. 8.
) 106
. The states of this circuit are: 000. 8.22(b)
QB
QB
QB
JA FFA KA
QA
QA
8. Prob. K1 FF2 : FF3 : J2. K2 J3.22(ii)
X 0 0 1 1 1 1 Counter State QA QB 1 0 0 0 1 1 0 1 0 1 0 1 JA X 0 0 1 X X FLIPFLOP Inputs KA JB 1 X X X 0 1 1 X 1 X 1 X KB X 1 X 1 X 1
This gives and
JB = KB = 1 JA = KA = (QB ¤ X)
The circuit is shown in Fig. it requires four FFs. FF0 : J0. 001. Prob.
Q3 0 0 Count Sequence Q2 Q1 Q0 0 1 1 0 1 0 J0 X 1 K0 1 X J1 X 0 FF Inputs K1 J2 1 X 1 X K2 X 0 J3 0 0 K3 X X (Contd. 8. The Q2 output will be the required output when the input waveform is used as the clock input.22(b). and 100. 8.) Table Prob. therefore. 8.
Logic 1 JB FFB KB Clock pulses x = 1 UP = 0 DOWN Fig. The unused states are taken as don’t care (X) conditions. 011. K3
The count sequence and the corresponding values of the FF inputs required to get the count sequence are given below.23 A divideby5 circuit will give the required inputoutput relationship. K0 FF1 : J1. 010.(Contd.24 Since there are ten states. The FFs with their inputs are given as follows.
Prob. the expressions for FF inputs can be minimized and the minimized expressions are: J0 = K0 = 1 J1 = Q1 ⋅ Q0 + Q3 ⋅ Q2 K1 = Q0 J2 = Q1 ⋅ Q0 K2 = Q1 ⋅ Q0 + Q3 ⋅ Q2 J3 = Q2 ⋅ Q1 ⋅ Q0 K3 = Q2 Using the FLIPFLOPs and the above expressions. 8. 8.25
107
.) Q3 0 0 0 1 1 1 1 1 0 Count Sequence Q2 Q1 Q0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 J0 X 1 X 1 X 1 X 1 K0 1 X 1 X 1 X 1 X J1 1 X X 0 1 X X 1 FF Inputs K1 J2 X 0 1 X X 0 1 X X X X 0 0 0 1 X K2 0 0 1 X X X X 1 J3 0 0 1 X X X X X K3 X X X 0 0 0 0 1
Using Kmaps.25.25 The circuit is given in Fig. 8.
Pulses Logic 1
QA ENT ENP
QB
QC
QD
74163 Load Cr
Logic 1 Fig.(Contd. the circuit can be drawn. Prob.
Prob.26(b) 1/0 01 0/0 00 1/0
(c)
Present State Q1 0 0 Q0 0 0 Input X 0 1 Next state Q1* 0 0 Q0* 0 1 108 Output Y 0 0 J1 0 0 FF FF1 K1 X X J0 0 1 Inputs FF0 K0 X X (Contd. 8.26 (a)
Q1
Q1 Q0
Q1
Q0
D1
Q1 FF1
Q1
Y Q0
Q0
X
D0
Q0 FF0
Q0
(b)
Clock Fig.8. Prob.26(a) 0/0 1/1 0/0 11 1/0 10 0/0 Fig. 8.)
.
27
(a)
D1 = Q1 ⊕ X D0 = Q0 ⊕ Q1 Z = Q1 ⋅ X + Q0
109
. 8. Prob.26(c)
Q0
Q0
8.(Contd.) Present State Q1 0 0 1 1 1 1 Q0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 Next state Q1* 0 1 1 1 1 0 Q0* 1 0 0 1 1 0 Output Y 0 0 0 0 0 1 J1 0 1 X X X X FF FF1 K1 X X 0 0 0 1 J0 X X 0 1 X X Inputs FF0 K0 0 1 X X 0 1
Q1Q0 X 00 01 11 10 0 1 0 0 0 1 ´ ´ ´ ´
Q1Q0 X 00 01 11 10 0 ´ 1 ´ ´ ´ 0 1 0 0
J1 = Q0× X Q1Q0 X 00 01 11 10 0 1 0 1 ´ ´ ´ ´ 0 1
K1 = Q0× X Q1Q0 X 00 01 11 10 0 ´ 1 Y = Q1 × Q0 × X ´ 0 1 0 1 ´ ´
J0 = X
K0 = X
X J1 FF1 K1
Q1
Q1
J0 FF0 K0 Clock Fig.
J0. 8. 8. state table as shown above is prepared and inputs to FF0 and FF1 are obtained using the excitation table of JK FF. the initial state has been assumed as Q1 Q0 = 00 and correspondingly the other states have been assigned. and X as the input variables as given below.
X Q1Q0 00 01 11 10 0 0 1 0 1 0 ´ ´ ´ ´ X Q1Q0 00 01 11 10 0 ´ 1 ´ ´ ´ 0 1 0 0
J1 = Q0× X Q1Q0 X 00 01 11 10 0 1 0 1 ´ ´ ´ ´ 0 1
K1 = Q0× X Q1Q0 X 00 01 11 10 0 ´ 1 0 ´ 1 ´ 0 1 ´ K0 = Q1 ¤ X
J0 = X Fig. K1.(b) The state table will be
Q1 0 0 1 1 1 1 0 0 Present State Q0 0 0 0 0 1 1 1 1 Input X 0 1 0 1 0 1 0 1 Next State Q1* Q0* 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 Output Z 1 0 0 0 1 1 1 1
Here. and K0 with Q1. From the table. we obtain the output sequence as 001110.28
Present Q1 0 0 0 0 1 1 1 1 State Q0 0 0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 0 1 Next State Q1* 0 0 1 0 1 1 1 0 Q0* 0 1 0 1 0 1 1 0 FF1 J1 0 0 1 0 X X X X K1 X X X X 0 0 0 1 J0 0 1 X X 0 1 X X FF inputs FF0 K0 X X 1 0 X X 0 1
From the state diagram.
110
.28(a)
The circuit can be drawn using the above expressions. Kmaps are prepared for J1. Q0. Prob.
These are T2 = Q 2 ⋅ Q1 ⋅ Q 0 ⋅ X + Q 2 ⋅ X + Q 0 ⋅ X T1 = Q 0 + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X T0 = Q 0 + Q1 X and Y = Q0 ⋅ X S2 = Q 0 ⋅ X + Q1 ⋅ Q 0 ⋅ X R2 = Q 0 ⋅ X S1 = Q 0 + Q 2 ⋅ X R1 = Q 2 ⋅ X + Q 2 ⋅ Q 0 ⋅ X S0 = Q 1 ⋅ Q 0 ⋅ X R0 = Q0 and Y = Q0 ⋅ X J2 = Q1 ⋅ Q 0 ⋅ X + Q 0 ⋅ X K2 = X J1 = Q 0 + Q 2 ⋅ X K1 = Q 2 ⋅ X + Q 2 ⋅ X J0 = Q1 ⋅ X K0 = 1
(a)
(b)
(c)
and
Y = Q0 ⋅ X The complete circuits can be drawn using the above expressions.28 (b)
8. 8.J0 FF0 K0 Clock X
Q0
J1 FF1
Q1
Q0
K1
Q1
Fig. and JK FLIPFLOPs are given in the Table. SR.29
The State table along with the inputs required for T.
111
. Prob. From this the simplified expressions for these inputs are obtained using Kmaps.
112
.
Present State Q2 Q1 Q0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 Input Next State Output X Q2* Q1* Q0* Y J2 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 X X K2 X X X X X X X X 1 0 FF inputs J1 K1 J0 1 0 0 1 X X X X 1 0 X X X X 0 1 1 1 X X 0 1 X X 1 0 X X 1 0 K0 X X 1 1 X X 1 1 X X
The simplified expressions are: J2 = Q 0 ⋅ X + Q1 ⋅ Q 0 ⋅ X K2 = X J1 = Q 0 ⋅ X + Q 0 ⋅ X K1 = Q0 + X J0 = Q 2 ⋅ Q1 ⋅ X + Q1 ⋅ X + Q 2 ⋅ X K0 = 1 Y = Q 2 ⋅ X + Q1 ⋅ X + Q1 ⋅ Q 0 The Complete circuit can be drawn using the above expressions. K1.30 Table 8.31 The state diagram is given below. Prob. and K0 required for the FFS is given below.8. 8. 8.
1/0 1/0
000 1/0
001 1/1
010 1/0 0/0
1/0
111 1/1 0/1 110 0/0 0/1 101 0/1 Fig.17 along with the inputs J2. J1.31 0/0
011 0/0
0/0
100
1/0
113
. J0. K2.
29(c). When X1.32 (a) The circuit can be designed using the method similar to that of Example 8. 8. Therefore.34(a) (i) by solid arrows. 01000111010 8.15. the next states and the outputs are same.27(b) and is given below. 8. 8. the state transitions will be 00 ® 11 ® 11
Shown in the Fig.28. 8. From this we observe that the states 000 and 010 are identical. the state 010 can be eliminated and the reduced state table is given in Table Prob. Table Prob. the states 011 and 111 are identical. 8. 8.30.31 (a).From Table 8.31(a)
Present State Q2 Q1 Q0
* Q2
Next State X=0 * * Q1 Q0 0 1 0 1 0 1 1 1 1 0 1 0
* Q2
X=1 * * Q1 Q0 0 1 0 0 0 1 1 0 1 0 1 1
Output Y X=0X=1 0 0 0 1 1 0 0 0 0 0 1 1
0 0 0 0 1 1
0 0 1 1 0 1
0 1 0 1 1 0
1 0 1 1 1 1
0 0 0 0 0 0
Table Prob. and 8.26(c).34 (a) (i) The circuit is initially in stable total state 0001 (first row. 8. Similarly. 8.
114
. 8. 8.33 The output sequence can be obtained similar to Prob. eliminating the states 100 and 111 we obtain Table Prob. (b) The circuit can be designed using the method similar to the design of Probs.31 (b)
Present State Q2 Q1 Q0
* Q2
Next State X=0 * * Q1 Q0 0 1 1 0 1 1 1 0 1 0
* Q2
X=1 * * Q1 Q0 0 0 0 0 1 1 0 0 1 1
Output Y X=0X=1 0 0 1 1 0 0 0 0 1 1
0 0 0 1 1
0 0 1 0 1
0 1 1 1 0
1 0 1 1 1
0 0 0 0 0
8.18 we observe that from the present states 001 and 100.31 (b). This means these two states are identical and one of them can be eliminated. X2 because 11. second column). Prob. Therefore.
34(a) (ii) Here again both the states are required to change.34 (a) (ii) 11 11 10
00 01 11 10
(b) In (a)(i) The circuit is required to change from stable state 00 to stable state 11 . If it is 10.34(a) (ii)
Q1 Q2 X1 X2 00 01 00 00 00 00 Fig. therefore. race condition exists and the circuit will either attain 01 or 10 state first. the circuit goes to 10 stable state from 10 unstable state. therefore. When X1 X2 becomes 01.34(a) (i)
Since. Prob. 8. race condition exists. state transitions will be 00 ® 01 ® 10 ® 10 Shown in the Fig. the state transitions will be 11 ® 00 ® 00 It is shown by solid arrows in Fig. 8.
115
. In (a)(ii). both the states are required to change here. The circuit will be making transitions. 8. 11 ® 10 ® 00 ® 00 or 11 ® 01 ® 00 ® 00 depending upon whether Q1 changes first or Q2 changes first.34(a) (i) by dotted arrows. Both are shown in Fig. 8. 00 ® 10 ® 10 (ii) The circuit is initially in stable total state 1111 (third row. Prob. Prob. If it is 01. Prob. but due to unequal time delays. the circuit goes to stable state 10 which shows that the race is critical. 8.X1 X2 Q1 Q2 00 00 01 11 10
01 00
11 10 11 10 11 10
Fig. Prob. third column).
35(a). Prob. When X1 changes to 1 while X2 = 0. again the next state specified is 00. the entry in the first row. These are shown in Fig. therefore. Prob.
+ + (b) Kmaps are prepared for Q1 and Q 2 from the state transition table. squares corresponding to input sequence are filled. These are shown in Fig. the next state specified is 00. first column will be 00 . 8.The state change is from 11 to 00 through both the paths and therefore. the entry in the first row.35 (a) Transition Table
For X1 X2 = 00. Prob.35 (b)
The next state logic equations are
+ Q1 = X 1 X2 + X2 Q1 + Q 2 = X2 + X1 Q2
116
.35(b). fourth column will be 00 .35 (a)
X1 X2 00 Q 2 Q2 00 01 11 10 00 00 – – 01 – 11 11 – 11 01 01 11 – 10 00 01 01 –
Fig. 8. Prob. 8. All the remaining squares are unspecified. 8. therefore. Similarly.
X1 X 2 Q1 Q2 00 01 11 10 00 0 0 ´ ´ 01 ´ 1 1 ´ 11 0 0 1 ´ 10 0 0 0 ´
X1 X2 Q1 Q2 00 00 01 11 10 0 0 ´ ´
01 ´ 1 1 ´
11 1 1 1 ´
10 0 1 1 ´
+ (i) Kmap for Q 1
+ (ii) Kmap for Q 2
Fig. 8. the race is noncritical.
the next state and the output are unspecified for X1 = X2 = 0 and the entry in the first column. When the circuit is in stable state f . When X1 X2 = 01. fifth row will be –. since the outputs for stable states f and a are 1 and 0 respectively.35 (c). Prob 8. it can not go to X1 X2 = 01. the input can change to 00 or 11. when X1 X2 = 10. Y = 1.36 When the circuit is in stable state e inputs can change to 01 or 10.(c) The logic circuit is shown in Fig. the output Y may be 0 or 1 and the nextstate will be b. therefore. the output may change during unstable b or stable b . sixth row will be –. Prob. therefore. therefore.
117
. When X1 X2 becomes 11.35(c) Logic diagram
8. Since for the stable state b . while transition from e ® b ® b . 8. If it changes to 00. the nextstate will be e and since X1 = 1 and X2 is changing state. From f . the entries in the second column. –. Y = 1 and the next state will be f and then f . is not possible when the circuit is in stable state e . –. X1 X2 = 00. therefore. Similarly. X2 has changed while X1 = 1. the nextstate will be a and the output may be 0 or 1.
X1
X2 X2 Q1 X1 Q2
Q1+
Q2+
Fig. the output is 0 and for the stable state e the output is 1.
the capacitor will get charged to voltage V(1) making the input to the inverter as logic 0 which produces logic 1 at the output. the output voltage will be maximum positive. It will saturate at vo = VD + VZ1. the output voltage vo will change from (VD + VZ1) to – (VZ2 + VD). vo = – (VZ2 + VD) This gives voltage at the noninverting input terminal as
− (V Z 2 + V D )
118
R2 R1 + V R1 + R 2 R1 + R 2 R
.. 9. This shows that it is not possible for vo to be in logic 0 state under steady state.e. This makes the voltage at the noninverting input terminal as R2 R1 (V Z 1 + V D ) + V R1 + R 2 R1 + R 2 R When the voltage at the input increases and passes through the above voltage.CHAPTER 9
9. Thus.1 t
9. Prob.
vc V(1) t V(0) t vo V(1) t
V(0) 0 T1 T2 Fig. vo = V(1). when vi > VUT . the output of the AND gate will be V(1) which will charge the capacitor C with the time constant t = RC. thereby discharging the capacitor with the same time constant through the output transistor of the AND gate.1 Let us assume that the voltage vc = V(0). the voltage corresponding to LOW level. 9. i. the output of the inverter goes to V(0). When vc reaches V(1). and so on. at t = 0. square waveform will be generated at the output. Hence R2 R1 (V Z 1 + VD ) + VUT = V R1 + R 2 R1 + R 2 R Now. The output of the NAND gate will be logic 1.2 Let vo be in logic 0 state under steadystate condition. The waveforms of vc and vo are illustrated below. Therefore.3 When the voltage vi at the input is very low.
2 V and remains at that level as long as the input voltage is higher than VLT.2 V
0
t
5. Now. As soon as the decreasing input voltage passes through VLT.4(b). the output is + 5. 9.When the voltage at the input decreases and passes through this value. Prob. 6 + 0. 1
» 0.1 ( 4. 9. the output changes from +5.4 Using the expressions for VUT and VLT derived in Prob.2 V. Prob. When the input voltage is zero. 6 ) + 100 (1) 100 + 0. 9. Prob.0042 V VLT = −
0. 1 100 + 0.1 100 + 0.2 V. The output waveform is illustrated in Fig. 6) + 100 (1) 100 + 0.2 V (b) Fig.9938 V The input waveform is shown in Fig.2 V to –5. 6 + 0. the output vo changes from – (VZ2 + VD) to + (VZ1 + VD). 1 ( 4. when the increasing input voltage passes through the voltage VUT.1
» 1. 9.
vi 5V VUT VLT 0
t
5V (a) vo 5. Hence VLT = −
R2 R1 (V + VD ) + V R1 + R 2 Z 2 R1 + R 2 R
9.4 119
. the output comes back to +5.3.4(a) with VUT and VLT marked. we obtain VUT =
0.
at which time the output will swing back from – Vo′ to + Vo′′ . where b = (R2/R1 + R2). during the interval T2 when the output is negative. vc = b Vo′′ b Vo′′ = Vo′′ – ( Vo′′ + b Vo′ ) e. the output voltage levels will be
Vo′ = VZ2 + VD1 – VD » VZ2
and
Vo′′ = VZ1 + VD2 – VD » VZ1
120
. Consequently. the capacitor will discharge with the same time constant from b Vo′′ to – Vo′ . However.9. Similarly. vc = b Vo′ b Vo′ = – Vo′ + ( Vo′ + b V o′′ ) e–T2/t T2 = t 1n
Vo′ + bVo′′ Vo′ (1 − b )
The charging and discharging will go on in the same way and the time period of the resulting output square waveform will be T = T1 + T2
1 1 and the frequency = f = = T T1 + T2
9. The capacitor voltage is given by vc = V o′′ – (Vo′′ + b Vo′ )e – t/t at \ or t = T1. Therefore.5 The maximum negative output voltage Vo′ and the maximum positive output voltage Vo′′ are given by
Vo′ = VZ2 + VD1
and
Vo′′ = VZ1 + VD2
Let us assume the output voltage to be maximum positive (V 0′′ ). The capacitor C will be charging from –b Vo′ to Vo′′ with the time constant t = RfC. the output voltage changes from positive maximum to negative maximum ( Vo′ ). vc = – Vo′ + ( Vo′ + b V o′′ ) e – t/t at \ or t = T2. the discharge will be terminated as soon as vc reaches –b Vo′ . the feedback resistance R¢f in series with the conducting diode D will be in the circuit. During the discharging of the capacitor.6 During the interval T1 when vo is positive. R¢¢ in series with the conducting diode will f be effective.T1 /t T1 = t 1n
Vo′′ + bVo′ Vo′′ (1 − b )
At T1.
i. 9. In case R¢f ¹ R¢¢f . t 2 = R ′′ C f Vo′ (1 − b )
and
The output voltage waveform is shown in Fig.8 When the output voltage is in logic 1 state. When the capacitor voltage passes through the voltage bVo. the capacitor C charges with the time constant t = RC. the capacitor discharges with the same time constant until its voltage becomes VLT.6
9.
v V ¢¢ o bVO¢¢ vc t2 t vo
t1 0
bV¢¢ O . t 1 = R′ C f Vo′′(1 − b ) Vo′ + bVo′′ .VO ¢ T1 T2 T3 T4
Fig. and R¢f = R¢¢. the output goes back to V(1). 9. Prob.7 If vo = –Vo under steadystate. At this voltage. the square wave f will be symmetrical..6. 9. This shows that the output voltage cannot remain as –Vo under steadystate. V(1). The charging gets terminated when vc reaches VUT and the output changes to V(0) = 0 V. 9. the output voltage will go to +Vo. Prob. Now. the capacitor C will get charged with the polarity opposite to that indicated in the figure. The timings T1 and T2 corresponding to the charging and discharging of C respectively are given by T1 = RC 1n T2 = RC 1n
V (1) − V LT V (1) − VUT
and
VUT V LT
121
. the periods T1 and T2 can be obtained using the relationships derived in Prob.5 and are given by T1 = t 1 1n T2 = t 2 1n
Vo′′ + bVo′ .If we assume identical Zeners for convenience.e.
6).VLT + 1n T = T1 + T2 = RC ê1n ú VLT û ë V (1) . 9. In this circuit when the output is positive.9 –
GREEN
and Let \
T2 = τ 2 1n
1+β 1−β
R1 = R2 = 100 kW. On the other hand. b =
1 2
and
C = 1000 mF
R¢f = 27. Prob. 9.7 RC Assuming R = 1. 7 × 1. 5 × 10 3
122
9.6 kW TON » 0.9 An astable multivibrator with T1 = 30 s and T2 = 60 s can be used for this purpose. 2 × 10 −6 ≈ 200 pF 0. we obtain (using the results of Prob. A circuit using OP AMP Schmit trigger circuit is shown below. Assuming identical Zener diodes.Hence.3 kW and R¢¢f = 54.10 (a) The pulse duration is given by
. T1 = τ 1 1n
1+ β 1− β
R¢ f R¢¢ f – +
D1 D2 R – R1 + + VZ VZ RED D3 D4 vo
C R2 Fig.VUT
9.5 kW C =
0. the diode D4 will conduct when the output is negative and consequently the GREEN bulb will be ON. diode D3 conducts and the RED bulb is ON.
VUT ù é V (1) .
5 × 10 −3 5 × 10 −3 ≈ 178. Prob. Therefore. the maximum frequency. fmax = 180 Hz 9.12 The frequency and duty cycle are given by 1. Therefore. Prob. 6 nF 0.8.(b) The pulse duration for C < 1000 pF is given by the graph shown in Fig. fmax =
1 ≈ 134 Hz 7.11 (a) Here R = 2 kW \C=
5 × 10 −3 = 3. 67
and the maximum frequency. 4 f= C (RA + 2RB ) and D =
(9. the time period. 7 × 40 × 10 3
(b)
C=
The duty cycle is 90% with an external resistance of 40 kW.1)
RA + RB × 100 RA + 2RB
123
(9. T =
5 = 7.
10000 7000 4000 2000 1000 700 400 200 100 70 40 20 10 122 123
TON Output pulse width. Assuming R = 10 kW.2)
.8
9. 57 µF 0. ns
R = 50 kW R = 30 kW R = 20 kW R = 10 kW R = 5 kW
1 2 4 10 20 40 100 200 400 1000 CEXT External timing capacitance. pF Fig. 5 m s 0. 9. 9. we obtain from the graph C » 35 pF. 7 × 2 × 10 −3
The duty cycle is 67% with the internal resistor.
is given by vc = 1 VCC + 2 VCC (1 − e − t / τ 1 ) 3 3 t = T1.13(b) and corresponding to the discharging is shown in Fig.13 (a) When the voltage across the capacitor (vc) is increasing and is less than 2/3 VCC. (9. When vc reaches 2/3 VCC. vc = 2 VCC 3
124
at
.12
9. Assuming RA = 1 kW
Now. Prob. As soon as this decreasing voltage crosses 1/3 VCC.13(a).13(c).
VCC
RA 4 8 7 2 555 6 + C 5 1 3 – vC vO RB
0. the charging starts again. Prob. 9. 9.12. (9. 9. (b) The circuit corresponding to the charging of the capacitor C is shown in Fig. 9. we obtain C=
1. 67 nF × 10 3 × 100 × 10 3 3
The circuit is shown in Fig.2) 60 = or
RA + RB × 100 RA + 2RB
RB = 2RA. Prob. vc.1).From Eq.01 mF Fig. the capacitor gets discharged through RA and RB with the time constant t2 = (RARB) C and the output voltage drops to 0 V. The waveforms of vc and output voltage. vo are illustrated in Fig. 4 ≈ 4. Prob. the output voltage is HIGH and the capacitor charges with the time constant t1 = RAC. 9. During charging the voltage across the capacitor. from Eq. Prob.
vC To VCC 2/3VCC t1 1/3VCC To 0V 0 T1 vo V(1) t T2 t t2
0 T (a) VCC RA RA vC + – vC C + – C RB VCC
(b) Fig. 9. Prob. vc is given by
RB RB é2 ù VCC ú e . vc =
1 3
VCC
R A RB é 2 R A .7 RAC
During discharging.7 t1 = 0.RB ù C 1n ê ú + RB RA ë RA .T1 /t 1 = 1 2 T1 » 0.t /t 2 + VCC vc = ê VCC R A + RB R A + RB ë3 û
at which gives T2 = t = T2.2 RB û
125
.13
(c)
\ or
e .
14 (a) The input pulses and the corresponding output for this monostable circuit of Fig. we obtain
RB R VCC < 1 VCC .13 c. Prob. or R B < A 3 2 RA + RB
9. 9. It remains HIGH for a period T = 1.
126
. The condition which must be satisfied to achieve this is 0.7 RAC + Duty cycle = T1/T ´ 100%
RA RB é 2 RA .14
A
B
The output is in LOW state until the first falling edge (A) appears.20 ù 1n ê ú = 0. 50% duty cycle). It will remain LOW till the next negative edge (B) appears.2 RB û
RB = 20 kW From part (a).7 R A RA + 20 ë RA . at which time it goes HIGH.2 RB û
(c) From the expressions for T1 and T2 obtained in part (b).40 û
or RA » 48 kW
(e) From Fig. we obtain
RA 20 é 2 RA .
T1 Input pulses Output 0 1 T Fig.35 are given in Fig. then the frequency of the output waveform will be
fo =
fi æ 1ö ç fi = T ø ÷ n è 1
Thus the circuit functions as a frequency divider. Prob.RB ù C 1n ê ú RA + RB ë RA .14. we observe that it is possible to make T1 = T2 (i.7RA = (d) If
R A RB é 2 R A . 9. Prob. 9.e. If (n – 1) T < T < nT1 where n is an integer.RB ù 1n ê ú RA + RB ë RA ..\ T = T1 + T2 = 0.1 RAC and then goes LOW. 9.
2 kW and C = 0.3 m s T = 1. thereby discharging C and the output goes LOW.e.1 RC. 9. if we choose RA = 2.35. 9. the output goes to HIGH for a time period T = 1.15 If the output is in HIGH state under steadystate. When the voltage across the capacitor reaches 2/3 VCC.16 In the circuit of Fig. the transistor goes to saturation. Thus.1 RAC
Therefore. 9.
127
. the output and the discharge terminals go LOW.242 m s 9.. the circuit is reset. i. if we connect pin4 (Reset) to pin2 (Trigger) it becomes a retriggerable monostable multivibrator. the circuit becomes a retriggerable monostable multivibrator. In this circuit.2 ms < T < 0. Hence. When the input pulse goes from LOW to HIGH. it is not possible for the circuit to be in HIGH output state under steadystate. whenever the trigger pulse goes LOW.1 mF then T = 0.35 such that Since 0. the transistor T1 of the timer is cutoff and the capacitor is therefore getting charged.(b) Here
T1 = 1 m s 10
Choose RA and C values in Fig.
1 10.3(b).5
Net Output Vo 0 1 2 3 –3 –2 –1 0
10.2
10 10 S = V.
128
.5 + 2.5
Output due to offset + 3.5 – 0.3 (i) Let b3 = 0.5 + 3. From this we observe that this circuit converts digital inputs in one’s complement format to analog output. i. 10. The analog output voltages for each of the digital inputs are given below.5 – 3.5 + 1.
The step size or resolution =
Digital Input S2 S1 S0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Output voltage without offset – 3. Prob. From this we obtain Iin
=
VR (8 /11R) × ( r + 8 /11R) r (8 /11R) 2R + ( r + 8 /11R ) VR 2R
The current due to b6 is \ or
V R (8/ 11R ) VR = 2 R( r + 8 /11R) + r (8/ 11r ) 16 × 2 R
r=8R
RF b2 2R r Iin +
VO
VR
R 4R 8R
Fig.5 + 3..3(a)
(ii) Let b3 = b2 = b0 = 0.3(a).e.5 – 1. Prob. The equivalent circuit corresponding to the lower order four bits is shown in Fig.CHAPTER 10
10.5 – 2.5 – 3. 10. 2 8 − 1 255 2 5/255 V the leastsignificant bit will be significant.5 + 3. and b1 = 1. As long as DV < .5 + 3.5 – 3. Prob. The corresponding equivalent circuit is shown in Fig.5 + 0. b2 = 1 and b1 = b0 = 0.5 – 3. 10.
4. Prob.ç R R /2 R /3 ø è
129
. we obtain r = 8R
RF b0 8R r Iin VR R 2R 4R +
VO
Fig. to satisfy the same condition. and b0 = 1 The equivalent circuit is shown in Fig. The analog output voltages for various digital inputs are given in table The output voltage is given by
RF RF æ RF ö Vo + V1 + V2 ÷ Vo = . 10. 10. Prob. 10. we obtain r = 8 R.Iin =
VR (8 /13 R) ´ r (8 /13 R ) ( r + 8 /13 R) 4R + r + 8 /13 R VR .3(b)
(iii) Let b3 = b2 = b1 = 0. 4R
The current due to b5 is
To satisfy the same condition. Prob. Therefore.
RF b1 4R r Iin +
VO
VR
R 2R 8R
Fig.3(c) from which we obtain Iin =
VR ( 4 / 7 R) × ( r + 4 / 7 R) r ( 4 / 7 R) 8R + ( r + 4 / 7 R)
The current due to b4 is VR/8R.4 The modified circuit will be equivalent to the circuit given in Fig. 10.3 (c)
10.
5 130
. Prob. 10.5. 10. Prob. Table Prob. 10. 10.S0
R RF = R R/2 +
S1
VO
S2
R/3 Fig.5 The circuit for 4bit D/A converter is shown in Fig.5 V for the digital input 0000 and
+ 1/2 V1 0 1 0 1 0 R/2 RF = R + VO R 0 1 S2 ROFF 1/2 V +
R/4
V (1) = 1/2 V
R/8 1 0 V (0) = 1/2 V Fig. This circuit without offset gives an analog output of –7.4
S2 0 0 0 0 1 1 1 1
Digital Inputs S1 S0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Analog Output V 0 +1 +2 +3 –3 –2 –1 0
We observe from the table that this circuit also converts digital input in one’s complement format to analog output. Prob.4
where
Vn = – =+
1 2 1 2
if Sn = 1 if Sn = 0. 10.
The decoder circuit can be designed in the usual manner.5 V for the digital input 1111. This voltage must be 0. R RX = 4 + 2 + 1 or RX = R/7
R R/2 R/4 R/7 S3 Fig.7 Let the analog voltage range be from –V0 to +V0. 10. ROFF = 15 10.R + R /4 + R /2 + R ÷ è ø X
where. Therefore.6 + VO
The resulting circuit is shown in Fig. Prob.
S0 S1 S2 RF = R
10.5 V for 0000 input and –7. the output voltage will be

1 2
RF RF RF ö æ RF ç . R Therefore. the offset required is +7.
131
. the resistor chain will be connected between +V0 and –Vo and only six comparators will be required. RX is the resistance in the path of switch S 3 . 10. The reference voltages are given below. Prob. Therefore.
Reference voltages V0 VR7 = 5/7 V0 VR6 = 3/7 V0 VR5 = 1/7 V0 VR4 = –1/7 V0 VR3 = –3/7 V0 VR2 = –5/7 V0 VR1 = –V0 –9/7 V0 0 2’s complement digital output S 011 010 001 000 111 110 101 100
If we choose to ignore 100 output.6 When the 4bit digital input is 0000. Prob. The step size will be 2/7 V0.6. The circuit is shown in Fig. 10.7.5 V for 1111 input. There is one more negative number than the positive numbers in 2’s complement representation.+7.
10. Therefore. Prob.
132
.7 – + – + – C5 Two’s complement format + – + – + – + – + C1 C2 C3 C4 L A T C H E S D E C O D E R C6 C7
B2 ü B1 ý B0 þ
ï ï
10. f < 12 per second.8 The conversion time t is given by
Va ⋅ 2 N ⋅ TC VR where.V R Va Analog voltage VR7 = +5/7 V0 R VR6 = +3/7 V0 R VR5 = +1/7 V0 R VR4 = –1/7 V0 R VR3 = –3/7 V0 R VR2 = –5/7 V0 R VR1 = –V0 R –9/7 Vo Fig. and VR is the reference voltage. The largest Va can be equal to VR. N is the number of bits in the digital output. TC is the time period of the clock. when Va = VR
t = 2 N ⋅ TC + t = 2 N + 1 ⋅ TC = 2 13 × 10 −5 or. f<
10 5 8192
Therefore. Va is the analog voltage.
10(b)
Analog input voltage range ± 2. It is obtained by complementing the natural BCD code. 10. for example.44 mV mV mV mV mV
(ii) Complementary coded decimal code (CCD) input The analog output range for this code is 0 to + 10 V. the straight binary code for decimal 2 is 0010.10.22 2.10(a) gives the voltage corresponding to LSB for each of the ranges.22 2.22 2.9 The voltage step =
=
10 V 26 −1
10 V 63
10. (c) CTC: It is complementary two’s complement code.88 1. natural BCD code
133
. decimal 2 will be coded as 1101 – 1000 = 0101.10 (a) DAC 80 is a 12bit D/A converter. Where n is the number of bits used to represent the number.10(a)
Analog output range 0 0 0 0 0 to ± 2. (d) CCD: It is complementary coded decimal code. For example. (i) Complementary binary input (CBI) Table Prob. (b) COB: It is complementary offset binary code.22 2. Decimal 2 will be coded in CSB as complement of 0010. 10. Therefore.88 1. 10.5 V ±5V ± 10 V 0 to 5 V 0 to 10 V Voltage corresponding to LSB 1.44 4.44 4. For example. which is 1101.5 V to ± 5 V to ± 10 V to + 5 V to + 10 V Voltage corresponding to LSB 1. For example. the voltage corresponding to LSD = 10/1000 = 10 mV (b) ADC 80 is a 12bit A/D converter.11 (a) CSB: It is complementary straight binary code. The voltages corresponding to LSB for various analog input ranges are given in Table Prob. it will be coded in CTC as 0001. Table Prob.44 mV mV mV mV mV
10. 10. two’s complement representation of – 2 is 1110 and therefore. It is determined by finding out CSB and then offsetting it by –2n – 1. Table Prob.10(b). It is obtained by complementing two’s complement.
11 gives the decimal number for each of the 4bit binary numbers in each of the above codes.for decimal 2 is 0010 and therefore. 10.11
Binary CSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Equivalent decimal values COB CTC +7 +6 +5 +4 +3 +2 +1 0 –1 –2 –3 –4 –5 –6 –7 –8 –1 –2 –3 –4 –5 –6 –7 –8 +7 +6 +5 +4 +3 +2 +1 0 CCD – – – – – – 9 8 7 6 5 4 3 2 1 0
134
. Table Prob. 10. Table Prob. it will be coded in CCD as 1101.
It is given below for each memory. 00 to 77. 00000 to FFFFF. 00 to 3F. 000 to 7FF. 00 to 17. 11.) 135
.2 (a) 0 to 3. 0000 to FFFF. (b) 0 to 3.3 The maximum access rate = 1/Cycle time gives the maximum rate for each memory. 0000 to 1777.CHAPTER 11
11. 000 to 377. 0000 to 3777. 0 to F. 000 to 3FF. 000000 to 177777. 00 to FF.
Memory A B Maximum rate
1 × 10 9 = 666666/s 1500 1 × 10 9 = 1724137/s 580
(Contd. 0000000 to 3777777.1 The number of pins P is given by 2P = M (a) P = 2 Address range: A1A0 = 00 to 11 (b) P = 4 Address range: A3A2A1A0 = 0000 to 1111 (c) P = 6 Address range: A5A4A3A2A1A0 = 000000 to 111111 (d) P = 8 Address range: A7A6A5A4A3A2A1A0 = 00000000 to 11111111 (e) P = 10 Address range: A9A8A7A6A5A4A3A2A1A0 = 0000000000 to 1111111111 (f) P = 11 Address range: A10A9A8A7A6A5A4A3A2A1A0 = 00000000000 to 11111111111 (g) P = 16 Address range: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (h) P = 20 Address range:
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11.
e.7 (a) For 4 K locations. (c) For obtaining 16 K bytes of RAM. Let us. IC1 has been used for the lower four bits and the lower chip. The most significant bit A11 of the address is used to select the chip and the other 11 bits A10A0 are applied to both the chips. The address bit A11 is applied at the chip select ( CS 1 ) input of ROM0 and its complement is applied at
136
. The upper chip. Prob. for convenience. 2lineto4line) decoder IC will be required. The most significant four bits of the addresses are to be used to select one out of the 16 sets.5 (a) which can be understood easily. Prob. 11. two chips of 2716 and one inverter are required. This decoder will select one out of the four chips depending upon the values of A10 and A11. number these sixteen sets as RAM0 to RAM15. (c) 16 K bytes = 16 K ´ 8 = (16 ´ 1024) ´ (4 ´ 2) = 32 ´ (1024 ´ 4) Therefore. 11. the address A0 – A9 is applied to both the chips. The complete circuit is shown in Fig. The lower ten bits of the address (A0 – A9) are connected to the address bus of each RAM chip. 11. therefore. (b) 2 chips of 2142. One 1out of16 decoder will be required to select a specific chip pair. 11. 32 chips of 2142 will be required.5 (b).5 (a) Since the total number of locations is 4 K. IC2 for the upper four bits.4 (a) 4 chips of 2142 and one 1out of4 (i. Here. For this purpose a 4lineto16line decoder circuit is to be used in a way similar to that used in Fig. (c) 4 K ´ 16 = 2 ´ 2 ´ (2 K ´ 8) The number of 2716 chips required is four. the width of the address bus required is 12.5 (b) are required.(Contd. 11. Prob.) Memory C D E F Maximum rate
1 × 10 9 = 2222222/s 450
6 1 × 10 9 = 5 ´ 10 /s 200
1 × 10 9 = 16666666/s 60 1 × 10 9 = 1250000/s 800
11. Prob. A0 – A9 will be same for all the 16 sets. (b) 2 K ´ 16 = (2 K ´ 8) ´ 2 This also requires two chips of 2716.5 (a). of the 8bit word. One inverter will be required to select one pair of 2716s. 16 sets of 1 K ´ 8 circuits as shown in Fig.. two 2142 RAM chips are connected as shown in Fig. (b) For obtaining 1024 ´ 8. and A10 and A11 are applied to a 2lineto4line decoder. 11. the width of the address bus required is 12. 11.6 (a) 4 K bytes = 4 K ´ 8 = 2 ´ (2 K ´ 8) Therefore.
11.0 I/O1 – I/O4
CS 1 CS2
+VCC A0 – A9 2142 RAM .2 I/O1 – I/O4
CS 1 CS2
A11
WE
OD
WE
WE
OD OD
2142 RAM . whereas A11 = 1 will select ROM1.7(b) shows 2 K ´ 16 ROM. 11. a oneoutofN decoder is used to select one of the N memory locations. use two sets of 2 K ´ 16 memory (Fig.8 (a) In the linear selection addressing. Figure Prob.8(a) shows as 4lineto16line decoder used to select one out of sixteen memory locations.7(a). Prob.7(a) illustrates the relevant portion of the circuit. 11. (c) For obtaining 4 K ´ 16 ROM. (b) Figure Prob. Prob.7(b)) and connect them as shown in Fig. Prob. 11.5(a)
CS 2 input.
137
D
A0 – A9
A
+VCC
T
A
B
U
(4
A10
2lineto4linedecoder
1
OD
–
0
B
WE
I
T)
. 11. Therefore.1 I/O1 – I/O4
CS 1 CS2
2 3 A0 – A9
+VCC S 2142 RAM . Prob. 11. The lower order eight bits of each of the 16bit words are stored in IC1 and the higher order eight bits are stored in the corresponding location in IC2.3 I/O1 – I/O4
CS 1 CS2
+VCC
Fig. For example. 11. Fig. when A11 = 0 ROM0 is selected.A0 – A9
WE
OD
2142 RAM .
7(b) 138
. Prob. Prob.7(a) 2716
A0 – A10
IC1
CS CS CS 2716
IC2
A0 – A10
ü ï ï ï 16bit output ï ý (D – D ) 0 15 ï ï ï ï þ
Fig.A0 – A9
2142 IC1 OD I/O1 – I/O4
WE
CS 1 OD CS2
2142 IC2 A0 – A9 I/O1 – I/O4
ï ï ï ï ï ï8bit output ý (D0 – D7) ï ï ï ï (D4 – D7) ï ï ï þ
(D0 – D3) ü
Fig. 11. 11. 11.5(b) (8 – B I T) D0 – D7 D A T A O0 – O7 O0 – O7 D8 – D15 B U S
CS 2 2716
2716 A0 – A10 ROM0
CS 1
O0 – O7
A11
A0 – A10
ROM1 O0 – O7 Fig. Prob.
8 (b). Prob 11. the X address is A1A0 which selects a row and the Y address is A3A2 which enables a column. Prob. 11.0
Memory location 0 Memory location 1 Memory location 2
ì 3 ï ï A2 Address ï ï inputs í ï A1 ï ï ï A0 î
A
1 4lineto 16line decoder 2
14 15
Memory location 14 Memory location 15
Fig.
0 1 2 3 Column Row 0
D00 1 of 4 Decoder DL A0
D01
D02
D03
ì ï A1 ï ï ï ï ï ï Row drivers ï í Diode ï matrix ï Column ïA enable 2 ï ï ï ï A3 ï î
1 of 4 Decoder DH
D10
D11
D12
D13
1
D20
D21
D 22
D23
2
4bit address
D30
D31
D32
D33
3
Column sense amplifiers
Chip select (CS) Data output Fig.8(b) 139
.8(a)
(b) In the coincident selection addressing. 11. Prob. Each memory element is placed at the intersection of a row and a column. The decoder circuitry consists of 1outofX and 1outofY decoders as shown in Fig. Here. a memory location is selected by applying an X address and a Y address.
C charges to logic 1 through T3. the ratio C2/C3 must be very large. Depending upon which Y is selected by making it 0. T1 and T2 will conduct and C will get discharged to logic 0 level. the logic level of C will be complement of input logic level. then during f2 = 1.
140
. therefore. the gates of the inverters are not held at VDD but are clocked so that T3 conducts only when f2 = 1 and not when f1 = 1. W = X). (iii) Associate Operation with Lower Bit Masked: The operation is similar to the operation of (ii) above. It is also possible to read more than one location at a time. The same data also appears at the D outputs following the arguments of (iv) above. even if the bit stored on C1 is 1. C3 charges from C2 forming a capacitive loop. On the other hand. C2 >> C3.e. Similarly. outputs of the OR gates are 1 irrespective of the logic level at W (i. which will disable the latches. Here.9a.12 (i) Association Operation: When A1A0 = 11. and
W = 1. The f2 needs to be 1 only long enough to allow C2 to charge from VDD through T3 and T4. the latches are enabled for the location by making the Y input 0. In general. the operation of the circuit will be similar to the operation explained in (i) above except that the output of the AND gate on the I1 side will always be 0. and W = 0. The output will be OR operation performed on all the selected outputs. match condition will be checked only for I0 bit. during f3 and f4 phases. 11. Therefore. 11.
(iv) Read Operation: When A1A0 = 00. and W = 1. the complement of logic level on C will be transferred to output capacitor (between drain of T6 and ground). in the circuit of Fig. Now.10 When the transistor T4 conducts. T2 is OFF). therefore. Therefore.9 The operation of this circuit is similar to that of the circuit of Fig. the power is always drawn from the supply throughout the clock cycle. otherwise it will be 1. if the data input bit is same as the bit stored (Q0). When T3 conducts. there is considerable reduction in power dissipation in this circuit. T4 also conducts. In order to charge C3 without causing appreciable voltage drop. (ii) Associate Operation with Higher Bit Masked: When A1A0 = 01.11 During the interval when f1 = 1. T1 will be OFF and C will continue at logic 1 level. The AND gate of D1 output is enabled. The output Y of the wiredOR gate will be 0 if both the data inputs match with the bits stored. 11. This happens when more than one address input is made 0. This logic level remains on C after f1 returns to logic 0. if the data input is 1. (v) Write Operation: When A1A0 = 00. the output of the AND gate is 1 for mismatch and 0 for match.11. 11. if the input is at logic 0.9(a). otherwise it is 1. the output Q0 of the latch appears at the corresponding D output. In contrast to this. The outputs of the NOR gates will be 0. The data outputs D1 and D0 are both 0.. the latches are disabled. independently of data input (since f2 = 0. Therefore. 11. The output of the EXOR gate will be 0.
11. Y0 – Y7 of each chip are connected to a common bus. Prob. the corresponding higher bit (I1) is latched into the latch and it also appears at the D1 output.13 Since 16 ´ 2 = 2 ´ (8 ´ 2). data outputs. therefore. it requires two chips..15. the association operation is performed for the lower bit (ii) above.14. Since the number of words is 8. The resulting system has 16 address inputs (Y0 – Y15).14 8 ´ 8 = 4 ´ (8 ´ 2) Therefore. 11. and mode control inputs of two 8 ´ 2 CAMs are connected as shown in Fig. it becomes a CAM of sixteen 2bit words.14 can be connected as shown in Fig. When there is matching. two 8 ´ 8 CAMs as shown in Fig. 8bit word CAM. i. the operation will be similar to the operation of part (a) above. the key is
141
. 11. Prob. 11.e. The first operation is to interrogate the MSB of all words for a 1 with all other bits masked. for designing a 16 ´ 8 CAM. Thus. The outputs will be 0 for matched conditions and 1 for mismatch conditions. Prob. 11.
I1 I0 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 D0 D1
A0 A1 I0 I1
8´2 CAM IC1 D1 D0
W
W
W
A0 A1 I0 I1
D1
D0
8´2 CAM IC2
Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
Fig. 11.13. the number of chips required is four. The data inputs. Prob. 11.13
11.(vi) Associate and Write at the Match Addresses: (a) When A1A0 = 01 and W = 0. 11. The circuit of 8 ´ 8 CAM is shown in Fig. (b) When A1A0 = 10 and W = 0. The matching will be performed for higher bits and the lower bit (I0) will be stored in the locations for which I1 match. therefore.16 It is a 16word.15 16 ´ 8 = 2 ´ (8 ´ 8) Therefore.
11. Prob. if several words indicate a match.14
I7 8 ´ 8 CAM
I0 Y0Y7 Y0Y7 D0 D1 D2 D3 D4 D5 D6 D7
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
W
D7 D6 D5 D4 D3 D2 D1 D0 8 ´ 8 CAM
Y8Y15
Y0Y7
I7 Fig. If only one word indicates a match. However. then the maximum valued word search is complete. then the CAM is to be interrogated again with key as 11XXXXXX. Prob. In case no match occurs when the MSB is interrogated.15
I0
1XXXXXXX. then the next key has to be
142
. 11.A7 A6 I7 I6
A5 A4 I5 I4
A3 A2 I3 I2
A1 A0 I1 I0
A1 A0 I1 I0 8´2 CAM
A1 A0 I1 I0 8´2 CAM
A1 A0 I1 I0 8´2 CAM
A1 A0 I1 I0 8´2 CAM
Y0 – Y7
Y0 – Y7
Y0 – Y7 D0 D4
Y0 – Y7
W D1
D7
D0 D6
W D1
D5
W D1
D3
D0 D2
W D1
D1
D0 D0
W
Fig.
11.17 11.18
11.19
11.20
01XXXXXX. This process is to continue till at the most all the bits of the words are interrogated. In any case no more than 8 interrogation cycles will be required to determine the maximum valued word. In the case of RAM, each word is to be compared sequentially. Therefore, the time required for the search will be dependent on the number of words stored which is sixteen in this case. The operation is similar to the operation of Prob. 11.16 with 1’s replaced by 0’s in the search process. A CAM is ideal for this. Because of the parallel search operation in CAM, just in one cycle, we can find out whether the word is already stored or not. If not, it can be stored in the next location available. In contrast to this, the search process is serial in a RAM which is time consuming and hence a RAM is not suitable for this purpose. The inputs and the outputs of all the CCDs are to be connected in parallel. The additional address bits are decoded and used to select one of the CCDs for read/write operation. The clock and write enable are also connected in parallel. For expanding word length, the address, chip select, write enable, and clock inputs of all the devices are connected in parallel. The number of data inputs and outputs are used independently. The number of inputs/outputs will be equal to the number of CCDs.
143
CHAPTER 12
12.1 The BCDtoExcess3 code converter’s truth table is given below.
BCD A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 Excess3 E2 E1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0
(a) For the design using PROM, a PROM of size 10 ´ 4 is required, but since PROM of this size does not exist, therefore, a PROM of size 16 ´ 4 is to be used. Data is to be stored in the PROM at the addresses corresponding to the BCD code, the data is Excess3 code. For example at the address 0000, the data stored is 0011 and at the address 1001 the data stored is 1100. (b) Logical expressions can be written for E3, E2, E1, and E0 outputs in terms of A,B,C, and D inputs. To reduce the hardware requirements, these expressions can be minimized using Kmaps.
A B C D
E3 E2 E1 E0 Fig. Prob. 12.1 (b)
The simplified expressions are: E3 = A + BC + BD E2 = B C D + B C + B D E1 = C D + CD E0 = D
144
The size of PLA required is No. of inputs =4 No. of outputs =4 No. of product terms =9 The circuit is given in Fig. Prob. 12.1(b). (c) The required size of PAL is No. of inputs =4 No. of outputs =4 Minimum number of =3 AND gates for each output The circuit is given in Fig. Prob. 12.1(c).
A E3 B E2 C E1 D E0
Fig. Prob. 12.1 (c)
12.2 Follow similar procedure as given in Prob. 12.1. 12.3 Prepare truth table and follow similar procedure as given in Prob. 12.1. 12.4 The inputs of two 82S100 devices are to be connected in parallel. This will result in 8 + 8 = 16 outputs. 12.5 The inputs I0 to IM1 are common for all the PLAs. Depending on the values of IM to IM+Q1, one of the output lines of the decoder will go LOW activating the corresponding PLA and disabling all the other PLAs. Hence, the number of inputs increases. 12.6 Architecture of a PLD refers to the attributes of the device significant to the logic of a design to be implemented. It includes. · Configuration of pins. · The size and the arrangement of the programmable array(s). · Configuration of the input and output interface logic.
145
8
Input I1
I1 I2 I2 I3 I3 I4 I4
Column 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29
Input/output IO1
IO 1 IO8 IO 8 O2
Column 2 3 30 31 6 7 10 11 14 15 18 19 22 23 26 27
O2 O3
O3 O4 O4 O5 O5 O6 O6 O7 O7
I5
I5
I6
I6
I7
I7 I8 I8
146
.7
Input I1
I1 I2 I2 I3 I3 I4 I4 I5 I5 I6 I6 I7 I7 I8 I8 I9 I9 I10 I 10
Column 2 3 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31
Input/output IO2
IO 2 IO3 IO 3 IO4 IO 4 IO5 IO 5 IO6 IO 6 IO7 IO 7
Column 6 7 10 11 14 15 18 19 22 23 26 27
12.12.
12. MUX–2. which means its output will be either same as input 0 or input 1. Reg. D. (a) Open all the inputs to the controlling AND gate. B. topmost cell will be selected and f will be 1. (b) Keep all the inputs intact (connected) to the controlling AND gate. Reg. Comb.12. Prob. whereas for x2 = 1.9 It has four multiplexers. MUX–1.10. Reg. Reg. Comb.
0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1
8 8 8 8 8 7 7 7 7 7 7 7 7
Comb. Reg. of product Terms 8 8 8 Output Enable pin11 pin11 Term Controlled Term Controlled pin11 pin11 Term Controlled Term Controlled pin11 pin11 Term Controlled Term Controlled pin11 pin11 Term Controlled Term Controlled Output Output pin/FF output feedback input feedback
0 0 0
0 0 0
0 0 1
0 1 0
Reg. F . G and H intact to the controlling AND gate and open all other connections. For x2 = 0. Reg. f = 1
147
. the cell second from the top will get selected and f = 0.11 Here the output of an AND gate controls the output. Comb. Comb. C. 12. Comb. Similarly. Reg. for x1 =1 when and when x2 = 1. E .
input feedback input feedback input feedback input feedback input feedback input feedback input
12. f will be obtained from the upper multiplexer. (c) Keep the connections corresponding to the inputs A.10 These are given in Fig. MUX–3 and MUX–4. comb. f = 0 x2 = 1. Comb. 12. Each one may be programmed to be in 0 or 1.
MUX – 1 MUX – 2 MUX – 3 MUX – 4 No.12 When x1 = 0. Table below gives all the possible conditions.
10 148
REGISTER FEEDBACK CD = 00
COMBINATIONAL FEEDBACK CD = 10
BIDIRECTIONAL I/O CD = 11
A=1
.Registered output B = 1
Combinational output B = 0
AR D Q SP
A=0
AR D Q SP
A=1
AR D Q SP
AR D Q
A=0
SP
AR D Q
AR D Q SP
A=1
SP
Q
A=0
AR D Q SP
AR D Q SP
Q
Fig. Prob. 12.
the output will be obtained from the topmost multiplexer and when x2 = 1.Therefore. when x1 = 1. When x3 = 0. it will be obtained from the next multiplexer. f will be obtained from output of top multiplexers’ structure. Similarly. The bits to be stored will be
0 1 1 0 1 0 0 1
149
.13 The truth table of the given function f is
x1 0 0 0 0 1 1 1 1 x2 0 0 1 1 0 0 1 1 x3 0 1 0 1 0 1 0 1 f 0 1 1 0 1 0 0 1
when x1 = 0. the complete circuit can be analyzed.
x1 0 0 1 1 x2 0 1 0 1 f 1 0 0 1
12. f will be obtained from output of bottom multiplexers’ structure. Now. the truth table will be as given below. when x2 = 0. the output will be from the topmost cell. and when x3 = 1 it will be from be next cell.
(b) Let the first 2 K bytes be in EPROM and next 4 K bytes be in the RAMs. 13. assuming single byte op code = 256.3 (a) 2142 is a 1024 ´ 4 bits RAM Therefore. The memory address space for the mPs are given below. Therefore. 13.2 The number of distinct combinations of 8bit words = 28 = 256 Therefore. only one 2716 chip is required. 4 K bytes = 4 K ´ 8 bits = 4 ´ 2 ´ (1 K ´ 8) bits = 8 chips 2716 is a 2 K ´ 8 bits EPRPM. the total number of instruction codes.3(a) 150
. The relevant connections are shown below.1 The memory address space is given by M = 2P where.CHAPTER 13
13. Prob.
Microprocessor 8080A 6800 8086 9900 Z8000 Memory address space 64 K bytes 64 K bytes 1 M bytes 64 K bytes 8 M bytes
13.
A8 – A15 8085 A WR
RD
AD0 – AD7 ALE A0 – A7 8212
CLR
DS2 MD
DS 1
+VCC Fig. P is the address bus width. The total number of instruction codes in 8085A mP is 246.
Other connections are indicated below: A0 – A10 from mP to A0 – A10 of 2716 A0 – A9 from mP to A0 – A9 of each of 2142 CS2 of each 2142 to Vcc
WR from mP to WE of each 2142
RD from mP to OD of each 2142
A10 A11 A12 (from mP) A13 A14 A15 (from mP) A0 A1 A2 8205
E1
0 1 2 3 4 5 6 7
To CS of 2716 To CS 1 of RAM set 1 To CS 1 of RAM set 2 To CS 1 of RAM set 3 To CS 1 of RAM set 4
E2 E3
Fig. Prob. 13.3(b)
(c) The address of various chips are given below.
Memory chips EPROM RAM pair RAM pair RAM pair RAM pair Starting address in hex. 1 2 3 4 0000 0800 0C00 1000 1400 Last address in hex. 07FF 0BFF 0FFF 13FF 17FF
13.4
(i) MVI A, 00H ; Load accumulator with zero (ii) SUB A ; Subtract A from A (iii) ANI 00H ; AND A with zero (iv) XRA A ; A EXOR A Note that the information beyond semicolon (;) are comments. 13.5 Let DE and HL pairs be pointers to source and destination memory locations respectively. The program is given below: LXI D, 0F00 H ; Initialize source pointer LXI H, 1F00 H ; Initialize destination pointer LXI B, 100H ; Initialize counter LOOP: LDAX D ; Load A with contents of source memory CMA ; Complement A MOV M, A ; Store in destination memory INX D ; Increment pointers INX H
151
DCX B MOV A, C ORA B JNZ LOOP
; Decrement counter ; Check counter for zero
NEXT: 13.6 The program is given below: LXI H, 0A02H ; Store destination address in HL pair LDA 0A00H ; Load A with first number MOV B, A ; Transfer to B LDA 0A01H ; Load A with second number CMP B ; Compare A and B JZ FINIS ; Go to FINIS if the two numbers are equal JC GREAT ; If CY = 1, (A) < (B) MOV M, A ; Otherwise (A) > (B) JMP FINIS GREAT: MOV M, B FINIS : 13.7 The following instructions will clear the memory location. LXI H, 01A0H MVI M, 00H 13.8 LXI H, A001H ; Initialize pointer MOV C, M ; Get the number of bytes in C INX H ; Increase pointer by 1 START : MOV A, M ; Get a byte of data in A REP : DCR C JZ STOP ; Stop at end of data INX H CMP M ; Compare JC REP ; If (A) < (M), try next number JMP START STOP: STA FF00H ; Store the smallest element END 13.9 ANI 0FH 13.10 LOOP: DCR 0 JZ FINIS IN DATA MOV M, A INX H JMP LOOP FINIS: MOV B, A
152
SOLUTION The operation performed by each instruction is given below: START: LXI H, BUFR ; Initialize HL pair with address BUFR MOV C, 0BH ; Initialize counter with decimal 11 LOOP: DCR C ; Decrease counter by one JZ FINIS ; Go to FINIS if counter = 0 IN DATA ; Input a byte from DATA port MOV M, A ; Move the byte to memory ; location pointed to by HL pair INX H ; Advance the pointer by one JMP LOOP ; Go to loop FINIS: MOV B, A ; Move the contents of A to B The operation performed by this program is to input ten bytes from input port DATA and store them in memory locations starting from BUFR. 13.11 N=3+3+1+1+1+1+1+1 = 12 bytes 13.12 (A) 0000 1000 (B) 1001 0011 ADD B 1001 1011 The result is not a valid BCD number. ADD B instruction must be followed by DAA instruction. The effect of this is given below: 1001 1011 0000 0110 Add 6 because the leastsignificant four bits do not represent a valid BCD digit 1010 0001 0110 0000 Add 60 because the mostsignificant four bits do not represent a valid BCD digit 10000 0001 = (101)10 13.13 Assume a set of ten keys for entering BCD number and a 7segment display for displaying this number. It is also assumed that BCDto7segment codes are stored in memory from the starting address 00XXH. The block diagrams for the input and output devices are shown in Fig. Prob. 13.13(a) and (b) respectively. Assume 01H and 02H as the port addresses of the input device and output device respectively. The addresses are decoded and proper signals are generated for Enable and Device Select terminals for reading and writing. The program can be written as MVI B, XXH LXI H, 0000H IN 01H ADD B MOV L, A MOV A, M OUT 02H
153
14 The last six instructions will be POP PSW POP H POP D POP B EI RET
154
.13
13. Prob.VCC
D (MSB) DecimaltoBCD Encoder (Inputs & outputs activelow) C B Inverting Tristate Buffer
D3 D2 D1 Data bus of mP b c d
A D0
Enable (a) Current limiting resistors VCC Common anode a b c f d e e f g a g
Data bus
Dtype Latch
Device Select
(b)
Fig. 13.
00F1H LDA 00F0H CPI 0AH JNC QUE ADI 00110000 B MOV M. CL DX: DH.17 Eight 8bit or four 16bit AX: AH. making it 20bit address.16 Refer to Table 13.19 CS = 2000H IP = 1A00H 20bit address of the next instruction byte will be fetched from 20000 + 1A00 21A00 H 13. The program is given below: LXI H.3
mP 8086 80186 80286 80386SL 80386 DX 80486 DX Pentium Address bus width 20 20 24 25 32 32 32
13.Here it is assumed that the interrupts are kept disabled during the execution of the subroutine. A JMP STOP QUE : MVI M.15 The ASCII code for decimal 0 is 0110000 and for? is 0111111. 13. DL 13. 00111111 B STOP: END 13. Actual physical 20bit address is this 20bit data plus the contents of the pointer register. 13. AL BX: BH.18 Four zeros at the leastsignificant four bit positions are appended to the 16bit segment register.20 20bit current address of the stack will be 24000 + A000 2E000 H
155
. BL CX: CH.
14.3
Y
The entity declaration is LIBARY IEEE.
I0 I1 I2 I3 AB Fig. Y: OUT STDLOGIC).Name of entity chosen is F_A
156
.5 LIBRARY IEEE. .4 (a) For 2input NAND gate ARCHITECTURE df_nand 2 OF NAND 2 IS BEGIN Z Ü NOT (X AND Y) AFTER 10 ns. Y : IN BIT. 14. IN STDLOGIC. END dfnand 2. B.3. Prob. 14. END NAND 2. and I3 and two select inputs A and B. Hyphen (–) is not allowed. character ‘ ’ is not permitted.CHAPTER 14
14. ENTITY MULTI4 IS PORT (IO. 14. A. I1. It contains all the allowed characters. ENTITY NAND 2 IS PORT (X. USE IEEE. (b) ENTITY NAND 3 IS PORT (A. USE IEEE STDLOGIC. starting character can not be a numeral.1 (a) (b) (c) (d) (e) (f) 14. I3.3 A 4:1 multiplexer is shown in Fig. 14. Y : OUT BIT). END NAND 3. No. Upper and lower case characters can be mixed. END df_nand 3. It has four data inputs I0. ALL. No. I1. B . END MULTI_4. There is one output Y. No. I2. C : IN BIT. 1164 ALL. (b) For 3input NAND gate ARCHITECTURE df_nand 3 OF NAND 3 IS BEGIN Y Ü NOT (A AND B AND C) AFTER 10 ns.2 (a) Yes. STD_LOGIC_1164. Yes. I2. Prob. No. Z : OUT BIT). Two consecutive underscores are not allowed.
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. B. S3. 14. S4. ENTITY FA IS PORT (A. R : OUT STD_LOGIC). S1. S. END COMPONENT. S6. C OUT Ü (A AND B) OR (B AND CIN) OR (A AND CIN) AFTER 10 ns. S7 COUT). COMPONENT NAND2 PORT (X8. END COMPONENT. S5). USE IEEE. END COMPONENT. END F_A.ENTITY FA IS PORT (A. ARCHITECTURE FA_STR OF F_4 IS COMPONENT NAND 3 PORT (X1. Y: OUT STD_LOGIC). END FA_STR. S4). Z: OUT STD_LOGIC). COMPONENT INV PORT (P : IN STD_LOGIC. STD_LOGIC1164. SIGNAL AB. N4 : NAND3 PORT MAP (A. Q : OUT STD_LOGIC). B. X3 : IN STDLOGIC. S3. S3). BEGIN S Ü ((NOT A) AND B AND (NOT CIN)) OR ((NOT A) AND (NOT B) AND CIN) OR (A AND (NOT B) AND (NOT CIN)) OR (A AND B AND CIN) AFTER 15 ns. CIN. COUT: OUT STD_LOGIC) END FA. N9 : NAND3 PORT MAP (S5. ARCHITECTURE FULL_ADDER OF F_A IS. X6. S6). S COUT: OUT STD_LOGIC). S1). ALL. X2. CIN: IN STD_LOGIC. S). N7 : NAND2 PORT MAP (B. N8 : NAND2 PORT MAP (A. I3 : INV PORT MAP (CIN. CIN.6 LIBARY IEEE. S2). S7 : STD_LOGIC. B. S4. B. AB). BB). CINB. END COMPONENT. N3 : NAND3 PORT MAP (A. CINB. CIN: IN STD_LOGIC. END FULL_ADDER. I2 : INV PORT MAP (B. BB. BB. B. CIN. S5. CINB). S6. S7). N6 : NAND2 PORT MAP (A. S2. BEGIN I1 : INV PORT MAP (A. S2. X5. X9 : IN STD_LOGIC. BB. N2 : NAND3 PORT MAP (AB. N5 : NAND4 PORT MAP (S1. CIN. N1 : NAND3 PORT MAP (AB. CINB. X7 : IN STDLOGIC. COMPONENT NAND 4 PORT (X4.
5
158
.A I1 AB
B I2
CIN I3 N 1 BB CINB N2 S2 S1
N5 N3 S3
S
N4 A B B CIN A CIN N6 S5
S4
N7
S6
N9
COUT
N8
S7
Fig. 14. Prob.