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Third Edition

R P Jain

CHAPTER 1

1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure being measured and can assume any value in the given range. (b) Digital. An electric pulse is produced for every person entering the exhibition using a photoelectric device. These pulses are counted using a digital circuit. (c) Analog. The reading of the thermometer is proportional to the temperature being measured and can assume any value in the given range. (d) Digital. Inputs are given with the help of switches, which are converted into digital signals 1 and 0 corresponding to the switch in the ON or OFF position. These signals are processed using digital circuits and the results are displayed using digital display devices. (e) Analog. It receives modulated signals which are analog in nature. These signals are processed by analog circuits and the output is again in the analog form. (f) Digital. It has only two possible positions (states), ON and OFF. (g) Digital. An electric pulse is produced for every vote cast by pressing of switch of a candidate. The pulses thus produced for each candidate are counted separately and also the total number of votes polled are counted. 1.2 (a)

(i) S1 OFF OFF ON ON (iii) S OFF ON S2 OFF ON OFF ON Bulb ON OFF Bulb OFF OFF OFF ON (iv) (ii) S1 OFF OFF ON ON S1 OFF OFF ON ON S2 OFF ON OFF ON S2 OFF ON OFF ON Bulb OFF ON ON ON Bulb OFF ON ON OFF

(b) (i) S1 0 0 1 1 (iii) S 0 1 S2 0 1 0 1 Bulb 1 0 Bulb 0 0 0 1 (iv) (ii) S1 0 0 1 1 S1 0 0 1 1 S2 0 1 0 1 S2 0 1 0 1 Bulb 0 1 1 1 Bulb 0 1 1 0

(c)

(i) AND

(ii) OR

(iii) NOT

(iv) EX-OR

1.3

1 Input A 0 1 Input B 0 0 1 2 3 4 5 t(ms) 0 1 2 3 4 5 t(ms)

1 AND 0

1 OR 0

1 NAND 0

1 NOR 0

1 EX-OR 0

1.4

Inputs A 0 0 1 1 B 0 1 0 1 (a) 1 0 0 0 Outputs of (b) (c) 1 1 1 0 0 0 0 1 (d) 0 1 1 1

The operations performed are (a) NOR (b) NAND

(c) AND

2

(d) OR

1.7 (a) NAND. NOR (c) NAND (a) Inputs A 0 0 1 1 B 0 1 0 1 (b) AND (d) OR AB 0 0 1 0 AB 0 1 0 0 Output Y 0 1 1 0 (b) EX–OR (c) A Y B 3 .5 For Fig.8 (a) A 0 1 Y 1 0 (b) A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1 A+B Y 0 1 1 1 1 0 0 0 (c) A 0 0 1 1 B 0 1 0 1 A 1 1 0 0 B 1 0 1 0 1. 1.6 (a) A 0 1 Y 1 0 (b) A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1 AB 1 1 1 0 Y 0 0 0 1 (c) A 0 0 1 1 B 0 1 0 1 A 1 1 0 0 B 1 0 1 0 For Fig.6 1. 1.

(d) \ Y = AB + A B Y = AB + A B = AB ⋅ A B Y = Y = AB ⋅ AB = Y1 ⋅ Y2 where. the logic system will change from positive to negative and vice-versa. the resulting truth table will be same as that of the AND gate. In the positive logic system. Therefore. but the results are equally valid for any number of inputs. (a) A + A B + A B = (A + A B ) + A B = A (1 + B ) + A B = A × 1 + AB = A + AB = (A + A ) (A + B) = A + B (b) AB + A B + A B = (A + A ) B + A B = B + A B = (B + A ) (B + B ) = A +B (c) A BC + A B C + AB C + ABC = A BC + A B C + AB (C + C ) = A BC + A B C + AB = A BC + A (B + B C) = A BC + A (B + B ) (B + C) 4 1. the higher of the two voltages is designated as 1 and the lower voltage as 0. (b) Repeat part (a) for NAND and NOR gates.9 . if all ones and zeros are interchanged in the truth table of the OR gate. we shall consider 2-input gates. (a) In the truth table of positive logic AND gate replace all zeros by ones and all ones by zeros. Similarly. On the other hand in the negative logic system.8 For simplicity. The resulting truth table is same as that of the OR gate. if 1s and 0s are interchanged. the lower of the two voltage is designated as 1 and the higher voltage as 0. A Y1 Y Y1 = AB and Y2 = AB B Y2 1.

11 (a) The realization of LHS requires. two inverters. two 2-input AND gates. and one 3-input OR gate.10 (a) A 0 0 1 1 B 0 1 0 1 AB AB 0 0 1 0 A + A B + AB 0 1 1 1 A+B 0 1 1 1 0 1 0 0 (b) A 0 0 1 1 B 0 1 0 1 AB 0 0 0 1 AB AB AB + A B + A B 1 1 0 1 A +B 0 1 0 0 1 0 0 0 1 1 0 1 (c) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A BC 0 0 0 1 0 0 0 0 AB C 0 0 0 0 0 1 0 0 AB C 0 0 0 0 0 0 1 0 ABC LHS 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 AB 0 0 0 0 0 0 1 1 BC 0 0 0 1 0 0 0 1 CA 0 0 0 0 0 1 0 1 RHS 0 0 0 1 0 1 1 1 1. A A B B (i) 5 (ii) .= A BC + AB + AC = C (A + A B) + AB = C (A + A ) (A + B) + AB = C (A + B) + AB = AB + BC + CA 1. whereas the realization of RHS requires only one two input OR gate.

(b) The realization of LHS requires two inverters. whereas the realization of RHS requires only three 2-input AND gates and one 3-input OR gate. four 3-input AND gates and one 4-input OR gate. three 2-input AND gates and one 3-input OR gate.12 (a) AB + CD = AB + CD = AB ⋅ CD 6 . whereas the realization of RHS requires only one inverter and one 2-input OR gate. A A B B (i) (ii) (c) The realization of LHS requires three inverters. A B C (i) A B C (ii) 1.

while the right hand side is realizable by two 2-input NAND gates followed by another 2-input NAND gate. 1.(b) (A + B) (C + D) = ( A + B) ⋅ ( C + D ) = ( A + B) + ( C + D ) (i) The left hand side of (a) can be realized by using two 2-input AND gates followed by one 2-input OR gate. Hence an AND-OR configuration is equivalent to a NANDNAND configuration.13 (a) A B A B Y C D (i) (b) A B A B Y C D (i) C D (ii) Y C D (ii) Y 1. Hence an OR-AND configuration is equivalent to a NOR-NOR configuration. the AND operation is commutative. while the right hand side is realizable by two 2-input NOR gates followed by another 2-input NOR gate. (ii) The left hand side of (b) is realizable by two 2-input OR gates followed by a 2-input AND gate. then the AND operation is associative. If A × (B × C) = (A × B) × C. This can be proved by making truth table as given below: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 (A × B) × C 0 0 0 0 0 0 0 1 A × (B × C) 0 0 0 0 0 0 0 1 7 .14 (a) Since A × B = B × A Therefore.

then (since EXOR operation is commutative and associative) (1 Å 1) Å 0 Å 0 Å 0 Å . From the Table we observe that the last two columns are not identical. =1 8 . = 0 Å 0 Å 0 Å 0 Å . therefore. A + B = B + A. To verify whether the NAND operation is associative or not. . =0 Å1Å0Å0Å0Å. the NAND operation is commutative. which means A ⋅ ( B ⋅ C ) ≠ ( A ⋅ B) ⋅ C This shows that the NAND operation is not associative. The associative property requires A + (B + C) = (A + B) + C which can be proved by making the truth table in a way similar to the truthtable of (a) above (c) Since. which means the EX-OR operation is commutative. . The associative property requires (A Å B) Å C = A Å (B Å C) This can be proved by making truth table 1. . (b) Since.17 Therefore. . . if only three of the variables are 1. then (1 Å 0) Å 0 Å 0 Å . = 0 (iii) Similarly. = 1 Å 0 Å 0 Å . A Å B = B Å A. . therefore. then (1 Å 1) Å 1 Å 0 Å 0 Å . By making a truth table similar to the truth table of (a) above we can verify that ( A + B) + C ≠ A + ( B + C ) 1. .16 1. which means the NOR operation is commutative.Since the last two columns of the truth table are identical.. .15 (a) Since = A ⋅ B = B ⋅ A . =1 Å0=1 (ii) If only two of the variables are 1 and all others are zero. we prepare the truth table as given below.. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A ⋅ ( B ⋅ C) 1 1 1 1 0 0 0 1 ( A ⋅ B) C 1 0 1 0 1 0 1 1 (b) Since. OR operation is commutative. the NOR operation is not associative. which proves that the AND operation is associative. . A + B = B + A . Two possible realizations are given on page 9: (i) If only one of the variables is 1 and all others are zero. .

Two pins are required for the power supply (VCC and GND). it is packaged as 14-pin IC. Take an N-bit binary number bN–1 bN–2 . . (b) 7404 is a hex inverter. (a) 7402 is a quad 2-input NOR gate. . (e) 7411 is a triple 3-input AND gate. Two pins are left free (NC). Each gate requires three pins. Since a logical variable can assume one of the two values (0 or 1) the number of possible combinations is 2N.18 1. Therefore. It is obvious from the above discussion that Z = 1. The number of pins = 4 ´ 3 + 2 = 14. 1. . (c) 7408 is a quad 2-input AND gate. The number of pins = 4 ´ 3 + 2 = 14. The number of pins = 2 ´ 6 + 2 = 14. This means there are four identical 2-input NOR gates. Hence it is a 14-pin IC. The number of pins = 3 ´ 4 + 2 = 14.19 In the same way we can try higher number of ones. (g) 7427 is a triple 3-input NOR gate.17 Y AÅBÅCÅD 1. (h) 7432 is a quad 2-input OR gate. . (d) 7410 is a triple 3-input NAND gate. . 9 . 000 to 11 . The number of pins = 3 ´ 4 + 2 = 14.A B C D AÅB AÅBÅC Y AÅBÅCÅD or A B AÅB C D CÅD Fig. b2b1b0 and write all combinations from 00 . if an odd number of variables are 1 and Z = 0 if an even number of variables are 1. 111 in normal binary ascending order. the four gates requires 3 ´ 4 = 12 pins. therefore. The number of pins = 5 ´ 2 + 2 = 12. . (f) 7420 is a dual 4-input NAND gate. two for inputs and one for output. The number of pins = 4 ´ 3 + 2 = 14. Since 12-pin IC package is not used.

22 1.1.55V = 0 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 AND Y1 0 0 0 0 0 0 0 1 OR Y2 0 1 1 1 1 1 1 1 Output NAND Y3 1 1 1 1 1 1 1 0 NOR Y4 1 0 0 0 0 0 0 0 1.21 (i) 7486 is a quad EX-OR gate. The number of pins = 3 ´ 4 + 2 = 14.20 1. A B C Y or A B C Logic 1 (b) A B C Y or A B C Logic 0 (c) A B C Y or A B C Logic 1 (d) A B C Y or A B C Logic 0 10 Y Y Y Y . (a) (i) 7408 and 7432 (ii) 7400 (b) (i) 7432 and 7408 (ii) 7402 Logic Circuit A 0.23 (a) Yes.4V = 0 2V = 1 Logic Circuit B –0.75V = 1 –1.

(a) Active-high (b) Active-low (c) Active-high (d) Active-low (a) Active-low (b) Active-high (c) Active-low (d) Active-high (a) A B Y C Y = A × B × C = (A × B) × (C) (b) A B Y C Y = A + B + C = (A + B) + (C) (c) A B AB Y C AB C Y = A ⋅ B ⋅ C = ( A ⋅ B) + C = ( A ⋅ B) ⋅ C = A⋅ B⋅C (d) A B C 11 Y .1. AND — by connecting one of the inputs to logic 0 OR — by connecting one of the inputs to logic 1 NAND — by connecting one of the inputs to logic 0 NOR — by connecting one of the inputs to logic 1.27 Yes.26 1.24 1.25 1.

1.28 (a) A Å B = A B + A B A Å B = AB + A B = AB + AB = A Å B (b) A ⊕ B = AB + AB A Å B = AB + A B = AB + AB A Å B = AB + A B = AB + AB (c) B Å (B Å AC) = B Å B Å AC = 0 Å AC = AC 12 .

5 + 0.125 = (10.875)10 Quotient Remainder 1 0 1 0 0 1 1 Thus (37)10 = (100101)2 Similarly.11100 2.2 (a) = 0.0011 = 1 ´ 23 + 1 ´ 22 + 0 ´ 21 + 1 ´ 20 + 0 ´ 2–1 + 0 ´ 2–2 + 1 ´ 2–3 + 1 ´ 2–4 = 8 + 4 + 0 + 1 + 0 + 0 + 0.1010 = 8 + 2 + 0.125 + 0.25 + 0.5 + 0.0625 = (13. (b) (255)10 = (11111111)2 (c) (15)10 = (1111)2 13 37 2 18 2 9 2 4 2 2 2 1 2 18 9 4 2 1 0 0 0 1 0 1 .CHAPTER 2 2.1 (a) 111001 = 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 16 + 8 + 0 + 0 + 1 = (57)10 (b) 101001 = 1 ´ 25 + 0 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 0 + 8 + 0 + 0 + 1 = (41)10 (c) 11111110 = 1 ´ 27 + 1 ´ 26 + 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 1 ´ 22 + 1 ´ 21 + 0 ´ 20 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254)10 (d) 1100100 = 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100)10 (e) 1101.625)10 (g) 0.1875)10 (f) 1010.125 = (0.

(d) Integer part: (26)10 = (11010)2 Fractional part: 0.25 0.5 ´2 ´2 0.5 1.0 ¯ ¯ 0 1 Therefore, (26.25)10 = (11010.01)2 (e) Integer part: (11)10 = (1011)2 Fractional part: 0.75 0.5 ´2 ´2 1.5 1.0 ¯ ¯ 1 1 Thus (11.75)10 = (1011.11)2 (f) 0.1 0.2 0.4 0.8 0.6 0.2 0.4 0.8 ´2 ´2 ´2 ´2 ´2 ´2 ´2 ´2 0.2 0.4 0.8 1.6 1.2 0.4 0.8 1.6 ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ 0 0 0 1 1 0 0 1... Thus, (0.1)2 = (0.00011001)2 The process may be terminated at the required number of significant bits. 2.3 (a) 1 1 1 1 0 0 ¬ Carry 1 1 0

1 0 +1 1 1 1 0 Final carry (b) 1 1 + 1 0 Final carry 2.4 (a) 01000 –01001 1 0 1 0 1 1 0 0

1 0. 1. 0.

1 1 0 0 1 1 0

¬ Carry 0 0 1 1

01000 + 10111 (2’s complement) 11111 Since the MSB of the sum is 1, which means the result is negative and it is in 2’s complement form. 2’s complement of 11111 = 00001 = (1)10 Therefore, the result is –1.

14

(b)

(c)

01100 Þ 01100 –00011 + 11101 (2’s complement) 101001 = + 9 Ignore 0011.1001 Þ 0011.1001 –0001.1110 +1110.0010 (2’s complement) 10001.1011 = + 1.6875 Ignore Quotient

375 8 46 8 5 8

2.5 (a)

Remainder 7 6 5 6 7

46 5 0

5 Therefore, (375)10 = (567)8 = (101110111)2 (b) Quotient Remainder 249 31 1 8 31 3 7 8 3 0 3 8 3

7

1

(c)

2.6 (a)

(b) (c)

Therefore, (249)10 = (371)8 = (011111001)2 Integer part: (27)10 = (33)8 = (011011)2 Fractional part: 0.125 ´8 1.000 ¯ 1 Thus (0.125)10 = (0.1)8 = (0.001)2 Therefore, (27.125)10 = (33.1)8 = (011011.001)2 11 011 100.101 010 = (334.52)8 (334.52)8 = 3 ´ 82 + 3 ´ 81 + 4 ´ 80 + 5 ´ 8–1 + 2 ´ 8–2 = (220.65625)10 01 010 011.010 101 = (123.25)8 = (83.328125)10 10 110 011 = (263)8 = (179)10

15

2.7 (a)

375 16 23 16 1 16

Quotient 23 1 0

Remainder 7 7 1

1 7 7 Therefore, (375)10 = (177)16 (or 177H) = (0001 0111 0111)2 (b) Quotient Remainder 249 15 9 16 15 0 15 16 F 9 Therefore, (249)10 = (F9)16 (or F9H) = (1111 1001)2 (c) Integer part: Quotient Remainder 27 1 11 16 1 0 1 16 1 B Thus (27)10 = 1BH Fractional part: 0.125 ´ 16 2.000 ¯ 2 \ (0.125)10 = 0.2H \ (27.125)10 = (1B.2)16 = 1B.2H = (00011011.0010)2 2.8 (a) 1101 1100.1010 10 = (DC.A8)16 (DC.A8)16 = 13 ´ 161 + 11 ´ 160 + 10 ´ 16–1 + 8 ´ 16–2 = (220.65625)10 (b) 0101 0011.0101 01 = (53.54)16 = (83.328125)10 (c) 1011 0011 = (B3)16 = (179)10 2.9 For each decimal digit write its natural BCD code (a) 46 = 0100 0110 (BCD) (b) 327.89 = 0011 0010 0111.1000 1001 (BCD) (c) 20.305 = 00100000.0011 0000 0101 (BCD) 2.10 For each decimal digit write its 4-bit Excess-3 code. (a) 46 = 0111 1001 (Excess-3) (b) 327.89 = 0110 0101 1010.1011 1100 (Excess-3) (c) 20.305 = 0101 0011.0110 0011 1000 (Excess-3)

16

0 1 2 : : 13 14 15 16 17 18 : : 29 30 31 G4 0 0 0 : : 0 0 0 1 1 1 : : 1 1 1 G3 0 0 0 G2 0 0 0 : : 0 0 0 0 0 0 G1 0 0 1 G0 0 1 1 3 1 1 0 0 1 1 Decimal No. which has three ones. we obtain 100111 001011 000011 101100 101000 2. form 6-bit Gray Code as given in Table 2. From Table 2.13 (a) Write the 7-bit ASCII code for each character (See Table 2. a 0 is to be attached as MSB and the resulting 8-bit code with even parity will be 00101110.P.P. JAIN = 1010010 0101110 1010000 0101110 1001010 1000001 1001001 1001110 (b) Write the 8-bit EBCDIC code for each character (See Table 2.9). Therefore. we obtain (46)10 = 111001 (Gray Code) 2. Therefore.9) R. For example. 0 1 2 0 : 17 : 30 31 32 33 : 46 : 62 63 G5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 G4 0 0 0 Table 2 G3 0 0 0 G2 0 0 0 G1 0 0 1 G0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 Similarly.8 formulate 5-bit Gray code as given below in Table 1.10) R. a 1 is to be attached as MSB and the resulting 8-bit code with even parity will be 11010010 Similarly.9) R.11 Starting from 4-bit Gray code given in Table 2.14 (a) Count the number of ones for every character from ASCII table and attach a 1 or 0 as the MSB for odd or even number of ones respectively.2. JAIN = 101001 011011 100111 011011 100001 010001 011001 100101 2.P. 17 .12 Writing the 6-bit code for each character (See Table 2. the code for l is 0101110 which has four ones. the ASCII code for R is 1010010. Table 1 Decimal No. JAIN = 11011001 01001011 11010111 01001011 11010001 11000001 11001001 11010101 (c) Write the 6-bit internal code for each character (See Table 2.

therefore. if binary to hexadecimal conversion is used.21 Let us consider the BCD code for 9 and find out its Hamming code for error correction.3. (b) Repeat part (a) for EBCDIC code.7 requires p2 = 1 odd parity for 4.18 Consider the following examples: (i) 7 0111 Þ 0111 –3 –0011 + 1100 (1’s complement) 4 10011 1 End-Around Carry (EAC) 0100 = 4 (ii) 3 0011 Þ 0011 –7 – 0111 + 1000 (1’s complement) –4 1011 = –4 in 1’s complement form From the above examples the rules of subtraction can be summarized as: (a) Add ones complement of the subtrahend to the minuend. add end-around carry (EAC) (c) If the MSB of the sum is 0. the minimum number of bits required to encode 56 elements of information is 6.19 100 ´ 20 ´ 8 bits. 8-bit ASCII code for R with odd parity is 01010010 (b) Repeat part (a) for EBCDIC code.16 (a) Since.5. R = 11010010 = D2 H and l = 00101110 = 2EH for even parity and R = 01010010 = 52H and l = 10101110 = AEH for odd parity. Decimal digit 9 Position BCD odd parity for 1. 2. the result is negative and it is in one’s complement format.17 In the 8 bit ASCII code with the parity bit. 2. 2.6. 8 bits are required to encode 130 elements of information.5. 25 = 32 and 26 = 64. the resulting format will be hexadecimal.In a similar way parity bit can be attached to every character. For example.6. 2.15 (a) Attach 0 or 1 as MSB to make the number of ones odd. (b) 27 < 130 < 28 Therefore. (b) If a carry is produced. 2. 2. 2.7 requires p1 = 1 odd parity for 2.3. the result is positive (d) If the MSB of the sum is 1.7 requires p3 = 1 ® 1 p1 : : : 1 : 1 : 1 2 p2 : : : : : 1 : 1 18 Hamming Code 3 4 5 n1 p3 n2 1 : : 1 : 1 : 1 : : : : : : : 0 0 : : 0 : 0 : 0 6 n3 0 : : 0 : 0 : 0 7 n4 1 : : 1 : 1 : 1 .20 132 ´ 7 bits. For example.

Hamming code is determined for each BCD digit and the complete sequence is given below. Decimal digit 0 1 2 3 4 5 6 7 8 9 Position ® 1 p1 1 0 1 0 0 1 0 1 0 1 2 p2 1 0 0 1 1 0 0 1 0 1 Hamming code 3 4 5 n1 p3 n2 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 6 n3 0 0 1 1 0 0 1 1 0 0 7 n4 0 1 0 1 0 1 0 1 0 1 19 .Therefore. Similarly. Hamming code for decimal digit 9 is 1 1 1 0 0 0 1.

1 (a) The number of covalent bonds breaking away increases with temperature. whereas in a metal an increase in the temperature results in a greater thermal motion of the ions.73 mV 3. 232 − 2 × 100% 2 = 161. (3.14% 3.2) From Eqs. (b) All the covalent bonds are intact at 0 K and hence there are no free charge carriers..4 I2 = 10 = e {(V2 – V1)/2 ´ 26} I1 or V2 – V1 = 52 1n 10 = 119.1) (3. whereas at room temperature some of the covalent bonds break away resulting in small conductivity.693 mV » 36 mV Since.3 From the V–I relation of the diode. This results in a decrease in the mobility and hence resistivity increases with temperature.5 (a) The circuit will be under steady-state at t = 20ms. V1 = 700 mV Therefore. V2 – V1 = hVT 1n 2 = 2 ´ 26 ´ 0. V2 = 700 + 36 = 736 mV Percentage change = 736 − 700 × 100% 700 or (b) = 5. and hence decreases the mean free path of the free electrons.616 I2 = 2. dQ =0 dt 20 . which decreases the resistivity of the semiconductor material.2 (a) Using the V-I relation of the diode.2).616 ´ 2 = 5.e.1) and (3. i.6% 3. 3.CHAPTER 3 3. we obtain and » I0 exp (V1/hVT) I2 = 2I1 » I0 exp (V2/hVT) I1 2 = exp (V2 – V1/hVT) (3. we obtain I1 » I0 exp (700/hVT) and \ or (b) I2 » I0 exp (750/hVT) I2/I1 = exp (50/2 ´ 26) = 2.232 mA Percent change = 5.

7V 0 -5V Id 1 mA 0 -0. VR = 5 = 0. 5 × 10 −3 dt τ IR ≈ Solving this with initial condition Q(0) = 10–9 C (part (a)).5 mA Excess Q Minority Charge 0 0 t 1. \ V1 R = 10 = 1mA 10 Q =I t Q = 1 ´ 10–6 ´ 10–3 = 10–9 C (b) The diode will turn off when excess minority charge has been removed.5 ´ 10–9 e–t Set Q = 0 for cut-off \ t = 1.099 ms 21 t tR t t tR t .∴ I1 ≈ Since. 5 mA R 10 The differential equation is dQ Q + = − 0. The recovery time constant tR = RCO = 10 ´ 103 ´ 10 ´ 10–12 = 0.1 ms Vi V1 = 0V 0 -V2 = -5V Vd 0.5 ´ 10–9 + 1. we obtain Q = – 0.099 ms (c) The various waveforms are given below.

1 = 3.. 1 ³ 4. Hence it is conducting in the active region.1 V) respectively.6 (a) Since the E-B junction is forward-biased. therefore the transistor cannot be in saturation. Then the base and collector voltages will be VBE. It may either be operating in the active region or in the saturation region. now IC < hFEIB which means the transistor is certainly operating in the saturation region. Therefore. sat RC V BB − V BE . therefore.1 ≈ 2 mA 3 The current IB remains same as in part (a). sat (= 0. the collector current IC and the base current IB are given by IC = and IB = VCC − VCE . (b) The value of RC required for the transistor to be in saturation is given by IC = VCC − VCE . 3 £ 127. If the value of RC used is more than 4. the transistor is conducting (i. Therefore.3. Therefore. sat RB 5 − 0. sat RB = 10 − 0. IC is flowing). 8 kW 3. ⋅ 6 − 0. let us again assume that the transistor is operating in the saturation region.8 V) and VCE. sat (= 0.7 kW \ The value of Rc just sufficient for saturation will be 4. Let us assume that the transistor is operating in the saturation region. with VCC = 6V.7kW. 33 mA 3 5 − 0.7 kW. 1 kW 2.27 kW 22 . sat RC or RC ≥ 10 − 0.1 mA Since IC>hFE IB. (c) The value of RB required to drive the transistor into saturation is given by IC ≤ h FE × or RB ≤ 100 ⋅ ≤ h FE I B V BB − V BE . 8 = 21 µA 200 = hFE IB = 21 ´ 100 = 2.e. the transistor will continue to be operating in the saturation region.

27 kW.5 V (b) For active region operation VCE − VCE . sat RC ≤ V BB − V BE .25 V 3. the range of VBB for active region is 0.8 23 . 8 = 233. sat ⋅ + V BE . 53 IC + 50 IB = 4.3 3.8 For the transistor to be in saturation VCC − VCE .The value of RB just sufficient to drive the transistor into saturation will be 127. sat + RE (IC + IB) = VBB Substituting the values. hFE (min) = R ⋅ V C BB − V BE . VBB < R B VCC − VCE .25 V Therefore. 8 2 100 < 3. 1 = 200 ⋅ 1 5 − 0. sat or. If a smaller value of RB than the value calculated above is used. sat RB ⋅ h FE R B VCC − V CE. cut–in £ 0. 3.5 V < VBB < 3. we obtain. sat RC h FE 5 − 0. sat 5 − 0. the voltage VBB £VBE. the transistor will be driven deeper into saturation.9 Assume the transistor to be in saturation. sat + RE (IC + IB) = VCC and RBIB + VBE. RCIC + VCE.1 < 100 ⋅ + 0.25 V (c) The range of VBB for saturation region is VBB ³ 3.7 (a) For the transistor to be in the cut-off region. sat RB ⋅ h FE or. sat RC ≥ V BB − V BE . Writing KVL equations for the collector and base circuits.

hence the transistor is not in saturation.sat = IB.05 V 24 .7 or. This helps in improving the switching speed of transistor circuit. IB = 8.2 Solving these equations. the voltage at B will change as soon as Vi changes because of the capacitive voltage divider. 5 mA = 2. 3. the voltages at B change with the time constant Ci (RB||Ri) If a capacitor C is connected across RB.096 mA and IB = –6.214 mA Since IB comes out to be negative.10 The equivalent circuit at the input of a transistor consists of input resistance Ri in parallel with the input capacitance Ci as shown in Fig.7 V in the active region. 5 µA 100 \ The minimum value of Vi required for the load transistors to be in saturation is Vi(min) = 25 ´ 10–3 ´ 10 + 0.43 ´ 10–4 mA \ IC = hFE IB = 8. Assuming VBE = 0.43 ´ 10–2 mA 3. IC = 0.43 ´ 10–2 mA and IE » –8.sat = 5V = 2. KVL for the base circuit will be [RB + (1 + hFE) RE] IB = 5 – 0.5 mA 2 kW 2.and 50 IC + 100 IB = 4.11 (a) For the load transistors IC.8 = 1. given below: C + Vi – Equivalent circuit at the transistor input B RB Ri Ci When fast changes occur in Vi.

3. (c) Assume T1 to be cut-off and T2 to be in saturation. 5 − 0. 042 mA 1 100 hFE IB = 150 ´ 0.042 = 6. 25 .8 V 5 2 ´5+ ´ 0. Similarly. therefore. (b). 8 Therefore.(b) Assuming the load transistors to be in saturation the equivalent circuit at their input will be as shown in Fig. the transistor is definitely in saturation. I B = = 0.3 mA 3.8 V 10 kW Vi 0. there is no current drawn from the supplies. (a).3 mA Since IC < hFE IB. if T1 is in saturation and T2 is cut-off then IC1 = I1 + I2 (d) V1 0V 0V 5V 5V V2 0V 5V 0V 5V Y 5V 0V 0V 0V It performs NOR operation. and the voltage at Y is 5 V. Now.12 (a) When both the transistors are cut-off. IC = 5 = 5 mA. the voltage Vi = VO can be determined using the principle of superposition and is given by Vi = VO = = 3. Since T2 is in saturation. æ VCC ö the voltage at Y will be 0 V. 8 − 0.8 5+2 5+2 (c) The base current IB1 = I B2 = 3.8 V (a) (b) Vi 5 kW 0. 8 mA 10 = 0. (b) When both the transistors are in saturation. the voltage at Y is 0V. which reduces to the circuit shown in Fig.8 V 10 kW 0. The currents I1 and I2 will be same ç = è RC ÷ ø and IC2 = I1 + I2.13 (a) Assume the transistor to be in saturation.

(c) When both S1 and S2 are closed.15 Now IC <hFE⋅IB Which means the transistor no longer remains in saturation. Therefore. IC = I + I1 = 5 + 1. the circuit will be as shown below: VCC RC T1 VCC RC T2 Now.075 = 6. I C = I + I1 + I2 = 5 + 2 ´ 1. Therefore. RC 3.075 mA assuming the transistor to be in saturation. it is conducting in the active region. Hence. if we again assume the transistor to be in saturation. 3. the transistor will be operating in the active region.075 = 7.16 The effective resistance = RC || RC = 2 26 . the total resistance in the collector circuit of T2 is RC || RC = RC/2 which means its collector current increases. 3. This requires the base current to be doubled for the transistor to remain in saturation. If this current flows through RC of driver. the voltage at its collector will be VO = 5 – 2 ´ 103 ´ 25 ´ 100 ´ 10–6 =0 Which shows that it is not possible to have a base current of 25 mA for each of the load transistor. Therefore. total base current will be 25 ´ 100 mA. I1 = (5 – 0.075 mA Since IC < hFE ⋅ IB Therefore. Therefore.7/4) = 1.14 The base current required for each transistor to be in saturation is 25mA.15 Let T1 be cut-off. the transistor continues to remain in saturation. the load transistors will not remain in saturation.(b) When S1 is closed. Therefore.

28. the VDS VS ID characteristic will be same as the characteristic for VGS = 0 in Fig. therefore. V 27 . mA Load curve 4 3 2 1 0 A 0 5 10 B VGS = 5 V 4 V 3 V 2 V 1 V VDS.RC ⋅ CO 2 3. 3. the time constant = VDS1 = VDD – VDS2 Take various values of ID and for each ID determine VDS2 from the curve of (a). (b) Transistor T2 acts as load for T1. VO = 5V VO » 0V Therefore. for a given value of ID.41(b). 3. the v-i characteristic of the load is that of part (a). and Vi = 5V. ID on the characteristic of Fig. ID. we get a load curve AB as shown below. From this we see that when Vi = 0. Therefore. Thus. Since the current ID is same in both T1 and T2. Calculate VDS1 and locate a point corresponding to VDS1. therefore. the voltage.17 (a) Since VGS = 0. the circuit functions as an inverter.

we can consider 28 .077 0. TC.026 0. 312 = 2 2 = I av = = 4. the fan-out of this combination will be 10.04 <1. The value of noise margin decreases with increased N. Therefore.984 hFE = 20 Noise Margin D1 0. (c) Fan out and noise margin increases with increase in hFE.14V. The current drawn from the supply I2 = Average current 3.015 Load gate transistors not in saturation ’’ ’’ VO 1. 6 − 1.055 <1.997 0.6 ´ 4. the load gates are in saturation and T1 and T2 are cut-off. T1 and/or T2 are in saturation and VO = 0.05 0.17 0. 6 − 0.04 <1. hence Y = Y1 = Y2 = 1 Corresponding to this.064 The voltage VO and noise margin D1 are given in Table. the load gate transistors come out of saturation.48 mW 4.04 Noise Margin D1 0. if N > 7. all the transistors TA. Therefore.055 1. The current drawn from the supply. (d) For hFE = 10.578 mW = 16.CHAPTER 4 4. 2 = 5.135 0.3 (a) Let us consider all the possible cases: Case I A = B = C = D = 0.578 mA Average Power drawn from the supply = VCC ´ Iav = 3.1 When the output of the driver gate is high. TB.2V. I1 = VCC − VO 3. 844 mA 640 RC when the output of the driver is low. 4.14 1. Alternatively. VO = 1.106 0.09 1. 312 mA 640 I1 + I 2 3.22 0. 14 = = 3.1 0.14 1. 844 + 5. Therefore. each gate will be able to drive 5 gates.09 1. and TD are cut-off.2 (a) & (b) hFE = 10 N 5 6 7 8 9 10 VO 1.

96 mW 4.6 ´ 9. for low output IL = 5. the propagation delay time-constant = RC ⋅ 2C O 2 = RC ⋅ CO which is same as the propagation delay time-constant of a single gate. Case IV A = B = 0 and at least one of the inputs to gate Q is LOW. the current drawn from the supply is IH = 3.1) When the output is high. Y = Y1 = Y2 will be LOW and this situation is similar to that of Case II. With wire-ANDing. The state of transistor T2 29 .844 ´ 2 mA Similarly. RB is the resistance in the base circuit of a load gate.4 (a) This circuit has active pull-up (consisting of T2 and 100 W resistor) instead of passive pull-up RC used in normal RTL gates. which means the base current of 5 + 5 load transistors can flow through R¢C and give same output voltage corresponding to logic 1 as the output voltage of each gate individually while driving 5 load gates. The transistor whose input is HIGH will be driven to saturation forcing the output voltage to LOW. Therefore. With load gates. Therefore. N is the number of load gates. Case III At least one of the inputs to gate P is HIGH and C = D = 0.equivalent collector resistance R¢C = RC || RC = RC/2. there is no problem of fan-out. Ci is the input capacitance of a load gate. the timeconstant will be æ RC RB ç 2 + N è ö ÷ × (2 CO + NCi ) ø (see Prob.312 ´ 2 mA \ Iav = 9. 4. the fan-out is 10. the propagation delay time-constant for a single driver (without wired-logic) is RB æ ç RC + N è ö ÷ × ( CO + NCi ) ø where.156 mW = 32.156 mA Power drawn from the supply = 3. This will lead to a situation similar to that of Case III. Consequently. (b) Without load gates. This will drive the corresponding transistors into saturation and consequently Y = Y1 = Y2 will be LOW and hence the load transistors will be cut-off. Case II At least one of the inputs of each gate P and Q are HIGH.

0. when the input Vi is HIGH. sat » 0.e.6 V) 640 W 450 W IB 100 W T2 IO 450 W/N P VBE. sat = 0 N O öù 450 æ 2. 2 − 0. 4.will always be opposite to that of T3. The output voltage VO will be HIGH. (b) If it is driving N load gates. 6 100 + 450 / N = = Writing KVL for the closed path P. Therefore.IB ³ IO \ öù 30 é 450 æ 2. T2 is in saturation and T3 is cut-off.0. 4. the output circuit corresponding to HIGH state will be as shown in Fig. When Vi is LOW.5. 8 100 + 450 / N 2.6 ´ç ê2 ÷ ú ³ 100 + 450/ N 1090 ê N è 100 + 450/ N ø ú ë û From the above equation..6 1 é ê 3. T3 will be in saturation.4(a).8 ç 100 + 450/ N ÷ ú 1090 ê N è øú ë û For T2 to be in saturation hFE. VCC(3. i. sat − V BE. Prob. sat 100 + 450 / N 3.sat » 0 V. 6 − 0.4(a) IO = VCC − VCE .8 V Equivalent input circuit of load gates Fig. sat − or IB = 450 I – VBE. 30 . if T3 is cut-off. T2 is in saturation (since T1 is cut-off) and vice-versa. we obtain N ³ 2. we obtain VCC – 1090 IB – VBE. Therefore. while T2 is cut-off and VO = VCE. Prob.6 . N ³ 3 since N is an integer.8 .6 2.

54 mA This will increase the fan-out to 17. (c) The relevant portion of the circuit is shown in Fig.5 volts.6 V 100 W T2A IC3A A = 1 T3A T3B T2B 100 W IE2B B = 0 Fig. I1 = I2 = . = IN. Prob. 7 mA 5 and IB = 0.8 + 0. ∴ I1 = 31 . 2 − 0 .2 V. Neglecting the base currents IE2B = I C 3 A = 3.5 (a) When all the inputs are HIGH the voltage at the point P will be Vp = 0. IO = 2.Since. 6 = N ⋅ I1 100 + 450 / N The values of I1 for various values of N are given in Table Table N1 30 40 50 60 70 I1 (mA) 750 585 480 403 349 The base current required for saturation for a normal RTL is about 300 mA. Prob.4(b). 4. but the noise margin D0 will be reduced from 0. which is very large.4(b) 4. 4.8 V to 0. 5 = 0. 5 − 1. whereas T2A and T3B are cut-off.7 – 0. 2 100 = 32 mA VCC = 3. . which means N can be taken as 70. Here T3A and T2B are in saturation.16 = 0. . Therefore. 6 − 0.7 = 1.

7 ´ 3 = 2.82 ´ 10 + 2.6 For a fan-out of 10. 4. This collector current must be same as the collector current of the single gate driving N gates which is given by NIL + I¢1 \ NIL + I¢1 = N¢IL + MI¢1 VCC(5 V) I¢1 RC T1 Y1 Y P1 IL VCC(5 V) R VCC RC T2 I¢1 Y2 IL P2 VCC R VCC RC TM I¢1 YM IL VCC R PN¢ M Gates wire-ANDed Fig.2 V. the collector current of T1 is given by. Prob.42 mA. IL = 0. 0. Assuming all the other inputs of load gates to be HIGH. The worst condition corresponds to the situation when the output transistor of one of the driving gates is in saturation and all others are cut-off.(b) In this case VP = 0. and IB = 0.7 shows the relevant portion of the circuit.8 + 0. but the noise margin D0 will be increased to 1. N¢ is the fan-out with the wire-ANDed connection. 4. Corresponding to this the output voltage at Y is VCE.82 mA Assuming T1 to be in saturation.sat » 0. Prob.7 The Fig. 4. N¢ IL + MI¢1 where. which means the input diodes of all the load gates driven from this combination are conducting.182 = hFE ´ 0.4 or hFE » 26 4.9 V \ I1 = 0.4 V.7 32 N¢ Load gates .26 mA This will reduce the fan-out to 6.

VP = 0. If we assume that the transistor T1 is in saturation. This shows that the circuit operates as a NAND gate. VCC – VP = R1I1 + R2IB1 Also I1 = (1 + hFE) IB1 IB1 = 5 − 2. If all the inputs are HIGH.7 V Since the voltage at P is higher than the voltage at the collector of T1. I2 = IB2 = I1 – I2 = 1. the assumption that T1 is in saturation is inconsistent.7 + 0. 75 + 2 VCC − VCE . sat = 0. sat 5 = 0.7 + 0. Hence T1 is in active region. Hence Y = 0.543 – 0. Therefore. 182 0.7 + 0.16 mA.8 When all the inputs are HIGH. (a) When all the inputs are HIGH. the input diodes will be nonconducting.2 + 0.66 (M – 1) 4.sat R1 + R 2 = \ 5 − 0. sat + VD + VBE. 093 mA 1.16 = 1. T1 will be in active region and T2 in saturation region. Hence Y = 1.3 V The voltage at the collector of T1 = VCE. 82 = N – 2. sat = 0. the corresponding input diode conducts and therefore. sat = 1.543 mA. IB1 cannot exist.7 + 0.9 V.383 mA Standard load = VCC − V D − VCE. 75 × 31 + 2 V BE 2 . sat = 0. which keeps T1. the voltage drop across R2 will reverse-bias the C-B junction of T1 and therefore T1 will definitely be operating in active region. VP = VBE1 + VD + VBE3. 2 × 10 3 = 49.9 If any input is LOW. sat + VD + VBE. therefore. then VP = VBE.7 V in active region. 7 − 0.8 = 2.or N¢ = N – (M – 1) I¢1/IL = N – (M – 1) 2.8 = 2. D2.8 = 1.2 V Here. In fact when T1 is conducting. and I1 = 1.8 + 0.182 RC 33 IC2 = N ⋅ I L + . the input diodes are non-conducting. and T2 cut-off. 093 N + 2. 2 = 1. VBE has been assumed to be 0. 4. 78 µA 1.

093 N + 2.10 (a) When at least one of the inputs is LOW.093 ´ 5 = 5.7 + 6. VP = V (0) + VD = 0.4 V.9 + 0. 465 = 12 .For T2 to be in saturation.2 – 0.4 V The 1 level noise margin = D1 = Vg + VZ + Vg – VP = 0.4 – 0. 045 mW 2 4.9 V Corresponding to this T1 and T2 will be nonconducting.8 = 8.7 V D0 = –V(1) + (VP – VDg) = – 5 + (2. active + VZ + VBE.182) ´ 5 = 18.2 + 0. VP = VBE. VCC – VP = R1 (1 + hFE) IB1 + R2 IB1 34 . N < 36 Therefore.465 mW The average power Pav = = P ( 0 ) + P (1) 2 18.2 V (b) When all the inputs are HIGH. IC2 £ hFE IB2 or.6) = – 3.182 £ 30 ´ 1.9 = 0.12.5 + 0. the power P (1) = I1 ´ Vcc = 1.5 – 0. When all the inputs are HIGH. T1 will be conducting in active region. 1.543 + 2.625 mW When the output is HIGH.7 = 0. the fan-out of this gate is 35 which is much higher than the fanout of the DTL gate of Fig. the power P (0) = (I1 + I¢1) VCC = (1. (b) Noise margins D1 = 0.6)] = – 7. 4.383 or.5 – 0.9 =7V The 0 level noise margin = D0 = – [V (1) – (VP – VDg)] = – [15 – (8. sat = 0.6 + 0. Therefore. 625 + 5.9 + 0.5 + 6. Writing KVL from VCC to VP.4 V (c) When the output is LOW. VP = 8. Zener will be in the breakdown region and T2 in saturation.

or. (c) N £ 76 P(0) = (I1 + I¢1) ´ VCC = (2.8 + 0. 4 = R1 (1 + h FE ) + R 2 3 ( 41) + 12 = 0.1 mW \ Pav = 29.9867 mA N¢ = N – (M – 1) I¢1/IL = N – 1.844 or. Therefore. 4 35 .94 ´ 15 = 14. VB1 = 0.004 – 0.95 mA \ IC2 = 0. Since the temperature sensitivity of a Zener diode is positive whereas for a forwardbiased diode it is negative.8 + 0. therefore.94 mA.9867) ´ 15 = 44. The input diode and the base-emitter junction of T1 are in polarity opposition.0489 = 2. IB1 = VCC − V P 15 − 8.86 mW P(1) = I1 ´ VCC = 0. I¢1 = 0. 857 mA 1.48 mW 4. I1 = 41 ´ 0.9867 + 0.0489 mA The current through Zener diode. In HTL.2 = 1V Current through RC2 = 5 −1 = 2. the temperature sensitivities of these two junctions cancel. Hence the temperature sensitivity of the HTL gate is significantly better than that of the DTL gate.16 = 1. 9867 mA 15 The load current IL = 0. the temperature sensitivity of the circuit depends on the temperature sensitivities of D2 and the base-emitter junction of T2. 4.8 = 2.004 + 0.95 N £ 40 ´ 1. therefore.13 (a) When the output is LOW. 8 = 0. 3 = 0 . 675 mA 4 VC2 = 0. D2 is replaced by the Zener diode.11 IL = 0. Base-collector junction of T1 is forward-biased T2 and T3 are in saturation. Therefore.3 V Current through RB1 = 5 − 2.004 mA \ IB2 = I1 – I2 = 2.7 + 0.12 The noise margins depend upon temperature because the voltage across a conducting diode and VBE are temperature dependent.844 mA The current through RC = 14. the temperature sensitivities of Z and the base-emitter junction of T2 cancel (their magnitudes are of the same order).03 (M – 1) 4.

2 = 46 mA 100 = which is very large and will increase significantly the power dissipation.857 = 3. (b) When the output is in LOW state.11 = 1.675 + 2.385 mA 4. 2 − 0. 4 36 .15 (a) If RC4 = 0. 4. 5 mA 1. T3 and T4 are cut-off \ ICC1 = Current through RB1 = 5 − 0.7 = 0. T4 and D are cut-off. This means T4 will be in saturation and its collector current would be IC4 = VCC − VCE 4 . \ VB1 = 0. 9 4 = 1.15. IC4 = 0 Therefore. sat − VCE 3.14 The current I remains same and it does not affect the fan-out of the gate G1.36 = 42. 4.Since.8 V if the diode D is not present.2 + 0. VB4 = 1 V which makes VBE4 = 0. 7 = 2. therefore.10 and 4. Prob. 8 − 0.025 mA (c) The total current will be sum of current through RB1 (as given in (b) part above) and given in Eqs. (c) (i) When output is in LOW state. both T3 and T4 will be conducting simultaneously for some time which will cause almost short circuiting of the VCC supply.9 T2. The base current and the collector current of T4 will become IB4 = = VCC − V BE 4 . the change in output from logic 0 to logic 1 will be faster. it is simply a wastage of power. 4. (ii) When output is in HIGH state.sat − V D RC 2 5 − 0 . sat 100 5 − 0.532 mA (b) At least one of the inputs is LOW. Moreover. therefore. Since T3 does not turn off (because of storage time) as quickly as T4 turns on. the relevant portion of the circuit with output shorted to ground is shown in Fig. the shorting of output to ground will not have any effect.025 + 41. ICC(0) = 0.

6 = 4.5 mA This large current will continuously be drawn from the supply as long as at least one of the inputs is LOW. which will make the transistor T4 of the gate whose T3 is cut-off to conduct through T3 of the other gate which is in saturation. while that of the other gate is cut-off.56 kW 4. 44 kW I OL + 8 I IL 16 − 8 × 1. Prob.17.44kW < RC < 4. The corresponding current drawn from the power supply will be IC4 + IB4 = 41. 4. 4. 4 = = 1. VCC = 5V RC4 = 100 kW RC2 = 1. (i) When the output Y = 1.56 kW RC(min) = Therefore. 4. Prob. This continuous current will damage these transistors. This will damage the transistor T4 and the diode D.15 4. 2 − 0.and IC4 = VCC − VCE 4 . When both the outputs are HIGH or LOW. The voltage at Y will be LOW.18 The relevant portion of the circuit is given in Fig.5 = 43.4 kW T4 IB4 C2 E2 C3 D Is IC4 E3 Fig. 4. Prob.18.17 The circuit is shown in Fig. 4) × 10 3 kW = I OH + 8 I IH 250 + 8 × 40 VCC − VOL 5 − 0.16 Let the output transistor T3 of one gate is in saturation. RC(max) = VCC − VOH (5 − 2. VCC – (5 IOH + 6 IIH) RC ³ VOH 37 .4 mA. the currents drawn from the supply will be same as the currents without this connection. 1.sat − V D RC 4 5 − 0. 7 = 41 mA 100 = \ Is = IC4 + IB4 = 41 + 2.

17 VCC = 5 V IOL IOH IOH IOH IOH IOH Fig. 4 ) × 10 3 kW = 1. 4. Prob. Prob.which gives RC(max) = VCC − VOH ( 5 − 2 .18 38 RC Load gates IIH IIL IIH IIL IIH IIL IIH IIL IIH IIL IIH IIL Y . 74 kW = 5 I OH + 6 I IH 5 × 250 + 6 × 40 VCC = +5 V RC IIH IOH Output circuit of open-collector gate Fig. 4.

(i) ALS driving standard devices IOH (ALS) = – 400 mA IOL (ALS) = 8 mA (74 series) IIH (Standard) = 40 mA IIL (Standard) = – 1.19 Let us assume a supply voltage VCC = + 5V and corresponding VOH = 2.159 kW 40 − 7 × 1. 6 = Therefore.21 Let us take ALS devices driving other devices.6 mA 39 .28 kW 4.74 kW. 30 A Lamp 7407 Fig. 4.4 V \ RC(max) = RC(min) = ( 5 − 2. VCC − VOL £ IOL + NIIL RC which gives RC(min) = VCC − VOL I OL + NI IL 5 − 0. 4 ) × 10 3 ≈ 1. Prob.159kW < RC < 1.(ii) When the output Y = 0. 28 kW 7 × 250 + 7 × 40 5 − 0.20 7407 is an open-collector non-inverting buffer with VOH = 30V (maximum).20 (a) No (b) No (c) No VCC = +5 V A (d) Yes VCC = +10 V 10 V.20. 4. 0. 4. it is assumed that only one of the driving gates has its output transistor in saturation while the output transistors of all the other gates are cut-off. 72 kW 16 − 6 × 1.72 kW and 1. Prob. 4. 6 and Therefore. which means a lamp load along with the necessary supply voltage may be connected as shown in Fig. A value of RC = 1 kW is reasonable. 4 ≈ 0. 4 ≈ 0. RC should be between 0.

Then the output circuit will appear as shown in Fig.18 Vn = 0. 3 Since T4 is operating as an emitter-follower. Prob.22 Case I Let T2 be cut-off. whereas it is 10 when the output is HIGH. Prob. Similarly.797 Vn) = – 0. = 1. the fan-out is 5.18 + 0. the fan-out is 20.22(b).998 Vn = (b) VYP = – (Vn – VYQ) = – 0. (a) The noise voltage at the collector of T2 = the noise voltage at the base of T4.22(a). 1. and – IOH (ALS) = 10 ´ IIH (Standard) – IOL (ALS) = 5 ´ IIL (Standard) This means. whose equivalent circuit is shown in Fig. the noise voltage present in the output is negligibly small. 4.002 Vn Therefore. 797 Vn . Case II Let T2 be conducting and T1 be cut-off. P RC2 T4 Vn RE4 Q (a) Fig. we obtain (a) VYQ = R E 4 (1 + h FE ) V R C 2 + (1 + h FE ) R E 4 n 1. 5 (101) V 0. if the terminal P is grounded.203 Vn 40 . Prob. Therefore.1 mA Which gives a fan-out of 20 when the output is HIGH and 80 when it is LOW.22 (b) Y Vn RC2 B4 I E4 RE4 Q C4 hFE I Y P From the equivalent circuit. 4. 5) n = 0. the complete table can be verified. 3 + (101) (1. Therefore. VYQ = 0. 4. 4. when the output is LOW.797 Vn (b) VYP = – (Vn – 0. the fan-out is 5 (ii) ALS driving ALS IIH (ALS) = 20 mA IIL (ALS) = – 0. therefore.Here.

75 V) T4 RC2 RE4 Fig. 4. the output transistor will burn out.e.2 V supply will appear across RE4 or RE3 and no damage is caused to the supply and the circuit. D = 1.48V VIL MC10H125 Translator (b) Input/output logic level voltages of Translator Fig. 4.2 V 4.4 mA is produced.5V –0.This again shows that the noise voltage is very small between Y and P and hence the terminal P is grounded. (b) The 5. Y1 = 0 and Y2 = 1. whereas in the case of ECL the change in current is negligibly small when the output changes from LOW to HIGH and vice-versa. Prob.26 The output logic levels of ECL. when Y1 = 1 and Y2 = 0 identical situation will prevail making the output 1.8 VIH VIL 0. 4. VCC = 0 VCC = 0 RC2 (-0. Also 5.55 V) -5. Prob.25.9V VOH VOH 2V 0.26 2. the voltage across T4 acting as a diode).13V VIH –1. Prob.26 41 –1.85 V) T4 Y1 RE4 (-1. 4.5V VOL –1. Similarly. when the output changes from V(0) to V(1).2 V Y2 (-0. it can be proved for all the other cases. the output will be equal to Y1 = Y2.2 V supply voltage will appear across the output transistor T4 or T3.2 V supply gets applied to their bases through RC2 and RC1 respectively. Corresponding to this T4 of G1 is acting as an emitter follower while that of G2 is acting as a diode. 4. Therefore. When Y1 and Y2 both are same. and E = 0 Therefore.25 -5. 4.7V VOL ECL (a) Output logic level voltages of ECL TTL (c) Input logic level voltages of TTL .23 (a) The 5. In this when Y1 and Y2 are connected together. Similarly. This confirms that OR operation is performed when the outputs are connected in wired logic. and the input logic levels of TTL are shown in Fig. 4.24 In a TTL gate. The relevant portions of the circuits are shown in Fig.75 V (i. a current spike of 41.. input/output logic levels of MC10H125 IC. the voltage at the output terminal will be equal to – 0. Consequently T4 goes to cut-off.25 Let A = B = C = 0. Prob.

VIH (TTL) < VOH (Translator) VIL (TTL) > VOL (Translator) which shows that the output of the translator is compatible with TTL. A B ECL Y Y MC10H125 Translator Fig.25. Prob.27 The output Y of ECL NOR gate is Y = A + B The output of the Translator circuit is Y and the output of TTL Inverter will be Y = Y. Now if the output gets shorted to ground. since T2 is not meant to carry such large currents.29 Its operation is given below Inputs A 0 0 VCC VCC B 0 VCC 0 VCC T1 OFF ON OFF ON State of T2 OFF OFF ON ON T3 ON OFF ON OFF T4 ON ON OFF OFF Output Y VCC 0 0 0 42 . On the other hand when Vi is LOW.28 (a) Consider the NMOS inverters shown in Fig. When T1 is ON. This will cause a relatively very high current to flow through T2 which may damage it. whole of VCC will appear across T2 which is conducting. and if the output gets shorted to ground. 4. 4. Similarly. large current from VDD will continuously flow through the load transistor T2 which may damage the load transistor. (b) Consider the CMOS inverter of Fig. it does not cause any problem. 4. The normal current through T1 and T2 is extremely small being the OFF current of either T1 or T2. the output voltage is LOW (» 0V). 3. we observe.27 Y TTL The complete circuit is shown in the above figure. VIH (Translator) < VOH (ECL) VIL (Translator) > VOL (ECL) which shows that the input of MC10H125 IC is ECL compatible. 4. 4.33. If the output accidently gets shorted.From the logic levels. T1 is cut-off.

When output is LOW. 4. VOH 3. we observe.37V VIL 2V 0. Prob. Prob.8V CMOS (a) MC10H124 translator (b) Fig.4. 4.33 From these logic levels. therefore. TTL/CMOS 54/74 54H/74H 54L/74L 54S/74S 54LS/74LS 54AS/74AS 54ALS/74ALS 74HC 400 500 200 1000 4000 2000 400 74HCT 400 500 200 1000 4000 2000 400 74AC 400 500 200 1000 4000 2000 400 74ACT 400 500 200 1000 4000 2000 400 4. CMOS-to-ECL interfacing is possible using TTL-to-ECL translator.31 54/74 (a) 74HC/74HCT (b) 74 AC/74 ACT 2 15 54H/74H 2 12 54L/ 74L 21 133 54S/ 74S 2 12 54LS/ 74LS 11 66 54AS/ 54ALS/ 74AS 74ALS 8 48 40 240 4. 4. The remaining 14 mA of current can drive 140 74ALS gates.33 The output logic levels of CMOS and the input logic levels of MC10H124 TTL-to-ECL translator are given in Fig.34.32 When output is HIGH. Therefore. 4. VIH (Translator) < VOH (CMOS) VIL (Translator) > VOL (CMOS) which shows that the input of the translator is compatible with CMOS. 4.34 The output logic levels of MC10H125 translator and the input logic levels of CMOS (74HCT & 74 ACT) are shown in Fig. 43 .76V VIH VOL 0.33. maximum possible number of ALS gates which can be driven is 140. it can drive a total of up to 1200 gates. Since the output of the translator is compatible with ECL. Prob.30 The fan-out is given below. it can drive 20 74AS gates requiring 10 mA of current.

5V VIH = 3. and 74 AC series VIL = 1. 4. the output of the translator is compatible with these CMOS devices. we observe. 4. VIH (CMOS) < VOH (Translator) VIL (CMOS) > VOL (Translator) Therefore. a resistance R and VCC are required to be connected to pull up the voltage at P corresponding to VOH (Translator) VCC R P MC10H125 Translator (c) Fig.5V VOL MC10H125 Translator (a) CMOS (74HCT & 74ACT) (b) Fig. VIL (CMOS) > VOL Translator but VIH (CMOS) < VOH (Translator) Therefore. Since the input of the translator is compatible with ECL.5V For these CMOS ICs.8V VIL 0. therefore.VOH 2.34 From these logic levels.35V VIH = 3.34 CMOS 44 . For CMOS 74 HC. Prob.5V VIH 2V 0. ECL-toCMOS interfacing is possible.85V and for CMOS 74 C series VIL = 1. Prob.

2 (a) A 0 0 0 0 0 0 0 B 0 0 0 0 1 1 1 Inputs C 0 0 1 1 0 0 1 45 D 0 1 0 1 0 1 0 Output f 0 0 0 0 0 1 1 (Contd. 5.) .1 Let S1 and S2 be the two switches. 5. Prob. 5.CHAPTER 5 5. Prob.1(a) Bulb (a) The truth table is given below: S1 0 0 1 1 S2 0 1 0 1 L 0 1 1 0 (b) The logic equation is L = S 1 S2 + S1 S 2 (c) The AND-OR realization is given in Fig.1(b): S1 S2 L Fig. 5. Prob.1(a): 0 S1 1 L 0 S2 ON = 1 OFF = 0 1 Supply Fig. Prob. 5.1(b) (d) Replace each of the AND gates and the OR gate in the above figure by NAND gates. The resulting circuit will be NAND-NAND realization. The circuit diagram of the system is shown in Fig.

3 (a) f1 = (A + B + C + D ) ( A + B + C + D) ( A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) ( A + B + C + D) ( A + B + C + D ) f2 = (A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (b) The K-maps for f1 and f2 are given in Fig.3 46 0 01 0 11 0 0 10 0 CD AB 00 00 01 11 10 0 0 0 0 0 0 (b) 0 0 0 01 11 10 . 5. Prob. Prob. Prob.) Inputs A 0 1 1 1 1 1 1 1 1 B 1 0 0 0 0 1 1 1 1 C 1 0 0 1 1 0 0 1 1 D 1 0 1 0 1 0 1 0 1 Output f 1 0 0 0 0 0 1 1 1 (b) The K-map is given in Fig. The simplified expression is f = BC + BD CD AB 00 00 01 11 10 1 1 1 (a) Fig. 5.(Contd.3(a) and (b) respectively. 5. The minimized expressions are: CD AB 00 00 01 11 10 0 0 0 0 (a) Fig.2. Prob.2 1 1 B 1 BC D (b) BD 01 11 10 B C f 5. 5.

4(a) 47 . 5. 5.4 (a) A B C D B C B D A D f A B Fig.3 (c) (d) (d) Replace all the AND and OR gates in figures (A) and (B) by NOR gates to obtain realizations using only NOR gates. Prob. Prob. Prob. 5.3(c) and (d) for f1 and f2 respectively. 5.f1 = ( B + C + D) ( A + B + C) ( A + B + D) (A + B + D ) (A + B + C ) f2 = (A + C ) (A + B) ( A + C + D ) (B + D ) (c) The OR-AND realizations are shown in Fig. B C D A C A B f1 B f2 A B C A B D A B D A B C D A C D Fig.

Prob. 5.4(b) (c) Realization for (a) requires 7400 – 1 7420 – 1/2 7430 – 1 a total of three chips.5 48 . 5. Prob. Realization for (b) requires 7427 – 1 74260 – 1 a total of only two chips.(b) A B C D A B C f A B D A B D Fig.5 (a) A C A C D 7410 Y B (b) A B C A B C B C D Y 1/ 3 7427 7427 Fig. 5.

14. 5. Prob. 13. 15) (c) f = A + C A f B Fig. 7. 5. 5. Prob.(c) Realization of (a) requires only one chip whereas (b) requires two chips. 5. the expression for f1 can be written as f1 = (C ¤ D) (A ¤ B) + (C ⊕ D) (A ⊕ B) = (A ⊕ B) ¤ (C ⊕ D) CD AB C D (A ¤ B) 00 01 11 10 1 1 1 1 1 1 1 1 00 01 11 10 C D (A Å B) CD (A ¤ B) C D (A Å B) Fig. 6. 3.6 A D 3/4 7402 C D f B Fig.8 (a) Figure Prob. 9.8 (i) below gives the K-map.7(b) 5.7(a) (b) f = å m (2. 8.8(i) 49 . Prob. 5.6 5. 5. 11. 12. Prob. 10. Using offset adjacencies shown in the K-map.7 (a) CD AB 00 01 11 1 1 10 1 1 1 1 A 00 01 11 10 C 1 1 1 1 1 1 Fig.

9. E2 and E3 are given in Fig. (b) Its K-map is given in Fig.8(iii) The minimized expression is f2 = A B + AB D + ACD The realization using NAND gates is given in Fig. 5. 5. CD AB 00 00 01 11 10 1 1 1 1 (iii) 1 1 1 A 01 11 1 10 B A B D A C D Fig.8(ii) f1 Its realization using EX-OR gates is given in Fig. 5. Prob. 5. Prob. The minimized expressions are: E0 = A 50 . This requires one 7410 chip and one gate of 7400 chip. Prob.9 Truth table of BCD-to-Excess-3 code converter is given below.A B C D Logic 1 Fig.8(ii). 5.8 f2 (iv) 5. E1.8(iv). Prob. 5. The K-maps for the outputs E0. This realization requires only one 7486 IC chip. Pro. Prob. BCD D 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 Excess-3 E1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0 Here only ten out of sixteen combinations are used and the other six are taken as don’t-care conditions.

11(c). 51 .11(b). 5. 5. A = E0 B = E1 E 0 + E1 E 0 C = E 2 E 1 + E2 E1 E0 + E3 E1 E 0 D = E3 E2 + E3 E1 E0 The circuit can now be drawn using NAND gates. Prob.11 (a) The K-map is shown in Fig. 5. The minimized expression is f1 = C D = C + D (b) The K-map is shown in Fig. Prob.BA DC 00 1 0 0 1 01 11 1 0 0 1 E0 (a) ´ ´ ´ ´ 10 1 0 ´ ´ BA DC 00 1 0 1 0 01 11 1 0 1 0 ´ ´ ´ ´ E1 (b) 10 1 0 ´ ´ 00 01 11 10 00 01 11 10 BA DC 00 0 1 1 1 01 11 1 0 0 0 E2 (c) ´ ´ ´ ´ 10 0 1 ´ ´ BA DC 00 0 0 0 0 01 11 0 1 1 1 ´ ´ ´ ´ E3 (d) 10 1 1 ´ ´ 00 01 11 10 00 01 11 10 Fig. The minimized expression is f 3 = ( A + B + C + D ) ( B + C + D) ( A + B + C ) ( A + C + D ) The circuits for f1. The K-maps can then be prepared and minimized. 5. Prob. f2. 5.9 E1 = BA + B A E2 = CB A + C A + C B E3 = D + CA + CB The circuit can be drawn using NAND gates. 5. Prob. The minimized expression is f 2 = ( A + B + D) ( B + C + D ) ( A + C ) (c) The K-map is shown in Fig.10 Truth table of Excess-3-to-BCD converter can be prepared using the truthtable of Prob. 5.11(a). and f3 can be drawn using NOR gates.9. The minimized expressions are given below.

CD AB 00 01 11 10 CD AB 00 01 11 0 10 00 01 11 10 0 0 0 0 0 0 (a) CD AB 00 0 0 0 0 0 0 00 01 11 10 0 0 0 0 (b) 0 0 0 01 11 0 10 0 0 00 01 11 10 0 0 0 (c) Fig.12 and the minimized expression is f 1 = A BE + AC E + ABD + BC + AB CD E This can be realized using NAND gates. Prob. Prob. Similarly. 5. 513(a).12 5.12 The K-map for f1 is shown in Fig. 52 .13 (a) Its K-map is given in Fig. A = 0 BC DE 00 00 01 11 10 A BE BC 10 1 DE 00 01 11 10 A = 1 AB CDE 00 1 1 1 1 1 1 1 01 11 10 1 AC E 01 11 1 1 1 1 1 ABD BC Fig. 5. 5. Prob. the minimized expression for f2 is f 2 = C E + ABD + ADE + AD E + B CE + CDE + AB E which can be realized using NAND gates. Prob.11 5.

(b) Similar to part (a). Prob. 5.13(b) (b) The K-map is given in Fig. C D Y C D Fig. f2 = A C D + BC + AB 53 (SOP) .14(a) and (b) show the K-maps of f1 for NAND and NOR realizations respectively.(a) CD AB 00 00 01 11 10 1 1 01 11 0 1 0 0 1 0 10 1 0 0 Fig. 5. 5.14 (a) Figure Prob. The minimized expressions are f1 = ABC + CD + BD + AD (SOP) and f1 = ( A + B + C ) (C + D) ( B + D) ( A + D) (POS) Circuits using NAND and NOR gates can be designed using the above expressions. 5.13(a) The minimized expression is Y = AC D + B C D + ACD A C D B C D A C D Y Fig. Prob.18 of the book and Y = C D + CD (c) Realization of part (a) requires 2 IC chips (7410) whereas for part (b) one IC chip (7400) only is required. 5. the minimized expressions are obtained which are given below. Prob.13(c) 5.

15. Prob.and f2 = ( A + B ) ( B + D ) ( B + C ) ( A + C ) (POS) These equations can be used to design circuits with NAND and NOR gates. 5.15 Its K-map and circuit realization are given in Fig.14 1 ´ 1 00 01 11 10 1 1 1 CD 00 01 11 10 ´ 0 0 (b) 0 0 AB 00 0 01 0 11 0 ´ 10 5. (a) A C (B Å D) AB CD 00 00 01 11 10 A C (B ¤ D) 1 01 11 1 1 D f1 10 1 A B C (b) B 01 11 1 1 1 A 1 1 A(C Å D) A (B Å C) AB CD 00 00 01 11 10 10 C A 1 1 f2 1 C D 54 . 5. AB CD 00 01 11 10 1 1 ´ (a) Fig. Prob.

5.16 55 1 0 1 0 10 0 1 0 B 1 D (b) A C Po . 5.15 f3 A C(B Å D) 5. Prob.16(b).(c) AB CD 00 00 01 11 10 1 1 01 11 1 1 10 A C A C (BÅD) B D Fig. Prob. Prob. 5. from which Po is obtained as Po = AC (B ¤ D) + A C (B Å D) + A C (B Å D) + AC (B ¤ D) = (A Å C) ¤ (B + D) Its realization using EX-OR and EX-NOR gates is given in Fig.16.16(a). Table Prob. AB CD 00 00 01 11 10 1 0 1 0 01 11 0 1 0 1 (a) Fig. 5. Prob. 5.16 Its truth table is given in Table Prob.16 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4-bit word B C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Odd parity bit PO 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 Even parity bit PE 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 The K-map for Po is given in Fig. 5.

17 From the truthtable given in Prob. Similarly. Prob. These are given in Fig.16.18(a).5. Similarly. 5. (a) An and Bn are applied at the two inputs of first half-adder HA – 1. 5.18(b). 5. and Cn be the sum and carry outputs respectively. The minimized expression for f1 is f 1 = ABC D E + ABCD F + CEF + A B C DEF The circuit for f1 can be realized using NAND gates. we can minimize the function using 1s which will lead to a circuit realizable by NAND gates. The minimized expression for f2 is f2 = (A + B + C + D + E + F ) ( A + B + D + E + F) ( A + B + C + E + F ) (A + C + D + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + D ) (A + B + D + E) (B + C + D + E) (B + C + D + F ) (A + B + C + D) The circuit for f2 can be realized using NOR gates. Its truth table is given in Table Prob. 5. Bn. 5. Prob. addend.18 (a) The K-map using 1’s is given in Fig. we can minimize using 0’s which will lead to a circuit realizable by NOR gates.17 (b) PE 5. and Cn – 1 respectively and Sn. 5.19 Let the augend. Table Prob. Prob. and the carry inputs to the full-adder be An.17.19. K-map is prepared and the circuit is designed. (b) The K-map using 0’s is given in Fig.19(a) An 0 0 1 1 Bn 0 1 0 1 56 S1 0 1 1 0 C1 0 0 0 1 . PE = A ⊕ B ⊕ C ⊕ D AB CD 00 00 01 11 10 1 (a) 1 1 1 01 11 1 1 1 10 1 A B C D Fig. 5. Its outputs are S1 (Sum) and C1 (Carry). 5. Prob.

B A CD 00 00 0 01 11 10 1 0 CD 00 1 EF 01 11 10 EF 01 11 10 00 1 1 01 11 10 1 1 AB CDEF CD 00 00 1 01 11 10 1 1 1 1 1 CEF 01 11 10 EF CD 00 01 11 10 00 01 11 10 1 1 EF ABC D E ABCDF Fig. 5. 5.18(a) 0 1 CD 10 0 EF 00 01 11 10 CD 00 0 00 0 0 0 0 01 11 10 0 B A CD 00 00 0 01 11 10 CD 00 00 1 01 11 10 0 0 0 0 0 0 EF 01 11 0 0 0 0 0 0 EF 01 11 0 10 EF 01 11 10 00 0 01 11 10 Fig. Prob. Prob.18(b) 57 .

19(b) C1 0 0 1 0 0 1 S1 0 1 0 0 1 0 Cn – 1 0 0 0 1 1 1 Cn 0 0 1 0 1 1 Sn 0 1 0 1 0 1 K-maps for Cn and Sn are shown below: Cn – 1 C 1 S1 00 0 1 0 0 01 0 1 11 ´ ´ 10 1 1 Cn – 1 C1 S1 00 0 1 0 1 01 1 0 11 ´ ´ 10 0 1 K-map for Cn K-map for Sn Cn = C1 + S1 × Cn – 1 Sn = S1 C n . 5. and Cn – 1 is given below: Table Prob.19(a) Truth table of the full-adder using input variables S1. 58 .1 + S 1 Cn – 1 = C1 + C2 = S1 Å Cn – 1 Sn and Cn are generated using HA –2 and an OR gate as shown in the block diagram. C1.An Bn Cn – 1 HA – 1 C1 S1 HA – 2 C2 S2 = Sn Cn Fig. Prob 5.

5 0 0 0 0 Grouping of two minterms Variables Check for inclusion B C D in groups of 4 0 — 0 0 — 0 1 1 ü ü ü (Contd. Prob. 5. 13. Since the propagation delay time (tpd) of AND–1 is less than the tpd of EX-OR(1). 3 1. Propagation dealy time for Cn = tpd [EX-OR(1) + tpd (AND-2) + tpd(OR) = 20 + 10 + 10 = 40 ns. 6. 15) Table (a) Group 0 1 Grouping of minterms according to number of 1’s. 1 0. therefore. C. 4 1. 8.19(b) OR Cn 5.(b) An Bn EX–OR(1) S1 EX–OR(2) S2 = Sn C2 C1 AND-2 AND–1 Cn–1 Fig. 1. D) = p M(2. 11. 4. B. 5. 5. 3.21 f (A. A 0 1 4 3 5 6 11 13 14 15 0 0 0 0 0 0 1 1 1 1 Variables B C D 0 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 Check for inclusion in groups of 2 ü ü ü ü ü ü ü ü ü ü Minterm 2 3 4 Table (b) Group 0 Minterms A 0.20 Propagation delay time for Sn = tpd [EX-OR(1)] + tpd [EX –OR(2)] = 20 + 20 = 40 ns. 14.) 59 0 — — 0 . 7. 9. it is not counted. 12) = S m (0. 10.

11 BC Dü 5. 5 0 0 Variables B C — — 0 0 D — — Table (d) PI table PI terms Decimal numbers 0 1 ´ ´ 3 ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ Minterms 4 5 6 11 13 14 15 ´ ´ 0. 11 5. 3 AB Dü 4.) Group 1 Minterms A 4. Therefore. 1. 14 11.5 4. the minimized function is f (A. 15 13. we see the minterms that are covered by each prime-implicant and find the minimum number of prime-implicants that will cover all the minterms. B. 1. C. 60 . therefore. 15 ABC 14. 15 ü ü ü ü ü ü ü From the PI table.13 6. 1. 6 3. All the other columns contain 2 or more Xs. starting from the prime-implicant A B D. D) = AC + ABD + ABD + B CD + BC D + BCD + ACD There can be other options also. 15 14. 5 Ä AC ü 1. 15 0 0 — — — 1 1 1 Variables Check for inclusion B C D in group of 4 1 1 0 1 1 — 1 1 0 — 1 0 1 1 — 1 — 0 1 1 0 1 1 — ü 2 3 Table (c) Grouping of 4 minterms Group 0 Minterms A 0. 5 0. 4. 6 A B Dü B CDü 3. we see that the column for minterms 0 contains only one ´.(Contd. Depending upon the prime-implicants selected above. 15 ABD 13.13 BC D ü 6. A C is an essential prime-implicant. 4. 14 ACD ü 11. 4.

5. 11 1. Group Minterm/ don’t care term 1 2* 8 3 5 9 11 13* 15 A 0 0 1 0 0 1 1 1 1 Variables B C 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 1 D 1 0 0 1 1 1 1 1 1 Check for inclusion in group of 2 ü ü ü ü ü ü ü ü ü 1 2 3 4 Table (b) Group Grouping of 2 minterms/don’t care terms A 0 0 — 0 1 — — 1 1 1 1 Variables B C 0 — 0 0 0 0 1 0 — — 1 — 0 0 1 0 1 0 — 0 1 — D 1 1 1 — — 1 1 1 1 1 1 Check for inclusion in group of 4 ü ü ü Minterms/ don’t care terms 1. 3 8. 15 A — — — — 1 1 Variables B C 0 — 0 — — — — 0 — 0 — — D 1 1 1 1 1 1 1 2 There are a total of 5 prime-implicants BD . 9 2*. 13* 9. and AD from Table (c) and AB C and AB C from Table (b). 61 . 3. D) = Sm (1. 13) Table (a) Grouping of minterms/don’t care terms according to number of 1’s. 11. 9. 11 9.22 f (A. 11 5. 13* 11. 13* 9. 15 1 2 3 ü ü ü ü ü ü Table (c) Group Grouping of 4 minterms/don’t care terms Minterms/ don’t care terms 1. 13*.5. 13*. 3. 3 1. 11. 15 9. 9. 8. 15) + d(2. B. 13* 1. 3. C. 9. 9. 9 3. 11. 5. 5 1. CD. 5. 15 13. 9. 11 1.

11. 9 8. 26. 11. Therefore. and ABC . 5. 9. B. Except the minterm 3 all the other minterms have heen covered by the essential prime-implicatns. C. E) = Sm (8. 15 ü ABC 2*. 31) Table (a) Group 1 Grouping of minterms according to number of 1’s A 8 16 9 10 18 24 11 13 21 25 26 15 27 30 31 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 B 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 Variables C D 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 E 0 0 1 0 0 0 1 1 1 1 0 1 1 0 1 Check for inclusion in group of 2 ü ü ü ü ü ü ü ü ü ü ü ü ü ü Minterm 2 3 4 5 Table (b) Group Minterms A 1 8. 10 0 0 Grouping of 2 minterms B 1 1 Variables C D 0 0 0 — E — 0 Check for inclusion in group of 4 ü ü (Contd. 15. 27. 9. 11 ´ CD 1.) 62 . 16. 5. 9. C. The minimized function is f (A. B. 10. 21. 9 ü ´ ´ ´ Ä ü ´ ´ ´ ´ Ä ´ ´ ü ´ ü The essential prime. 24. 25. 30. 13*. 18 . D) = B D + C D + AD + AB C . 3 AB C 8. B D is to be included in the minimized expression. 13. AD.Table (d) PI Table PI terms Decimal numbers 1 2* Minterms/don’t care terms 3 5 8 9 11 13* ´ Ä 15 BD 1.23 f (A. 3. D. 13* ü ´ AD 9.implicants are: CD.

11. 9. 18 16. 27. 11 8. 30. 11. 15 9. 26 16. 24. 24. 24 9. 26. 25. 27 26.31 30. 27 10. 24. 27. 27. 26. 24. 18. 27 26. 10. 24. 27 11. 9. 25 8. 27 24. 25. 15 11. 15. 25 24. 15. 11 8.) Group Minterm A 8. 11. 31 — 1 1 0 0 — 0 — 1 1 1 0 — 0 1 1 1 — 1 1 B Variables C D 0 0 0 0 — 0 0 0 0 0 0 — 0 1 0 0 — 1 — 1 0 — 0 — 0 0 1 1 1 0 — 1 1 — — 1 1 1 1 1 E 0 0 0 1 1 1 — 0 0 — 0 1 1 1 1 — 0 1 1 — Check for circlusion in group of 4 ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü 2 3 4 1 0 — 1 1 1 1 1 — 1 1 1 1 1 1 1 1 1 1 1 Table (c) Grouping of 4 minterms Group Minterms A 8. 13. 26 16. 24. 11. 13 9. 11 10. 25 10. 11. 25. 26. 26 24. 26 11. 24 16. 18. 10. 11 9. 27 9. 30 15. 30. 9. 9. 15 25. 26. 26. 10. 27 13. 26 8. 31 31 31 31 0 — 0 — — — 1 1 0 — 0 — — — 1 1 — — 1 1 B Variables C D 0 0 0 0 0 0 0 0 — 0 — 0 0 0 0 0 — — — — 63 — 0 — — 0 — — — — — — — 1 1 — — 1 1 1 1 E — — — 0 — 0 0 0 1 1 1 1 — — — — 1 1 — — Check for inclusion in group of 8 ü ü ü ü ü 1 1 1 1 1 1 1 — — 1 1 1 1 1 1 1 1 1 1 1 1 ü ü ü ü ü ü 2 3 . 15 9. 11. 25 8. 10. 26 9. 11. 27 10.(Contd. 26. 27 24. 27. 25. 13. 31 27. 26 18.

27. 27 — Tabe (e) PI Table PI terms Decimal numbers 8 Minterms 9 10 11 13 15 16 18 21 24 25 26 27 30 31 Ä 21 AB CDE ü ü 16. 15 ABE BDE 11. 10. B. 13. 26. 24. 25. 11. 15. 26. 30. E) = A B C D E + A C E + A BE + ABD + B C 64 . 24. C. 9. 31 ü 8.Tabe (d) Group 1 Minterms Grouping of 8 minterms A B 1 Variables C D 0 — E — 8. 27. 11. 9. 24. 26 ACE ü 9. 27 ´ Ä ´ ´ ´ ´ ´ Ä ´ ´ ü ´ ´ Ä ´ ´ ü ´ ´ ´ ´ ´ Ä ü ü ü ´ ´ The minimized function is f (A. ´ BC 25. 11. 10. 31 ABD ü 26. 18. D.

10. the data input lines corresponding to these decimal numbers are to be connected to logic 0 and the data input lines 0.3). The circuit is shown in Fig. and S0 Table Prob.. 8.CHAPTER 6 6. Logic 0 Logic 1 0 1 2 3 4 5 6 7 16:1 8 9 Multiplexer 10 74150 11 12 13 14 15 G S3 S2 S1 S0 Logic 0 (MSB) A B C D (LSB) Fig. 5. 11. 7. Prob. Since the data output is 1 when the input variables correspond to decimal numbers 2.1 (a) In the 16:1 multiplexer IC 74150. 13. 6. the inputs A. 1. 3. 12 and 15.1(b) A 0 0 0 0 1 1 1 1 Inputs B 0 0 1 1 0 0 1 1 65 C 0 1 0 1 0 1 0 1 Output Y 0 D D 1 D 1 D D . therefore. 6. S1 . and C are to be connected to S2. 6. In this. and 14 are to be connected to logic 1. i. 6. complement of the data input line selected. the data output is inverted input. 9.1.1 Y (b) To realize a four variable truthtable or logic expression using an 8:1 multiplexer the truth table is partitioned as shown by dotted lines (Table 6.e. 4. B. Prob.

6. the system will function as a 32:1 multiplexer. (ii) Another method can use two 16:1 multiplexers with their select lines connected together. This IC also has the data output which is complement of the data input line selected. 6. 6.select inputs respectively. Prob. 6. we note the output Y for each of the combinations of A. while the enable input of the other multiplexer is connected to A . the first multiplexer is enabled and for A = 1 the second multiplexer is enabled. Prob. Prob. If A is connected to the Enable input of one of the 16:1 multiplexers. Logic 1 0 D 1 2 D Logic 0 3 4 5 6 7 S2 S1 S0 74152 Y A B Fig. 66 . Thus for the first 16 of the 32 data inputs one multiplexer gives output depending upon the select inputs while for the remaining 16 data inputs the other multiplexer gives the output.1(b). C. Now if the two outputs are ORed together. B. and C and then make the connections accordingly.2(ii). This is followed by a 2:1 multiplexer to select one of the two outputs.2 A 32:1 multiplexer can be designed using two 16:1 multiplexers following any one of the following approaches. Prob. The select line of the 2 : 1 multiplexer is driven from input A. 1. the circuit is shown in Fig.2(i). A.3. 6. D. Now. where A is the MSB. we observe the relationship between input D and output Y for each group of two rows. There are four possible values of Y and these are 0.3. From this table. The complete circuit is shown in Fig. 6. The complete circuit is shown in Fig. and E. 6. 6. say. To realize this. B. D.3 The truth table of a full-adder in given in Table Prob. The implementation of this function using a 74152 IC is shown in Fig. (i) A 32:1 multiplexer will have five selection lines.1(b) C 6. Assuming 74152 IC.1(b). These are given in Table Prob. then for A = 0. Prob. and D . using 8:1 multiplexers requires one multiplexer for Sn and one for Cn output.

C. E) S3 S2 S1 S0 ì ï Data ï í inputs ï ï î A (MSB) 16 17 M2 18 16 : 1 31 G2 Y2 · Fig. D. B.ì ï ï Data í inputs ï ï î G1 E (LSB) D C B 0 1 2 M 1 Y1 15 16 : 1 S3 S2 S1 S0 Output F (A. Prob. 6. C.2(i) ì ï ï Data í inputs ï ï î G1 Logic 0 B C D E (LSB) 0 1 2 M1 Y1 15 16 : 1 A(MSB) S3 S2 S1 S0 S 0 Output M3 Y 1 2 : 1 F (A. D. Prob. E) G3 S3 S2 S1 S0 16 17 18 31 G2 M2 16 : 1 Y2 ì ï Data ï inputsí ï ï î Logic 0 Logic 0 Fig.2(ii) 67 . B. 6.

Prob.Table Prob. 6.3 68 74152 IC2 Cn S2 S1 S0 S2 S1 S0 74152 IC1 Sn . 6.3 An 0 0 0 0 1 1 1 1 Inputs Bn 0 0 1 1 0 0 1 1 Outputs Cn–1 0 1 0 1 0 1 0 1 Sn 0 1 1 0 1 0 0 1 Cn 0 0 0 1 0 1 1 1 The gates required for NAND-NAND realization are: 4-input NAND gate 1 3-input NAND gates 5 2-input NAND gates 3 Inverters 3 Logic 1 0 1 2 3 4 5 6 7 Logic 0 An Bn Cn–1 Logic 1 0 1 2 3 4 5 6 7 Logic 0 Fig.

Also Cin = 1. the following IC packages will be required: 7420 – 1 7410 – 2 7400 – 1 In contrast to four packages required in NAND-NAND realization. 6. the circuit functions as a 4-bit adder.Therefore. the realization using 8:1 multiplexers require only 2 IC packages. therefore. When the switch S is in ADD position the outputs of the EX-OR gates will be same as the B inputs. The complete circuit is shown below. the EX-OR gates function as inverters.5 (i) gives the truth table of Gray-to-BCD code converter. On the other hand.4 The A inputs are applied directly to the adder. Therefore. Also Cin = 0.5 Table Prob 6. 6. whereas the B inputs are applied through EX-OR gates. 64444 74444 8 4 4 B3 B2 B1 B0 B Input A3 A2 A1 A0 64748 A input 7 4 8 3 4-bit Adder ADD Cin S SUB VCC C0 S3 S2 S1 S0 6. when S is in SUB position. the circuit adds A to the 2’s complement of B and hence functions as a 4-bit subtractor. Table Prob.5(i) G3 0 0 0 0 0 0 0 0 1 1 Gray code G2 G1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 G0 0 1 1 0 0 1 1 0 0 1 69 D 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 BCD code B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 0 1 0 1 0 1 .

6 The truth table of BCD-to-7-segment decoder is given in Table Prob. 6.6(i) shows a common-anode 7-segment display device.5 (ii). 6. 6. and B outputs. 6. Table Prob.6(i) D 0 0 0 0 0 0 C 0 0 0 0 1 1 BCD Inputs B A 0 0 1 1 0 0 0 1 0 1 0 1 a 0 1 0 0 1 0 b 0 0 0 0 0 1 Seven-Segment Outputs c d e f 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 g 1 1 0 0 0 0 (Contd.5(ii) G3 0 0 1 1 G2 0 1 0 1 D 0 0 X 1 C 0 1 X 0 B G1 G1 X 0 A G1 ⊕ G0 G 1 ¤ G0 X G1 ⊕ G0 The G3 and G2 are used as the select inputs. C. and one 7400 IC packages. 6. Prob 6.5(b). one 7430.(a) For A output (i) When G3 G2 = 00 G1 0 0 1 1 G0 0 1 1 0 A 0 1 0 1 (ii) When G3G2 = 01 G1 1 1 0 0 G0 0 1 1 0 A 0 1 0 1 \ A = G1 ⊕ G0 (iii) When G3 G2 = 10 G1 1 1 0 0 G0 0 1 1 0 A X X X X \ A = G1 ¤ G0 (iv) When G3 G2 = 11 G1 0 0 1 1 G0 0 1 1 0 A 0 1 X X \A= X \ A = G1 ⊕ G0 Similarly. 6. It requires one 74154.6(i) and Fig. (b) The complete circuit is shown in Fig. Prob. one 7420.) 70 . The complete circuit can be drawn which requires two 74153 packages and one 7486 package. Table Prob. These are given in Table Prob. we can obtain the expressions for the D.

Prob. The circuit for generating data inputs for the multiplexers corresponding to Table Prob. The ICs required are: 74153 3 1 packages 2 71 .6 (ii). 6.5(b) (a) From Table Prob. 6. 6. 6.6(i) (Contd. Prob.Table Prob.6(i). 6.) D 0 0 1 1 1 1 1 1 1 1 C 1 1 0 0 0 0 1 1 1 1 BCD Inputs B A 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 a 1 0 0 0 X X X X X X b 1 0 0 0 X X X X X X Seven-Segment Outputs c d e f 0 0 0 0 X X X X X X 0 1 0 1 X X X X X X 0 1 0 1 X X X X X X 0 1 0 0 X X X X X X g 0 1 0 0 X X X X X X Y0 Y1 Y2 Y3 Y4 Y5 G1 G0 74154 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 S3 S2 S1 Y15 S0 Aü (LSB)ï ï ï ï ï ï Bï ï ï ï ï BCD ï ýoutputs ï ï Cï ï ï ï ï ï ï ï Dï (MSB) ï þ 0 13 4 444 44 2 2 1 3 G G G G Gray code inputs Fig.6(ii) which gives outputs in terms of A and B inputs for each combination of D and C inputs. we can prepare Table Prob. 6.6 (ii) is shown in Fig.

6. The ICs required are: 74154 one package 7420 one package 7410 one package 72 . Prob.7408 7432 7404 3/4 package 3/4 package 1/2 package Anode a b c d e f g f e a b g c d · DP DP Fig.6(ii) D 0 0 1 1 Inputs C 0 1 0 1 a BA b 0 B⊕ A 0 X c Outputs d BA e A A+ B A X f A+B AB 0 X g B A 0 X BA 0 0 X B¤A A X AB 0 X B A+ B B BA A+B AB BA BÅA B¤A A A Fig.5. 6.6(i) Table Prob.6(ii) (b) The circuit is designed in a way similar to Prob. Prob. 6. 6.

7 (c). Here eight rows of the truth table are grouped together. The circuit can now be designed using two 74153 ICs and two EX-OR (7486) gates. we obtain Table Prob. 6. Table Prob. 6. and B inputs are to be applied to the S2. S1. and (c).7(b) can be obtained from the truth table following the procedure of Prob.1(b). 6. Table Prob. Table Prob. 6. and S0 select inputs respectively. The IC packages required are same as in part (b) with 74154 replaced by 7442.7(a) D 0 0 0 0 1 C 0 0 1 1 0 B 0 1 0 1 0 G3 0 0 0 0 1 G2 0 0 1 1 1 G1 0 1 1 0 0 G0 A A A A A The circuit can now be designed using four 74151A ICs (one for each of the outputs). (b) Table Prob. 6. 6. (b).7(c) D 0 1 G3 0 1 G2 C 1 G1 B⊕ C 0 G0 A ⊕ B A 73 .7430 one package 7404 1/6 package (c) The IC 7442 is a BCD-to-decimal decoder circuit with active-low outputs. The D. (d) From the IC packages requirements for parts (a).5 (a). 6.5(i) can be rearranged suitably to give the truth table of BCD-toGray code converter. C.7 Table Prob.7(b) D 0 0 1 1 C 0 1 0 1 G3 0 0 1 X G2 0 1 1 X G1 B B 0 X G0 A⊕ B A⊕ B A X (c) Following the approach similar to (b).7 (a) is obtained following the procedure used in Prob. These outputs are to be connected exactly in the same way as in the case of part (b) realization. 6. (a) From the truth table. we observe the savings in hardware when demultiplexers/decoders are used for the realization of multiple output systems. 6. 6. Table Prob.

f2. 7404 – 1 74153 – 2. (d) Following the procedure used in Example 6. (c) The circuit can be designed using one demultiplexer and two 8-input and one 6-input NAND gates.7(d) Table Prob. and f3 outputs using multiplexers and inverters. (e) The minimized expressions are G3 = D G2 = C + D G1 = C B + C B G0 = B A + B A The realization will require eleven 2-input NAND gates. 6. 7486 – 1 75157 – 1.3. and f3 can be designed following the procedure outlined in Example 6. 6. The circuits can now be designed for f1. the circuit can be designed using one BCD-to-decimal decoder IC 7442 and NAND gates (2-.7(d) Part a b c d e No.The circuit can now be designed using one 74157 (Quad 2:1 multiplexer) IC and two EX-OR gates of 7486. 4-. f2. (b) Using the truth table the circuits for f1. (f) The package count for each part are given in Table Prob 6.1.8(i) (a) The truth table is reduced to Table Prob. and 6-input).8 The truth table for f1. of IC packages 74151A – 4. The realizations will require one 16 : 1 multiplexer for each output. 6. 7420 – 1 7400 – 3 6. and f3 outputs is given in Table Prob. 6.8(ii) for realization using 8 : 1 multiplexers. Table Prob.8(i) D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inputs C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Outputs B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 74 f1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 f2 1 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1 f3 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 . f2. 7486 – 1 7442 – 1. 5-. 7430 – 2.

and A are used as S2.9 75 . S1. 6. Prob. there are 40 data input lines (I0 through I39). B. S0 select inputs respectively for 8:1 multiplexers M1 through M5.8(ii) D 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 f1 A A A A A A A A f2 1 1 0 0 0 A A 1 f3 0 A 1 A A 0 A 0 6. S1. The lower order three select bits C. I0 – I7 G M1 S2 S1 S0 C B A I8 – I15 S2 S1 S0 G M2 0 1 2 3 4 M6 5 6 7 G S2 S1 S0 Y I16 – I23 G I24 – I31 M3 S2 S1 S0 C B A S2 S1 S0 M4 G C B A (LSB) F E (MSB) D I32 – I39 Enable S2 S1 S0 G M5 Fig. 6 select lines FEDCBA. 6. which selects output of one of the multiplexers M1 through M5. and D are used as select inputs S2.Table Prob. E. The higher order three select bits F.9 In a 40:1 multiplexer. and S0 for the multiplexer M6.

Prob.10 76 . data input 7 of M2 (I15) will appear at the output Y.10 The BCD-to-decimal decoder is to be used as an 1 : 8 demultiplexer. and A. 6. B. 6. D is active0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 D X2 X1 X0 (LSB) C B A D1 7442 D X2 X1 X0 0 1 2 3 D6 4 D 7442 5 6 7 8 C B A9 C B A D2 7442 8 9 10 11 12 13 14 15 D X2 X1 X0 ( C B A D3 7442 Enable 16 17 18 19 20 21 22 23 X5 X4 X3 (MSB) X2 X1 X0 D C B A D4 7442 24 25 26 27 28 29 30 31 D X2 X1 X0 C B A D5 7442 32 33 34 35 36 37 38 39 Fig.For example if the select inputs are 011111. The address inputs for demultiplexers D1 through D6 are C.

if the 6-bit select inputs are 001111.low input for demultiplexer function. and X0 are applied at the C. Prob. Prob.11 For the full-adder circuit designed using half-adder circuits shown in Fig. The outputs 8 and 9 of D1 through D5 are not used in this configuration. 6. 6. Therefore. The lower order three bits of the address X2. and X3 are applied at the C. This corresponds to output on line 15 (which is same as the decimal equivalent of 001111). EX–OR(1) An Bn S1 EX–OR(2) S2 = Sn C1 AND-2 AND–1 Cn–1 Fig. the propagation delay time for the carry to propagate from C–1 to Cn–1 in the circuit of Fig. For an nbit adder. X4. 6. 6. 6. which activates decoder D2 and the output 7 of this decoder goes low. 6. Prob.12 (a) will be n ´ 40 = 40 ns. Q4 P4 Q3 P3 Q2 P2 Q1 P1 BCD adder #4 C¢¢¢¢ C2 0 BCD adder #3 C¢¢¢ C1 0 BCD adder #2 C¢¢ C0 0 BCD adder #1 C¢0 C–1 144444444444444 2444444444444444 4 3 5-digit output Fig. A select inputs respectively of each decoder chip D1 through D5. X1. For example. The higher order three bits of the address X5. B. P4 and Q4 are applied at the A and B inputs respectively of adder # 4 and similarly the other inputs are applied as shown below. and A select inputs respectively of D6. this carry has to ripple through all the n adders. B. Prob.11.10.12 77 C0 S15–S12 S11–S8 S7–S4 S3–S0 . The complete circuit is shown in Fig.12 Let the four digits BCD numbers be P4P3P2P1 and Q4Q3Q2Q1. 6. then output 1 of D6 is activated.11 C2 OR Cn The propagation delay time for Cn is tpd = tpd [EX-OR(1)] + tpd (AND-2) + tpd (OR) = 20 + 10 + 10 = 40 ns This is the propagation delay time for carry to travel one full-adder.

The complete circuit is shown below.14 78 . 6. A = B. and A < B outputs are connected to the corresponding cascading inputs of C2 respectively.13. A0 – A3 B0 – B3 C1 7485 A>B A=B A<B A4 – A7 A>B A=B A<B 7485 A>B A=B A<B B4 – B7 C2 A>B A=B A<B Logic 1 Logic 0 Fig. Table Prob. Using K-maps the minimized expressions given below are obtained. Prob. 6. 6. Its A > B.6.13 Its truth table is given in Table Prob.13 Inputs A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 Outputs A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 A > B = A0 B 1 B0 + A1 A0 B 0 + A1 B 1 A = B = A1 B 1 (A0 ¤ B0) + A1B1 (A0 ¤ B0) = (A0 ¤ B0) (A1 ¤ B1) A < B = A 1 A 0 B0 + A 0 B1B0 + A 1B1 The complete circuit can be drawn using gates.14 The comparator C1 compares the least significant four bits. 6.

Inputs CIC 1 A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B = 1001 = 1011 =1 =0 =1 = 0000 = 0000 =1 =0 =1 = 1011 = 1101 =1 =0 =1 = 0010 = 0001 =1 =0 =0 = 0010 = 0011 =0 =1 =0 = 0001 = 1000 =0 =0 =1 Outputs A>B=0 A<B=1 CIC 2 A>B=0 A<B=0 CIC 3 A>B=0 A<B=0 CIC 4 A>B=1 A<B=0 CIC 5 A>B=0 A<B=1 A=B=0 CIC 6 A>B=0 A=B=0 A<B=1 6. The binary output is obtained at B3B2B1B0 outputs as shown in Fig. and A inputs respectively. and B1) are applied to C.15 The operation is given below. The other three bits (D1. Prob.16. D and E inputs are connected to logic 0. 6.6. C1. B.16 The least-significant bit (A1) of BCD input is same as the least-significant bit of the output. 79 .

if the parity of the 6-bit word is ODD. then E0 of IC2 will be HIGH. Connect EVEN and ODD inputs to logic 1 and 0 respectively. then å EVEN output is 1 if the 7-bit input is even and 0 if the 7-bit input is odd.19 80 . The circuit is shown below. one of which is in IC1 and the other one in IC2.G SEVEN ü ï 8-bit odd ý parity word ï þ 74180 H EVEN SODD ODD Logic 1 Logic 0 Fig. these seven bits along with the å EVEN output bit will give an 8-bit word with odd parity. then å ODD output will be 1. whereas. 6. Prob. 6.G A . If more than one inputs are given in the same chip. Prob. If EVEN and ODD inputs are at logic 1 and 0 respectively.18 Apply the 6-bit input to A through F inputs and connect the other two inputs G and H to logic 0. which will disable the IC1 chip. If two inputs are given simultaneously. This shows that the circuit is a priority encoder. Therefore. A .19 The 7-bit input is applied at A through G inputs and H = 0. the highest numbered input will appear in the binary form at the output. 6. 6.ì A1 ï BCD ï B1 inputs í C ï 1 ïD î 1 B0 A B C D E G 74184 Y1 Y2 Y3 Y4 Y5 B1 ï Binary ï ý outputs B B3 ï þ 2 ü ï (MSB) Fig. å EVEN output will be 1. If the parity of the 6-bit word is even.17 The IC 74148 is a priority octal-to-binary encoder.16 6.

21 and its operation is explained in the Table Prob. B0 – B7 SEVEN P1 74180 SODD EVEN B8 – B13 Logic 0 SEVEN P2 74180 SODD G H B0 – B13 EVEN ODD Fig.20 and its operation is given in Table Prob. 6. 6.21 81 A B C S EVEN D E F 74180 G H EVEN SODD ODD 1 on even parity 15-bit even parity word Logic 1 B14 .21 The circuit is shown in Fig.20 The circuit is shown in Fig.21.20 ODD ü ï ý ï þ Table Prob. Prob. 6. Prob. 6. 6. 6. Prob. Prob.6.20 Parity of B0 – B7 åEVEN EVEN ODD 1 0 P1 åODD 0 1 Parity of B8 – B13 EVEN ODD EVEN ODD åEVEN 1 0 0 1 P2 åODD 0 1 1 0 From the table we see that the parity of B0 – B13 and åODD of P2 is even.20. 6. 6. B0 B1 B2 B3 B4 B5 B6 B7 7486 B8 B9 Logic 1 Fig.

26 Let the four BCD digits be ABCD.Table Prob. 6. The least-significant bits of the BCD digits are applied at the data inputs of M1 and similarly higher order bits are applied to M2. 6. with A as MSD. The select input are fed from the mod-4 counter. 6.25 See Fig. Prob.23. 6. The circuit is given in Fig. 6. Prob. Here P1.26. Prob.21 Parity of B0 – B7 EVEN EVEN ODD ODD Parity of B8 – B9 EVEN ODD ODD EVEN Cascading inputs EVEN ODD 1 0 0 1 0 1 1 0 Outputs åEVEN 1 0 1 0 åODD 0 1 0 1 6.22 b80 6. P2. 6.23 The circuit is given in Fig. which drives a BCD-to-decimal decoder. 82 .24 See Fig. Prob.22 b0 – b 7 SEVEN P1 EVEN ODD b8 b9 – b16 SEVEN P2 EVEN ODD SEVEN P10 EVEN ODD High on EVEN High on ODD b17 b72 – b79 SEVEN P9 EVEN ODD Fig. and M4.25 6. 6. M3. Prob. and P3 are 9-bit parity checkers.24 (a and b) 6.

6.b0 P1 b8 SEVEN b9 P2 b15 SEVEN High on EVEN SODD High on ODD b16 SEVEN P3 b24 Fig. Prob. Prob. 6.23 (a) VCC VCC Current Limiting resistor VCC BCD input (MSB) ìD ïC í ïB îA 7442 GND 0 1 2 3 4 5 6 7 8 9 Fig.24(a) 83 .

6. Seven 5:1 multiplexers and a mod-5 counter will be required for this. 6. when the counter outputs are 01. the inputs required at the rows for each column are as given in Table Prob. The circuit is to be designed in a way similar to that of Prob.24 0 1 2 3 (LSB) A B C D Enable (logic 0) D1 E F G H D2 0 1 15 Detects 0001 Fig. C.26.(b) +170 V R = 10 kW 0 1 2 3 4 5 6 7 8 9 Anode NIXIE Tube 0 1 2 3 4 5 6 7 8 9 +5V VCC 74141 D C A 1444 24444 4 B 3 BCD Input (b) Fig.27 For R to glow. 6. If the clock frequency is sufficiently high. Prob. and fourth displays in sequence. Prob. third. One column must glow at a time in sequence. In this way each display will be ON for onefourth of the total time.27. thereby displaying the digit A on the left-most 7-segment display. and 11 B.25 14 15 Detects 0001111 The multiplexer outputs are decoded by the BCD-to-7-segment decoder with active-low outputs. When the counter output is 00. and D digits are displayed respectively on second. 84 . 6. Similarly. 6. 10. the display would appear to be continuous. digit A is selected and at the same time anode A1 goes HIGH.

6. Prob.A0 B0 C0 D0 0 1 M1 2 3 S S 1 0 BCD-to-7-segment decoder a b c d e f g Buffer inverters ··· 0 1 2 3 4 BCD-to-decimal decoder A1 B1 C1 D1 0 1 M2 2 3 S S 1 0 A B C (MSB) D A2 B2 C2 D2 0 1 2 M3 3 S S 1 0 A1 A2 A3 A4 A3 B3 C3 D3 0 1 2 M4 3 S S 1 0 Q0 Q1 Q2 Q3 Mod-4 counter Clock Fig.26 Table Prob.27 Row/Column ® ¯ 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 2 1 0 0 1 0 0 0 3 1 0 0 1 1 0 0 4 1 0 0 1 0 1 0 5 0 1 1 0 0 0 1 85 . 6.

Therefore.3 R Q Q S Fig. then Sn = Q n and Rn = Qn. (iii) If Jn = 0 and Kn = 1 then Sn = 0 and Rn = Qn. 7.5. This results in both the inputs of AND gate G5 to be 1 giving Q = 1.1 When S = R = 0. then Sn = 0 and Rn = 1 which will make Qn+1 = 0. the circuit of fig. 86 . Now if S = R = 0. its output will be 1. Therefore. when a clock pulse is applied. therefore.3.e. Hence. the FLIP-FLOP is set irrespective of the S. Following the above discussion.3 7. if Qn = 1 then Sn = 0. Qn+1 = Q n. (c) If Pr = Cr = 1. Therefore. 7. the inputs and output of G2 remain unaffected. the outputs of G3 and G4 are 0 and 1 respectively. Since one of the inputs of G1 is 0. Now. i. i. if Qn = 0. its output Q = 1. G1 and G2 will act as inverters.CHAPTER 7 7. 7. 7.2 (a) With S = 1 and R = 0. Sn = Rn = 0 and the output Qn+1 = Qn = 1. which makes the lower input of G1 as 0 while the upper one becomes one giving again Q = 1. (ii) When Jn = 1 and Kn = 0. That is. if Qn = 1. then Sn = 1 and Rn = 0 which makes Qn+1 = 1. On the other hand if Qn = 0 then Sn = 1 which will make Qn+1 = 1. it will go to set state in this condition when a clock pulse is applied.e. we find that the FLIP-FLOP will go to the reset state when a clock pulse is applied. Qn+1 = Qn. Therefore. (iv) If Jn = Kn = 1. Q1 = 1 and Q = 0 in a manner similar to part (a) and also Q and Q will remain unchanged when S and R both are made 0.. the AND gates G5 and G6 are enabled. Q will be 0 which makes one of the inputs of G3 0. then the FLIP-FLOP is reset following the same logic as discussed in part (a).5 (i) When Jn = Kn = 0.4 (a) With Pr = 0. Prob 7. Similarly. then Sn = Q n and Rn = 0. Now. This means the outputs do not change. the outputs Q and Q will not change. 7. This makes both the inputs of G2 as 1 giving an output Q = 0. (b) With S = 0 and R = 1. 7. whatever may be the other input of G3. making this circuit identical to a normal clocked S – R FLIP-FLOP as shown in Fig. Therefore. the AND gates are disabled resulting in Sn = Rn = 0. R. (b) If Cr = 0.. and CK inputs. whatever may be the state of the FLIP-FLOP.4 is same as that of Fig. the outputs of the gates G3 and G4 will be 1.

Y1 = Y2 7. R = Q = 0 and S = Q = 1 and on 87 .6 Y1 = ( J ⋅ Q ) ⋅ CK = J ⋅ Q ⋅ CK and Y2 = J ⋅ Q ⋅ CK Hence. When a clock pulse is applied.11 Let Q = 1 and Q = 0.8 Clock Input Q2 = Q Output í ìQ îQ 7.9 Clock Input Output í ìQ îQ 7.7.7 Q1 = Q and 7. This makes R = Q = 1 and S = Q = 0.10 Clock Input Output Q 7. Now. Q and Q will become 0 and 1 respectively.

12 The truth table is given in Table Prob. 7. whereas.14(b).application of a clock pulse. 7. Q and Q become 1 and 0 respectively. a clock pulse will make Q and Q 0 and 1 respectively.12. 7. 7. From this table we observe that when Tn = 0. The K-maps can be prepared and minimized. Qn+1 = Q n. 7. This show that Q and Q change with every clock pulse. The K-maps for Y1 and Y2 are shown below. the outputs change with every clock pulse.14 (a) CK 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 J 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Characteristic table K Qn 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Qn + 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Truth table for decoder Y1 Y2 1 X 1 X 1 X 1 X 1 X 1 1 0 X 0 1 X 1 X 1 X 1 X 1 X 1 X 0 1 1 1 0 (b) The excitation table and the truth table for decoder are given in Table Prob.14 The characteristic table and the truth table for decoder are given in Table Prob. Now Q = D = 1 and the next clock pulse will change the Q output to 1.14 (a). when Tn = 1. which give Y1 = Q + CK + J = Q ⋅ J ⋅ CK and Y2 = CK + K + Q = Q ⋅ K ⋅ CK Table Prob.13 When Q = D = 0. 7. 7. Table Prob. Thus. Qn+1 = Qn.12 Tn 0 0 1 1 Qn 0 1 0 1 Sn 0 1 1 0 Rn 1 0 0 1 Qn+1 0 1 1 0 7. and hence the circuit behaves as a toggle switch. The minimized expressions are: 88 .

7. 7.15(i) from which we obtain the minimized expressions for S and R as S = D and R = D and Table Prob. 7.14(b) CK 0 0 0 0 1 1 1 1 Excitation table D 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 1 0 0 1 1 Truth table for decoder Y1 Y2 1 X 1 X 1 1 0 X X 1 X 1 X 0 1 1 (c) Using the above method.KQ CKJ 00 00 1 01 ´ 11 ´ 10 1 01 1 ´ ´ 1 11 0 ´ 1 0 10 1 ´ 1 1 KQ CKJ 00 ´ 1 1 ´ 01 ´ 1 1 ´ 11 1 1 0 1 10 ´ 1 0 ´ 00 01 11 10 Y 1 = Q + CK + J = Q ⋅ J ⋅ CK (a) Y 2 = CK + K + Q = Q ⋅ K ⋅ CK (b) Y1 = CK + D = CK ⋅ D and Y = CK + D = CK ⋅ D Table Prob.15 (a) The truth table required for conversion from S-R to D FLIP-FLOP is given in Table Prob.15(a) Data input D 0 1 0 1 Output Q 0 0 1 1 89 S-R FF inputs S R 0 1 0 X X 0 1 0 . 7. we obtain Y1 = CK ⋅ T ⋅ Q Y2 = CK ⋅ T ⋅ Q Complete circuits can be drawn for each of the above cases. The K-maps for S and R outputs are prepared as shown in Fig. Prob.15(a). 7.

Prob.15 (d) gives the required truth table from which we obtain the minimized expressions for S and R as S = T ⋅Q and R =T⋅Q 90 . 7. 7.Q D 0 0 1 0 0 1 1 ´ (a) Q D 0 0 1 ´ 1 1 0 0 (b) Fig. 7.15(b) Data input D 0 1 0 1 Output Q 0 0 1 1 J 0 1 X X J-K FF inputs K X X 1 0 (c) The required truth table is given in Table Prob. 7.15(c) and the minimized expression for D is given by D = JQ + KQ Table Prob.15(c) Data inputs J 0 0 1 1 0 1 0 1 K 0 1 0 1 1 1 0 0 Output Q 0 0 0 0 1 1 1 1 D-FF input D 0 0 1 1 0 0 1 1 (d) Table Prob.15(b) from which the minimized expressions are obtained as J= D and K= D Table Prob. 7. 7.15(i) (b) The required truth table is given in Table Prob.

(iii) When the clock goes from LOW to HIGH: Case I: Let D = 0 Y1 will remain 1 and Y2 changes from 1 to 0. K = R 7. Now. Q will become 0. Q = 1. Case II: Let D = 1.18 (a) When the switch is in position 1. This means the state of the FLIP-FLOP cannot change. When the clock goes back to 0. even if the switch 91 . Y2 will remain 1 and Y1 changes from 1 to 0.15(d) Data input T 0 1 1 0 Output Q 0 0 1 1 S S – R FF inputs R X 0 1 0 0 1 0 X (e) The truth table can be prepared and expressions for J and K inputs obtained. 7.17. J=K=T Similarly. as soon as it makes contact for the first time. if the switch is changed over to position 0. (i) When the clock is LOW: Y1 = Y2 = 1 independent of D input and the state of the FLIP-FLOP cannot change. then Y1 = Y2 = 1 which also does not affect the output Q. 7. if there is any change in D. Q becomes 0. Therefore. (ii) When the clock is HIGH: Y1 and Y2 are complement to each other and for each value of D we find that the values of Y1 and Y2 do not change. When the clock comes back to 0 from 1. Y1 and Y2 will remain unaltered.17 The waveforms obtained are shown in Fig. Therefore. if there is any change in D. Y1 and Y2 will remain unaltered. 7. Q goes to 1. 7. While the clock is HIGH. Therefore. Pr = 0 and Cr = 1. Prob.Table Prob.16 Let the inputs to the latch be Y1 and Y2. while the clock is HIGH. The minimized expressions obtained are given below: (f) (g) (h) (i) (j) (k) T = J Q + KQ T =D⊕Q D = S + RQ D =T⊕Q T = S Q + RQ J = S. Now. Now. all the other conversions can be made. then Y1 = Y2 = 1 which will not affect the output Q.

the outputs Q and Q do not change.20 The waveforms are shown in Fig. This difficulty can be overcome by adding additional delay to assure reliable operation. CKs and CKD waveforms are shown in Fig.19 7.17 (a) debounces. Q = 0 and Q = 1. Prob. Now.20. 7.19 The clock. Prob. at the first contact Q becomes 1. the level triggered D-type FF will operate as a positive-edge-triggered FF. (b) When the switch is in position 1. Prob. Now. When CKD goes HIGH. the operation will not be reliable. 7. 7. 7.19.Clock 1 0 0 1 1 2 3 4 5 6 7 8 9 10 11 12 J 0 1 Q 0 1 Q 0 (b) Fig. the switch will operate in the reverse switching. Prob 7. the data is loaded into the destination FF. When the switch is thrown to position 0. Clock CKS Dt1 CKD Dt2 Fig. 92 . This means. The states of the counter are 00. if the delay time Dt2 is more than it takes to change the present output of the source FF. the clock skew may violate the hold time requirements of the destination FF. the output Q will not be affected. Prob. 01 and 10. In fact. when the switch debounces. 7. 7. Similarly.21. At the rising edge of the clock CKs.21 The waveform at CK will be as shown in Fig. the data present at the data input terminal Ds is loaded into the source FF.

1 Clock pulses 1 0 1 0 1 Q 0 = J1 Q1 0 1 0 2 3 4 5 6 7 J 0 = Q1 Fig. Prob. 7. Prob.21 93 . 7.20 Fig.

CHAPTER 8 8. 8.1(ii) 8. 94 . 8. 8. The circuit effectively reduces to that of Fig. 8. Let us assume that all the FLIP-FLOPs are in the clear state. Table Prob. The circuit effectively reduces to that of Fig. all the A AND gates are enabled and all the B AND gates are disabled. The various outputs when clock pulses are applied are given in Table Prob.1(i). Q3 FF3 D3 Q2 FF2 D2 Q1 FF1 D1 D0 FF0 Q0 Serial input Fig. Prob. This is a right-shift register. M = 1. Its state diagram is shown in Fig.1 (i) When the mode control input. Serial input D3 FF3 Q3 D2 FF2 Q2 D1 FF1 Q1 D0 Q0 FF0 Fig. i.2 A 5-stage twisted-ring counter is shown in Fig. Q4 = Q3 = Q2 = Q1 = Q0 = 0. it functions as a leftshift register. the circuit comes back to its initial state. Prob. it is a mod-10 counter. 8.2(a). Prob.1(ii). Therefore.e.2(b).2. 8.2 At the end of clock pulse 0 1 2 3 4 5 6 7 8 9 10 Q4 0 1 1 1 1 1 0 0 0 0 0 Q3 0 0 1 1 1 1 1 0 0 0 0 Outputs Q2 0 0 0 1 1 1 1 1 0 0 0 Q1 0 0 0 0 1 1 1 1 1 0 0 Q0 0 0 0 0 0 1 1 1 1 1 0 At the end of the tenth clock pulse. Prob.1(i) (ii) When M = 0. Prob. Prob. 8.. all the B AND gates are enabled and all the A AND gates are disabled. In this case the data will get shifted to the left direction.. 8. i.e.

Prob. . Y1.3 Q4 0 1 1 1 1 1 0 0 0 0 Q3 0 0 1 1 1 1 1 0 0 0 Inputs Q2 Q1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 Q0 0 0 0 0 0 1 1 1 1 1 Y0 1 0 0 0 0 0 0 0 0 0 Y1 0 1 0 0 0 0 0 0 0 0 Y2 0 0 1 0 0 0 0 0 0 0 Y3 0 0 0 1 0 0 0 0 0 0 Outputs Y 4 Y5 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Y6 0 0 0 0 0 0 1 0 0 0 Y7 0 0 0 0 0 0 0 1 0 0 Y8 0 0 0 0 0 0 0 0 1 0 Y9 0 0 0 0 0 0 0 0 0 1 95 . 8.2(a) 00000 10000 11000 11100 11110 00001 00011 00111 01111 11111 Fig. 8. respectively.3 gives the K-map for Y0 . . .2(b) 8. The truth table for the decoder is given in Table Prob. be the outputs corresponding to pulses 0. The minimized expressions are given by Y0 = Q 4 Q 0 Y1 = Q4 Q 3 Y2 = Q3 Q 2 Y3 = Q2 Q 1 Y4 = Q1 Q 0 Y5 = Q4Q0 Y6 = Q 4Q3 Y7 = Q 3Q2 Y8 = Q 2Q1 Y9 = Q 1Q0 Table Prob. . the Y outputs are don’t care. Similarly. .3.3 Let Y0. Prob. 8. 8. other K-maps can be prepared. 2.D4 Q4 FF4 Clock Clear D3 Q3 FF3 D2 Q2 FF2 D1 Q1 FF1 D0 Q0 FF0 Q0 Fig. Figure Prob. 1. 8. For all the remaining combinations of Q’s. The K-map is to be prepared for each output.

8. From the count sequence we observe that Q0 changes with every clock pulse. 96 . which are designed in the same way as Prob. 8. a 4-stage twisted-ring counter is required.4 To generate these waveforms.The circuit can be drawn using ten 2-input AND gates. 8. 8. Q3Q2 Q1Q0 00 00 01 11 10 1 0 0 ´ Q4 = 0 01 ´ ´ 0 ´ 11 ´ ´ 0 ´ 10 ´ ´ ´ ´ Fig.3 Q4 = 1 Q3Q2 Q1Q0 00 00 01 11 10 0 ´ ´ ´ 01 ´ ´ ´ ´ 11 0 ´ 0 0 10 0 ´ ´ ´ 8.5 The count sequence is given in Table Prob. 8.4(ii).4(i) Q3 Q2 f1 Q1 Q0 f2 Q2 f3 Q0 f4 Q3 Q1 Fig. 1 Clock Pulses Q3 Q2 Q1 2 3 4 5 6 7 8 9 10 11 12 13 Q0 Fig. This can be obtained by using a T-type FLIP-FLOP (FF0) with T0 = 1. Prob. waveforms can be obtained by using decoders shown in Fig.4(ii) 8.3.4(i). Prob. Prob. Prob. Prob. 8. The waveforms at the Q outputs are shown in Fig. 8.5. The required.

whereas for a DOWN counter Q outputs are to be connected to the clock inputs. Prob. T0 = T1 = T2 = 1 T0 Clock Q0 FF0 Q0 T1 Q1 FF1 Q1 T2 FF2 Q2 Q2 Fig. 8. The complete circuit is shown in Fig.Q1 changes whenever Q0 changes from 0 to 1. The desired changes in Q2 can be obtained by using Q1 as the clock input for FF2 with T2 = 1. 8. Therefore. if Q 0 is used as the clock input for FF1 with T1 = 1. 8.6 97 . 8. therefore. whereas the AND gates B are enabled when UP/DOWN input is at logic 0 connecting Q outputs to the clock inputs. Similarly. Prob. T0 = T1 = T2 = T3 = 1 T0 Clock pulses Q0 FF0 A0 T1 Q1 FF1 B0 A1 T2 Q2 FF2 B1 Q2 A2 T3 Q3 FF3 Q0 Q1 B2 Q3 UP/ DOWN Fig. Prob.5 Q2 0 1 1 1 1 0 0 0 Q1 0 1 1 0 0 1 1 0 Q0 0 1 0 1 0 1 0 1 8. the desired changes in Q1 will be obtained. The AND gates A are enabled when UP/ DOWN input is at logic 1.6 For a ripple UP counter Q outputs of the preceding stages are to be connected to the clock inputs of the succeeding stages. connecting Q outputs to clock inputs. AND-OR gates are used between stages as shown below.5.5 Table Prob. Q2 changes whenever Q1 goes from 0 to 1.

D0

D1

D2

D3

Load

Pr Q0 FF0 Q0

Pr Q1 FF1 Q1 Fig. Prob. 8.7

Pr Q2 FF2

Q2

Pr

Q3

FF3 Q3

The preset inputs are used for asynchronous loading. The relevant portion of the circuit is shown on next page. When load input is HIGH, the data at the D inputs will be entered in the FLIP-FLOPs. The other details will be same as in Prob. 8.6. 8.8 At the end of the tenth pulse Q3 = Q1 = 1, the output of G becomes 0. Also CK = 0, therefore, the output of the latch is 0. Now if Q1 or Q3 goes to 0, the output of the latch continues to be 0. When the eleventh clock pulse appears at CK, the output of the latch will go to 1 and normal counting will proceed. 8.9 (a) For the divide-by-5 circuit, the count sequence will be 000, 001, 010, 011, 100, 000. Therefore, as soon as the count reaches 101, all the three FLIPFLOPs must be cleared. The circuit is shown in Fig. Prob. 8.9.

T0 = T1 = T2 = 1 T0 Clock pulses Q0 FF0 Cr Q 0 T1 Q1 FF1 Cr Q 1 Fig. Prob. 8.9 T2 Q2 FF2 Cr Q 2

(b) For the divide-by-7, the resetting of FLIP-FLOPs is required as soon as the count reaches 111. Therefore, a 3-input NAND gate with inputs Q0, Q1, and Q2 will be required to clear the FLIP-FLOPs. 8.10 The waveforms are shown in Fig. Prob. 8.10. It is clear from the waveforms that the frequency divisions by 3, 6, and 12 are obtained at the QC, QD, and QA outputs respectively.

98

Clock 1 pulses 0 1 QD QC 0 1 0 1 QB QA 0 1 0

1

2

3

4

5

6

7

8

9

10 11 12 13

Fig. Prob. 8.10

**8.11 The states of the circuit of Prob. 8.10 are given below.
**

QD 0 0 0 1 1 1 0 0 0 1 1 1 0 QC 0 0 1 0 0 1 0 0 1 0 0 1 0 QB 0 1 0 0 1 0 0 1 0 0 1 0 0 QA 0 0 0 0 0 0 1 1 1 1 1 1 0

**(a) The ÷ 7 counter is obtained by terminating the count sequence when QB = QA = 1. The circuit is shown in Fig. Prob. 8.11(a).
**

Output QA QB QC

QD

A input 7 Clock pulses B input R1 R2 4 9 2

Fig. Prob. 8.11(a) 99

**(b) The ÷ 9 counter is obtained by terminating the count sequence as soon as QD = QA = 1. The circuit is shown in Fig. Prob. 8.11(b).
**

Output QA QB QC QD

A input Clock pulses B input

7

4

9 R1

2 R2

Fig. Prob. 8.11(b)

**(c) The ÷ 11 counter is obtained by terminating the count sequence as soon as QD = QC = QA = 1. The circuit is shown in Fig. Prob. 8.11(c).
**

Output QA QB QC QD

·

A input Clock pulses B input 7 4 9 R1 2 R2

Fig. Prob. 8.11(c)

8.12 If we use the complements of QD, QC, QB, and QA as outputs, we obtain the DOWN counter. The sequence is given in Table Prob. 8.12.

QD QC QB QA

0 1 1 1 1 1 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0 0 1 1 1 1 100

0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 (Contd.)

8. the counter is reset as soon as it becomes 1001 0110. it becomes a divideby-100 circuit. The resulting circuit is shown in Fig. two IC packages will be required. The complete circuit is shown below.13 Logic 0 8.14 IC7490 is a decade counter. To get a divide-by-96 counter. Prob. IC 7493 is a 4-bit binary counter. Prob.(Contd. 100 101 QA QB QC A input Clock pulses B input QD A input QA QB QC QD IC1 7490 S1 S2 R1 R2 IC2 7490 S1 S2 R1 R2 B input Fig.14 101 .13 Since 128 = 16 ´ 8. a divide-by-16 counter followed by a divide-by8 counter will become a divide-by-128 counter. Prob.13. 8. therefore.) QD QC QB QA 0 0 0 0 0 0 1 1 0 1 0 1 8. Therefore. 8. If two such ICs are cascaded. Q0 QA Q1 QB Q2 QC Q3 QD QA Q4 QB Q5 QC Q6 QD A input Clock pulses B input A input IC1 7493 R1 R2 B input IC2 7493 R1 R2 Logic 0 Fig.

For the mod-13 counter QD. we have to use 7493 as a mod-13 and 7492 as mod-6 counters. For the mod-6 counter. Prob. therefore.8.16 Clock pulses QA 1 2 3 4 5 6 7 8 9 10 11 12 13 QB QC QD Fig.15 8. Prob. QA QB QC QD QA QB QC QD A input Clock pulses B input 7493 R1 R2 A input B input 7492 R1 R2 Fig. Prob. The complete circuit is shown in Fig. and QA outputs of 7493 are ANDed and used to clear the counter when the count reaches 1101. 8. 8. QC.16 102 . 8.15 Since 78 = 13 ´ 6.15. QA output of 7492 is connected to B input and the QD output of 7493 is connected to A input of 7492.

8.8. The clearing operation will occur at the rising edge of the next clock. Prob.18 8. When the count reaches the maximum value (111 in 4-bit binary and 1001 in decade counter) its RC output goes HIGH which makes ENP = ENT of IC2 HIGH for one clock cycle advancing its output by 1 and making Q 103 .17 Clock pulses QA 1 2 3 4 5 6 7 8 9 10 11 12 13 QB QC QD RC Fig. Prob.18 The counter have states from 0000 to 1100.17 8. The waveforms are 1 Clock pulses QA 2 3 4 5 6 7 8 9 10 11 12 13 14 QB QC QD Cr Fig.19 The counter ICI operates as a counter for counting in the UP direction when Cr = L = 1. 8.

This will make ENP = ENT of IC3 HIGH and therefore. There are two possible operations in this circuit.outputs of ICI 0 at the next clock cycle. 0010. the clock pulses are applied at CK-DOWN input. Prob. 8. 8. When the outputs of IC1 and IC2 both reach the maximum count. the counter is loaded with P inputs which must be PA = PB = PC = PD = 0.20 QC QD (b) Cr L 8. As soon as the count reaches 1100. Prob.20(a) between the QC. Prob. 0100. When the output becomes 0. the next clock pulse will be registered in this counter and simultaneously IC1 and IC2 will be cleared. QD outputs and the clear input (with L = 1).21(b). 8. 8. the counter is cleared. The circuit is given in Fig. 8. Prob.27. the counter is loaded with preset inputs 0101 and the states will be: 0101. This way the counting will continue.21 For the DOWN counter. 8. and 0001. 8. QA +VCC CK-UP CK-DOWN Cr PA PB PC PD L Borrow 74192 QB QC QD Carry Clock pulses +VCC Fig. 0011. 8. Prob. Alternative II: Connect the circuit shown in Fig. whereas only one type of operation is possible in the circuit of Fig. Prob. QD outputs and load (L) input (with Cr = 1).20 Alternative I: Connect the circuit shown in Fig. QC QD (a) Fig.21(a) and waveforms are shown in Fig. As soon as the count becomes 1100. After this clock cycle ENP = ENT = 0 for IC2 and IC1 will go on counting the pulses.20(b) between QC.21(a) 104 . RC outputs of both of these ICs will go HIGH.

8.22(ii) is obtained to determine the FF inputs.21(b) 8.22(ii) X 0 0 Counter State QA QB 0 1 0 1 JA 1 X 105 FLIP-FLOP Inputs KA JB X 0 1 X KB X 1 (Contd. 8. Its state table is given in Table Prob.22(a) 00 0 0 1 1 01 Table 8. Prob.22(a).22(i) from which Table Prob. 8.Clock 1 pulses 0 1 QA 0 QB 1 0 QC QD 1 0 1 0 Borrow Fig. 8. Prob.22(i) Next State Present State A B 0 0 1 1 0 1 0 1 X=0 A 1 0 0 1 B 1 0 1 0 A 0 1 1 0 X=1 B 1 0 1 0 Table Prob.) . 1 11 1 0 0 10 Fig. 8. Prob.22 The modified state diagram is given in Fig. 8.

22(b). 011. The unused states are taken as don’t care (X) conditions. 010. Prob. K0 FF1 : J1. The states of this circuit are: 000. 8. 8. 001.22(b) QB QB QB JA FFA KA QA QA 8. it requires four FFs. and 100.) 106 . K3 The count sequence and the corresponding values of the FF inputs required to get the count sequence are given below.22(ii) X 0 0 1 1 1 1 Counter State QA QB 1 0 0 0 1 1 0 1 0 1 0 1 JA X 0 0 1 X X FLIP-FLOP Inputs KA JB 1 X X X 0 1 1 X 1 X 1 X KB X 1 X 1 X 1 This gives and JB = KB = 1 JA = KA = (QB ¤ X) The circuit is shown in Fig. FF0 : J0. The Q2 output will be the required output when the input waveform is used as the clock input. 8.) Table Prob. K1 FF2 : FF3 : J2. Q3 0 0 Count Sequence Q2 Q1 Q0 0 1 1 0 1 0 J0 X 1 K0 1 X J1 X 0 FF Inputs K1 J2 1 X 1 X K2 X 0 J3 0 0 K3 X X (Contd. Logic 1 JB FFB KB Clock pulses x = 1 UP = 0 DOWN Fig.24 Since there are ten states.(Contd.23 A divide-by-5 circuit will give the required input-output relationship. therefore. Prob. The FFs with their inputs are given as follows. 8. K2 J3.

) Q3 0 0 0 1 1 1 1 1 0 Count Sequence Q2 Q1 Q0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 J0 X 1 X 1 X 1 X 1 K0 1 X 1 X 1 X 1 X J1 1 X X 0 1 X X 1 FF Inputs K1 J2 X 0 1 X X 0 1 X X X X 0 0 0 1 X K2 0 0 1 X X X X 1 J3 0 0 1 X X X X X K3 X X X 0 0 0 0 1 Using K-maps.(Contd. 8. 8. the circuit can be drawn.25. Pulses Logic 1 QA ENT ENP QB QC QD 74163 Load Cr Logic 1 Fig. Prob.25 The circuit is given in Fig. 8.25 107 . the expressions for FF inputs can be minimized and the minimized expressions are: J0 = K0 = 1 J1 = Q1 ⋅ Q0 + Q3 ⋅ Q2 K1 = Q0 J2 = Q1 ⋅ Q0 K2 = Q1 ⋅ Q0 + Q3 ⋅ Q2 J3 = Q2 ⋅ Q1 ⋅ Q0 K3 = Q2 Using the FLIP-FLOPs and the above expressions. Prob.

Prob.26(a) 0/0 1/1 0/0 11 1/0 10 0/0 Fig.) . Prob. 8.26(b) 1/0 01 0/0 00 1/0 (c) Present State Q1 0 0 Q0 0 0 Input X 0 1 Next state Q1* 0 0 Q0* 0 1 108 Output Y 0 0 J1 0 0 FF FF1 K1 X X J0 0 1 Inputs FF0 K0 X X (Contd. 8.8.26 (a) Q1 Q1 Q0 Q1 Q0 D1 Q1 FF1 Q1 Y Q0 Q0 X D0 Q0 FF0 Q0 (b) Clock Fig.

Prob.) Present State Q1 0 0 1 1 1 1 Q0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 Next state Q1* 0 1 1 1 1 0 Q0* 1 0 0 1 1 0 Output Y 0 0 0 0 0 1 J1 0 1 X X X X FF FF1 K1 X X 0 0 0 1 J0 X X 0 1 X X Inputs FF0 K0 0 1 X X 0 1 Q1Q0 X 00 01 11 10 0 1 0 0 0 1 ´ ´ ´ ´ Q1Q0 X 00 01 11 10 0 ´ 1 ´ ´ ´ 0 1 0 0 J1 = Q0× X Q1Q0 X 00 01 11 10 0 1 0 1 ´ ´ ´ ´ 0 1 K1 = Q0× X Q1Q0 X 00 01 11 10 0 ´ 1 Y = Q1 × Q0 × X ´ 0 1 0 1 ´ ´ J0 = X K0 = X X J1 FF1 K1 Q1 Q1 J0 FF0 K0 Clock Fig.(Contd. 8.26(c) Q0 Q0 8.27 (a) D1 = Q1 ⊕ X D0 = Q0 ⊕ Q1 Z = Q1 ⋅ X + Q0 109 .

(b) The state table will be Q1 0 0 1 1 1 1 0 0 Present State Q0 0 0 0 0 1 1 1 1 Input X 0 1 0 1 0 1 0 1 Next State Q1* Q0* 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 Output Z 1 0 0 0 1 1 1 1 Here. 8. we obtain the output sequence as 001110. and X as the input variables as given below. the initial state has been assumed as Q1 Q0 = 00 and correspondingly the other states have been assigned.28 Present Q1 0 0 0 0 1 1 1 1 State Q0 0 0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 0 1 Next State Q1* 0 0 1 0 1 1 1 0 Q0* 0 1 0 1 0 1 1 0 FF1 J1 0 0 1 0 X X X X K1 X X X X 0 0 0 1 J0 0 1 X X 0 1 X X FF inputs FF0 K0 X X 1 0 X X 0 1 From the state diagram.28(a) The circuit can be drawn using the above expressions. Q0. Prob. state table as shown above is prepared and inputs to FF0 and FF1 are obtained using the excitation table of J-K FF. K1. 8. X Q1Q0 00 01 11 10 0 0 1 0 1 0 ´ ´ ´ ´ X Q1Q0 00 01 11 10 0 ´ 1 ´ ´ ´ 0 1 0 0 J1 = Q0× X Q1Q0 X 00 01 11 10 0 1 0 1 ´ ´ ´ ´ 0 1 K1 = Q0× X Q1Q0 X 00 01 11 10 0 ´ 1 0 ´ 1 ´ 0 1 ´ K0 = Q1 ¤ X J0 = X Fig. and K0 with Q1. 110 . K-maps are prepared for J1. From the table. J0.

and J-K FLIPFLOPs are given in the Table.29 The State table along with the inputs required for T. 8.J0 FF0 K0 Clock X Q0 J1 FF1 Q1 Q0 K1 Q1 Fig. 111 . S-R. From this the simplified expressions for these inputs are obtained using K-maps.28 (b) 8. These are T2 = Q 2 ⋅ Q1 ⋅ Q 0 ⋅ X + Q 2 ⋅ X + Q 0 ⋅ X T1 = Q 0 + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X T0 = Q 0 + Q1 X and Y = Q0 ⋅ X S2 = Q 0 ⋅ X + Q1 ⋅ Q 0 ⋅ X R2 = Q 0 ⋅ X S1 = Q 0 + Q 2 ⋅ X R1 = Q 2 ⋅ X + Q 2 ⋅ Q 0 ⋅ X S0 = Q 1 ⋅ Q 0 ⋅ X R0 = Q0 and Y = Q0 ⋅ X J2 = Q1 ⋅ Q 0 ⋅ X + Q 0 ⋅ X K2 = X J1 = Q 0 + Q 2 ⋅ X K1 = Q 2 ⋅ X + Q 2 ⋅ X J0 = Q1 ⋅ X K0 = 1 (a) (b) (c) and Y = Q0 ⋅ X The complete circuits can be drawn using the above expressions. Prob.

112 .

Present State Q2 Q1 Q0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 Input Next State Output X Q2* Q1* Q0* Y J2 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 X X K2 X X X X X X X X 1 0 FF inputs J1 K1 J0 1 0 0 1 X X X X 1 0 X X X X 0 1 1 1 X X 0 1 X X 1 0 X X 1 0 K0 X X 1 1 X X 1 1 X X The simplified expressions are: J2 = Q 0 ⋅ X + Q1 ⋅ Q 0 ⋅ X K2 = X J1 = Q 0 ⋅ X + Q 0 ⋅ X K1 = Q0 + X J0 = Q 2 ⋅ Q1 ⋅ X + Q1 ⋅ X + Q 2 ⋅ X K0 = 1 Y = Q 2 ⋅ X + Q1 ⋅ X + Q1 ⋅ Q 0 The Complete circuit can be drawn using the above expressions. 8. J0.31 The state diagram is given below. J1.17 along with the inputs J2. K2. 8.30 Table 8. 1/0 1/0 000 1/0 001 1/1 010 1/0 0/0 1/0 111 1/1 0/1 110 0/0 0/1 101 0/1 Fig. and K0 required for the FFS is given below.31 0/0 011 0/0 0/0 100 1/0 113 .8. Prob. K1.

(b) The circuit can be designed using the method similar to the design of Probs. 8. the next states and the outputs are same. Table Prob.30. 8. 8. the state 010 can be eliminated and the reduced state table is given in Table Prob. This means these two states are identical and one of them can be eliminated. Therefore.31 (b) Present State Q2 Q1 Q0 * Q2 Next State X=0 * * Q1 Q0 0 1 1 0 1 1 1 0 1 0 * Q2 X=1 * * Q1 Q0 0 0 0 0 1 1 0 0 1 1 Output Y X=0X=1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0 0 0 8.15. 8. the states 011 and 111 are identical.28. 8. 01000111010 8.33 The output sequence can be obtained similar to Prob. second column). 8. 114 . Prob. When X1. 8.31 (a).34(a) (i) by solid arrows.31 (b).32 (a) The circuit can be designed using the method similar to that of Example 8. 8.From Table 8. and 8. 8.34 (a) (i) The circuit is initially in stable total state 0001 (first row. Therefore.29(c).27(b) and is given below. the state transitions will be 00 ® 11 ® 11 Shown in the Fig.18 we observe that from the present states 001 and 100. X2 because 11. From this we observe that the states 000 and 010 are identical. eliminating the states 100 and 111 we obtain Table Prob.26(c).31(a) Present State Q2 Q1 Q0 * Q2 Next State X=0 * * Q1 Q0 0 1 0 1 0 1 1 1 1 0 1 0 * Q2 X=1 * * Q1 Q0 0 1 0 0 0 1 1 0 1 0 1 1 Output Y X=0X=1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 Table Prob. Similarly. 8.

the circuit goes to 10 stable state from 10 unstable state. Prob. 11 ® 10 ® 00 ® 00 or 11 ® 01 ® 00 ® 00 depending upon whether Q1 changes first or Q2 changes first. both the states are required to change here.34 (a) (ii) 11 11 10 00 01 11 10 (b) In (a)-(i) The circuit is required to change from stable state 00 to stable state 11 . race condition exists.X1 X2 Q1 Q2 00 00 01 11 10 01 00 11 10 11 10 11 10 Fig.34(a) (ii) Here again both the states are required to change. 115 .34(a) (ii) Q1 Q2 X1 X2 00 01 00 00 00 00 Fig. 8. but due to unequal time delays. If it is 10. 00 ® 10 ® 10 (ii) The circuit is initially in stable total state 1111 (third row. state transitions will be 00 ® 01 ® 10 ® 10 Shown in the Fig. Prob. If it is 01. In (a)-(ii).34(a) (i) by dotted arrows. the circuit goes to stable state 10 which shows that the race is critical.34(a) (i) Since. 8. therefore. Prob. the state transitions will be 11 ® 00 ® 00 It is shown by solid arrows in Fig. 8. third column). 8. therefore. Both are shown in Fig. When X1 X2 becomes 01. Prob. race condition exists and the circuit will either attain 01 or 10 state first. Prob. 8. The circuit will be making transitions.

therefore. Prob. 8. + + (b) K-maps are prepared for Q1 and Q 2 from the state transition table. All the remaining squares are unspecified. These are shown in Fig. the entry in the first row. therefore. X1 X 2 Q1 Q2 00 01 11 10 00 0 0 ´ ´ 01 ´ 1 1 ´ 11 0 0 1 ´ 10 0 0 0 ´ X1 X2 Q1 Q2 00 00 01 11 10 0 0 ´ ´ 01 ´ 1 1 ´ 11 1 1 1 ´ 10 0 1 1 ´ + (i) K-map for Q 1 + (ii) K-map for Q 2 Fig. first column will be 00 . 8.35 (a) X1 X2 00 Q 2 Q2 00 01 11 10 00 00 – – 01 – 11 11 – 11 01 01 11 – 10 00 01 01 – Fig.35(b). Prob. the next state specified is 00. Prob.35(a). squares corresponding to input sequence are filled. fourth column will be 00 . again the next state specified is 00. 8. the race is non-critical.The state change is from 11 to 00 through both the paths and therefore. the entry in the first row. 8. These are shown in Fig.35 (b) The next state logic equations are + Q1 = X 1 X2 + X2 Q1 + Q 2 = X2 + X1 Q2 116 .35 (a) Transition Table For X1 X2 = 00. Similarly. 8. Prob. When X1 changes to 1 while X2 = 0.

–. the output may change during unstable b or stable b . the input can change to 00 or 11. the output Y may be 0 or 1 and the next-state will be b. is not possible when the circuit is in stable state e . since the outputs for stable states f and a are 1 and 0 respectively. When the circuit is in stable state f . fifth row will be –. therefore. X1 X2 X2 Q1 X1 Q2 Q1+ Q2+ Fig. Y = 1 and the next state will be f and then f . From f . Prob 8.35(c) Logic diagram 8. –. Prob.(c) The logic circuit is shown in Fig. X1 X2 = 00. sixth row will be –. the output is 0 and for the stable state e the output is 1.35 (c). the next-state will be a and the output may be 0 or 1. If it changes to 00. When X1 X2 becomes 11. the next state and the output are unspecified for X1 = X2 = 0 and the entry in the first column. therefore. Y = 1. the next-state will be e and since X1 = 1 and X2 is changing state. the entries in the second column.36 When the circuit is in stable state e inputs can change to 01 or 10. it can not go to X1 X2 = 01. therefore. 117 . When X1 X2 = 01. Similarly. while transition from e ® b ® b . when X1 X2 = 10. 8. X2 has changed while X1 = 1. therefore. Since for the stable state b .

and so on. Thus. Therefore. 9. vo = – (VZ2 + VD) This gives voltage at the non-inverting input terminal as − (V Z 2 + V D ) 118 R2 R1 + V R1 + R 2 R1 + R 2 R . at t = 0. thereby discharging the capacitor with the same time constant through the output transistor of the AND gate. 9. square waveform will be generated at the output. When vc reaches V(1). vc V(1) t V(0) t vo V(1) t V(0) 0 T1 T2 Fig. Prob.3 When the voltage vi at the input is very low. This shows that it is not possible for vo to be in logic 0 state under steady state. the output voltage vo will change from (VD + VZ1) to – (VZ2 + VD).. vo = V(1). the output of the inverter goes to V(0). It will saturate at vo = VD + VZ1. The waveforms of vc and vo are illustrated below. when vi > VUT .CHAPTER 9 9. i. the output of the AND gate will be V(1) which will charge the capacitor C with the time constant t = RC.2 Let vo be in logic 0 state under steady-state condition. the output voltage will be maximum positive. the capacitor will get charged to voltage V(1) making the input to the inverter as logic 0 which produces logic 1 at the output.1 Let us assume that the voltage vc = V(0). Hence R2 R1 (V Z 1 + VD ) + VUT = V R1 + R 2 R1 + R 2 R Now. This makes the voltage at the non-inverting input terminal as R2 R1 (V Z 1 + V D ) + V R1 + R 2 R1 + R 2 R When the voltage at the input increases and passes through the above voltage.1 t 9. the voltage corresponding to LOW level.e. The output of the NAND gate will be logic 1.

9.2 V. Hence VLT = − R2 R1 (V + VD ) + V R1 + R 2 Z 2 R1 + R 2 R 9. As soon as the decreasing input voltage passes through VLT. the output vo changes from – (VZ2 + VD) to + (VZ1 + VD). the output comes back to +5.2 V 0 t -5. vi 5V VUT VLT 0 t -5V (a) vo 5. Now.4(b).0042 V VLT = − 0. we obtain VUT = 0.4 Using the expressions for VUT and VLT derived in Prob. 6 + 0. 1 » 0.2 V (b) Fig. 1 100 + 0. 6) + 100 (1) 100 + 0.2 V to –5.4(a) with VUT and VLT marked.When the voltage at the input decreases and passes through this value. The output waveform is illustrated in Fig. the output changes from +5.4 119 . 6 ) + 100 (1) 100 + 0.1 » 1. when the increasing input voltage passes through the voltage VUT.2 V.2 V and remains at that level as long as the input voltage is higher than VLT.9938 V The input waveform is shown in Fig. When the input voltage is zero.3. 9. Prob. 1 ( 4.1 ( 4. 9. Prob.1 100 + 0. the output is + 5. 6 + 0. 9. Prob.

Similarly. the discharge will be terminated as soon as vc reaches –b Vo′ . at which time the output will swing back from – Vo′ to + Vo′′ . During the discharging of the capacitor. where b = (R2/R1 + R2). the capacitor will discharge with the same time constant from b Vo′′ to – Vo′ . The capacitor C will be charging from –b Vo′ to Vo′′ with the time constant t = RfC. during the interval T2 when the output is negative. the output voltage levels will be Vo′ = VZ2 + VD1 – VD » VZ2 and Vo′′ = VZ1 + VD2 – VD » VZ1 120 . the feedback resistance R¢f in series with the conducting diode D will be in the circuit. vc = b Vo′′ b Vo′′ = Vo′′ – ( Vo′′ + b Vo′ ) e. Consequently. vc = b Vo′ b Vo′ = – Vo′ + ( Vo′ + b V o′′ ) e–T2/t T2 = t 1n Vo′ + bVo′′ Vo′ (1 − b ) The charging and discharging will go on in the same way and the time period of the resulting output square waveform will be T = T1 + T2 1 1 and the frequency = f = = T T1 + T2 9.5 The maximum negative output voltage Vo′ and the maximum positive output voltage Vo′′ are given by Vo′ = VZ2 + VD1 and Vo′′ = VZ1 + VD2 Let us assume the output voltage to be maximum positive (V 0′′ ). Therefore. R¢¢ in series with the conducting diode will f be effective. the output voltage changes from positive maximum to negative maximum ( Vo′ ). The capacitor voltage is given by vc = V o′′ – (Vo′′ + b Vo′ )e – t/t at \ or t = T1.6 During the interval T1 when vo is positive.9. However.T1 /t T1 = t 1n Vo′′ + bVo′ Vo′′ (1 − b ) At T1. vc = – Vo′ + ( Vo′ + b V o′′ ) e – t/t at \ or t = T2.

9. This shows that the output voltage cannot remain as –Vo under steady-state. At this voltage. 9. The charging gets terminated when vc reaches VUT and the output changes to V(0) = 0 V.6 9.VO ¢ T1 T2 T3 T4 Fig. In case R¢f ¹ R¢¢f .If we assume identical Zeners for convenience. Prob. the periods T1 and T2 can be obtained using the relationships derived in Prob.7 If vo = –Vo under steady-state. the capacitor C charges with the time constant t = RC. the output goes back to V(1). t 2 = R ′′ C f Vo′ (1 − b ) and The output voltage waveform is shown in Fig. i. t 1 = R′ C f Vo′′(1 − b ) Vo′ + bVo′′ . the square wave f will be symmetrical. Prob. When the capacitor voltage passes through the voltage bVo. 9. the capacitor discharges with the same time constant until its voltage becomes VLT.e. v V ¢¢ o bVO¢¢ vc t2 t vo t1 0 -bV¢¢ O .8 When the output voltage is in logic 1 state.5 and are given by T1 = t 1 1n T2 = t 2 1n Vo′′ + bVo′ .6. The timings T1 and T2 corresponding to the charging and discharging of C respectively are given by T1 = RC 1n T2 = RC 1n V (1) − V LT V (1) − VUT and VUT V LT 121 . the output voltage will go to +Vo. 9. Now. and R¢f = R¢¢. the capacitor C will get charged with the polarity opposite to that indicated in the figure. V(1)..

2 × 10 −6 ≈ 200 pF 0. 9. A circuit using OP AMP Schmit trigger circuit is shown below. On the other hand.9 An astable multivibrator with T1 = 30 s and T2 = 60 s can be used for this purpose. b = 1 2 and C = 1000 mF R¢f = 27. we obtain (using the results of Prob.6 kW TON » 0.Hence.5 kW C = 0.VUT 9. 5 × 10 3 122 9.9 – GREEN and Let \ T2 = τ 2 1n 1+β 1−β R1 = R2 = 100 kW.6). Prob. In this circuit when the output is positive.10 (a) The pulse duration is given by . 9.3 kW and R¢¢f = 54. 7 × 1. diode D3 conducts and the RED bulb is ON. T1 = τ 1 1n 1+ β 1− β R¢ f R¢¢ f – + D1 D2 R – R1 + + VZ VZ RED D3 D4 vo C R2 Fig. VUT ù é V (1) . the diode D4 will conduct when the output is negative and consequently the GREEN bulb will be ON. Assuming identical Zener diodes.VLT + 1n T = T1 + T2 = RC ê1n ú VLT û ë V (1) .7 RC Assuming R = 1.

9. 7 × 2 × 10 −3 The duty cycle is 67% with the internal resistor.12 The frequency and duty cycle are given by 1. 4 f= C (RA + 2RB ) and D = (9. Therefore. 5 × 10 −3 5 × 10 −3 ≈ 178. ns R = 50 kW R = 30 kW R = 20 kW R = 10 kW R = 5 kW 1 2 4 10 20 40 100 200 400 1000 CEXT External timing capacitance. 57 µF 0. Therefore. pF Fig. we obtain from the graph C » 35 pF. Assuming R = 10 kW. fmax = 180 Hz 9. 7 × 40 × 10 3 (b) C= The duty cycle is 90% with an external resistance of 40 kW. 5 m s 0. 6 nF 0.2) . 67 and the maximum frequency. 9.1) RA + RB × 100 RA + 2RB 123 (9. the time period.(b) The pulse duration for C < 1000 pF is given by the graph shown in Fig. 10000 7000 4000 2000 1000 700 400 200 100 70 40 20 10 122 123 TON Output pulse width. Prob.8.8 9. the maximum frequency.11 (a) Here R = 2 kW \C= 5 × 10 −3 = 3. T = 5 = 7. fmax = 1 ≈ 134 Hz 7. Prob.

Prob. The waveforms of vc and output voltage. 9. we obtain C= 1. (b) The circuit corresponding to the charging of the capacitor C is shown in Fig. 9. the output voltage is HIGH and the capacitor charges with the time constant t1 = RAC. vc. the capacitor gets discharged through RA and RB with the time constant t2 = (RA||RB) C and the output voltage drops to 0 V. When vc reaches 2/3 VCC. the charging starts again.12 9. As soon as this decreasing voltage crosses 1/3 VCC. During charging the voltage across the capacitor. Prob. 9.1). from Eq. 4 ≈ 4. vo are illustrated in Fig.13 (a) When the voltage across the capacitor (vc) is increasing and is less than 2/3 VCC.13(b) and corresponding to the discharging is shown in Fig. (9. 9. Prob.12. Prob. Assuming RA = 1 kW Now. 9.13(c). vc = 2 VCC 3 124 at . Prob.13(a). (9. 67 nF × 10 3 × 100 × 10 3 3 The circuit is shown in Fig. VCC RA 4 8 7 2 555 6 + C 5 1 3 – vC vO RB 0.2) 60 = or RA + RB × 100 RA + 2RB RB = 2RA. is given by vc = 1 VCC + 2 VCC (1 − e − t / τ 1 ) 3 3 t = T1.From Eq.01 mF Fig.

Prob. 9.2 RB û 125 .7 t1 = 0.7 RAC During discharging.RB ù C 1n ê ú + RB RA ë RA .13 (c) \ or e .t /t 2 + VCC vc = ê VCC R A + RB R A + RB ë3 û at which gives T2 = t = T2. vc is given by RB RB é2 ù VCC ú e .vC To VCC 2/3VCC t1 1/3VCC To 0V 0 T1 vo V(1) t T2 t t2 0 T (a) VCC RA RA vC + – vC C + – C RB VCC (b) Fig. vc = 1 3 VCC R A RB é 2 R A .T1 /t 1 = 1 2 T1 » 0.

13 c.14 A B The output is in LOW state until the first falling edge (A) appears.RB ù 1n ê ú RA + RB ë RA . 126 .40 û or RA » 48 kW (e) From Fig.1 RAC and then goes LOW.2 RB û RB = 20 kW From part (a). 9.7 R A RA + 20 ë RA . Prob. If (n – 1) T < T < nT1 where n is an integer. 9. It remains HIGH for a period T = 1. at which time it goes HIGH.7RA = (d) If R A RB é 2 R A . 9.e.\ T = T1 + T2 = 0. then the frequency of the output waveform will be fo = fi æ 1ö ç fi = T ø ÷ n è 1 Thus the circuit functions as a frequency divider. 50% duty cycle). Prob.RB ù C 1n ê ú RA + RB ë RA . T1 Input pulses Output 0 1 T Fig. 9. It will remain LOW till the next negative edge (B) appears. or R B < A 3 2 RA + RB 9.7 RAC + Duty cycle = T1/T ´ 100% RA RB é 2 RA . we observe that it is possible to make T1 = T2 (i. Prob..35 are given in Fig. The condition which must be satisfied to achieve this is 0.2 RB û (c) From the expressions for T1 and T2 obtained in part (b).14 (a) The input pulses and the corresponding output for this monostable circuit of Fig. we obtain RB R VCC < 1 VCC .14.20 ù 1n ê ú = 0. we obtain RA 20 é 2 RA .

2 ms < T < 0. the circuit becomes a retriggerable monostable multivibrator.2 kW and C = 0. When the input pulse goes from LOW to HIGH.1 RC. the output goes to HIGH for a time period T = 1. When the voltage across the capacitor reaches 2/3 VCC.1 RAC Therefore. 9.(b) Here T1 = 1 m s 10 Choose RA and C values in Fig.15 If the output is in HIGH state under steady-state. it is not possible for the circuit to be in HIGH output state under steady-state. In this circuit.16 In the circuit of Fig. whenever the trigger pulse goes LOW. 127 . the transistor goes to saturation. the output and the discharge terminals go LOW. the transistor T1 of the timer is cut-off and the capacitor is therefore getting charged.1 mF then T = 0. thereby discharging C and the output goes LOW..242 m s 9. if we choose RA = 2.35 such that Since 0.3 m s T = 1. the circuit is reset.e. Thus. if we connect pin-4 (Reset) to pin-2 (Trigger) it becomes a retriggerable monostable multivibrator.35. Hence. i. 9. 9.

Prob.5 – 1.5 – 3. 128 .5 + 3.5 + 3. From this we obtain Iin = VR (8 /11R) × ( r + 8 /11R) r (8 /11R) 2R + ( r + 8 /11R ) VR 2R The current due to b6 is \ or V R (8/ 11R ) VR = 2 R( r + 8 /11R) + r (8/ 11r ) 16 × 2 R r=8R RF b2 2R r Iin + VO VR R| |4R| |8R Fig.CHAPTER 10 10.2 10 10 S = V.3(a).5 + 3. Prob. and b1 = 1. The equivalent circuit corresponding to the lower order four bits is shown in Fig. From this we observe that this circuit converts digital inputs in one’s complement format to analog output. The step size or resolution = Digital Input S2 S1 S0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output voltage without offset – 3.5 + 3.5 – 0. 10. The analog output voltages for each of the digital inputs are given below.5 Output due to offset + 3. i.5 – 3.3 (i) Let b3 = 0.3(a) (ii) Let b3 = b2 = b0 = 0.5 + 2. The corresponding equivalent circuit is shown in Fig. 10. As long as DV < .e. 10.5 + 0. 2 8 − 1 255 2 5/255 V the least-significant bit will be significant.5 + 1..5 Net Output Vo 0 1 2 3 –3 –2 –1 0 10.5 – 3.5 – 3.1 10.3(b).5 – 2. Prob. b2 = 1 and b1 = b0 = 0.

4. 10. Therefore. we obtain r = 8R RF b0 8R r Iin VR R| |2R| |4R + VO Fig. 10. 10. The analog output voltages for various digital inputs are given in table The output voltage is given by RF RF æ RF ö Vo + V1 + V2 ÷ Vo = . Prob.ç R R /2 R /3 ø è 129 .3 (c) 10. Prob.4 The modified circuit will be equivalent to the circuit given in Fig. RF b1 4R r Iin + VO VR R| |2R| |8R Fig. 10.3(b) (iii) Let b3 = b2 = b1 = 0. Prob.Iin = VR (8 /13 R) ´ r (8 /13 R ) ( r + 8 /13 R) 4R + r + 8 /13 R VR . to satisfy the same condition.3(c) from which we obtain Iin = VR ( 4 / 7 R) × ( r + 4 / 7 R) r ( 4 / 7 R) 8R + ( r + 4 / 7 R) The current due to b4 is VR/8R. and b0 = 1 The equivalent circuit is shown in Fig. we obtain r = 8 R. 4R The current due to b5 is To satisfy the same condition.

10. Table Prob. 10.4 where Vn = – =+ 1 2 1 2 if Sn = 1 if Sn = 0. Prob. 10. This circuit without offset gives an analog output of –7.S0 R RF = R R/2 + S1 VO S2 R/3 Fig. Prob. Prob.5 The circuit for 4-bit D/A converter is shown in Fig.4 S2 0 0 0 0 1 1 1 1 Digital Inputs S1 S0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Analog Output V 0 +1 +2 +3 –3 –2 –1 0 We observe from the table that this circuit also converts digital input in one’s complement format to analog output.5 130 . 10.5 V for the digital input 0000 and + 1/2 V1 0 1 0 1 0 R/2 RF = R + VO R 0 1 S2 ROFF 1/2 V + R/4 V (1) = -1/2 V R/8 1 0 V (0) = 1/2 V Fig.5. 10.

R RX = 4 + 2 + 1 or RX = R/7 R R/2 R/4 R/7 S3 Fig. There is one more negative number than the positive numbers in 2’s complement representation.+7. R Therefore. The reference voltages are given below.5 V for the digital input 1111.5 V for 1111 input.6 When the 4-bit digital input is 0000. The step size will be 2/7 V0. the output voltage will be - 1 2 RF RF RF ö æ RF ç .5 V for 0000 input and –7. the offset required is +7. This voltage must be 0. Reference voltages V0 VR7 = 5/7 V0 VR6 = 3/7 V0 VR5 = 1/7 V0 VR4 = –1/7 V0 VR3 = –3/7 V0 VR2 = –5/7 V0 VR1 = –V0 –9/7 V0 0 2’s complement digital output S 011 010 001 000 111 110 101 100 If we choose to ignore 100 output. ROFF = 15 10. Prob. 131 . RX is the resistance in the path of switch S 3 . 10.7. 10. Prob. Therefore.6. The circuit is shown in Fig. 10. The decoder circuit can be designed in the usual manner. S0 S1 S2 RF = R 10.R + R /4 + R /2 + R ÷ è ø X where.6 + VO The resulting circuit is shown in Fig. Prob. Therefore.7 Let the analog voltage range be from –V0 to +V0. the resistor chain will be connected between +V0 and –Vo and only six comparators will be required.

Prob.8 The conversion time t is given by Va ⋅ 2 N ⋅ TC VR where. N is the number of bits in the digital output. f < 12 per second. TC is the time period of the clock. Va is the analog voltage. 132 .V R Va Analog voltage VR7 = +5/7 V0 R VR6 = +3/7 V0 R VR5 = +1/7 V0 R VR4 = –1/7 V0 R VR3 = –3/7 V0 R VR2 = –5/7 V0 R VR1 = –V0 R –9/7 Vo Fig. and VR is the reference voltage. Therefore. 10. f< 10 5 8192 Therefore.7 – + – + – C5 Two’s complement format + – + – + – + – + C1 C2 C3 C4 L A T C H E S D E C O D E R C6 C7 B2 ü B1 ý B0 þ ï ï 10. when Va = VR t = 2 N ⋅ TC + t = 2 N + 1 ⋅ TC = 2 13 × 10 −5 or. The largest Va can be equal to VR.

22 2. 10. it will be coded in CTC as 0001. For example.44 mV mV mV mV mV 10. 10.11 (a) CSB: It is complementary straight binary code. Decimal 2 will be coded in CSB as complement of 0010. (d) CCD: It is complementary coded decimal code.88 1. for example. the voltage corresponding to LSD = 10/1000 = 10 mV (b) ADC 80 is a 12-bit A/D converter. the straight binary code for decimal 2 is 0010.44 mV mV mV mV mV (ii) Complementary coded decimal code (CCD) input The analog output range for this code is 0 to + 10 V. It is determined by finding out CSB and then offsetting it by –2n – 1. (i) Complementary binary input (CBI) Table Prob. (c) CTC: It is complementary two’s complement code.10. Table Prob. 10.44 4. decimal 2 will be coded as 1101 – 1000 = 0101.22 2.10 (a) DAC 80 is a 12-bit D/A converter.10(a) gives the voltage corresponding to LSB for each of the ranges.10(a) Analog output range 0 0 0 0 0 to ± 2.44 4. The voltages corresponding to LSB for various analog input ranges are given in Table Prob. two’s complement representation of – 2 is 1110 and therefore.10(b) Analog input voltage range ± 2.5 V to ± 5 V to ± 10 V to + 5 V to + 10 V Voltage corresponding to LSB 1. which is 1101.88 1. For example. Where n is the number of bits used to represent the number. natural BCD code 133 .22 2.5 V ±5V ± 10 V 0 to 5 V 0 to 10 V Voltage corresponding to LSB 1.22 2. (b) COB: It is complementary offset binary code. Table Prob.9 The voltage step = = 10 V 26 −1 10 V 63 10. For example. Therefore.10(b). It is obtained by complementing the natural BCD code. 10. It is obtained by complementing two’s complement.

10. Table Prob.11 gives the decimal number for each of the 4-bit binary numbers in each of the above codes.11 Binary CSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Equivalent decimal values COB CTC +7 +6 +5 +4 +3 +2 +1 0 –1 –2 –3 –4 –5 –6 –7 –8 –1 –2 –3 –4 –5 –6 –7 –8 +7 +6 +5 +4 +3 +2 +1 0 CCD – – – – – – 9 8 7 6 5 4 3 2 1 0 134 . Table Prob. 10. it will be coded in CCD as 1101.for decimal 2 is 0010 and therefore.

0000 to FFFF. 00 to 3F.2 (a) 0 to 3.3 The maximum access rate = 1/Cycle time gives the maximum rate for each memory.CHAPTER 11 11. Memory A B Maximum rate 1 × 10 9 = 666666/s 1500 1 × 10 9 = 1724137/s 580 (Contd. 000 to 377. (b) 0 to 3. 000 to 7FF. 0000 to 3777. 000000 to 177777. 00 to 17. 11. 0000 to 1777.1 The number of pins P is given by 2P = M (a) P = 2 Address range: A1A0 = 00 to 11 (b) P = 4 Address range: A3A2A1A0 = 0000 to 1111 (c) P = 6 Address range: A5A4A3A2A1A0 = 000000 to 111111 (d) P = 8 Address range: A7A6A5A4A3A2A1A0 = 00000000 to 11111111 (e) P = 10 Address range: A9A8A7A6A5A4A3A2A1A0 = 0000000000 to 1111111111 (f) P = 11 Address range: A10A9A8A7A6A5A4A3A2A1A0 = 00000000000 to 11111111111 (g) P = 16 Address range: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (h) P = 20 Address range: A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11. 0 to F. It is given below for each memory.) 135 . 00000 to FFFFF. 0000000 to 3777777. 00 to 77. 000 to 3FF. 00 to FF.

11. 11. the width of the address bus required is 12.6 (a) 4 K bytes = 4 K ´ 8 = 2 ´ (2 K ´ 8) Therefore. two 2142 RAM chips are connected as shown in Fig.5 (a). The complete circuit is shown in Fig. of the 8-bit word. Prob. 11.4 (a) 4 chips of 2142 and one 1-out of-4 (i. IC2 for the upper four bits. (b) 2 chips of 2142. and A10 and A11 are applied to a 2-line-to-4-line decoder.e. 11. Prob. 11. (b) 2 K ´ 16 = (2 K ´ 8) ´ 2 This also requires two chips of 2716. the width of the address bus required is 12. For this purpose a 4-line-to-16-line decoder circuit is to be used in a way similar to that used in Fig. (c) 4 K ´ 16 = 2 ´ 2 ´ (2 K ´ 8) The number of 2716 chips required is four. Prob. One inverter will be required to select one pair of 2716s.5 (b). two chips of 2716 and one inverter are required. number these sixteen sets as RAM-0 to RAM-15.. The upper chip. 32 chips of 2142 will be required. Here.7 (a) For 4 K locations. One 1-out of-16 decoder will be required to select a specific chip pair. The most significant bit A11 of the address is used to select the chip and the other 11 bits A10-A0 are applied to both the chips. 16 sets of 1 K ´ 8 circuits as shown in Fig. A0 – A9 will be same for all the 16 sets. (c) 16 K bytes = 16 K ´ 8 = (16 ´ 1024) ´ (4 ´ 2) = 32 ´ (1024 ´ 4) Therefore. IC1 has been used for the lower four bits and the lower chip. for convenience. (c) For obtaining 16 K bytes of RAM. 2-line-to-4-line) decoder IC will be required. The most significant four bits of the addresses are to be used to select one out of the 16 sets.5 (a) Since the total number of locations is 4 K.5 (b) are required. Prob. therefore.(Contd.5 (a) which can be understood easily. (b) For obtaining 1024 ´ 8. the address A0 – A9 is applied to both the chips. Let us.) Memory C D E F Maximum rate 1 × 10 9 = 2222222/s 450 6 1 × 10 9 = 5 ´ 10 /s 200 1 × 10 9 = 16666666/s 60 1 × 10 9 = 1250000/s 800 11. This decoder will select one out of the four chips depending upon the values of A10 and A11. 11. The lower ten bits of the address (A0 – A9) are connected to the address bus of each RAM chip. 11. The address bit A11 is applied at the chip select ( CS 1 ) input of ROM-0 and its complement is applied at 136 .

0 I/O1 – I/O4 CS 1 CS2 +VCC A0 – A9 2142 RAM . Prob. 11.7(b) shows 2 K ´ 16 ROM. 11. The lower order eight bits of each of the 16-bit words are stored in IC1 and the higher order eight bits are stored in the corresponding location in IC2.8 (a) In the linear selection addressing. (c) For obtaining 4 K ´ 16 ROM.2 I/O1 – I/O4 CS 1 CS2 A11 WE OD WE WE OD OD 2142 RAM . Fig. 11.3 I/O1 – I/O4 CS 1 CS2 +VCC Fig. whereas A11 = 1 will select ROM-1. when A11 = 0 ROM-0 is selected. 11. Therefore. Figure Prob. a one-out-of-N decoder is used to select one of the N memory locations.7(b)) and connect them as shown in Fig. Prob. (b) Figure Prob.5(a) CS 2 input. For example. Prob. Prob.A0 – A9 WE OD 2142 RAM . 11. 137 D A0 – A9 A +VCC T A B U (4 A10 2-lineto-4linedecoder 1 OD – 0 B WE I T) . 11. 11. use two sets of 2 K ´ 16 memory (Fig.8(a) shows as 4-line-to-16-line decoder used to select one out of sixteen memory locations.1 I/O1 – I/O4 CS 1 CS2 2 3 A0 – A9 +VCC S 2142 RAM .7(a).7(a) illustrates the relevant portion of the circuit.

Prob. Prob. Prob. 11. 11.7(a) 2716 A0 – A10 IC1 CS CS CS 2716 IC2 A0 – A10 ü ï ï ï 16-bit output ï ý (D – D ) 0 15 ï ï ï ï þ Fig.7(b) 138 .5(b) (8 – B I T) D0 – D7 D A T A O0 – O7 O0 – O7 D8 – D15 B U S CS 2 2716 2716 A0 – A10 ROM-0 CS 1 O0 – O7 A11 A0 – A10 ROM-1 O0 – O7 Fig. 11.A0 – A9 2142 IC1 OD I/O1 – I/O4 WE CS 1 OD CS2 2142 IC2 A0 – A9 I/O1 – I/O4 ï ï ï ï ï ï8-bit output ý (D0 – D7) ï ï ï ï (D4 – D7) ï ï ï þ (D0 – D3) ü Fig.

11. Prob 11. a memory location is selected by applying an X address and a Y address. Prob. the X address is A1A0 which selects a row and the Y address is A3A2 which enables a column. Each memory element is placed at the intersection of a row and a column.8(a) (b) In the coincident selection addressing.8(b) 139 .8 (b).0 Memory location 0 Memory location 1 Memory location 2 ì 3 ï ï A2 Address ï ï inputs í ï A1 ï ï ï A0 î A 1 4-line-to 16-line decoder 2 14 15 Memory location 14 Memory location 15 Fig. Here. 11. Prob. 0 1 2 3 Column Row 0 D00 1 of 4 Decoder DL A0 D01 D02 D03 ì ï A1 ï ï ï ï ï ï Row drivers ï í Diode ï matrix ï Column ïA enable 2 ï ï ï ï A3 ï î 1 of 4 Decoder DH D10 D11 D12 D13 1 D20 D21 D 22 D23 2 4-bit address D30 D31 D32 D33 3 Column sense amplifiers Chip select (CS) Data output Fig. The decoder circuitry consists of 1-out-of-X and 1-out-of-Y decoders as shown in Fig.

11. Therefore.9(a).. (iii) Associate Operation with Lower Bit Masked: The operation is similar to the operation of (ii) above. if the input is at logic 0. the logic level of C will be complement of input logic level.12 (i) Association Operation: When A1A0 = 11. (v) Write Operation: When A1A0 = 00. the power is always drawn from the supply throughout the clock cycle. 11. T1 and T2 will conduct and C will get discharged to logic 0 level. 11. The output Y of the wired-OR gate will be 0 if both the data inputs match with the bits stored. which will disable the latches. The output will be OR operation performed on all the selected outputs. It is also possible to read more than one location at a time. the ratio C2/C3 must be very large. This happens when more than one address input is made 0. even if the bit stored on C1 is 1. Therefore. 11. C3 charges from C2 forming a capacitive loop. the operation of the circuit will be similar to the operation explained in (i) above except that the output of the AND gate on the I1 side will always be 0. outputs of the OR gates are 1 irrespective of the logic level at W (i. the complement of logic level on C will be transferred to output capacitor (between drain of T6 and ground).e. then during f2 = 1. T4 also conducts. The output of the EX-OR gate will be 0. and W = 1. In order to charge C3 without causing appreciable voltage drop. T2 is OFF). The data outputs D1 and D0 are both 0. therefore. (ii) Associate Operation with Higher Bit Masked: When A1A0 = 01. On the other hand. otherwise it is 1. In contrast to this. otherwise it will be 1. Depending upon which Y is selected by making it 0. When T3 conducts. the output Q0 of the latch appears at the corresponding D output. 11. and W = 1. Similarly. therefore.9 The operation of this circuit is similar to that of the circuit of Fig. the gates of the inverters are not held at VDD but are clocked so that T3 conducts only when f2 = 1 and not when f1 = 1. Here. The f2 needs to be 1 only long enough to allow C2 to charge from VDD through T3 and T4. if the data input bit is same as the bit stored (Q0). the latches are disabled. (iv) Read Operation: When A1A0 = 00. The same data also appears at the D outputs following the arguments of (iv) above. 11. C charges to logic 1 through T3. match condition will be checked only for I0 bit. The AND gate of D1 output is enabled. In general. and W = 0. there is considerable reduction in power dissipation in this circuit. The outputs of the NOR gates will be 0.11 During the interval when f1 = 1. C2 >> C3. T1 will be OFF and C will continue at logic 1 level. if the data input is 1.9a. during f3 and f4 phases. Now. W = X).10 When the transistor T4 conducts. Therefore. 140 . This logic level remains on C after f1 returns to logic 0. the output of the AND gate is 1 for mismatch and 0 for match. independently of data input (since f2 = 0. the latches are enabled for the location by making the Y input 0. in the circuit of Fig.

e. Thus.14 8 ´ 8 = 4 ´ (8 ´ 2) Therefore. it becomes a CAM of sixteen 2-bit words. 11. 11.14 can be connected as shown in Fig. 11. 11. Y0 – Y7 of each chip are connected to a common bus.15 16 ´ 8 = 2 ´ (8 ´ 8) Therefore. 11. data outputs. The first operation is to interrogate the MSB of all words for a 1 with all other bits masked. Prob. The outputs will be 0 for matched conditions and 1 for mismatch conditions. therefore. it requires two chips. 8-bit word CAM. for designing a 16 ´ 8 CAM. therefore. i.16 It is a 16-word. the number of chips required is four.14.13 Since 16 ´ 2 = 2 ´ (8 ´ 2). The data inputs. 11. the operation will be similar to the operation of part (a) above. the key is 141 . (b) When A1A0 = 10 and W = 0. Prob. 11. Since the number of words is 8. The resulting system has 16 address inputs (Y0 – Y15). Prob.13. I1 I0 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 D0 D1 A0 A1 I0 I1 8´2 CAM IC1 D1 D0 W W W A0 A1 I0 I1 D1 D0 8´2 CAM IC2 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Fig. The circuit of 8 ´ 8 CAM is shown in Fig. the corresponding higher bit (I1) is latched into the latch and it also appears at the D1 output. and mode control inputs of two 8 ´ 2 CAMs are connected as shown in Fig. The matching will be performed for higher bits and the lower bit (I0) will be stored in the locations for which I1 match. Prob. 11.15.(vi) Associate and Write at the Match Addresses: (a) When A1A0 = 01 and W = 0. the association operation is performed for the lower bit (ii) above.13 11. two 8 ´ 8 CAMs as shown in Fig.. When there is matching.

11. 11. Prob.A7 A6 I7 I6 A5 A4 I5 I4 A3 A2 I3 I2 A1 A0 I1 I0 A1 A0 I1 I0 8´2 CAM A1 A0 I1 I0 8´2 CAM A1 A0 I1 I0 8´2 CAM A1 A0 I1 I0 8´2 CAM Y0 – Y7 Y0 – Y7 Y0 – Y7 D0 D4 Y0 – Y7 W D1 D7 D0 D6 W D1 D5 W D1 D3 D0 D2 W D1 D1 D0 D0 W Fig. However.15 I0 1XXXXXXX. if several words indicate a match. then the maximum valued word search is complete. If only one word indicates a match. In case no match occurs when the MSB is interrogated. Prob. then the next key has to be 142 . then the CAM is to be interrogated again with key as 11XXXXXX.14 I7 8 ´ 8 CAM I0 Y0-Y7 Y0-Y7 D0 D1 D2 D3 D4 D5 D6 D7 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 W D7 D6 D5 D4 D3 D2 D1 D0 8 ´ 8 CAM Y8-Y15 Y0-Y7 I7 Fig.

11.17 11.18

11.19

11.20

01XXXXXX. This process is to continue till at the most all the bits of the words are interrogated. In any case no more than 8 interrogation cycles will be required to determine the maximum valued word. In the case of RAM, each word is to be compared sequentially. Therefore, the time required for the search will be dependent on the number of words stored which is sixteen in this case. The operation is similar to the operation of Prob. 11.16 with 1’s replaced by 0’s in the search process. A CAM is ideal for this. Because of the parallel search operation in CAM, just in one cycle, we can find out whether the word is already stored or not. If not, it can be stored in the next location available. In contrast to this, the search process is serial in a RAM which is time consuming and hence a RAM is not suitable for this purpose. The inputs and the outputs of all the CCDs are to be connected in parallel. The additional address bits are decoded and used to select one of the CCDs for read/write operation. The clock and write enable are also connected in parallel. For expanding word length, the address, chip select, write enable, and clock inputs of all the devices are connected in parallel. The number of data inputs and outputs are used independently. The number of inputs/outputs will be equal to the number of CCDs.

143

CHAPTER 12

12.1 The BCD-to-Excess-3 code converter’s truth table is given below.

BCD A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 Excess-3 E2 E1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0

(a) For the design using PROM, a PROM of size 10 ´ 4 is required, but since PROM of this size does not exist, therefore, a PROM of size 16 ´ 4 is to be used. Data is to be stored in the PROM at the addresses corresponding to the BCD code, the data is Excess-3 code. For example at the address 0000, the data stored is 0011 and at the address 1001 the data stored is 1100. (b) Logical expressions can be written for E3, E2, E1, and E0 outputs in terms of A,B,C, and D inputs. To reduce the hardware requirements, these expressions can be minimized using K-maps.

A B C D

E3 E2 E1 E0 Fig. Prob. 12.1 (b)

**The simplified expressions are: E3 = A + BC + BD E2 = B C D + B C + B D E1 = C D + CD E0 = D
**

144

The size of PLA required is No. of inputs =4 No. of outputs =4 No. of product terms =9 The circuit is given in Fig. Prob. 12.1(b). (c) The required size of PAL is No. of inputs =4 No. of outputs =4 Minimum number of =3 AND gates for each output The circuit is given in Fig. Prob. 12.1(c).

A E3 B E2 C E1 D E0

Fig. Prob. 12.1 (c)

12.2 Follow similar procedure as given in Prob. 12.1. 12.3 Prepare truth table and follow similar procedure as given in Prob. 12.1. 12.4 The inputs of two 82S100 devices are to be connected in parallel. This will result in 8 + 8 = 16 outputs. 12.5 The inputs I0 to IM-1 are common for all the PLAs. Depending on the values of IM to IM+Q-1, one of the output lines of the decoder will go LOW activating the corresponding PLA and disabling all the other PLAs. Hence, the number of inputs increases. 12.6 Architecture of a PLD refers to the attributes of the device significant to the logic of a design to be implemented. It includes. · Configuration of pins. · The size and the arrangement of the programmable array(s). · Configuration of the input and output interface logic.

145

8 Input I1 I1 I2 I2 I3 I3 I4 I4 Column 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 Input/output IO1 IO 1 IO8 IO 8 O2 Column 2 3 30 31 6 7 10 11 14 15 18 19 22 23 26 27 O2 O3 O3 O4 O4 O5 O5 O6 O6 O7 O7 I5 I5 I6 I6 I7 I7 I8 I8 146 .7 Input I1 I1 I2 I2 I3 I3 I4 I4 I5 I5 I6 I6 I7 I7 I8 I8 I9 I9 I10 I 10 Column 2 3 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31 Input/output IO2 IO 2 IO3 IO 3 IO4 IO 4 IO5 IO 5 IO6 IO 6 IO7 IO 7 Column 6 7 10 11 14 15 18 19 22 23 26 27 12.12.

Comb. f = 1 147 .12. Reg. MUX–3 and MUX–4. Reg. E . whereas for x2 = 1. G and H intact to the controlling AND gate and open all other connections. D. Comb. 12. f = 0 x2 = 1. Comb. For x2 = 0. Comb. 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 8 8 8 8 8 7 7 7 7 7 7 7 7 Comb.11 Here the output of an AND gate controls the output. f will be obtained from the upper multiplexer. for x1 =1 when and when x2 = 1. MUX–1. the cell second from the top will get selected and f = 0. Comb. input feedback input feedback input feedback input feedback input feedback input feedback input 12. Prob. Reg. Similarly. topmost cell will be selected and f will be 1. MUX–2. Reg. (a) Open all the inputs to the controlling AND gate. Reg.10. F . (b) Keep all the inputs intact (connected) to the controlling AND gate. Each one may be programmed to be in 0 or 1. 12.9 It has four multiplexers. which means its output will be either same as input 0 or input 1. Table below gives all the possible conditions. Reg. C.12 When x1 = 0. comb. of product Terms 8 8 8 Output Enable pin-11 pin-11 Term Controlled Term Controlled pin-11 pin-11 Term Controlled Term Controlled pin-11 pin-11 Term Controlled Term Controlled pin-11 pin-11 Term Controlled Term Controlled Output Output pin/FF output feedback input feedback 0 0 0 0 0 0 0 0 1 0 1 0 Reg. Comb. MUX – 1 MUX – 2 MUX – 3 MUX – 4 No. Reg. B. 12. (c) Keep the connections corresponding to the inputs A.10 These are given in Fig.

Prob. 12.Registered output B = 1 Combinational output B = 0 AR D Q SP A=0 AR D Q SP A=1 AR D Q SP AR D Q A=0 SP AR D Q AR D Q SP A=1 SP Q A=0 AR D Q SP AR D Q SP Q Fig.10 148 REGISTER FEEDBACK CD = 00 COMBINATIONAL FEEDBACK CD = 10 BI-DIRECTIONAL I/O CD = 11 A=1 .

when x2 = 0. the complete circuit can be analyzed. The bits to be stored will be 0 1 1 0 1 0 0 1 149 . When x3 = 0. the output will be obtained from the top-most multiplexer and when x2 = 1. Now. and when x3 = 1 it will be from be next cell. the truth table will be as given below.13 The truth table of the given function f is x1 0 0 0 0 1 1 1 1 x2 0 0 1 1 0 0 1 1 x3 0 1 0 1 0 1 0 1 f 0 1 1 0 1 0 0 1 when x1 = 0. x1 0 0 1 1 x2 0 1 0 1 f 1 0 0 1 12. when x1 = 1. the output will be from the top-most cell. f will be obtained from output of bottom multiplexers’ structure.Therefore. it will be obtained from the next multiplexer. Similarly. f will be obtained from output of top multiplexers’ structure.

(b) Let the first 2 K bytes be in EPROM and next 4 K bytes be in the RAMs. Therefore.3 (a) 2142 is a 1024 ´ 4 bits RAM Therefore.3(a) 150 . P is the address bus width. assuming single byte op code = 256.1 The memory address space is given by M = 2P where. 13.2 The number of distinct combinations of 8-bit words = 28 = 256 Therefore. 4 K bytes = 4 K ´ 8 bits = 4 ´ 2 ´ (1 K ´ 8) bits = 8 chips 2716 is a 2 K ´ 8 bits EPRPM. 13. the total number of instruction codes. The relevant connections are shown below. only one 2716 chip is required. The memory address space for the mPs are given below. Prob.CHAPTER 13 13. The total number of instruction codes in 8085A mP is 246. A8 – A15 8085 A WR RD AD0 – AD7 ALE A0 – A7 8212 CLR DS2 MD DS 1 +VCC Fig. Microprocessor 8080A 6800 8086 9900 Z8000 Memory address space 64 K bytes 64 K bytes 1 M bytes 64 K bytes 8 M bytes 13.

Other connections are indicated below: A0 – A10 from mP to A0 – A10 of 2716 A0 – A9 from mP to A0 – A9 of each of 2142 CS2 of each 2142 to Vcc

WR from mP to WE of each 2142

**RD from mP to OD of each 2142
**

A10 A11 A12 (from mP) A13 A14 A15 (from mP) A0 A1 A2 8205

E1

0 1 2 3 4 5 6 7

To CS of 2716 To CS 1 of RAM set 1 To CS 1 of RAM set 2 To CS 1 of RAM set 3 To CS 1 of RAM set 4

E2 E3

Fig. Prob. 13.3(b)

**(c) The address of various chips are given below.
**

Memory chips EPROM RAM pair RAM pair RAM pair RAM pair Starting address in hex. 1 2 3 4 0000 0800 0C00 1000 1400 Last address in hex. 07FF 0BFF 0FFF 13FF 17FF

13.4

(i) MVI A, 00H ; Load accumulator with zero (ii) SUB A ; Subtract A from A (iii) ANI 00H ; AND A with zero (iv) XRA A ; A EX-OR A Note that the information beyond semicolon (;) are comments. 13.5 Let D-E and H-L pairs be pointers to source and destination memory locations respectively. The program is given below: LXI D, 0F00 H ; Initialize source pointer LXI H, 1F00 H ; Initialize destination pointer LXI B, 100H ; Initialize counter LOOP: LDAX D ; Load A with contents of source memory CMA ; Complement A MOV M, A ; Store in destination memory INX D ; Increment pointers INX H

151

DCX B MOV A, C ORA B JNZ LOOP

; Decrement counter ; Check counter for zero

NEXT: 13.6 The program is given below: LXI H, 0A02H ; Store destination address in H-L pair LDA 0A00H ; Load A with first number MOV B, A ; Transfer to B LDA 0A01H ; Load A with second number CMP B ; Compare A and B JZ FINIS ; Go to FINIS if the two numbers are equal JC GREAT ; If CY = 1, (A) < (B) MOV M, A ; Otherwise (A) > (B) JMP FINIS GREAT: MOV M, B FINIS : 13.7 The following instructions will clear the memory location. LXI H, 01A0H MVI M, 00H 13.8 LXI H, A001H ; Initialize pointer MOV C, M ; Get the number of bytes in C INX H ; Increase pointer by 1 START : MOV A, M ; Get a byte of data in A REP : DCR C JZ STOP ; Stop at end of data INX H CMP M ; Compare JC REP ; If (A) < (M), try next number JMP START STOP: STA FF00H ; Store the smallest element END 13.9 ANI 0FH 13.10 LOOP: DCR 0 JZ FINIS IN DATA MOV M, A INX H JMP LOOP FINIS: MOV B, A

152

SOLUTION The operation performed by each instruction is given below: START: LXI H, BUFR ; Initialize H-L pair with address BUFR MOV C, 0BH ; Initialize counter with decimal 11 LOOP: DCR C ; Decrease counter by one JZ FINIS ; Go to FINIS if counter = 0 IN DATA ; Input a byte from DATA port MOV M, A ; Move the byte to memory ; location pointed to by H-L pair INX H ; Advance the pointer by one JMP LOOP ; Go to loop FINIS: MOV B, A ; Move the contents of A to B The operation performed by this program is to input ten bytes from input port DATA and store them in memory locations starting from BUFR. 13.11 N=3+3+1+1+1+1+1+1 = 12 bytes 13.12 (A) 0000 1000 (B) 1001 0011 ADD B 1001 1011 The result is not a valid BCD number. ADD B instruction must be followed by DAA instruction. The effect of this is given below: 1001 1011 0000 0110 Add 6 because the least-significant four bits do not represent a valid BCD digit 1010 0001 0110 0000 Add 60 because the most-significant four bits do not represent a valid BCD digit 10000 0001 = (101)10 13.13 Assume a set of ten keys for entering BCD number and a 7-segment display for displaying this number. It is also assumed that BCD-to-7-segment codes are stored in memory from the starting address 00XXH. The block diagrams for the input and output devices are shown in Fig. Prob. 13.13(a) and (b) respectively. Assume 01H and 02H as the port addresses of the input device and output device respectively. The addresses are decoded and proper signals are generated for Enable and Device Select terminals for reading and writing. The program can be written as MVI B, XXH LXI H, 0000H IN 01H ADD B MOV L, A MOV A, M OUT 02H

153

VCC D (MSB) Decimal-toBCD Encoder (Inputs & outputs active-low) C B Inverting Tristate Buffer D3 D2 D1 Data bus of mP b c d A D0 Enable (a) Current limiting resistors VCC Common anode a b c f d e e f g a g Data bus D-type Latch Device Select (b) Fig.14 The last six instructions will be POP PSW POP H POP D POP B EI RET 154 .13 13. Prob. 13.

20 20-bit current address of the stack will be 24000 + A000 2E000 H 155 . AL BX: BH.19 CS = 2000H IP = 1A00H 20-bit address of the next instruction byte will be fetched from 20000 + 1A00 21A00 H 13.16 Refer to Table 13.18 Four zeros at the least-significant four bit positions are appended to the 16bit segment register. DL 13. 13.3 mP 8086 80186 80286 80386SL 80386 DX 80486 DX Pentium Address bus width 20 20 24 25 32 32 32 13.17 Eight 8-bit or four 16-bit AX: AH. A JMP STOP QUE : MVI M.Here it is assumed that the interrupts are kept disabled during the execution of the sub-routine. CL DX: DH.15 The ASCII code for decimal 0 is 0110000 and for? is 0111111. 13. 00111111 B STOP: END 13. making it 20-bit address. 00F1H LDA 00F0H CPI 0AH JNC QUE ADI 00110000 B MOV M. Actual physical 20-bit address is this 20-bit data plus the contents of the pointer register. BL CX: CH. The program is given below: LXI H.

Y : OUT BIT). END MULTI_4. 1164 ALL. character ‘ ’ is not permitted.3. Z : OUT BIT). No.3 A 4:1 multiplexer is shown in Fig. 14. -. IN STD-LOGIC. There is one output Y.2 (a) Yes. I1. It contains all the allowed characters. (b) For 3-input NAND gate ARCHITECTURE df_nand 3 OF NAND 3 IS BEGIN Y Ü NOT (A AND B AND C) AFTER 10 ns.CHAPTER 14 14. Prob. I1. I0 I1 I2 I3 AB Fig. 14. USE IEEE STD-LOGIC. No. No. Y : IN BIT. B. (b) ENTITY NAND 3 IS PORT (A. A. Upper and lower case characters can be mixed. 14. starting character can not be a numeral. USE IEEE. END df-nand 2. Prob. ALL. Two consecutive underscores are not allowed.3 Y The entity declaration is LIBARY IEEE. and I3 and two select inputs A and B. Y: OUT STD-LOGIC).Name of entity chosen is F_A 156 .1 (a) (b) (c) (d) (e) (f) 14. END NAND 2. B . I2. I2. Hyphen (–) is not allowed.4 (a) For 2-input NAND gate ARCHITECTURE df_nand 2 OF NAND 2 IS BEGIN Z Ü NOT (X AND Y) AFTER 10 ns. I3. Yes. 14. END NAND 3. No. END df_nand 3. STD_LOGIC_1164. C : IN BIT. ENTITY MULTI-4 IS PORT (IO.5 LIBRARY IEEE. It has four data inputs I0. ENTITY NAND 2 IS PORT (X. 14.

COMPONENT INV PORT (P : IN STD_LOGIC. ENTITY F-A IS PORT (A. X7 : IN STD-LOGIC. N5 : NAND4 PORT MAP (S1. N8 : NAND2 PORT MAP (A. B. CIN. BB). END FA_STR. S2. CIN. S5). ALL. S3. B. COMPONENT NAND2 PORT (X8. R : OUT STD_LOGIC). X2.6 LIBARY IEEE. BB. S2). I3 : INV PORT MAP (CIN. 157 . N6 : NAND2 PORT MAP (A. N3 : NAND3 PORT MAP (A. END COMPONENT. S1. SIGNAL AB. BB. END FULL_ADDER. B. S7 : STD_LOGIC. S COUT: OUT STD_LOGIC). B. ARCHITECTURE FULL_ADDER OF F_A IS. STD_LOGIC-1164. N2 : NAND3 PORT MAP (AB. S7). END F_A. S3). X6.ENTITY F-A IS PORT (A. COUT: OUT STD_LOGIC) END F-A. N9 : NAND3 PORT MAP (S5. S2. CIN. Z: OUT STD_LOGIC). N4 : NAND3 PORT MAP (A. S6). X3 : IN STD-LOGIC. S5. S1). I2 : INV PORT MAP (B. BEGIN S Ü ((NOT A) AND B AND (NOT CIN)) OR ((NOT A) AND (NOT B) AND CIN) OR (A AND (NOT B) AND (NOT CIN)) OR (A AND B AND CIN) AFTER 15 ns. CINB. CIN: IN STD_LOGIC. COMPONENT NAND 4 PORT (X4. S4. B. CIN. 14. X9 : IN STD_LOGIC. X5. BB. S4. CINB. N1 : NAND3 PORT MAP (AB. S4). BEGIN I1 : INV PORT MAP (A. END COMPONENT. N7 : NAND2 PORT MAP (B. S6. CINB). END COMPONENT. S3. S7 COUT). Y: OUT STD_LOGIC). ARCHITECTURE FA_STR OF F_4 IS COMPONENT NAND 3 PORT (X1. CINB. USE IEEE. C OUT Ü (A AND B) OR (B AND CIN) OR (A AND CIN) AFTER 10 ns. AB). S. S). Q : OUT STD_LOGIC). END COMPONENT. S6. CIN: IN STD_LOGIC.

Prob.5 158 .A I1 AB B I2 CIN I3 N 1 BB CINB N2 S2 S1 N5 N3 S3 S N4 A B B CIN A CIN N6 S5 S4 N7 S6 N9 COUT N8 S7 Fig. 14.

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