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# 太原理工大学 夏路易

## 3.4.2 使用 VHDL 语言设计例

Max+plus2 软件支持 VHDL 语言描述被设计电路的逻辑功能，如下举例说明如何使用该语

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## 例二： 设计一个 十进制加 法计数器

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count10 is
port(clk,reset,en: in std_logic;
qa,qb,qc,qd: out std_logic);
end count10;
architecture behave of count10 is
signal count_4: std_logic_vector(3 downto 0);
begin
qa<=count_4(0);
qb<=count_4(1);
qc<=count_4(2);
qd<=count_4(3);
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process(clk,reset)
begin
if (reset='0') then
count_4<="0000";
elsif(clk'event and clk='1') then
if(en='1') then
if(count_4="1001") then
count_4<="0000";
else
count_4<=count_4+'1';
end if;
end if;
end if;
end process;
end behave;

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## 第八步：选择 Max+plus2/Simulator 菜单，仿真结果如图 3.4.6 所示。

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cou12 is
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port(clk,reset,cin : in std_logic;
co : out std_logic;
bcd1p : out std_logic_vector(3 downto 0);
bcd10p : out std_logic_vector(2 downto 0));
end cou12;

## architecture behave of cou12 is

signal bcd1n: std_logic_vector(3 downto 0);
signal bcd10n: std_logic_vector(2 downto 0);
begin
bcd1p<=bcd1n;
bcd10p<=bcd10n;
kk1: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcd1n<="0000";
elsif (cin='1') then
if(bcd1n="1001" ) then
bcd1n<="0000";
else
bcd1n<=bcd1n+'1';
end if;
end if;
end if;
end process kk1;

kk2: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcd10n<="000";
elsif(cin='1') and (bcd1n="1001") then
if(bcd10n="001") then --归零条件
bcd10n<="000";
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else
bcd10n<=bcd10n+'1';
end if;
end if;
end if;
end process kk2;

kk3: process(bcd10n,bcd1n,cin)
begin
if(cin='1' and bcd1n="1001" and bcd10n="001") then
co<='1';
else
co<='0';
end if;
end process kk3;
end behave;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY x6012 IS
PORT (clk, reset,ena : IN std_LOGIC;
cpp : out std_logic;
a12g : out std_logic_vector(3 downto 0);
a12s : out std_logic_vector(2 downto 0);
b60g : out std_logic_vector(3 downto 0);
b60s : out std_logic_vector(2 downto 0));
END x6012;

## ARCHITECTURE x12 OF x6012 IS

component cou12
port(clk,reset,cin : in std_logic;
co : out std_logic;
bcd1p : out std_logic_vector(3 downto 0);
bcd10p : out std_logic_vector(2 downto 0));
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end component;

component cou60
port(clk,reset,cin : in std_logic;
co : out std_logic;
bcd1p : out std_logic_vector(3 downto 0);
bcd10p : out std_logic_vector(2 downto 0));
end component;

## signal c12,c601 : std_logic;

signal b60gp : std_logic_vector(3 downto 0);
signal b60sp : std_logic_vector(2 downto 0);

begin
u1:cou60 port map(clk,reset,ena,c601,b60gp,b60sp);
u0:cou12 port map(c601,reset,ena,c12,a12g,a12s);
b60s<=b60sp;
b60g<=b60gp;
cpp<=c601;
end x12;

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LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cou4 is
port(
clk,reset,cin : in std_logic;
-- co : out std_logic;
bcdap : out std_logic_vector(3 downto 0);
bcdbp : out std_logic_vector(3 downto 0);
bcdcp : out std_logic_vector(3 downto 0);
bcddp : out std_logic_vector(3 downto 0)

);
end cou4;

## architecture behave of cou4 is

signal bcdan: std_logic_vector(3 downto 0);
signal bcdbn: std_logic_vector(3 downto 0);
signal bcdcn: std_logic_vector(3 downto 0);
signal bcddn: std_logic_vector(3 downto 0);

begin

bcdap<=bcdan;
bcdbp<=bcdbn;
bcdcp<=bcdcn;
bcddp<=bcddn;
kk1: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcdan<="0000";
elsif (cin='1') then
if(bcdan="1001" ) then
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bcdan<="0000";
else
bcdan<=bcdan+'1';
end if;
end if;
end if;
end process kk1;

kk2: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcdbn<="0000";
elsif(cin='1') and (bcdan="1001") then
if(bcdbn="1001") then
bcdbn<="0000";
else
bcdbn<=bcdbn+'1';
end if;
end if;
end if;
end process kk2;

kk3: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcdcn<="0000";
elsif(cin='1') and (bcdbn="1001") and (bcdan="1001") then
if(bcdcn="1001") then
bcdcn<="0000";
else
bcdcn<=bcdcn+'1';
end if;
end if;
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end if;
end process kk3;

kk4: process(clk)
begin
if(clk'event and clk='1') then
if (reset='0') then
bcddn<="0000";
elsif(cin='1') and (bcdcn="1001") and (bcdbn="1001") and (bcdan="1001") then
if(bcddn="1001") then
bcddn<="0000";
else
bcddn<=bcddn+'1';
end if;
end if;
end if;
end process kk4;
end behave;

## 该计数器使用 MAX7000 系列器件的仿真结果见图 3.4.9。

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7 段译码的 VHDL 设计文件：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity seg7 is
port(ii :in std_logic_vector(3 downto 0);
y :out std_logic_vector(6 downto 0));
end seg7;

## architecture behave OF seg7 is

signal indata: std_logic_vector(3 downto 0);
begin
indata<=ii;
process(indata)
begin

case indata is
when "0000"=>y<="1111110";
when "0001"=>y<="0110000";
when "0010"=>y<="1101101";
when "0011"=>y<="1111001";
when "0100"=>y<="0110011";
when "0101"=>y<="1011011";
when "0110"=>y<="1011111";
when "0111"=>y<="1110000";
when "1000"=>y<="1111111";
when "1001"=>y<="1111011";
when "1010"=>y<="1110111";
when "1011"=>y<="0011111";
when "1100"=>y<="1001110";
when "1101"=>y<="0111101";
when "1110"=>y<="1001111";
when "1111"=>y<="1000111";
when others=>y<="XXXXXXX";
end case;
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end process;
end behave;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY cou47seg IS
PORT (clk, reset,ena : IN std_LOGIC;
seg1 : out std_logic_vector(6 downto 0);
seg2 : out std_logic_vector(6 downto 0);
seg3 : out std_logic_vector(6 downto 0);
seg4 : out std_logic_vector(6 downto 0));
END cou47seg;

## ARCHITECTURE x47 OF cou47seg IS

component seg7
port(ii :in std_logic_vector(3 downto 0);
y :out std_logic_vector(6 downto 0));
end component;

component cou4
port(
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clk,reset,cin : in std_logic;
bcdap : out std_logic_vector(3 downto 0);
bcdbp : out std_logic_vector(3 downto 0);
bcdcp : out std_logic_vector(3 downto 0);
bcddp : out std_logic_vector(3 downto 0)
);
end component;
signal a,b,c,d : std_logic_vector(3 downto 0);
begin
u0:cou4 port map(clk,reset,ena,a,b,c,d);
u1:seg7 port map(a,seg1);
u2:seg7 port map(b,seg2);
u3:seg7 port map(c,seg3);
u4:seg7 port map(d,seg4);
end x47;

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