UNIVERSITY OF WATERLOO Department of Electrical and Computer Engineering

ECE 324 VHDL Tutorial Notes

Wayne M. Loucks, PEng Robert B. Gorbet, PEng Carol C.W. Hulls, PEng Bill Bishop

wmloucks@pads.uwaterloo.ca rbgorbet@uwaterloo.ca chulls@kingcong.uwaterloo.ca wdbishop@pads.uwaterloo.ca

June 2002

Copyright (c) 2002 by the University of Waterloo. All Rights Reserved.

UNIVERSITY OF WATERLOO Department of Electrical and Computer Engineering

Section I: VHDL Tutorial

June 2002

VHDL Tutorial

Tutorial Outline
• Introduction to VHDL • VHDL Designs • Signals • Assignment Statements • Process Statements • Examples • VHDL and Quartus II

Introduction to VHDL

I-1

VHDL Tutorial

VHDL
• V H D L VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

• Language to describe the structure and/or behaviour of digital hardware designs • VHDL designs can be simulated and/or synthesized • Two versions of VHDL have been standardized by the IEEE – VHDL87 ⇒ IEEE-1076-1987 – VHDL93 ⇒ IEEE-1076-1993

Introduction to VHDL

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VHDL Tutorial

VHDL Documentation
• Books – Michael John Sebastian Smith, Application Specific Integrated Circuits, Addison-Wesley, Reading Mass., 1998. – Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill, New York, NY, 2000. – Douglas Perry, VHDL, 3rd Edition, McGraw Hill, New York, NY, 1998. – Peter J. Ashenden, The Designer’s Guide to VHDL, Morgan Kaufmann Publishers, Inc., San Francisco, CA, 1996. – Sudhakar Yalamanachili, VHDL Starter’s Guide, Prentice-Hall, Upper Saddle River, NJ, 1998. – David Pellerin and Douglas Taylor, VHDL Made Easy, Prentice-Hall, Upper Saddle River, NJ, 1997. – K.C. Chang, Digital Design and Modelling with VHDL and Synthesis IEEE Computer Society, Los Alamitos, CA, 1997. • Websites ⇒ A list of web resources can be found on the course website

Introduction to VHDL

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VHDL Tutorial

Entities, Architectures, and Configurations
• VHDL is a strongly-typed language for describing a digital hardware design. The structure of a VHDL design resembles the structure of a modern, object-oriented software design in the sense that every VHDL design describes both an external interface and an internal implementation. A VHDL design consists of the following specifications: Entity : A specification of the external interface to the design. The specification of the external interface to the design is unique. Architecture : A specification of the internal implementation of the design. There can be several specifications of the internal implementation of the design. Configuration : A specification of the mapping between an architecture and a particular instance of an entity. There must be a configuration for each instance of an entity. The configuration defaults to the last compiled architecture if one has not been explicitly specified.

VHDL Designs

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VHDL Tutorial

Architecture and Entity Introduction

Some description of a module's operation

Conceptual view of problem

E1: Module 1 (Entity for Module 1) A B separate the implementation from its interface in the system Define the ports of unit to be designed (its interface, specified as an entity)

C

A1: Module 1 Architecture 2 Provide another design for Module 1

A3: Module 1 Architecture 3 Provide another design for Module 1

ASIC DESIGN

Speed DESIGN

A2: Module 1 Architecture 2 Provide another design for Module 1

A4: Module 1 Architecture 4 Provide another design for Module 1

Area DESIGN

Fault Tolerant DESIGN

entityintro 1.

VHDL Designs

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VHDL Tutorial

Architecture and Entity Hierarchy
E3: Module 3 (entity for Module 3)

X Y Z D

A1: Module 3 Architecture 1 Interconnect various modules X Y Z M1 M2 M1 D Designer of A1 Need not know internal detail of E2 or E3.

E1: Module 1 (Entity for Module 1) A B separate the implementation from its interface in the system

E2: Module 2 (Entity for Module 2) A separate the implementation from its interface in the system

C

C

B

entityintro 2.

VHDL Designs

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VHDL Tutorial

Small Example
andnand.vhd

-- A

VHDL file to implement a And-Nand

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY andNand IS PORT( a, b : IN STD_LOGIC; q, qBar : OUT STD_LOGIC ); END andNand; ARCHITECTURE gateVersion OF andNand IS SIGNAL a_and_b : STD_LOGIC; BEGIN a_and_b <= a AND b; q <= a_and_b; qBar <= NOT a_and_b; END gateVersion;

NOTE

andnand.

VHDL Designs

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VHDL Tutorial

Language Elements
Comments : -- All comment lines start with two hyphens. Libraries and Packages : There are many libraries and packages available for VHDL. An important VHDL library is the IEEE library. This library provides the std logic 1164 package. This package provides a set of user-defined datatypes and conversion functions that should be used in VHDL designs. It can be instantiated as follows: LIBRARY ieee; USE ieee.std_logic_1164.ALL; Datatypes : VHDL supports a set of built-in datatypes as well as user-defined datatypes. Only a few will be introduced in this tutorial! • Built-in datatypes will not be used this term. They work well for simulation but not so well for synthesis. – BIT: Boolean value of 0 or 1. – BIT VECTOR: An array of bits. – INTEGER: An integer value (within a range).

VHDL Designs

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VHDL Tutorial

STD LOGIC 1164 Defined Datatypes
• The datatypes specified in STD LOGIC 1164 will be used exclusively this term. STD ULOGIC Values Uninitialized – Don’t care Forcing 1 Weak Unknown ’U’ ’-’ ’1’ ’W’ Forcing Unknown High Impedance Forcing 0 Weak 0 Weak 1 ’X’ ’Z’ ’0’ ’L’ ’H’

– STD ULOGIC VECTOR: An array of STD ULOGIC. – STD LOGIC: A resolved version of STD ULOGIC. If two or more distinct STD LOGIC are driven onto a bus in a design at one instant in time, the bus will have a defined value (usually X). – STD LOGIC VECTOR: An array of STD LOGIC. – NOTE: IEEE recommends the use of STD LOGIC and STD LOGIC VECTOR.

VHDL Designs

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VHDL Tutorial

Entity Declaration
The entity declaration specifies the following: • Name of the entity • Set of port declarations defining the inputs and outputs to the digital hardware design. – Port name ∗ Consists of letters, digits, and/or underscores ∗ Must begin with a letter ∗ Case insensitive – Port direction IN OUT INOUT BUFFER LINKAGE Input port Output port Bidirectional port Buffered output port Deprecated in IEEE 1076-2000

– Port signal type ∗ STD LOGIC ∗ STD LOGIC VECTOR(max DOWNTO min)

VHDL Designs

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VHDL Tutorial

Signals
In VHDL, signals are used to convey information between (and within) entities. Signals represent connection points in a VHDL design. Sample Signal Specifications: SIGNAL x1 SIGNAL c SIGNAL byte SIGNAL din0 SIGNAL dinA : BIT; : BIT_VECTOR(1 TO 4); : BIT_VECTOR(10 DOWNTO 0); : STD_LOGIC; : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL ece324 : STD_LOGIC; Signals are associated with a value and a set of attributes. Attributes allow VHDL designers to check for signal transitions, model delays, and create ”generic” descriptions of entities. Attributes are often used during simulation. Attribute Syntax ece324’EVENT Attribute Note This attribute is true if an event just happened on the signal ece324. This attribute is fully supported for simulation and partially supported for synthesis. Creates a signal the same as ece324 but delayed by a time T. This attribute is only supported for simulation

ece324’DELAYED(T)

VHDL Designs

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VHDL Tutorial

Signal Operators
Logical Operators : • AND • OR • XOR • XNOR • NOT • NAND • NOR Relational Operators : • Equal = • Not Equal /= • Less Than < • Greater Than > Accessing Vector Elements : some_signal(0) <= other_signal(1);

VHDL Designs

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VHDL Tutorial

Assignment Statements
SIGNAL x, y, z SIGNAL a, b, c SIGNAL sel : STD_LOGIC; : STD_LOGIC_VECTOR(7 DOWNTO 0); : STD_LOGIC_VECTOR(2 DOWNTO 0);

-- Concurrent Signal Assignment Statements -- NOTE: Both x and a are produced concurrently x <= y AND z; a <= b OR c; -- Alternatively, signals may be assigned constants x <= ’0’; y <= ’1’; z <= ’Z’; a <= "00111010"; -- Assigns 0x3A to a b <= X"3A"; -- Assigns 0x3A to b c <= X"3" & X"A"; -- Assigns 0x3A to c

VHDL Designs

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VHDL Tutorial

Assignment Statements
SIGNAL x, y, z SIGNAL a, b, c SIGNAL sel : STD_LOGIC; : STD_LOGIC_VECTOR( 7 downto 0); : STD_LOGIC_VECTOR( 2 downto 0);

-- Conditional Assignment Statement -- NOTE: This implements a tree structure of logic gates! x <= ’0’ WHEN sel = "000" ELSE y WHEN sel = "011" ELSE z WHEN x = ’1’ ELSE ’1’; -- Selected Signal Assignment Statement -- NOTE: The selection values must be constants. WITH sel SELECT x <= ’0’ WHEN "000", y WHEN "011", z WHEN "100", ’1’ WHEN OTHERS; -- Selected signal assignments also work with vectors. WITH x SELECT a <= "01010101" WHEN ’1’, b WHEN OTHERS; -- NOTE: Conditional assignment statements are evaluated -in (priority) order while selected signal assignment -statements are evaluated in parallel.

VHDL Designs

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VHDL Tutorial

Process Statements
This construct is not required for the labs this term. However, a process is a fundamental concept of VHDL. The process statement allows a VHDL designer to describe the behaviour of a portion of an architecture. It is easy to fall into the trap of believing that statements within a process are sequential. This is not (necessarily) the case! The following is a quote from the Brown and Vranesic text... The tendency for the novice is to write code that resembles a computer program, containing many variables and loops. It is difficult to determine what logic circuit the CAD tools will produce when synthesizing such code. ... A good general guideline is to assume that if the designer cannot readily determine what logic circuit is described by the VHDL code, then the CAD tools are not likely to synthesize the circuit that the designer is trying to describe.

VHDL Designs

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VHDL Tutorial

Process Specific Statements
Variables : Variables can be declared within a process. Variables can be used like signals. However, variables and signals have a subtle difference with respect to the assignment of a value. VARIABLE variable_name IF Statements : IF condition1 THEN statements1; ELSIF condition2 THEN statements2; ELSE statements3; END IF; : variable_type;

VHDL Designs

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VHDL Tutorial

Process Specific Statements (cont.)
Case Statements : CASE variable_name IS WHEN value1 => statement1; WHEN value2 => statement2; WHEN OTHERS => statement4; END CASE; Loop Statements : Assert Statements : Wait Statements : Wait statements halt the execution of a process until a desired event or delay has happened. Wait statements can be used to build sequential designs.

VHDL Designs

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VHDL Tutorial

Process Statement in a Combinational Problem
SIGNAL a, b, c : STD_LOGIC; SIGNAL Sel, x, y, z : STD_LOGIC; SIGNAL DV : STD_LOGIC_VECTOR(17 DOWNTO 0); -- Assume that a, b, c and Sel are set on elsewhere PROCESS (a, b, c) -- a, b, and c are in the sensitivity list. -- In this case (combinational) they are -- inputs. BEGIN -- Signal assignment statements can go anywhere -- inside a process. x <= a; -- If statements IF a = ’0’ THEN x <= c AND b; y <= c OR b; ELSIF b = ’0’ THEN z <= c OR a; ELSE w <= ’0’; END IF; -- Note x, y, and z are -- not always assigned -- in this example -- Continued on next slide

VHDL Designs

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VHDL Tutorial

Process Statement in a Combinational Problem (cont.)
-- Continued from previous example -- Case statement CASE Sel IS WHEN ’0’ => z <= a AND b; WHEN OTHERS z <= a OR b; -- For Loops FOR i IN 1 to 4 LOOP DV(i) <= a XOR b; END LOOP; -- While Loops WHILE boolean_expression LOOP statement; -- More statements could be added here. END LOOP; END PROCESS;

VHDL Designs

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VHDL Tutorial

Process Statement in Sequential Circuits
-----Assume we have defined ports and signals such that: d is the flip-flop input pin reset is the flip-flop reset pin clock is the flip-flop clock pin q is the flip-flop output pin

ff1: PROCESS ( clock, reset ) BEGIN IF (reset = ’1’) THEN q <= ’0’; ELSIF (clock = ’1’) AND (clock’EVENT) THEN q <= d; END IF; END PROCESS ff1;

VHDL Designs

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VHDL Tutorial

Example
Consider the following problem using vector outputs
Logical Problem (ECE 223, ME 262)
Entity

DataIn(vector)

Segments(6)

Segments

Segments(1)

DPin

Segments(0)

Segments(2)

Segments(3) DP Segments(7)
sevenseg

VHDL Designs

Segments(4) Segments(5)

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VHDL Tutorial

Vector Seven Segment Entity
Assumption: • The mapping from Segments(1) to pins on the FPGA must be done by the user. -- Seven Segment Display Example -Individual Assignments -- Decimal Point is ignored for sake of brevity LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY seven_seg IS PORT ( dataIn : IN STD_LOGIC_VECTOR(3 DOWNTO 0); decimalIn: IN STD_LOGIC; segments : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END seven_seg; ARCHITECTURE theLongWay OF seven_seg IS BEGIN -- seven segment display is active low -- segments defined same as with showhex -6 -1 5 -0

VHDL Designs

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VHDL Tutorial

-2 4 -3 -- 7 is decimal point, always off WITH dataIn SELECT segments(0) <= ’1’ ’1’ ’1’ ’0’ WITH dataIn SELECT segments(1) <= ’1’ ’1’ ’1’ ’1’ ’1’ ’0’ WITH dataIn SELECT segments(2) <= ’1’ ’1’ ’1’ ’1’ ’1’ ’1’ ’0’ WITH dataIn SELECT segments(3) <= ’1’ ’1’ ’1’ ’0’ WITH dataIn SELECT segments(4) <= ’1’ ’0’ WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN "0000", "0001", "0111", OTHERS; "0001", "0010", "0011", "0111", "1001", OTHERS; "0001", "0011", "0100", "0101", "0111", "1001", OTHERS; "0001", "0100", "0111", OTHERS;

WHEN "0010", WHEN OTHERS;

VHDL Designs

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VHDL Tutorial

WITH dataIn SELECT segments(5) <= ’1’ WHEN "0101", ’0’ WHEN OTHERS; WITH dataIn SELECT segments(6) <= ’1’ WHEN "0001", ’1’ WHEN "0100", ’0’ WHEN OTHERS; -- segments(7) <= DecimalIn; END theLongWay;

ARCHITECTURE theBetterWay OF seven_seg IS BEGIN -- seven segment display is active low -- segments defined same as with showhex -6 -1 5 -0 -2 4 -3 -- 7 is decimal point, always off WITH dataIn SELECT segments <= "10000001" WHEN "0000", "11001111" WHEN "0001", "10010010" WHEN "0010", "10000110" WHEN "0011", "11001100" WHEN "0100", "10100100" WHEN "0101", "10100000" WHEN "0110", "10001111" WHEN "0111",

VHDL Designs

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VHDL Tutorial

"10000000" WHEN "1000", "10000100" WHEN "1001", "11111111" WHEN OTHERS; END theBetterWay;

VHDL Designs

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VHDL Tutorial

VHDL and Quartus II
• Open a new vhdl file • Use a template to give basic structure. (2 input AND gate); • LIBRARY • USE • ENTITY • ARCHITECTURE

VHDL Designs

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VHDL Tutorial

A First VHDL Description
• Start Quartus II and open a new VHDL file. • Save the file as a VHDL file named and.vhd. • Start editing the file... --- A 2 input AND Gate --- A nice description of my file -- My name and date -LIBRARY ieee; USE ieee.std_logic_1164.all;

VHDL Designs

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VHDL Tutorial

Designing a Multiplexer
Suppose you wished to design a Quad 2-Input Multiplexer (MUX)...

select_data

data_a data_q data_a

• Required Inputs – 1 control bit – 4 pairs of 2 input lines • Outputs – Four output lines

VHDL Designs

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VHDL Tutorial

Entity Declaration for a Quad 2-Input Multiplexer
-- Quadruple 2 Input MUX LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY quad_2_input IS PORT ( select_data data_a, data_b data_q ); END quad_2_input;

: IN : IN : OUT

STD_LOGIC; STD_LOGIC_VECTOR(3 DOWNTO 0); STD_LOGIC_VECTOR(3 DOWNTO 0)

VHDL Designs

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VHDL Tutorial

Device Functionality
The truth table for the MUX would be:

select 0 1

data q0 data a0 data b0

data q1 data a1 data b1

data q2 data a2 data b2

data q3 data a3 data b3

VHDL Designs

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VHDL Tutorial

Architecture Body
• The architecture body can contain a description of – Behaviour – Structure – Combination of behaviour and structure • The architecture body contains – A name – A description of the entity being implemented – Statements to implement the entity

VHDL Designs

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VHDL Tutorial

Gate Model
-- Quadruple 2 Input MUX LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY quad_2_input IS PORT ( select_data data_a, data_b data_q ); END quad_2_input; ARCHITECTURE gates_only OF quad_2_input IS BEGIN data_q(0) data_q(1) data_q(2) data_q(3) <= <= <= <= (data_a(0) (data_a(1) (data_a(2) (data_a(3) AND AND AND AND NOT NOT NOT NOT select_data) select_data) select_data) select_data) OR OR OR OR (data_b(0) (data_b(1) (data_b(2) (data_b(3) AND AND AND AND select_data); select_data); select_data); select_data);

: IN : IN : OUT

STD_LOGIC; STD_LOGIC_VECTOR(3 DOWNTO 0); STD_LOGIC_VECTOR(3 DOWNTO 0)

END gates_only;

VHDL Designs

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VHDL Tutorial

Conditional Assignment
-- Quadruple 2 Input MUX LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY quad_2_input IS PORT ( select_data data_a, data_b data_q ); END quad_2_input; ARCHITECTURE conditional_assign OF quad_2_input IS BEGIN data_q <= data_a WHEN select_data = ’0’ ELSE data_b; END conditional_assign;

: IN : IN : OUT

STD_LOGIC; STD_LOGIC_VECTOR(3 DOWNTO 0); STD_LOGIC_VECTOR(3 DOWNTO 0)

VHDL Designs

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VHDL Tutorial

Selected Assignment Statement
-- Quadruple 2 Input MUX LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY quad_2_input IS PORT ( select_data data_a, data_b data_q ); END quad_2_input; ARCHITECTURE using_select OF quad_2_input IS BEGIN WITH select_data SELECT data_q <= data_a WHEN ’0’, data_b WHEN OTHERS, END using_select;

: IN : IN : OUT

STD_LOGIC; STD_LOGIC_VECTOR(3 DOWNTO 0); STD_LOGIC_VECTOR(3 DOWNTO 0)

VHDL Designs

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VHDL Tutorial

Process and If Statements
-- Quadruple 2 Input MUX LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY quad_2_input IS PORT ( select_data data_a, data_b data_q ); END quad_2_input; ARCHITECTURE process_if OF quad_2_input IS

: IN : IN : OUT

STD_LOGIC; STD_LOGIC_VECTOR(3 DOWNTO 0); STD_LOGIC_VECTOR(3 DOWNTO 0)

BEGIN PROCESS (select_data, data_a, data_b) BEGIN IF (select_data = ’0’) THEN data_q <= data_a; ELSE data_q <= data_b; END IF; END PROCESS; END process_if;

VHDL Designs

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VHDL Tutorial

Process and Case Statements
-- Quadruple 2 Input MUX LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY quad_2_input IS PORT ( select_data data_a, data_b data_q ); END quad_2_input; ARCHITECTURE process_case OF quad_2_input IS BEGIN PROCESS (select_data, data_a, data_b) BEGIN CASE select_data IS WHEN ’0’ => data_q <= data_a; WHEN OTHERS => data_q <= data_b; END CASE; END PROCESS; END process_case;

: IN : IN : OUT

STD_LOGIC; STD_LOGIC_VECTOR(3 DOWNTO 0); STD_LOGIC_VECTOR(3 DOWNTO 0)

VHDL Designs

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VHDL Tutorial

Process and Loop Statements
-- Quadruple 2 Input MUX LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY quad_2_input IS PORT ( select_data data_a, data_b data_q ); END quad_2_input; ARCHITECTURE process_loop OF quad_2_input IS BEGIN PROCESS (select_data, data_a, data_b) BEGIN FOR i IN 0 to 3 LOOP data_q(i) <= (data_a(i) AND NOT select_data) OR (data_b(i) AND select_data); END LOOP; END PROCESS; END process_loop;

: IN : IN : OUT

STD_LOGIC; STD_LOGIC_VECTOR(3 DOWNTO 0); STD_LOGIC_VECTOR(3 DOWNTO 0)

VHDL Designs

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VHDL Tutorial

Execution of VHDL
When do the statements get executed? • Compile your VHDL code • Simulate your VHDL MUX using the waveform file mux.vwf

VHDL Designs

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VHDL Tutorial

Using Components
This slide illustrates the use of components.
LIBRARY ieee; USE ieee.std_logic_1164.all; -- Entity Declaration ENTITY conf_seven_seg IS PORT( ConfDataIn : IN STD_LOGIC_VECTOR(3 downto 0); ConfDPin : IN STD_LOGIC; ConfSegments: OUT STD_LOGIC_VECTOR(7 downto 0)); END conf_seven_seg; -- Architecture Body ARCHITECTURE Long OF conf_seven_seg IS SIGNAL DPInternal : STD_LOGIC; SIGNAL DinInternal : STD_LOGIC_VECTOR(3 downto 0); SIGNAL DoutInteral : STD_LOGIC_VECTOR(7 downto 0); COMPONENT seven_seg PORT( DataIn : IN STD_LOGIC_VECTOR(3 downto 0); DecimalIn : IN STD_LOGIC; segments : OUT STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; BEGIN LongSevenSeg: seven_seg PORT MAP (DataIn => ConfDataIn, DecimalIn => ConfDPIn, segments => ConfSegments ); END Long;

VHDL Designs

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