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Specially designed microprocessors
– It is small on chip computer
Highly integrated chip includes all or most parts needed for controller A typical microcontroller has:
– bit manipulation – easy and direct access to I/O – quick and efficient interrupt processing
Microcontroller drastically reduces design cost
Worldwide Microcontroller shipments - in millions of dollars '95 4-bit 8-bit 1826 5634 '96 1849 6553 1628 '97 1881 7529 2191 '98 1856 8423 2969 '99 1816 9219 3678 00 1757 9715 4405
WSTS & ICE
Worldwide Microcontroller shipments - in millions '95 4-bit 8-bit 16-bit 1100 1803 157 '96 1100 2123 227 '97 1096 2374 313 '98 1064 2556 419 '99 1025 2681 501 00 970 2700 585
WSTS & ICE
disk drives) Automobiles (engine control.Applications Appliances (microwave oven. modems. Environmental control (greenhouse. stereos) Computers and computer equipment (laser printers. home) Instrumentation Aerospace Robotics. diagnostics. refrigerators. factory.. . television and VCRs.. etc. climate control).
and other tasks. 8. – keyboard handling. or 32 bit microcontrollers specialized processors include features specific for – communications. .Flavors 4. – video processing. – signal processing. 16.
80188 (Intel) 80386 EX (Intel) 65C02/W65C816S/W65C134S (Western Design Center) MC14500 (Motorola) .Part 1 Popular Microcontrollers 8048 (Intel) 8051 (Intel and others) 80c196 (MCS-96) 80186.
Part 2 Popular Microcontrollers 68HC05 (Motorola) 68HC11 (Motorola and Toshiba) 683xx (Motorola) PIC (MicroChip) COP400 Family (National Semiconductor) COP800 Family (National Semiconductor) HPC Family (National Semiconductor) Project Piranha (National Semiconductor) .
Part 3 Popular Microcontrollers Z8 (Zilog) HD64180 (Hitachi) TMS370 (Texas Instruments) 1802 (RCA) MuP21 (Forth chip) F21 (Next generation Forth chip) .
Part 1 Programming Microcontrollers Machine/Assembly language Interpreters (Java. .. .) Compilers (C.... C++.) Fuzzy Logic and Neural Networks .
Part 1 Development Tools Simulators Resident Debuggers Emulators .
LCD driver.) . FLASH. memory. etc. etc.) Additional features (EEPROM.Choosing microcontoller Technical support Development tools Documentation Purchasing more devices at one manufacturer (A/D.
Microcontrollers Basic parts are: – Central Processing Unit – RAM – EPROM/PROM/ROM or FLASH Memory – I/O serial or/and parallel – timers – interrupt controller external inerrupts interrupt control ROM RAM timer 1 timer 0 counter inputs CPU Optional parts are: – – – – Watch Dog Timer AD Converter LCD driver etc. OSC bus control 4 I/O ports serial port TxD RxD P0 P2 P1 P3 address/ data .
Intel 8051 A typical 8051 contains: – CPU with Boolean processor – 5 or 6 interrupts: 2 external. 2 priority levels P2 LATCH PORT2 RAR 128x8 RAM 4Kx8 ROM PCH PCL P0 LATCH DPH DPL P2 LATCH PORT2 RAM BUFFER SENSE AMPS INTERNAL BUS A ALU ROM IR PLA – 2 or 3 16-bit timer/counters – programmable full-duplex serial port – 32 I/O lines (four 8-bit ports) – RAM – ROM/EPROM in some models PSW TMP2 TMP1 B CONTROL SP ALU P0 LATCH PORT0 SCON SBUF(REC) SBUF(XMIT) TCON TMOD TL0 TH0 TL1 TH1 TIMER CONTROL IE IP INTERRUPT CONTROL P3 LATCH PORT3 SERIAL PORT .
7 . bi-directional I/O port – Pins that have 1s written to them float and can be used as high-impedance inputs – Multiplexed low-order address and data bus during accesses to external program and data memory RST EA/Vpp PSEN XTAL1 ADDRESS AND DATA BUS XTAL2 ALE/PROG SECONDARY FUNCTIONS RxD TxD PORT 3 INT0 INT1 T0 T1 WR RD PORT 2 PORT 1 ADDRESS BUS .Part 1 Intel 8051: Pin Description VCC VSS PORT 0 VSS .Power Supply P0.Port 0 – Open drain.Ground: 0V VCC .0-P0.
External interrupt INT1 .Serial output port INT0 .Serial input port TxD .Timer 0 external input T1 .7 .7 .0-P2.External interrupt T0 .External data memory write strobe – RD .0-P3. .Timer 1 external input WR .Part 2 Intel 8051: Pin Description P2. – Port 2 emits high-order address byte during accesses to external program and data memory Port 3 serves the special features: – – – – – – – RxD .Port 3 – Bi-directional I/O port with internal pull-ups – Pins that have 1s written to them float and can be used as high-impedance inputs.External data memory read strobe P3.Port 2 – Bi-directional I/O port with internal pull-ups – Pins that have 1s written to them float and can be used as high-impedance inputs.
Crystal 1 – Input to the inverting oscillator amplifier and input to internal clock generator circuits PSEN .Part 3 Intel 8051: Pin Description RST .External Access Enable – EA must be externally held low to enable device to fetch code from external memory locations. ALE .Crystal 2 – Output from the inverting oscillator amplifier .Program Store Enable – Read strobe to external program memory XTAL2 .Reset – A high on this pin for two machine cycles resets the devices EA .Address Latch Enable – Output pulse for latching the low byte of address during an access to external memory XTAL1 .
0/A8 Dual In-Line Package Plastic Lead Chip Carrier Plastic Quad Flat Pack P1.2/A10 P2.1/AD1 P0.5 P1.7/A15 P2.0/AD0 P0.5/AD5 P0.5/A13 P2.3 P1.6/A14 P2.Part 1 Intel 8051: Pin Configurations P1.1 INT0/P3.6 P1.6/AD6 EA ALE PSEN P2.6 RD/P3.4/AD4 P0.1 P1.3 T0/P3.2/AD2 P0.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.7 RST RxD/P3.7 XTAL2 XTAL1 Vss .4/A12 P2.6/AD6 P0.2 INT1/P3.4 T1/P3.5 WR/P3.1/A9 P2.2 P1.0 TxD/ P3.4 P1.3/AD3 P0.3/A11 P2.
0/RxD 6 NIC 7 P3.4/AD4 34 P0.3/INT1 –29 –28 –31 P2.4/T0 11 P3.6/A14 P2.1/A9 –26 P2.2/AD2 –42 P0.2/A10 P2.1/AD1 37 P0.6/A14 12 1 P1.4/T0 –17 P3.1/A9 P2.5/T1 12 P3.Part 2 Intel 8051: Pin Configurations –6 –1 –40 44 34 –7 –39 1 33 PQFP PLCC –17 –18 –1 NIC –2 P1.3 44 P1.7 4 RST 5 P3.1/TxD 8 P3.6 3 P1.3/INT1 10 P3.5/AD5 33 P0.4/AD4 –40 P0.3/AD3 35 P0.4/A12 –29 P2.0/A8 P2.5/AD5 –39 P0.3 –6 P1.5/A13 –30 P2.5/T1 –18 P3.5 –8 P1.4/A12 P2.3/A11 P2.1 –4 P1.6/WR –19 P3.6/AD6 32 P0.6 –9 P1.6/WR 13 P3.0 41 P1.0/AD0 38 VCC 39 NIC 40 P1.4 –7 P1.2/AD2 36 P0.4/RD 14 XTAL2 15 XTAL1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VSS NIC P2.7/A15 –32 PSEN –33 ALE –34 NIC –35 EA –36 P0.1 42 P1.7/A15 PSEN ALE NIC EA P0.4/RD –20 XTAL2 –21 XTAL1 –22 VSS –23 NIC –24 P2.3/AD3 –41 P0.0/RxD –12 NIC –13 P3.1/TxD –14 P3.4 .7/AD7 22 31 P0.3/A11 –28 P2.2 –5 P1.6/AD6 –38 P0.7/AD7 –37 P0.2/A10 –27 P2.2 43 P1.0/A8 –25 P2.0 –3 P1.0/AD0 –44 VCC 11 23 –16 P3.2/INT0 –15 P3.5/A13 P2.2/INT0 9 P3.7 –10 RST –11 P3.5 2 P1.1/AD1 –43 P0.
PSW and SP – sixteen-bit Program Counter (PC) – Data Pointer registers RAR 128x8 RAM 4Kx8 ROM PCH PCL P0 LATCH DPH DPL P2 LATCH PORT2 RAM BUFFER SENSE AMPS INTERNAL BUS P2 LATCH PORT2 A ALU ROM IR PLA TMP2 TMP1 B CONTROL PSW ALU SP P0 LATCH PORT0 SCON SBUF(REC) SBUF(XMIT) TCON TMOD TL0 TH0 TL1 TH1 TIMER CONTROL IE IP INTERRUPT CONTROL P3 LATCH PORT3 SERIAL PORT .Part 1 Intel 8051: CPU Primary elements are: – eight bit ALU with associated registers A. B.
Part 2 Intel 8051: CPU The ALU can manipulate one-bit as well as eight-bit data types – This features makes the 8051 especially well suited for controller-type applications A total of 51 separated operations move and manipulate three data types: – Boolean (1-bit) – Byte (8-bit) – Address (16-bit) .
Part 3 Intel 8051: CPU Instruction types: – – – – – Arithmetic Operations Logic Operations for Byte Variables Data Transfer Instructions Boolean Variable Manipulation Program Branching and Machine Control .
bringing total number of instructions to 111. encompassing 255 of the 256 possible 8-bit instruction opcodes 8051 instruction set fares well at both real-time control and data intensive algorithms .Part 4 Intel 8051: CPU There are eleven addressing modes: – seven for data – four for program sequence control Most operations allow several addressing modes.
and a different functions Architecture supports several distinct “physical” address spaces functionally separated at the hardware level: – – – – – On .chip program memory Off .Part 1 Intel 8051: Memory Organization Program memory is separate distinct from data memory – Each memory type has a different addressing mechanism.chip data memory On chip special function registers .chip data memory Off . different control signals.chip program memory On .
Part 2 Intel 8051: Memory Organization Program (Code) memory – Holds the actual 8051 program that is to be run – Limited to 64K – may be found on-chip as ROM or EPROM – may be stored completely off-chip in an external ROM or an external EPROM – Flash RAM is also another popular method of storing a program – Various combinations of these memory types may be used (e. 4 K on-chip and 64 KB off-chip) .g.
Part 3 Intel 8051: Memory Organization External RAM – External RAM is any random access memory which is found off-chip – External RAM is slower • To increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction cycle • To increment a 1-byte value stored in External RAM requires 4 instructions and 7 instruction cycles – While Internal RAM is limited to 128 bytes (256 bytes with an 8052). the 8051 supports External RAM up to 64K .
Intel 8051: Memory Organization
– Two types:
• Internal RAM; and • Special Function Register (SFR) memory
– Internal RAM is on-chip so it is the fastest RAM available – Internal RAM is volatile, when the 8051 is reset this memory is cleared – Special Function Registers (SFRs) are areas of memory that control specific functionality of the 8051 processor
Intel 8051: Memory Access
PORT 2 : High byte of address held for the duration of read or write cycle PORT 0 : time multiplexed low byte of address with data byte Signal ALE: used to capture the address byte into an external latch
CS RD WR
PSEN RD WR
64 Kbytes - Program memory (external) 64 Kbytes - Data Memory
Intel 8051: Memory Access
STAGE 1 P1 XTAL1 P2 STAGE 2 P1 P2 STAGE 3 P1 P2 STAGE 4 P1 P2 STAGE 5 P1 P2 STAGE 6 P1 P2
XTAL1 STAGE 4 P1 P2 STAGE 5 P1 P2 STAGE 6 P1 P2 STAGE 1 P1 P2 STAGE 2 P1 P2 STAGE 3 P1 P2
PSEN INS. IN INS. IN
INS. IN P0
Part 1 Intel 8051: Program Memory PROGRAM MEMORY Up to 64K of Program Memory PSEN: read strobe for all external program fetches PSEN: not activated for internal program fetches Depending on EA pin lowest bytes can be either in the on-chip ROM or in an external ROM 0xFFFF EA = 0 0x0000 EXTERNAL EA = 1 PSEN .
its service location is available as general purpose Program Memory LOWER PART OF PROGRAM MEMORY 0x0028 0x0023 0x0018 0x0013 8 BYTES 0x0008 0x0003 RESET 0x0000 INTERRPUT LOCATIONS .Part 2 Intel 8051: Program Memory Boot address .0x0000 Each interrupt is assigned a fixed location in Program Memory If interrupt is not going to used.
Part 3 Intel 8051: Program Memory Port 0 and Port 2 are dedicated to bus functions during external Program Memory fetches PORT0 EA AD0-AD7 A0-A7 INSTR LATCH ALE PORT2 LE A8-A15 ADDR PSEN 8051 OE EROM .
Part 1 Intel 8051: Data Memory DATA MEMORY Up to 64K Data Memory Access to Data memory use RD or WR to strobe the memory 0xFFFF INTERNAL 0xFF 0x00 0x0000 RD WR EXTERNAL .
although they are physically separate entities INTERNAL 0xFF UPPER 128 ACCESSIBLE BY INDIRECT ADDRESSING ONLY ACCESSIBLE BY DIRECT ADDRESSING ONLY 0x7F SPECIAL FUNCTION REGISTERS PORTS STATUS BITS CONTOL BITS TIMER REGISTERS STACK POINTER ACCUMULATOR (ETC.Intel 8052) Direct addressing higher then 0x7F access one memory space.Part 2 Intel 8051: Data Memory Internal Memory Addresses are one byte wide 128 bytes address space (256 . indirect addressing higher then 0x7F access a different memory space Upper 128 and SFR space occupying same block of addresses.) LOWER 128 ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING 0x00 .
Part 3 Intel 8051: Data Memory The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers R0 through R7 Two bits in the PSW selects register bank – Register instructions are shorter LOWER 128 BYTES OF INTERNAL RAM 0x7F 0x2F BANK SELECT BITS IN PSW 0x20 0x1F BIT ADDRESSABLE SPACE (BIT ADDRESSES 0-7F) The next 16 bytes form a block of bit-addressable space 11 0x18 0x17 10 0x10 0x0F 4 BANKS OF 8 REGISTERS R0-R7 RESET VALUE OF STACK POINTER 01 0x08 0x07 00 0x00 .
Part 1 Intel 8051: SFR SFRs are accessed as if they were normal Internal RAM SFR registers exist in the address range of 80h through FFh Each SFR has an address and a name .
Part 2 Intel 8051: SFR 0 F8 F0 B E8 E0 ACC D8 D0 PSW C8 C0 B8 IP B0 P3 A8 IE A0 P2 98 SCON 90 T1 88 TCON 80 T0 1 2 3 4 5 6 7 FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F PCON 87 SBUF TMOD SP TL0 DPL TL1 DPH TH0 TH1 .
Part 3 Intel 8051: SFR Accumulator (A) – Accumulator register B Register (B) – Used during multiply and divide operations – The Stack Pointer is initialized on 0x07 after a reset. and this causes stack to begin at location 0x08 Data Pointer(DPTR) – Consist high byte (DPH) and low byte (DPL) – It may be manipulated as a 16-bit register or as two independent 8-bit registers PSW – Contains program status information Stack Pointer (SP) – Eight bits wide – Stack may reside anywhere in on chip RAM .
P2. P1. TL0) Counting Registers for Timer/Counter 1 and 0 Serial Data Buffer (SDBF) – It is actually two separated registers: receive and transmit buffer registers – When data is moved to SBUF it goes to the transmit buffer – When data is moved from SBUF it comes from the receive buffer Control Registers – – – – – IP: Interrupt priority IE: Interrupt enable TMOD Timer/Counter mode TCON Timer/Counter control PCON Power control . T0) – (TH1. P4) – Latches of Port 0 to 3. TL1) (TH0.Part 4 Intel 8051: SFR Ports 0 to 3 (P0. respectively Timer Registers (T1.
Bank 2 [ 0x10-0x17].Intel 8051: PSW 7 PSW Carry flag Auxiliary Carry flag Flag 0 Re gistar Bank Sele ct bit 1 CY 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 - 0 P Parity flag Ove rflow flag Re gistar Bank Sele ct bit 1 Auxiliary Carry flag is used for BCD operations Flag 0 is available to user for general purposes The contest of (RS1.Bank 3 [0x18-0x1F] . 11 . 01 . 10 . RS2) enable working register banks as follows: 00 .Bank 0 [0x00-0x07].Bank 1 [0x08-0x0f].
numbered S1 through S6 Each state time lasts for two oscillator periods Each state is then divided into a Phase 1 and Phase 2 half .Intel 8051: CPU Timing S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 ALE The internal clock generator defines the sequence of states that make up a machine cycle A machine cycle consists of 6 states.
Part 1 Intel 8051: Port Structures Pseudo bi-directional I/O port structure – On Port0 R2 is disabled except during bus operations (open-collector output) READ/M ODIFY/ WRITE ENB +5V +5V Q2 The address latch bit is updated by direct addressing instructions The value read is “OR-tied” function of Q1 and the external device To use a pin for input latch must be set INTERNAL BUS WRITE PULSE D SET R1 R2 Q Q1 I/O PIN Q CLR BUS CYCLE TIMING INPUT BUFFER ENB READ .
Intel 8051: Port Interfacing The output buffers of Ports 0. 2 and 3 can each drive 4 LS TTL inputs Can be driven by open-collector and open-drain outputs – 0-to-1 transitions will not be fast since there is little current pulling the pin up Port 0 output buffers can each drive 8 LS TTL inputs (external bus mode) As port pins PORT 0 requires external pull-ups to be able to drive any inputs bit . 1.
Intel 8051: Special Peripheral Functions There are few special needs common among control-oriented computer systems: – – – – keeping tracks of elapsed time maintaining a count of signal transitions measuring the precise width of input pulses communicating with other systems – closely monitoring asynchronous external events .
the count is incremented – The new count value is appears in S3P1 of the following detection cycle – Max count rate is 1/24 of oscillator frequency TMOD . T1) – External input is sampled at S5P2 of every machine cycle – When the samples show high in one cycle and low in the next.Timer/Counter control register .Timer/Counter mode register TCON .Part 1 Intel 8051: Timers/Counters Two 16-bit Timer/Counter registers Timer: Register is incremented every machine cycle (1 machine cycle = 12 oscillator periods) Counter: Register is incremented in response to 1-to-0 transition at its corresponding external input pin (T0.
Intel 8051: Timers/Counters
GATE: Gating control when set C/T: Counter or Timer Selector M1 M0:
– 00: 8-bit Timer/Counter with 5-bit prescaler – 01: 16-bit Timer/Counter – 10: 8-bit auto reload Timer/Counter – 11: (Timer0) TL0 is 8-bit Timer/Counter controlled by Timer0 control bits TH0 is 8-bit timer only controlled by Timer1 control bits – 11: (Timer1) Timer/Counter is stopped
GATE C/T M1 M0
Intel 8051: Timers/Counters
TCON 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
TF: Overflow flag
– Set by hardware on Timer/Counter overflow – Cleared by hardware when processor vectors to interrupt routine
TR: Run control bit
– Set/Cleared by software to turn Timer/Counter on/off
IE: Interrupt Edge flag
– Set by hardware when external interrupt edge detected – Cleared when interrupt processed
IT: Interrupt Type control bit
– Set/Cleared by software to specify falling edge/low level triggered external interrupts
Intel 8051: Timers/Counters
OSC 1/12 TL1 (5 bits) T1 PIN TH1 (8 bits)
Part 5 Intel 8051: Timers/Counters OSC 1/12 C/T=0 TL1 (8 bits) C/T=1 T1 PIN TH1 (8 bits) TF1 INTERRUPT TR1 GATE MODE 1 INT1 PIN .
Part 6 Intel 8051: Timers/Counters OSC 1/12 TL1 (8 bits) T1 PIN RELOAD TR1 GATE TH1 (8 bits) TF1 INTERRUPT MODE 2 INT1 PIN .
Part 7 Intel 8051: Timers/Counters OSC 1/12 C/T=0 TL0 (8 bits) C/T=1 T0 PIN TF0 INTERRUPT TR0 GATE MODE 3 1/12 fosc TH0 (8 bits) TF1 INTERRUPT INT0 PIN TR1 .
Part 1 Intel 8051: Serial Port Interface Full-duplex Serial port receive and transmit registers are both accessed at Special Function Register SBUF – Writing to SBUF loads the transmit register – Reading from SBUF accesses a physically separated receive register Four modes of operation – In all four modes transmission is initiated by any instruction that uses SBUF as destination register – Reception is initiated in Mode 0 by condition RI=0 and REN=1 In other modes by the incoming start bit if REN=1 SCON .Serial Port Control Register .
Shift register. 8-bit UART.Part 2 Intel 8051: Serial Port Interface SCON 7 SM0 6 SM1 5 SM0 4 REN 3 TB8 2 RB8 1 TI 0 RI SM0 SM1: – – – – 00: Mode 0. 9-bit UART. variable SM2: Enables multiprocessor features in Mode 2 and Mode 3 – When the stop bit is received. variable 10: Mode 2. 9-bit UART. fosc//12 01: Mode 1. the interrupt will be activated only if RB8=1 (9th bit =1) REN: Enables serial reception – Set/Clear by software . fosc//32 or fosc//64 11: Mode 3.
if SM2=0. is the stop bit that was received TI: Transmit interrupt flag – Set by hardware.Part 3 Intel 8051: Serial Port Interface SCON 7 SM0 6 SM1 5 SM0 4 REN 3 TB8 2 RB8 1 TI 0 RI TB8: 9th data bit that will be transmitted in Mode2 and Mode3 – Set/Clear by software RB8: 9th data bit that was received in Mode2 and Mode3 In Mode 1. Must be cleared by software . Must be cleared by software RI: Receive interrupt flag – Set by hardware.
exits through TXD – 10 bits are transmitted/received: start bit(0). stop bit(1) – On receive the stop bit goes into RB8 in SCON register – The baud rate is variable . 8 data bits (LSB first).Part 4 Intel 8051: Serial Port Interface MODE 0: – – – – Serial data enters and exits through RXD TXD outputs shift clock 8 bits are transmitted/received: 8 data bits (LSB first) The baud rate is fixed at 1/12 oscillator frequency MODE 1: – Serial data enters through RXD.
exits through TXD – 11 bits are transmitted/received: start bit(0).Part 5 Intel 8051: Serial Port Interface MODE 2: – Serial data enters through RXD. 8 data bits (LSB first). the 9th bit is TB8 in SCON register – On receive. the 9th bit goes into RB8 in SCON register – The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency MODE 3: – Same as MODE 2 in all respects except baud rate – The baud rate is variable . stop bit(1) – On transmit. a programmable 9th bit.
auto-reload : Timer Overflow Rate=Oscillator frequency/[12*(256-TH1)] .3 Baud Rate =[(2SMOD)/32]* Timer 1 Overflow Rate – Timer mode.Part 6 Intel 8051: Serial Port Interface Mode 0 Baud Rate = Oscillator frequency/12 Mode 2 Baud Rate =[(2SMOD)/64]*Oscillator frequency – SMOD is bit in Special Function Register PCON Mode 1 and Mode3 baud rate is determined by Timer 1 overflow rate Mode 1.
059 MHz 11.059 MHz 6 MHz 12 MHz SMOD C/T 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mode 2 2 2 2 2 2 2 2 1 Reload Value FF FD FD FA F4 E8 1D 72 FEEB .5 110 110 Timer1 fosc 12 MHz 11.2 K 9.2 K 135.059 MHz 11.8 K 2.Part 7 Intel 8051: Serial Port Interface Baud Rate 62.059 MHz 11.059 MHz 11.059 MHz 11.6 K 4.4 K 1.5 K 19.
Part 1 Intel 8051: Interrupt Control IE 7 EA 6 5 4 ES 3 ET! 2 EX1 1 ET0 0 EX0 EA: Enable/Disable all interrupts – If EA=0 no interrupts will be acknowledged – If EA=1 each interrupt source is individually enabled/disbled ES: Serial Port interrupt enable bit ET: Timer interrupt enabled bit EX: External interrupt enable bit .
TF1) INT0 IT0=1 IE0 TF0 • Serial Port (RI or TI) INT1 IT1=0 IE1 IT1=1 INTERRUPT SOURCE TF1 RI TI . INT1) • 2 timers (TF0.Part 2 Intel 8051: Interrupt Control • 5 interrupt sources IT0=0 • 2 external (INT0.
until the requested interrupt is actually generated. IE1 in TCON • Cleared by hardware if the interrupt was transition-activated • if the interrupt was level-activated. IT1 in register TCON The flags that generate these interrupts are IE0. external source controls request bits If external interrupt is level-activated. or else another interrupt will be generated . External source has to deactivate the request before interrupt service is completed. the external source has to hold request active.Part 3 Intel 8051: Interrupt Control External interrupts – – INT0 IT0=0 IE0 – – Level-activated or transition-activated IT0=1 depending on bits IT0.
Part 4 Intel 8051: Interrupt Control Timer interrupts – Interrupts are generated by TF0 and TF1 in register TCON – When a timer interrupt is generated. the flag that generated it is cleared by hardware when the service routine is vectored to Serial Port interrupt – generated by the logical OR of bits RI and TI in register SCON TI RI .
Priority bit=0: Low Priority PS: Serial Port priority bit PT: Timer priority bit PX: External priority bit .Part 5 Intel 8051: Interrupt Control IP 7 6 5 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Priority bit=1: High Priority.
the request of higher priority level is serviced If requests of the same priority level are received simultaneously.Part 6 Intel 8051: Interrupt Control A low-priority interrupt can be interrupted by a higher priority interrupt. . but not by another low-priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests are received simultaneously. an internal polling sequence determines which request is serviced – ``priority within level'' structure is only used to resolve simultaneous requests of the same priority level.
Part 7 Intel 8051: Interrupt Control Interrupt Priority within Level Polling Sequence 1 (Highest) External Interrupt 0 2 3 4 5 (Lowest) Timer 0 External Interrupt 1 Timer 1 Serial Port .
Part 8 Intel 8051: Interrupt Control The INT0 and INT1 levels are inverted and latched into the Interrupt Flags IE0 and IE1 at S5P2 of every machine cycle Serial Port flags RI and TI are set at S5P2 The Timer 0 and Timer 1 flags. the response time is always more than 3 cycles and less than 9 cycles . are set at S5P2 of the cycle in which the timers overflow If a request is active and conditions are right. TF0 and TF1. a hardware subroutine call to the requested service routine will be the next instruction to be executed In a single-interrupt system.
which has a Schmitt Trigger input Accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running The RST pin is sampled during S5P2 of every machine cycle While the RST pin is high.Part 1 Intel 8051: Reset The reset input is the RST pin. the port pins. ALE and PSEN are weakly pulled high Driving the ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state .
Part 2 Intel 8051: Reset S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 RST INTERNAL RESET SIGNAL SAMPLE RST SAMPLE RST ALE PSEN P0 IN S. IN IN S. IN A0-A7 A0-A7 A0-A7 A0-A7 A0-A7 11 OSC. IN IN S. PERIODS 19 OSC. IN IN S. IN IN S. IN IN S. PERIODS .
Intel 8051: Power On Reset RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles The oscillator start-up time depend on the oscillator frequency Port pins will be in a random state until the oscillator has started and the internal reset algorithm has written 1s to them Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location .
Intel 8051: EPROM Versions Electrically programmable by user Relative slow Limited number of erase/write cycles .
Intel 8051: OTP Versions One Time Programmable It is standard EPROM without erasing window It is used for limited production .
Intel 8051: FLASH Versions Supports in-system and in-board code changes Electrically erasable Reduces code inventory and scrap Simplifies the task of upgrading code and reduces upgrade cycle time Provides just-in-time system software downloads Truly non-volatile .
Intel 8051: The On-Chip Oscillator Intel 8051 microcontrollers have an on-chip oscillator resonators are connected between XTAL1 and XTAL2 pins external oscillators (HMOS or CMOS) QUARTZ CRYSTAL OR CERAMIC RESONATOR 8051 XTAL2 C1 C2 XTAL1 VSS .
Intel 8051: Power Management Low power devices Power saving Voltage monitoring .
Intel 8051: Power Reduction Modes CHMOS versions provides power reduced modes of operations There are two power reducing modes Idle and Power Down In the Idle mode oscillator continues to ran Interrupt. Timer and Serial Port blocks continue to be clocked clock signal is gated off to the CPU In the Power Down mode the oscillator is frozen .
Part 1 Intel 8051: Instruction Set Arithmetic Operations ADD ADDC SUBB INC DEC MUL DIV DA Addition Addition with Carry Flag Subtraction Increment Decrement Multiply Divide Decimal Adjust Accumulator .
Part 2 Intel 8051: Instruction Set Logical Operations AND ORL XRL CLR CPL RL RLC RR RLC SWAP And Or Exclusive-Or Clear (Accumulator) Complement Rotate Left Rotate Left through Carry Flag Rotate Right Rotate Right through Carry Flag Swap nibbles within Accumulator A A A A A A A .
Part 3 Intel 8051: Instruction Set Data Transfer MOV MOVC MOVX PUSH POP XCH XCHD Move Move Code byte Move External RAM byte/word Push direct byte on stack Pop direct byte from stack Exchange Exchange low order Digit .
Part 4 Intel 8051: Instruction Set Boolean Variable Manipulation CLR SET CPL ANL ORL MOV Clear bit/flag Set bit/flag Complement bit/flag AND bit and flag OR bit and flag Move bit .
Part 5 Intel 8051: Instruction Set Program and Machine Control #1 ACALL LCALL RET RETI AJMP LJMP SJMP JMP Absolute Subroutine Call Long Subroutine Call Return from Subroutine Return from interrupt Absolute Jump Long Jump Short (Relative) Jump @A+DPTR Jump indirect relative to the DPTR .
Part 6 Intel 8051: Instruction Set Program and Machine Control #2 JZ JNZ JC JNC JB JNB JBC CJNE DJNZ NOP Jump if Accumulator is Zero Jump if Accumulator is Not Zero Jump if Carry flag is set Jump if No Carry flag Jump if Bit set Jump if Bit Not set Jump if Bit set & Clear bit Compare and Jump if Not Zero Decrement and Jump if Not Zero No Operation .
Part 7 Intel 8051: Instruction Set Instructions that affect Flag Settings #1 ADD ADDC SUBB MUL DIV DA RRC RLC C X X X 0 0 X X X OV X X X X X AC X X X .
Part 8 Intel 8051: Instruction Set Instructions that affect Flag Settings #2 SET CLR CPL ANL ORL MOV CJNE C C C C 1 0 X X X X X X OV AC C. bit Operations on PSW X X .
30h MOV A.@DPTR MOVX @DPTR.A MOVC A.@R0 External Direct – only two commands that use External Direct – DPTR holds the correct external memory address MOVX A.#20h MOV A.A External Indirect Code Indirect MOVX @R0. never to an SFR MOV A.Intel 8051: Addressing Modes Immediate Addressing Direct Addressing Indirect Addressing – refers to Internal RAM.@A+DPTR .
Worldwide Microcontroller shipments .in millions of dollars '95 4-bit 8-bit 1826 5634 '96 1849 6553 1628 '97 1881 7529 2191 '98 1856 8423 2969 '99 1816 9219 3678 00 1757 9715 4405 16-bit 1170 Source WSTS & ICE .
Matra Microchip .Intel 8051: Manufacturers AMD ARM Microcontrollers ARC Cores Atmel Dallas OKI Philips Siemens SMC SSI Hitachi semiconductors Intel ISSI Texas Instruments ZiLog etc.
Intel 8051: Additional Features Watch Dog Timers Clock Monitor Resident Program Loader Software protection P Supervisory Circuit .
a hardware reset will be initiated Especially useful for unattended systems .Watch Dog Timers Provides a means of graceful recovery from a system problem If the program fails to reset the watchdog at some predetermined interval.
Clock Monitor If the input clock is too slow. a clock monitor can shut the microcontroller down Usually software controlled status (on/off) .
Resident Program Loader Loads a program by initializing program/data memory from either a serial or parallel port Eliminates the erase/burn/program cycle (typical with EPROM’s) Allows system updating from an offsite location .
piracy. modifications. Only OTPs and Windowed devices option . etc.Software protection Protect unauthorized snooping (reverse engineering.
Part 1 P Supervisory Circuit Functions: – – – – – – – – P reset (active low or high) Manual reset input Two stage power fall warning Backup-battery switchover Write protection of RAM 2.275 threshold detector Battery OK flag indicator Watch Dog timer PF1 PF0 Vcc WDI GND MR LOW LINE RESET 1 2 3 4 5 6 7 8 16 15 14 OUT BATT OK BATT BATT ON CE IN CE OUT WDO RESET MAXIM MAX807 13 12 11 10 9 .
Part 2 P Supervisory Circuit PIN 1 2 3 4 5 6 7 8 NAME PFI PFO VCC WDI GND MR LOW LINE RESET (H) FUNCTION Power-Fall Input Power-Fall Output Input Supply Voltage Watchdog Input Ground Manual-Reset Input Low-Line Comparator Input Active-High Reset Output .
Part 3 P Supervisory Circuit PIN 9 10 11 12 13 14 15 16 NAME RESET (L) WDO CE OUT CE IN BATT ON BATT BATT OK OUT FUNCTION Active-Low Reset Output Watchdog Output Chip-Enable Output Chip-Enable Input Battery On Output Backup-Battery Input Battery OK Signal Output (Vbatt>2.265) Output Supply Voltage to CMOS RAM .
Part 4 P Supervisory Circuit +5V 0.1uF Vcc BATT OUT ON BATT CMOS RAM CE OUT OTHER SYSTEM RESET SOURCES PUSH BUTTON SWITCH MR ADDRESS DECODE ADDRESS I/O NMI(INT) RESET INT REAL TIME CLOCK CE IN MAXIM MAX807 WDI LOW LINE RESET +12V RESET BATT OK PFI PFO WDO GND uP +12V FAILURE WATCHDOG FAILURE .1uF 0.
watchdog.2 kbyte 128 to 256 I/O 32 Timers/ Counters Up to 3 communication full duplex serial port two serial USARTs Additional Features 25 to 33 0 to 16 3 Intel 0.5 4 to 32 128 to 256 128 to 256 256-byte to 2.5 to 24 2.7 to 5.7 to 6 ROM [KB] 2 to 8 RAM [bytes] 128 to 256 256-byte to 1. I2C watchdog.Characteristics Comparisons Manufacturer Atmel Dallas Clock [MHz] 24 V [V] 2. power monitor.7 to 6 0 to 32 24 to 56 2 to 3 UART Matra Oki Siemens 42 2. 16-bit MPY/DIV unit . address and data encryption 4 to 8 channel 8bit ADC.2kbyte 32 2 to 3 UART. PWM ROM protection and secret tag. watchdog 24 18 to 40 0 to 16 8 to 32 32 56 2 to 3 3 to 4 UART two serial ports two watchdog timers.7 to 6 2.