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By Nagabhooshan S.Shet
The key board here we are interfacing is a matrix keyboard. This key board is designed with a particular rows and columns. These rows and columns are connected to the microcontroller through its ports of the micro controller 8051. We normally use 8*8 matrix key board. So only two ports of 8051 can be easily connected to the rows and columns of the key board. When ever a key is pressed, a row and a column gets shorted through that pressed key and all the other keys are left open. When a key is pressed only a bit in the port goes high. Which indicates microcontroller that the key is pressed. By this high on the bit key in the corresponding column is identified. Once we are sure that one of key in the key board is pressed next our aim is to identify that key. To do this we firstly check for particular row and then we check the corresponding column the key board. To check the row of the pressed key in the keyboard, one of the row is made high by making one of bit in the output port of 8051 high . This is done until the row is found out. Once we get the row next out job is to find out the column of the pressed key. The column is detected by contents in the input ports with the help of a counter. The content of the input port is rotated with carry until the carry bit is set. The contents of the counter is then compared and displayed in the display. This display is designed using a seven segment display and a BCD to seven segment decoder IC 7447. The BCD equivalent number of counter is sent through output part of 8051 displays the number of pressed key.
Circuit diagram of INTERFACING KEY BOARD TO 8051. The programming algorithm, program and the circuit diagram is as follows. Here program is explained with comments.
Circuit diagram of INTERFACING KEY BOARD TO 8051. Keyboard is organized in a matrix of rows and columns as shown in the figure. The microcontroller accesses both rows and columns through the port. 1. The 8051 has 4 I/O ports P0 to P3 each with 8 I/O pins, P0.0 to P0.7,P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7. The one of the port P1 (it understood that P1 means P1.0 to P1.7) as an I/P port for microcontroller 8051, port P0 as an O/P port of microcontroller 8051 and port P2 is used for displaying the number of pressed key. 2. Make all rows of port P0 high so that it gives high signal when key is pressed. 3. See if any key is pressed by scanning the port P1 by checking all columns for non zero condition. 4. If any key is pressed, to identify which key is pressed make one row high at a time. 5. Initiate a counter to hold the count so that each key is counted. 6. Check port P1 for nonzero condition. If any nonzero number is there in [accumulator], start column scanning by following step 9. 7. Otherwise make next row high in port P1. 8. Add a count of 08h to the counter to move to the next row by repeating steps from step 6. 9. If any key pressed is found, the [accumulator] content is rotated right through the carry until carry bit sets, while doing this increment the count in the counter till carry is found. 10. Move the content in the counter to display in data field or to memory location 11. To repeat the procedures go to step 2.
#0fh mov p1.r4 rl a mov r4.a mov a.initiating counter .p2 jz press .p2 jnz colscan mov a.a press: mov a.repeat for check next key.#00h mov p1.#01h mov r4.making one row high at a time .jump to check next row next: after identifying the row to check the colomn following steps are followed colscan: in: mov r5.r3 add a.increment counter by 08 count .making all rows of port p1 zero .#00h rrc a jc out inc r3 jmp in mov a.taking input from port A .r3 da a mov p2.a mov a.check until any key is pressed after making sure that any key is pressed mov a.decimal adjust the contents of counter before display .make one row high at a time .jump on getting carry .Program to interface matrix keyboard to microcontroller 8051 Start of main program: to check that whether any key is pressed start: mov a.a mov a.rotate right with carry until get the carry .making all rows of port p1 high .rotate left to check next row .increment one count .a mov r3. . 2009.a jmp start .a sjmp next .after getting the row jump to check column . out: Interfacing 7-segment display using 7447 decoder by Ranjith | August 17th.#00h mov a.#08h mov r3.r4 mov p1.
) with a common electrode. Common Anode (CA) The common leg for all the cathode is of Anode type. For the discussion purpose. Seven-segment displays contains the arrangement of the LEDs in “Eight” (8) passion. we can control the Port Output. Pin configuration of a seven segment display: LED’s are basically of two types: 1. Of course. Using lookup table. This uses 7 output pins of microcontroller 2. 0Volts will be considered as Binary 0. Here is the block diagram of the Seven Segment LED arrangement.The Light Emitting Diode (LED). and 5Volts will be considered as Binary1. all the 8 legs (’a’ through ‘h’) are of anode type and the common cathode will be connected to the GND of the supply. Using 7447 decoder. Considering these two condition. The purpose of arranging it in that passion is that we can make any number out of that by switching ON and OFF the particular LED’s. In the microprocessor binary system. and a Dot (. This method uses 4 output pins of microcontroller . Common Cathode (CC) All the 8 anode legs uses only one cathode. finds its place in many applications in this modern electronic fields. we use CC LED. By energizing any of the legs with +5 Volts will lead to switch the correspondent segment ON. we can make an arrangement as the microcontroller gives OUT the 0s and 1s through its ports. which is common. lead (Anode or Cathode). In a CC LED. 1. 2. where by just reversing the logical voltages we can implement the same for CA LED also. which is connected to the 8 legs of the LED. One of them is the Seven Segment Display. There 2 methods of interfacing LED with the Microcontroller Intel 8051/8951. implicitly we can Switch-ON required legs of the display.
we send the BCD of the number that we wanted to display to a middleware IC 7447. But. the first figure is interfacing the CA LED where as the second is of CC LED. Here in this case. in the second case. Circuit diagram for interfacing Common Anode 7-Segment Display . The number required to display is sent as the lower nibble of the Port 2 of the Microcontroller. The 7447 converts the four input bits (BCD) to their corresponding 7-segment codes. in the 1st case. We connect first four pins of the microcontroller Port 2 to the 7447 and the Output 8 pins of 7447 to the 8 legs of the LED as shown in the figure. the IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment code. Te circuit diagrams are shown below. we connect all the 8 pins of the port directly to the LED and control the voltage through the ports manually to display the desired number. the BCD to LED code converter. microcontroller communicates with external world through its ports. which by itself gives out the correspondent 7 segment codes to the LED. In both the cases. But. Click here for the method “using 7447 decoder” Using 7447 decoder: The IC7447 is a BCD to 7-segment pattern converter.The difference between the two main methods is simple and clear. Here we explain using lookup table. The outputs of the 7447 are connected to the 7-segment display. This setup is the advanced form of the <previous> setup where we entered the patterns manually to display the desired character.
One of them is the Seven Segment Display.#00h up: mov p2.D djnz r3. 2009.#255 D1: mov r1.) with a common electrode. Here is the block diagram of the Seven Segment LED arrangement. Start form zero . finds its place in many applications in this modern electronic fields.#0ah. The Light Emitting Diode (LED).D1 inc a cjne a. The purpose of arranging it in that passion is that we can make any number out of that by switching ON and OFF the particular LED’s. Delay Interfacing 7-segment display using 7447 decoder by Ranjith | August 17th.up sjmp again .#255 D: djnz r1. Seven-segment displays contains the arrangement of the LEDs in “Eight” (8) passion. lead (Anode or Cathode). a mov r3. and a Dot (.Circuit diagram for Common Cathode 7-Segment Display Program: This program displays characters 0 through 9 on seven-segment display using IC 7447 as the middle wear. again: mov a. . Move to Port 2 .
we can make an arrangement as the microcontroller gives OUT the 0s and 1s through its ports. we can control the Port Output. the BCD to LED code converter. But. This method uses 4 output pins of microcontroller The difference between the two main methods is simple and clear. For the discussion purpose. Common Anode (CA) The common leg for all the cathode is of Anode type. By energizing any of the legs with +5 Volts will lead to switch the correspondent segment ON. In the microprocessor binary system. all the 8 legs (’a’ through ‘h’) are of anode type and the common cathode will be connected to the GND of the supply. In a CC LED. . Using 7447 decoder. 1. in the 1st case. in the second case.Pin configuration of a seven segment display: LED’s are basically of two types: 1. which by itself gives out the correspondent 7 segment codes to the LED. we send the BCD of the number that we wanted to display to a middleware IC 7447. Common Cathode (CC) All the 8 anode legs uses only one cathode. we use CC LED. we connect all the 8 pins of the port directly to the LED and control the voltage through the ports manually to display the desired number. microcontroller communicates with external world through its ports. Considering these two condition. and 5Volts will be considered as Binary1. which is connected to the 8 legs of the LED. In both the cases. 2. This uses 7 output pins of microcontroller 2. Of course. which is common. 0Volts will be considered as Binary 0. There 2 methods of interfacing LED with the Microcontroller Intel 8051/8951. Using lookup table. implicitly we can Switch-ON required legs of the display. But. where by just reversing the logical voltages we can implement the same for CA LED also.
Click here for the method “using 7447 decoder” Using 7447 decoder: The IC7447 is a BCD to 7-segment pattern converter. We connect first four pins of the microcontroller Port 2 to the 7447 and the Output 8 pins of 7447 to the 8 legs of the LED as shown in the figure. This setup is the advanced form of the <previous> setup where we entered the patterns manually to display the desired character.Here we explain using lookup table. The number required to display is sent as the lower nibble of the Port 2 of the Microcontroller. Te circuit diagrams are shown below. Here in this case. the first figure is interfacing the CA LED where as the second is of CC LED. Circuit diagram for interfacing Common Anode 7-Segment Display . The 7447 converts the four input bits (BCD) to their corresponding 7-segment codes. the IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment code. The outputs of the 7447 are connected to the 7-segment display.
ADC .#00h up: mov p2. Start form zero .up sjmp again . again: mov a.D djnz r3. a mov r3. Move to Port 2 .#255 D1: mov r1.Circuit diagram for Common Cathode 7-Segment Display Program: This program displays characters 0 through 9 on seven-segment display using IC 7447 as the middle wear.#255 D: djnz r1.pressure . ANALOG DIGITAL TO CONVERTER . Therefore we need to convert these analog signals in to digital so that 8051 can read it.humidity are analog.#0ah.velocity .D1 inc a cjne a.Most transducers and sensors such as temperature . Delay ADC-DAC Interfacing Analog signals are very common inputs to embedded systems .
1RC R=10K and C=150pF f=606Hz the conversion time is 110us.28 0.5) 2.5 Vin (Volts) 0 to 5 0 to 5.56 1. L-H pulse edge triggered • INTR -.90 for Vin = 2x Vref/2. Vin=Vin(+) – Vin (-) • Range = 0 to 2x Vref/2.56 0 to 1 Input Voltage range • Default 0-5V. Vref/2 (Volts) Open (2. However. Can be changed by setting different value for Vref/2 pin. (Refer Table) •Step Size a Smallest change – (2 x Vref/2)/ 256 for ADC804 for eg for step size 10mv . active low • RD – Read Digital data from ADC.Start conversion.D0-D7 • CLK IN & CLK R – CLK IN is an input pin connected to an external clock source when an external clock is used for timing. ADC804 has an internal clock generator. To use the internal clock generator of the ADC804. the clock frequency is determined by the equation.53 5. f = 1/1. Data Out Dout = Vin / Step Size .56/256 = 10 1/256=3. In that case.12 0 to 2. we get 256 as a digital output on D0-D7.Commonly used ADC device – ADC804 ABOUT IC PinOut • CS – Chip Select . Goes low to indicate conversion done • Data bits -. the CLK IN and CLK R pins are connected to a capacitor and a resistor. H-L edge triggered • WR -. Step size (mV) 5/256 = 19.12/256 =20 2.end of conversion.digital output on D0-D7 changes by one count for every 10mv change of the input analog voltage.
• Keep monitoring INTR – If INTR =0. Algorithm • Make CS=0 and send a low-to-high to pin WR to start the conversion. WR of the ADC804 to the 8051 system (ensure polarity) – Connect CS of ADC804 to an appropriate address decoder output – Connect INTR of ADC804 to an external interrupt Pin on the 8051 (INT0 or INT1) IO Mapping (easiest . the conversion is finished and we can go to the next step.for input vtg.28 volts) and stepsize of 10mv Dout =2560/10 =256 or FF that is full scale output. INTR to some port bits on the 8051 (12 in all). WR. INTR. Conversion Time Greater than 110us for ADC804 Resolution 8 bits for ADC804 INTERFACING ADC804 TO 8051 Signals to be interfaced (on the ADC804) – D0-D7. CS Can do both Memory mapping and IO mapping Memory Mapping (timing is critical) – Connect D0-D7 of ADC804 to the data bus of the 8051 system – Connect RD. of 2. . CS. RD. RD.56 volts (Vref=1. WR.I prefer ) – Connect D0-D7.
WR=0 setb P3.wait for INTR clr p3. WAIT .WR=1.– If INTR=1.generate cs to ADC clr P3. #0xff .5 .Chip select setb P3.6 .5 .7 .7 .read digital o/p sjmp AGAIN INTERFACING ADC804 TO 8051 ADC808/809 Chip with 8 analog channel. we make CS=0 and send a high-to-low pulse to RD to get the data out of the ADC804 chip. • ADC804 has only ONE analog input: Vin(+).4.6 . P1 . keep polling until it goes low. This means this kind of chip allows to monitor 8 different transducers.RD=0 -High to low transition mov A.low to high transition WAIT: jb P3.RD=1 clr P3. To configure as input AGAIN clr p3. • After INTR=0. • ALE: Latch in the address • Start : Start of conversion (same as WR in 804) • OE: output enable (same as RD in 804) • EOC: End of Conversion (same as INTR in 804) . ASSEMBLY LANGUEGE (A51) ADC_IO: mov P1.
) • Select an analog channel by provide bits to A. you can use circuit like • Monitor EOC Pin . • Activate SC with a high-to-low pulse (start conversion) The conversion is begun on the falling edge of the start conversion pulse. • Activate OE with a high-to-low pulse to read data out of the ADC chip.Channel IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 CBA 000 001 010 011 100 101 110 111 Algorithm Notice that the ADC808/809 that there is no self-clocking and the clock must be provided from an external source to the CLK pin.After conversion this pin goes high. • Enable clock • Activate ALE with a low-to-high pulse. (you can use programmable clock oscillator to enable or disable clock by programmable bit. . B. C.
Vee Usage: – Just write a byte to the IO port and the DAC converts it to an analog value Some 8051 clones have ADCs and DACs in built PROGRAM TO INTERFACE ADC .and V+ to GND) PinOut – D0-D7 à Connected to the Processor’s IO port – Vref+.DIGITAL TO ANALOG CONVERTER . Vref-.DAC Commonly used DAC808 (MC1408) – R/2R ladder – Iout = Iref (D7/2 + D6/4 + D5/8 + …… + D0/256) – Iout converted to voltage by a resistive load or op-amp based isolator (Rf from Vout to V.
The ADC804 is an analog to digital converter. when CS = 0 and a low-to-high pulse is applied to WR pin. Pin description is as follows: CS : Chip Select: It is an active low input used to activate the ADC804 IC. The ADC converts the analog input to its binary equivalent and holds in an internal register. ADC starts converting analog input to digital. When a CS = 0 and high-to-low pulse is applied to the RD pin. To activate ADC804. then 8-bit digital output is available at the D0-D7 data pins. Resolution of this IC is 8 bits and works with +5V. The amount it takes to convert varies depending on the CLK IN and CLK R values. the INTR pin is forced low by the ADC804. RD : Read: It is an active low input used to get the converted data out of the ADC chip. this pin must be low. When the data conversion is complete. If input voltage 5V then converted digital output is FF. WR : Write: This is an active low input used to inform the ADC to start the conversion process. . which converts analog voltage to its digital equivalent.
4 setb p3.#99h jc L3v mov P3. check whether i/p is greater than 4V .5. jump if input is less than 3V .#80h mov p2. In this program if input voltage accedes certain range then 8255 sets corresponding bits mov a. send high signal to 4th line .4 and P3.here3 mov a. Analog input is applied to pin 6 of ADC.5 respectively.a mov r6.#66h jc L2v . check whether i/p is greater than 2V .a subb a.Here ADC 0804 is connected to port1 of 8051. low to high signal to WR.4 here3: jb p3.#ffh start: clr p3. configuring port 2 as i/p .#cch jc L4v mov P3. send high signal to 5th line .WR and INTR of ADC is connected to P3. check whether conversion is over.r5 subb a. jump if input is less than 2V .r5 subb a. start of conversion .p2 mov r5.#10h jmp last L4v: mov a. pin-INTR . Here WR is the start of conversion and INTR is the end of conversion.#08h jmp last L3v: mov a. check whether i/p is greater than 3V . jump if input is less than 4V .
send high signal to 3rd line .#0ffh here: djnz r1.here mov r2. we always used busy waiting.initialize timer 0 as 8-bit auto-reload timer MOV TH0. the CPU is busy testing the bit while waiting for its value to change. The CPU would sit in a loop.r5 subb a.#04h jmp last L2v: mov a.set timer 0 high-byte to produce 50us delay (assuming system clock frequency of 12MHz) SETB TR0 .if timer 0 overflow bit is not set.end . if it was the serial port transmit interrupt bit it announced the complete transmission of a byte.#33h jc L1v mov P3#02h jmp last L1v: mov a. check whether i/p is greater than 1V . Below is a program for generating a pulse train of 10KHz on port 1 pin 0. The setting of the bit announced an event.#0ffh here1: djnz r2. In the line JNB TF0.0 . repeat this instruction CLR TF0 . MOV TMOD. If it was a timer overflow bit it announced the timer's overflow to zero. All of these are . testing a bit (the timer overflow bit.testing the overflow bit of timer 0 and waiting for it to change to 1. the data received bit. #02H .r5 mov P3.here1 jmp start .mov P3.#01h last: mov r1. send high signal to 2nd line . waitForOverflow . jump if input is less than 1V . In other words. when we wrote programs to exercise the timers and the serial port. #0CEH . send high signal to 1st line Related source codes : Interrupts Revision of Timers In an earlier section we looked at the 8051 timers and how we could use them to generate a pulse train of a particular frequency on a port pin (for example). if it was the serial port receive interrupt bit it announced the arrival of an entire byte of data.invert (complement) port 1 pin 0 JMP waitForOverflow Busy Waiting The above program implements what is known as busy waiting.start timer 0 waitForOverflow: JNB TF0.reset timer 0 overflow bit CPL P1. Last year. waitForOverflow the CPU is continuously executing the same instruction . the data transmitted bit) waiting for it to be set.
another event may occur and be missed because the CPU was not in its busy waiting loop). This form of CPU sharing is known as round robin scheduling and we will talk about it more when we deal with the section on real-time operating systems. they are all sharing the CPU. the process has the CPU. However. 2. busy waiting becomes almost impossible to implement. since there is only one processor in the computer (in most cases) then this cannot be the case.step through the program and at each point it can be determined what the next instruction to be executed will be. A computer may be running many applications at the same time. The operating system uses a hardware timer to generate this interrupt. The OS hands the CPU over to the next process in the list (ie. say a word processor. The answer is an interrupt. The interrupt is generated by the hardware. Relatively easy to test . Continuous CPU operation is heavy on power consumption . 4. If more than one event needs to be tracked busy waiting becomes difficult to implement (need to test more than one bit in the busy waiting loop and deal with whichever event occurs. The OS is now no longer running. In reality. While dealing with this event. The operating system (OS) hands the CPU to one process (in OS terms. The OS starts the timer. The running process is interrupted after its allotted CPU time has elapsed and the operating system takes the CPU so that it can then hand the CPU over to the next process. Modern operating systems use interrupts to produce the illusion of a multiprocessor computer. a CD player and a web server. continuously testing the appropriate bit and waiting for it to be set. . The CPU waits for these events.not good for battery operated devices. Interrupts An interrupt is the occurrence of an event that causes a temporary suspension of a program while the event is serviced by a section of code known as the interrupt service routine. and so on until it gets back to the initial process. 3. How is one process stopped so that another can get the CPU? After all. an programs or applications are known as processes) for a set amount of time (perhaps milliseconds) and then hands it over to the next process for a set amount of time. The OS initializes the timer to count for a specified time. Disadvantages of busy waiting: • • • • The CPU is tied up with a mundane task when it could be off doing something more useful. All of the applications think they have sole access to the CPU. The timer overflows and generates an interrupt. the list of processes that are waiting to use the CPU).events. therefore the operating system itself is not running and therefore it cannot stop the running process. Advantages of busy waiting: • • Easy to implement. The sequence is as follows: 1. If some events have higher priorities than others and must be dealt with before lower priority events.
1 When an interrupt occurs the following happens: . • • • Two external interrupts are provided through pins INTO-bar and INT1-bar. when you press a key on your mobile phone. regardless of what it was doing in its main program. Interrupt Flag Location External 0 IE0 TCON.7 Serial Port Receive RI SCON. which are the alternate functions of port 3 pin 2 and port 3 pin 3.5 Timer 1 TF1 TCON.1 External 1 IE1 TCON. The interrupt described in the OS above is an internal interrupt generated by a timer overflow. The interrupt flag bits are detailed below. respectively. The microcontroller is then forced to jump to the ISR. The serial port on the 8051 can generate an interrupt when a byte has been transmitted or when a byte is received. The ISR jumps to step 1 above. 6. Two internal interrupts are generated by timer 0 overflow and by timer 1 overflow. They are heavily used in embedded systems. Desktop operating systems are not the only software systems to make use of interrupts.0 Serial Port Transmit TI SCON.5. Interrupt events can internal or external. the keypad sends an interrupt signal to the microcontroller. The interrupt forces the program counter to jump to the interrupt service routine (ISR). The diagram below illustrates a system program flow with interrupts. For example.3 Timer 0 TF0 TCON. An example of an external interrupt is a signal generated by a key press on a keypad. 8051 Interrupts The 8051 has five interrupt sources. Most systems deal with external events through interrupts.
When an interrupt in the 8051 occurs. Enabling and Disabling Interrupts As can be seen from the interrupt vector table above. TF0. Bit Symbol Description Number Enable/disable all interrupts. This address is known as the interrupt vector. reset is similar to powering down and the powering up the system. The table below details the interrupt vectors for the 8051. For example. as detailed below. as shown above. Not much room for the ISRs When you examine the vector table above you will notice there are only eight memory locations between the vectors. Interrupt Flag Vector System reset RST 0000H External interrupt 0 IE0 0003H Timer 0 TF0 000BH External interrupt 1 IE1 0013H Timer 1 TF1 001BH Serial port RI or TI 0023H A system reset is a special type of interrupt. Therefore. This is the address the microcontroller begins with on power-up. At location 001BH we put a jump to somewhere else in code memory and at this point we put our timer 1 ISR. To enable interrupts we set the appropriate bits in the interrupt enable SFR. For example. is loaded into the PC. cannot take up more than eight memory locations because it would then take up the space reserved for the serial port ISR. For example. On power-up or reset all interrupts are disabled. if timer 1 overflows (and interrupts are enabled. the timer interrupt flags are TF0 and TF1 and the serial interrupt flags are RI and TI. why didn't the timer overflowing (setting TF0) cause an interrupt? The answer is simple: we did not enable interrupts. The solution is simple. We used these flags during the second year of the course. The programmer must ensure the ISR for timer 1 is placed at this address. this is not a problem. if we need an ISR for dealing with timer 1 and we also need one for dealing with the serial port. we'll talk more about enabling and disabling interrupts shortly) the PC is loaded with the value 001BH. -6 -5 .• • • The current instruction completes execution. If this bit is cleared all interrupts are disabled. the address of the next instruction). If it is set each interrupt source EA 7 is individually enabled or disabled by setting or clearing the appropriate enable bit. If our ISRs are short. If this is the case. It interrupts the running program and loads the PC with the vector address 0000H. we waited for timer 0 to overflow by testing the state of the timer overflow flag. then the timer 1 ISR. the vector address. This register is detailed below. The address of the ISR for the interrupt is loaded into the PC. Interrupt Vectors When an interrupt occurs the address of the interrupt service routine is loaded into the PC. placed at location 001BH. The PC is saved on the stack (ie.
Take a look at the code below for an example. To ensure this.Enable/disable serial port interrupts (set to enable. clear EX1 2 to disable). Enable/disable timer 0 overflow interrupt (set to ET0 1 enable. . clear to disable). when entering a critical section. entering a critical section CLR EA . For example. It seems pointless to have to set it and then set the individual enable bit to enable an interrupt. to enable the timer 0 overflow interrupt we would write the following code: SETB EA SETB ET0 To disable an interrupt we simply clear the appropriate interrupt enable bit. the global enable bit is set (SETB EA). clear to disable). . clear to disable). For example. a critical section of code must be allowed to complete in entirety without being interrupted. whatever interrupts were enabled prior to entering the critical section are again enabled when the critical section has been complete. To enable an interrupt we must set the EA bit and then set the appropriate interrupt enable bit. Enable/disable timer 1 overflow interrupt (set to ET1 3 enable.enable timer 0 interrupt SETB EX1 . In other words.enable all interrupts SETB ET0 . Enable/disable external 0 interrupt (set to enable. Enable/disable external 1 interrupt (set to enable. . In this way. execute critical section code SETB EA .enable external 1 interrupt (remaining 3 interrupt sources remain disabled) . when leaving the critical section. interrupts ET0 and EX1 are again enabled (remaining 3 interrupt sources remain disabled) ES 4 . to disable the timer 0 overflow interrupt: CLR ET0 Why is there a global enable bit (EA)? You may be curious as to why the EA bit exists at all. all interrupts are disabled (CLR EA). There are sections of code known as critical sections (we will deal with these when we discuss operating systems in the Embedded Software class) that must not be interrupted. However.disable interrupts . clear EX0 0 to disable). there is a very good reason for having the EA bit. SETB EA . exit critical section . Then.
To set an interrupt to high priority we set the appropriate bit in the interrupt priority (IP) SFR. On reset. therefore re-enabling whichever interrupts had been enabled in the first place.) The 8051 has a definite polling sequence that deals with simultaneous interrupts. He/she simply disables all interrupts at the start of the critical section and then sets the global enable bit on exiting the critical section. Therefore.for now take it that all interrupts have the same priority. some events are more important than others. but some microcontrollers/microprocessors have more than two levels. Let's also imagine a user presses a key on the keypad and opens the oven door at the same time. If we imagine for a moment a microcontroller that has eight priority levels 0 to 7. external 1 will be serviced before timer 1. heating food). Each interrupt is serviced in the following order: External 0 followed by Timer 0 Overflow followed by External 1 followed by Timer 1 Overflow followed by the Serial Port. In this . Therefore. External interrupt 1 PX1 2 priority level. For example. Bit Symbol Description Number -7 -6 -5 Serial port interrupt PS 4 priority level. An interrupt service routine (ISR) can itself be interrupted. The 8051 has only two priority levels. microcontrollers are designed so that interrupts can be prioritized. External interrupt 0 PX0 0 priority level.If we take the above code as an example. If a low priority interrupt is being serviced while a high priority interrupt occurs. The interrupt caused by opening the door is more important than the interrupt caused by the key press (when the oven door is opened the microwave must immediately shut down. imagine a microwave oven in operation (ie. all interrupts are set at the low priority. Polling Sequence What happens if two interrupts of the same priority occur at the same time? (We will deal with interrupt priority in a moment . Once the high priority ISR completes execution begins again at the next instruction in the low priority ISR. as detailed below. 0 and 1. with 7 as the highest priority. The 8051 has only two interrupt priority levels. the programmer writing the critical section code doesn't need to know which interrupts are enabled. Interrupt Priority In most systems. Timer 1 interrupt priority PT1 3 level. the low priority ISR is interrupted (in exactly the same way as the main program is interrupted) and the high priority interrupt is serviced. if for example an interrupt occurs on timer 1 and external 1 at the same time. regardless of what's being pressed on the keypad) and it should be serviced first. with 1 being the high priority. An ISR cannot be interrupted by an interrupt of the same or lower priority. Timer 0 interrupt priority PT0 1 level.
A 10KHz signal has a cycle of 100us. #02H . do nothing but wait for interrupt The code in boldface is the ISR. to generate a 7KHz pulse train on P1. They simply tell the assembler where in code memory to place the following section of code. Servicing More Than One Interrupt Let's say we wish to generate two pulse trains of differing frequencies. Therefore we need an interrupt to occur every 50us (pulse train of 50% duty cycle . Assuming a 12MHz system clock implies the timer will step once every 1us . They are not part of the 8051 code. invert port 1 pin 0 RETI . the PC is loaded with 0 and the first instruction executed is that stored at location 0. For example.50) 206 to overflow.case a level 5 ISR (for example) can only be interrupted by interrupts at levels 6 and 7.6. The reset vector for the 8051 is 0. reset vector JMP main . This is the timer 0 interrupt vector. Therefore. jump above interrupt vectors ORG 000BH . start timer 0 SETB EA . The ORG 000BH directive causes the assembler to place the following piece of code (our timer 0 ISR) at location 000BH. To achieve this we will enable timer 0 overflow interrupt and set up timer 0 so that it overflows every 50us. timer 0 in 8-bit auto-reload timer mode MOV TH0. our first instruction (at location 0) is a jump to somewhere in code memory above the ISR vectors (in the above example we jump to 0030H). jump above interrupt vectors ORG 000BH . return from interrupt ORG 0030H .we need the timer to count from (256 . this is the address automatically placed in the PC (by hardware) when an interrupt occurs on timer 0 (and timer 0 interrupt is enabled). When timer 0 overflows (every 50us) the following occurs: • • • • PC is saved on the stack PC gets 000BH (interrupt vector for timer 0) Execution begins in ISR (in this case it simply inverts P1. we could use the following code: ORG 0 . reset vector JMP main . 50us at 0). ie. put 206 decimal into TH0 SETB TR0 . when the 8051 powers up or is reset. global interrupt enable SETB ET0 . invert port 1 pin 7 . Some Examples Generating a 10KHz pulse train on port 1 pin 0 using interrupts.7 and a 500Hz pulse train on P1. ORG 0 . Therefore. main program entry point main: MOV TMOD.50us at 1.7 .execution beings again in the main program where it left off (in this case the JMP $ instruction) The ORG statements are assembler directives. We can do this with the 8-bit auto-reload mode. enable timer 0 interrupt JMP $ . timer 0 interrupt vector CPL P1. When using interrupts we do not want our main program to write over the area reserved for the ISRs. 0CEH .0 .0) RETI takes the PC off the stack . timer 0 interrupt vector CPL P1.
timer 1 in 16-bit mode MOV TH0. this requires the timer be initialized with the starting value (64536) each time it overflows.6 pin is not inverted exactly every 1ms (because a few microseconds are lost while servicing timer 0) then this is not very noticeable in the low frequency signal. enable timer 0 interrupt SETB ET1 . This could present a problem because the microseconds that .6) is inverted. initialize timer 1 with (65536 . the polling sequence says the interrupt on timer 0 will be serviced before timer 1.6 . force timer 1 interrupt SETB ET0 . timer 1 is put into 16-bit mode.1000) 64536 (FC18H SETB TR1 . timer 1 interrupt vector JMP timer1ISR . do nothing but wait for interrupt timer1ISR: CLR TR1 . if timer 1 is being serviced when timer 0 overflows. Then. This is to start the timer initially. This is acceptable in this situation because timer 0 is being used to generate the higher frequency signal. timer 0 in 8-bit auto-reload timer mode. main program entry point main: MOV TMOD. enable timer 1 interrupt SETB EA . This can be achieved using one of the timers in mode 2 (8-bit auto reload). start timer 0 SETB TF1 . Also note that timer 0 ISR is left at the reset vector since it is such a short ISR. the timer is first stopped in the ISR and the value FC18H is loaded. stop timer 1 MOV TH1. jump to timer 1 ISR ORG 0030H . #0FCH MOV TL1. What if both interrupts occur simultaneously? If it happens that both timer 0 and timer 1 overflow at the same time. start timer 1 CPL P1. However. Again. #18H . With a duty cycle of 50% the time delay required for generating the 7KHz pulse train is 71us. To achieve this. a timer 1 overflow interrupt will occur and the timer will be initialized again. However. A 500Hz pulse train has a cycle of 2ms. The code above uses timer 0 to generate the 7KHz pulse train on P1. However. return from interrupt ORG 001BH .RETI . If the P1. timer 0 will have to wait because both interrupt sources are at the same priority level (low level) and no ISR can be interrupted by an interrupt of the same priority. This is too long of a delay to be achieved using the 8-bit auto reload mode. 1ms later. Notice in the main program a timer 1 interrupt is forced through software. #0B9H . the timer started again and the pin (P1. timer 1 ISR is moved elsewhere in code memory (after the main program in this example) and a jump to the ISR is placed at timer 1's reset vector. put (256 . since there are only 8 bytes between each vector. global interrupt enable JMP $ .71) 185 decimal into TH0 SETB TR0 . invent port 1 pin 6 RETI A 7KHz pulse train has a cycle of 143us. with a duty cycle of 50% this results in a time delay of 1ms (1000us).7. Therefore. #12H . Once the interrupts are enabled execution will jump to the timer 1 ISR and the timer is initialized and started.
while at the same time the higher frequency signal on P1. the main program should be altered as shown below: main: MOV TMOD. force timer 1 interrupt SETB PT0 .71) 185 decimal into TH0 SETB TR0 . Therefore. serial port interrupt vector JMP serialPortISR .are lost while servicing timer 1 would be noticeable in the higher frequency signal on P1. This program will loop indefinitely. Timer 0 ISR is very short (just invert P1.TI and RI. at address 0023H. main program entry point . global interrupt enable JMP $ . timer 1 ISR will be suspended and timer 0 will be serviced. In other words. timer 1 in 16-bit mode MOV TH0. when an overflow occurs the hardware automatically resets the interrupt flag. put (256 . Serial Port Interrupts There is only one serial port interrupt vector in the 8051.7 is kept accurate. • • TI is set by hardware when an entire character has been transmitted from SBUF down the serial line. A Baud rate of 9600 with a system clock frequency of 12MHz is generated (see notes on the 8051 serial port for more information on setting the serial port Baud rate). if timer 1 is being serviced and an overflow occurs on timer 0. enable timer 0 interrupt SETB ET1 . #12H . enable timer 1 interrupt SETB EA . start timer 0 SETB TF1 . do nothing but wait for interrupt Timer 0 is set to high priority. The serial port flags are not automatically cleared when vectoring to the ISR. starting with the space character (20H) and progressing through the set to the last character (7EH) and back to the start again. if the timer's interrupt is enabled. RI is set by hardware when an entire character has been received on the serial line and is waiting in SBUF to be read by the program. As we saw when dealing with interrupts on the timers. the ISR must first check to see which of the two flags actually caused the interrupt and then clear this interrupt flag. It is very important to note that this is NOT the case with the serial port interrupt flags. set timer 0 overflow to high priority interrupt SETB ET0 . not the hardware.7 and return) so the time lost there will not be noticed on the P1. the serial port ISR must first check to see which source caused the interrupt. Since the same vector is used for both TI and RI. 0B9H . the timer overflow flag is cleared by hardware when the CPU vectors to the interrupt vector address. However.6 signal. Repeatedly Sending the ASCII Character Set on the Serial Line The program below shows how to send the ASCII character set (excluding the control characters) down the serial line. ORG 0 JMP main ORG 0023H . Since the serial port can be used to transmit and receive data at the same time. there are two serial port interrupt sources . Therefore. jump to serial port ISR ORG 0030H . Clearing the serial port interrupt flags is the responsibility of the software.7. timer 0 in 8-bit auto-reload timer mode.
start timer 1 CLR SM0 SETB SM1 . Therefore. testTI . If so it jumps to the subroutine for dealing with this case. Transmitting and Receiving on the Serial Port If our system transmits and receives data on the serial port at the same time then we need to first check to see which flag (TI or RI) actually caused the interrupt. our serial port ISR does not need to test to see whether the interrupt was caused by TI or RI. if TI is not set jump to end CLR TI . and call subroutine that deals with an entire byte sent (most likely to send another byte) endSerialPortISR: RETI In the above ISR. when a serial port interrupt occurs we know it has been caused by the transmission of an entire byte. timer 1 in 8-bit auto-reload timer mode MOV TH1. It is important to test RI before testing TI. if TI is set clear it CALL dataSent . #20H . the ISR must test TI even if it found RI was set. after first clearing RI. RI is tested to see if the interrupt was caused by a received byte. . if A contains 7FH replace it with the start of the sequence (20H the space character) skip:MOV SBUF. global interrupt enable JMP $ . if A does not contain 7FH (the end of the ASCII sequence) skip next line MOV A. endSerialPortISR . If TI is set it jumps to the subroutine for dealing with this case. do nothing but wait for interrupt serialPortISR: CJNE A. serialPortISR: JNB RI. It then checks to see if TI is set. since we are only transmitting data. #20H . skip . high byte value to generate baud rate of 9600 SETB TR1 . send character to serial port INC A . Take note. #7FH. if RI is set clear it CALL dataReceived . If RI is set then we must deal with this received byte as soon as possible because another byte may be on the way. A . if RI is not set jump to testing TI CLR RI .main: MOV TMOD. send ASCII space character first by initializing A to 20H SETB ES . increment to next character in ASCII sequence CLR TI . Therefore. a byte may have been sent at the same time as a byte was received and therefore both RI and TI may be set together. and call subroutine for dealing with received byte testTI: JNB TI. after first clearing TI. clearing SM0 and setting SM1 puts serial port into mode 1 SETB TI . enable serial port interrupts SETB EA . It simply transmits the next character and then clears TI. #20H . force serial port transmit interrupt MOV A. clear the transmit interrupt flag RETI In the above example. A typical serial port ISR for dealing with this is shown below. 0FDH .
2 while INT1-bar is at P3.0. As stated above. Similarly.3). all 8051 port pins are at logic 1. The output value is controlled via P1. There is some process. If the external interrupt is set to edge activation then the external source must ensure the pin is kept high for one complete machine cycle and then low for one complete machine cycle. the external source (the peripheral. that causes the interrupt) must ensure the interrupt pin is kept low for at least one machine cycle. the interrupt may be caused by either a low-level or a negative edge on the INTx-bar pin. External Interrupts External interrupts occur as a result of a low-level or negative edge on the INT0-bar or INT1-bar pins on the 8051 (INT0-bar is at P3. Whenever the . a level sensor connected to the external 0 interrupt (INT0) produces a logic 0 when the liquid is lower than min (green line). For example. both valves will initially be closed. the CPU will see a negative edge on the interrupt pin and set the flag accordingly (IE0 or IE1). A liquid level sensor is connected to the external 1 interrupt (INT1). a logic 0 on this port pin opens the valve while a logic 1 cloeses it. The input value is similarly controlled via P1. In this way. such as a keypad. If the interrupts are level activated. Controlling the Level of Liquid in a Tank The diagram below shows a tank interfaced (via suitable electronic circuitry) to the 8051.whereas it is less critical if some time is lost between transmitting bytes. With the basic 8051 running at 12MHz the machine cycle is 1us. controlled by the 8051. a logic 0 opens the valve while a logic 1 closes it. The flags that generate these interrupts are IE0 and IE1 in the TCON register. that makes use of the liquid in this tank. tested) once every machine cycle. The choice of low-level activation or edge activation can be programmed through the IT0 and IT1 bits in the TCON register. This sensor produces a logic 0 when the liquid level is higher than max (red line). to set external interrupt 0 as low-level activated and external interrupt 1 as edge activated we could write the following: CLR IT0 SETB IT1 The external interrupt pins are sampled (ie. on reset.1. Since.
It should be noted that the choice of applying the min-liquid sensor to INT0-bar and the max-liquid sensor to INT1-bar is completely arbitrary. The external 0 ISR should then open the input value in order to start filling the tank. global interrupt enable JB P3. the INT0 line will go from HIGH to LOW: a negative edge. external interrupt 0 vector CLR P1.2) is at logic 1.2. because the temperature is too low).2) is logic 1 then the liquid level is above min. if P3. continue with main program (the process that makes use of the liquid in the tank) The ISRs are very simple. When the liquid in the tank drops below the minimum level.1 . However. .1 . therefore the ISR at vector 0003H simply opens the input valve. for this example of the use of external interrupts. therefore skip next instruction CLR P1. The main program performs the initialization.0. as long as we also swapped the ISRs. close input valve RETI ORG 0030H main: SETB IT0 . We simply wish to write the code for handling the two interrupts. if INT0-bar is logic 0 the liquid level is below min.0 is cleared and when enough liquid has been taken from the tank the output valve is closed by setting P1. this process is of no concern to us. ORG 0 JMP main ORG 0003H . external interrupt 1 vector SETB P1. skip . therefore turn open input valve skip: . if the liquid level is already too low we will never see a negative edge on INT0-bar (it is already at 0. The external 1 ISR should then close the input value in order to stop filling the tank. An external 0 interrupt occurs when the liquid level is too low. However. and will remain at 0.1 . open input valve RETI ORG 0013H . the INT1 line will go from HIGH to LOW: a negative edge.. An external 1 interrupt occurs when the liquid level is too high. if INT0-bar (P3. enable external interrupt 0 SETB EX1 . set external interrupt 1 as edge activated SETB EX0 . . enable external interrupt 1 SETB EA . We therefore need to check to see if INT0-bar (which is at P3. the system would work exactly the same if we swapped the sensors from one external interrupt pin to the other. When the level in the tank reaches the maximum. However..process requires liquid from the tank. set external interrupt 0 as edge activated SETB IT1 . P1.3 is 0 then we must open the input valve and then proceed with the main program. therefore the ISR at vector 0013H simply closes the input valve. If it is logic 1 it means the liquid level is not too low and we can jump to the end of the initialization.
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