UNITED

STATES PATENT AND TRADEMARK

OFFICE
Address: COMMISSIONER

United States Patent and Trademark
P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspta.gov

UNITED

STATES

DEPARTMENT

OF COMMERCE

FOR PATENTS

Office

APPLICATION

NO.

FILING DATE

FIRST NAMED INVENTOR

ATTORNEY

DOCKET NO.

CONFIRMATION

NO.

95/001,160 26111 7590

·03/24/2009
03/20/2012

7210016

2805.001REX6
EXAMINER PElKARl, ART UNIT BEHZAD

2351

STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C. 1100 NEW YORK AVENUE, N.W. WASHINGTON, DC 20005

I.'

PAPER NUMBER

3992

MAIL DATE

DELIVERY

MODE

03/20/2012

PAPER

Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication.

PTOL-90A

(Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
Commissioner for Patents United States Patents and Trademark Office P.O.Box 1450 Alexandria, VA 22313-1450 www.uspto.gov

DO NOT USE IN PALM PRINTER
THIRD PARTY REQUESTER'S CORRESPONDENCE ADDRESS

Date:

MAILED
MAR 202012

HA YNES AND BOONE, LLP IP SECTION 2323 VICTORY AVENUE SUITE 700 DALLAS, TX 75219

CENTRAL. REEXAMINATION UNO"

Transmittal of Communication to Third Party Requester Inter Partes Reexamination
REEXAMINATION CONTROL NO. : 95001160 PATENT NO. : 7210016 TECHNOLOGY CENTER: 3999 ART UNIT : 3992

Enclosed is a copy of the latest communication from the United States Patent and Trademark Office in the above identified Reexamination proceeding. 37 CFR 1.903. Prior to the filing of a Notice of Appeal, each time the patent owner responds to this communication, the third party requester of the inter partes reexamination may once file written comments within a period of 30 days from the date of service of the patent owner's response. This 30-day time period is statutory (35 U.S.c. 314(b)(2)), and, as such, it cannot be extended. See also 37 CFR 1.947. If an ex parte reexamination has been merged with the inter partes reexamination, no responsive submission by any ex parte third party requester is permitted. All correspondence relating to this inter partes reexamination proceeding should be directed to the Central Reexamination Unit at the mail, FAX,or hand-carry addresses given at the end of the communication enclosed with this transmittal.

PTOL-2070(Rev.07-04)

Control No.

Patent Under Reexamination

ACTION CLOSING PROSECUTION (37 CFR 1.949)
-- The MAILING DA TE of this communication

95/001,160
Examiner BEHZAD PEl KARl

7210016
Art Unit

3992
address. --

appears on the cover sheet with the correspondence

Responsive to the communication(s) filed by: Patent Owner on 03 November, 2011 Third Party(ies) on 01 December, 2011 Patent owner may once file a submission under 37 CFR 1,951 (a) within ~ month(s) from the mailing date of this Office action. Where a submission is filed, third party requester may file responsive comments under 37 CFR 1.951 (b) within 30-days (not extendable- 35 U.S.C. § 314(b)(2» from the date of service of the initial submission on the requester. Appeal cannot be taken from this action. Appeal can only be taken from a Right of Appeal Notice under 37 CFR 1.953. All correspondence relating to this inter partes reexamination proceeding should be directed to the Central Reexamination Unit at the mail, FAX, or hand-carry addresses given at the end of this Office action.

PART I. THE FOLLOWING

ATTACHMENT(S)

ARE PART OF THIS ACTION:

1. 0 Notice of References Cited by Examiner, PTO-892 2. 0 Information Disclosure Citation, PTO/SS/08 3.0 PART II. SUMMARY OF ACTION: 1b. 0 Claims __ 2. 3. 4. 5. 6. 7. 8 9 1a. [gI Claims 1-24 are subject to reexamination. are not subject to reexamination. have been canceled. are patentable. [Amended or new claims]

0 Claims

__ __

[gI Claims 5 and 6 are confirmed. [Unamended patent claims]

0 Claims

0 Claims __ are objected to. 0 The drawings filed on 0 are acceptable 0 are not acceptable. 0 The drawing correction request filed on __ is: D approved. D disapproved. 0 Acknowledgment is made of the claim for priority under 35 U.S.C. 119 (a)-(d). The certified

[gI Claims 1-4 and 7-24 are rejected.

o been received.
__

D not

been received.

D been

filed in Application/Control

copy has: No __

10.00ther

u.s. Patent and Trademark Office PTOL-2065 (08/06)

Paper No. 20120308

Transmittal of Communication to Third Party Requester Inter Partes Reexamination
-- The MAILING DA TE of this communication

Control No. 95/001,160 Examiner BEHZAD PEl KARl

Patent Under Reexamination 7210016 Art Unit

3992

appears on the cover sheet with the correspondence address. --

Enclosed is a copy of the latest communication from the United States Patent and Trademark Office in the above-identified reexamination proceeding. 37 CFR 1.903. Prior to the filing of a Notice of Appeal, each time the patent owner responds to this communication, the third party requester of the inter partes reexamination may once file written comments within a period of 30 days from the date of service of the patent owner's response. This 30-day time period is statutory (35 U.S.C. 314(b)(2)), and, as such, it cannot be extended. See also 37 CFR 1.947. If an ex parte reexamination has been merged with the inter partes reexamination, submission by any ex parte third party requester is permitted. no responsive

All correspondence relating to this inter partes reexamination proceeding should be directed to the Central Reexamination Unit at the mail, FAX, or hand-carry addresses given at the end of the communication enclosed with this transmittal.

U.S. Patent and Trademark Office PTOL-2070 (5/04)

Paper No.

20120308

Application/Control Art Unit: 3992

Number: 95/001,160

Page 2

DETAILED ACTION

Inter Partes Reexamination 1. This is an inter partes reexamination of U.S. Patent No. 7,210,016 ('016 patent). Claims

1-24 are subject to reexamination.

Prosecution Summary 2. The following is a brief summary of the prosecution to date in this reexamination

proceeding: • On December 15,2008, a Request for ex parte reexamination of claims 7, 13,21 and 22 of the '016 patent was filed by a third party requestor in 901009,357. • On January 16,2009, the USPTO mailed a decision granting ex parte reexamination and ordering the reexamination of claims 7, 13, 21 and 22 in 901009,357. • On March 24, 2009, a Request for inter partes reexamination of claims 1-24 of the '016 patent was filed by the third party requestor in 95/001,160. included a request to merge with 901009,357. • On May 8, 2009, the USPTO mailed a non-final Office action which rejected claims 7, 13,21 and 22 in 901009,357. Claims 7, 13,21 and 22 were rejected under 35 U.S.C. 102(b) as being clearly anticipated by Coteus. Claims 7, 13 and 21 were also subject to a double patenting rejection as being unpatentable over claims 7, 13 and 21 of U.S. Patent No. 7,177,998. The Request

Application/Control Art Unit: 3992 •

Number: 95/001,160

Page 3

On May 26,2009, the USPTO mailed a decision granting inter partes reexamination and ordering the reexamination of claims 1-24 in 95/001,160.

• •

On July 23, 2009, an interview was held to discuss the rejections in 90/009,357. On August 10,2009, patent owner filed a response to the non-final rejections in 90/009,357. The response included arguments and a declaration under 37 CFR

1.132. No amendments were filed. • On August 11, 2009, patent owner filed a terminal disclaimer to overcome the double patenting rejection in 90/009,357. • On December 16, 2009, a Decision Merging Proceedings was mailed, merging 95/001,160 and 90/009,357 into a single reexamination proceeding. • On March 30, 2010, a merged non-final Office action (later vacated) was mailed for the merged proceedings 95/001,160 and 90/009,357. • On June 1,2010, patent owner filed a response (later vacated) to the non-final rejections in the merged proceedings 95/001,160 and 90/009,357. • On July 1,2010, the third party requestor in 95/001,160 filed comments (later vacated) to the non-final rejections in the merged proceedings 95/001,160 and 90/009,357. • On September 30, 2010, in response to a petition filed by patent owner on January 20,2010, the merger of reexamination proceedings 95/001,160 and 90/009,357 was dissolved. The Office action mailed March 30, 2010, the patent owner

response filed June 1, 2010, and the third party comments filed July 1, 2010 were vacated.

Application/Control Art Unit: 3992 •

Number: 95/001,160

Page 4

On September 30, 2010, the USPTO issued a decision sua sponte to withdraw the determination that Coteus raised a SNQ with respect to claims 7, 13,21 and 22 of the '016 patent in the inter partes reexamination proceeding order.

On June 21, 2011, a non-final office action was mailed, rejecting claims 1-24, but erroneously including a rejection of claims 7, 13,21 and 22 as being taught by Coteus.

• •

On July 21, 2011, patent owner filed a response to the non-final Office action. On August 19, 2011, third party requester filed arguments in response to patent owner's remarks of July 21, 2011.

On October 3,2011, the USPTO mailed a corrected non-final Office action, rejecting rejected claims 1-4 and 7-24 and confirming claims 5 and 6.

On November 3, 2011, patent owner filed a response in which claim 21 was amended. The response included arguments and a declaration under 37 CFR

1.132 of Robert J. Murphy. • On December 1, 2011, the third party requester filed comments, including a declaration under 37 CFR 1.132 of Harvey Stiegler. • On February 8, 2012, the third party requester filed a notice of non-participation for the 95/001,160 proceeding. • On February 17,2012, the third party requester filed a notice to withdraw the comments filed December 1, 2011.

Application/Control Number: 95/001,160 Art Unit: 3992
References 3. The references discussed herein are as follows: (1) (2) U.S. Patent No. 6,292,903 to Coteus et al. ("Coteus") PCT Application W099/46687 to Hitachi, invented by Sato et al. ("Sato")

Page 5

(with some reference to counterpart (3) (4) (5) (6) (7)

us. Patent

6,359,815 to Sato)

U.S. Patent No. 5,615,358 to Vogley ("Vogley") U.S. Patent No. 5,819,076 to Jeddeloh et al ("Jeddeloh") U.S. Patent No. 6,211,703 to Takekuma et al. ("Takekuma") U.S. Patent No. 5,663,661 to Dillon et al. ("Dillon") Hyundai HY5DV651622 Data Sheet ("Hyundai").

Claim Rejections - Relevant Statutes 4. The following is a quotation of the appropriate paragraphs of35 U.S.C. 102 that form the

basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless (b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States. (e) the invention was described in (I) an application for patent, published under section I22(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351 (a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21 (2) of such treaty in the English language.

Application/Control Art Unit: 3992 5. The following

Number: 95/001,160

Page 6

IS

a quotation

of 35 U.S.C. 103(a) which

forms the basis for all

obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically in section 102 of this title, if the differences between the subject matter art are such that the subject matter as a whole would have been obvious to a person having ordinary skill in the art to which said subject matter negatived by the manner in which the invention was made. disclosed or described as set forth sought to be patented and the prior at the time the invention was made pertains. Patentability shall not be

Summary of Proposed Rejections and Status
6. The following rejections were proposed by the Request filed March 24, 2009: • Issue 1: claims 1,2,4,5,8, 14, 15, 18-20,23 and 24 are alleged to be anticipated

by Coteus under 35 U.S.C. § 102(e). The rejection of claims 19, 20 and 24 is adopted, with modifications to the rationale in support thereof. The proposed rejection of claims 1,2,4,5,8, • 14, 15, 18 and 23 is not adopted.

Issue 2: claims 7, 8, 13-15 and 18-23 are alleged to be anticipated by Sato under 35 U:s.C. § 102(b). The rejection of claims 7, 8,13-15 and 18-23 is adopted as proposed.

Issue 3: claims 9, 10, 12 and 16 are alleged to be rendered obvious by Sato in view of Jeddeloh under 35 U.S.C. § 103. The rejection of claims 9, 10, 12 and 16 is adopted, with modifications to the rationale in support thereof.

Application/Control Art Unit: 3992 •

Number: 95/001,160

Page 7

Issue 4: claims 11 and 17 are alleged to be rendered obvious by Sato in view of Jeddeloh further in view of Takekuma under 35 U.S.C. § 103. The rejection of claims 11 and 17 is adopted, with modifications to the rationale in support thereof.

Issue 5: claims 1,2,4,6-8,

13-15 and 18-24 are alleged to be rendered obvious by

Sato in view ofVogley under 35 U.S.C. § 103. The rejection of claims 1,2,4, 7, 8, 13-15 and 18-24 is adopted, with modifications to the rationale in support thereof. The proposed rejection of claim 6 is not adopted. • Issue 6: claims 3, 9, 10, 12 and 16 are alleged to be rendered obvious by Coteus in view of Jeddeloh under 35 U.S.C. § 103. The rejection of claims 3, 9, 10, 12 and 16 is not adopted. • Issue 7: claims 11 and 17 are alleged to be rendered obvious by Coteus in view of Jeddeloh and in further view of Takekuma under 35 U.S.C. § 103. The rejection of claims 11 and 17 is not adopted. • Issue 8: claims 4, 19 and 20 are alleged to be obvious by Coteus in view of Takekuma under 35 U.S.C. § 103. The rejection of claims 19 and 20 is adopted. The rejection of claim 4 is not adopted. • Issue 9: claims 3, 9, 10, 12 and 16 are alleged to be rendered obvious by Sato in view ofVogley and in further view of Jeddeloh under 35 U.S.C. § 103.

Application/Control Art Unit: 3992

Number: 95/001,160

Page 8

The rejection of claims 3, 9,10, 12 and 16 is adopted, with modifications to the rationale in support thereof. • Issue 10: claims 11 and 17 are alleged to be rendered obvious by Sato in view of Vogley and Jeddeloh and in further view of Takekuma under 35 U.S.C. § 103. The rejection of claims 11 and 17 is adopted, with modifications to the rationale in support thereof. • Issue 11: claim 4 is alleged to be rendered obvious by Sato in view of Vogley and further in view of Dillon and Hyundai under 35 U.S.C. § 103. The rejection of Claim 4 is adopted, with modifications to the rationale in support thereof.

Claim Interpretation
7. In the analysis provided in the Request and associated claim charts, the third party

requester makes several references to claim construction in a litigation proceeding to clarify the scope of the claims (see, for example, element 7.1a of Exhibit K). These references have been noted. During reexamination, however, the standards for claim interpretation set forth in the MPEP will apply. Note that the Patent and Trademark Office determines the scope of claims in patent applications not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction "in light of the specification as it would be interpreted by one of ordinary skill in the art." In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 [70 USPQ2d 1827] (Fed. Cir. 2004). Indeed, the rules of the PTO require that application claims must

Application/Control Art Unit: 3992

Number: 95/001,160

Page 9

"conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description." 37 CFR 1.75(d)( 1). Different standards of proof and claim interpretation are employed by the District Courts and the Office. See for example In re ZIetz, 893 F.2d 319, 322, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989). Thus, where a proposed rejection referencing claim construction has been adopted or adopted as modified below, the examiner has determined that the claim construction (I) is correct as written or (2) falls within the scope of a construction determined by the examiner.

Claim Rejections - Detailed Explanation Issue 1 Claims 1, 2, 4, 5, 8, 14, 15, 18-20, 23 and 24 are alleged to be anticipated by Coteus under 35

u.s.c. § 102(e).

8.

Claims 19,20 and 24 are rejected under 35 U.S.C. § 102(e) as being anticipated by

Coteus. The proposed rejection of this claim set forth in the Request is adopted, with modifications to the rationale in support thereof. See the Request pp. 11 and 13-22 and the claim chart in Exhibit J, which are hereby incorporated by reference. (1) With regard to claims 19, 20 and 24, the examiner disagrees with the analysis in

element lAb (see page 3 of Exhibit J) where it is stated that the first propagation time from the memory controller to the first DRAM Dl "must be shorter" than the propagation time from the

Application/Control Art Unit: 3992

Number: 95/001,160

Page 10

memory controller to the second DRAM Dn. The examiner agrees that the propagation times may be different, which is a critical feature of the claims, but it is noted that there is no restriction in Coteus on which one of the lines (to DRAM Dl or to Dn) has the shorter propagation time. The assertion that there is no restriction in Coteus on which one of the lines has the shorter propagation time applies to claim 19 (see element 19.4b of Exhibit J), claim 20 (dependent on claim 19) and claim 24 (see element 24.4b of Exhibit J). (2) With regard to claims 19 and 20, the examiner adds that the termination for the

first and second signal lines (see elements 4.1 and 4.2 of Exhibit J) and for the control signal path (see element 4.3 of Exhibit J) could also be taught by the ports where lines 104a, (N-l)a, and 102a, respectively, enter the DRAMs. (3) With regard to claim 20, the examiner adds that because the time delays 15a-15n

are optimized to enable the data to arrive at the memory during the enablement period triggered by the timing signal, this teaches the claimed "coincidentally". lines 6-28 and 46-62. Note, e.g., Coteus, column 17,

9.

The proposed rejection ofc1aims 1,2,4,5,8,14,15,18 (1)

and 23 is not adopted.

With regard to claims 1, 2,4, 5, 8, 14, 15 and 18, the arguments presented on

pages 17-19 of patent owner's response filed November 3,2011 are incorporated by reference herein .. (2) In addition, claim 5 recites, "a timing signal path coupled to the first memory

device and the second memory device, the timing signal path to carry a timing signal that

Application/Control Art Unit: 3992

Number: 95/001,160

Page 11

indicates a first time at which the write command propagating on the control signal path is sampled by the first memory device, and wherein the timing signal indicates a second time at which the write command propagating on the control signal path is sampled by the second memory device." The proposed rejection of claim 5 refers to passages in Coteus wherein the timing signal is used to trigger the loading of data into the memory devices. .

While it is agreed that some type of measurement must occur to determine the propagation times of the various lines, and some type of sampling must occur in the DRAM of Coteus, there is no explicit teaching in Coteus of a timing signal that indicates the time at which write commands propagating on the control signal path are sampled by the first and second memory devices. (3) With regard to claim 23, Coteus does not teach that the respective times when

each of the memory devices captures the write data are staggered in time.

Issue 2 Claims 7, 8, 13-15 and 18-23 are alleged to be anticipated by Sato under 35 Us.c. J02(b) .

§

. 10.

Claims 7, 8, 13-15 and 18-23 are rejected under 35 U.S.C. § 102(b) as being anticipated See the

by Sato. The proposed rejection of these claims set forth in the Request is adopted.

Request pp. 11 and 22-33 and the claim chart in Exhibit K, which are hereby incorporated by reference.

Application/Control Art Unit: 3992

Number: 95/001,160

Page 12

Issue 3
Claims 9, 10, 12 and 16 are alleged to be rendered obvious by Sato in view of Jeddeloh under 35

usc.

§ 103.

11.

Claim 9, 10, 12 and 16 is rejected under 35 U.S.C. § 103 as being unpatentable over Sato The proposed rejection ofthis claim set forth in the Request is adopted,

in view of leddeloh.

with modifications to the rationale in support thereof. See the Request pp. 11, 12 and 22-36 and the claim chart in Exhibit K, which are hereby incorporated by reference. With regard to the proposed rejection of claims 9, 10, 12 and 16, the examiner adds that: Although Sato did not mention the use of phase offset selection circuits to select clock signals from a plurality of phase-distributed clock signals to serve as a timing reference for

transmission of data onto the signal lines, this feature was explicitly taught by leddeloh (note, e.g., Jeddeloh, Figure 7, as described in Exhibit K). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize the delay circuitry of leddeloh for the delay elements in the system of Sato, since (1) the systems were compatible because both were designed to delay the transmission of data by a variable amount of delay that is determined by a microprocessor to coordinate data transfers across a memory bus (note Sato, Figure 1, and Jeddeloh, Abstract), (2) the elements of leddeloh were flexibly designed to be used in other systems (note Jeddeloh, column 5, lines 42-45, and column 17, lines 54-59) and (3) such a combination would provide

Application/Control Art Unit: 3992

Number: 95/001,160

Page 13

low-skew control signals, "thereby permitting significant advantages in terms of reliability and speed" (note Jeddeloh, column 5, lines 42-45, and column 17, lines 60-63).

Issue 4
Claims 11 and 17 are alleged to be rendered obvious by Sato in view of Jeddelohfurther in view of Take kuma under 35 Us.c.

§ 103.

12.

Claims 11 and 17 are rejected under 35 U.S.C. § 103 as being unpatentable over Sato in

view of leddeloh and further in view of Takekuma. The proposed rejection of this claim set forth in the Request is adopted, with modifications to the rationale in support thereof. See the Request pp. 11, 12 and 22-37 and the claim chart in Exhibit K, which are hereby incorporated by reference. With regard to the proposed rejection of claims 11 and 17, the examiner adds that: The Sato/Jeddeloh combination described above did not mention that the clock generation circuitry comprises a phase-locked loop circuit to generate the first clock signal based on a reference clock signal that has a lower frequency than the first clock signal. Sato and Jeddeloh each describe a clock generator, but neither provides details of how one is made. However, this feature was explicitly taught by Takekuma (note, e.g., Takekuma, Figure 30, as described in Exhibit K). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize the clock signal generator of Takekuma in the Sato/Jeddeloh

Application/Control Art Unit: 3992

Number: 95/001,160

Page 14

combination described above, since (1) Sato and Jeddeloh each require a clock generator (note Sato, clock generator [Center of Figure 10J, and Jeddeloh, clock generator 30), and Takekuma provides details of how one might be implemented (see Takekuma, Figure 30), (2) the Takekuma implementation was flexibly designed to be used to provide timing for memory buses (as specifically required by Sato and Jeddeloh) or various other types of buses (note Takekuma, column 8, lines 29-36) and (3) such a combination would enable fast signal transmission to be achieved in memory systems such as that of the Sato/Jeddeloh combination described above, "in which the signal propagation time is large and the delay time to each module is different depending on its position" (note Take kuma, column 21, lines 21-24).

Issue 5 Claims 1, 2, 4, 6-8, 13-15 and 18-24 are alleged to be rendered obvious by Sato in view ofVogley under 35

iis.c. § 103.
13-15 and 18-24 are rejected under 35 U.S.C. § 103 as being The proposed rejection of this claim set forth in the

13.

Claims 1, 2, 4,7,8,

unpatentable over Sato in view ofVogley.

Request is adopted, with modifications to the rationale in support thereof. See the Request pp. 11, 12,22-33 and 38-48 and the claim chart in Exhibit L, which are hereby incorporated by

reference,
With regard to the proposed rejection of claims 1, 2, 4, 7, 8, 13-15 and 18-24, the examiner notes that:

Application/Control Art Unit: 3992
(1)

Number: 95/001,160

Page 15

Claims 7, 8, 13-15 and 18-23 are believed to be taught by Sato alone, for the

reasons noted above. (2) The proposed rejection is modified only to the extent that it lacks a formal

statement of the motivation to combine Sato and Vogley. The examiner adds the following: It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Sato to further delay the write data for each SDRAM to take account of the propagation time of the write command as taught by Vogley, because [see the reasons provided on page 48 of the request, with reference to Exhibit L].

14.

The proposed rejection of claim 6 is not adopted. Claim 6 recites, "a third signal line to carry a first timing signal that indicates a time at

which the first data transmitted on the first signal line is sampled by the first memory device; and a fourth signal line to carry a second timing signal that indicates a time at which the second data transmitted on the second signal line is sampled by the second memory device." The proposed rejection of claim 6 refers to passages in Sato wherein clock signals are used as a reference for writing data into the memory devices, but these appear to be "acquisition references" inasmuch as the clock signals act to trigger reading data from and writing data to the memory devices. The rejection does not teach sampling by the memory devices. Instead, Sato teaches sampling by the memory controller, which sends signals to adjust delays in the delay circuits or in the SDRAM itself. Note Figures 11 and 12, spanning pages 12 and 13 of Sato (also shown in, column 9, line 29, to column 10, line 14, of U.S. Patent No. 6,359,815), the mode wherein C'W="l
fl.

Application/Control Art Unit: 3992

Number: 95/001,160

Page 16

While it is agreed that sampling does occur to determine the propagation times of the various lines, and some type of sampling must occur in the DRAM of Sato, there is no explicit teaching in Sato of timing signals that indicate the times at which data propagating on the first and second signal lines are sampled by the first and second memory devices.

Issue 6 Claims 3, 9, 10, 12 and 16 are alleged to be rendered obvious by Coteus in view of Jeddeloh under 35

usc.

§ 103.

15.

The proposed rejection of claims 3, 9,10,12

and 16 is not adopted.

With regard to claims 3, 9, 10, 12 and 16, the arguments presented on pages 17-19 and 45-47 of patent owner's response filed November 3, 2011 are incorporated by reference herein.

Issue 7 Claims 11 and 17 are alleged to be rendered obvious by Coteus in view of Jeddeloh and in further view of Take kuma under 35 Us.c. § 103.

16.

The proposed rejection of claims 11 and 17 is not adopted. With regard to claims 11 and 17, the arguments presented on pages 17-19'and 45-47 of

patent owner's response filed November 3, 2011 are incorporated by reference herein.

Application/Control Art Unit: 3992 Issue 8

Number: 95/001,160

Page 17

Claims 4, 19 and 20 are alleged to be obvious by Coteus in view of Take kuma under 35

us.c. § 103.
17. Claims 19 and 20 are rejected under 35 U.S.C. § 103 as being unpatentable over Coteus

in view of Takekuma. The proposed rejection of these claims set forth in the Request is adopted, with modifications to the rationale in support thereof. See the Request pp. 11, 12, 1322 and 52-54 and the claim chart in Exhibit J, which are hereby incorporated by reference. With regard to the proposed rejection of claims 19 and 20, it is noted that Coteus appears to fully teach these features, e.g., the ports where lines 104a, (N-l)a, and 102a, respectively, enter the DRAMs, as described above. Nevertheless, Coteus did not actually use the term "termination" in reference to the lines. .Takekuma describes "termination resistors" added to transmission lines (note, e.g., Takekuma, Figure 6, resistors 40-45, as described in Exhibit J). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize the termination resistors of Takekuma as termination components in the system of Coteus, since such a combination would provide an "effective" termination for the signal lines in the memory devices (note Takekuma, column 13, lines 5-13).

18.

The proposed rejection of claim 4 is not adopted. With regard to claim 4, the arguments presented on pages 17-19 and 47-50 of patent

owner's response filed November 3,2011 are incorporated by reference herein.

Application/Control Art Unit: 3992

Number: 95/001,160

Page 18

Issue 9 Claims 3, 9, 10, 12 and 16 are alleged to be rendered obvious by Sato in view ofVogley and infurther view of Jeddeloh under 35

us.c. § 103.

19.

Claims 3, 9,10,12

and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over

Sato in view ofVogley and further in view of Jeddeloh. The proposed rejection of these claims set forth in the Request is adopted, with modifications to the rationale in support thereof. Request pp. 11, 12, 22-33 and 38-49 and the claim chart in Exhibit L, which are hereby incorporated by reference. (1) With regard to the proposed rejection of claims 9, 10, 12 and 16, it is noted that:

Sato/Jeddeloh combination appears to fully teach these features, for the reasons given above. (2) adds that: Although the Sato/V ogley combination discussed above did not mention the use of phase offset selection circuits to select clock signals from a plurality of phase-distributed clock signals With regard to the proposed rejection of claims 3,9,10,12 and 16, the examiner

to serve as a timing reference for transmission of data onto the signal lines, this feature was explicitly taught by Jeddeloh (note, e.g., Jeddeloh, Figure 7, as described in Exhibit L). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize the delay circuitry of Jeddeloh for the delay elements in the

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SatoNogley combination discussed above, since (1) the systems were compatible because both were designed to delay the transmission of data by a variable amount of delay that is determined by a microprocessor to coordinate data transfers across a memory bus (note Sato, Figure 1, and Jeddeloh, Abstract), (2) the elements of Jeddeloh were flexibly designed to be used in other systems (note Jeddeloh, column 5, lines 42-45, and column 17, lines 54-59) and (3) such a combination would provide low-skew control signals, "thereby permitting significant advantages in terms of reliability and speed" ( Jeddeloh, column 5, lines 42-45, and column 17, lines 60-63).

Issue 10 Claims 11 and 17 are alleged to be rendered obvious by Sato in view ofVogley and Jeddeloh and infurther view of Take kuma under 35

usc. § 103.
/

20.

Claims 11 and 17 are rejected under 35 U.S.C. § 103 as being unpatentable over Sato in The proposed

view ofVogley and further in view of leddeloh and further in view of Takekuma.

rejection of these claims set forth in the Request is adopted, with modifications to the rationale in support thereof. Request pp. 11, 12,22-33 and 38-49 and the claim chart in Exhibit L, which are hereby incorporated by reference. With regard to the proposed rejection of claims 11 and 17, the examiner adds that: The Sato/Vogley/Jeddeloh combination described above did not mention that the clock

generation circuitry comprises a phase-locked loop circuit to generate the first clock signal based on a reference clock signal t~at has a lower frequency than the first clock signal. Sato, Vogley and Jeddeloh each describe a clock generator, but neither provides details of how one is made.

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However, this feature was explicitly taught by Takekuma (note, e.g., Takekuma, Figure 30, as described in Exhibit L). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize the clock signal generator of Takekuma in the SatoNogley/Jeddeloh combination described above, since (1) Sato, Vogley and Jeddeloh each

require a clock generator (note Sato, clock generator [Center of Figure 10), Vogley system clock device 65 and Jeddeloh, clock generator 30), and Takekuma provides details of how one might be implemented (see Takekuma, Figure 30), (2) the Takekuma implementation was flexibly designed to be used to provide timing for memory buses (as specifically required by Sato, Vogley and Jeddeloh) or various other types of buses (note Takekuma, column 8, lines 29-36) and (3) such a combination would enable fast signal transmission to be achieved in memory systems such as that of the SatoNogley/Jeddeloh combination described above, "in which the

signal propagation time is large and the delay time to each module is different depending on its position" (note Takekuma, column 21, lines 21-24).

Issue 11
Claim 4 is alleged to be rendered obvious by Sato in view of Vogley and further in view of Dillon and Hyundai under 35

usc. § 103.

21.

Claims 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Sato in view of

Vogley and further in view of Dillon and further in view of Hyundai. The proposed rejection of these claims set forth in the Request is adopted, with modifications to the rationale in support

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thereof. Request pp. 11, 12,22-33 and 38-51 and the claim chart in Exhibit L, which are hereby incorporated by reference. (1) With regard to the proposed rejection of claim 4, it is noted that the proposed

rejection of claim 4 is modified to the extent that it references the rejection of claim 1 (based on the Sato/Vogley combination discussed above), which has been modified above. (2) Claim 4 is believed to be taught by the SatoN ogley combination alone, for the

reasons noted above. (3) The proposed rejection is further modified only to the extent that it lacks a formal

statement of the motivation to combine Sato and Vogley. The examiner adds the following: It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the SatoN ogley combination to include a termination resistor as in Hyundai integrated in a memory module connected to the memory bus as in Dillon, because [see the reasons provided on pages 49-51 a/the Request, with reference to Exhibit L].

Response to Submissions by Patent Owner and Requestor
22. The response by the patent owner on November 3, 2011, the comments filed by the third

party requester on December 1,2011, and the declarations of Robert J. Murphy and Harvey Stiegler have been carefully considered. As noted above, the third party requester has sent a notice of non-participation and a

request to withdraw the December 1, 2011 comments. At that time, the comments had already

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been entered and considered by the examiner. Because these comments have not been expunged from the record, they are relied upon for purposes of this Office action.

Issue 1 (1) With regard to claims 1,2,4,5,8, 14, 15 and 18, requester's comments filed

December 1,2011 argue: "it is noted that the delay element '11a is used to delay the clock bus 103a as well as the controlladdress bus 102a. Specifically, and as shown in FIG. 2a, reproduced above, the output of DELAY lla is provided to DRIVERs Sa and 8b, which drive the above-listed buses, respectively. Accordingly, any changes to delay element lla will adjust the delay (phase) of the clock bus 103a as well as the delay of the control/address bus 102a. "[T]he phase of the clock signal applied to register 1Oal through input 10al' [and thus to bus 102a] is the same as the phase of the clock signal provided to the DIMM 14a over bus 103a, owing to the fact that the input 10al' and bus 103a are both connected to the output of delay element 11a." Coteus at col. 26, Ins. 10-21"

Initially, the examiner reached exactly the same conclusion with regard to the Coteus reference. However, paragraphs 16-22 of the most recent Murphy declaration include convincing arguments such as: "When clock signal 11" latches address and command information into register 1Oal, the address and command information cannot correspond to data latched by the DRAMs using the same edge. Instead, when clock signal 11" latches address and command information into register 1Oal, the address and command information would correspond to data latched using a subsequent edge ... Still further, the Controll Address signals are flushed (replaced with new values) beginning with the same clock edge that initiates a memory operation. (Fig. 2a). This further proves that the propagation delay on the Control/Address bus is not relevant to the timing relationship of clock and data delays between the memory controller and the individual memory devices on the DIMM."

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The comments presented by the third party requester on December 1, 2011 and the declaration of Harvey Stiegler do not address the clock edge arguments in paragraphs 16-22 of the Murphy declaration. These arguments are presented on pages 17-19 of the patent owner's

response filed November 3, 2011, which are incorporated herein by reference. (2) With regard to claims 20, 23 and 24, patent owner's arguments are not

convmcmg. Note pages 15-28 of patent owner's response filed November 3, 2011. Whereas claims 1,2,4,5,8,14,15 and 18 are directed to the effect of signals travelling

on a control signal path, claims 20 and 23 are directed to the effect of signals travelling on a timing path (e.g., clock line) and claim 24 is directed to the effect of signals travelling on an address path. As noted above, patent owner has effectively argued that in Coteus the signals travelling on a control path do not influence the timing of data transmission delays to the memory devices. However, these same arguments do not apply to claims 20,23 and 24. Pages 8-16 of requester's comments filed December 1,2011 are convincing with regard to claims 20, 23 and 24 and are incorporated herein by reference. (3) :

With further regard to claim 5, requester's comments filed December 1, 2011, This argument is

pages 3-5 argue that the DRAM of Coteus must necessarily perform sampling. accepted by the examiner.

But this argument is not sufficient because there is no explicit teaching in Coteus of a timing signal that indicates the time at which write commands propagating on the control signal

path are sampled by the first and second memory devices, as required by claim 5.

Application/Control Art Unit: 3992 (4) argues:

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Page 24

With regard to claim 23, the response by patent owner filed November 3,2011

"Coteus explicitly discloses that its clock signal on bus 103a arrives at various memory devices at the same time." (see page 28)

This argument is not convincing for the reasons given in Requester's comments filed December 1,2011: "The Patent Owner's arguments for the patentability of amended claim 21, from which claim 23 depends, rely on a premise that Coteus requires a clock signal reach all memory devices at the "same time". As discussed above, this premise is directly contradicted by Coteus. Since the clock signal in Coteus arrives at the various memory devices at different times, Coteus also teaches that the "respective times when each of the memory devices captures the write data are staggered in time" as recited in the amended claim. Thus, consistent with the comments above, and the Examiner's holding on this issue in other claims, the rejection of claim 23 should be maintained." (see page 16, footnotes omitted)

However, patent owner continues: "Even if there were inadvertent differences in the times when the clock signal reaches Coteus's memory devices, those differences would not be enough to anticipate claim 21. Claim 21 as amended now specifically recites that the claimed difference must be "such that the respective times when each of the memory devices captures the write data are staggered in time." Any inadvertent or inevitable variations in Coteus would not satisfy that additional limitation." (see page 28)

The examiner agrees with this statement.

Issue 5 (1) With regard to claims 1,2,4,7,8,13-15 and 18-24, patent owner has not shown

that the claims are distinct from the rejections based on Sato. The rejections have been

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maintained. In response to pages 37-45 of patent owner's arguments filed November 3, 2011, the comments filed by the third party requester on December 1,2011, pages 23-25, are incorporated herein by reference. (2) With regard to claim 6, page 5 of requester's comments filed December 1,2011,

argues that the DRAM of Sato must necessarily perform sampling. This argument is accepted by the examiner. But this argument is not sufficient because there is no explicit teaching in Sato of a timing signal that indicates the times at which data propagating on the first and second signal lines are sampled by the first and second memory devices, as required by claim 6.

Issues 6 and 7 With regard to claims 3, 9, 10-12, 16 and 17, these are directed to theeffect of signals travelling on a control signal path. As with claims 1,2,4,5,8, 14, 15 and 18 ofIssue 1, the

comments presented by the third party requester on December 1, 2011 and the declaration of Harvey Stiegler do not address the clock edge arguments in paragraphs 16-22 of the Murphy declaration. These arguments are presented on pages 17-19 and 45-47 of the patent owner's response filed November 3,2011, which are incorporated herein by reference.

Issue 8 (1) With regard to claims 19 and 20, patent owner's arguments are not convincing.

Note pages 22-26 of patent owner's response filed November 3,2011.

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Claims 19 and 20 are directed to the effect of signals travelling on a timing path (e.g., clock line). As noted above, patent owner has effectively argued that in Coteus the signals travelling on a control path do not influence the timing of data transmission delays to the memory devices. However, these same arguments do not apply to claims 19 and 20. Pages 8-16 of requester's comments filed December 1, 2011 are convincing with regard to claims 19 and 20 and are incorporated herein by reference. (2) With regard to claim 4, this is directed to the effect of signals travelling on a 14, 15 and 18 oflssue 1, the comments

control signal path. As with claims 1,2,4,5,8,

presented by the third party requester on December 1, 2011 and the declaration of Harvey Stiegler do not address the clock edge arguments in paragraphs 16-22 of the Murphy declaration. These arguments are presented on pages 17-19 and 47-50 of the patent owner's response filed November 3,2011, which are incorporated herein by reference.

Issues 2, 3, 4, 9, 10 and 11 With regard to Issues 2, 3, 4, 9, 10 and 11, patent owner has not shown that the claims are distinct from the rejections based on Sato. The rejections have been maintained. patent owner's arguments filed November 3,2011 directed to Issues 2,3,4, In response to

9, 10 and 11, the

comments filed by the third party requester on December 1,2011 directed to Issues 2, 3, 4,9, 10 and 11 are incorporated herein by reference.

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In order to overcome these rejections, patent owner must effectively prove, by argument or by amendment, that the timing of the Sato signals does not teach or suggest the timing described in the claims.

Conclusion
23.

This is an ACTION CLOSING PROSECUTION (ACP); see MPEP § 2671.02.

(1) Pursuant to 37 CFR 1.951(a), the patent owner may once file written comments limited to the issues raised in the reexamination proceeding and/or present a proposed amendment to the claims which amendment will be subject to the criteria of 37 CFR 1.116 as to whether it shall be entered and considered. Such comments and/or proposed amendments must be filed within a time period of 30 days or one month (whichever is longer) from the mailing date of this action. Where the patent owner files such comments and/or a proposed amendment, the third party requester may once file comments under 37 CFR 1.951(b) responding to the patent owner's submission within 30 days from the date of service of the patent owner's submission on the third party requester. (2) If the patent owner does not timely file comments and/or a proposed amendment pursuant to 37 CFR 1.951(a), then the third party requester is precluded from filing comments under 37 CFR 1.951(b). (3) Appeal cannot be taken from this action, since it is not a final Office action.

Submissions
24. In order to ensure full consideration of any amendments, affidavits or declarations, or

other documents as evidence of patentability, such documents must be submitted in response to this Office action. Submissions after the next Office action, which is intended to be an Action

Closing Prosecution (ACP), will be governed by 37 CFR 1.116(b) and (d), which will be strictly enforced.

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Service of Papers 25. Any paper filed with the USPTO, i.e., any submission made, by either the Patent Owner. must be served on every other party in the reexamination

or the Third Party Requester

proceeding, including any other third party requester that is part of the proceeding due to merger of the reexamination proceedings. As proof of service, the party submitting the paper to the

Office must attach a Certificate of Service to the paper, which sets forth the name and address of the party served and the method of service. Papers filed without the required Certificate of Service may be denied consideration. 37 CFR 1.903'; MPEP 2666.06.

Amendments 26.

in Reexamination

Proceedings proceeding

Any proposed amendment to the specification and/or claims in this reexamination

must comply with 37 CFR 1.530(d)-(j), must be formally presented pursuant to 37 CFR 1.52(a) and (b), and must contain any fees required by 37 CFR I.20( c). Amendments in an inter partes reexamination proceeding are made in the same manner that amendments MPEP 2666.01. in an ex parte reexamination are made. in a

See MPEP 2250 for guidance as to the manner

of making amendments

reexamination proceeding.

Extensions of Time 27. Extensions of time under 37 CFR 1. 136(a) will not be permitted in inter partes

reexamination proceedings because the provisions of 37 CFR 1.136 apply only to "an applicant" and not to the patent owner in a reexamination proceeding. Additionally, 35 U.S.C. 314(c)

requires that inter partes reexamination proceedings "will be conducted with special dispatch"

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(37 CFR 1.937). Patent owner extensions of time in inter partes reexamination proceedings are provided for in 37 CFR 1.956. Extensions of time are not available for third party requester comments, because a comment period of30 days from service of patent owner's response is set by statute. 35 U.S.C. 314(b)(3).

Notification 28.

of Concurrent Proceedings

The patent owner is reminded of the continuing responsibility under 37 CFR 1.985(a), to

apprise the Office of any litigation activity, or other prior or concurrent proceeding, involving the patent undergoing reexamination or any related patent throughout the course of this reexamination proceeding. The third party requester is also reminded of the ability to similarly inform the Office of any such activity or proceeding throughout the course of this reexamination proceeding. See MPEP § 2686 and 2686.04.

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All correspondence relating to this inter partes reexamination proceeding should be directed:

By Mail to:

Mail Stop Inter Partes Reexam Attn: Central Reexamination Unit Commissioner of Patents United States Patent & Trademark Office P.O. Box 1450 Alexandria, VA 22313-1450

By FAX to: (571) 273-9900 Central Reexamination Unit By hand to:Customer Service Window Randolph Building 401 Dulany Street Alexandria, VA 22314 Registered users ofEFS-Web may alternatively submit such correspondence via the electronic filing system EFS- Web, at https:llefs.uspto.gov/efile/myportal/efs-registered. EFS- Web offers the benefit of quick submission to the particular area of the Office that needs to act on the correspondence. Also, EFS- Web submissions are "soft scanned" (i.e., electronically uploaded) directly into the official file for the reexamination proceeding, which offers parties the opportunity to review the content of their submissions after the "soft scanning" process is complete. Any inquiry concerning this communication should be directed to the Central Reexamination Unit at telephone number (571) 272-7705.

Signed: IB. James Peikari/ B. James Peikari Primary Examiner Art Unit 3992

Conferees: Iwhcl
Alexander Kosowski Supervisor Art Unit 3992

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