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EMC Lect 6 [Compatibility Mode]|Views: 0|Likes: 0

Published by Govind Reddy

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https://www.scribd.com/doc/86589646/EMC-Lect-6-Compatibility-Mode

03/24/2012

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A Typical Power Supply Network

Consider a single section of the inductive (off-chip) portion of the network. Since the line impedance >> load impedance, it is modeled as a lumped inductance.

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• Each section of the supply network is an LC circuit – Has a resonant frequency fres < fclock – Then, inductor carries the average (DC) current – And capacitor supplies the instantaneous (AC) current • Size the bypass capacitor to – Supply cycle to cycle AC current with acceptable ripple – Handle inductor start/stop transient

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3/21/2012

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The bypass capacitance C > ki Qclock / V V is the maximum allowed supply variation Here, Qclock = Iav Tclock is the charge transferred in one clock cycle. Inductor provides the current Iav and the capacitor the difference . The factor ki is: ki = max 0 [ I (t ) Iav ]dt / IavTclock t

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3/21/2012 Here. ki = 0 5 Noise in Digital Systems 6 3 . ki = 1 If I(t) is a DC. ki reflects the maximum fraction of the total charge transferred each cycle ( Qclock) that must be supplied by the capacitor at a given t. If I(t) is a delta function.

inter-symbol interference .cross-talk .signaling power supply noise Need to eliminate or cancel this noise We cannot overpower it! 8 4 .3/21/2012 Proportional and Independent Noise Sources 7 Noise proportional to signal swing .signal return noise .

this variation results in additive voltage noise 10 5 .receiver offset .unrelated power supply noise .receiver sensitivity .3/21/2012 Noise independent of signal swing .reference offsets Can overpower this noise 9 Power Supply Noise Voltage drops across parasitics cause variation in the voltage of a single supply ( VDD or GND) from one point in the system If signal is referenced to local supply.

May not meet timing specs .Jitter in timing circuits 11 Cross Talk • Noise induced by one signal interferes with another signal • Capacitive coupling between on-chip lines • Capacitive and Inductive coupling between off-chip lines • Coupling over shared signal returns 12 6 .3/21/2012 Affects delay of many elements .

effective capacitance of Cc is doubled 13 • If aggressor(s) switch in the same direction. Cc is effectively eliminated • Can cause 2:1 variation in delay in some cases • Significant cause of jitter if timing is critical 14 7 .3/21/2012 Cross Talk and Delay • Capacitive cross talk can affect delay of RC signals • If aggressor(s) switch in opposite direction.

3/21/2012 Impact of noise on delay 15 16 8 .

3/21/2012 Impact of noise on functionality 17 Transmission Line Cross Talk A signal transition on one line induces forward and reverse traveling waves on adjacent lines Inductive and Capacitive Coupling 18 9 .

3/21/2012 Consider a positive transient on aggressor line. A Capacitive coupling induces a voltage on victim line B – positive waves in both forward and reverse directions 19 • Inductive coupling induces a current in line B – positive wave in the reverse direction – negative wave in the forward direction 20 10 .

in a homogeneous medium cancellation is exact .3/21/2012 Inductive and capacitive coupling add at the near end of the line – both waves are positive – pulse begins at beginning of coupled section Inductive and capacitive coupling subtract at the far end of the line .narrow pulse coincident with wave on aggressor 21 22 11 .

independent bounded vs. statistical Allocate noise to various sources Prepare a budget for the bounded sources – Net margin is what remains after bounded sources Compare magnitude of net margin to standard deviation of statistical sources – BER is a function of this SNR Constrain design to meet the budget 24 12 .3/21/2012 Managing noise 23 Divide noise along two axes proportional vs.

3/21/2012 Proportional Parallel cross-talk ISI Independent Receiver offset Receiver sensitivity Bounded Statistical Perpendicular crosstalk Power supply noise Thermal noise 25 Margins and Margin Ratio Gross margin (VGM) is half the signal swing Net margin (VNM) is gross margin less all bounded noise sources Margin ratio (VNM/VGM) is a good figure of merit – indicates proportion by which one can increase noise sources without causing failure 26 13 .

this case will occur 28 14 . but if one makes enough units and run them long enough.3/21/2012 27 Worst .Case Analysis All noise sources have the greatest possible magnitude and they all add up in the same direction Unlikely in any single unit at any instant in time.

3/21/2012 Signal swing Vs = 400 mV Vni Receiver offset Power supply noise Total Vni Kn Cross-talk Reflections Total Kn 50 mV 20 mV 70 mV 10% 10% 20% Kn Vs = 80 mV 29 Gross margin = 200 mV Vni = 70 mV KnVs = 80 mV Vn = 150 mV Net margin = 50 mV Margin ratio = 0.25 30 15 .

shot noise. power supply noise…. cross talk.thermal noise.4 mv (rms) 32 16 . These sources are modeled as a Gaussian distribution of zero mean – relevant parameter is the RMS value 31 Adding Gaussian Noise Sources Vrms = sqrt [ Vi² ] Cross-talk : 10 mV (rms) PS noise Total : 20 mV (rms) : 22. we consider the probability distribution of values rather than the worst case values .3/21/2012 Statistical Analysis For some noise sources.

then SNR = VNM/VGN What is the probability that the noise will exceed the margin? P(error) = erfc(VNM/VGN) < exp [ .3/21/2012 If the net margin is VNM and the total Gaussian noise is VGN.½ (VNM/VGN )² ] 33 Electrical wire models: The Ideal Wire The Lumped Model The Lumped RC model The Distributed rc Line The Transmission Line 34 17 .

When the wires are short or the cross-section of the wire is large or the interconnect material used has a low resistivity. inter-wire capacitance can be ignored. or when the wires run together only for a short distance. 35 The circuit parasitics of a wire are distributed along its length and are not lumped at a single position. When the separation between neighboring wires is large. it is often possible to lump the different fractions into a single circuit element. and all the parasitic capacitance can be modeled as capacitance to ground. The advantage of this approach is that the effects of the parasitic then can be described by an ordinary differential equation. 36 18 . Yet. when only a single parasitic component is dominant. The description of distributed elements requires partial differential equations. or when the interaction between the components is small.3/21/2012 Inductive effects can be ignored if the resistance of the wire is substantial — this is the case for long Aluminium wires with a small cross-section — or if the rise/fall time of the applied signal is large. a capacitanceonly model can be used.

with L the length of the wire and cwire the capacitance per unit length. This capacitive lumped model is simple. the wire still represents an equipotential region. yet effective. and is the model of choice for the analysis of most interconnect wires in digital circuits. and to lump the distributed capacitance into a single capacitor In this model. it is meaningful to consider only the capacitive component of the wire. and the wire itself does not introduce any delay.3/21/2012 As long as the resistive component of the wire is small and the switching frequencies are in the low to medium range. 37 Clumped = L cwire. The only impact on performance is by the loading effect of the capacitor on the driving gate. 38 19 . The driver is modeled as a voltage source and a source resistance Rdriver.

2 RC 2. This simple model.9 RC RC 40 20 .69 RC RC 2.3/21/2012 On-chip metal wires of over a few mm length have a significant resistance. which are more adequately represented by a distributed rc-model.3 RC Distributed rc network 0. A first approach lumps the total wire resistance of each wire segment into one single R and similarly combines the global capacitance into a single capacitor C.38 RC 0. called the lumped RC model is pessimistic and inaccurate for long interconnect wires. 39 Voltage range 0 to 50 % 0 to 63 % 10 to 90% 0 to 90 % Lumped RC network 0.5 RC 0. The equipotential assumption is no longer valid and a resistive-capacitive model has to be adopted .

42 21 . the inductance of the wire starts to dominate the delay behavior. and the quality of the interconnect material become high enough so that the resistance of the wire is kept within bounds. This is more precisely the case when the rise and fall times of the signal become comparable to the time of flight of the signal waveform across the line. and transmission line effects must be considered. lumped C model suffices 41 When the switching speeds become sufficiently fast.3/21/2012 Distributed rc delays should be considered only when tpRC > tpgate of the driving gate rc delays should be considered only when the rise (fall) time at the line input is smaller than RC – R and C are the total resistance and capacitance of the wire Otherwise.

3/21/2012 The lossless transmission line. either at the source (series termination). 43 Loads in MOS digital circuits tend to be of a capacitive nature. is appropriate for wires at the printed-circuit board level. resistance plays an important role in ICs. displays a time constant Z0CL. or at the destination (parallel termination) with a resistance equal to the characteristic impedance of the line. To avoid potentially disastrous transmission line effects such as ringing or large propagation delays. the line should be terminated. 44 22 . The transient response at the capacitor node. the resistance of the transmission line can be ignored . From the load’s point of the view. Due to the high conductivity of the Copper interconnect material used there. therefore. and the lossy transmission line model should be considered. the line behaves as a resistance with value Z0.On the other hand. How this influences the transmission line behavior and when the load capacitance should be taken into account? The characteristic impedance of the transmission line determines the current that can be supplied to charge capacitive load CL.

CL= 2 pF. 45 Output rises to its final value with a time-constant of 100 ps (= 50 W 2 pF) after a delay equal to the time-of-flight of the line. Propagation delay of the line equals the sum of the time-of-flight of the line (50 ps) and the time it takes to charge the capacitance (= 0. Z0 = 50 W.69 Z0 CL = 69 ps). tflight = 50 ps.3/21/2012 Capacitively terminated transmission line: RS = 50 W. The capacitive load should be considered in the analysis only when its value is comparable to or larger than the total capacitance of the transmission line 46 23 .

This reflected wave also approaches its final value asymptotically. the amplitude of this traveling wave is attenuated along the line: The arrival of the wave is followed by a diffusive relaxation to the steady-state value at point x. This forces the line temporarily to 0 V. The step input still propagates as a wave through the line. a voltage dip occurs at the source node. The farther it is from the source. the reflection equals .3/21/2012 After 2 tflight. This effect gradually disappears as the output node converges to its final value.5 V. 47 The response of a lossy RLC line to a unit step combines wave propagation with a diffusive component. However. Upon reaching the destination node. Since Vdest equals 0 initially. the more the response resembles the behavior of a distributed rc line 48 24 . the incident wave is reflected.2.

the total resistance of the line) >> 2 Z0. or substrates behave in a far more complex way than predicted by the above analysis. boards. At the board level. For instance. Be aware that actual wires on chips. and the line behaves as a distributed rc line when R ( = rL. When R = 5 Z0. tf) is smaller than the time-offlight of the transmission line (tflight). At that point. 50 25 . 49 1) Transmission line effects should be considered when the rise or fall time of the input signal (tr . one need worry about transmission line effects only when tr < 150 ps. cause extra reflections and can affect both signal shape and delay. This condition is easily achieved with state-of-the-art processes and packaging technologies. For on-chip wires with a length of 1 cm. Ignoring the inductive component of the propagation delay can easily result in overly optimistic delay predictions. we should account for the delay of the line when tr < 8 ns. the line is more appropriately modeled as a distributed rc line. called transmission line taps.3/21/2012 In fact. the resistive effect becomes dominant. branches on wires. where wires can reach a length of up to 50 cm. only 8 % of the original step reaches the end of the line.

the distributed rc model is more appropriate.3/21/2012 2) Transmission line effects should be considered only when the total resistance of the wire is limited to R < 5 Zo If this is not the case. Both constraints can be summarized in the following set of bounds on the wire length: 51 26 .

Yeditepe c6713 Dsk Lab Manual and 4

Dsp Lab Report-2 by L Govind ec

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