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Published by: sabatino123 on Mar 30, 2012
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The ALJ also concluded that various combinations of NextBus, Harriman, Farmwald ’037

and Release 4 render obvious claims of the ’405 and ’109 patents. ID at 219-23. He based these

conclusions on the same reasons provided for the combinations based on Yano and Dan. Id. As

discussed above, however, those reasons are unsupported.

In addition, the ALJ did not address evidence and arguments supporting non-obviousness.

CIB at 91-100; CRB at 48-51. For example, the ALJ failed to address why it would have been

obvious to implement the alleged DDR features in NextBus or Harriman or even that such a

modification was possible. Indeed, the fact that the NextBus and Harriman systems ran at 25 MHz

(at most) is strong evidence that they would not have functioned at twice that rate. CX-

10765C.0131. If they could have operated twice as fast, the clock frequency simply would have been

50 MHz instead of 25 MHz. And if confronted with a system that could have operated at 50 MHz,

but was limited because it only had a 25 MHz clock, one of ordinary skill would have simply

increased the clock frequency to 50 MHz and would not have looked to modify the system to use

both edges of the clock signal (add DDR functionality) since there would have been no impediment

to increasing the clock frequency. Id. at 123.

Further, NextBus involved communications over a backplane bus between a CPU and a

board. Id. at 46-47. The CPU does not keep track of low-level information necessary for issuing a

precharge operation, providing bank selection information, or issuing a code specifying a sense

operation. Id. at 79, 123-26. The claimed precharge operation, bank selection information, and sense

operation are irrelevant to such a backplane bus or bus 209 of Harriman. Id. at 124-27.

In addition, under the ALJ’s construction, a “memory device” in NextBus and Harriman is a

board with a memory controller. ID at 109. That board would issue the codes or bank selection to

itself. CX-10765C.0124-27. Dr. Jacob agreed this is non-sensical, testifying that it “doesn’t make

sense” for the structure that is “performing the methods described in the claims [to] reside[] within



the memory device.” HTr. 1099:20-24.

Finally, the ALJ’s reasons why the purported strobe signal of NextBus or Harriman would

have been incorporated into Farmwald ’037 are unsupported. He asserted that it would have been

obvious to do so because “all the references sought to address the well-known need in the industry

for faster data access by overcoming the inherent skew associated with various clocking schemes.”

ID at 222. But the ALJ ignores that Farmwald ’037 operates at 500 MHz—twenty times faster than

NextBus and Harriman. CX-10765C.0130-31; RX-4269 at 4:44-46; RX-4265.0013. He does not

explain why one of ordinary skill would have looked to such slow systems to improve the speed of

the much faster of Farmwald ’037 systems. CX-10765C.0131

The ALJ also asserted that combinations with Farmwald ’037 would “improve the efficiency

and speed . . . by indicating to the target memory device that data is on the bus, thereby enabling

higher-frequency data access rates.” ID at 222. But Farmwald ’037 already knows when data is on

the bus, for example, through the use of a delay value stored in an access time register, enabling

speeds well beyond NextBus and Harriman. RX-4269.0022 at 6:40-45; CX-10765C.0130-31. The

ALJ ignored this point. ID at 223. He also did not address that Respondents’ expert acknowledged

that he is unaware of any memory devices at the time that could implement the protocol of the

NextBus specification. HTr. 1121-22. Simply put, the ALJ’s reasons for the combinations of the

NextBus specification, Harriman, Farmwald ’037 and Release 4 are contrary to the evidence and do

not make sense.

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