NAME: EC 1401 /VLSI DESIGN TOPICS COVERED: UNIT III SPECIFICATIONS USING VERILOG HDL: (i) VLSI design Flow (ii) Identifiers (iii)Gate primitives (iv)Behavioral modeling (v) Switch Level Modeling (vi)Timing controls (vii) (viii) Procedural assignments Conditional Statements

(ix)Structural and gate level description of Ripple carry adder, 3:8 Decoder, Priority encoder, Comparator in Verilog . PART A 1.What is HDL? HDL stands for Hardware Description language. There are two types of HDL’s: VHDL – Very high speed Integrated circuit Hardware Description Language Verilog HDL 2.What is Verilog? Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level. 3. What are the various modeling used in Verilog? (i). Gate-level modeling (Or) Structural modeling (ii). Data-flow modeling

(iii) Switch-level modeling (iv)Behavioral modeling 4. What is structural gate-level modeling? Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together. 5. What is Switch-level modeling? Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the MOS-transistor level are described using the MOSFET switches. Eg; nmos,pmos,cmos,rnmos,rpmos,rcmos 6. What are identifiers? Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters. Examples: A014, a ,b, in_o, s_out Keywords: Reserved Identifiers are known as Keywords. Eg: assign, module,end Escaped Identifiers : It is a way of providing printable ASCII characters and it starts with a \ (backslash ) character. 7. What are the value sets in Verilog? Verilog supports four levels for the values needed to describe hardware referred to as value sets. Value levels Condition in hardware circuits 0 Logic zero, false condition 1 Logic one, true condition X Unknown logic value Z High impedance, floating state 8. Give the classifications of timing control? Methods of timing control: (i). Delay-based timing control (ii). Event-based timing control (iii) Level-sensitive timing control Types of delay-based timing control: (i). Regular delay control (ii). Intra-assignment delay control (iii). Zero delay control Types of event-based timing control: (i). Regular event control (ii). Named event control (iii). Event OR control (iv). Level-sensitive timing control 9. Give the different arithmetic operators?

and buf(non-inverting drive buffer). or.Operator symbol Operation performed Number of operands * Multiply Two / Divide Two + Add Two . No else statement Syntax : if ( [expression] ) true – statement. 13. nand. The output variable Control is assigned logic 1 always. There are two types of pull gates in Verilog : pullup and pulldown. An initial block executes once in the simulation and is used to set up initial conditions and step-by-step data flow (ii). logic gates have delays associated with them: (i) Rise delay (ii) Fall Delay (iii) Turn off delay 15. What are the types of conditional statements? 1. What are gate primitives? Verilog supports basic logic gates as predefined primitives. The important operations are and. (i). Syntax : pullgate name <instance name>(output variable). xnor. What are the types of typical gate delays in Verilog HDL? In real circuits. Give the different bitwise operators. Operator symbol Operation performed Number of operands ~ Bitwise negation One & Bitwise and Two | Bitwise or Two ^ Bitwise xor Two ^~ or ~^ Bitwise xnor Two ~& Bitwise nand Two ~| Bitwise nor Two 11. An always block executes in a loop and repeats during the simulation. xor. Give the two blocks in behavioral modeling. These primitives are nstantiated like modules except that they are predefined in verilog and do not need a module definition. 14. Primitive logic function keyword provide the basics for structural modeling at gate level. One else statement . 2. Define Pull gates. 12. Eg: pullup PUP(control).Subtract Two % Modulus Two ** Power (exponent) Two 10. Pull gates have only one output with no inputs.

Name the types of ports in Verilog Types of port Keyword Input port Input Output port Output Bidirectional port inout 17. Nested if-else-if Syntax : if ( [expression1] ) true statement 1. (ii)always @(a. Eg: assign #5 sum = a^ b.Syntax : if ( [expression] ) true – statement. Give the basic syntax of Verilog HDL. . Output < variable list>.b). else if ( [expression2] ) true-statement 2. 3. What is a continuous statement in Verilog HDL? Continuous assignment statement is the most basic statement in Dataflow modeling used to drive a value onto a net. 16. else default-statement. else if ( [expression3] ) true-statement 3.What is a task in Verilog? A task is like a procedure that provides the ability to execute common piece of code from several different places in a description. the false-statement is executed. Non-blocking assignment 18. Why do you require sensitivity list? The sensitivity list is used to specify the event which flags off the execution of the statements inside a block. What are the types of procedural assignments? 1. 19. The [expression] is evaluated. Blocking assignment 2. else false-statement. Syntax : assign <delay> <variable> = expression. . If it is false (zero) or ambiguous (x).. 21. If it is true (1 or a non-zero value) true-statement is executed. 20. Syntax : always @ (sensitivity list) Eg: (i)always @(posedge clock). Syntax: module <module name > (Variable list). Input <variable list>.

b.(May 08/May 09)(12) The flowchart of designing a VLSI circuit is given below: Design Specification Behavioral Description RTL Description Functional Verification and Testing Logic Synthesis /Timing Verification Logic Design Process Gate level Netlist Logical Verification and Testing Floor Planning /Automatic Place and r route Physical Design Process Physical Layout Layout verification Implementation . PART B 5.carry).sum. Explain in detail the VLSI design flow.. endmodule Eg: module halfadder(a.

data flow and gate. area and power specifications. Functional verification and Testing: Design descriptions are tested for their functionality at every level . interface and overall architecture of the digital circuit to be designed is described abstractly. it is tested extensively with the help of a simulation tool. Logic synthesis converts the RTL description into gate level net list.RTL description that is register transfer language explains the design in the form of data flow. . This is carried out by the simulation tool. Behavioral Description and RTL Description: The design at this level has to be extended with the help of known functional blocks and it is the next level of detailed description.behavioral. the sizes of all the functional blocks are calculated and locations are assigned. Once the behavioral level design description is ready. Once again the design is tested for its functionality. those which interact frequently are kept close together. The main objective of this step is to keep the highly connected blocks physically close to each other. Logic Synthesis: The corresponding hardware realization of the circuit is carried at this level. PHYSICAL DESIGN: Floor Planning: In this step. The circuits are realized through FPGA or ASIC. functionality. Logic synthesis tool ensures that the gate level net list meets timing.Design Specification: In this stage. Blocks with I/O pins are kept close to the periphery. Gate level net list: A gate level net list is a description of the circuit in terms of gates and connections between them. This is to check whether al l the functions are carried out as expected and to rectify them.

Minimize the critical net delays Make the chip as dense as possible Minimize the power dissipation Minimize the interconnect congestion Minimize the timing requirement Minimize cross talk Minimize the interconnect length: 2. After verification. There are two types of routing : Global routing and Detailed routing The goal of the global router is to provide complete instructions to the detailed router on where to route .. the performance specifications are computed and verified.nand.and.nor. Implementation: Once the placement and routing are completed. . it is time to make the interconnections by routing the chip.B.input n) Eg: or or1(A.Write a note on gate primitives in Verilog HDL. input2…….xnor Syntax: multiple input gate type <instance name>(output A.(8 Marks ) Verilog HDL has the capability of gate level modeling.S1.C.xor.D. Eg: or. The following are the bult in primitive gates in VErilog HDL: (i) Multiple input gates: These gates have one or more than one input with one output.Placement: The objectives of the placement step are: • • • • • • • Routing: Once the designer has floor planned a chip and the logic cells have been placed.input 1. the design of the VLSI circuit is implemented in an IC.The main objective of this step is to reduce the interconnect length and area and to reduce the delays in the critical path.).

S1. notif1 Syntax: Tristate gate type <instance name>(input A. Eg: bufif0.C).Gate) . bufif1. output B. Syntax : pullgate name <instance name>(output variable). These gates have an additional control signal.not Syntax: multiple output gate type <instance name>(input A. These gates have only one input with multiple outputs. Control C). These gates can be used in an application where the output of a gate has to drive more than one load. A pullup gate places logic 1 on its output and a pulldown gate places a logic 0 on its output. Eg: buf.output 1. Eg: nmos. (iii) Tristate gates.. The output variable Control is assigned logic 1 always.ouyput n) Eg: buf buf1(A. (iv) Pull gates: These gates have only one output with no inputs. Control C ) Eg: bufif1 buffer(A. Eg: pullup PUP(control). S2. cmos. rcmos.(ii) Multiple output gates. Eg: nmos MOS1(Source.The input is driven to the output only after the activation of the control signal. pmos. output2……. input B.Drain. Syntax: gate type<instance name>(output A. notif0.S3).B. These gates are used for switch level modeling in Verilog HDL.that is data flows from input to the output and the data flow can be turned off by appropriately setting the control input. (v) MOS switches: These gate models unidirectional switches.

An initial block starts at time 0.(May 08) (OR) Explain structured procedure statements (OR) Write a note on always and initial statement Ans. If there are multiple initial blocks.Multiple behavioral statements can be grouped using the keywords begin and end. An always block starts at time 0. 3. initial begin M =2’b10. These statements are the two most basic statements in behavioral modeling. tranif0.(vi) Bidirectional Switches: These switches are bidirectional that is data flows from both ways and there is no delay when data propagates through the switches. Consider a program to generate a clock signal : . executes the statements in the always block continuously in a looping fashion. They are always and initial. monitoring waveforms and other processes that must be executed only once during the entire simulation run. All other behavioral statements can appear only inside these structural procedure statements. executes once during a simulation and then does not execute again. signal B. Initial statement: All statements inside an initial statement constitute an initial block. Y= 3’b001. This statement is used to model a block of activity that is repeated continuously in a digital circuit. Eg: tran. Always Statement: All behavioral statements inside an always statement constitute an always block. End The initial blocks are used for initialization. each block starts to execute concurrently at time 0. Eg : initial X = 1’b1. Control C).Write a note on Behavioral modeling . tranif1 Syntax: gate type<instance name>(signal A. There are two structured procedure statements in Verilog HDL.

 Eg: : # 5 reg = 1’b0.Blocking Assignments: . # 5 a = 2’b01. Ans.Blocking Assignments:  These statements are executed and processed at the same simulation time. initial clock = 1’b0. Application of Non. # 5 a = 2’b01. (i) Blocking Assignments:  These statements are executed in the order they are specified in a sequential block. (ii) Non. always #5 clock = ~clock.Eg: module clockgen(clock). output reg clock. “a” will assigned to value 01 only after 10 time units.  The “<= “ operator is used to specify the Non-blocking assignments.  Eg: # 5 reg = 1’b0. endmodule 4.  Read and write operations are performed simultaneously. A blocking assignment will not block execution of statements that follow in a parallel block.What are the procedural assignment statements?(OR) Differentiate Blocking and Non blocking statements.  The “= “ operator is used to specify blocking assignments. “a” will assigned to value 01 after 05 time units. A read operation is performed on each right hand side variables and then the write operations are executed according to the scheduled time.  Separate read and write operations are performed.

 Separate read and write operation. The symbol “# “ is used to specify the delay in a Verilog program. This is used to model several concurrent data transfer that takes place after a common event. Case (i): using Non-Blocking Assignments: always @(posedge clock) a <=b .Explain the various timing control constructs available in Verilog HDL. After the execution of first statement ‘b’ value is stored in ’ a’ and the original value of ‘a’ is lost and hence when the second statement is executed some value will be stored in ‘b’.  These statements eliminate the race condition in digital circuits. In the above program blocking assignment is used . In the above program Non blocking assignment is used . The values of ‘a’ and ‘b’ is first read and then assigned as per the instruction in the program. Therefore swapping is done in this case. always @(posedge clock) b =a. 5. Timing controls provide a way to specify the simulation time at which procedural statements will execute. Consider a program for swapping the values of two registers: Case (i): using Blocking Assignments: always @(posedge clock) a =b . The various methods of timing control are : .(Dec 07) Various timing controls are available in Verilog HDL. Eg. Therefore swapping is not done in this case. always @(posedge clock) b <=a.

y. initial begin x =0. # (4:5:6) q =0. z=0.z. Eg. initial begin x =0.z.(i) Delay based timing control: This timing control specifies in an expression specifies the time duration between when the statement is encountered and when the statement is executed.  Zero delay control : This isa method to ensure that a statement is executed last after all the statements in that simulation time are executed. z=0. There are three types:  Regular delay control : This is used when a non-zero delay is specified to the left of a procedural assignment. Such delay specifications alters the flow of activity in a different manner. Eg: # 10 y =1.y. Max. it is possible to assign delay to the right of the assignment operator. Eg: reg x. end initial .delay Typ. Min  Intra assignment delay control: Instead of specifying delay control to the of the assignment . // Takes the value of x and z and evaluate x+z at zero time but assigns to y only after 5 time units. reg x. y = # 5 x+z .

event OR control. Events can be used to trigger execution of a statement or a block of statements. elseif end  Named event control: Verilog provides the capability to declare an event and then trigger and recognize the occurrence of that event . Statements can be executed on changes in signal value or at a positive or negative transition of the signal value. The event does not hold any data. end // The statements x = 1 and z =1 will be executed last as they have a delay time as # 0. named event control and level sensitive timing control. Event based timing control : An event is the change in the value on a register or a net. Declaration by the keyword event and triggering the event by the symbol -> . Eg: q = @(posedge clock ) d. Eg: event store data // name of the event is store data always @ (posedge clock) . #0 z=1. (ii). The keywords posedge and negedge are used for positive transition and negative transition respectively.  Event OR control : This refers to transition on any of the multiple signals or events can trigger the execution of a statement or a block of statements. There are four types of event based timing control : Regular event control. else q = 1’b1.begin # 0 x =1. Eg: always @ (rest or clock or d) begin if (reset = = 0) q = 1’b0.  Regular event control : The @ symbol is used to specify an event control.

The keyword wait is used for level sensitive onstructs.begin if (data packet = = 4) -> store data // event store data is called again  Level sensitive Timing Control : Verilog HDL allows the ability to wait for a certain condition to be true before a statement or a block of statement is executed. 6. Eg: always wait ( count _enable) # 20 count = count +1 // the statement count +1 will be executed only when the signal count_enable is at logic 1.(a) Write a Verilog program to simulate a 4 bit ripple carry adder by instantiating four full adders. (May 09/Dec 08/May 08//Dec 07) Block Diagram Of 4 Bit Ripple carry adder: B3 A3 B2 A2 B1 A1 B0 A FA C3 FA C2 FA C1 C0 C4 S3 S2 S1 S0 Veilog program .

c(4).c0.b. wire (c1.b.a(1).s3. Fulladder fa1(s(0).a(0). input [3:0]a.c(2)).c0). xor x1(s. and a1(s1.c0.c3). input a.c0.c(0)). Fulladder fa3(s(2). output[3:0]b.a(2).c(2).s.s). or o1(cout.a.b(2).a(3).s2. endmodule module fulladder(a.s2.s). and a2(s2.b(0).c(1).s3) endmodule (b)Write a Verilog program to simulate a 2-bit magnitude comparator(Dec 07) .module RCA (a.cout.c(3).b).b.b.c(3)). Fulladder fa2(s(1).a).a. output[3:0]b.c(1)).s1.c2.b(1). input c0. output cout. cout.c0). output cout.c0. and a3(s3.b. Fulladder fa4(s(3). wire s1.b(3).

s3).a[0]).s4.s6). a[0]. output e. wire(s1.g2. or o1(d.s3. not n6(s6.s5.s3). input[1:0]a. and a6 (l2.s4.l1.s2.a[1].x1. xor x1(x1.s1.s1.g2. output c: output d.b.b[1]. and a4 (g3.l2.s6. not n1(s1.b[0]). and a2 (g1.l3). not n5(s5. and a7(l3.g3).c. not n1(s3.b[1]).s2. endmodule .a[1]).x2. and a1 (c.g1.d.b[0]). xor x2(x2. input[1:0]b.s4).b[1]).module magcomp(a.b[0]).g1. not n1(s4.b[1]).a[1].x2). and a5(l1.s2.g3. a[0].b[0]).l2. and a3 (g2.e0. a[1].s5.x1).a[0].l1. or o2(e. not n1(s2.l3).

7.I1). input I1. wire I1bar.(Dec 08) Truth Table for 3:8 decoder: I1 0 0 0 0 1 1 1 1 I2 0 0 1 1 0 0 1 1 I3 0 1 0 1 0 1 0 1 01 1 0 0 0 0 0 0 0 02 0 1 0 0 0 0 0 0 03 0 0 1 0 0 0 0 0 04 0 0 0 1 0 0 0 0 05 0 0 0 0 1 0 0 0 06 0 0 0 0 0 1 0 0 07 0 0 0 0 0 0 1 0 08 0 0 0 0 0 0 0 1 O1 = I1bar . not n1(I1 bar.I3 O3 = I1bar . and(O[1].I2bar.I2).I1bar. and(O[0]. Write a verilog program for 3:8 decoder. not n2(I2 bar.I3 bar O4 = I1bar .I2 .I1bar. not n3(I3 bar.I2 bar .I2 bar .I3 bar O6 = I1 +I2bar +I3 O7 = I1b +I2 +I3 bar O8 = I1 + I2 + I3 module 3:8 decoder(I1. output [7:0]O. O).I3 bar.I3.I3).I2 .I3).I2.I3.I3 bar 02 = I1bar .I2bar.I3 O5 = I1.I2 bar .I2. .I2 bar.I3bar).

else q = 1’b1. and(O[6]. elseif (condition 2) Expression 2. and(O[7]. 8.I2.I3bar). Explain the syntax of conditional statements in Verilog HDL with examples.I3bar).(May 08) (8 marks) (i) If statement : The if construct checks a specific condition and decides execution based on the result . and(O[5]. else default statement. endif endif end If condition 1 is satisfied or met with then expression 1 is evaluated .I2.and(O[2].I1.I1.I2bar. and(O[4].I1. elseif end .I3).I2.I3).I3bar). if satisfied expression 2 is evaluated . Eg: begin if (reset = = 0) q = 1’b0.If none of the conditions are satisfied then a default statement is executed.otherwise it checks for the next condition. and(O[3].I2.I1bar.I2bar.I1bar.I1. The syntax of an if statement is: if(condition 1) Expression 1.I3).

endcase Eg: module mux(s. endcase endmodule 9. default: statement. Switch modeling elements: (i) MOS switch (ii) CMOS switch (iii) Bidirectional switches (iv) Power and Ground (v) Resistive switches (vi) Pull up and pull down .i3. input [1:0]s.i2. The switches are available as primitive in Verilog. input i0.(May ’08)(8 Marks) Switch level modeling forms the bsic level of modeling digital circuits.o).i0. The MOS transistor is the basic element around which a VLSI circuit is built. Case_expression condition 1 : statement 1. By successive instantiation of these switches .i3. Case_expression condition 1 : statement 1. It has the following syntax: case( case_expression ) Case_expression condition 1 : statement 1. 2’b11:0=i3. 2’b10:0=i2. Write a note on switch level modeling. output 0. 2’b01:0=i1.i2. Case_expression condition 1 : statement 1.logic gates can be realized.(ii) Case Statement: A case statement is a multi way conditional branch. case(s) 2’b00:0=i0.i1.i1.

Eg: cmos MOS1(out. Syntax: gate type<instance name>(signal A. (i) Syntax: gate type<instance name>(output input B. Eg: nmos MOS1(Source. tranif1 Eg: tran. Eg: pullup PUP(control).in.P_control.Drain.P_control. (iv)Pull gates: These gates have only one output with no inputs. The input pins are connected in one side and the output pins are connected in the other. P_control turns the PMOS ON when it is in the logic state 0. signal B. Syntax: gate type<instance name>( out. Eg: nmos.Gate) (ii ) CMOS Switches: A CMOS switch is formed by connecting a PMOS and NMOS switch in parallel. A pullup gate places logic 1 on its output and a pulldown gate places a logic 0 on its output. .N_control) (iii) Bidirectional Switches: These switches are bidirectional that is data flows from both ways and there is no delay when data propagates through the switches. Control C).that is data flows from input to the output and the data flow can be turned off by appropriately setting the control input. Control C). N_control turns the NMOS ON when it is in the logic state 1. tranif0. pmos. Syntax : pullgate name <instance name>(output variable).MOS switches: These gate models unidirectional switches. The output variable Control is assigned logic 1 always (v) Power and Ground : Power and ground sources are specified by the keywords supply 1 and supply 0. These gates are used for switch level modeling in Verilog HDL.N_control).

(8 marks) The truth table of priority encoder is shown below: a[0] 1 x x x a[1] 0 1 x x a[2] 0 0 1 x a[3] 0 0 0 1 b[0] 0 0 1 1 b[1] 0 1 0 1 b[0) = a[3] +a[2] b[1] = a[3] +a[1]a[2] module priority(a.a[2]).(vi)Resistive Switches: These switches have higher source to drain impedance than regular switches and reduce the strength of the signal passing through them.b). Eg: rnmos. Write a Verilog code for a priority encoder. wire d1. endmodule . not n1(d2.rpmos 10.d2.a[1]. or o1(b[0]. output[1:0]b.a[3].d1). or o2 (b[1].a[2]. input([3:0]a.d[2]).a[3]). and a1 (d1.