ADVANCED MICROPROCESSORS

Session – 24 Prof. Venkataramaiah. P. P HEAD – Department of Instrumentation Technology & Medical Electronics M.S.Ramaiah Institute of Technology, Bangalore

Topics to be covered
Session 24 : 22/11/2005 : Interrupt Processing, Interrupt Vector table, Hardware Interrupts. Expanding the Interrupt Structure Interrupt Applications

Session 25 : 23/11/2005 : Session 26 : 25/11/2005 :

INTERRUPT
The meaning of ‘interrupts’ is to break the sequence of operation.While the cpu is executing a program,on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is transferred back again to the main program.

Purpose of Interrupts
Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data transfer rate.

Interrupt Sources  Hardware Interrupts (External Interrupts) ex: NMI. INTR  Software Interrupts (Internal Interrupts and Instructions) ex: INT n (Software Instructions) .

TF PUSH CS PUSH IP FETCH ISR ADDRESS POP IP POP CS POP FLAGS ISR procedure PUSH registers POP registers IRET .8086 Interrupt Response Mainline Program PUSH Flags CLEAR IF .

Fetch the ISR address from the interrupt vector table. 3. 5. It resets the TF in the flag Register.1. It decrements SP by 2 and pushes CS on the stack. 4. Disables INTR by clearing the IF. It decrements SP by 2 and pushes IP on the stack. 2. . 6. It decrements SP by 2 and pushes the flag register on the stack.

Interrupt Vector Table 010H 00CH 008H 004H 000H Type 4 POINTER (OVERFLOW) Type 3 POINTER (BREAK POINT) Type 2 POINTER (NON-MASKABLE) Type 1 POINTER (SINGLE STEP) Type 0 POINTER (DIVIDE ERROR) 16 bits CS base address IP offset .

03FFH 03FCH Type 255 (Available) Available Interrupts Type 32 (Available) (224) 080H 07FH Type 31 (Reserved) Reserved Interrupts (27) Type 5 Reserved 0014H .

Interrupt Vector Table INT Number INT 00 INT 01 INT 02 : : INT FF Physical Address 00000 00004 00008 : : 003FC .

Example Find the physical address in the interrupt vector table associated with a) INT 12H b) INT 8H Solution: a) 12H * 4 = 48H Physical Address: 00048H ( 48 through 4BH are set aside for CS & IP) b) 8 * 4 = 20H Memory Address : 00020H .

INT Can Jump to any Goes to fixed memory location with in 1MB location in the interrupt address range vector table to get address of ISR Used by the programmer in the sequence of instructions in the program Externally activated hardware interrupt can come at any time 2.Difference between INT and CALL instructions S. .No CALL 1.

CS:IP 5.S. 4. Flags can be saved IRET to pops of F. .No CALL 3. Cannot be masked (disabled) Automatically saves CS: IP of next instruction RET is the last instruction INT INTR can be masked In addition to CS:IP.

Functions associated with INT00 to INT04 (Exceptions) INT 00 (divide error)  INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by zero  ISR is responsible for displaying the message “Divide Error” on the screen .

82/0 = undefined result EX2: Mov AX.CL .535/2 = 32767 larger than 255 maximum capacity of AL .CL=00 DIV CL .Ex1: Mov AL. 65.82H . BL=02 DIV BL .AL= 82 SUB CL.2 .0 FFFFH. AX = FFFFH Mov BL.

INT 01  For single stepping the trap flag must be 1  After execution of each instruction. 8086 automatically jumps to 00004H to fetch 4 bytes for CS: IP of the ISR  The job of ISR is to dump the registers on to the screen .

1111 1110 1111 1111 B PUSH AX POP F .Resetting TF (TF = 0) First method: PUSH F POP AX AND AX.

SP AND 0(BP). OFE FFH POP F .Second method: PUSH F MOV BP.

PUSH F POP AX OR AX. 0000 0001 0000 0000 B PUSH AX POP F .Setting TF (TF = 1) Use OR instruction in place of AND instruction.

INT 02 (Non maskable Interrupt) 8086 5v NMI When ever NMI pin of the 8086 is activated by a high signal (5v). the CPU Jumps to physical memory location 00008 to fetch CS:IP of the ISR assocaiated with NMI .

It is one byte instruction whereas other instructions of the form “INT nn” are 2 byte instructions. .INT 03 (break point) A break point is used to examine the cpu and memory after the execution of a group of Instructions.

There is an instruction associated with this INT 0 (interrupt on overflow). the INT 0 is not executed but is bypassed and acts as a NOP. INT 04 ( Signed number overflow) . In case where 0F = 0 . If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will activate INT 04 if 0F = 1.

0F = 1 0100 0000 0100 0000 1000 0000 +64 +64 +128 INT 0 causes the cpu to perform “INT 04” and jumps to physical location 00010H of the vector table to get the CS : IP of the ISR . BL INT 0 . 64 Mov BL . 64 ADD AL .Example Mov AL .

P HEAD – Department of Instrumentation Technology & Medical Electronics M.Ramaiah Institute of Technology. P. Bangalore . Venkataramaiah.ADVANCED MICROPROCESSORS Session – 25 Prof.S.

HARDWARE INTERRUPTS NMI : Non maskable interrupts INTR : Interrupt request NMI INTR INTA 8086 Edge triggered Input Level triggered Input Response to INTR input .

Hardware Interrupts NMI: TYPE 2 Interrupt INTR: Between 20H and FFH .

INTO NMI INTR Single Step Priority Highest Lowest .Interrupt priority structure Interrupt Divide Error. INT(n).

Write timing diagram.University Questions Aug 2005 CSE/ISE (VTU) Explain the sequence of operation follow after the execution of INTR interrupt. What do you mean by interrupt priorities? List out interrupt priorities in 8086. .

University Questions Feb 2005 EC/TC (VTU) i) On receiving a hardware interrupt. Explain why this is required. (6 marks) Even though interrupt service routine is similar to any procedure routine from the last instruction of interrupt routine is IRET which is coded differently from the RET instruction of the subroutine return. Explain the reasons for this separate IRET instruction (4 marks) ii) . the 8086 processor pushes the flag to the stack and clears the TF and IF before doing any further operation.

(8 marks) .University Questions Aug 2005 EC/TC (VTU) What is an Interrupt Vector? Explain in detail the events that occur when a real mode interrupt becomes active. (6marks) Feb 2005 IT (VTU) Describe the software and hardware interrupts of 8086.

.Important Questions  What are the sources of Interrupts in 8086?  What is Interrupt vector table?  Briefly describe the conditions which cause the 8086 to perform each of the following types of Interrupts –Type 0 . Type 4 What do you mean by Interrupt priorities? State the Interrupt priorities of 8086. Type 1. Type 3. Type 2.

Applications of NMI Power failure detection circuit: Vcc Vcc R R CEXT REXT R 7414 AC B2 5v B1 A1 A2 Q Q NMI Opto Isolator 74LS122 Monoshot .

 The value of R & C are chosen so that pulse width of 2 AC I/P periods.c power is applied Q = 1. The output of the isolator is shaped by Schmit trigger inverter that provides a 50Hz pulse to the trigger Input of monoshot. no trigger pulses to monoshot hence Q = 0. Q = 0  If the AC power fails. Q = 1interrupting the microprocessor .  74LS122’s retriggarable as long as a.

 The ISR stores the contents of all internal registers and other ddc into a batterybacked up memory  The filter capacitor (normally high). . the voltage decays exponentially provides energy for the memory after the AC power ceases.

 The microprocessor responds to the INTR input by pulsing INTA output in anticipation of receiving an interrupt vector type number as data bus (D7 – D0) . it must be held at logic 1 level until it is recognized.INTR and INTA  Interrupt request input (INTR) is level sensitive.

INTR LOCK INTA D7-D0 Vector number Interrupt type is inserted in the second pulse INTA .

Minimum mode  IO/M = 0  I/O operation during the INTA bus cycle  LOCK = 0 To avoid BIU from accepting a hold request between two INTA cycles .

Maximum mode  Status lines s0 and s2 will enable INTA via 8288  Lock = 0 from T2 of first cycle until T2 of the second cycle to prevent the 8086 from accepting RQ/GT input .

Using a 3 state buffer for INTA D7-D0 (low data byte) 8086 74LS244 1G 2G INTR INTA 10 K … . Pull up resistors 5v Switches S7 S6 S0 Switch open = 1 Switch closed = 0 .

 Microprocessor outputs INTA that is used to enable 74LS244  The octal buffer applies the interrupt vector type number to the data bus in response to INTA  The vector type number is easily changed with the DIP switches. .

Making the INTR input Edge-trigger 5v 8086 Q INTR D Edge-triggered Interrupt request PR CLK CR Reset INTA .

 RESET signal initially clears the flip-flop so that no interrupts requested when the system is powered  Clock input becomes an edge-triggered interrupt request input  Clear I/P is used to clear the request when the INTA is output by the microprocessor .

VCC 10K IR0 INTR : IR1 : IR7 ..Expanding the Interrupt structure Using 74LS244 to expand D7 – D0 8086 8 74LS244 1G 2G 5v INTA .

then the output of the NAND gate goes to logic 1 and requests an interrupt through INTR input.If any of the IR input becomes a logic 0. .

IR6 1 1 1 1 1 1 0 IR5 1 1 1 1 1 0 1 IR4 1 1 1 1 0 1 1 IR3 1 1 1 0 1 1 1 IR2 1 1 0 1 1 1 1 IR1 1 0 1 1 1 1 1 IR0 0 1 1 1 1 1 1 Vector FEH FDH FBH F7H EFH DFH BFH Bit D7 = 1 .

HARDWARE INTERRUPT APPLICATIONS D7 – D0 8255 8086 ASCII Keyboard Kp 5v NMI Keyboard data .

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