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S.No. 1. 2. 3. 4. 5. 6. 7. 8. 9. (a) (b) (c) (d) (e) (f) (g) (h) TITLE Integrated Circuit Layout Integrated Circuit Design Tanner IC Work Flow S-EDIT T-SPICE W-EDIT L-EDIT LVS (Layout Vs Schematic) Layout Examples Nand Gate Nor Gate Transmission Gate Xor Gate using TX gate Xnor Gate 4*1 Multiplexer Full Adder Parallel Adder Page No. 3 4 9 11 23 25 28 43 45 46 47 48 49 50 52 54 56
Integrated Circuit Layout
Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors.
Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. When using a standard process - where the interaction of the many chemical, thermal, and photographic variables are known and carefully controlled - the behavior of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. A layout engineer's job is to place and connect all the components that make up a chip so that they meet all criteria. Typical goals are performance, size, and manufacturability. The layout must pass a series of checks in a process known as verification. The two most common checks in the verification process are Design Rule Checking (DRC), and Layout Versus Schematic (LVS). When all verification is complete the data is translated into an industry standard format, typically GDSII, and sent to a semiconductor foundry. The process of sending this data to the foundry is called tapeout due to the fact the data used to be shipped out on a magnetic tape. The foundry converts the data into another format and uses it to generate the photomasks used in a photolithographic process of semiconductor device fabrication. In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, much like the early days of PCB design. Modern IC Layout is done with the aid of IC layout editor software, or even automatically using EDA tools, including place and route tools or schematic driven layout tools. The manual operation of choosing and positioning the geometric shapes is informally known as "polygon pushing".
designers must account for its statistical nature. in order to achieve the desired speed of operation. 3. An IC process as of 2006 may well have more than 600 rules. Digital IC design is used to produce components such as microprocessors. 5. oscillators and active filters. The rules for what can and cannot be manufactured are also extremely complex. such as transistors. maximizing circuit density. to balance the effects of heat generation across the IC. where such concerns are less of an issue. as well as market pressure to produce designs rapidly. Attention must be given to power dissipation of transistors and interconnect resistances and current density of the interconnect. and flash) and digital ASICs. In short. or IC design. and verification of the instructions that the IC is to carry out. the physical layout of certain circuit subblocks is typically critical.4 Integrated circuit design Integrated circuit design. A large chip. IC design can be divided into the broad categories of digital and analog IC design. Digital design focuses on logical correctness. capacitors and the metallic interconnect of these components onto a piece of semiconductor. the design of an IC using EDA software is the design. The complexity of modern IC design. or ICs. and resistance. to segregate noisy portions of an IC from quiet portions. and placing circuits so that clock and timing signals are routed efficiently. FPGAs. may well have more transistors than there are people on Earth. Electromigration in metallic interconnect and ESD damage to the tiny components are also of concern. Analog IC design also has specializations in power IC design and RF IC design. resistors. phase locked loops. 4. linear regulators. contacts and vias since ICs contain very tiny devices compared to discrete components. as of 2006. Furthermore. A method to isolate the individual components formed in the substrate is necessary since the substrate silicon is conductive and often forms an active region of the individual components. matching. 2. encompassing the particular logic and circuit design techniques required to design integrated circuits. Design steps A typical IC design cycle involves several steps: 1. Modern ICs are enormously complicated. ROM. Fundamentals Integrated circuit design involves the creation of electronic components. Feasibility study and die size estimate Functional verification Circuit/RTL design Circuit/RTL simulation Logic simulation Floorplanning 4 . has led to the extensive use of automated design tools in the IC design process. Finally. Analog IC design is used in the design of op-amps. analog ICs use larger area active devices than digital designs and are usually less dense in circuitry. Fidelity of analog signal amplification and filtering is usually critical and as a result. or to facilitate the placement of connections to circuitry outside the IC. power dissipation. Analog design is more concerned with the physics of the semiconductor devices such as gain. The two common methods are p-n junction isolation and dielectric isolation. test. typically silicon. is a subset of electrical engineering. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography. memories (RAM. since the manufacturing process itself is not completely predictable.
The third step. Tweak (if necessary) 20. Yield Analysis / Warranty Analysis Reliability (semiconductor) 24. and the domain of functional verification. plan for next generation chip using production information if possible Digital design Roughly speaking. Packaging 17. Mask data preparation 14. This involves figuring out which gates to use. It is extremely difficult to verify that the RTL will do the right thing in all the possible cases that the user may throw at it. The RTL describes the exact behavior of the digital circuits on the chip.5 6. Wafer fabrication 15. Ramp up 22. Layout review 11. Examples include a C/C++ model. Post silicon validation 18. Many techniques are used. Datasheet generation Portable Document Format 21. Physical design: This step takes the RTL. Layout 8. is responsible for the chip doing the right thing. SystemC. RTL design. Production 23. and thousands of lines of computer code. SystemVerilog Transaction Level Models. Design For Test and Automatic test pattern generation 12. Die test 16. hardware emulation. Static timing analysis 10. and a library of available logic gates. does not affect the functionality at all (if done correctly) but determines how fast the chip operates and how much it costs. The spec may have some terse description. lint-like code checking. Design review 7. defining places for them. none of them perfect but all of them useful – extensive logic simulation. digital IC design can be divided into three parts • • • ESL design: This step creates the user functional specification. The user may use a variety of languages and tools to create this description. physical design. RTL design This is the hardest part. Device characterization 19. 5 . Layout verification 9. formal methods. and so on. RTL design: This step converts the user specification (what the user wants the chip to do) into a register transfer level (RTL) description. and wiring them together. Design for manufacturability (IC) 13. Each of these innocent looking statements expands to hundreds of pages of text. as well as the interconnections to inputs and outputs. Failure analysis on any returns 25. such as encodes in the MP3 format or implements IEEE floating-point arithmetic. Note that the second step. and creates a chip design.
Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip. Physical design Here are the main steps of physical design. input/output (I/O) pins are assigned and large objects (arrays. Design for manufacturability: The design is modified. Routing: The wires that connect the gates in the netlist are added. to make it as easy and efficient as possible to produce.6 A tiny error here can make the whole chip useless. time consuming and hard to spot. Tapeout and mask generation: the design data is turned into photomasks in mask data preparation. 6 . making sure the mapping to logic was done correctly. called design closure. Logic/placement refinement: Iterative logical and placement transformations to close performance and power constraints. and checking that the manufacturing rules were followed faithfully. noise (Signal Integrity). or worse. No one even noticed it until the chip had been in production for months. at a cost of $475 million (US). • • • • • • • • • • Floorplanning: The RTL of the chip is assigned to gross regions of the chip. Clock insertion: Balanced buffered clock trees are introduced into the design. every chip sold until they could fix the bug. Final checking: Since errors are expensive. etc. and yield (Design for Manufacturability) violations are removed. This is achieved by adding extra vias or adding dummy metal/diffusion/poly layers wherever possible while complying to the design rules set by the foundry. where possible.) are placed. Postwiring optimization: Remaining performance (Timing Closure). Yet Intel was forced to offer to replace. extensive error checking is the rule. This is a difficult problem in its own right. in cases that occurred very infrequently. Placement: The gates in the netlist are assigned to nonoverlapping locations on the die area. cores. The famous Pentium FDIV bug caused the results of a division to be wrong by at most 61 parts per million. In practice there is not a straightforward progression considerable iteration is required to ensure all objectives are met simultaneously. for free.
The first circuit simulator for analog ICs was called SPICE (Simulation Program with Integrated Circuits Emphasis). When inexpensive computer processing became available in the 1970s. computer programs were written to simulate circuit designs with greater accuracy than practical by hand calculation. analog ICs were designed using hand calculations. A simple CMOS Operational Amplifier Layout Analog design Before the advent of the microprocessor and software based design tools. Overall. computerized circuit simulation enables a higher degree of confidence that the circuit will work as expected upon manufacture. usually involving no more than ten transistors and few connections. 7 . The computerized circuit simulators also enable mistakes to be found early in the design cycle before a physical device is fabricated. Computerized circuit simulation tools enable greater IC design complexity than hand calculations can achieve. An iterative trial-and-error process and "overengineering" of device size was often necessary to achieve a manufacturable IC. op-amps are one example. permitting Monte Carlo analysis and process sensitivity analysis to be practical. a computerized circuit simulator can implement more sophisticated device models and circuit analysis too tedious for hand calculations. making the design of analog ASICs practical. The effects of parameters such as temperature variation. Additionally. Reuse of proven designs allowed progressively more complicated ICs to be built upon prior knowledge. These ICs were basic circuits.7 Process corners Process corners provide digital designers the ability to simulate the circuit while accounting for variations in the technology process. doping concentration variation and statistical process variations can be simulated easily to determine if an IC design is manufacturable.
To add to the design challenge. Unlike board-level circuit design which permits the designer to select devices that have each been tested and binned according to value. this fabrication variability forces certain design techniques and prevents the use of other design techniques familiar to the board-level designer. However. 8 . such as resistors.8 Coping with variability A challenge most critical to analog IC design involves the variability of the individual devices built on the semiconductor chip. Fortunately for IC design. The design techniques necessary to reduce the effects of the device variation are: • • • • • Using the ratios of resistors. device properties often vary between each processed semiconductor wafer. etc. some IC resistors can vary ±20% and β of an integrated BJT can vary from 20 to 100. For example. which do match closely. Segmenting large devices. uneven doping levels. Using devices with matched geometrical shapes so they have matched variations. into parts and interweaving them to cancel variations. Device properties can even vary significantly across each individual IC due to doping gradients. The underlying cause of this variability is that many semiconductor devices are highly sensitive to uncontrollable random variances in the process. the absolute values of the devices are less critical than the identical matching of device performance. can have large effects on device properties. Making devices large so that statistical variations becomes an insignificant fraction of the overall device property. Using common centroid device layout to cancel variations in devices which must match closely (such as the transistor differential pair of an op amp). Slight changes to the amount of diffusion time. rather than absolute resistor value. the device values on an IC can vary widely which are uncontrollable by the designer.
circuit simulation. full-custom layout editing. waveform probing. placement and routing. LVS and design rule checking (DRC) verification. 9 . netlist extraction.9 Tanner IC Work Flow Tanner Tools are fully-integrated solutions consisting of tools for schematic entry.
1. Simulate the layout using T-SPICE with a high-level spice model. Perform an LVS (Layout VS Schematic) to make sure your layout is functionally the same as the schematic you designed in S-EDIT. Simulate the schematic to make sure it behaves as you expect using T-SPICE. Layout the schematic in L-EDIT. What follows is a brief overview of the steps. making sure L-EDIT generates the parasitic capacitances so they are included in the simulation. There are four basic steps: Design the schematic in S-EDIT. 5. 4. 3.10 Introduction This document gives a rough overview of how to design & simulate things with Tanner Tools. 2. 10 .
Tanner’s schematic entry program. File -> new design Type the design name and locate it in a folder and click ok11 .11 S-EDIT Simulating Schematics in S-EDIT Run Tanner Tools S-Edit.
tanner).12 Add libraries from libraries toolbarAdd (all.0\Libraries\All 12 . This all folder is located at: My Documents\Tanner EDA\Tanner Tools v13. it includes complete library components.
13 Now we need to create a cell: 13 .
14 Give a name to cell0: (Inverter) Scroll mouse for zoom in and zoom out14 .
15 Click on devices for CMOS Inverter designSelect pmos and click on Instance With mouse device will attached. right click on workspace or done to go back 15 . place it by single click.
and paste Vdd and Gnd 16 .16 Similarly we can paste Nmos -> Properties of devices can be changed from properties toolbar. it is customizable Select misc from library toolbar.
17 Select SPICE_Elements then voltagesource, Type of voltage can be changed by instance cell, as follows
Paste one DC and one Pulse voltage source at workspace
Now connections can be made from wire selection 17
Just click on open node of device and wire the nodes accordingly
Now we need to add Input port and Output port 18
Now connect input, output port accordingly
md) with SPICE_commands -> include Hp05.0\L-Edit and LVS\LVS\SPR_Core\hp05.20 Now include SPICE_commands (printvoltage) from library & Connect this to input and output port to check waveform We need to include model file (hp05.md” 20 .md file location is inserted at value “C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.
click on component. then by pressing scroll button.21 Paste this include command anywhere at workspace To move a component anywhere at workspace. For simulation of design go to Setup-> spice_simulation Select Spice options (analysis) then define time parameter 21 . it can be moved anywhere. Now circuit is complete. Just save it.
then Select Tools-> start simulation 22 .22 Click OK.
23 T-SPICE It will automatically invoke T-Spice software Then simulation -> run simulation A Netlist file will be open as follows Spice commands can be inserted from Insert Command Button 23 .
24 24 .
It will automatically invoked at the time of running T-spice Waveform: Input and outputs are overlapped in this waveform. we can separate it by Expand chart 25 .25 W-EDIT Waveform can be checked Using W-Edit.
FFT can be seen from FFT Button 26 .26 Now check the waveform After selecting output.
27 27 .
28 L-EDIT CMOS Inverter Structure: - Double click on L-Edit. File -> new Now copy TDB (Tanner Data Base) file from browse 28 .
0\L-Edit and LVS\Tech\Mosis\morbn20.tdb And Click OK Goto cell -> new Name the cell-> 29 .29 Path for TDB File C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.
30 Grids spacing can be minimized or maximized using – or + sign To change the technology Goto setup-> Design Select Lambda or microns accordingly and click ok 30 .
31 Before designing layout we need to remember following equations N Diffusion = N select and Active – (1) P Diffusion = P select and Active . First draw active 31 .(2) From layer palette. we can select layer then for drawing layer we need to switch at Drawing boxes as follows Now we can start layout designing We are Taking Example of CMOS Layout design Background of L-Edit is P-Substrate by default We need to design PMOS.
32 Now draw P select over Active with keeping in mind Lambda based design rules Now draw poly over it accordingly Now draw metal1 to design Contact Now draw Active Contact for Active region 32 .
gate and drain Now we need to put this in N-Well We can perform DRC (Design Rule Check) at every stage 33 .33 We have designed source.
it will be shown in corresponding layout.34 If we are violating any Design rule then it will be shown in Error verification navigator On pointing any error. now we need to edit N-well We can check DRC at every stage 34 . as follows It is called lens.
we need to draw Poly contact To define port. go to (A) 35 . we need to design Gate contact In case of Poly Layer.35 Now we need to draw Body terminal. Gate contact After designing Body terminal (n select+ active+metal1+active contact).
36 .36 Type the name of port.
and after connecting these two.37 Similarly we can design N MOS. CMOS layout will look like as follows Now we can extract netlist by doing some settings 37 .
38 38 .
0\L-Edit and LVS\Tech\Mosis\morbn20.ext 39 . and Spice output file at desired location Location for .39 Now select Extract standard rule set. and click on pencil Now we need to include Extract file.ext file is C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.
select Names (writing nodes) 40 .40 Define location for output files In output.
41 Click ok.md file for analysis 41 . An spice file will open as follows We can open this spice file in T-Spice and can perform desired analysis We need to include hp05. now go to extract button Click on extract.
we can simulate it. W-Edit will invoked and we can check the response: 42 .tran 1ns 500ns After saving spice file.PRINT TRAN V(vin) .PRINT TRAN V(vout) .42 We need to insert some spice commands to perform transient analysis : VVoltageSource_1 Vdd Gnd DC 5 VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n) .
then ok We need to browse spice netlist files for layout netlist and Schematic netlist 43 . and file -> new & Select file type-> LVS setup.43 LVS (Layout Vs Schematic) We got two output files (one from S-Edit and second from L-Edit). Now we can compare results by using LVS Double click on LVS.
Both netlists are equal. 44 . we need to run verification as follows & Results can be checked from Verification Window.44 After including these files.
45 LAYOUT EXAMPLES: 1.0\hp05.75u M3 5 a gnd 4 NMOS L=1u W=2.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.75u M4 1 b 5 4 NMOS L=1u W=2.1u 100u .print tran v(1) v(a) v(b) . NAND gate: NAND gate layout Spice File: .md" M1 1 a vdd 7 PMOS L=1u W=2.END 45 .75u vdd vdd gnd 5 Va a gnd PULSE (0 5 0 100n 300n 3u 6u) Vb b gnd PULSE (0 5 0 100n 300n 6u 12u) .tran .75u M2 vdd b 1 7 PMOS L=1u W=2.
46 Waveform: 2. NOR Gate: 46 .
75u M3 5 a vdd 4 PMOS L=1u W=2.1u 100u .75u vdd vdd gnd 5 Va a gnd PULSE (0 5 0 100n 300n 3u 6u) Vb b gnd PULSE (0 5 0 100n 300n 6u 12u) .END Waveform: 47 .0\hp05.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.75u M2 gnd b outputa 7 NMOS L=1u W=2.md" M1 outputa a gnd 7 NMOS L=1u W=2.47 Spice File: .75u M4 outputa b 5 4 PMOS L=1u W=2.print tran v(outputa) v(a) v(b) .tran .
tran .48 3.5u M2 out a in 3 NMOS L=1u W=2.1u 40u . TRANSMISSION GATE: Spice File: .END Waveform: 48 .5u vdd vdd gnd 5v Vin in gnd PULSE (0 5 0 1u 1u 4u 10u) Va a gnd PULSE (0 5 0 1u 1u 4u 10u) .include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.print in out .0\hp05.md" M1 out a in 4 PMOS L=1u W=2.
75u M2 outputa b a 8 PMOS L=1u W=2.END 49 .49 4. XOR GATE USING TX GATES Spice File: .1u 40u .5u M4 outputa bbar a 6 NMOS L=1u W=3u M5 outputa b inta 6 NMOS L=1u W=3u M6 inta a 4 6 NMOS L=1u W=3u vdd vdd gnd 5v Va a gnd PULSE (0 5 0 1u 1u 4u 10u) Vb b gnd PULSE (0 5 0 1u 1u 4u 10u) Vbbar bbar gnd PULSE (5 5 0 1u 1u 4u 10u) .include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.75u M3 inta a vdd 7 PMOS L=1u W=2.print a bbar outputa .tran .0\hp05.md" M1 outputa bbar inta 10 PMOS L=1u W=2.
50 Waveform: 5. XNOR GATE 50 .
1u 40u .75u M4 out b a 6 NMOS L=1u W=3u M5 3 a gnd 6 NMOS L=1u W=3u M6 out bbar 3 6 NMOS L=1u W=3u vdd vdd gnd 5 Va a gnd PULSE (0 5 0 1u 1u 4u 10u) Vb b gnd PULSE (0 5 0 1u 1u 4u 10u) Vbbar bbar gnd PULSE (5 5 0 1u 1u 4u 10u) .print a bbar out .tran .md" M1 out b 3 10 PMOS L=1u W=2.END Waveform: 51 .0\hp05.51 Spice File: .5u M3 out bbar a 7 PMOS L=1u W=2.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.75u M2 3 a vdd 9 PMOS L=1u W=2.
52 6.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13. 4X1 MUX Spice File: .md" M1 out s2 16 9 PMOS L=1u W=5u M2 16 s1 B 7 PMOS L=1u W=5u M3 out s2bar 1 5 PMOS L=1u W=5u M4 1 s1bar A 3 PMOS L=1u W=5u M5 out s2 1 23 NMOS L=1u W=5u M6 1 s1 A 23 NMOS L=1u W=5u M7 out s2 11 31 PMOS L=1u W=5u M8 11 s1bar D 29 PMOS L=1u W=5u M9 out s2bar 14 27 PMOS L=1u W=5u M10 14 s1 C 25 PMOS L=1u W=5u M11 out s2bar 11 23 NMOS L=1u W=5u M12 11 s1 D 23 NMOS L=1u W=5u M13 out s2 14 23 NMOS L=1u W=5u M14 14 s1bar C 23 NMOS L=1u W=5u M15 out s2bar 16 23 NMOS L=1u W=5u M16 16 s1bar B 23 NMOS L=1u W=5u Va a gnd PULSE (0 5 0 0 0 2u 4u) Vb b gnd PULSE (0 5 0 0 0 4u 8u) Vc c gnd PULSE (0 5 0 0 0 8u 16u) Vd d gnd PULSE (0 5 0 0 0 16u 32u) Vs1 s1 gnd PULSE (0 5 0 0 0 16u 32u) 52 .0\hp05.
tran .END Waveform 53 .print v(s1) v(s2) v(out) .1u 200u .53 Vs1bar s1bar gnd PULSE (0 5 16u 0 0 16u 32u) Vs2bar s2bar gnd PULSE (0 5 32u 0 0 32u 64u) Vs2 s2 gnd PULSE (0 5 0 0 0 32u 64u) .
5p PD=4u AS=1.5p PD=8u AS=7.5p PS=4u M9 14 c gnd 16 NMOS L=1u W=3u AD=7.0\hp05. FULL ADDER Spice File: .5p PD=4u AS=7.5p PD=8u AS=1.5u M10 4 b 3 16 NMOS L=1u W=3u AD=1.5u AS=7.5p PD=8u AS=7.5p PS=8u M5 5 a 2 20 PMOS L=1u W=3u AD=1.5p PS=8u M12 3 a 2 16 NMOS L=1u W=3u AD=1.5p PS=8u 54 .54 7.5p PS=8u M15 12 c 13 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u M20 vdd a 13 20 PMOS L=1u W=3u AD=7.5p PD=4u AS=1.5p PS=8u M6 S0 2 vdd 20 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=4u AS=7.5p PS=4u M4 vdd b 17 20 PMOS L=1u W=3u AD=8.5p PD=8u AS=12p PS=14u M21 vdd 12 carry 20 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M22 12 c 11 16 NMOS L=1u W=3u AD=7.25p PD=8.5p PS=8u M14 2 12 14 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5u M3 6 b 5 20 PMOS L=1u W=3u AD=1.75p PD=14.5p PS=8u M19 19 a 12 20 PMOS L=1u W=3u AD=1.5p PD=8u AS=8.25p PD=8.5p PS=4u M11 gnd b 14 16 NMOS L=1u W=3u AD=8.5p PS=8u M18 17 a vdd 20 PMOS L=1u W=3u AD=7.5p PS=4u M2 17 c vdd 20 PMOS L=1u W=3u AD=7.5p PS=8u M7 2 12 17 20 PMOS L=1u W=3u AD=7.5p PS=8u M23 gnd b 15 16 NMOS L=1u W=3u AD=7.5u AS=7.5p PS=4u M24 11 b gnd 16 NMOS L=1u W=3u AD=7.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.5p PD=8u AS=7.25p PS=8.5p PD=8u AS=7.5p PS=8u M25 14 a gnd 16 NMOS L=1u W=3u AD=7.5p PS=8u M8 gnd c 4 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.25p PS=8.5p PS=8u M13 S0 2 gnd 16 NMOS L=1u W=3u AD=12.5p PD=8u AS=1.5p PD=8u AS=1.5p PD=8u AS=8.5p PS=8u M16 vdd b 19 20 PMOS L=1u W=3u AD=7.5p PD=4u AS=7.md" M1 vdd c 6 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=4u M17 13 b vdd 20 PMOS L=1u W=3u AD=7.5u AS=7.5p PD=8u AS=7.
tran 1m 100m va a gnd 0v vb b gnd 5v vc c gnd 5v .5p PD=8u AS=12p PS=14u M28 gnd 12 carry 16 NMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u vdd vdd gnd 5v .print tran v(a) v(s0) v(carry) .55 M26 15 a 12 16 NMOS L=1u W=3u AD=1.5p PS=8u M27 gnd a 11 16 NMOS L=1u W=3u AD=7.end Waveform 55 .5p PD=4u AS=7.
5u AS=7.md" M1 vdd c 6 22 PMOS L=1u W=3u AD=7.5u AS=7.5p PD=8u AS=1.5p PS=4u M23 9 b0 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M10 2 16 8 69 NMOS L=1u W=3u AD=7.5p PS=4u M2 6 b0 5 22 PMOS L=1u W=3u AD=1.56 8.25p PD=8.5p PD=8u AS=7.25p PS=8.5p PD=8u AS=12p PS=14u M19 gnd c 8 69 NMOS L=1u W=3u AD=8.5p PD=8u AS=7.5p PS=8u M20 16 c 9 69 NMOS L=1u W=3u AD=7.5u AS=7.5p PD=8u AS=1.5p PS=4u M15 11 b0 vdd 22 PMOS L=1u W=3u AD=7.5p PS=8u M11 vdd c 10 22 PMOS L=1u W=3u AD=8.5p PS=4u M8 3 a0 2 69 NMOS L=1u W=3u AD=1.5p PS=8u M26 gnd a0 9 69 NMOS L=1u W=3u AD=7.5p PS=8u M18 vdd a0 11 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u M6 gnd c 4 69 NMOS L=1u W=3u AD=7.5p PS=8u M4 s0 2 vdd 22 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=4u M7 4 b0 3 69 NMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PS=4u M28 28 c0 vdd 35 PMOS L=1u W=3u AD=7.5p PD=4u AS=1.5p PD=8u AS=7.5p PD=4u AS=7.25p PD=8.5p PD=8u AS=1.5p PD=8u AS=12p PS=14u M27 vdd c0 23 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=1.5p PS=8u M22 gnd b0 12 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=7.5p PD=4u AS=7.5p PS=8u M25 12 a0 16 69 NMOS L=1u W=3u AD=1.5p PD=8u AS=7.25p PD=8.5u M29 vdd 16 c0 22 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u 56 .5p PS=8u M24 8 a0 gnd 69 NMOS L=1u W=3u AD=7.0\hp05.5p PD=4u AS=1.5p PS=8u M21 gnd b0 8 69 NMOS L=1u W=3u AD=8.5p PS=8u M14 vdd b0 14 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PD=4u AS=7.5p PS=8u M9 s0 2 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5u AS=7.25p PD=8.5p PS=8u M17 14 a0 16 22 PMOS L=1u W=3u AD=1.5p PS=8u M13 vdd b0 10 22 PMOS L=1u W=3u AD=8.5p PD=8u AS=8.5p PS=4u M3 5 a0 2 22 PMOS L=1u W=3u AD=1. Four Bit Parallel Adder Spice File: .5p PS=8u M16 10 a0 vdd 22 PMOS L=1u W=3u AD=7.5p PS=8u M12 16 c 11 22 PMOS L=1u W=3u AD=7.5p PS=8u M5 2 16 10 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.
5p PD=4u AS=1.5p PS=4u M72 46 b2 vdd 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PD=4u AS=1.5p PS=8u M34 gnd c0 20 69 NMOS L=1u W=3u AD=7.5u AS=7.25p PS=8.5p PS=8u M68 34 44 42 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u M48 vdd 27 c1 35 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M49 27 c0 26 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5u AS=7.5p PS=8u M55 gnd a1 26 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=7.5p PS=8u M53 25 a1 gnd 69 NMOS L=1u W=3u AD=7.5p PS=4u M66 37 a2 34 69 NMOS L=1u W=3u AD=1.5p PS=8u M70 vdd b2 45 54 PMOS L=1u W=3u AD=8.5p PS=4u M35 25 c0 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M40 17 27 25 69 NMOS L=1u W=3u AD=7.5p PS=8u M71 vdd b2 50 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u M43 vdd b1 32 35 PMOS L=1u W=3u AD=7.5p PS=4u M31 21 a1 17 35 PMOS L=1u W=3u AD=1.5u AS=7.5p PD=8u AS=7.5p PD=8u AS=7.5p PS=8u M61 s2 34 vdd 54 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=4u AS=7.5p PD=8u AS=7.5p PS=8u M74 50 a2 44 54 PMOS L=1u W=3u AD=1.5u M36 gnd 16 c0 69 NMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M37 20 b1 19 69 NMOS L=1u W=3u AD=1.5p PS=4u M52 26 b1 gnd 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=1.5p PD=4u AS=7.5p PS=8u M45 28 a1 vdd 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5u M65 38 b2 37 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PD=8u AS=1.5p PS=4u M64 42 c1 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M73 45 a2 vdd 54 PMOS L=1u W=3u AD=7.5p PS=8u M75 vdd a2 46 54 PMOS L=1u W=3u AD=7.5p PS=8u M78 gnd b2 42 69 NMOS L=1u W=3u AD=8.5p PD=8u AS=12p PS=14u M56 gnd 27 c1 69 NMOS L=1u W=3u AD=13.5p PD=8u AS=8.5p PS=8u M41 27 c0 29 35 PMOS L=1u W=3u AD=7.5p PD=4u AS=1.5p PS=8u M42 vdd b1 28 35 PMOS L=1u W=3u AD=8.5p PD=4u AS=7.5p PS=8u M33 17 27 28 35 PMOS L=1u W=3u AD=7.5p PS=4u 57 .5p PD=4u AS=7.5p PD=8u AS=1.5p PS=8u M50 gnd b1 25 69 NMOS L=1u W=3u AD=8.5p PS=8u M62 34 44 45 54 PMOS L=1u W=3u AD=7.5p PS=4u M44 29 b1 vdd 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PD=8u AS=7.5p PS=8u M63 gnd c1 38 69 NMOS L=1u W=3u AD=7.25p PS=8.25p PS=8.5p PS=4u M58 45 c1 vdd 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=1.25p PD=8.5p PS=8u M46 32 a1 27 35 PMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PD=8u AS=7.5p PS=4u M38 19 a1 17 69 NMOS L=1u W=3u AD=1.5p PS=8u M51 gnd b1 30 69 NMOS L=1u W=3u AD=7.25p PD=8.5p PS=8u M32 s1 17 vdd 35 PMOS L=1u W=3u AD=12p PD=14u AS=7.57 M30 23 b1 21 35 PMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PS=8u M47 vdd a1 29 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.5p PD=8u AS=7.25p PD=8.25p PD=8.5p PS=8u M39 s1 17 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=8u AS=7.5p PD=8u AS=1.5u AS=7.5p PD=4u AS=7.5p PD=8u AS=7.5p PD=8u AS=12p PS=14u M76 vdd 44 c2 54 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M77 44 c1 43 69 NMOS L=1u W=3u AD=7.5p PS=8u M79 gnd b2 47 69 NMOS L=1u W=3u AD=7.5p PD=15u AS=12p PS=14u M57 vdd c1 40 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.5p PS=8u M69 44 c1 46 54 PMOS L=1u W=3u AD=7.5p PS=8u M67 s2 34 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5u M59 40 b2 39 54 PMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PS=8u M54 30 a1 27 69 NMOS L=1u W=3u AD=1.5p PS=4u M60 39 a2 34 54 PMOS L=1u W=3u AD=1.
5p PD=8u AS=1.25p PS=8.tran 1m 100m va0 a0 gnd 0v vb0 b0 gnd 5v vc c gnd 5v va1 a1 gnd 5v vb1 b1 gnd 0v va2 a2 gnd 0v vb2 b2 gnd 5v va3 a3 gnd 5v vb3 b3 gnd 0v .5p PS=8u M91 53 63 64 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.5p PS=8u M90 s3 53 vdd 72 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=8u AS=7.25p PS=8.5p PS=8u M98 53 63 61 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=12p PS=14u M84 gnd 44 c2 69 NMOS L=1u W=3u AD=15p PD=16u AS=12p PS=14u M85 vdd c2 60 72 PMOS L=1u W=3u AD=7.5p PS=4u M108 62 b3 gnd 69 NMOS L=1u W=3u AD=7.5p PS=4u M95 gnd b3 61 69 NMOS L=1u W=3u AD=8.5p PS=4u M88 vdd b3 64 72 PMOS L=1u W=3u AD=8.end 58 .5p PD=8u AS=7.5p PD=8u AS=7.5u M87 60 b3 59 72 PMOS L=1u W=3u AD=1.5p PS=8u M96 57 a3 53 69 NMOS L=1u W=3u AD=1.5p PS=8u M111 gnd a3 62 69 NMOS L=1u W=3u AD=7.5p PS=4u M101 65 b3 vdd 72 PMOS L=1u W=3u AD=7.5p PS=8u M102 64 a3 vdd 72 PMOS L=1u W=3u AD=7.25p PD=8.5p PD=4u AS=7.5p PD=8u AS=7.5u AS=7.5p PD=4u AS=7.5p PS=8u M109 61 a3 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M82 47 a2 44 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PD=8u AS=1.5p PS=8u M89 59 a3 53 72 PMOS L=1u W=3u AD=1.5p PS=8u M110 68 a3 63 69 NMOS L=1u W=3u AD=1.5p PS=8u M97 s3 53 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=4u AS=1.5p PD=8u AS=8.5p PD=8u AS=1.5p PD=8u AS=7.5p PD=4u AS=1.5p PD=8u AS=1.5p PS=8u M83 gnd a2 43 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u M105 vdd 63 c3 72 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M106 63 c2 62 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5u AS=7.5p PS=8u M81 42 a2 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M100 vdd b3 71 72 PMOS L=1u W=3u AD=7.5p PS=4u M86 64 c2 vdd 72 PMOS L=1u W=3u AD=7.5p PS=8u M104 vdd a3 65 72 PMOS L=1u W=3u AD=7.5p PD=4u AS=7.5p PS=4u M93 61 c2 gnd 69 NMOS L=1u W=3u AD=7.print tran v(s0) v(s1) v(s2) v(s3) v(c3) .5p PD=8u AS=7.25p PD=8.5u M94 58 b3 57 69 NMOS L=1u W=3u AD=1.5p PS=8u M92 gnd c2 58 69 NMOS L=1u W=3u AD=7.5p PS=8u M99 63 c2 65 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u M112 gnd 63 c3 69 NMOS L=1u W=3u AD=13.5p PD=8u AS=7.5p PD=15u AS=12p PS=14u vdd vdd gnd 5v .58 M80 43 b2 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u M103 71 a3 63 72 PMOS L=1u W=3u AD=1.5p PS=8u M107 gnd b3 68 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=7.
59 Waveform: 59 .
Ltd.Hyderabad Trident Techlabs Pvt.varma@tridenttechlabs. 60 . Ltd.EDA Mob. : +91-9989993522 E-Mail: p..60 THANK YOU Phanendra Varma Gunturi Application Engineer.com Trident Techlabs Pvt.
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