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A

Compal Confidential
2

KAV10 Schematics Document


Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M

2008-12-30

l.c
om

REV: 1.0

Cover Page

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2007/8/18

Deciphered Date

Document Number

Rev
1.0

KAV10 LA-4781P

he

2006/08/18

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

Tuesday, December 30, 2008

Sheet

of

40

Diamondville SC

Compal Confidential

FCBGA8
437Pins

Model Name : KAV10


File Name : LA-4781P
P/N : DA60000A600(R0)
DA60000A610(R1)
DAZ06F00100

22x22mm
CRT Conn

FSB

H_A#(3..31)

Memory BUS(DDRII)

Calistoga GSE
FCBGA998

DDRII-SO-DIMM
page 11

1.8V DDRII 400/533

LVDS

LCD Conn.

Thermal Sensor

Clock Generator
CK505
page 12

H_D#(0..63)

400/533MHz

page 14

RGB

page 4,5

27x27mm

page 13

page 6,7,8,9,10

EMC1402
page 2

DMI
X2 mode
2

USB Port X1

page 28

USB
HDA

ICH7M
BGA652

PCI-Express

USB Board X2
USB Card
Reader X1
RTS5158E

31x31mm

page 23

page 15,16,17,18

SDIO CONN

MINI Card x2

10/100 Ethernet

SATA

BlueToothX1

page19

AR8114A

page 27
page 19

page 28

SATA HDD CONN

page 24

CMOS CAM

page 22

page22

LPC BUS
WLANX1

Transfermer

page19

page 24

WWANX1

Aralia Codec

page19

ALC272

Power ON/OFF
& LED CONN

page 20

RJ45

DC/DC Interface
page 29

page 24

page 26

ENE KBC
KB926page

3VALW/5VALW
page 33

DC IN

page 31

SPI
25

1.5VS/0.9VS/
2.5VS

BATT IN

AMP & INT


Speaker
page 21

page 36,37

page 32

Int.KBD
CHARGER

1.8V/VCCP

page 34

SPI ROM

page 27

page 20

HeadPhone &
MIC Jack
page 21

page 25

Touch Pad

page 35

INT DMIC

page 27

CPU_CORE

page 38
2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
1.0

KAV10 LA-4781P
Tuesday, December 30, 2008

Sheet
E

of

40

Voltage Rails

External PCI Devices

Power Plane

Description

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+0.9VS

0.9V switched power rail for DDR terminator

ON

OFF

OFF

+VCCP

VCCP switched power rail

ON

OFF

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF
OFF

+1.8V

1.8V power rail for DDR

ON

ON

+2.5VS

2.5V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

DEVICE

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

PIRQ

EC SM Bus1 address

+VALW

+V

+VS

Clock

Full ON

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

HIGH

HIGH

HIGH

ON

ON

ON

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S3 (Suspend to RAM)

REQ/GNT #

No PCI Device

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

IDSEL #

S4 (Suspend to Disk)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

ON

OFF

OFF

OFF

EC SM Bus2 address

Device

Address

Device

Address

Smart Battery

0001 011X b

EMC1402

1001 100X b

EEPROM(24C16/02)

1010 000X b

ICH7M SM Bus address

BOARD ID Table(Page 25)


ID

R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)

Ra

NC
100K
100K
100K

Rb

0
8.2K
18K
NC

Vab

0V
0.25V
0.50V
3.3V

Device

Address

Clock Generator
(SLG8SP556VTR)

1101 001Xb

DDR DIMMA

1010 000Xb

l.c
om

0
1
2
3

BRD ID

Notes List

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2007/8/18

Deciphered Date

Document Number

Rev
1.0

KAV10 LA-4781P

he

2006/08/18

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

Tuesday, December 30, 2008

Sheet

of

40

<6> H_A#[3..16]
<6> H_D#[0..15]

<16> H_A20M#
<16> H_FERR#
<16> H_IGNNE#
<16> H_STPCLK#
<16> H_INTR
<16> H_NMI
<16> H_SMI#

T20

H_BR0#

IERR#
INIT#

F16
V16

H_IERR#
H_INIT#_R

LOCK#

W20

H_LOCK#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

D15
W18
Y17
U20
W19

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

AA17
V20

H_HIT#
H_HITM#

R27
330_0402_5%

H_BR0# <6>
R33 1

2 1K_0402_5%

H_LOCK# <6>

H_INIT# <16>

Close to CPU

H_RESET# <6>

H_RS#[0..2] <6>
<6> H_DSTBN#0
<6> H_DSTBP#0
<6> H_DINV#0

H_TRDY# <6>
<6> H_D#[16..31]

K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15

PROCHOT#
THRMDA
THRMDC

G17
E4
E5

H_PROCHOT#_R
H_THERMDA
H_THERMDC

THERMTRIP#

H17

H_THERMTRIP#

PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#

1
R202

2
22_0402_5%

<6> H_DSTBN#1
<6> H_DSTBP#1
<6> H_DINV#1

H_PROCHOT# <38>

Close to CPU

BCLK[0]
BCLK[1]

CLK_CPU_BCLK
CLK_CPU_BCLK#

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_DP#1

AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1

A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5

GTLREF
ACLKPH
DCLKPH
BINIT#
MISC
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]

T13 PAD

H_THERMTRIP# <6,16>
+CPU_GTLREF

V11
V12

Y11
W10
Y12
AA14
AA11
W12
AA16
Y10
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
V9

T10 PAD

H_HIT# <6>
H_HITM# <6>

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
BR1#

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DP#0

CLK_CPU_BCLK <12>
CLK_CPU_BCLK# <12>

R240 1
R239 1

@
@

2 1K_0402_5%
2 1K_0402_5%

ACLKPH
DCLKPH

+CPU_EXTBGREF

C21
C1
A3

RSVD3
RSVD2
RSVD1

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

<12> CPU_BSEL0
<12> CPU_BSEL1
<12> CPU_BSEL2

C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4

COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
CORE_DET
CMREF[1]

T1
T2
F20
F21

H_DSTBN#2 <6>
H_DSTBP#2 <6>
H_DINV#2 <6>
T15

H_D#[48..63]

<6>

H_DSTBN#3 <6>
H_DSTBP#3 <6>
H_DINV#3 <6>
T12
R57
R58
R208
R209

27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%

2
2
1
1

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#

R18
R17
U4
V17
N18
A13
B7

<6>

H_DPRSTP# <16,38>
H_DPSLP# <16>
H_DPWR# <6>
H_PWRGOOD <16>
H_CPUSLP# <6>
+CPU_CMREF

+VCCP

2
1

1
R48
2K_0402_1%
2

C62
0.1U_0402_16V4Z

R51
1K_0402_1%

+CPU_CMREF

1K_0402_5% H_A20M#
1K_0402_5% H_IGNNE#

R234
1K_0402_1%

+CPU_EXTBGREF

C342
1U_0402_6.3V4Z

Zo=27.4ohm +/-15%, make


than 0.5"
Zo=55ohm +/-15%, make
than0.5"

1
R238
2K_0402_1%

C65
0.1U_0402_16V4Z

R49
2K_0402_1%
2

R47
1K_0402_1%

+CPU_GTLREF

2
2

H_A#32
H_A#33
H_A#34
H_A#35

+VCCP

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DP#3

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_DP#2
PAD
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
H_DP#3
PAD
COMP0
1
COMP1
1
COMP2
2
COMP3
2

Layout note:
COMP0,2 connect with
trace length shorter
COMP1,3 connect with
trace length shorter

+VCCP

1
1

R28
R32

1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%

+VCCP

2
2
2
2

+VCCP

+VCCP

1
1
1
1

R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4

AU80586GE025512_FCBGA437

AU80586GE025512_FCBGA437

R34
R30
R31
R29

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DP#2

DATA GRP 2

1
R201
56_0402_5%
2

NC1
NC2
NC3
NC4
NC5
NC6
NC7

D6
G6
H6
K4
K5
M15
L16

H_DEFER# <6>
H_DRDY# <6>
H_DBSY# <6>
2

A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#

H_DEFER#
H_DRDY#
H_DBSY#

CONTROL

U18
T16
J4
R16
T15
R15
U17

T21
T19
Y18

HIT#
HITM#

THERM
XDP/ITP SIGNALS

H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#

PAD

DEFER#
DRDY#
DBSY#

H_D#[32..47]

U5B

+VCCP

H CLK

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1

H_ADS# <6>
H_BNR# <6>
H_BPRI# <6>

DATA GRP 1

T7

C19
F19
E21
A16
D19
C14
C18
C20
E20
D20
B18
C15
B16
B17
C16
A17
B14
B15
A14
B19
M18

H_ADS#
H_BNR#
H_BPRI#

BR0#

ADDR GROUP 1

<6> H_ADSTB#1
C

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1

V19
Y19
U21

NC

<6> H_A#[17..31]

+VCCP

ADS#
BNR#
BPRI#

DATA GRP 0

<6> H_ADSTB#0
<6> H_REQ#[0..4]

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
AP0
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

ADDR
GROUP
0

P21
H20
N20
R20
J19
N19
G20
M19
H21
L20
M20
K19
J20
L21
K20
D17
N21
J21
G19
P20
R19

DATA GRP 3

U5A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_AP0
T5
PAD H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

This shall place near CPU


R200
R198
R206
R199
R205

1
1
1
1
1

2 56_0402_5%
2 56_0402_5%
2@ 56_0402_5%
2 56_0402_5%
2 68_0402_5%

ITP_TMS
ITP_TDI
PREQ#
ITP_TDO
H_PROCHOT#

Close to CPU pin


within 500mils.
Zo=55ohm

Close to CPU pin


within 500mils.
Zo=55ohm

Close to CPU pin


within 500mils.
Zo=55ohm

H_THERMDA, H_THERMDC routing together.


Trace width / Spacing = 10 / 10 mil

Modify schematic by 10/21


2 56_0402_5%
2 56_0402_5%

+3VS

ITP_TCK
ITP_TRST#

0.1U_0402_16V4Z

R213 1
R218 1

C351
1
2

CPU THERMAL SENSOR

1
C352
U17

2
1
H_THERMDA

H_THERMDC
2200P_0402_50V7K

3
4

VDD

SMCLK

DP

SMDATA

DN

ALERT#

THERM#

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 <25>
EC_SMB_DA2 <25>

R304 1
10K_0402_5%

+3VS

GND

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Diamondville(1/2)
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
1

of

40

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32

C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14

VCCPC64
VCCPC63
VCCPC62
VCCPC61

F14
F13
E14
E13

+VCCP

V10
A9
B9

VCCF
VCCQ1
VCCQ2

+CPU_CORE

A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12

VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45

0.1U_0402_16V7K

1U_0402_6.3V6K

1
C295

C307

C337

0.1U_0402_16V7K

C341

C57

1U_0402_6.3V6K

2
220U_B2_2.5VM_R35

PLACE IN CAVITY

+1.5VS

130mA
VCCA

D7

+1.5VS

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

F15
D16
E18
G15
G16
E17
G18

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

VCCSENSE

C13

VCCSENSE

VSSSENSE

D13

VSSSENSE

1
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

<38>
<38>
<38>
<38>
<38>
<38>
<38>

C338
0.1U_0402_16V7K

+CPU_CORE

N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20

R221
100_0402_1%

+VCCP

U5C

VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95

Length match within 25 mils


The trace space 7 mils,
Zo=27.4ohm

VCCSENSE <38>
VSSSENSE <38>

AU80586GE025512_FCBGA437

100_0402_1%

+CPU_CORE

+CPU_CORE

2 x 330uF(9mohm/2)

PLACE IN CAVITY
1U_0402_6.3V6K
C308

C309

C310

1U_0402_6.3V6K

C311

C312

1U_0402_6.3V6K

C313

C314

1U_0402_6.3V6K

C320

C321

1U_0402_6.3V6K

C322

C323

1U_0402_6.3V6K

C324

C326

1U_0402_6.3V6K

C327

C325

1U_0402_6.3V6K

C315

+ C51

AU80586GE025512_FCBGA437

+ C331

330U_D2_2.5VY_R9M
2

10U_0805_10V4Z
C298

C299

2
10U_0805_10V4Z

1U_0402_6.3V6K

C300

10U_0805_10V4Z

C301

2
10U_0805_10V4Z

1U_0402_6.3V6K

C302

1U_0402_6.3V6K

10U_0805_10V4Z

C46

10U_0805_10V4Z

C304

1U_0402_6.3V6K

10U_0805_10V4Z

C303

C335

10U_0805_10V4Z

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_10V4Z

C328

C334

10U_0805_10V4Z

l.c
om

330U_D2_2.5VY_R9M
2 @

10U_0805_10V4Z

ai

2
1U_0402_6.3V6K

R220

VSS1
VSS2
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS41
VSS42
VSS45
VSS46
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84

U5D

A2
A4
A8
A15
A18
A19
A20
B1
B2
B5
B8
B13
B20
B21
C8
C17
D1
D5
D8
D14
D18
D21
E3
E6
E7
E8
E15
E16
E19
F4
F5
F6
F7
F17
F18
G1
G4
G7
G9
G13
G21
H3
H4
H7
H9
H13
H16
H18
H19
J5
J7
J9
J13
J17
K1
K6
K7
K9
K13
K15
K21
L3
L4
L5
L6
L7
L9
L13
L15
L18
L19
M1
M5
M7
M9
M13
M21
N4

ho

tm

PLACE IN CORRIDOR AND CLOSE TO CPU

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Diamondville(2/2)
Size
B
Date:

Document Number

in

2007/8/18

Rev
1.0

xa

Deciphered Date

KAV10 LA-4781P

he

2006/08/18

Issued Date

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Tuesday, December 30, 2008

Sheet
1

of

40

R6
54.9_0402_1%
2
1

+VCCP

H_XRCOMP
H_XSCOMP
+H_SWNG0
H_YRCOMP
H_YSCOMP
+H_SWNG1

R7
24.9_0402_1%
2
1

R182
24.9_0402_1%
2
1

A10
A6
C15
J1
K1
H1

HCLKN
HCLKP
H_DBSY#
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

F10
C12
H16
E2
B9
C7
G8
B10
E1

H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF

AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3

CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DBSY#
H_DEFER#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DPWR#
H_DRDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10

H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#

U1B
<17>
<17>
<17>
<17>

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

<17>
<17>
<17>
<17>

DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1

DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1

Y29
Y32
Y28
Y31

DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1

DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1

V28
V31
V29
V32

DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1

M_CLK_DDR0
M_CLK_DDR1

<11> M_CLK_DDR0
<11> M_CLK_DDR1

M_CLK_DDR#0
M_CLK_DDR#1

<11> M_CLK_DDR#0
<11> M_CLK_DDR#1

AF33
AG1

SM_CK_0
SM_CK_1

AJ1
AM30

SM_CK_2
SM_CK_3

AG33
AF1
AK1
AN30

<11> DDR_CKE0
<11> DDR_CKE1

<11> DDR_CS0#
<11> DDR_CS1#

H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_RESET# <4>
CLK_MCH_BCLK# <12>
CLK_MCH_BCLK <12>
H_DBSY# <4>
H_DEFER# <4>
H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>
H_DPWR# <4>
H_DRDY# <4>

<11> M_ODT0
<11> M_ODT1

+1.8V

R232 1
1
R228

2 80.6_0402_1%
2
80.6_0402_1%

+DIMM_VREF

H_DSTBN#[0..3] <4>

SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3

DDR_CKE0
DDR_CKE1

AN21
AN22
AF26
AF25

DDR_CS0#
DDR_CS1#

AG14
AF12
AK14
AH12
AJ21
AF11

SM_OCDCOMP_0
SM_OCDCOMP_1

M_ODT0
M_ODT1

AE12
AF14
AJ14
AJ12

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SMRCOMPN
SMRCOMPP

AN12
AN14
AA33
AE1

SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1

10uA
1

CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6

C18
E18
G20
G18
J20
J18

RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9

K32
K31
C17
F18
A3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

Layout Note:
+DIMM_VREF trace
width and spacing
is 20/20.

CFG/RSVD

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#

E31
G21
F26
H26
J15
AB29
W27

D_REFCLKN
D_REFCLKP
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#

A27
A26
J33
H33
J22

PM

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF0
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_VREF1

F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17

DMI

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

DDR2 MUXING

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

C55
0.1U_0402_16V4Z

C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
M5
K5
J5
H3
J4
N3
M4
M3
N8
N6
K3
N9
M1
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
W2
W1
V2
W4
W7
W5
V5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5

HOST

R175
54.9_0402_1%
2
1

H_A#[3..31] <4>

U1A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

C53
0.1U_0402_16V4Z

<4> H_D#[0..63]

CLK

H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

H_RS#[0..2]

2.2K_0402_5%

MCH_ICH_SYNC# <15>
PM_BMBUSY# <17>
PM_EXTTS#0
PM_EXTTS#0 <11>
PM_EXTTS#12
1
PM_DPRSLPVR <17,38>
R203 0_0402_5%
H_THERMTRIP#
H_THERMTRIP# <4,16>
ICH_POK
ICH_POK
<17,25>
PLTRST_R# 1
2
PLTRST# <15,17,19,24,25,27>
R211 100_0402_5%

CLK_MCH_DREFCLK# <12>
CLK_MCH_DREFCLK <12>
MCH_SSCDREFCLK# <12>
MCH_SSCDREFCLK <12>
MCH_CLKREQ# <12>

Strap Pin Table

H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>

H_REQ#[0..4]

MCH_CLKSEL0 <12>
MCH_CLKSEL1 <12>
MCH_CLKSEL2 <12>

Calistoga-GSE_FCBGA998

H_DSTBP#[0..3] <4>
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
@ PAD T32
CFG5
1
2
CFG6
R181
@ PAD T33

CFG5

Low

= DMI x 2

High = DMI x 4

<4>
<4>

H_CPUSLP# <4>
H_TRDY# <4>

Calistoga-GSE_FCBGA998

+3VS

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

PM_EXTTS#0
PM_EXTTS#1

+VCCP

1
R187
@
1
R188

2
10K_0402_5%
2
10K_0402_5%

+VCCP

1
R180

221_0402_1%

221_0402_1%

R167

100_0402_1%

+H_SWNG1

0.1U_0402_16V4Z
C251

1
R178
2

100_0402_1%

0.1U_0402_16V4Z
C240

1
2

100_0402_1%

C50 be placed <100mils


from GMCH pin

R166

C243

0.1U_0402_16V4Z

2
1
2

+H_SWNG0

+H_VREF
200_0402_1%

R174

R176

+VCCP

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Calistoga(1/5)-GTL/DMI/DDR
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
1

of

40

<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2
<11> DDR_A_DM[0..7]

<11> DDR_A_DQS[0..7]

<11> DDR_A_DQS#[0..7]

<11> DDR_A_MA[0..13]

<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_WE#

T9
T8

PAD
PAD

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

AK12
AH11
AG17

SA_BS_0
SA_BS_1
SA_BS_2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AB30
AL31
AF30
AK26
AL9
AG7
AK5
AH3

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AC28
AJ30
AK33
AL25
AN9
AH8
AM2
AE3

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AC29
AK30
AJ33
AM25
AN8
AJ8
AM3
AE2

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

AJ17
AK18
AN28
AM28
AH17

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#

AH21
AJ20
AE27
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20

DDR2 SYSTEM MEMORY

U1C

SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SB_CAS#
SB_RAS#
SB_WE#

AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]

<11>

AG19
AG21
AG20

l.c
om

Calistoga-GSE_FCBGA998

ho

tm

ai

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Calistoga(2/5)-DDR2

in

2007/8/18

Size Document Number


Custom
Date:

xa

Deciphered Date

Rev
1.0

KAV10 LA-4781P

he

2006/08/18

Issued Date

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Tuesday, December 30, 2008

Sheet
1

of

40

U1F

CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF

H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29

L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL

LVDS_ACLK#
LVDS_ACLK

D30
C30
A30
A29

LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP

<13> LVDS_A0#
<13> LVDS_A1#
<13> LVDS_A2#

LVDS_A0#
LVDS_A1#
LVDS_A2#

G31
F32
D31

LA_DATAN_0
LA_DATAN_1
LA_DATAN_2

<13> LVDS_A0
<13> LVDS_A1
<13> LVDS_A2

LVDS_A0
LVDS_A1
LVDS_A2

H31
G32
C31

LA_DATAP_0
LA_DATAP_1
LA_DATAP_2

F33
D33
F30

LB_DATAN_0
LB_DATAN_1
LB_DATAN_2

E33
D32
F29

LB_DATAP_0
LB_DATAP_1
LB_DATAP_2

<14> GMCH_CRT_G
<14> GMCH_CRT_R

Close to U4.H25
2
R183

1
255_0402_1%
R171 2

<14> GMCH_CRT_VSYNC
<14> GMCH_CRT_HSYNC

2
R184

<13> LVDS_SCL
<13> LVDS_SDA
<13> GMCH_ENVDD
1
1.5K_0402_1%

<13> LVDS_ACLK#
<13> LVDS_ACLK

+3VS

1
R192
1
R191

GMCH_CRT_G
GMCH_CRT_R

CRT_IREF

1 100K_0402_5%

<25> GMCH_ENBKL

GMCH_CRT_B

LCTLA_CLK
2
10K_0402_5%
LCTLB_DATA
2
10K_0402_5%

LCTLA_CLK
LCTLB_DATA
LVDS_SCL
LVDS_SDA
L_IBG

SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#

N30
R30
T29

SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL

M30
P30
T30

SDVO

H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25

<14> GMCH_CRT_CLK
<14> GMCH_CRT_DATA
<14> GMCH_CRT_B

EXP_A_COMPI
EXP_A_ICOMPO

R28
M28

SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN

P28
N32
P32
T32

SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP

N28
M32
P33
R32

PEGCOMP

+1.5VS_PCIE
R190
24.9_0402_1%
2

+1.5VS

TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

A21
C20
E20
G23
B21
C21
D21

TV_DCONSEL0
TV_DCONSEL1

G26
J26

TV

MISC

R9

SDVO_CTRLDATA
SDVO_CTRLCLK
G_CLKN
G_CLKP

VGA

R8

<12> CLK_MCH_3GPLL#
<12> CLK_MCH_3GPLL

GMCH_CRT_R
150_0402_1%
GMCH_CRT_G
1
150_0402_1%
GMCH_CRT_B
1
150_0402_1%

LVDS

R10

H27
J27
Y26
AA26

Disable TV

Calistoga-GSE_FCBGA998

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Issued Date

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Calistoga(3/5)-VGA/LVDS/TV
Size
B
Date:

Document Number

Rev
1.0

KAV10 LA-4781P
Tuesday, December 30, 2008

Sheet
1

of

40

+1.5VS
U1E

+VCCP

T10
R10
P10
N10
L10
D1
M10
A18
AB10
AA10

VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
RSVD_3
RSVD_4
RSVD_5
RSVD_6

NCTF

CFG_19
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25

AH33
Y33
V33
R33
G33
AK32
AG32
AE32
AC32
AA32
U32
H32
E32
C32
AM31
AJ31
AA31
U31
T31
R31
P31
N31
M31
J31
F31
AL30
AG30
AE30
AC30
AA30
Y30
V30
U30
G30
E30
B30
AA29
U29
R29
P29
N29
M29
H29
E29
B29
AK28
AH28
AE28
AA28
U28
T28
J28
D28
AM27
AF27
AB27
AA27
Y27
U27
T27
R27
P27
N27
M27
G27
E27
C27
B27
AL26
AH26
W26
U26
AN25
AK25
AG25
AE25
J25
G25
A25
H23
F23
B23
AM22
AJ22
AF22
G22
E22
J21
H21
F21
AM20
AK20
AH20
AF20
D20
W19
R19
AM18
AH18
AF18
U18
H18
D18
AK17
V17
T17
F17
B17
AH16
U16

K28
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15

Calistoga-GSE_FCBGA998

U1G

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110

VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185

J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1

W33
AM33
AL33
C33
B33
AN32
A32
AN31
W28
V27
W29
J24
H24
W32
G24
F24
E24
D24
K33
A31
E21
C23
AN19
AM19
AL19
AK19
AJ19
AH19
AN3
Y9
J19
H19
G19
F19
E19
D19
C19
B19
A19
Y8
G16
F16
E16
D16
C16
B16
AN2
A16
Y7
AM4
AF4
AD4
AL4
AK4
W31
AJ4
AH4
AG4
AE4
AM1

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC56
NC57
NC58
NC59
NC60

NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72

W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18

RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42

Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17

Calistoga-GSE_FCBGA998

l.c
om

VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19

ai

VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64

AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1

VSS

U1H
T25
R25
P25
N25
M25
P24
N24
M24
Y22
W22
V22
U22
T22
R22
P22
N22
M22
Y21
W21
V21
U21
T21
R21
P21
N21
M21
Y20
W20
V20
U20
T20
R20
P20
N20
M20
Y19
P19
N19
M19
Y18
P18
N18
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14
W14
V14
U14
T14
R14
P14
N14
M14

NC

+VCCP

Calistoga(4/5)-PWR/GND

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size Document Number
Custom
Date:

xa

2007/8/18

Deciphered Date

Rev
1.0

KAV10 LA-4781P

he

2006/08/18

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

Calistoga-GSE_FCBGA998

Tuesday, December 30, 2008

Sheet

of

40

10mil

10mil
2
C283
0.47U_0603_16V4Z

VTT41
VTT42
VTT43
VTT44
VTT45

C43
0.1U_0402_16V4Z

C319
1U_0402_6.3V4Z

40mA Max.

+1.5VS_DPLLB

10mil
10mil
1

L2

1
2
+1.5VS
FBM-L10-160808-301-T_0603
1
+

1
2
+1.5VS
FBM-L10-160808-301-T_0603

1
+
2

+1.5VS_MPLL 45mA
+1.5VS_HPLL 45mA
+1.5VS_DPLLA 50mA
+1.5VS_DPLLB 50mA
+1.5VS150mA
+2.5VS60mA

+2.5VS
1

Route +2.5VS from GMCH pinN33 to


decoupling cap <200mil to the edge.

C267
2

400mA

+2.5VS_CRTDAC

+VCCP

+1.5VS_PCIE
R177
2
1
0_0805_5%

CRTDAC: Route FB
within 3" of Calistoga

+1.5VS_3GPLL
+2.5VS

+2.5VS

40mA Max.

+1.5VS_DPLLA

L20

70mA
70mA
1

R172 1
2
10_0603_5%

+2.5VS

+2.5VS

+1.5VS

1
+
2

+2.5VS

C248
0.47U_0603_16V4Z

Route VSSACRTDAC gnd from GMCH to


decoupling cap ground lead and then
connect to the gnd plane.

+2.5VS

close pin C29/D29

2006/08/18

Issued Date

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2
A

close pin B31

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C287
0.1U_0402_16V4Z

C44
10U_0805_10V4Z

C24
10U_0805_10V4Z

C235
0.1U_0402_16V4Z

C23
10U_0805_10V4Z

C239
0.1U_0402_16V4Z

C286
1U_0603_10V6K

C278
10U_0805_10V4Z

C277
0.1U_0402_16V4Z
C52
10U_0805_10V4Z

C48
0.1U_0402_16V4Z

+1.5VS

Calistoga-GSE_FCBGA998

P1
L1
G1
U1
Y1

C246
0.1U_0402_16V4Z

U4_AA1
U4_F1

C237
0.01U_0402_25V7K

R38
0_0603_5%
2
1

+1.5VS

C247
0.1U_0402_16V4Z

10mil

45mA Max.

+1.5VS_HPLL

C260
4.7U_0805_6.3V6K

533 MTS=1720mA

C259
220U_B2_2.5VM_R35

C281
4.7U_0805_6.3V6K

R45
0_0603_5%
2
1

+1.8V

C253
10U_0805_10V4Z

C276
4.7U_0805_6.3V6K

C40
220U_B2_2.5VM_R35

0.47U_0603_16V4Z

45mA Max.

+1.5VS_MPLL
2

C254
10U_0805_10V4Z

U4_A7

210mil

C245
10U_0805_10V4Z

C22

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40

C13

0.47U_0603_16V4Z

A14
D10
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
AA1
F1

0_0603_5%
1

330U_D2_2.5VY_R9M
C236

U4_A14

10mil

+1.5VS

0.1U_0402_16V4Z

C249

330U_D2_2.5VY_R9M
C257

780mA

C25

10mil

10mil

0.1U_0402_16V4Z

+VCCP

U4_AB33
U4_AM32

C256
0.1U_0402_16V4Z

+3VS

C293
4.7U_0603_6.3V6M

40mA

C330
4.7U_0603_6.3V6M

+1.5VS

C288
1U_0603_10V6K

C250
0.1U_0402_16V4Z

1 1

+2.5VS

R168
@
10_0402_5%

20mA

C244
10U_0805_10V4Z

1250mA

+1.5VS
R210
+1.5VS_3GPLL

C242
0.1U_0402_16V4Z

D15 @
RB751V-40TE17_SOD323-2

+1.5VS_3GPLL

C241
0.022U_0402_16V7K

+1.5VS

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28

PCI-E/MEM/PSB PLL decoupling


Disable TV

0.1U_0402_16V4Z

AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
J14
J10
H10
AE9
AD9
U9
AD8
AD7
AD6

+VCCP

B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26400mA
N33 2mA
M33
J23
C24
B24
B25
B31 10mA
B32

C329
1U_0603_10V6K

VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCATVBG
VSSATVBG
VCCDTVDAC
VCCDQTVDAC
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAMPLL
VCCAHPLL
VCCADPLLA
VCCADPLLB
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCC3G0
VCC3G1
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCSYNC
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
VCCALVDS
VSSALVDS

C318
1U_0603_10V6K

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21

C54
1U_0603_10V6K

T26
R26
P26
N26
M26
V19
U19
T19
W18
V18
T18
R18
W17
U17
R17
W16
V16
T16
R16
V15
U15
T15

POWER

C266
0.1U_0402_16V4Z

C265
0.1U_0402_16V4Z

C261
0.1U_0402_16V4Z

144mA

U1D

C39
10U_0805_10V4Z

C41
10U_0805_10V4Z

C37
220U_B2_2.5VM_R35

2940mA

+1.5VS

+VCCP

Title

Calistoga(5/5)-PWR/GND
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
1

10

of

40

+1.8V

+1.8V
JDIM1

+DIMM_VREF

+1.8V

DDR_A_D0
DDR_A_D1

<7> DDR_A_D[0..63]
<7> DDR_A_DM[0..7]

Layout Note:
Place near JDIM1

<7> DDR_A_DQS[0..7]

DDR_A_DQS#0
DDR_A_DQS0

R41
1K_0402_1%

DDR_A_D2
DDR_A_D3

<7> DDR_A_MA[0..13]

+DIMM_VREF
D

Share +DIMM_VREF for


1.DDRII VREF
2.GMCH SM_VREF_0
SM_VREF_1

R43
1K_0402_1%

C71
2.2U_0603_6.3V6K

C70
2.2U_0603_6.3V6K

C89
2.2U_0603_6.3V6K

C90
2.2U_0603_6.3V6K

C91
2.2U_0603_6.3V6K

+1.8V

DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

+DIMM_VREF

20mils

C86

0.1U_0402_16V4Z
2

DDR_A_D16
DDR_A_D17
C92
DDR_A_DQS#2
DDR_A_DQS2

2.2U_0603_6.3V6K

C87
0.1U_0402_16V4Z

C88
0.1U_0402_16V4Z

C68
0.1U_0402_16V4Z

C69
0.1U_0402_16V4Z

DDR_A_D24
DDR_A_D25

For EMI DDR issue

DDR_A_DM3

2
+1.5VS

+1.8V
1

2
@ 0.1U_0402_16V4Z

2
@ 0.1U_0402_16V4Z

2
@ 0.1U_0402_16V4Z

C94

+3VS

C95
C159

DDR_A_D26
DDR_A_D27
<6> DDR_CKE0
<7> DDR_A_BS2

DDR_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
<7> DDR_A_BS0
<7> DDR_A_WE#

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

<7> DDR_A_CAS#
<6> DDR_CS1#

DDR_A_CAS#
DDR_CS1#

<6> M_ODT1

+0.9VS

M_ODT1
DDR_A_D32
DDR_A_D33

C100
0.1U_0402_16V4Z

C80
0.1U_0402_16V4Z

C78
0.1U_0402_16V4Z

C99
0.1U_0402_16V4Z

C101
0.1U_0402_16V4Z

C82
0.1U_0402_16V4Z

C83
0.1U_0402_16V4Z

C102
0.1U_0402_16V4Z

C103
0.1U_0402_16V4Z

C81
0.1U_0402_16V4Z

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6
+0.9VS

8
7
6
5

1
2
3
4

DDR_A_RAS#
DDR_A_MA4
DDR_A_MA2
DDR_A_BS1

56_0804_8P4R_5%
RP2
1
8
2
7
3
6
4
5

56_0804_8P4R_5%
RP6
DDR_CKE1
8
1
DDR_A_MA7
7
2
DDR_A_MA6
6
3
DDR_A_MA11
5
4

56_0804_8P4R_5%
RP3
1
8
2
7
3
6
4
5

56_0804_8P4R_5%
RP4
8
1 DDR_A_MA12
7
2 DDR_A_MA9
6
3 DDR_A_MA8
5
4 DDR_A_MA10

DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_CAS#

DDR_A_WE#
DDR_A_BS0
M_ODT1
DDR_CS1#

DDR_A_D50
DDR_A_D51

RP5
8
7
6
5

Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil

DDR_A_DM7
DDR_A_D58
DDR_A_D59
<12> CLK_SMBDATA
<12> CLK_SMBCLK

+3VS

C361

56_0804_8P4R_5%

CLK_SMBDATA
CLK_SMBCLK
+3VS

DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
D

DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>

DDR_A_D14
DDR_A_D15

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D20
DDR_A_D21
R54
DDR_A_DM2

2
0_0402_5%

PM_EXTTS#0 <6>

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1

DDR_CKE1 <6>
C

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0#

DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0# <6>

M_ODT0
DDR_A_MA13

M_ODT0 <6>

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>

DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R53
R52

2 10K_0402_5%
2 10K_0402_5%

1
1

P-TWO_A5652C-A0G16
CONN@

DIMMA

Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"

1 R159
2
56_0402_5%
1 R160
2
56_0402_5%

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

f@

DDR_CKE0

Title

DDRII-SODIMMA
Size
B
Date:

in

DDR_A_BS2

ho

tm

56_0804_8P4R_5%

DDR_A_D56
DDR_A_D57

DDR_A_DM0

ai

1
2
3
4

0.1U_0402_16V4Z

RP1
DDR_A_MA0
DDR_A_MA13
DDR_CS0#
M_ODT0

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_A_D4
DDR_A_D5

Document Number

Rev
1.0

xa

C104
0.1U_0402_16V4Z

C84
0.1U_0402_16V4Z

C79
0.1U_0402_16V4Z

DDR_A_DQS#4
DDR_A_DQS4

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

KAV10 LA-4781P

he

C61
220U_B2_2.5VM_R35

DDR_A_D18
DDR_A_D19

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

l.c
om

<7> DDR_A_DQS#[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Tuesday, December 30, 2008

Sheet

11

of

40

FSB

FSA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

266

PCI
MHz

100

REF
MHz

33.3

DOT_96 USB
MHz
MHz

14.318

96.0

L11
2
1
FBMA-L11-201209-221LMA30T_0805

+3VS

C834
47P_0402_50V8J

48.0

133

100

33.3

14.318

96.0

48.0

200

100

33.3

14.318

96.0

48.0

+3VM_CK505

+3VS

C151
10U_0805_10V4Z

C181
0.1U_0402_16V4Z

C175
0.1U_0402_16V4Z

C197
0.1U_0402_16V4Z

C199
0.1U_0402_16V4Z

C155
0.1U_0402_16V4Z

C154

R112

0.1U_0402_16V4Z

Close to L11
+1.05VM_CK505

166

100

33.3

14.318

96.0

48.0

C851
47P_0402_50V8J

333

100

33.3

14.318

96.0

48.0

100

100

33.3

14.318

96.0

48.0

400

100

33.3

14.318

96.0

48.0

C163
10U_0805_10V4Z

C198
0.1U_0402_16V4Z

C152
0.1U_0402_16V4Z

C153
0.1U_0402_16V4Z

SDA
VDD_SRC
SCL

+VCCP

CLK_SMBDATA

10

CLK_SMBCLK

71

CLK_CPU_BCLK

VDD_PCI

CPU_0

VDD_CPU

CPU_0#

70

CLK_CPU_BCLK#

68

CLK_MCH_BCLK

67

CLK_MCH_BCLK#

24

CLK_MCH_DREFCLK

25

CLK_MCH_DREFCLK#

28

MCH_SSCDREFCLK

29

MCH_SSCDREFCLK#

32

CLK_PCIE_SATA

33

CLK_PCIE_SATA#

35

CLK_MCH_3GPLL

36

CLK_MCH_3GPLL#

39

CLK_PCIE_CARD

40

CLK_PCIE_CARD#

57

CLK_PCIE_WLAN

56

CLK_PCIE_WLAN#

61

CLK_PCIE_WWAN

60

CLK_PCIE_WWAN#

19

R140

VDD_48

27

VDD_PLL3

66

+1.05VM_CK505

<6>

R142
1K_0402_5%

SRC_0/DOT_96

31

VDD_PLL3_IO

SRC_0#/DOT_96#

62

VDD_SRC_IO

R141

52

1K_0402_5%
@

23

+VCCP

<23> CLK_SD_48M

12_0402_5% 1

2 R143

LCDCLK/27M
VDD_SRC_IO
LCDCLK#/27M_SS

12_0402_5% 1

2 R137

FSA

20

FSB

R81

FSB

1K_0402_5%
@
1
2

33_0402_5% 1

<17> CLK_ICH_14M

VDD_SRC_IO

2 R101

FSC

SRC_3
FS_B/TEST_MODE
SRC_3#

CLK_SMBCLK

+3VS

0.1U_0402_16V4Z

REF_1

SRC_4

<6>

R86
1K_0402_5%

VGATE

<17,25,38> VGATE

SRC_4#

NC

SRC_6
SRC_6#

H_STP_CPU#

<17> H_STP_CPU#
<17> H_STP_PCI#

53

H_STP_PCI#

54

CLK_XTAL_IN

CPU_STOP#
SRC_7
PCI_STOP#
SRC_7#

+VCCP

CLK_XTAL_OUT

SRC PORT LIST

CLK_SMBCLK <11>
CLK_CPU_BCLK

<4>

CLK_CPU_BCLK#

PORT

DEVICE

<4>

CLK_MCH_BCLK

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

<6>

CLK_MCH_BCLK#

<6>

CLK_MCH_DREFCLK

<6>

CLK_MCH_DREFCLK#

<6>

MCH_SSCDREFCLK

<6>

MCH_SSCDREFCLK#

<6>

CLK_PCIE_SATA <16>
CLK_PCIE_SATA# <16>
CLK_MCH_3GPLL

MCH_DREFCLK
SATA HDD
MCH_3GPLL
PCIE_CARDREADER
PCIE_WLAN
PCIE_WWAN
PCIE_LAN
PCIE_ICH

<8>

CLK_MCH_3GPLL#

<8>

CLK_PCIE_CARD

<27>

CLK_PCIE_CARD#

<27>

XTAL_IN
SRC_8/CPU_ITP

XTAL_OUT

SRC_8#/CPU_ITP#

CLK_PCIE_WLAN

<19>

CLK_PCIE_WLAN#

<19>

CLK_PCIE_WWAN

<19>

CLK_PCIE_WWAN#

<19>

64

63

<4> CPU_BSEL2

@
1
2
R95
0_0402_5%

1K_0402_5%
@
1
2

13
PCI2_TME
MCH_CLKSEL2

<6>
33_0402_5% 1

<25> CLK_PCI_LPC

33_0402_5% 1

<15> CLK_PCI_ICH

R98
0_0402_5%

2 R115
2 R121

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

14
15

R99
1K_0402_5%

FSC

R97
R100
10K_0402_5%
2
1

For PCI4_SEL, 0 = Pin24/25


Pin28/29
1 = Pin24/25
Pin28/29

:
:
:
:

DOT96 / DOT96#
LCDCLK / LCDCLK#
SRC_0 / SRC_0#
27M/27M_SS

For PCI2_TME:0=Overclocking of CPU and SRC allowed


(ICS only)
1=Overclocking of CPU and SRC NOT allowed

PCI4_SEL
ITP_EN

+3VS

R129

R119

R109

10K_0402_5%
@

10K_0402_5%
@

10K_0402_5%

SRC_10

17

44

CLK_PCIE_LAN

45

CLK_PCIE_LAN#

50

CLK_PCIE_ICH

51

CLK_PCIE_ICH#

CLK_PCIE_LAN

CLK_PCIE_ICH

+3VS

<24>

CLK_PCIE_LAN#

<24>
<17>

CLK_PCIE_ICH#

MCH_CLKREQ#
SATA_CLKREQ#
WLAN_CLKREQ#
WWAN_CLKREQ#

R139
R111
R84
R85

2
2
2
2

1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

<17>

PCIF_5/ITP_EN
SRC_11

18

VSS_PCI

SRC_11#

REQ PORT LIST

48
47

PORT

VSS_REF

22

CLKREQ_3#

37

VSS_IO

CLKREQ_4#

41

VSS_CPU

CLKREQ_6#

VSS_PLL3

CLKREQ_7#

VSS_SRC

CLKREQ_9#

VSS_48

26
69
30

73

VSS_SRC

SLKREQ_10#

VSS_SRC

CLKREQ_11#

VSS

USB_1/CLKREQ_A#

MCH_CLKREQ#

58

WLAN_CLKREQ#

65

WWAN_CLKREQ#

MCH_CLKREQ#

<6>

WLAN_CLKREQ#
WWAN_CLKREQ#

<19>
<19>

43
49
46
21

SATA_CLKREQ#

DEVICE

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

SATA_CLKREQ# <17>

MCH_3GPLL
PCIE_WLAN
PCIE_WWAN

SATA

SLG8SP556VTR_QFN72_10X10

PCI2_TME

R132

R117

@
R110

10K_0402_5%

10K_0402_5%

10K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Routing the trace at least 10mil

CLK_XTAL_OUT

27P_0402_50V8J

PCI4_SEL

ITP_EN

2
C162

Y2
14.31818MHZ_16PF_DSX840GA

27P_0402_50V8J

C169

SRC_9#

SRC_10#

42

CLK_XTAL_IN

SRC_9

PCI_2

PCI_4/SEL_LCDCL

59

+3VS

PCI_1

PCI_3

16

34
+3VS

CKPWRGD/PD#

11

0_0402_5%

CLK_SMBDATA <11>

REF_0/FS_C/TEST_

R82

SRC_2

USB_0/FS_A

8
MCH_CLKSEL1

C200

VDD_IO

SRC_2#

<17> CLK_ICH_48M

@
1
2
R91
0_0402_5%

CPU_1#

VDD_CPU_IO

38

<4> CPU_BSEL1

CPU_1

56_0402_5%

@
1
2
R147
0_0402_5%

VDD_REF

72

<4> CPU_BSEL0

0.1U_0402_16V4Z

U11

55

H_STP_PCI#
2
@ 10K_0402_5%

12

MCH_CLKSEL0

C189

CLK_SMBDATA

SA000020K00 (Silego : SLG8SP556VTR )


SA000020H10 (ICS : ICS9LPRS387AKLFT)

1
R645

Q10B
2N7002DW-T/R7_SOT363-6

+3VM_CK505

0.1U_0402_16V4Z

<17> ICH_SMBCLK

+3VS

C167

Close to L12

Reserved

R138
2.2K_0402_5%
FSA 2
1

<17> ICH_SMBDATA

2.2K_0402_5%

L12 2
1
FBMA-L11-201209-221LMA30T_0805

+VCCP

R108

2.2K_0402_5%
2N7002DW-T/R7_SOT363-6
Q10A

FSC

2007/10/15

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Clock Generator CK505


Size

Document Number

Rev
1.0

KAV10 LA-4781P
Date:

Tuesday, December 30, 2008

Sheet
1

12

of

40

LCD POWER CIRCUIT


+LCDVDD
+3VS

+3VALW
1

W=20mils
1

1
47K_0402_5%

1
2

D20
Q5
AO3413_SOT23-3

R39

@
4.7U_0805_10V4Z

SM05T1G_SOT23-3
1

2N7002DW-T/R7_SOT363-6

C59

Q4B

3 2

R35
47K_0402_5%

R40
150_0603_5%

C45

+LCDVDD
1

0.1U_0402_16V4Z

W=20mils

Q4A
2

<8> GMCH_ENVDD

R60
100K_0402_5%
1
2

2N7002DW-T/R7_SOT363-6

C58

4.7U_0805_10V4Z
2

C63
0.1U_0402_16V4Z

LCD/PANEL BD. Conn.

330P_0402_50V7K

1 C368

100P_0402_50V8J

1 C362

+3VS

For panel ADJ

<25> INVT_PWM
<25> BKOFF#

<8> LVDS_A1
<8> LVDS_A1#
B

<8> LVDS_A0
<8> LVDS_A0#
<8> LVDS_A2
<8> LVDS_A2#
<8> LVDS_ACLK
<8> LVDS_ACLK#

(20 MIL)

+LCDVDD_L
INVT_PWM
BKOFF#
LVDS_SDA
LVDS_SCL

LVDS_A1
LVDS_A1#
LVDS_A0
LVDS_A0#
LVDS_A2
LVDS_A2#
LVDS_ACLK
LVDS_ACLK#

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND

22

1
1

+3VS

FBMA-L11-201209-221LMA30T_0805 L7 2
FBMA-L11-201209-221LMA30T_0805 L6 2

R44
10K_0402_5%
1
2

+LEDVDD

400mA B+
280mA +LCDVDD

R42
10K_0402_5%

JLVDS1

LVDS_SCL

LVDS_SCL <8>

LVDS_SDA

LVDS_SDA <8>
B

GND

21

l.c
om

ACES_87213-2000G
CONN@

LVDS /INVERTER

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2007/8/18

Deciphered Date

Document Number

Rev
1.0

KAV10 LA-4781P

he

2006/08/18

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

Tuesday, December 30, 2008

Sheet

13

of

40

Close to CRT CONN for ESD.

PSOT24C_SOT23-3

Place closed to chipset

L1
BK1608LL121-T 0603
1
2
L3
BK1608LL121-T 0603
1
2
L4
BK1608LL121-T 0603
1
2

<8> GMCH_CRT_R
<8> GMCH_CRT_G

R13

R19

150_0402_1%
2
1

150_0402_1%
2
1

R5

150_0402_1%
2
1

<8> GMCH_CRT_B

C12

C30

5
P
2

1
L19

2
BK1608LL121-T 0603

1
L5

2
BK1608LL121-T 0603

C20
10P_0402_50V8J
2

C29
10P_0402_50V8J

JVGA_HS
JVGA_VS
2

U15
CRT_HSYNC_1

1
C232
10P_0402_50V8J

<8> GMCH_CRT_HSYNC

39_0402_5%
1 R282
2

OE#

BLUE

C7
10P_0402_50V8J
2

2
2
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J

2
0.1U_0402_16V4Z

C38

C35

RED
GREEN

+CRT_VCC
1

PSOT24C_SOT23-3

D3

Add D3 D4<SCA00000A00> for ESD


20081114

D4

SN74AHCT1G125DCKR_SC70-5

C31
10P_0402_50V8J

2
0.1U_0402_16V4Z

1
C234

1 R296
2
39_0402_5%

CRT_VSYNC_1

<8> GMCH_CRT_VSYNC

U4

OE#

Place closed to chipset

+CRT_VCC

SN74AHCT1G125DCKR_SC70-5

CRT PORT
+CRT_VCC

+5VS
+3VS

D6
2

JCRT1

RED

+3VS
2

R16

R164

JVGA_HS
BLUE

2.2K_0402_5%
2

2.2K_0402_5%

JVGA_VS
VGA_DDC_DAT
VGA_DDC_CLK
1

Q14B
2N7002DW-T/R7_SOT363-6
VGA_DDC_CLK
6

<8> GMCH_CRT_DATA

VGA_DDC_DAT
GREEN

R163

2.2K_0402_5%
2

C36
0.1U_0402_16V4Z
1
2

RB491D_SC59-3

2.2K_0402_5%

R165

<8> GMCH_CRT_CLK

+CRT_VCC
3

W=40mils

C400
100P_0402_50V8J

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

G
G

16
17

SUYIN_070546FR015S233ZR
CONN@
CRT_DET# <17>
2

Q14A
2N7002DW-T/R7_SOT363-6

R293
100K_0402_5%

+CRT_VCC

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CRT PORT
Size
B
Date:

Document Number

Rev
1.0

KAV10 LA-4781P
Tuesday, December 30, 2008

Sheet
E

14

of

40

+3VS

U6B

PCI_DEVSEL#

R263 1

2 8.2K_0402_5%

PCI_STOP#

R262 1

2 8.2K_0402_5%

PCI_TRDY#

R264 1

2 8.2K_0402_5%

PCI_FRAME#

R259 1

2 8.2K_0402_5%

PCI_PLOCK#

R256 1

2 8.2K_0402_5%

PCI_IRDY#

R258 1

2 8.2K_0402_5%

PCI_SERR#

R257 1

2 8.2K_0402_5%

PCI_PERR#

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

+3VS

R254 1

2 8.2K_0402_5%

PCI_PIRQA#

R255 1

2 8.2K_0402_5%

PCI_PIRQB#

R271 1

2 8.2K_0402_5%

PCI_PIRQC#

R270 1

2 8.2K_0402_5%

PCI_PIRQD#

R276 1

2 8.2K_0402_5%

PCI_PIRQE#

R272 1

2 8.2K_0402_5%

PCI_PIRQF#

R275 1

2 8.2K_0402_5%

PCI_PIRQG#

R273 1

2 8.2K_0402_5%

PCI_PIRQH#

R274 1

2 8.2K_0402_5%

PCI_REQ#0

R265 1

2 8.2K_0402_5%

PCI_REQ#1

R266 1

2 8.2K_0402_5%

PCI_REQ#2

R261 1

2 8.2K_0402_5%

PCI_REQ#3

R277 1

2 8.2K_0402_5%

PCI_REQ#4

R278 1

2 8.2K_0402_5%

PCI_REQ#5

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI_REQ#0

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

C/BE0#
C/BE1#
C/BE2#
C/BE3#

B15
C12
D12
C15

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

PLTRST#
PCICLK
PME#

C26
A9
B19

PLTRST#_R
CLK_PCI_ICH

G8
F7
F8
G7

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI

PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_REQ#5

PCI_IRDY#

PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

1 R244

100K_0402_5%

For EC request.

CLK_PCI_ICH

Place closely pin A9

<12>

CLK_PCI_ICH
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

Interrupt

A3
B4
C5
B5

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AE5
AD5
AG4
AH4
AD9

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

2 8.2K_0402_5%

@
R246
10_0402_5%

R260 1

MISC
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

AE9
AG8
AH8
F21
AH20

@
C359
8.2P_0402_50V8D
MCH_ICH_SYNC#

<6>

2
B

ICH7_BGA652

+3VS
@
C297

U16 @

PLTRST# <6,17,19,24,25,27>

PLTRST#_R

0.1U_0402_16V4Z

TC7SH08FUF_SSOP5
R227

l.c
om

2
0_0402_5%

100K_0402_5%

1
R226

ho

tm

ai

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

ICH7M(1/4)HUB,PCI,HOST
Size

Document Number

in

2007/8/18

Rev
1.0

xa

Deciphered Date

KAV10 LA-4781P

Date:

he

2006/08/18

Issued Date

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Tuesday, December 30, 2008

Sheet
1

15

of

40

C49
18P_0402_50V8J
2
1

OUT

R217 1
20K_0402_5%

+RTCVCC

U6A
AB1
AB2

ICH_RTCX2
ICH_RTCRST#

ICH_INTVRMEN
SM_INTRUDER#

+RTCVCC

AA3
W4
Y5

2 @ R72 1
10K_0603_5%
2

0.1U_0402_16V4Z

<20> HDA_SYNC_AUDIO

W1
Y1
Y2
W3

C317
1U_0603_10V4Z
1
2

<20> HDA_BITCLK_AUDIO
<20> HDA_RST_AUDIO#

HDA_SYNC_ICH
2
39_0402_5%
HDA_BITCLK_ICH
2
39_0402_5%
HDA_RST_ICH#
2
39_0402_5%
HDA_SDOUT_ICH
2
39_0402_5%

+3VS

LFRAME#
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

V3

LAN_CLK
LAN_RSTSYNC

U5
V4
T5

LAN_RXD0
LAN_RXD1
LAN_RXD2

ACZ_BCLK
ACZ_SYNC

HDA_RST_ICH#

R5

ACZ_RST#

T2
T3
T1

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

T4

SATA_LED#

2
SATA_LED#

<12> CLK_PCIE_SATA#
<12> CLK_PCIE_SATA
R613

AF3
AE3
AG2
AH2

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2

AF7
AE7
AG6
AH6

AG26

H_FERR#

CLK_PCIE_SATA#
CLK_PCIE_SATA

AF1
AE1

2 24.9_0402_1%

AH10
SATARBIAS AG10

10mils
IDE_DIORDY
IDE_IRQ
SATA_ITX_DRX_N0

1
C824

SATA_ITX_C_DRX_N0
2
3900P_0402_50V7K

SATA_ITX_C_DRX_N0 <22>

SATA_ITX_DRX_P0

1
C823

SATA_ITX_C_DRX_P0
2
3900P_0402_50V7K

SATA_ITX_C_DRX_P0 <22>

AG16
AH16
AF16
AH15
AF15

AG24

H_PWRGOOD

IGNNE#
INIT3_3V#
INIT#
INTR

AG22
AG21
AF22
AF25

H_IGNNE#

RCIN#

AG23

KB_RST#

SMI#
NMI

AF23
AH24

H_SMI#
H_NMI

AH22

H_STPCLK#

AF26

THRMTRIP_ICH#

STPCLK#

DCS1#
DCS3#

SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP

IDE
IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

LPC_FRAME# <25>
2

1 R204 10K_0402_5%

+3VS

GATEA20 <25>
H_A20M# <4>

1 56_0402_5%
R20

H_DPRSTP# <4,38>
H_DPSLP# <4>
+VCCP

H_FERR# <4>

H_PWRGOOD <4>
C

H_IGNNE# <4>

H_INIT#
H_INTR

H_INIT# <4>
H_INTR <4>
+VCCP

DA0
DA1
DA2

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

GATEA20
H_A20M#

FERR#

SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AE22
AH28

LPC_FRAME#

H_DPRSTP#
H_DPSLP#

SATA

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

<22> SATA_DTX_C_IRX_N0
<22> SATA_DTX_C_IRX_P0

AF18

AB3

AF24
AH25

10K_0402_5%
<26> SATA_LED#

AC3
AA5

AG27

THERMTRIP#

ACZ_SDOUT

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

CPUSLP#

GPIO49 / CPUPWRGD

U1
R6

HDA_SDOUT_ICH

A20GATE
A20M#

AA6
AB5
AC4
Y6

TP1 / DPRSTP#
TP2 / DPSLP#

LAN_TXD0
LAN_TXD1
LAN_TXD2

HDA_BITCLK_ICH
HDA_SYNC_ICH

<20> HDA_SDIN0

LAD0
LAD1
LAD2
LAD3

LDRQ0#
LDRQ1# / GPIO23

U3

U7
V6
V7

R610

INTVRMEN
INTRUDER#

AC-97/AZALIA

<20> HDA_SDOUT_AUDIO

1
R235
1
R230
1
R236
1
R233

RTCRST#

LAN

C294

LPC_AD[0..3] <25>

RTXC1
RTCX2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DDREQ

KB_RST# <25>
H_SMI# <4>
H_NMI <4>

R194
56_0402_5%

H_STPCLK# <4>
1 R196
2
24.9_0402_1%

H_THERMTRIP# <4,6>

Layout note: R196 needs to placed


within 2" of ICH7, R194 must be placed
within 2" of R196 w/o stub.

AH17
AE17
AF17
AE16
AD16
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

+RTCBATT
2

NC

R432
1K_0402_5%

AE15

ICH7_BGA652

D31

close ICH7

1 1

C50
18P_0402_50V8J
2
1

+RTCVCC
+3VS

332K_0402_1%
2 ICH_INTVRMEN

R216
1

1M_0402_5%
2 SM_INTRUDER#

RTC

R214
1

ICH_RTCX1

Y1
32.768K_1TJS125BJ4A421P
2
1
NC
IN

LPC

+RTCVCC

R37
10M_0402_5%
2
1

CPU

BAS40-04_SOT23-3

1
R285
1
R283

SATA_DTX_C_IRX_N2
2
1K_0402_5%
SATA_DTX_C_IRX_P2
2
1K_0402_5%

2
4.7K_0402_5%

1 R23

2
8.2K_0402_5%

1 R36

IDE_DIORDY

IDE_IRQ

+CHGRTC
C528
0.1U_0402_16V4Z

SATA_RXn/p need tie to ground when SATA port no used

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

ICH7M(2/4)LAN,ATA,LPC,RTC
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
1

16

of

40

Place closely pin B2

+3VS

Place closely pin AC1

CLK_ICH_48M

ICH_RI#

A28

SB_SPKR
SUS_STAT#
ITP_DBRESET#

A19
A27
A22

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

+3VALW
R59
1
2
8.2K_0402_5%

10K_0402_5%
R269 1
2 LINKALERT#

<20> SB_SPKR
PAD T4

10K_0402_5%
R268 1
2 OCP#

<6> PM_BMBUSY#

OCP#
H_STP_PCI#
H_STP_CPU#

@ 10K_0402_5%
R223 1
2 SB_SPI_CS#

R148
10K_0402_5%

High: CRT Plugged


1
1
2
Q11G
2N7002_SOT23

PM_CLKRUN#
D

CRT_DET

8.2K_0402_5%
R250 2
1 ICH_LOW_BAT#
@ 10K_0402_5%
R222 1
2 SPI_MOSI

<12> H_STP_PCI#
<12> H_STP_CPU#

+3VS

AB18
B23
AC20
AF21

<19> ICH_PCIE_WAKE#
<25> SERIRQ
<25> EC_THERM#
<12,25,38> VGATE

<25> EC_SMI#

GPIO0 / BM_BUSY#

GPIO18 / STPPCI#
GPIO20 / STPCPU#
GPIO26

B21
E23

GPIO27
GPIO28

AG18

ICH_PCIE_WAKE# F20
SERIRQ
AH21
EC_THERM#
AF20

GPIO32 / CLKRUN#

AF19
AH18
AH19
AE19

CLK_ICH_14M
CLK_ICH_48M

SUSCLK

C20

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

B24
D23
F22

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

AA4

ICH_POK

AC22

PM_DPRSLPVR

TP0 / BATLOW#

C21

ICH_LOW_BAT#

PWRBTN#

C23

PBTN_OUT#

LAN_RST#

C19

PLTRST#

Y4

EC_RSMRST#
R26 10K_0402_5%
1
2

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

EC_SCI#
ACIN

PWROK
GPIO16 / DPRSLPVR

RSMRST#

WAKE#
SERIRQ
THRM#

AD22

VRMPWRGD

CRT_DET

AC21
AC18
E21

GPIO6
GPIO7
GPIO8

GPIO

AC1
B2

CLK14
CLK48

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#

VGATE

EC_SMI#

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO11 / SMBALERT#

A21

AC19
U2

<14> CRT_DET#

SPKR
SUS_STAT#
SYS_RST#

GPIO

@ 10K_0402_5%
R224 1
2 SPI_MISO

1K_0402_5%
R241 1
2 ICH_PCIE_WAKE#

PM_BMBUSY#

RI#

SYS

10K_0402_5%
R267 1
2 ITP_DBRESET#

1
C22
B22
A26
B25
A25

SATA
GPIO

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

SMB

<12> ICH_SMBCLK
<12> ICH_SMBDATA

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

1
R245

R212

@ 10_0402_5%

@ 10_0402_5%
2

U6C

Clocks

2.2K_0402_5%
2

10K_0402_5%
1

10K_0402_5%

+3VALW

R207
8.2K_0402_5%

R252
2.2K_0402_5%

2
R56

R55

POWER MGT

R251

+3VS
1

R22

8.2K_0402_5%
1
2 PM_CLKRUN#

10K_0402_5%
1
2 SERIRQ
2

R21

CLK_ICH_14M

+3VALW
1

+3VALW

C355
@ 4.7P_0402_50V8C

C275
@ 4.7P_0402_50V8C

CLK_ICH_14M <12>
CLK_ICH_48M <12>
T16 PAD
PM_SLP_S3# <25>
PM_SLP_S4# <25>
PM_SLP_S5# <25>
R24
ICH_POK <6,25>
1
2 10K_0402_5%
PM_DPRSLPVR <6,38>

PBTN_OUT# <25>
PLTRST# <6,15,19,24,25,27>
EC_RSMRST# <25>

EC_SCI# <25>
ACIN <25,31>

EC_LID_OUT#

EC_LID_OUT# <25>

SATA_CLKREQ#

SATA_CLKREQ# <12>

ICH7_BGA652

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2

H26
H25
G28
G27

PERn2
PERp2
PETn2
PETp2

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3

K26
K25
J28
J27

PERn3
PERp3
PETn3
PETp3

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4

M26
M25
L28
L27

C73
C75

2
2

SDIO

<27>
<27>
<27>
<27>

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2

C66
C67

<24>
<24>
<24>
<24>

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3

C60
C64

<19>
<19>
<19>
<19>

PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_C_PRX_N4
PCIE_ITX_C_PRX_P4

LAN
B

WWAN

C106 2
C130 2

P26
P25
N28
N27
T25
T24
R28
R27

USB_OC#3
USB_OC#0
USB_OC#2

<28> USB_OC#0
R247 2
1
10K_0402_5%
R249 2
1
10K_0402_5%
R248 2
1
10K_0402_5%

SPI_MOSI
SPI_MISO

P5
P2

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

D3
C4
D5
D4
E5
C3
A2
B3

PERn4
PERp4
PETn4
PETp4
PERn5
PERp5
PETn5
PETp5
PERn6
PERp6
PETn6
PETp6
SPI_CLK
SPI_CS#
SPI_ARB

SPI

+3VALW
USB_OC#6
USB_OC#1
USB_OC#7
USB_OC#4
USB_OC#5

SB_SPI_CS#

R2
P6
P1

PERn1
PERp1
PETn1
PETp1

PCI-EXPRESS

WLAN

SPI_MOSI
SPI_MISO
OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

USB

V26
V25
U28
U27

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y26
Y25
W28
W27

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA28
AA27

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBRBIAS#
USBRBIAS

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

<6>
<6>
<6>
<6>

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

<6>
<6>
<6>
<6>

AD25
AD24
AC28
AC27
AE28
AE27

CLK_PCIE_ICH#
CLK_PCIE_ICH

C25
D25

DMI_IRCOMP

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

D2
D1

USBRBIAS

CLK_PCIE_ICH# <12>
CLK_PCIE_ICH <12>
R243 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

Within 500 mils


+1.5VS
<28>
<28>
<22>
<22>
<28>
<28>
<28>
<28>
<19>
<19>
<19>
<19>
<19>
<19>
<23>
<23>

USB1(Left)
CMOS
USB2(Left)
USB3(Right)
WiMAX
WWAN
BT
Card reader

R242 22.6_0402_1%
1
2

l.c
om

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

F26
F25
E28
E27

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

DIRECT MEDIA INTERFACE

U6D
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P1

<19>
<19>
<19>
<19>

Within 500 mils

ICH7M(3/4)USB,GPIO,PCIE

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size Document Number
Custom
Date:

xa

2007/8/18

Deciphered Date

Rev
1.0

KAV10 LA-4781P

he

2006/08/18

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

ICH7_BGA652

Tuesday, December 30, 2008

Sheet
1

17

of

40

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

1
+5VS

+3VS

C93
220U_B2_2.5VM_R35

R237

C279

C305

C349

D21
0.1U_0402_16V4Z

0.1U_0402_16V4Z

RB751V-40TE17_SOD323-2

100_0402_5%

Place closely pin


D28,T28,AD28.

ICH_V5REF_RUN
C343

1U_0603_10V4Z

+5VALW +3VALW

R64

RB751V-40TE17_SOD323-2
2

10_0402_5%

D11
@

ICH_V5REF_SUS
C346
0.1U_0402_16V4Z

+3VS

C356
0.1U_0402_16V4Z

Place closely pin AG28 within 100mlis.


+1.5VS_DMIPLLR

+1.5VS_DMIPLL

B27

0.5_0805_1%

2
0_0805_5%

C271
0.01U_0402_25V7K

R186
2

Connected +1.5VS directly


when disable SATA.

C282
0.1U_0402_16V4Z

C269
1U_0603_10V4Z

+1.5VS
C350
0.1U_0402_16V4Z

1
T2
T6

PAD
PAD

ICH_AA2
ICH_Y7

VccSATAPLL

+3VS
A

R7

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
VccRTC
VccSus3_3[1]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc3_3[2]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

V5
V1
W2
W7

U6

VccDMIPLL

AD2

AA2
Y7

Vcc3_3 / VccHDA
VccSus3_3/VccSusHDA

Vcc3_3[1]

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

+1.5VS

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

Place closely pin AG9.


10mA

0.64A

AH11

0.1U_0402_16V4Z

+1.5VS

AG28

Place closely pin AG5.


1

C340

+1.5VS
+3VS

+3VALW

+1.5VS_DMIPLL

C263
0.1U_0402_16V4Z

R189
1

C272
10U_0805_10V4Z

+1.5VS

50mA

V5REF_Sus

Vcc1_5_A[24]
Vcc1_5_A[25]
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

C336

C316

+ C252

220U_B2_2.5VM_R35

1U_0603_10V4Z

+3VS

56mA
+3VALW

10mA

AE23
AE26
AH26

1
+VCCP
2

14mA

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

+3VS

0.27A
1

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

C285
0.1U_0402_16V4Z

+3VS

+RTCVCC

P7
1

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

C332

45mA

0.1U_0402_16V4Z
2

C333

0.1U_0402_16V4Z
2

AB17
AC17

+3VALW
C347
0.1U_0402_16V4Z

+3VALW
C339
0.1U_0402_16V4Z

+1.5VS

T7
F17
G17
AB8
AC8

K7

C284 0.1U_0402_16V4Z
ICH_K7
PAD

T1117mA

C28
G20

ICH_C28
ICH_G20

T3
T14

A1
H6
H7
J6
J7

PAD
PAD
+1.5VS
1

C344
0.1U_0402_16V4Z

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

ICH7_BGA652
A

C291
0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Secret Data


2006/08/18

Issued Date

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

ICH7_BGA652

Security Classification

0.1U_0402_16V4Z

W5

A24
C24
D19
D22
G19

C296

C292
0.1U_0402_16V4Z

0.1U_0402_16V4Z

V5REF[2]

C262
4.7U_0805_10V4Z

F6

U6E

0.94A

0.1U_0402_16V4Z

C274
0.1U_0402_16V4Z

10mA ICH_V5REF_SUS

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C289
0.1U_0402_16V4Z

+1.5VS

0.77A

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C273
0.1U_0402_16V4Z

AD17

V5REF[1]

C345
0.1U_0402_16V4Z

G10

C353
0.1U_0402_16V4Z

ICH_V5REF_RUN

+VCCP

U6F

6mA

C354
0.1U_0402_16V4Z

Title

ICH7M(4/4)POWER/GND
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P
Sheet

Tuesday, December 30, 2008


1

18

of

40

Mini-Express Card for WLAN


+3VS_WLAN

+1.5VS

C195

4.7U_0805_10V4Z
2

C98
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
C118

C121

4.7U_0805_10V4Z
2

C113
0.01U_0402_25V7K
1

JMINI1

<12> CLK_PCIE_WLAN#
<12> CLK_PCIE_WLAN

<17> PCIE_PTX_C_IRX_N1
<17> PCIE_PTX_C_IRX_P1
<17> PCIE_ITX_C_PRX_N1
<17> PCIE_ITX_C_PRX_P1
+3VS_WLAN

0.1U_0402_16V4Z
EC_TX_P80_DATA
1
EC_RX_P80_CLK
R87

C222

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS_WLAN

1
R62

2
0_1206_5%

+3VS
+1.5VS

WL_OFF#
PLTRST#
1
2
0_0402_5%
R83
1
2
0_0402_5%
R348 @

WL_OFF# <25>
PLTRST# <6,15,17,24,25,27>
+3VS
+3VALW

USB20_N4 <17>
USB20_P4 <17>

+5VS

MINI1_LED# <28>

R253
10K_0402_5%
BT@

(9~16mA)

53
54
55
56

G1
G2
G3
G3

2 CL_RST#2_R
0_0402_5%

2
4
6
8
10
12
14
16

FOX_AS0B226-S99N-7F
CONN@

Q21
BT@
+3VS

2
@ 0_1206_5%

C233
150U_Y_6.3VM

WWAN_CLKREQ#
<12> CLK_PCIE_WWAN#
<12> CLK_PCIE_WWAN

<17> PCIE_PTX_C_IRX_N4
<17> PCIE_PTX_C_IRX_P4
<17> PCIE_ITX_C_PRX_N4
<17> PCIE_ITX_C_PRX_P4
10U_0805_10V4Z
1
2
@
C226

+3VS_WWAN
D7
@ CM1293-04SO_SOT23-6
1
4
CH1
CH4

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+UIM_PWR_1

UIM_CLK

USB20_N5 <17>
USB20_P5 <17>
WWAN_LED# <25>

(9~16mA)

@ D16

C258
0.1U_0402_16V4Z

8
9

+3VS
+3VALW
+3VS_WWAN

0.1U_0402_16V4Z
1
C185

C149

C186

C105
2

0.1U_0402_16V4Z

2
10U_0805_10V4Z

2006/08/05

Issued Date

0.01U_0402_25V7K

Compal Electronics, Inc.

Compal Secret Data

Security Classification

CONN@

Reserve for SIM card does not meet rise time


and pull-up is needed.

2
0_0402_5%
2
@ 0_0402_5%

DAN217T146_SC59-3
1

+UIM_PWR
TAITW_PMPAT6-06GLBS7N14N0

1
R94
1
R408

3
C264
1U_0603_10V4Z

+UIM_PWR_1

22P_0402_50V8J

GND
GND

+UIM_PWR
UIM_RST
UIM_CLK

C17

1
2
3

22P_0402_50V8J
C18

VCC
RST
CLK

R25
10K_0402_5%
2
1

C14

1
4

22P_0402_50V8J

UIM_VPP
UIM_DATA

GND
VPP
I/O
DET

+3VALW

FOX_AS0B226-S99N-7F
CONN@

JP5
4
5
6
7

l.c
om

CH3

10

ACES_87213-0800G
CONN@

ai

CH2

tm

2
0_0402_5%
2
@ 0_0402_5%

WXMIT_OFF# <25>
PLTRST# <6,15,17,24,25,27>
+3VS_WWAN

1 GND
2
3
4
5
6
7
8 GND

ho

UIM_RST

WXMIT_OFF#
PLTRST#
1
R93
1
R407

<17> USB20_P6
<17> USB20_N6

1
2
3
4
5
6
7
8

USB20_P6
USB20_N6

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

f@

Vp

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

JBT1

+1.5VS

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

Title

Mini-Card/BT CONN

in

Vn

2
4
6
8
10
12
14
16

53
54
55
56

UIM_DATA

2
4
6
8
10
12
14
16

G1
G2
G3
G3

UIM_VPP

1
3
5
7
9
11
13
15

Size

xa

<12> WWAN_CLKREQ#

+3VS_BT

Close to WWAN CONN

1
3
5
7
9
11
13
15

BT@
C348
1

0.1U_0402_16V4Z

JMINI2
ICH_PCIE_WAKE#

1
R70

2
0_1206_5%

1
+

1
R65

+3VALW

+3VS_BT
Q20
BT@AO3413_SOT23-3
S

+3VS_WWAN

+3VS

DTC124EK_SC59
3

+3VS_WWAN

<17> ICH_PCIE_WAKE#

<25> BT_OFF#

Mini-Express Card for WWAN

BT MODULE CONN

Document Number

Rev
1.0

KAV10 LA-4781P
Date:

he

<25,27> EC_TX_P80_DATA
<25,27> EC_RX_P80_CLK

1
3
5
7
9
11
13
15

WLAN_CLKREQ#

<12> WLAN_CLKREQ#

1
3
5
7
9
11
13
15

1 1

ICH_PCIE_WAKE#

<17> ICH_PCIE_WAKE#

Tuesday, December 30, 2008

Sheet

19

of

40

+VDDA

R365
10K_0402_5%

J8

C455

2
1U_0402_6.3V4Z

+5VAMP

R366
10K_0402_5%

L21 1
2
FBMA-L11-201209-221LMA30T_0805

+5VS

2
1

1
1U_0402_6.3V4Z

<25> BEEP#

C460 1
1U_0402_6.3V4Z

R368

2
B
E

C457

2
C458
3

MONO_IN

0.1U_0402_16V4Z

U26

(output = 300 mA)

IN
OUT

BYP

40mil

GND
SHDN

@ G9191-475T1U_SOT23-5

4.75V

+VDDA

1
2
C459
0.01U_0402_25V7K

1
2
Q29
R367
2.4K_0402_1%
2SC2411KT146_SOT23-3

560_0402_5%

L22 1
2
FBMA-L11-201209-221LMA30T_0805

C456

60mil 1

0.1U_0402_16V4Z

@ JUMP_43X39
1

+3VS
JP4

560_0402_5%

R441
DMIC_DATA
R438

D25
RB751V-40TE17_SOD323-2
2

R370
10K_0402_5%

+AVDD_HDA

35

AMP_LEFT

LINE_OUT_R

36

AMP_RIGHT

16

MIC2_L

HP_OUT_L

39

17

MIC2_R

HP_OUT_R

41

LINE1_L

NC

LINE1_R

DMIC_CLK

1
R377

<25> EAPD

Sense Pin

SENSE A

SENSE B

Impedance

2
0_0402_5%

47

PORT-A (PIN 39, 41)

20K

PORT-B (PIN 21, 22)

10K

PORT-C (PIN 23, 24)

5.1K

PORT-D (PIN 35, 36)

39.2K

PORT-E (PIN 14, 15)

20K

PORT-F (PIN 16, 17)

10K

PORT-G (PIN 43, 44)

5.1K

PORT-H (PIN 45, 46)

CD_R

NC

CD_GND
BIT_CLK

DMIC_CLK

46
43
44

1
R371

2 C470
22P_0402_50V8J

2
1
22_0402_5%

For EMI

HDA_BITCLK_AUDIO <16>

MIC1_L
MIC1_R

SDATA_IN

PCBEEP

MONO_OUT
LINE1_VREFO

RESET#
GPIO1
SYNC
MIC1_VREFO_L
SDATA_OUT
MIC1_VREFO_R
GPIO0
GPIO3
SENSE A
SENSE B

MIC2_VREFO
VREF

EAPD

48

SPDIFO

4
7

DVSS1
DVSS2

HDA_SDIN0_AUDIO

2
33_0402_5%

HDA_SDIN0 <16>

For ALC272

29
2.2U_0402_6.3VM
C491 1

31

32

10mil

28

HP_RIGHT

1
MIC1_VREFO_L

HP_RIGHT

27
40

NC

33

AVSS1
AVSS2

26
42

CODEC_VREF

HP_LEFT

C490
2.2U_0402_6.3VM

AGND
ALC272X-GR

1
R380

2
0_0805_5%

1
R383

2
0_0805_5%

1
R379

2
0_0805_5%

1
R382

2
0_0805_5%

1
R381

2
0_0805_5%

1
R384

2
0_0805_5%

GND

GNDA

GND

GNDA

Issued Date

Compal Electronics, Inc.

Compal Secret Data


2006/12/25

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

HP_LEFT <21>

10mil

HP_LEFT

Security Classification

HP_RIGHT <21>

30

JDREF

DGND
Change to SA00002CI20
20081204

1
R372

37

ALC272-GR_LQFP48_9X9

Codec Signals

39.2K

NC

0.1U_0402_16V4Z

SENSE_A
SENSE_B

1 20K_0402_1%
1 5.11K_0402_1%

2
3
13
34

CD_L

C474

DMIC_DATA

45

C473

<16> HDA_SDOUT_AUDIO

R376 2
R375 2

Add D17<SCA00000A00> for ESD


20081114

10U_0805_10V4Z

10

<16> HDA_SYNC_AUDIO

C603
220P_0402_50V8J

AMP_RIGHT <21>

11

<16> HDA_RST_AUDIO#

AMP_LEFT <21>

20K_0402_1%

C472

10U_0805_10V4Z

R378

C471
MIC1_R

<21> MIC1_R

MIC1_C_L
21
4.7U_0805_6.3V6K
MIC1_C_R
22
4.7U_0805_6.3V6K
MONO_IN
12

C604
220P_0402_50V8J

+3VS

C465

19

5
6

LINE_OUT_L

NC

20

<21> MIC1_L

NC

18

C464

G1
G2

0.1U_0402_16V4Z

15

24

14

23

MIC1_L

C463

2
1

U27

DVDD

2
0.1U_0402_16V4Z

DVDD_IO

0.1U_0402_16V4Z

C467
38

25

20mil

40mil

AVDD2

C462
10U_0805_10V4Z

0.1U_0402_16V4Z
1
1
C466

AVDD1

+VDDA

L24 1
2
FBM-11-160808-700T_0603

For ESD 10/11

L23
MBK1608121YZF_0603
+3VS_DVDD
1
2

1
2
3
4

ACES_88266-04001
CONN@

D17
SM05T1G_SOT23-3

HD Audio Codec

<21> MIC_PLUG#
<21> HP_PLUG#

1
2
3
4

DMIC_CLK_R
0_0603_5%
DMIC_DATA_R
0_0603_5%

DMIC_CLK
1

R369

<17> SB_SPKR

C461 1
1U_0402_6.3V4Z

Title

HD Audio Codec ALC272


Size
B

Document Number

Rev
1.0

KAV10 LA-4781P

Date:

Tuesday, December 30, 2008


G

Sheet

20
H

of

40

Int. Speaker Conn.

+5VAMP
0.1U_0402_16V4Z

1
C384
10U_0805_10V4Z

20mil

JP20

SPKRSPKR+
SPKLSPKL+

C385
2

R385
R386
R387
R388

1
1
1
1

2
2
2
2

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

SPK_RSPK_R+
SPK_LSPK_L+

4
3
2
1

Change to SM01000AL00
20081114

4 GND
3 GND
2
1

6
5

Right
Left

ACES_87213-0400G
CONN@

+5VAMP

GAIN0

GAIN1

ROUT+

18

SPKR+

ROUT-

14

SPKR-

SPKL+

SPKL-

<20> AMP_RIGHT

2 0.47U_0603_10V7K

C395 1

AMP_C_RIGHT 17

2 0.47U_0603_10V7K

RIN-

2 0.47U_0603_10V7K

AMP_C_LEFT

LINLOUT-

NC
EC_MUTE#

19

BYPASS
SHUTDOWN
GND5
GND1
GND2
GND3
GND4

<25> EC_MUTE#

SPK_L+

D13
SM05T1G_SOT23-3

R319
100K_0402_5%

Add D10 D13<SCA00000A00> for ESD


20081114

20081029 Update to 6dB

12

Keep 10 mil width

10
2

C398
0.47U_0603_10V7K

21
20
13
11
1

R318
100K_0402_5%

LIN+
LOUT+

C397 1

<20> AMP_LEFT

D10
SM05T1G_SOT23-3
1

GAIN1
C394 1

2
2

GAIN0

SPK_L-

RIN+

SPK_R+

SPK_R-

2 0.47U_0603_10V7K

C392 1

@ R316
100K_0402_5%
2

@ R315
100K_0402_5%

VDD
PVDD1
PVDD2

U13

16
15
6

TPA6017A2_TSSOP20

C485
330P_0402_50V7K

LINE Out/Headphone Out

C486

330P_0402_50V7K
JHP1

20mil
<20> HP_LEFT

HP_LEFT

<20> HP_RIGHT

HP_RIGHT

1
R374
1
R373

Chenge to 56.2
20081104

HPOUT_L_1
2
56.2_0402_1%
HPOUT_R_1
2
56.2_0402_1%

1
L26
1
L25

1
2
6
3

HPOUT_L_2

2
FBM-11-160808-700T_0603
2
FBM-11-160808-700T_0603

HPOUT_R_2

ohm for DA-HP FSOV

HP_PLUG#

<20> HP_PLUG#

5
7 SHLD1
8 SHLD2
FOX_JAS7331-K30H9-7F
CONN@

MIC1_VREFO_L

MIC1_VREFO_L

D26

D27
RB751V-40TE17_SOD323-2
1 1

1 1

RB751V-40TE17_SOD323-2

1
R405
1
R404

<20> MIC1_L
<20> MIC1_R

2
1K_0603_1%
2
1K_0603_1%

1
L28
1
L27

MIC JACK
2

R402
4.7K_0402_5%
2

R403
4.7K_0402_5%

JMIC1

FBM-11-160808-700T_0603

MIC2_L_1

FBM-11-160808-700T_0603

MIC2_R_1

1
2
6
3
4

1
C488
220P_0402_50V8J

1 <20> MIC_PLUG#
C489
220P_0402_50V8J

MIC_PLUG# 5
7 SHLD1
8 SHLD2

FOX_JAS7331-K30H9-7F
CONN@

l.c
om

(HDA Jack)

Amplifier & Audio Jack

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2007/8/18

Deciphered Date

Document Number

Rev
1.0

KAV10 LA-4781P

he

2006/12/25

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

Tuesday, December 30, 2008

Sheet

21

of

40

CMOS Camera CONN

+3VS

SATA HDD Conn.


1

JSATA1
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

<16> SATA_ITX_C_DRX_P0
<16> SATA_ITX_C_DRX_N0

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

1
2
3
4
5
6
7

C3
0.1U_0402_16V4Z

GND
HTX+
HTXGND
HRXHRX+
GND

2
JP1
1
2
3
4

USB20_N1_1
USB20_P1_1

1
2
3
4

G1
G2

5
6

ACES_88266-04001
CONN@
+3VS

+5VS

<16> SATA_DTX_C_IRX_N0
<16> SATA_DTX_C_IRX_P0

SATA_DTX_C_IRX_N0

1
C507

SATA_DTX_IRX_N0
2
3900P_0402_50V7K

SATA_DTX_C_IRX_P0

1
C510

SATA_DTX_IRX_P0
2
3900P_0402_50V7K

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
GND1
VCC12
GND2
VCC12

D2
USB20_P1

CH3

+3VS

Vp

Add D2<SC300000B00> for ESD


20081114

23
24

CH4

CH2

Vn

CH1

USB20_N1

CM1293-04SO_SOT23-6

2
@ 0_0402_5%

R146
OCTEK_SAT-22SG1G_NR
CONN@

L8

(NEW)

<17> USB20_N1

Change Library

<17> USB20_P1

USB20_N1

USB20_P1

USB20_N1_1
USB20_P1_1

WCM2012F2S-900T04_0805

1
R145

2
@ 0_0402_5%

Add L8<SM0700001310> for EMI


20081114

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

SATA HDD/SSD
Size
B

Document Number

Rev
1.0

KAV10 LA-4781P

Date:

Tuesday, December 30, 2008


G

Sheet

22
H

of

40

2
R614

1
0_0402_5%

U7

2
R651
2
R634

+3VS
+3VALW

2
C825

1
0_0603_5%
1
@ 0_0603_5%

1
0.1U_0402_16V4Z

+XDPWR_SDPWR_MSPWR

1
3
7
9
11
33

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

8
44
45
47
48

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

4
5
14

DM
DP
GPIO0

VREG
MS_D4
NC

10
22
30

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10
MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

XTAL_CTR
MS_D5

13
24

EEDO
EECS
EESK
SD_CMD

15
16
17
36

1
D

C827
4.7U_0603_6.3V6K

R617
100K_0402_5%

C828
0.1U_0402_16V4Z

RST#_L

RST#
MODE_SEL
XTLO
XTLI

<17> USB20_N7
<17> USB20_P7
<26> 5IN1_LED#

RST#
1
0_0402_5%

2
R625

USB20_N7
USB20_P7

Vender suggesttion
C829
1U_0402_6.3V4Z

MODE_SEL

1
@ C830
47P_0402_50V8J

R619
0_0402_5%
2

@
1

1
C831

AGND
AGND

2
R620

1
0_0603_5%

+3VS

XTAL_CTR
If Open , use 12MHz. crystal
If Pull high , use CLKGEN 48MHz.
SD_CMD

RTS5158E-GR_LQFP48_7X7
R623
0_0402_5%
Change

to RT5159-GR <SA00002YP00>
20081104

2
2

6
46

XTAL_CTR

SDCLK_XDD1_MSCLK
1
0_0402_5%

2
R618

@ Y4
12MHZ_16PF_6X12000012

1
@

DGND
DGND

XDCLE
XDCE#
XDALE
SDDAT2_XDRE#
SDDAT3_XDWE#
XD_RDY
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK_L
SDDAT6_XDD7_MSD3
MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
XDD5_MSBS
XDD4_SDDAT1
SDCD
SDWP
XDCD

R624
33_0402_5%

XTLI

2
6P_0402_50V8D

R622
6.19K_0402_1%

2
0_0402_5%

1
R621

<12> CLK_SD_48M
C

RREF

2
1U_0402_6.3V4Z

Change to 0ohm for RTS5159


20081128

2
12
32

1
C826

C832
22P_0402_50V8J
@
1
C833

XTLO

2
6P_0402_50V8D

EMI

+XDPWR_SDPWR_MSPWR

+XDPWR_SDPWR_MSPWR

1
R626
100K_0402_5%

C835
0.1U_0402_16V4Z


RTS5158EEMI).

MSCLK and SDCLK


, (
solution

SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT7_XDD2_MSD2
SDDAT1_XDD3_MSD1
XDD4_SDDAT1
XDD5_MSBS
SDDAT0_XDD6_MSD0
SDDAT6_XDD7_MSD3

32
10
9
8
7
6
5
4

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
XDALE
XDCD
XD_RDY
SDDAT2_XDRE#
XDCE#
XDCLE

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31
41
42

7 IN 1 CONN

7in1-GND
7in1-GND

SD-VCC
MS-VCC

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

20
14
12
30
29
27
23
18
16

SD-CD
SD-WP
SD-CMD

1
2
25

MS-SCLK
MS-BS
MS-INS

26
13
22

SDCLK_XDD1_MSCLK
XDD5_MSBS
MS_INS#

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

17
15
19
24

SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2
SDDAT6_XDD7_MSD3

SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2

1
C879

XD-VCC

SDCD
SDWP
SD_CMD

10U_0805_10V4Z

JREAD1
3

SDCLK_XDD1_MSCLK
1
@

C836
22P_0402_50V8J

7in1-GND
7in1-GND

l.c
om

TAITW_R015-A10-LM_NR
CONN@

f@

Title

5 in 1 Card reader

in

2007/8/18

Size Document Number


Custom KAV10 LA-4781P

Rev
1.0

xa

Deciphered Date

Date:

he

2006/08/04

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

Sheet

Tuesday, December 30, 2008


1

23

of

40

+3V_LAN

+3V_LAN

AR8114A: remove L1,C881,C885,R643. C841=1uF


AR8132:remove R644,R645. C841=0.1uF
C837

U12
1
4

C855
4.7U_0805_10V4Z
8132@

1
2
3
4

C881
0.1U_0402_16V4Z
2 8132@

A0
A1
A2
GND

R628
4.7K_0402_1%

8
7
6
5

VCC
WP
SCL
SDA

TWSI_SCL
TWSI_SDA

Place Close to Chip


LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

AT24C02BN-SH-T_SO8
@

R629
R630
R631
R632

1
1
1
1

2
2
2
2

49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%

VDDHO

CTR12

1U_0603_10V4Z

3
4

<6,15,17,19,25,27> PLTRST#
<25> LAN_WAKE#
1
R633

+3V_LAN

2
4.7K_0402_5%

2
8114@C842
8114@
C842
2
C843
2
C844

<12> CLK_PCIE_LAN

7
41

RX_P

<17> PCIE_ITX_C_PRX_N3

<17> PCIE_PTX_C_IRX_N3

PCIE_PTX_IRX_P3

38

PCIE_PTX_IRX_N3

37

0.1U_0402_16V7K

Place Close to Chip

LAN_X1
LAN_X2

Y5
LAN_X1

25MHZ_20P

C852
27P_0402_50V8J

LAN_X2

2
1
R635 2.37K_0402_1%

TX_P

XTLO
XTLI

31
33

SMCLK
SMDATA

12
34
49

AR8114A 10/100 LAN

TX_N

9
10

C853
27P_0402_50V8J

Atheros

RX_N

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

11
42

AVDDVCO1
AVDDVCO2

DVDDL0
DVDDL1
DVDDL2
DVDDL3

28
32
45
46

+1.2_DVDDL

AVDDL0
AVDDL1
AVDDL2
AVDDL3
AVDDL4

8
16
22
36
39

+1.2_AVDDL

15
19
25

+2.5V_VDDH

1
C854
0.1U_0402_16V4Z
8114@

C860
0.1U_0402_16V4Z
2

C861
0.1U_0402_16V4Z
LAN_MDI0+
LAN_MDI0-

RD+
RDCT
NC
NC
CT
TD+
TD-

RX+
RXCT
NC
NC
CT
TX+
TX-

16
15
14
13
12
11
10
9

+3V_LAN

Q58

RJ45_MIDI1+
RJ45_MIDI1RJ45_CT0
RJ45_CT1
RJ45_MIDI0+
RJ45_MIDI0-

R640
1
1
R639

C862
1000P_1206_2KV7K

C880
0.1U_0402_16V4Z
2 8132@

1
2
R637
0_0603_5%

2
1

0_0603_5%
2
1
1
C856
C857
1000P_0402_50V7K
1U_0603_10V4Z
2
2

L30 FBMA-L11-201209-221LMA30T_0805
1
2
1

LAN_ACTIVITY#
2
R641

+3V_LAN

For EMI.

7
@
2
C864

RJ45_MIDI1-

1
470P_0402_50V7K

6
5
4

C869
100P_0402_50V8J
LAN_SK_LAN_LINK#
1

324546

Place Close to Pin 28

R650
0_0402_5%
8114@
1
JRJ45
1
2
12 Amber LEDR647
8132@ 0_0402_5%
LAN_ACTIVITY#_R
1
11 Amber LED+
8132@ 511_0402_1%
8 PR4-

+3V_LAN

2
@

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

10

1 R642
511_0402_1%

C866
C867
0.1U_0402_16V4Z 0.1U_0402_16V4Z

AVDDVCO2
2

C863
0.1U_0402_16V4Z

If overclocking, R638, L30 stuffed and R637 removed.


If not overclocking, R637, L30 suffed and R638 removed.
AR8132:L30=0ohm,C856=0.1uF. remove C857

+1.2_DVDDL

C865 close to Pin46


AR8114A: C865=0.1uF
AR8132:C865=1uF

C882
0.1U_0402_16V4Z

C865
0.1U_0402_16V4Z

PR4+

16223639

PR2PR3-

1925

Place Close to Pin15

PR3+

C871
0.1U_0402_16V4Z

PR2+
+2.5V_VDDH

PR1SHLD2
PR1+
SHLD1

14

2
2
C870
1U_0402_6.3V4Z

Green LED+

C874
C876
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.2_AVDDL

13

Green LED-

Place Close to Pin8

C872
0.1U_0402_16V4Z

C877
0.1U_0402_16V4Z
1

C873
C875
0.1U_0402_16V4Z 0.1U_0402_16V4Z

FOX_JM3611A-R2125-7F
CONN@

For EMI.

AVDDVCO1

C868
100P_0402_50V8J

R648
5.1K_0402_5%
8114@

@
2
C878

1
470P_0402_50V7K

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2006/08/04

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

+1.2_DVDDL

R638
1

CTR12

MMJT9435T1G_SOT223
8114@
+1.2_AVDDL
1
1
C858
C859
10U_0805_10V4Z
0.1U_0402_16V4Z
8114@
8114@
2
2

75_0402_5%
2
2
75_0402_5%

1 LAN_ACTIVITY#_R
8114@ 511_0402_1%

1
C848
0.1U_0402_16V4Z
2

350uH_NS0013LF

2
R649

1
C847
0.1U_0402_16V4Z
2

L29
FBMA-L11-201209-221LMA30T_0805
1
2
8114@

LAN_ACTIVITY#

+1.2_AVDDL
R636
1 8132@ 2 +2.5V_VDDH
10K_0402_1% R63
0_0402_5%
8114@

4
2

1
2
3
4
5
6
7
8

+3V_LAN

T1
LAN_MDI1+
LAN_MDI1-

AR8114-AL1E_QFN48_6X6

+AVDD_CEN

Layout Notice : Place as close


chip as possible.

J7
2

+3VALW

+3V_LAN

20
21
23
24
26
35

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5

GND

13
14
17
18

@ JUMP_43X39

AVDDH0
AVDDH1
AVDDH2

RBIAS
TESTMODE

27

AVDDL_REG
AVDDL/AVDDL_REG

44

0.1U_0402_16V7K

LAN_ACTIVITY#
LAN_SK_LAN_LINK#

TRXP0
TRXN0
TRXP1
TRXN1

REFCLKP
REFCLKN

47
48

VBG1P18V

43

2
C845
2
C850

LED_ACTn
LED_10_100n
LED_DUPLEXn

40

<17> PCIE_PTX_C_IRX_P3

TWSI_SCL
TWSI_SDA

PERSTn
WAKEn

<17> PCIE_ITX_C_PRX_P3

<12> CLK_PCIE_LAN#

1
1000P_0402_50V7K
1
0.1U_0402_16V7K
1
0.1U_0402_16V7K

CTR12

29
30

2
C839
0.1U_0402_16V4Z

C846
4.7U_0805_10V4Z

VDD33

+2.5V_VDDH/VDD17

+3V_LAN
2
C841

TWSI_CLK
TWSI_DATA

VDD18O

+1.8_VDD/LX

1
8114@ 1U_0603_10V4Z

C838
0.1U_0402_16V4Z

U14
2
C840

C849

+2.5V_VDDH/VDD17 1
+2.5V_VDDH
1
2
2
R643 8132@ 0_0603_5%
R646 8114@ 0_0603_5%

+AVDD_CEN

R627
4.7K_0402_1%

0.1U_0402_16V4Z

+1.8_VDD/LX
1
2
R644 8114@ 0_0603_5%
1
2
L10
8132@ 4.7UH_1008HC-472EJFS-A_5%_1008

0.1U_0402_16V4Z
2
1

Title

AR8114
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
E

24

of

40

+3VALW
+EC_AVCC

High

Low
<32>
<32>
<4>
<4>

KSO1
KSI1

WL_BTN#

KSI5

3G_BTN#

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#

<17> PM_SLP_S3#
<17> PM_SLP_S5#
<17> EC_SMI#

FAN_SPEED1

<28> FAN_SPEED1

EC_TX_P80_DATA
EC_RX_P80_CLK

<19,27> EC_TX_P80_DATA
<19,27> EC_RX_P80_CLK
<26> ON/OFF#
<26> PWR_SUSP_LED
<26> NUM_LED#

PWR_SUSP_LED
NUM_LED#

XCLKI
XCLKO

EC_MUTE# <21>
USB_ON# <28>

USB_ON#

1
@ 0_0402_5%

R90

BT_LED# <26>
TP_CLK <27>
TP_DATA <27>

TP_CLK
TP_DATA

97
98
99
109

SPI Flash ROM

GPIO

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GPI

V18R

LID_SW# <26>

73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

WWAN_LED#
2
R92

BATT_GRN_LED#
CAPS_LED#
BATT_AMB_LED#
PWR_LED
SYSON

EC_LID_OUT#
EC_ON
ICH_POK_EC

WWAN_LED_R#
1
0_0402_5%

WWAN_LED# <19>

EC_RSMRST# <17>
EC_LID_OUT# <17>
RB751V-40TE17_SOD323-2
EC_ON <26>
D12
@
1
2 ICH_POK
BKOFF# <13>
WL_OFF# <19> 1
R103
WXMIT_OFF# <19>

2
0_0402_5%

EC_THERM#
SUSP#
PBTN_OUT#

BATT_TEMP

C179 1

ACIN

C115 1

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

0V
0.25V
0.50V
3.3V

PM_SLP_S4# <17>
GMCH_ENBKL <8>
EAPD <20>
EC_THERM# <17>
SUSP# <29,34,35,36>
PBTN_OUT# <17>
LAN_WAKE# <24>
+3VALW
C116
1U_0603_10V4Z

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

SPI_CLK_R
SPI_SI
SPI_SO

MX25L512AMC-12G_SO8
@

ENE
suggesttion
at C0
revision

+3VALW

8M SPI ROM
1

20mils

FSEL#SPICS# 2
R77
SPI_CLK
2
R88
FWR#SPI_SI 2
R89
SPI_CLK_R
1
33_0402_5%

VGATE <12,17,38>

+3VALW

1
2
22P_0402_50V8J R76

U19
SPI_CS#

20mil

RB751V-40TE17_SOD323-2

Add C117
20081114

SPI_CS#
1
0_0402_5%
SPI_CLK_R
1
10_0402_5%
SPI_SI
1
0_0402_5%

R76R88 for EMI

U10
8

VCC

HOLD

VSS

SPI_SO 2
R80

1 FRD#SPI_SO
0_0402_5%

SST25LF080A_SO8-200mil

tm

C182 1

Vab

0
8.2K
18K
NC

ICH_POK <6,17>

+5VS

BATT_OVP

Rb

NC
100K
100K
100K

@
1
2
+3VS
R104 10K_0402_5%

124

2
C117
EC_SMB_CK2
2
4.7K_0402_5%
EC_SMB_DA2
2
4.7K_0402_5%

Ra

R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)

D19
110
112
114
115
116
117
118

2
4.7K_0402_5%
2
4.7K_0402_5%

+3VS

BRD ID

0
1
2
3

32.768K_1TJS125BJ4A421P

1
R124
1
R125

ID

FSTCHG <34>
BATT_GRN_LED# <26>
CAPS_LED# <26>
BATT_AMB_LED# <26>
PWR_LED <26>
SYSON <29,35>
VR_ON <38>
ACIN <17,31>

0.1U_0402_16V4Z

1
R127
TP_DATA
1
R128

Rb

BOARD ID Table

1
@ 0_0402_5%

R79

ECAGND

11
24
35
94
113

119
120
126
128

C122

TP_CLK

R120
100K_0402_5%

BRD_ID

ICH_POK
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLK1
XCLK0
GND
GND
GND
GND
GND

15P_0402_50V8J

4
OUT

IN
NC

NC
3

X1

Ra

R126
18K_0402_1%

C123
C150

WWAN_LED_R# <28>

BT_OFF# <19>
LID_SW#

SPI Device Interface

SM Bus

KB926QFC0_LQFP128

15P_0402_50V8J

Follow ENE AP sheet


KB926D-AN1-100

AVCC
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

+3VALW
1
R122
1
R123
1
R75
1
R78

67

9
22
33
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC

PS2 Interface

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%

83
84
85
86
87
88

EN_DFAN1 <28>
IREF <34>
CALIBRATE# <34>
+3VALW

77
78
79
80

122
123

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

EN_DFAN1
IREF

l.c
om

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

ai

Swap to WLAN

High

68
70
71
72

DA Output

BATT_TEMP <32>
BATT_OVP <34>
ADP_I <34>

BRD_ID

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

WXMIT_OFF#

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

AD Input

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

ACOFF <34>

2006/08/04

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

KB926/BIOS
Size Document Number
Custom
Date:

f@

WXMIT_OFF#

GPIO15

BATT_TEMP
BATT_OVP

in

KSI5

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

PWM Output

INVT_PWM <13>
BEEP# <20>

ACOFF

Rev
1.0

xa

KSI[0..7]
<26,27,28> KSI[0..7]

INVT_PWM
BEEP#

KAV10 LA-4781P

Tuesday, December 30, 2008

he

<26,27,28> KSO[0..15]

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

21
23
26
27

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

12
13
37
20
38

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

1
2
3
4
5
7
8
10

EC_RST#
EC_SCI#

<17> EC_SCI#

KSO[0..15]

WLAN_OFF#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

<12> CLK_PCI_LPC
<6,15,17,19,24,27> PLTRST#

2
47K_0402_5%

0.1U_0402_16V4Z

KSI1

U8

AGND

1
10_0402_5%

C120

KSO1

69

<17> SERIRQ
<16> LPC_FRAME#
<16> LPC_AD3
<16> LPC_AD2
<16> LPC_AD1
<16> LPC_AD0

For ESD.

2
R69 @
@ 22P_0402_50V8J
1
+3VALW
R74

<16> GATEA20

2
0_0402_5%

C107
2
1

2 10K_0402_5%

1
R66

C109
1000P_0402_50V7K

R67

+3VS
<16> KB_RST#

C161
1000P_0402_50V7K

0.1U_0402_16V4Z
1
2 1 ECAGND
L14
BK1608LL121-T 0603

+EC_AVCC
C194
@
1000P_0402_50V7K

C119
0.1U_0402_16V4Z

C110
0.1U_0402_16V4Z

C196

C114
0.1U_0402_16V4Z

+3VALW

1
2
BK1608LL121-T 0603

C193
0.1U_0402_16V4Z

L13

Sheet

25

of

40

+3VS

LED

+3VALW

ON/OFF switch

+3VS

R195

R347

To PWR/B Conn.

100K_0402_5%

+5VS
ON/OFF#

ON/OFFBTN#

JP2

51ON# <31>

<25> PWR_LED
<25> PWR_SUSP_LED

C4

D1

Compal Footprint

RLZ20A_LL34
@

Q3 2N7002_SOT23
SDIO_LED#

<27> SDIO_LED#

ACES_85201-0605
CONN@

MEDIA_LED#

Q45B
2N7002DW-T/R7_SOT363-6

@ 1000P_0402_50V7K
1

+3VS

1
2
3
4
5
6

ON/OFFBTN#
PWR_LED
PWR_SUSP_LED

DAN202U_SC70

+5VALW

ON/OFF# <25>

51_ON#

SATA_LED#

D14

<23> 5IN1_LED#
<16> SATA_LED#

Bottom Side

Q45A
2N7002DW-T/R7_SOT363-6

1
@ 10K_0603_5%
1
@ 10K_0603_5%

@ 10K_0402_5%

TOP Side

2
R73
2
R96

MEDIA_LED#

1
SDIO@

S 2N7002_SOT23

Q1

2
G

R3

LED2
+5VALW

10K_0402_5%
1

+5VALW

1
2
R284 1.2K_0402_5%
1
2
R286 330_0402_5%

follow JAWD0
20080623

4
2

EC_ON

YG

<25> EC_ON

+3VS
D

BATT_AMB_LED#

BATT_GRN_LED#

BATT_AMB_LED# <25>
BATT_GRN_LED# <25>

HT-297DQ-GQ_AMB-YG

LID Switch
Bluetooth LED

MEDIA_LED

+5VS

+3VALW

(GREEN)
2

R4
1K_0402_5%
1
LED6

LED5

1
LED3

R2
1K_0402_5%

HARVATEK
BT_LED#

KSO1

Bluetooth Button

HT-191UYG-DT YEL/GRN_0603
MEDIA_LED#

BT_LED# <25>

HT-191UYG-DT YEL/GRN_0603
NUM_LED#

LED4
HT-191NBQA_BLUE_0603
BT@
1

A3212ELHLT-T_SOT23W-3

R1
1K_0402_5%

1
C111
U9

10P_0402_50V8J

LID_SW# <25>

GND

C112
0.1U_0402_16V4Z

OUTPUT

+5VS

(GREEN)

2
R518
1.5K_0402_1%
BT@

VDD
1

CAPS_LED

+5VS

(GREEN)

(BLUE)
R71
47K_0402_5%

NUM_LED

+5VS

NUM_LED# <25>

HT-191UYG-DT YEL/GRN_0603
CAPS_LED#

CAPS_LED# <25>

KSI2

KSI2

D33

Add D33<SCA00000A00> for ESD


20081114
KSI2 <25,27>
PSOT24C_SOT23

BT@SMT1-05-A_4P

KSO1

5
6

<25,27,28> KSO1

BT_BTN#

KSO1

KSI2

SW4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

LID SW/LED/CMOS
Size
B
Date:

Document Number

Rev
1.0

KAV10 LA-4781P
Tuesday, December 30, 2008

Sheet

26

of

40

To TP/B Conn.
JP11

1
2
3
4
5
6
7
8
9
10
11
12

LEFT_BTN#

INT_KBD Conn.

+5VS
TP_DATA

<25> TP_DATA

KSO4

C145 1

KSI0
KSI1
KSI2
KSO0
KSO1
KSO2
KSI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSI4
KSO9
KSI5
KSI6
KSO10
KSO11
KSI7
KSO12
KSO13
KSO14
KSO15

100P_0402_50V8J

KSI1

C133 1

100P_0402_50V8J

KSO5

C142 1

100P_0402_50V8J

KSI2

C140 1

100P_0402_50V8J

KSO6

C148 1

100P_0402_50V8J

KSI3

C141 1

100P_0402_50V8J

KSO7

C146 1

100P_0402_50V8J

KSI4

C137 1

100P_0402_50V8J

KSO8

C147 1

100P_0402_50V8J

KSI5

C138 1

100P_0402_50V8J

KSO9

C136 1

100P_0402_50V8J

KSI6

C135 1

100P_0402_50V8J

KSO10

C129 1

100P_0402_50V8J

KSI7

C134 1

100P_0402_50V8J

KSO11

C128 1

100P_0402_50V8J

KSO0

C139 1

100P_0402_50V8J

KSO12

C126 1

100P_0402_50V8J

KSO1

C143 1

100P_0402_50V8J

KSO13

C127 1

100P_0402_50V8J

KSO2

C131 1

100P_0402_50V8J

KSO14

C124 1

100P_0402_50V8J

KSO3

C132 1

100P_0402_50V8J

KSO15

C125 1

100P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25
26

GND1
GND2

TP_CLK

<25> TP_CLK

C157
100P_0402_50V8J

RIGHT_BTN#
C158
100P_0402_50V8J

G13
G14

13
14

ACES_87151-1207G
CONN@

LEFT_BTN#

+5VS

TP_CLK

RIGHT_BTN#
C156
0.1U_0402_16V4Z

TP_DATA

100P_0402_50V8J

D18

D9

PSOT24C_SOT23

PSOT24C_SOT23

Add D9 D18<SCA00000A00> for ESD


20081114
SW 2
SMT1-05-A_4P
1

RIGHT_BTN#

SW 3
SMT1-05-A_4P
1

5
6

ACES_85201-24051
CONN@

LEFT_BTN# 3

5
6

C144 1

JP12
KSI0

<25,26,28>

KSO[0..15] <25,26,28>

1
2
3
4
5
6
7
8
9
10
11
12

KSI[0..7]

KSO[0..15]

KSI[0..7]

To SDIO Conn.
JP6
<26> SDIO_LED#

<6,15,17,19,24,25>

PLTRST#

<12> CLK_PCIE_CARD#
<12> CLK_PCIE_CARD
<17> PCIE_ITX_C_PRX_N2
<17> PCIE_ITX_C_PRX_P2
<17> PCIE_PTX_C_IRX_N2
<17> PCIE_PTX_C_IRX_P2

SDIO_LED#
PLTRST#

+3VS

CLK_PCIE_CARD#
CLK_PCIE_CARD
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2

1
2
3
4
5
6
7
8
9
10
11
12
13
14

EC DEBUG PORT

1
2
3
4
5
6
7
8
9
10
11
12

JP14
+3VALW
<19,25> EC_TX_P80_DATA
<19,25> EC_RX_P80_CLK

EC_TX_P80_DATA
EC_RX_P80_CLK

1
2
3
4

1
2
3
4

ACES_85205-0400
CONN@

GND1
GND2

l.c
om

ACES_87213-1200G
CONN@

ho

tm

ai

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

KB/SDIO/TP/LPC Debug CONN


Size
B
Date:

Document Number

in

2007/8/18

Rev
1.0

xa

Deciphered Date

KAV10 LA-4781P

he

2006/08/18

Issued Date

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Tuesday, December 30, 2008

Sheet
1

27

of

40

USB CONN. 1
1

+5VALW

Change to SA000017B00
20081212

+USB_VCCA

W=80mils

+USB_VCCA
1
+USB_VCCA
U2

C34
0.1U_0402_16V4Z
2
1
R130
@ 200K_0402_5%

1
2
3
4

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

C15
330P_0402_50V7K
JUSB1
1
2
3
4

USB20_N0_1
USB20_P0_1

RT9711PS_SO8

USB_ON#

USB_OC#0 <17>

1
<25> USB_ON#

+ C231
150U_Y_6.3VM

C16
@ 1000P_0402_50V7K

5
6
7
8

VCC
DD+
GND
GND1
GND2
GND3
GND4

SUYIN_020173MR004S512ZL
CONN@
1

R144

0_0402_5%

D29
6

CH3

USB20_N0_1

CH2

L9
<17> USB20_P0

+USB_VCCA

Vp

Vn

<17> USB20_N0

USB20_P0

USB20_N0

USB20_P0_1

USB20_N0_1

@ WCM2012F2S-900T04_0805
USB20_P0_1

CH4

CH1

CM1293-04SO_SOT23-6

1
R136

2
0_0402_5%

Add D29<SC300000B00> for ESD


20081114

To USB/B Conn.
KSO1
KSI1

WL_BTN#

KSI5

3G_BTN#

FAN1 Conn
+5VS
C10

+5VS

10U_0805_10V4Z
2

JP3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

+5VALW
1

1
3

U3

<25> EN_DFAN1

1
R46

VEN
VIN
VO
VSET

GND
GND
GND
GND

+VCC_FAN1
VSET
2
330_0402_5%
G993P1UF_SOP8
1
C427
0.01U_0402_25V7K

8
7
6
5

EN_DFAN1

1
2
3
4

D8
1SS355_SOD323-2

BAS16_SOT23-3
C396
10U_0805_10V4Z
1
2

+3VS

<25> USB_ON#
<19> MINI1_LED#
<25> WWAN_LED_R#
<25,26,27> KSO1
<25,27> KSI1
<25,27> KSI5

USB_ON#
MINI1_LED#
WWAN_LED_R#
KSO1
KSI1
KSI5
USB20_N2
USB20_P2

<17> USB20_N2
<17> USB20_P2

USB20_N3
USB20_P3

<17> USB20_N3
<17> USB20_P3

C399
1000P_0402_50V7K
1
2

20080430
Add soft-start for +5VS drop issue

D5
1

Change to SA000022J00<RICHTEK>
20080227

+3VS

40mil
2

ACES_87213-1600G
CONN@

R305
10K_0402_5%
JP13

+VCC_FAN1

1
2
3

<25> FAN_SPEED1
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
G1
G2

C393
1000P_0402_50V7K

ACES_85205-03001
CONN@

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

USB PORTS/FAN
Size
B
Date:

Document Number

Rev
1.0

KAV10 LA-4781P
Tuesday, December 30, 2008

Sheet
E

28

of

40

+5VALW TO +5VS

C76

R50

10U_0805_10V4Z
2
2
1U_0603_10V4Z

C214

+3VS
SI4800BDY-T1-E3_SO8
8
7
6
5

470_0603_5%

Q12
1
2
3

10U_0805_10V4Z
2
2
10U_0805_10V4Z

+5VALW

2
1

C74

C215

C201

C202

10U_0805_10V4Z
2
2
1U_0603_10V4Z

R179
470_0603_5%

R302
100K_0402_5%

3
C108

SUSP

1
2
R185
200K_0402_5%

+VSB

SYSON#

C255

Q17A
SUSP

0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6

Q8A
SUSP

0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6

5 SUSP
4

2
R68
100K_0402_5%

Q17B
2N7002DW-T/R7_SOT363-6

Q8B
2N7002DW-T/R7_SOT363-6
4

+VSB

5VS_GATE

10U_0805_10V4Z
2
2
10U_0805_10V4Z

1
2
3

Q6

C96

+3VALW

SI4800BDY-T1-E3_SO8
8
7
6
5
4

C97

+3VALW TO +3VS
+5VS

3 1

+5VALW

Q28A
SYSON

2
2N7002DW-T/R7_SOT363-6
1

<25,35> SYSON

RTCVREF

+1.8V

<37> SUSP

SUSP

Q28B
5

<25,34,35,36> SUSP#

2N7002DW-T/R7_SOT363-6

2 SUSP
G
Q7
2N7002_SOT23

2 SYSON#
G
Q23
2N7002_SOT23

l.c
om

2 SUSP
G
Q24
2N7002_SOT23

2 SUSP
G
Q15
2N7002_SOT23

2 SUSP
G
Q2
2N7002_SOT23

R279
470_0603_5%

R61
470_0603_5%

R280
470_0603_5%

R169
470_0603_5%

R297
100K_0402_5%
@
1

+0.9VS

R18
470_0603_5%

+VCCP
2

+2.5VS

R298
100K_0402_5%

+1.5VS

+5VALW

DC INTERFACE

in

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
B
Date:

xa

2007/8/18

Deciphered Date

Document Number

Rev
1.0

KAV10 LA-4781P

he

2006/08/18

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

Tuesday, December 30, 2008

Sheet

29

of

40

H29
H

H_3P8X3P2N
H11
H

H18
H
@
1

H_2P1

H19
H

H10
H
@

@
1

H20
H

H_3P2

H14
H
@

H26
H
@

@
1

H17
H

H27
H

H28
H

H1
H

@
1

H16
H

H22
H

H3
H

H_2P8

GNDA
@
1

FM3

FM4
@

@
1

FM2

FM1

FIDUCIAL_C40M80

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/18

Deciphered Date

2007/8/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Screw
Size
B
Date:

Document Number

Rev
1.0

KAV10 LA-4781P
Tuesday, December 30, 2008

Sheet

30

of

40

PR1
1M_0402_1%
1
2

VIN

VIN

VIN

P
G

PR5
22K_0402_5%
1
2

PC5
PR6
1000P_0402_50V7K
20K_0402_1%

PC6
0.1U_0603_25V7K

PR7
10K_0402_5%

PC1
1000P_0402_50V7K

1
1
PC2
100P_0402_50V8J

LM358DT_SO8
PD3
RLZ4.3B_LL34

PC4
100P_0402_50V8J

1
PC3
1000P_0402_50V7K

4
3
2
1

GND 4
GND 3
2
1

6
5

PACIN

PR102
10K_0402_5% PU1A
2
1 1 0

<17,25> ACIN

PR3
84.5K_0402_1%

PR4
100K_0402_1%
1
2

SP02000GC00
PJP1

@ PR2
10K_0402_5%

PL1
SMB3025500YA_2P
1
2

DC_IN_S1

VS

ACES_87213-0400G
CONN@

PR8
10K_0402_5%
1
2

RTCVREF

<34> PACIN

Vin Dectector

Min.
H-->L 16.976V
L-->H 17.430V

PBJ1
2

+RTCBATT
+RTCBATT

Typ
17.525V
17.901V

Max.
17.728V
18.384V

ML1220T13RE
45@

VIN

PJ2
2

+5VALW

+0.9VS
3

(1A,40mils ,Via NO.=2)

+VSB

+1.8VP

+1.8V

JUMP_43X118

(4.6A,200mils ,Via NO.=10)


1

PC128
0.1U_0402_16V7K

PJ9
1

+VCCP

JUMP_43X118

PC127
0.1U_0402_16V7K

+2.5VS

JUMP_43X118

(0.14A,40mils ,Via NO.=2)

(7.09A,300mils ,Via NO.=16)

+2.5VSP
2

JUMP_43X79

PJ8
PC126
0.1U_0402_16V7K

RTCVREF

PC129
0.1U_0402_16V7K

PJ7
1

JUMP_43X39

+1.05VSP

+1.5VS

(3.464A,160mils ,Via NO.=8)

+0.9VSP

(120mA,40mils ,Via NO.= 2)

PC8
0.1U_0603_25V7K

PJ5
1

1
2

PC125
0.1U_0402_25V6

JUMP_43X118

JUMP_43X118

(5.58A,240mils ,Via NO.= 12)

+VSBP

VS

PC130
0.1U_0402_16V7K

<26> 51ON#

TP0610K-T1-E3_SOT23-3

PR13
22K_0402_1%
1
2

PC7
0.22U_1206_25V7K

PR12
100K_0402_1%

+1.5VSP

PJ6

+3VALW

1
PQ1
N1

PR10
68_1206_5%
2

PR11
200_0603_5%
1
2

PC124
0.1U_0402_16V7K

PR9
68_1206_5%

CHGRTCP

PJ4
2

+5VALWP

BATT+

PJ3
1

(4.69A,200mils ,Via NO.= 10)

PD4
RLS4148_LL34-2
PD5
RLS4148_LL34-2

JUMP_43X118

PC123
0.1U_0402_16V7K

+3VALWP

PR14
200_0603_5%

N2

PC9
G920AT24U_SOT89-3
1
10U_0805_10V4Z

l.c
om

IN
GND

PC10
1U_0805_25V4Z

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

in

Deciphered Date

DCIN & DETECTOR


Size Document Number
Custom
Date:

xa

2007/09/20

Rev
1.0

he

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

f@

ho

tm

OUT

ai

3.3V

PU2

PR16
560_0603_5%
1
2

+CHGRTC

PR15
560_0603_5%
1
2

KAV10 LA-4781P

Tuesday, December 30, 2008


D

Sheet

31

of

39

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
VL
VL
2

VMB
PJP2

3
2

+
-

PQ2
DTC115EUA_SC70-3
3

PU3A
LM393DG_SO8

VL

PR25
100K_0402_1%

PR26
1K_0402_1%

PR23
100K_0402_1%
2
1

+3VALW P

1
2

PR24
6.49K_0402_1%
2
1

PC15
1000P_0402_50V7K

PC14
0.22U_0603_10V7K

PR21
100_0402_1%
1

PR20
100_0402_1%

PR22
17.4K_0402_1%

PD6
RLS4148_LL34-2
2
1

O
4

TM_REF1

PR19
7.32K_0402_1%
1
2

MAINPW ON <33>
1

PR18
47K_0402_1%
1
2

PC13
0.01U_0402_25V7K

PR17
47K_0402_1%

PC12
1000P_0402_50V7K

PC11
0.1U_0603_25V7K

PH1
100K_0603_1%_TSM1A104F4361RZ

SUYIN_200275MR005G11VZR

BATT+
1

EC_SMCA
EC_SMDA

PL2
SMB3025500YA_2P
1
2

BATT_S1

7
6
5
4
3
2
1

7
6
5
4
3
2
1

BATT_TEMP <25>

PH2 near main Battery CONN :


BAT. thermal protection at 92 degree C
Recovery at 56 degree C

EC_SMB_CK1 <25>
EC_SMB_DA1 <25>

VL

@ PR27
47K_0402_1%

@ PR28
47K_0402_1%
1
2

@ PH2
100K_0603_1%_TH11-4H104FT
2
1

8
6

@ PR32
15.4K_0402_1%

O
-

@ PD7
LL4148_LL34-2
2
1

@ PC18
0.22U_0603_16V7K

PU3B
LM393DG_SO8

PR31
22K_0402_1%

5
TM_REF1

1
2

TP0610K-T1-E3_SOT23-3

PR30
@ 13.7K_0402_1%
1
2

PC17
0.1U_0603_25V7K

VL

1
2
2

PC16
0.22U_1206_25V7K

1
PR29
100K_0402_1%

VL

+VSBP

PQ3
3

B+

VL

PR34
0_0402_5%
2

PQ4
2N7002W -T/R7_SOT323-3

2
G

<33> SPOK

PC19
0.1U_0402_16V7K

PR33
100K_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

BATTERY CONN / OTP


Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008


D

Sheet

32

of

39

ISL6237_B+

ISL6237_B+

DL3

23

16

LGATE1

18

DL5

LGATE2

FB3
@ PR42
10K_0402_1%

VL

30

OUT2

32

REFIN2

PGND

22

OUT1

10

FB1

11

BYP

SKIP

29

2VREF_ISL6237
1

PC25
2200P_0402_50V7K
2
1

PR39
4.7_1206_5%

PR41
61.9K_0402_1%
2

PHASE1

1
+ PC35
150U_D2E_6.3VM_R18

PHASE2

PQ8
SI7716DN-T1-E3_PAK1212-8

25

LX5

2
C

PR43
9.76K_0402_1%
1
2

LX3

3
2
1

PC32
0.1U_0603_25V7K

1
2
3

DH5
PR40 0_0603_5%
BST5A 2
1

17

15

BOOT1

UGATE1

BOOT2

PC29
1U_0603_10V6K
1
2

UGATE2

+5VALWP

PL4
8.2UH_FDV0630-8R2M=P3_3.7A_20%
2
1

PC34
680P_0402_50V7K

3
2
1

PC28
4.7U_0805_6.3V6K
2
1

7
LDO

24

VCC

26

PC31
0.1U_0603_25V7K

PC33
680P_0402_50V7K

19

PVCC

PR38
0_0402_5%

TP

PQ6
SI7326DN-T1-E3_PAK1212-8

1
1
1
PC30
330U_D2E_6.3VM_R25M

DH3
PQ7
PR37 0_0603_5%
SI7716DN-T1-E3_PAK1212-8
2
1 BST3A

PR36
4.7_1206_5%

33

VIN

PU4

+3VALWP

1
2
3
PL3
8.2UH_FDV0630-8R2M=P3_3.7A_20%
1
2

PC27
1U_0603_10V6K
1
2

PC26
0.1U_0603_25V7K

PQ5
SI7326DN-T1-E3_PAK1212-8
4

PC24
4.7U_0805_25V6-K
2
1

VL

PC20
4.7U_0805_25V6-K
2
1

JUMP_43X118

PC22
2200P_0402_50V7K
2
1

PC21
4.7U_0805_25V6-K
2
1

PC23
4.7U_0805_25V6-K
2
1

PR35
0_0805_5%
1
2

PJ10

B+

FB5

REF

PC36 0.22U_0603_10V7K

LDOREFIN

@ PR44 0_0402_5%
2
1

VL

PR45 0_0402_5%
1
2

EN_LDO

POK1

13

SPOK <32>

ILIM1

12

ILM1

ILIM2

31

ILIM2

TPS51427_QFN32_5X5

PR48
330K_0402_1%
2
1

PR49
330K_0402_1%

+5VALWP Ipeak=5.58A ; Imax=3.906A


Choke DCRmax=65.6m ohm
Rds(on)=16m ohm(max) ; Rds(on)=13.5m ohm(typical)
Vlimit=(5E-06 * 200K)/10=100mV
Ilimit=100mV/16m ~ 100mV/13.5m
=6.06A ~ 7.41A
Iocp=Ilimit+Delta I/2
=6.614A ~ 7.97A
Delta I=1.123A (Freq=400KHz)

PR53
0_0402_5%

2VREF_ISL6237

PC146
1U_0603_10V6K
1
2

PR51
0_0402_5%

1
2VREF_ISL6237

21

EN2

EN1

27
2

14

GND

28

TON

POK2

1
2

<32> MAINPWON

PC38
0.047U_0603_16V7K

@ PR55
47K_0402_5%
1
2

PR54
0_0402_5%
2
1

PR52
806K_0603_1%

@ PR50
0_0402_5%

NC

NC

2
1

PC37
0.22U_0603_10V7K

VL

PD12
1SS355TE-17_SOD323-2

@ PC39
0.047U_0402_16V7K

PQ35
TP0610K-T1-E3_SOT23-3

l.c
om

+3.3VALWP Ipeak=4.687A ; Imax=3.281A


Choke DCRmax=65.6m ohm
Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical)
Vlimit=(5E-06 * 200K)/10=100mV
Ilimit=100mV/16.5m ~100mV/13.5m
=6.06A ~ 7.41A
Iocp=Ilimit+Delta I/2
=6.614A ~ 7.964A
Delta I=1.108A (Freq=300KHz)

PR47
200K_0402_1%
1
2

20

PR46
100K_0402_1%
1
2

VS

PD8
GLZ5.1B_LL34-2
1
2

ai

ho

+5VALWP/+3VALWP
Size
Document Number
Custom
Date:

f@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Rev
1.0

KAV10 LA-4781P

in

2008/09/20

xa

Deciphered Date

Tuesday, December 30, 2008

he

2007/09/20

Issued Date

tm

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Sheet
1

33

of

39

B+
@ PD1 B540C_SMC
1
2

2
3

PC44
2200P_0402_25V7K
2
1

PR195
200K_0402_1%
1
2

1 1

SUSP#

SUSP# <25,29,35,36>

VIN

PD17
1SS355TE-17_SOD323-2
2
1
2

PQ38
DTC115EUA_SC70-3

CSON

22

CELLS

CSOP

21

CSIN

VCOMP

CSIP

19

ICM

PHASE

18

VREF

UGATE

17

DH_CHG

CHLIM

BOOT

16

ACLIM

VDDP

15

CSOP
PQ11
SI7326DN-T1-E3_PAK1212-8
2

PL5
8.2UH_FDV0630-8R2M=P3_3.7A_20%
CHG
1
2

11

VADJ

LGATE

14

1
RB751V-40_SOD323-2
1
26251VDD

12

GND

PGND

13

PR208
4.7_0603_5%
PC161
4.7U_0805_6.3V6K

BATT+

PR62 0.05_1206_1%
4

PQ13
SI7326DN-T1-E3_PAK1212-8

6251VDDP
DL_CHG

PR206
PC159
2.2_0603_5%
0.1U_0603_25V7K
BST_CHG 1
2 BST_CHGA 2
1
PD18

3
2
1

10

ICOMP

20

CSON

PR199
20_0603_5%
1
2
PC153
0.047U_0603_16V7K
1
2
PR200
20_0603_5%
2
1
PR201
PC156
20_0603_5%
0.1U_0603_25V7K
1
2
PR203
2_0402_5%
LX_CHG

PC53
10U_1206_25V6M
2
1

EN

2 PACIN
2N7002W
-T/R7_SOT323-3
G
S

PQ40D

PC52
10U_1206_25V6M
2
1

23

PC150
0.1U_0603_25V7K
2
1

ACSET ACPRN

PC152
0.1U_0603_25V7K
2
1

PR57
4.7_1206_5%

24

DCIN

PR213
20K_0402_1%

PD14
1SS355TE-17_SOD323-2
ACOFF
1
2

DCIN

VDD

0.1U_0402_16V7K
PR212
38.3K_0402_1%
6251VREF 1
6251aclim
2

PR207
100K_0402_1%

PC160
0.01U_0402_25V7K
2
1

<25> IREF

6251VREF

PC158
1
2

PR205
62K_0402_1%
2
1

2
PC157
@ 100P_0402_50V8J

VIN

PC40
680P_0402_50V7K

PR204
100_0402_1%
1
2

PU5
1

0.01U_0402_25V7K

PR190
47K_0402_1%
1
2

FSTCHG <25>

3
2
1

6.81K_0402_1%
2

1
ACOFF

6800P_0402_25V7K
2

FSTCHG

RB715F_SOT323-3

1
3

2N7002W -T/R7_SOT323-3

PR202

6251_EN

2
2 1

PC155
1
2

<25> ADP_I

PACIN

PR197
22K_0402_5%
1
2

PQ41
DTC115EUA_SC70-3

<25> ACOFF

1
PR198
2

PQ39
2
G

100K_0402_1%

1
2

PC154
1

<31> PACIN

PR193
150K_0402_1%

@ RHU002N06_SOT323-3

PR194

6251VDD

2
PC149
0.1U_0402_16V7K

PQ44

PQ37
DTC115EUA_SC70-3

8
7
6
5

PR192
10K_0402_1%

PD15

2
G

DCIN

PR196
10K_0402_5%
2
1

<25> FSTCHG

CSIN

PQ34
@ DTC115EUA_SC70-3

1
2
3
PC42
4.7U_1206_25V6K
2
1

P3

PD16
1SS355TE-17_SOD323-2
1

CSIP

PR59
200K_0402_1%

JUMP_43X118

PJ11
2

PQ36 TP0610K-T1-E3_SOT23-3

PR152
@ 47K_0402_1%

PQ33
@ DTA144EUA_SC70-3

PC45
0.1U_0603_25V7K
2
1

PQ12
P1403EVG_SO8

CHG_B+

PR56 0.05_1206_1%
4

PC148
2.2U_0603_6.3V6K
2
1

B340A_SMA2

B+

P3
8
7
6
5

PC43
4.7U_1206_25V6K
2
1

PQ10
P1403EVG_SO8
1
2
3

100K_0402_1%

PR191
100K_0402_1%
2
1

PC147
5600P_0402_25V7K
1
2

P2
PD13

VIN

ISL6251AHAZ-T_QSOP24

3.99V

PR74
340K_0402_1%

PR77
10K_0402_1%
1
2

2
PU1B
LM358DT_SO8
7 0

VADJ--->Ground--->3.39V

PR79
105K_0402_1%

Vcell=(0.175*VADJ+3.99)
4

Normal 3S LI-ON Cells

PC66
0.01U_0402_25V7K

VADJ-->VREF-->4.41V

CV mode

Charging Voltage
(0x15)

BATT Type

<25> BATT_OVP

PR76
499K_0402_1%
2

4.35V

Per cell=3.5V

Pre Cell

CC=0.3~1.76A
IREF=1.62*Icharge
IREF=0.486V~2.85V
3.24V==>2A

BATT-OVP=0.1112*VMB

CALIBRATE#

VS

LI-3S :13.5V----BATT-OVP=1.5012V

@ PR220
499K_0402_1%

Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)
where Vaclm=0.8199V, Iinput=1.343A

PC65
0.01U_0402_25V7K

<25> CALIBRATE#

@ PR211
301K_0402_1%
1
2

CP mode
Vaclim=2.39*(20K/(20K+38.3K))=0.8199V

VMB

CP = 85%*Iada ; CP = 1.343A

Iada=0~1.58A(30W)

12600mV

12.60V
Charger ADJ

Calibrate#

4.2V

N/A

3.99V
4.35V

PR211

PR220

301K

499K

301K

499K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

CHARGER
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008


D

Sheet

34

of

39

OZ813A_B+

PJ12

+1.5VSP

1
2

PR214
51_0402_1%

1
+

PC82
330U_B2_2.5VM

PR224
@ 2.8K_0402_1%

PD20

PC172
2.2U_0402_6.3V6M

BST_1.8V 1

PC164
22P_0402_50V8J

1.5VS2N

PR216
147K_0402_1%
1
2
PC74
2200P_0402_25V7K
1
2

PC166
1U_0402_6.3V6K

1
2

PR146
51_0402_1%

PC118
330U_B2_2.5VM

2200P_0402_25V7K

1
PR228
@2.8K_0402_1%
2

PC176
2200P_0402_25V7K

1.8VS1N

PQ23
SI7326DN-T1-E3_PAK1212-8

PC81
1
2

1.8VS1P

1
@ PC78
0.01U_0402_25V7K

+1.8VP
1

PC174
2
1

3
2
1

PR226
PR227
100K_0402_1% 90.9K_0402_1%
1
2 1
2

PC175
22P_0402_50V8J

4.7U_0805_25V6-K

DH_1.8V-2

DL_1.8V

1.8VS1N
1.8VS1P

OZ813A_B+

PL7
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2

PC95
PR148
680P_0402_50V7K
4.7_1206_5%
2
1
2
1

RB751V-40_SOD323-2

PR103
0_0402_5%
2
1

B+

PC165
2200P_0402_25V7K
2
1

1.5VS2P

PC122
680P_0402_50V7K

+5VALW

PC79
4.7U_0805_25V6-K
2
1

0.1U_0402_16V7K
PC171
2
1

VSET1
CS1N
CS1P
PGD1
LX1
HDR1
7
8
9
10
11
12
2

2
1

DL_1.5V

DH_1.8V-1

PC173
1000P_0402_50V7K

+5VALW

25

PR147
4.7_1206_5%
2
1
2

LX1.8V
PR225
150K_0402_1%

PR215
100K_0402_1%
1
2

1
18
17
16
15
14
13

PC170
0.01U_0402_25V7K

1
2

PC169
1U_0402_6.3V6K

1
2

2
PR223
75K_0402_1%
1

PR222
124K_0402_1%

2
1

BST2
LDR2
VDDP
GDNP
LDR1
BST1

1.8SET

PR229
150K_0402_1%

RB751V-40_SOD323-2

OZ813LN_QFN24
ON/SKIP2
VIN
VREF
TSET
VDDA
ON/SKIP1

1.5VSET

PD19

BST_1.5V

VSET2
CS2N
CS2P
PGD2
LX2
HDR2

GNDA
1
2
3
4
5
6

24
23
22
21
20
19

2
PR218
1K_0402_1%
1
2

PR217
22_0402_1%
1
2

PU6

PC163
0.1U_0402_16V7K

AO4932_SO8

PL6
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2

1
PC162
1000P_0402_50V7K

OZ813A_DREF

<25,29> SYSON

DL_1.5V

LX_1.5V

1.5VSET

VFB=2.75V
PC168
0.1U_0402_10V7K
2
1

PC167
0.022U_0402_16V7K
2
1

PR221
24K_0402_1%
1
2

1
2
3
4

D2
D2
G1
S1

DH_1.5V-1
@ PC121
0.01U_0402_25V7K

+5VALW

PR219
0_0402_5%
2
1

G2
S2/D1
S2/D1
S2/D1

JUMP_43X118

4.7U_0805_25V6-K

1.5V_EN
1

<25,29,34,36> SUSP#

DH_1.5V-2

1.5VS2P

PR151
0_0402_5%
2
1

8
7
6
5

PC76
1

PQ32

1.5VS2N
1

4.7U_0805_25V6-K
PC77
2
1

PQ24
SI7716DN-T1-E3_PAK1212-8

3
2
1

<1.5VSP>

DCR 21m ohm(max)

Cout ESR=15m ohm

<1.8VP>

DCR 21m ohm(max)

Cout ESR=15m ohm

Vo=VFB*(PR225/(PR225+PR223))=1.8V
Ipeak=4.6A, Imax=3.22A, Iocp=6A

l.c
om

Vo=VFB*(PR229/(PR229+PR222))=1.5V
Ipeak=3.464A, Imax=2.425A, Iocp=5A

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

in

Deciphered Date

1.5VSP / 1.8VP
Size Document Number
Custom
Date:

xa

2007/09/20

Rev
1.0

he

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

f@

ho

tm

ai

KAV10 LA-4781P

Tuesday, December 30, 2008


D

Sheet

35

of

39

1
2

PC91
4.7U_0805_25V6-K

1
2

5
PR108
0_0402_5%
1
2

B+

PR109
2.2_0603_5%
BST_1.05V 1
2

PQ31
SI7326DN-T1-E3_PAK1212-8

TRIP

11

V5DRV

10

2
PR105
14K_0402_1%

DL_1.05V

DRVL

LX_1.05V
+5VALW

PQ30
AO4712_SO8

1
4

TPS51117RGYR_QFN14_3.5x3.5

PC90
4.7U_0805_10V6K

+1.05VSP

1
+ PC94
330U_B2_2.5VM

PGND
8

PGOOD

GND

PC92
@ 47P_0402_50V8J
1
2

6
2

PC87
1U_0603_10V6K

12

VFB

LL

PR106
4.7_1206_5%

14

15

V5FILT

13

DH_1.05V

DRVH

PC88
680P_0603_50V7K

VOUT

VBST

PL11
1.2UH +-30% 1164AY-1R2N=P3 10.1A
1
2

5
6
7
8

PR110
422_0603_1%
1
2

TON

PC93
0.1U_0603_25V7K
BST_1.05V-1 1
2

3
2
1

+5VALW

TP

PU9

EN_PSV

@PC89
@
PC89
0.1U_0402_16V7K

PR189
30K_0402_5%

<25,29,34,35> SUSP#

PR144
300K_0402_5%
1
2

@ JUMP_43X79

3
2
1

PC86
4.7U_0805_25V6-K

PJ16
1.05V_B+

PR145
8.2K_0402_1%
1
2

PR104
20.5K_0402_1%

<Vo=1.05V> VFB=0.75V
Vo=VFB*(1+PR145/PR104)=0.75*(1+8.2K/20.5K)=1.05V
Fsw=261KHz
Cout ESR=15m ohm Rdson(max)=16.5m Rdson(typical)=13.5m
Ipeak=7.09A, Imax=4.963A, Iocp=8.51A
Delta I=((19-1.05)*(1.05/19))/(1.5u*261K)=2.53A
=>1/2DeltaI=1.265A
Vtrip=Rtrip*10uA=14K*10uA=0.14V
Iocpmin=Vtrip/(Rdsonmax*1.2)+1.265
=0.14/(0.0165*1.2)+1.265=8.34A
Iocpmax=(0.14/(0.0135*1.2))+1.265A=9.91A
Iocp=8.34A~9.91A
A

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

+1.05VSP
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
1

36

of

39

+1.8V

PJ14
JUMP_43X79

VIN

GND

VCNTL

NC

+3VALW

VREF

NC

VOUT

NC

TP

PC100
1U_0603_6.3V6M

PR118
1K_0402_1%

PC99
4.7U_0805_6.3V6K

PU8

+0.9VSP
1

PR120
1K_0402_1%
S
2N7002W -T/R7_SOT323-3

PC103
0.1U_0402_16V7K

PC101
0.1U_0402_16V7K
2
1

PQ27
2
G

PR119
0_0402_5%
1
2
1

<29> SUSP

APL5336KAI-TRL SOP

Ipeak=1A, Imax=0.7A

PC104
10U_0805_6.3V6M

PU11
IN

OUT

+2.5VSP
1

+3VS

APL5508-25DC-TRL_SOT89-3
1

PC106
@ PR123
4.7U_0805_6.3V6K 150_1206_5%

Ipeak=0.14A, Imax=0.098A

l.c
om

PC102
1U_0402_6.3V6K

GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

in

2008/09/20

+0.9VSP/+2.5VSP
Size Document Number
Custom
Date:

xa

Deciphered Date

he

2007/09/20

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
1

37

of

39

PR107
124K_0402_1%
2
1
PR112
1_0603_5%
2

Imax=2.1A
Iocp=5A

PMON

PC117
100P_0402_50V8J

25

CSP

V5IN

PM_DPRSLPVR

22

<6,17>

PQ25
AO4466_SO8

VGATE <12,17,25>

21

2
1

PGOOD

0_0402_5%
1

DPRSLP

CSN

PR116
2

VR_ON

27

26
PWRMON

TONSEL

28

29

30
ISLEW

31
V5FILT

32

GND

23

PL9
HCB2012KF-121T50_0805
1
2

B+

PC132
4700P_0402_25V7K

470_0402_1%
2

CLKEN#

24

0_0402_5%
1

PC110
4.7U_0805_25V6-K

PR121
1

+CPU_B+

PR113
10K_0402_1%
@ PR142
2

PC113
4.7U_0805_25V6-K
2
1

CSP

PR129
100_0402_1%
1
2

33P_0402_50V8K
2

VREF

<25>

PC133
0.1U_0603_25V7K
1
2

2
PC108

33
TP

TRIPSEL

470_0402_1%
2

VR_ON

OSRSEL

PR117
CSN
1

PU10

DROOP

PC97 33P_0402_50V8K
1
2

2
PR115
7.87K_0402_1%

VREF_CPU

PC109
0.22U_0603_10V7K
1
2

+3VS

5
6
7
8

PC96
27P_0402_50V8J
1
2

Ipeak=3A

PR111
@ 0_0402_5%

PR133
0_0402_5%

1
PR114
0_0402_5%

VREF_CPU

PC98
1U_0603_10V6K

+5VS

TPS51610RHB_QFN32_5X5

<5> VCCSENSE

GNDSNS

DRVL

20

LGATE_CPU

19

PHASE_CPU

18

BOOT_CPU

UGATE_CPU

PR130
0_0603_5%

PL10
2.2U_FDV0630-2R2M-P3_7.2A_20%
1
2

17

PC112
0.22U_0603_10V7K

PQ26
AO4712_SO8

PR131
100K_0402_1%
PR126
6.8_1206_5%

1
4

1
2

1
PR128
68_0402_5%
1

+5VS

PR125
43.2K_0402_1%
1
2

PC111
680P_0603_50V8J

1
2
PR127
24.9K_0402_1%

2
1
CSP

PC114
4.7U_0603_6.3V6K

PC115
6800P_0402_25V7K

CSN

PR135 1
2 0_0402_5%
<4,16> H_DPRSTP#
PR140 1
2 0_0402_5%
<5> CPU_VID6
PR136 1
2 0_0402_5%
<5> CPU_VID5
PR137 1
2 0_0402_5%
<5> CPU_VID4
PR138 1
2 0_0402_5%
<5> CPU_VID3
PR139 1
2 0_0402_5%
<5> CPU_VID2
PR143 1
2 0_0402_5%
<5> CPU_VID1
PR141 1
2 0_0402_5%
<5> CPU_VID0

PH5
150K +-5% ERTJ1VV154J 0603

3
2
1

+1.05VSP

+CPU_CORE

1
2

VID0

DRVH

16

VID1
15

VID3

VID2
14

VID4

VR_TT#

VID5

8
PH4
150K +-5% ERTJ1VV154J 0603

H_PROCHOT#

13

<4> H_PROCHOT#

12

PR132
10K_0402_1%

VID6

VBST

11

THERM

10

5
6
7
8

DPRSTP#

2
PR134
100_0402_1%

LL

+CPU_CORE

VSNS

3
2
1

<5> VSSSENSE

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

+CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
C
Date:

Document Number

Rev
1.0

KAV10 LA-4781P
Tuesday, December 30, 2008

Sheet

38
H

of

39

Version change list (P.I.R. List)


Item
D

Page 1 of 2
for PWR

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Date

Phase

Modify CPU_CORE VR_TT# circuit

circuit error

0.1

38

Cahnge PR128 to SD028680A80 (S RES 1/16W 68 +-5% 0402)

08/10/27 DVT

Diode modify

BOM error

0.1

31

Cahnge PD3 to SC4LZ43B0T4 ( S ZEN DIO RLZ4.3B (LL-34) )

08/10/27 DVT

Diode modify

BOM error

0.1

31

Cahnge PD4 to SC11N414880 ( S DIO RLS4148 LL34 )

08/10/27 DVT

Diode modify

BOM error

0.1

31

Cahnge PD5 to SC11N414880 ( S DIO RLS4148 LL34 )

08/10/27 DVT

Diode modify

BOM error

0.1

32

Cahnge PD6 to SC11N414880 ( S DIO RLS4148 LL34 )

08/10/27 DVT

Add 3/5V,charger,1.8/1.5V snubber

Add CPU snubber

Add CPU_CORE input capacitance

For ESD solution

0.1

33

Add PR36 PR39 PR57 PR147 PR148 to SD001470B80 (S RES 1/4W 4.7 +-5% 1206)

08/10/27 DVT

Add PC33 PC34 PC40 PC122 PC95 to SE074681K80 (S CER CAP 680P 50V K X7R 0402)

For ESD solution

0.1

33

Add PR126 to SD011680B80 (S RES 1/4W 6.8 +-5% 1206)

08/10/27 DVT

Add PC111 to SE024681J80 (S CER CAP 680P 50V J NPO 0603)

For ESD solution

0.1

38

Add PC133 SE042104K80 (S CER CAP .1U 25V K X7R 0603)

08/10/27 DVT

Add PC132 SE074222K80 (S CER CAP 2200P 50V K X7R 0402)

Add CPU_CORE input capacitance

For ESD solution

0.1

31

Add PC123 PC124 PC126 PC127 PC128 PC129 PC130 to SE076104K80 (S CER CAP .1U 16V K X7R 0402)

08/10/27 DVT

Add PC125 to SE072104K80 (S CER CAP 0.1U 25V K Y5V 0402)

10

Modify 1.05V LMOS

cost down

0.1

31

change PQ30 to SB00000AJ00 (S TR AO4712 1N SO8)

08/10/27 DVT

11

Modify 1.05V choke

cost down

0.1

31

change PL11 to SH00000FQ00 (S COIL 1.2UH +-30% 1164AY-1R2N=P3 10.1A)

08/10/27 DVT

12

Modify charger input capacitance size

0.1

31

change PC42 PC43 to SE142475K80 (S CER CAP 4.7U 25V K X5R 1206 H1.6)

08/10/29 DVT

13

Modify charger VADJ circuit

circuit error

14

Modify DIODE BOM (remove ROHN)

BOM error

15

Modify ACIN circuit

EVT issue solution

0.1

31

change PR4 SD02800008 to SD034100380(100K)

08/11/13 DVT

16

Modify 3/5V circuit

Modify 5V voltage for HW request

0.1

33

BOM error

17

Modify 1.8Vcircuit

Modify 1.8V voltage for HW request

0.1

35

18

Modify 1.05V circuit

add snubber for SED 3G solution

0.1

36

19

Modify 1.05V circuit

add boost for 1.05v issue

0.1

36

change PR43 to SD034976180 (S RES 1/16W 9.76K +-1% 0402)


add PR41 SD034619280(S RES 1/16W 61.9K +-1% 0402)
change PR223 to SD034750280 (S RES 1/16W 75K +-1% 0402)

08/12/26 PVT
08/12/26 PVT

change PR225 to SD034150380 S RES 1/16W 150K +-1% 0402)


add PC88 SE025681K80 (S CER CAP 680P 50V K X7R 0603)

08/12/26 PVT

add PR106 SD001470B80 (S RES 1/4W 4.7 +-5% 1206)

08/12/26 PVT

change PR109 to SD013220B80 (S RES 1/10W 2.2 +-5% 0603)

20
21

l.c
om

22
A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR (PWR)
Size Document Number
Custom
Date:

in

2008/09/20

Rev
1.0

xa

Deciphered Date

KAV10 LA-4781P

Tuesday, December 30, 2008

he

2007/09/20

f@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

ho

tm

ai

23

Sheet
1

39

of

39

A-TEST Change

Pre PVT-TEST Change

PVT-TEST Change

<10/21>
1.Remove C389 for Audio can't detect issue on page 16
2.Add KSO1/KSO2 PU +3VALW on page25
3.Add R205 for schematic mistake on page 04
4.Change EC RST to PLTRST on page 25
5.Add J8 to cost down Audio LDO on page 20
6.Add R72 to reserve +3VALW for 3G on page 19
7.Reserve C238 for CRTDAC on page 10
8.Add R87 for Debug card on page 19
9.Change C108/C255 to 0.1uF for random hang issue
10.Change JP3 pin assignment on page 28
<10/21>
1. Update Power SCH
<10/29>
1. Audio AMP 10dB update to 6dB
<11/3>
1. Update Power SCH
<11/4>
1. Change R373 R374 to 56.2 ohm for DA-HP FSOV
2. Add C834 C851 for 3G noise
3. Change KB926 C1 to D2
4. Card reader RT5158E change to RT5159-GR
<11/5>
1. Swap D7 pin define
<11/10>
1. EC add R79 R90 R92 for SMS wakeup

<8/25>
1. Update Power SCH
<8/26>
1. Update Power SCH
2. Change
D7 SC300000D00 to SC300000O00
3.Change
C49 C50 SE071180K80 to SE071180J80
<8/27>
1. Updata Power SCH
2. Modify
RJ45 temp footprint FOX_JM3611A-R4122-7F_12P-T
<8/28>
1. Updata Power SCH
<9/1>
1. Updata Screw
<9/5>
1. SWAP USB20_1 Signal.
<9/10>
1. Remove Mini card pin55 pin56
GND
2. Change JREAD1.42 H26 to GNDA
<9/12>
1. Swap 3G ESD pin neme
<9/15>
1. Update Audio Jack footprint
2. Chcnge R641 R642 300ohm to 511ohm for Arthros
3. Update L footprint
<9/16>
1. Update POWER SCH.
<9/17>
1. Update POWER SCH.
2. ADD R380 R383 for ESD.
<9/18>
1. Update ATHEROS 10/100 LAN <AR8132/AR8114>
<9/24>
1. Change C870 0.1u to 1u.
<9/26>
1. R88 change to 0ohm.

<11/28>
1. Reserve C40 C46 C47 C233
2. R617 change to 0ohm for RTS5159
3. R68 200K change to 100K for sequence
4. Remove C47
5. Add D30 for LVDS
6. Add C55 0.1U
7. U2 Change to SA000017B00
-because RT9715 Can't protect

<12/30>
1. Update power MP SCH

2006/08/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/8/18

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR-HW
Size Document Number
Custom
Date:

Rev
1.0

KAV10 LA-4781P

Tuesday, December 30, 2008

Sheet
1

40

of

40